From 1c41f87d67183db22edece9e8fdeb1c06a975917 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Tue, 24 Feb 2026 04:15:26 -0500 Subject: [PATCH] Verilog format --- test_regress/t/t_always_chg_first.v | 115 ++++++------ test_regress/t/t_always_combdly.v | 96 +++++----- test_regress/t/t_always_dly.v | 99 +++++----- test_regress/t/t_always_ff_never.v | 44 ++--- test_regress/t/t_always_nosplit.v | 246 ++++++++++++------------ test_regress/t/t_always_reorder.v | 77 ++++---- test_regress/t/t_always_split.v | 147 ++++++++------- test_regress/t/t_always_split_cond.v | 84 ++++----- test_regress/t/t_always_split_rst.v | 241 ++++++++++++------------ test_regress/t/t_always_splitord.v | 270 ++++++++++++++------------- 10 files changed, 711 insertions(+), 708 deletions(-) diff --git a/test_regress/t/t_always_chg_first.v b/test_regress/t/t_always_chg_first.v index 022f0a884..017b516d0 100644 --- a/test_regress/t/t_always_chg_first.v +++ b/test_regress/t/t_always_chg_first.v @@ -4,69 +4,74 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk, fastclk - ); +module t ( + input clk, + input fastclk +); - input clk; - input fastclk; // surefire lint_off_line UDDIXN + integer _mode; + initial _mode = 0; - integer _mode; initial _mode=0; + reg [31:0] ord1; + initial ord1 = 32'h1111; + wire [31:0] ord2; + reg [31:0] ord3; + wire [31:0] ord4; + wire [31:0] ord5; + wire [31:0] ord6; + wire [31:0] ord7; - reg [31:0] ord1; initial ord1 = 32'h1111; - wire [31:0] ord2; - reg [31:0] ord3; - wire [31:0] ord4; - wire [31:0] ord5; - wire [31:0] ord6; - wire [31:0] ord7; + // verilator lint_off UNOPT + t_chg_a a ( + .a(ord1), + .a_p1(ord2), + .b(ord4), + .b_p1(ord5), + .c(ord3), + .c_p1(ord4), + .d(ord6), + .d_p1(ord7) + ); - // verilator lint_off UNOPT - t_chg_a a ( - .a(ord1), .a_p1(ord2), - .b(ord4), .b_p1(ord5), - .c(ord3), .c_p1(ord4), - .d(ord6), .d_p1(ord7) - ); + // surefire lint_off ASWEMB + assign ord6 = ord5 + 1; + // verilator lint_on UNOPT - // surefire lint_off ASWEMB - assign ord6 = ord5 + 1; - // verilator lint_on UNOPT + always @( /*AS*/ord2) ord3 = ord2 + 1; - always @ (/*AS*/ord2) ord3 = ord2 + 1; + always @(fastclk) begin // surefire lint_off_line ALWLTR ALWMTR + if (_mode == 1) begin + //$write("[%0t] t_chg: %d: Values: %x %x %x %x %x %x %x\n", $time,fastclk,ord1,ord2,ord3,ord4,ord5,ord6,ord7); + //if (ord2 == 2 && ord7 != 7) $stop; + end + end - always @ (fastclk) begin // surefire lint_off_line ALWLTR ALWMTR - if (_mode==1) begin - //$write("[%0t] t_chg: %d: Values: %x %x %x %x %x %x %x\n", $time,fastclk,ord1,ord2,ord3,ord4,ord5,ord6,ord7); - //if (ord2 == 2 && ord7 != 7) $stop; - end - end - - always @ (posedge clk) begin - if (_mode==0) begin - $write("[%0t] t_chg: Running\n", $time); - _mode<=1; - ord1 <= 1; - end - else if (_mode==1) begin - _mode<=2; - if (ord7 !== 7) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + if (_mode == 0) begin + $write("[%0t] t_chg: Running\n", $time); + _mode <= 1; + ord1 <= 1; + end + else if (_mode == 1) begin + _mode <= 2; + if (ord7 !== 7) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module t_chg_a (/*AUTOARG*/ - // Outputs - a_p1, b_p1, c_p1, d_p1, - // Inputs - a, b, c, d - ); - input [31:0] a; output [31:0] a_p1; wire [31:0] a_p1 = a + 1; - input [31:0] b; output [31:0] b_p1; wire [31:0] b_p1 = b + 1; - input [31:0] c; output [31:0] c_p1; wire [31:0] c_p1 = c + 1; - input [31:0] d; output [31:0] d_p1; wire [31:0] d_p1 = d + 1; +module t_chg_a ( /*AUTOARG*/ + // Outputs + a_p1, b_p1, c_p1, d_p1, + // Inputs + a, b, c, d + ); + // verilog_format: off + input [31:0] a; output [31:0] a_p1; wire [31:0] a_p1 = a + 1; + input [31:0] b; output [31:0] b_p1; wire [31:0] b_p1 = b + 1; + input [31:0] c; output [31:0] c_p1; wire [31:0] c_p1 = c + 1; + input [31:0] d; output [31:0] d_p1; wire [31:0] d_p1 = d + 1; + // verilog_format: on endmodule diff --git a/test_regress/t/t_always_combdly.v b/test_regress/t/t_always_combdly.v index a76872ac3..8e8cfb4cb 100644 --- a/test_regress/t/t_always_combdly.v +++ b/test_regress/t/t_always_combdly.v @@ -4,58 +4,60 @@ // SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc; initial cyc=1; + integer cyc; + initial cyc = 1; - reg [31:0] a, b, c, d, e, f, g, h; + reg [31:0] a, b, c, d, e, f, g, h; - always @ (*) begin // Test Verilog 2001 (*) - // verilator lint_off COMBDLY - c <= a | b; - // verilator lint_on COMBDLY - end + always @(*) begin // Test Verilog 2001 (*) + // verilator lint_off COMBDLY + c <= a | b; + // verilator lint_on COMBDLY + end - always @ (posedge (clk)) begin // always bug 2008/4/18 - d <= a | b; - end - always @ ((d)) begin // always bug 2008/4/18 - e = d; - end + always @(posedge (clk)) begin // always bug 2008/4/18 + d <= a | b; + end + always @((d)) begin // always bug 2008/4/18 + e = d; + end - parameter CONSTANT = 1; - always @ (e, 1'b0, CONSTANT) begin // not technically legal, see bug412 - f = e; - end - always @ (1'b0, CONSTANT, f) begin // not technically legal, see bug412 - g = f; - end - always @ ({CONSTANT, g}) begin // bug745 - h = g; - end - //always @ ((posedge b) or (a or b)) begin // note both illegal + parameter CONSTANT = 1; + always @(e, 1'b0, CONSTANT) begin // not technically legal, see bug412 + f = e; + end + always @(1'b0, CONSTANT, f) begin // not technically legal, see bug412 + g = f; + end + always @({CONSTANT, + g + }) + begin // bug745 + h = g; + end + //always @ ((posedge b) or (a or b)) begin // note both illegal - always @ (posedge clk) begin - if (cyc!=0) begin - cyc<=cyc+1; - if (cyc==1) begin - a <= 32'hfeed0000; - b <= 32'h0000face; - end - if (cyc==2) begin - if (c != 32'hfeedface) $stop; - end - if (cyc==3) begin - if (h != 32'hfeedface) $stop; - end - if (cyc==7) begin - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + if (cyc == 1) begin + a <= 32'hfeed0000; + b <= 32'h0000face; end - end + if (cyc == 2) begin + if (c != 32'hfeedface) $stop; + end + if (cyc == 3) begin + if (h != 32'hfeedface) $stop; + end + if (cyc == 7) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule diff --git a/test_regress/t/t_always_dly.v b/test_regress/t/t_always_dly.v index f22a60ff9..a63120bc5 100644 --- a/test_regress/t/t_always_dly.v +++ b/test_regress/t/t_always_dly.v @@ -4,61 +4,60 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc; initial cyc=1; + integer cyc; + initial cyc = 1; - reg posedge_wr_clocks; - reg prev_wr_clocks; - reg [31:0] m_din; - reg [31:0] m_dout; + reg posedge_wr_clocks; + reg prev_wr_clocks; + reg [31:0] m_din; + reg [31:0] m_dout; - always @(negedge clk) begin - prev_wr_clocks = 0; - end + always @(negedge clk) begin + prev_wr_clocks = 0; + end - reg comb_pos_1; - reg comb_prev_1; - always @ (/*AS*/clk or posedge_wr_clocks or prev_wr_clocks) begin - comb_pos_1 = (clk &~ prev_wr_clocks); - comb_prev_1 = comb_pos_1 | posedge_wr_clocks; - comb_pos_1 = 1'b1; - end + reg comb_pos_1; + reg comb_prev_1; + always @( /*AS*/ clk or posedge_wr_clocks or prev_wr_clocks) begin + comb_pos_1 = (clk & ~prev_wr_clocks); + comb_prev_1 = comb_pos_1 | posedge_wr_clocks; + comb_pos_1 = 1'b1; + end - always @ (posedge clk) begin - posedge_wr_clocks = (clk &~ prev_wr_clocks); //surefire lint_off_line SEQASS - prev_wr_clocks = prev_wr_clocks | posedge_wr_clocks; //surefire lint_off_line SEQASS - if (posedge_wr_clocks) begin - //$write("[%0t] Wrclk\n", $time); - m_dout <= m_din; + always @(posedge clk) begin + posedge_wr_clocks = (clk & ~prev_wr_clocks); //surefire lint_off_line SEQASS + prev_wr_clocks = prev_wr_clocks | posedge_wr_clocks; //surefire lint_off_line SEQASS + if (posedge_wr_clocks) begin + //$write("[%0t] Wrclk\n", $time); + m_dout <= m_din; + end + end + + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + if (cyc == 1) begin + $write(" %x\n", comb_pos_1); + m_din <= 32'hfeed; end - end - - always @ (posedge clk) begin - if (cyc!=0) begin - cyc<=cyc+1; - if (cyc==1) begin - $write(" %x\n",comb_pos_1); - m_din <= 32'hfeed; - end - if (cyc==2) begin - $write(" %x\n",comb_pos_1); - m_din <= 32'he11e; - end - if (cyc==3) begin - m_din <= 32'he22e; - $write(" %x\n",comb_pos_1); - if (m_dout!=32'hfeed) $stop; - end - if (cyc==4) begin - if (m_dout!=32'he11e) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + if (cyc == 2) begin + $write(" %x\n", comb_pos_1); + m_din <= 32'he11e; end - end + if (cyc == 3) begin + m_din <= 32'he22e; + $write(" %x\n", comb_pos_1); + if (m_dout != 32'hfeed) $stop; + end + if (cyc == 4) begin + if (m_dout != 32'he11e) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule diff --git a/test_regress/t/t_always_ff_never.v b/test_regress/t/t_always_ff_never.v index 8c0d8024a..1acf09d06 100644 --- a/test_regress/t/t_always_ff_never.v +++ b/test_regress/t/t_always_ff_never.v @@ -4,37 +4,39 @@ // SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -interface intf - (input wire clk /*verilator public*/ ); +interface intf ( + input wire clk /*verilator public*/ +); endinterface module sub ( input wire clk, input wire dat ); - intf the_intf (.clk); + intf the_intf (.clk); - logic [63:0] last_transition = 123; - always_ff @(edge dat) begin - last_transition <= $time; - end + logic [63:0] last_transition = 123; + always_ff @(edge dat) begin + last_transition <= $time; + end - int cyc = 0; - always_ff @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 2) begin - if (last_transition != 123) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + int cyc = 0; + always_ff @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 2) begin + if (last_transition != 123) $stop; + $write("*-* All Finished *-*\n"); + $finish; end + end endmodule -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - sub the_sub (.clk, .dat ('0)); + sub the_sub ( + .clk, + .dat('0) + ); endmodule diff --git a/test_regress/t/t_always_nosplit.v b/test_regress/t/t_always_nosplit.v index 42820e98a..467fad89e 100644 --- a/test_regress/t/t_always_nosplit.v +++ b/test_regress/t/t_always_nosplit.v @@ -4,142 +4,146 @@ // SPDX-FileCopyrightText: 2018 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc; initial cyc=1; + integer cyc; + initial cyc = 1; - reg [15:0] m_din; + reg [15:0] m_din; - // We expect none of these blocks to split. - // Blocks that can split should go in t_alw_split.v instead. + // We expect none of these blocks to split. + // Blocks that can split should go in t_alw_split.v instead. - reg [15:0] b_split_1, b_split_2; - always @ (/*AS*/m_din) begin - b_split_1 = m_din; - b_split_2 = b_split_1; - end + reg [15:0] b_split_1, b_split_2; + always @( /*AS*/ m_din) begin + b_split_1 = m_din; + b_split_2 = b_split_1; + end - reg [15:0] c_split_1, c_split_2; - always @ (/*AS*/m_din) begin - c_split_1 = m_din; - c_split_2 = c_split_1; - c_split_1 = ~m_din; - end + reg [15:0] c_split_1, c_split_2; + always @( /*AS*/ m_din) begin + c_split_1 = m_din; + c_split_2 = c_split_1; + c_split_1 = ~m_din; + end - always @ (posedge clk) begin - $write(" foo %x", m_din); - $write(" bar %x\n", m_din); - end + always @(posedge clk) begin + $write(" foo %x", m_din); + $write(" bar %x\n", m_din); + end - reg [15:0] e_split_1, e_split_2; - always @ (posedge clk) begin - e_split_1 = m_din; - e_split_2 = e_split_1; - end + reg [15:0] e_split_1, e_split_2; + always @(posedge clk) begin + e_split_1 = m_din; + e_split_2 = e_split_1; + end - reg [15:0] f_split_1, f_split_2; - always @ (posedge clk) begin - f_split_2 = f_split_1; - f_split_1 = m_din; - end + reg [15:0] f_split_1, f_split_2; + always @(posedge clk) begin + f_split_2 = f_split_1; + f_split_1 = m_din; + end - function logic[15:0] sideeffect_func(logic [15:0] v); - /*verilator no_inline_task */ - $display(" sideeffect_func() is called %t", $time); - return ~v; - endfunction - reg [15:0] m_split_1 = 0; - reg [15:0] m_split_2 = 0; - always @(posedge clk) begin - if (sideeffect_func(m_split_1) != 16'b0) begin - m_split_1 <= m_din; - end else begin - m_split_2 <= m_din; - end + function logic [15:0] sideeffect_func(logic [15:0] v); + /*verilator no_inline_task */ + $display(" sideeffect_func() is called %t", $time); + return ~v; + endfunction + reg [15:0] m_split_1 = 0; + reg [15:0] m_split_2 = 0; + always @(posedge clk) begin + if (sideeffect_func(m_split_1) != 16'b0) begin + m_split_1 <= m_din; + end + else begin + m_split_2 <= m_din; + end end - reg [15:0] z_split_1, z_split_2; - always @ (posedge clk) begin - z_split_1 <= 0; - z_split_1 <= ~m_din; - end - always @ (posedge clk) begin - z_split_2 <= 0; - z_split_2 <= z_split_1; - end + reg [15:0] z_split_1, z_split_2; + always @(posedge clk) begin + z_split_1 <= 0; + z_split_1 <= ~m_din; + end + always @(posedge clk) begin + z_split_2 <= 0; + z_split_2 <= z_split_1; + end - reg [15:0] h_split_1; - reg [15:0] h_split_2; - reg [15:0] h_foo; - always @ (posedge clk) begin -// $write(" cyc = %x m_din = %x\n", cyc, m_din); - h_foo = m_din; - if (cyc > 2) begin - // This conditional depends on non-primary-input foo. - // Its dependency on foo should not be pruned. As a result, - // the dependencies of h_split_1 and h_split_2 on this - // conditional will also not be pruned, making them all - // weakly connected such that they'll end up in the same graph - // and we can't split. - if (h_foo == 16'h0) begin - h_split_1 <= 16'h0; - h_split_2 <= 16'h0; - end - else begin - h_split_1 <= m_din; - h_split_2 <= ~m_din; - end + reg [15:0] h_split_1; + reg [15:0] h_split_2; + reg [15:0] h_foo; + always @(posedge clk) begin + // $write(" cyc = %x m_din = %x\n", cyc, m_din); + h_foo = m_din; + if (cyc > 2) begin + // This conditional depends on non-primary-input foo. + // Its dependency on foo should not be pruned. As a result, + // the dependencies of h_split_1 and h_split_2 on this + // conditional will also not be pruned, making them all + // weakly connected such that they'll end up in the same graph + // and we can't split. + if (h_foo == 16'h0) begin + h_split_1 <= 16'h0; + h_split_2 <= 16'h0; end else begin - h_split_1 <= 16'h0; - h_split_2 <= 16'h0; + h_split_1 <= m_din; + h_split_2 <= ~m_din; end - end // always @ (posedge clk) + end + else begin + h_split_1 <= 16'h0; + h_split_2 <= 16'h0; + end + end // always @ (posedge clk) - always @ (posedge clk) begin - if (cyc!=0) begin - cyc<=cyc+1; - end - if (cyc==1) begin - m_din <= 16'hfeed; - end - if (cyc==4) begin - m_din <= 16'he11e; - if (!(b_split_1==16'hfeed && b_split_2==16'hfeed)) $stop; - if (!(c_split_1==16'h0112 && c_split_2==16'hfeed)) $stop; - if (!(e_split_1==16'hfeed && e_split_2==16'hfeed)) $stop; - if (!(f_split_1==16'hfeed && f_split_2==16'hfeed)) $stop; - if (!(m_split_1==16'hfeed && m_split_2==16'h0000)) $stop; - if (!(z_split_1==16'h0112 && z_split_2==16'h0112)) $stop; - end - if (cyc==5) begin - m_din <= 16'he22e; - if (!(b_split_1==16'he11e && b_split_2==16'he11e)) $stop; - if (!(c_split_1==16'h1ee1 && c_split_2==16'he11e)) $stop; - // Two valid orderings, as we don't know which posedge clk gets evaled first - if (!(e_split_1==16'hfeed && e_split_2==16'hfeed) && !(e_split_1==16'he11e && e_split_2==16'he11e)) $stop; - if (!(f_split_1==16'hfeed && f_split_2==16'hfeed) && !(f_split_1==16'he11e && f_split_2==16'hfeed)) $stop; - if (!(m_split_1==16'hfeed && m_split_2==16'h0000)) $stop; - if (!(z_split_1==16'h0112 && z_split_2==16'h0112)) $stop; - end - if (cyc==6) begin - m_din <= 16'he33e; - if (!(b_split_1==16'he22e && b_split_2==16'he22e)) $stop; - if (!(c_split_1==16'h1dd1 && c_split_2==16'he22e)) $stop; - // Two valid orderings, as we don't know which posedge clk gets evaled first - if (!(e_split_1==16'he11e && e_split_2==16'he11e) && !(e_split_1==16'he22e && e_split_2==16'he22e)) $stop; - if (!(f_split_1==16'he11e && f_split_2==16'hfeed) && !(f_split_1==16'he22e && f_split_2==16'he11e)) $stop; - if (!(m_split_1==16'he11e && m_split_2==16'h0000)) $stop; - if (!(z_split_1==16'h1ee1 && z_split_2==16'h0112)) $stop; - end - if (cyc==7) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + end + if (cyc == 1) begin + m_din <= 16'hfeed; + end + if (cyc == 4) begin + m_din <= 16'he11e; + if (!(b_split_1 == 16'hfeed && b_split_2 == 16'hfeed)) $stop; + if (!(c_split_1 == 16'h0112 && c_split_2 == 16'hfeed)) $stop; + if (!(e_split_1 == 16'hfeed && e_split_2 == 16'hfeed)) $stop; + if (!(f_split_1 == 16'hfeed && f_split_2 == 16'hfeed)) $stop; + if (!(m_split_1 == 16'hfeed && m_split_2 == 16'h0000)) $stop; + if (!(z_split_1 == 16'h0112 && z_split_2 == 16'h0112)) $stop; + end + if (cyc == 5) begin + m_din <= 16'he22e; + if (!(b_split_1 == 16'he11e && b_split_2 == 16'he11e)) $stop; + if (!(c_split_1 == 16'h1ee1 && c_split_2 == 16'he11e)) $stop; + // Two valid orderings, as we don't know which posedge clk gets evaled first + if (!(e_split_1==16'hfeed && e_split_2==16'hfeed) && !(e_split_1==16'he11e && e_split_2==16'he11e)) + $stop; + if (!(f_split_1==16'hfeed && f_split_2==16'hfeed) && !(f_split_1==16'he11e && f_split_2==16'hfeed)) + $stop; + if (!(m_split_1 == 16'hfeed && m_split_2 == 16'h0000)) $stop; + if (!(z_split_1 == 16'h0112 && z_split_2 == 16'h0112)) $stop; + end + if (cyc == 6) begin + m_din <= 16'he33e; + if (!(b_split_1 == 16'he22e && b_split_2 == 16'he22e)) $stop; + if (!(c_split_1 == 16'h1dd1 && c_split_2 == 16'he22e)) $stop; + // Two valid orderings, as we don't know which posedge clk gets evaled first + if (!(e_split_1==16'he11e && e_split_2==16'he11e) && !(e_split_1==16'he22e && e_split_2==16'he22e)) + $stop; + if (!(f_split_1==16'he11e && f_split_2==16'hfeed) && !(f_split_1==16'he22e && f_split_2==16'he11e)) + $stop; + if (!(m_split_1 == 16'he11e && m_split_2 == 16'h0000)) $stop; + if (!(z_split_1 == 16'h1ee1 && z_split_2 == 16'h0112)) $stop; + end + if (cyc == 7) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_always_reorder.v b/test_regress/t/t_always_reorder.v index 332d4fb2d..f5ca037b8 100644 --- a/test_regress/t/t_always_reorder.v +++ b/test_regress/t/t_always_reorder.v @@ -4,53 +4,52 @@ // SPDX-FileCopyrightText: 2018 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc; initial cyc=1; + integer cyc; + initial cyc = 1; - reg [15:0] m_din; + reg [15:0] m_din; - reg [15:0] v1; - reg [15:0] v2; - reg [15:0] v3; - integer nosplit; + reg [15:0] v1; + reg [15:0] v2; + reg [15:0] v3; + integer nosplit; - always @ (posedge clk) begin - // write needed so that V3Dead doesn't kill v0..v3 - $write(" values %x %x %x\n", v1, v2, v3); + always @(posedge clk) begin + // write needed so that V3Dead doesn't kill v0..v3 + $write(" values %x %x %x\n", v1, v2, v3); - // Locally-set 'nosplit' will prevent the if from splitting - // in splitAlwaysAll(). This whole always block should still be - // intact when we call splitReorderAll() which is the subject - // of this test. - nosplit = cyc; - if (nosplit > 2) begin - /* S1 */ v1 <= 16'h0; - /* S2 */ v1 <= m_din; - /* S3 */ if (m_din == 16'h0) begin - /* X1 */ v2 <= v1; - /* X2 */ v3 <= v2; - end + // Locally-set 'nosplit' will prevent the if from splitting + // in splitAlwaysAll(). This whole always block should still be + // intact when we call splitReorderAll() which is the subject + // of this test. + nosplit = cyc; + if (nosplit > 2) begin + /* S1 */ v1 <= 16'h0; + /* S2 */ v1 <= m_din; + /* S3 */ if (m_din == 16'h0) begin + /* X1 */ v2 <= v1; + /* X2 */ v3 <= v2; end + end - // We expect to swap S2 and S3, and to swap X1 and X2. - // We can check that this worked by the absense of dly vars - // in the generated output; if the reorder fails (or is disabled) - // we should see dly vars for v1 and v2. - end + // We expect to swap S2 and S3, and to swap X1 and X2. + // We can check that this worked by the absense of dly vars + // in the generated output; if the reorder fails (or is disabled) + // we should see dly vars for v1 and v2. + end - always @ (posedge clk) begin - if (cyc!=0) begin - cyc<=cyc+1; - if (cyc==7) begin - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + if (cyc == 7) begin + $write("*-* All Finished *-*\n"); + $finish; end - end + end + end endmodule diff --git a/test_regress/t/t_always_split.v b/test_regress/t/t_always_split.v index 4d0f0db26..057538c52 100644 --- a/test_regress/t/t_always_split.v +++ b/test_regress/t/t_always_split.v @@ -4,91 +4,90 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc; initial cyc=1; + integer cyc; + initial cyc = 1; - reg [15:0] m_din; + reg [15:0] m_din; - // We expect all these blocks should split; - // blocks that don't split should go in t_alw_nosplit.v + // We expect all these blocks should split; + // blocks that don't split should go in t_alw_nosplit.v - reg [15:0] a_split_1, a_split_2; - always @ (/*AS*/m_din) begin - a_split_1 = m_din; - a_split_2 = m_din; - end + reg [15:0] a_split_1, a_split_2; + always @( /*AS*/ m_din) begin + a_split_1 = m_din; + a_split_2 = m_din; + end - reg [15:0] d_split_1, d_split_2; - always @ (posedge clk) begin - d_split_1 <= m_din; - d_split_2 <= d_split_1; - d_split_1 <= ~m_din; - end + reg [15:0] d_split_1, d_split_2; + always @(posedge clk) begin + d_split_1 <= m_din; + d_split_2 <= d_split_1; + d_split_1 <= ~m_din; + end - reg [15:0] h_split_1; - reg [15:0] h_split_2; - always @ (posedge clk) begin -// $write(" cyc = %x m_din = %x\n", cyc, m_din); - if (cyc > 2) begin - if (m_din == 16'h0) begin - h_split_1 <= 16'h0; - h_split_2 <= 16'h0; - end - else begin - h_split_1 <= m_din; - h_split_2 <= ~m_din; - end + reg [15:0] h_split_1; + reg [15:0] h_split_2; + always @(posedge clk) begin + // $write(" cyc = %x m_din = %x\n", cyc, m_din); + if (cyc > 2) begin + if (m_din == 16'h0) begin + h_split_1 <= 16'h0; + h_split_2 <= 16'h0; end else begin - h_split_1 <= 16'h0; - h_split_2 <= 16'h0; + h_split_1 <= m_din; + h_split_2 <= ~m_din; end - end + end + else begin + h_split_1 <= 16'h0; + h_split_2 <= 16'h0; + end + end - reg [15:0] l_split_1, l_split_2; - always @ (posedge clk) begin - l_split_2 <= l_split_1; - l_split_1 <= l_split_2 | m_din; - end + reg [15:0] l_split_1, l_split_2; + always @(posedge clk) begin + l_split_2 <= l_split_1; + l_split_1 <= l_split_2 | m_din; + end - // (The checker block is an exception, it won't split.) - always @ (posedge clk) begin - if (cyc!=0) begin - cyc<=cyc+1; - if (cyc==1) begin - m_din <= 16'hfeed; - end - if (cyc==3) begin - end - if (cyc==4) begin - m_din <= 16'he11e; - //$write(" A %x %x\n", a_split_1, a_split_2); - if (!(a_split_1==16'hfeed && a_split_2==16'hfeed)) $stop; - if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop; - if (!(h_split_1==16'hfeed && h_split_2==16'h0112)) $stop; - end - if (cyc==5) begin - m_din <= 16'he22e; - if (!(a_split_1==16'he11e && a_split_2==16'he11e)) $stop; - if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop; - if (!(h_split_1==16'hfeed && h_split_2==16'h0112)) $stop; - end - if (cyc==6) begin - m_din <= 16'he33e; - if (!(a_split_1==16'he22e && a_split_2==16'he22e)) $stop; - if (!(d_split_1==16'h1ee1 && d_split_2==16'h0112)) $stop; - if (!(h_split_1==16'he11e && h_split_2==16'h1ee1)) $stop; - end - if (cyc==7) begin - $write("*-* All Finished *-*\n"); - $finish; - end + // (The checker block is an exception, it won't split.) + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + if (cyc == 1) begin + m_din <= 16'hfeed; end - end // always @ (posedge clk) + if (cyc == 3) begin + end + if (cyc == 4) begin + m_din <= 16'he11e; + //$write(" A %x %x\n", a_split_1, a_split_2); + if (!(a_split_1 == 16'hfeed && a_split_2 == 16'hfeed)) $stop; + if (!(d_split_1 == 16'h0112 && d_split_2 == 16'h0112)) $stop; + if (!(h_split_1 == 16'hfeed && h_split_2 == 16'h0112)) $stop; + end + if (cyc == 5) begin + m_din <= 16'he22e; + if (!(a_split_1 == 16'he11e && a_split_2 == 16'he11e)) $stop; + if (!(d_split_1 == 16'h0112 && d_split_2 == 16'h0112)) $stop; + if (!(h_split_1 == 16'hfeed && h_split_2 == 16'h0112)) $stop; + end + if (cyc == 6) begin + m_din <= 16'he33e; + if (!(a_split_1 == 16'he22e && a_split_2 == 16'he22e)) $stop; + if (!(d_split_1 == 16'h1ee1 && d_split_2 == 16'h0112)) $stop; + if (!(h_split_1 == 16'he11e && h_split_2 == 16'h1ee1)) $stop; + end + if (cyc == 7) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end // always @ (posedge clk) endmodule diff --git a/test_regress/t/t_always_split_cond.v b/test_regress/t/t_always_split_cond.v index b5cbdbc0d..fd714026b 100644 --- a/test_regress/t/t_always_split_cond.v +++ b/test_regress/t/t_always_split_cond.v @@ -5,60 +5,52 @@ // SPDX-License-Identifier: CC0-1.0 //bug1604 -module t (/*AUTOARG*/ - // Outputs - two, - // Inputs - clk, aresetn, ten - ); +module t ( /*AUTOARG*/ + // Outputs + two, + // Inputs + clk, + aresetn, + ten +); - input wire clk; - input wire aresetn; + input wire clk; + input wire aresetn; - input reg [9:0] ten; - output reg [1:0] two; + input reg [9:0] ten; + output reg [1:0] two; - // Passes with this - //output reg [1:0] rx; - //output reg [1:0] ry; + // Passes with this + //output reg [1:0] rx; + //output reg [1:0] ry; - function [1:0] func - ( - input [1:0] p0_x, - input [1:0] p0_y, - input [1:0] p1_x, - input [1:0] p1_y, - input [1:0] sel); + function [1:0] func(input [1:0] p0_x, input [1:0] p0_y, input [1:0] p1_x, input [1:0] p1_y, + input [1:0] sel); - reg [1:0] rx; - reg [1:0] ry; + reg [1:0] rx; + reg [1:0] ry; `ifdef NOT_DEF - // This way works - rx = sel == 2'b10 ? p1_x : p0_x; - ry = sel == 2'b10 ? p1_y : p0_y; + // This way works + rx = sel == 2'b10 ? p1_x : p0_x; + ry = sel == 2'b10 ? p1_y : p0_y; `else - // This way fails to compile - if (sel == 2'b10) begin - rx = p1_x; - ry = p1_y; - end - else begin - rx = p0_x; - ry = p0_y; - end + // This way fails to compile + if (sel == 2'b10) begin + rx = p1_x; + ry = p1_y; + end + else begin + rx = p0_x; + ry = p0_y; + end `endif - // Note rx and ry are unused - //func = rx | ry; // Also passes - func = 0; - endfunction + // Note rx and ry are unused + //func = rx | ry; // Also passes + func = 0; + endfunction - always @(*) begin - two = func( - ten[8 +: 2], - ten[6 +: 2], - ten[4 +: 2], - ten[2 +: 2], - ten[0 +: 2]); - end + always @(*) begin + two = func(ten[8+:2], ten[6+:2], ten[4+:2], ten[2+:2], ten[0+:2]); + end endmodule diff --git a/test_regress/t/t_always_split_rst.v b/test_regress/t/t_always_split_rst.v index ffe10eaa0..76af52866 100644 --- a/test_regress/t/t_always_split_rst.v +++ b/test_regress/t/t_always_split_rst.v @@ -5,155 +5,152 @@ // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [3:0] in = crc[3:0]; - wire clken = crc[4]; - wire rstn = !(cyc < 20 || (crc[11:8]==0)); + // Take CRC data and apply to testblock inputs + wire [3:0] in = crc[3:0]; + wire clken = crc[4]; + wire rstn = !(cyc < 20 || (crc[11:8] == 0)); - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [3:0] ff_out; // From test of Test.v - wire [3:0] fg_out; // From test of Test.v - wire [3:0] fh_out; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [3:0] ff_out; // From test of Test.v + wire [3:0] fg_out; // From test of Test.v + wire [3:0] fh_out; // From test of Test.v + // End of automatics - Test test (/*AUTOINST*/ - // Outputs - .ff_out (ff_out[3:0]), - .fg_out (fg_out[3:0]), - .fh_out (fh_out[3:0]), - // Inputs - .clk (clk), - .clken (clken), - .rstn (rstn), - .in (in[3:0])); + Test test ( /*AUTOINST*/ + // Outputs + .ff_out (ff_out[3:0]), + .fg_out (fg_out[3:0]), + .fh_out (fh_out[3:0]), + // Inputs + .clk (clk), + .clken (clken), + .rstn (rstn), + .in (in[3:0])); - // Aggregate outputs into a single result vector - wire [63:0] result = {52'h0, ff_out, fg_out, fh_out}; + // Aggregate outputs into a single result vector + wire [63:0] result = {52'h0, ff_out, fg_out, fh_out}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x rstn=%x\n", $time, cyc, crc, result, rstn); + $write("[%0t] cyc==%0d crc=%x result=%x rstn=%x\n", $time, cyc, crc, result, rstn); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc == 0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - end - else if (cyc < 10) begin - sum <= '0; - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'h77979747fd86e9fd - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc < 10) begin + sum <= '0; + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'h77979747fd86e9fd + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Test - (/*AUTOARG*/ +module Test ( /*AUTOARG*/ // Outputs ff_out, fg_out, fh_out, // Inputs clk, clken, rstn, in ); - input clk; - input clken; - input rstn; + input clk; + input clken; + input rstn; - input [3:0] in; + input [3:0] in; - output reg [3:0] ff_out; - reg [3:0] ff_10; - reg [3:0] ff_11; - reg [3:0] ff_12; - reg [3:0] ff_13; - always @(posedge clk) begin + output reg [3:0] ff_out; + reg [3:0] ff_10; + reg [3:0] ff_11; + reg [3:0] ff_12; + reg [3:0] ff_13; + always @(posedge clk) begin + if ((rstn == 0)) begin + ff_10 <= 0; + ff_11 <= 0; + ff_12 <= 0; + ff_13 <= 0; + ff_out <= 0; + end + else begin + ff_10 <= in; + ff_11 <= ff_10; + ff_12 <= ff_11; + ff_13 <= ff_12; + ff_out <= ff_13; + end + end + + output reg [3:0] fg_out; + reg [3:0] fg_10; + reg [3:0] fg_11; + reg [3:0] fg_12; + reg [3:0] fg_13; + always @(posedge clk) begin + if (clken) begin if ((rstn == 0)) begin - ff_10 <= 0; - ff_11 <= 0; - ff_12 <= 0; - ff_13 <= 0; - ff_out <= 0; + fg_10 <= 0; + fg_11 <= 0; + fg_12 <= 0; + fg_13 <= 0; + fg_out <= 0; end else begin - ff_10 <= in; - ff_11 <= ff_10; - ff_12 <= ff_11; - ff_13 <= ff_12; - ff_out <= ff_13; + fg_10 <= in; + fg_11 <= fg_10; + fg_12 <= fg_11; + fg_13 <= fg_12; + fg_out <= fg_13; end - end + end + end - output reg [3:0] fg_out; - reg [3:0] fg_10; - reg [3:0] fg_11; - reg [3:0] fg_12; - reg [3:0] fg_13; - always @(posedge clk) begin + output reg [3:0] fh_out; + reg [3:0] fh_10; + reg [3:0] fh_11; + reg [3:0] fh_12; + reg [3:0] fh_13; + always @(posedge clk) begin + if ((rstn == 0)) begin + fh_10 <= 0; + fh_11 <= 0; + fh_12 <= 0; + fh_13 <= 0; + fh_out <= 0; + end + else begin if (clken) begin - if ((rstn == 0)) begin - fg_10 <= 0; - fg_11 <= 0; - fg_12 <= 0; - fg_13 <= 0; - fg_out <= 0; - end - else begin - fg_10 <= in; - fg_11 <= fg_10; - fg_12 <= fg_11; - fg_13 <= fg_12; - fg_out <= fg_13; - end + fh_10 <= in; + fh_11 <= fh_10; + fh_12 <= fh_11; + fh_13[3:1] <= fh_12[3:1]; + fh_13[0] <= fh_12[0]; + fh_out <= fh_13; end - end - - output reg [3:0] fh_out; - reg [3:0] fh_10; - reg [3:0] fh_11; - reg [3:0] fh_12; - reg [3:0] fh_13; - always @(posedge clk) begin - if ((rstn == 0)) begin - fh_10 <= 0; - fh_11 <= 0; - fh_12 <= 0; - fh_13 <= 0; - fh_out <= 0; - end - else begin - if (clken) begin - fh_10 <= in; - fh_11 <= fh_10; - fh_12 <= fh_11; - fh_13[3:1] <= fh_12[3:1]; - fh_13[0] <= fh_12[0]; - fh_out <= fh_13; - end - end - end + end + end endmodule diff --git a/test_regress/t/t_always_splitord.v b/test_regress/t/t_always_splitord.v index cf7d87882..6730cb4c6 100644 --- a/test_regress/t/t_always_splitord.v +++ b/test_regress/t/t_always_splitord.v @@ -4,149 +4,153 @@ // SPDX-FileCopyrightText: 2003-2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc; initial cyc=1; + integer cyc; + initial cyc = 1; - reg [15:0] m_din; + reg [15:0] m_din; - // OK - reg [15:0] c_split_1, c_split_2, c_split_3, c_split_4, c_split_5; - always @ (posedge clk) begin - if (cyc==0) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - c_split_1 <= 16'h0; - c_split_2 <= 16'h0; - c_split_3 <= 16'h0; - c_split_4 <= 0; - c_split_5 <= 0; - // End of automatics + // OK + reg [15:0] c_split_1, c_split_2, c_split_3, c_split_4, c_split_5; + always @(posedge clk) begin + if (cyc == 0) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + c_split_1 <= 16'h0; + c_split_2 <= 16'h0; + c_split_3 <= 16'h0; + c_split_4 <= 0; + c_split_5 <= 0; + // End of automatics + end + else begin + c_split_1 <= m_din; + c_split_2 <= c_split_1; + c_split_3 <= c_split_2 & {16{(cyc != 0)}}; + if (cyc == 1) begin + c_split_4 <= 16'h4; + c_split_5 <= 16'h5; end else begin - c_split_1 <= m_din; - c_split_2 <= c_split_1; - c_split_3 <= c_split_2 & {16{(cyc!=0)}}; - if (cyc==1) begin - c_split_4 <= 16'h4; - c_split_5 <= 16'h5; - end - else begin - c_split_4 <= c_split_3; - c_split_5 <= c_split_4; - end + c_split_4 <= c_split_3; + c_split_5 <= c_split_4; end - end + end + end - // OK - reg [15:0] d_split_1, d_split_2; - always @ (posedge clk) begin - if (cyc==0) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - d_split_1 <= 16'h0; - d_split_2 <= 16'h0; - // End of automatics - end - else begin - d_split_1 <= m_din; - d_split_2 <= d_split_1; - d_split_1 <= ~m_din; - end - end + // OK + reg [15:0] d_split_1, d_split_2; + always @(posedge clk) begin + if (cyc == 0) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + d_split_1 <= 16'h0; + d_split_2 <= 16'h0; + // End of automatics + end + else begin + d_split_1 <= m_din; + d_split_2 <= d_split_1; + d_split_1 <= ~m_din; + end + end - // Not OK - always @ (posedge clk) begin - if (cyc==0) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - // End of automatics - end - else begin - $write(" foo %x", m_din); - $write(" bar %x\n", m_din); - end - end + // Not OK + always @(posedge clk) begin + if (cyc == 0) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + // End of automatics + end + else begin + $write(" foo %x", m_din); + $write(" bar %x\n", m_din); + end + end - // Not OK - reg [15:0] e_split_1, e_split_2; - always @ (posedge clk) begin - if (cyc==0) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - e_split_1 = 16'h0; - e_split_2 = 16'h0; - // End of automatics - end - else begin - e_split_1 = m_din; - e_split_2 = e_split_1; - end - end + // Not OK + reg [15:0] e_split_1, e_split_2; + always @(posedge clk) begin + if (cyc == 0) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + e_split_1 = 16'h0; + e_split_2 = 16'h0; + // End of automatics + end + else begin + e_split_1 = m_din; + e_split_2 = e_split_1; + end + end - // Not OK - reg [15:0] f_split_1, f_split_2; - always @ (posedge clk) begin - if (cyc==0) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - f_split_1 = 16'h0; - f_split_2 = 16'h0; - // End of automatics - end - else begin - f_split_2 = f_split_1; - f_split_1 = m_din; - end - end + // Not OK + reg [15:0] f_split_1, f_split_2; + always @(posedge clk) begin + if (cyc == 0) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + f_split_1 = 16'h0; + f_split_2 = 16'h0; + // End of automatics + end + else begin + f_split_2 = f_split_1; + f_split_1 = m_din; + end + end - always @ (posedge clk) begin - if (cyc!=0) begin - //$write(" C %d %x %x\n", cyc, c_split_1, c_split_2); - cyc<=cyc+1; - if (cyc==1) begin - m_din <= 16'hfeed; - end - if (cyc==3) begin - end - if (cyc==4) begin - m_din <= 16'he11e; - if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop; - if (!(e_split_1==16'hfeed && e_split_2==16'hfeed)) $stop; - if (!(f_split_1==16'hfeed && f_split_2==16'hfeed)) $stop; - end - if (cyc==5) begin - m_din <= 16'he22e; - if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop; - // Two valid orderings, as we don't know which posedge clk gets evaled first - if (!(e_split_1==16'hfeed && e_split_2==16'hfeed) && !(e_split_1==16'he11e && e_split_2==16'he11e)) $stop; - if (!(f_split_1==16'hfeed && f_split_2==16'hfeed) && !(f_split_1==16'he11e && f_split_2==16'hfeed)) $stop; - end - if (cyc==6) begin - m_din <= 16'he33e; - if (!(c_split_1==16'he11e && c_split_2==16'hfeed && c_split_3==16'hfeed)) $stop; - if (!(d_split_1==16'h1ee1 && d_split_2==16'h0112)) $stop; - // Two valid orderings, as we don't know which posedge clk gets evaled first - if (!(e_split_1==16'he11e && e_split_2==16'he11e) && !(e_split_1==16'he22e && e_split_2==16'he22e)) $stop; - if (!(f_split_1==16'he11e && f_split_2==16'hfeed) && !(f_split_1==16'he22e && f_split_2==16'he11e)) $stop; - end - if (cyc==7) begin - m_din <= 16'he44e; - if (!(c_split_1==16'he22e && c_split_2==16'he11e && c_split_3==16'hfeed)) $stop; - end - if (cyc==8) begin - m_din <= 16'he55e; - if (!(c_split_1==16'he33e && c_split_2==16'he22e && c_split_3==16'he11e - && c_split_4==16'hfeed && c_split_5==16'hfeed)) $stop; - end - if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + if (cyc != 0) begin + //$write(" C %d %x %x\n", cyc, c_split_1, c_split_2); + cyc <= cyc + 1; + if (cyc == 1) begin + m_din <= 16'hfeed; end - end + if (cyc == 3) begin + end + if (cyc == 4) begin + m_din <= 16'he11e; + if (!(d_split_1 == 16'h0112 && d_split_2 == 16'h0112)) $stop; + if (!(e_split_1 == 16'hfeed && e_split_2 == 16'hfeed)) $stop; + if (!(f_split_1 == 16'hfeed && f_split_2 == 16'hfeed)) $stop; + end + if (cyc == 5) begin + m_din <= 16'he22e; + if (!(d_split_1 == 16'h0112 && d_split_2 == 16'h0112)) $stop; + // Two valid orderings, as we don't know which posedge clk gets evaled first + if (!(e_split_1==16'hfeed && e_split_2==16'hfeed) && !(e_split_1==16'he11e && e_split_2==16'he11e)) + $stop; + if (!(f_split_1==16'hfeed && f_split_2==16'hfeed) && !(f_split_1==16'he11e && f_split_2==16'hfeed)) + $stop; + end + if (cyc == 6) begin + m_din <= 16'he33e; + if (!(c_split_1 == 16'he11e && c_split_2 == 16'hfeed && c_split_3 == 16'hfeed)) $stop; + if (!(d_split_1 == 16'h1ee1 && d_split_2 == 16'h0112)) $stop; + // Two valid orderings, as we don't know which posedge clk gets evaled first + if (!(e_split_1==16'he11e && e_split_2==16'he11e) && !(e_split_1==16'he22e && e_split_2==16'he22e)) + $stop; + if (!(f_split_1==16'he11e && f_split_2==16'hfeed) && !(f_split_1==16'he22e && f_split_2==16'he11e)) + $stop; + end + if (cyc == 7) begin + m_din <= 16'he44e; + if (!(c_split_1 == 16'he22e && c_split_2 == 16'he11e && c_split_3 == 16'hfeed)) $stop; + end + if (cyc == 8) begin + m_din <= 16'he55e; + if (!(c_split_1==16'he33e && c_split_2==16'he22e && c_split_3==16'he11e + && c_split_4==16'hfeed && c_split_5==16'hfeed)) + $stop; + end + if (cyc == 9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule