diff --git a/Changes b/Changes
index 6ea179dbb..e3473e6fc 100644
--- a/Changes
+++ b/Changes
@@ -9,6 +9,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ***   Fix vpi_iterate on memory words, bug655. [Rich Porter]
 
+****  Fix interface ports with comma lists, msg1058. [Ed Lander]
+
 
 * Verilator 3.850 2013-06-02
 
diff --git a/src/verilog.y b/src/verilog.y
index ad0ab2844..d99177f90 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -847,24 +847,18 @@ port<nodep>:			// ==IEEE: port
 	//			// IEEE: interface_port_header port_identifier { unpacked_dimension }
 	//			// Expanded interface_port_header
 	//			// We use instantCb here because the non-port form looks just like a module instantiation
-		portDirNetE id/*interface*/                      idAny/*port*/ variable_dimensionListE sigAttrListE
-			{ $$ = new AstPort($<fl>2,PINNUMINC(),*$3);
-			  AstVar* varp=new AstVar($<fl>2,AstVarType(AstVarType::IFACEREF),*$3,VFlagChildDType(),
-						  new AstIfaceRefDType($<fl>2,"",*$2));
-			  if ($4) varp->v3error("Unsupported: Arrayed interfaces");
-			  varp->addAttrsp($5);
-			  $$->addNext(varp); }
-	|	portDirNetE yINTERFACE                           idAny/*port*/ rangeListE sigAttrListE
-			{ $<fl>2->v3error("Unsupported: virtual interfaces"); }
-	|	portDirNetE id/*interface*/ '.' idAny/*modport*/ idAny/*port*/ rangeListE sigAttrListE
-			{ $$ = new AstPort($3,PINNUMINC(),*$5);
-			  AstVar* varp=new AstVar($<fl>2,AstVarType(AstVarType::IFACEREF),*$5,VFlagChildDType(),
-						  new AstIfaceRefDType($<fl>2,"",*$2,*$4));
-			  if ($6) varp->v3error("Unsupported: Arrayed interfaces");
-			  varp->addAttrsp($7);
-			  $$->addNext(varp); }
-	|	portDirNetE yINTERFACE      '.' idAny/*modport*/ idAny/*port*/ rangeListE sigAttrListE
-			{ $<fl>2->v3error("Unsupported: virtual interfaces"); }
+		portDirNetE id/*interface*/                      portSig variable_dimensionListE sigAttrListE
+			{ $$ = $3; VARDECL(AstVarType::IFACEREF); VARIO(UNKNOWN);
+			  VARDTYPE(new AstIfaceRefDType($<fl>2,"",*$2));
+			  $$->addNextNull(VARDONEP($$,$4,$5)); }
+	|	portDirNetE id/*interface*/ '.' idAny/*modport*/ portSig rangeListE sigAttrListE
+			{ $$ = $5; VARDECL(AstVarType::IFACEREF); VARIO(UNKNOWN);
+			  VARDTYPE(new AstIfaceRefDType($<fl>2,"",*$2,*$4));
+			  $$->addNextNull(VARDONEP($$,$6,$7)); }
+	|	portDirNetE yINTERFACE                           portSig rangeListE sigAttrListE
+			{ $<fl>2->v3error("Unsupported: virtual interfaces"); $$=NULL; }
+	|	portDirNetE yINTERFACE      '.' idAny/*modport*/ portSig rangeListE sigAttrListE
+			{ $<fl>2->v3error("Unsupported: virtual interfaces"); $$=NULL; }
 	//
 	//			// IEEE: ansi_port_declaration, with [port_direction] removed
 	//			//   IEEE: [ net_port_header | interface_port_header ] port_identifier { unpacked_dimension } [ '=' constant_expression ]
@@ -902,7 +896,7 @@ port<nodep>:			// ==IEEE: port
 	//UNSUP	portDirNetE /*implicit*/       '.' portSig '(' portAssignExprE ')' sigAttrListE
 	//UNSUP		{ UNSUP }
 	//
-	|	portDirNetE data_type          portSig variable_dimensionListE sigAttrListE
+	|	portDirNetE data_type           portSig variable_dimensionListE sigAttrListE
 			{ $$=$3; VARDTYPE($2); $$->addNextNull(VARDONEP($$,$4,$5)); }
 	|	portDirNetE yVAR data_type      portSig variable_dimensionListE sigAttrListE
 			{ $$=$4; VARDTYPE($3); $$->addNextNull(VARDONEP($$,$5,$6)); }
@@ -3636,6 +3630,9 @@ AstVar* V3ParseGrammar::createVariable(FileLine* fileline, string name, AstRange
 	return NULL;
     }
     AstVarType type = GRAMMARP->m_varIO;
+    if (dtypep->castIfaceRefDType()) {
+	if (arrayp) { fileline->v3error("Unsupported: Arrayed interfaces"); arrayp=NULL; }
+    }
     if (!dtypep) {  // Created implicitly
 	dtypep = new AstBasicDType(fileline, LOGIC_IMPLICIT);
     } else {  // May make new variables with same type, so clone
diff --git a/test_regress/t/t_interface_twod.pl b/test_regress/t/t_interface_twod.pl
new file mode 100755
index 000000000..1118f2e0e
--- /dev/null
+++ b/test_regress/t/t_interface_twod.pl
@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_interface_twod.v b/test_regress/t/t_interface_twod.v
new file mode 100644
index 000000000..4fe47a6c0
--- /dev/null
+++ b/test_regress/t/t_interface_twod.v
@@ -0,0 +1,47 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2013 by Wilson Snyder.
+
+interface ifc;
+   integer value;
+   modport i (output value);
+   modport o (input value);
+endinterface
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+   integer cyc=1;
+
+   ifc itop1a(),
+       itop1b();
+
+   wrapper  c1 (.isuba(itop1a),
+		.isubb(itop1b),
+		.i_valuea(14),
+		.i_valueb(15));
+
+   always @ (posedge clk) begin
+      cyc <= cyc + 1;
+      if (cyc==20) begin
+	 if (itop1a.value != 14) $stop;
+	 if (itop1b.value != 15) $stop;
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+      end
+   end
+endmodule
+
+module wrapper
+  (
+   ifc.i isuba, isubb,
+   input integer i_valuea, i_valueb
+   );
+   always @* begin
+      isuba.value = i_valuea;
+      isubb.value = i_valueb;
+   end
+endmodule