diff --git a/test_regress/t/t_interface_array2.py b/test_regress/t/t_interface_array2.py
index d4f986441..d30a25fe8 100755
--- a/test_regress/t/t_interface_array2.py
+++ b/test_regress/t/t_interface_array2.py
@@ -11,7 +11,7 @@ import vltest_bootstrap
 
 test.scenarios('simulator')
 
-test.compile()
+test.compile(timing_loop=True, v_flags2=["--timing"])
 
 test.execute()
 
diff --git a/test_regress/t/t_interface_array2.v b/test_regress/t/t_interface_array2.v
index ced787689..db5433194 100644
--- a/test_regress/t/t_interface_array2.v
+++ b/test_regress/t/t_interface_array2.v
@@ -54,12 +54,14 @@ module t
         genvar j;
         for (j = 0;j < N-1; j++) begin
             initial begin
+               #1;
                if (ifs[j].logic_in_intf != data[j]) $stop;
             end
         end
     endgenerate
 
     initial begin
+       #1;
        if (ifs[5].logic_in_intf != ~ifs[4].logic_in_intf) $stop;
        $write("*-* All Finished *-*\n");
        $finish;
diff --git a/test_regress/t/t_interface_array2_coverage.py b/test_regress/t/t_interface_array2_coverage.py
index 4b8df9ff0..c0c4569f2 100755
--- a/test_regress/t/t_interface_array2_coverage.py
+++ b/test_regress/t/t_interface_array2_coverage.py
@@ -12,7 +12,7 @@ import vltest_bootstrap
 test.scenarios('simulator')
 test.top_filename = "t/t_interface_array2.v"
 
-test.compile(v_flags2=["--coverage"])
+test.compile(timing_loop=True, v_flags2=["--coverage --timing"])
 
 test.execute()
 
diff --git a/test_regress/t/t_interface_array2_noinl.py b/test_regress/t/t_interface_array2_noinl.py
index 2c6d02725..4e3a93da0 100755
--- a/test_regress/t/t_interface_array2_noinl.py
+++ b/test_regress/t/t_interface_array2_noinl.py
@@ -12,7 +12,7 @@ import vltest_bootstrap
 test.scenarios('simulator')
 test.top_filename = "t/t_interface_array2.v"
 
-test.compile(v_flags2=["-fno-inline"])
+test.compile(timing_loop=True, v_flags2=["-fno-inline --timing"])
 
 test.execute()