From 199b32709c4fdc4b910bae38103eb92518692d94 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Tue, 30 Oct 2007 22:58:47 +0000
Subject: [PATCH] Fix div by zero in constant propagation

git-svn-id: file://localhost/svn/verilator/trunk/verilator@962 77ca24e4-aefa-0310-84f0-b9a241c72d87
---
 Changes                     | 4 ++++
 src/V3Number.cpp            | 4 ++++
 test_regress/t/t_math_div.v | 2 ++
 3 files changed, 10 insertions(+)

diff --git a/Changes b/Changes
index d80e79f1c..4b8df470d 100644
--- a/Changes
+++ b/Changes
@@ -3,6 +3,10 @@ Revision history for Verilator
 The contributors that suggested a given feature are shown in [].  [by ...]
 indicates the contributor was also the author of the fix; Thanks!
 
+* Verilator 3.65****
+
+**** Fix divide-by-zero errors in constant propagator.  [Rodney Sinclair]
+
 * Verilator 3.654 10/18/2007
 
 **** Don't exit early if many warnings but no errors are found. [Stan Mayer]
diff --git a/src/V3Number.cpp b/src/V3Number.cpp
index 78939f185..8ea96c406 100644
--- a/src/V3Number.cpp
+++ b/src/V3Number.cpp
@@ -1007,6 +1007,7 @@ V3Number& V3Number::opMulS (const V3Number& lhs, const V3Number& rhs) {
 V3Number& V3Number::opDiv (const V3Number& lhs, const V3Number& rhs) {
     // i op j, max(L(lhs),L(rhs)) bit return, if any 4-state, 4-state return
     if (lhs.isFourState() || rhs.isFourState()) return setAllBitsX();
+    if (rhs.isEqZero()) return setAllBitsX();
     if (lhs.width()>64) m_fileline->v3fatalSrc("Unsupported: Large / math not implemented yet: "<<*this);
     if (rhs.width()>64) m_fileline->v3fatalSrc("Unsupported: Large / math not implemented yet: "<<*this);
     setQuad(lhs.asQuad() / rhs.asQuad());
@@ -1015,6 +1016,7 @@ V3Number& V3Number::opDiv (const V3Number& lhs, const V3Number& rhs) {
 V3Number& V3Number::opDivS (const V3Number& lhs, const V3Number& rhs) {
     // Signed divide
     if (lhs.isFourState() || rhs.isFourState()) return setAllBitsX();
+    if (rhs.isEqZero()) return setAllBitsX();
     V3Number lhsNoSign = lhs;  if (lhs.isNegative()) lhsNoSign.opUnaryMin(lhs);
     V3Number rhsNoSign = rhs;  if (rhs.isNegative()) rhsNoSign.opUnaryMin(rhs);
     V3Number qNoSign = opDiv(lhsNoSign,rhsNoSign);
@@ -1029,6 +1031,7 @@ V3Number& V3Number::opDivS (const V3Number& lhs, const V3Number& rhs) {
 V3Number& V3Number::opModDiv (const V3Number& lhs, const V3Number& rhs) {
     // i op j, max(L(lhs),L(rhs)) bit return, if any 4-state, 4-state return
     if (lhs.isFourState() || rhs.isFourState()) return setAllBitsX();
+    if (rhs.isEqZero()) return setAllBitsX();
     if (lhs.width()>64) m_fileline->v3fatalSrc("Unsupported: Large % math not implemented yet: "<<*this);
     if (rhs.width()>64) m_fileline->v3fatalSrc("Unsupported: Large % math not implemented yet: "<<*this);
     setQuad(lhs.asQuad() % rhs.asQuad());
@@ -1037,6 +1040,7 @@ V3Number& V3Number::opModDiv (const V3Number& lhs, const V3Number& rhs) {
 V3Number& V3Number::opModDivS (const V3Number& lhs, const V3Number& rhs) {
     // Signed moddiv
     if (lhs.isFourState() || rhs.isFourState()) return setAllBitsX();
+    if (rhs.isEqZero()) return setAllBitsX();
     V3Number lhsNoSign = lhs;  if (lhs.isNegative()) lhsNoSign.opUnaryMin(lhs);
     V3Number rhsNoSign = rhs;  if (rhs.isNegative()) rhsNoSign.opUnaryMin(rhs);
     V3Number qNoSign = opModDiv(lhsNoSign,rhsNoSign);
diff --git a/test_regress/t/t_math_div.v b/test_regress/t/t_math_div.v
index d34d87902..6ecac51b6 100644
--- a/test_regress/t/t_math_div.v
+++ b/test_regress/t/t_math_div.v
@@ -85,6 +85,8 @@ module t (/*AUTOARG*/
 	    if (qq !== {61{1'bx}}) $stop;
 	    if (rq !== {61{1'bx}}) $stop;
 `endif
+	    if ({16{1'bx}} !== 16'd1/16'd0) $stop;  // No div by zero errors
+	    if ({16{1'bx}} !== 16'd1%16'd0) $stop;  // No div by zero errors
 	 end
 	 if (cyc==19) begin
 	    $write("*-* All Finished *-*\n");