From 19880520ea838c79f60b06d51ec0045f075eb2e0 Mon Sep 17 00:00:00 2001 From: em2machine Date: Sun, 21 Dec 2025 19:32:01 +0100 Subject: [PATCH] multidriven iface variant tests --- test_regress/t/t_multidriven_iface0.py | 18 +++++++ test_regress/t/t_multidriven_iface0.v | 68 ++++++++++++++++++++++++ test_regress/t/t_multidriven_iface1.py | 18 +++++++ test_regress/t/t_multidriven_iface1.v | 68 ++++++++++++++++++++++++ test_regress/t/t_multidriven_iface2.py | 18 +++++++ test_regress/t/t_multidriven_iface2.v | 69 ++++++++++++++++++++++++ test_regress/t/t_multidriven_iface3.py | 18 +++++++ test_regress/t/t_multidriven_iface3.v | 73 ++++++++++++++++++++++++++ test_regress/t/t_multidriven_iface4.py | 18 +++++++ test_regress/t/t_multidriven_iface4.v | 69 ++++++++++++++++++++++++ test_regress/t/t_multidriven_simple1.v | 2 + 11 files changed, 439 insertions(+) create mode 100755 test_regress/t/t_multidriven_iface0.py create mode 100644 test_regress/t/t_multidriven_iface0.v create mode 100755 test_regress/t/t_multidriven_iface1.py create mode 100644 test_regress/t/t_multidriven_iface1.v create mode 100755 test_regress/t/t_multidriven_iface2.py create mode 100644 test_regress/t/t_multidriven_iface2.v create mode 100755 test_regress/t/t_multidriven_iface3.py create mode 100644 test_regress/t/t_multidriven_iface3.v create mode 100755 test_regress/t/t_multidriven_iface4.py create mode 100644 test_regress/t/t_multidriven_iface4.v diff --git a/test_regress/t/t_multidriven_iface0.py b/test_regress/t/t_multidriven_iface0.py new file mode 100755 index 000000000..c6e56559a --- /dev/null +++ b/test_regress/t/t_multidriven_iface0.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2025 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_multidriven_iface0.v b/test_regress/t/t_multidriven_iface0.v new file mode 100644 index 000000000..e54160162 --- /dev/null +++ b/test_regress/t/t_multidriven_iface0.v @@ -0,0 +1,68 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty. +// SPDX-License-Identifier: CC0-1.0 + +// multidriven interface test - direct assignment to interface signal and task assign in same process + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +interface my_if; + logic l0; + + task set_l0_1(); l0 = 1'b1; endtask + task set_l0_0(); l0 = 1'b0; endtask +endinterface + +module mod #()( + input logic sel + ,output logic val +); + + my_if if0(); + + always_comb begin + if0.l0 = 1'b0; + + if(sel) begin + if0.set_l0_1(); + end + end + + assign val = if0.l0; + +endmodule + +module m_tb#()(); + + logic sel, val; + + mod m( + .sel(sel) + ,.val(val) + ); + + initial begin + #1; + sel = 'b0; + `checkd(val, 1'b0); + #1; + sel = 'b1; + `checkd(val, 1'b1); + #1; + sel = 'b0; + `checkd(val, 1'b0); + #1; + end + + initial begin + #5; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_multidriven_iface1.py b/test_regress/t/t_multidriven_iface1.py new file mode 100755 index 000000000..c6e56559a --- /dev/null +++ b/test_regress/t/t_multidriven_iface1.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2025 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_multidriven_iface1.v b/test_regress/t/t_multidriven_iface1.v new file mode 100644 index 000000000..7ff3bd263 --- /dev/null +++ b/test_regress/t/t_multidriven_iface1.v @@ -0,0 +1,68 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty. +// SPDX-License-Identifier: CC0-1.0 + +// interface task chain - nested task calls write interface signal in same always_comb + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +interface my_if; + logic l0; + + task set_l0_1_inner(); l0 = 1'b1; endtask + task set_l0_1_outer(); set_l0_1_inner(); endtask +endinterface + +module mod #()( + input logic sel + ,output logic val +); + + my_if if0(); + + always_comb begin + if0.l0 = 1'b0; + + if (sel) begin + if0.set_l0_1_outer(); + end + end + + assign val = if0.l0; + +endmodule + +module m_tb#()(); + + logic sel, val; + + mod m( + .sel(sel) + ,.val(val) + ); + + initial begin + #1; + sel = 'b0; + `checkd(val, 1'b0); + #1; + sel = 'b1; + `checkd(val, 1'b1); + #1; + sel = 'b0; + `checkd(val, 1'b0); + #1; + end + + initial begin + #5; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_multidriven_iface2.py b/test_regress/t/t_multidriven_iface2.py new file mode 100755 index 000000000..c6e56559a --- /dev/null +++ b/test_regress/t/t_multidriven_iface2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2025 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_multidriven_iface2.v b/test_regress/t/t_multidriven_iface2.v new file mode 100644 index 000000000..c0dd55c33 --- /dev/null +++ b/test_regress/t/t_multidriven_iface2.v @@ -0,0 +1,69 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty. +// SPDX-License-Identifier: CC0-1.0 + +// interface passed through module port - direct assign + task call in same always_comb + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +interface my_if; + logic l0; + + task set_l0_1(); l0 = 1'b1; endtask + task set_l0_0(); l0 = 1'b0; endtask +endinterface + +module mod #()( + input logic sel + ,output logic val + ,my_if ifp +); + + always_comb begin + ifp.l0 = 1'b0; + + if (sel) begin + ifp.set_l0_1(); + end + end + + assign val = ifp.l0; + +endmodule + +module m_tb#()(); + + logic sel, val; + my_if if0(); + + mod m( + .sel(sel) + ,.val(val) + ,.ifp(if0) + ); + + initial begin + #1; + sel = 'b0; + `checkd(val, 1'b0); + #1; + sel = 'b1; + `checkd(val, 1'b1); + #1; + sel = 'b0; + `checkd(val, 1'b0); + #1; + end + + initial begin + #5; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_multidriven_iface3.py b/test_regress/t/t_multidriven_iface3.py new file mode 100755 index 000000000..c6e56559a --- /dev/null +++ b/test_regress/t/t_multidriven_iface3.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2025 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_multidriven_iface3.v b/test_regress/t/t_multidriven_iface3.v new file mode 100644 index 000000000..597ab6ed9 --- /dev/null +++ b/test_regress/t/t_multidriven_iface3.v @@ -0,0 +1,73 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty. +// SPDX-License-Identifier: CC0-1.0 + +// interface modport + task import - write interface signal in same always_comb + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +interface my_if; + logic l0; + + task set_l0_1(); l0 = 1'b1; endtask + + modport mp ( + output l0, + import set_l0_1 + ); +endinterface + +module mod #()( + input logic sel + ,output logic val + ,my_if.mp ifp +); + + always_comb begin + ifp.l0 = 1'b0; + + if (sel) begin + ifp.set_l0_1(); + end + end + + assign val = ifp.l0; + +endmodule + +module m_tb#()(); + + logic sel, val; + my_if if0(); + + mod m( + .sel(sel) + ,.val(val) + ,.ifp(if0) + ); + + initial begin + #1; + sel = 'b0; + `checkd(val, 1'b0); + #1; + sel = 'b1; + `checkd(val, 1'b1); + #1; + sel = 'b0; + `checkd(val, 1'b0); + #1; + end + + initial begin + #5; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_multidriven_iface4.py b/test_regress/t/t_multidriven_iface4.py new file mode 100755 index 000000000..c6e56559a --- /dev/null +++ b/test_regress/t/t_multidriven_iface4.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2025 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_multidriven_iface4.v b/test_regress/t/t_multidriven_iface4.v new file mode 100644 index 000000000..af9d93589 --- /dev/null +++ b/test_regress/t/t_multidriven_iface4.v @@ -0,0 +1,69 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty. +// SPDX-License-Identifier: CC0-1.0 + +// interface task writes through output formal - actual is interface member + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +interface my_if; + logic l0; + + task automatic set_any(output logic q); + q = 1'b1; + endtask +endinterface + +module mod #()( + input logic sel + ,output logic val +); + + my_if if0(); + + always_comb begin + if0.l0 = 1'b0; + + if (sel) begin + if0.set_any(if0.l0); + end + end + + assign val = if0.l0; + +endmodule + +module m_tb#()(); + + logic sel, val; + + mod m( + .sel(sel) + ,.val(val) + ); + + initial begin + #1; + sel = 'b0; + `checkd(val, 1'b0); + #1; + sel = 'b1; + `checkd(val, 1'b1); + #1; + sel = 'b0; + `checkd(val, 1'b0); + #1; + end + + initial begin + #5; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_multidriven_simple1.v b/test_regress/t/t_multidriven_simple1.v index d5ad1d890..ef5e9d164 100644 --- a/test_regress/t/t_multidriven_simple1.v +++ b/test_regress/t/t_multidriven_simple1.v @@ -4,6 +4,8 @@ // without warranty. // SPDX-License-Identifier: CC0-1.0 +// task chain - testing nested task calls + // verilog_format: off `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);