diff --git a/src/V3ProtectLib.cpp b/src/V3ProtectLib.cpp
index a13dea844..d21d33252 100644
--- a/src/V3ProtectLib.cpp
+++ b/src/V3ProtectLib.cpp
@@ -443,7 +443,7 @@ class ProtectVisitor final : public VNVisitor {
         if (m_hasClk) {
             const std::string pname = varp->prettyName();
             m_seqParamsp->add(pname);
-            m_clkSensp->add("posedge " + pname + " or negedge " + pname);
+            m_clkSensp->add(pname);
         }
         m_cSeqParamsp->add(varp->dpiArgType(true, false));
         m_cSeqClksp->add(cInputConnection(varp));
diff --git a/test_regress/t/t_lib_clk_vec.py b/test_regress/t/t_lib_clk_vec.py
new file mode 100755
index 000000000..24eea89ec
--- /dev/null
+++ b/test_regress/t/t_lib_clk_vec.py
@@ -0,0 +1,30 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt_all')
+
+lib_dir = test.obj_dir + "/sub"
+test.mkdir_ok(lib_dir)
+
+test.run(logfile=lib_dir + "/verilator.log",
+         cmd=[
+             "perl", os.environ["VERILATOR_ROOT"] + "/bin/verilator", "-cc", "-Mdir", lib_dir,
+             "--lib-create", "sub", "--prefix", "Vsub", "+define+LIB_CREATE", test.top_filename
+         ],
+         verilator_run=True)
+
+test.run(logfile=lib_dir + "/make.log", cmd=[os.environ["MAKE"], "-C", lib_dir, "-f", "Vsub.mk"])
+
+test.compile(verilator_flags2=["--binary", "-LDFLAGS", "sub/libsub.a", lib_dir + "/sub.sv"])
+
+test.execute(xsim_run_flags2=["--sv_lib", lib_dir + "/libsecret", "--dpi_absolute"])
+
+test.passes()
diff --git a/test_regress/t/t_lib_clk_vec.v b/test_regress/t/t_lib_clk_vec.v
new file mode 100644
index 000000000..ddc4ef3c0
--- /dev/null
+++ b/test_regress/t/t_lib_clk_vec.v
@@ -0,0 +1,68 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+// The number of clocks in the clock vector
+
+localparam int N = 5;
+
+`ifdef LIB_CREATE
+// This is built with --lib-create
+
+module sub(
+  input logic [N-1:0] clkvec,
+  output logic [7:0] cnt[N]
+);
+
+  for (genvar i = 0; i < N; ++i) begin : GEN
+    logic [7:0] counter = 8'd0;
+    always @(posedge clkvec[i]) counter <= counter + 8'd1;
+    assign cnt[i] = counter;
+  end
+
+endmodule
+
+`else
+// This is built as the top level
+
+module top;
+
+  logic [N-1:0] clkvec = N'(0);
+  logic [7:0] cnt [N];
+
+  // Generate clocks by rotation
+  always #5 clkvec = {clkvec[N-2:0], clkvec[N-1] | ~|clkvec};
+
+  sub sub_i(clkvec, cnt);
+
+  always @(clkvec) begin
+    #1;
+    $write("%10t %05b", $time, clkvec);
+    for (int i = N-1; i >= 0; --i) begin
+      $write(" cnt[%0d]=%02d", i, cnt[i]);
+    end
+    $write("\n");
+
+    // No counter should reach above 10
+    for (int i = 0; i < N; ++i) begin
+      if (cnt[i] > 10) $stop;
+    end
+
+    // Conclude when all counters reach 10
+    begin
+      static bit done = 1'b1;
+      for (int i = 0; i < N; ++i) begin
+        if (cnt[i] != 10) done = 1'b0;
+      end
+      if (done) begin
+        $write("*-* All Finished *-*\n");
+        $finish;
+      end
+    end
+  end
+
+endmodule
+
+`endif