From 16fc6e339248d75220cffdd4338a48d7c75857e9 Mon Sep 17 00:00:00 2001 From: Ryszard Rozak Date: Fri, 13 Feb 2026 10:17:20 +0100 Subject: [PATCH] Change copyright format Signed-off-by: Ryszard Rozak --- test_regress/t/t_force_unpacked_struct.py | 8 ++++---- test_regress/t/t_force_unpacked_struct.v | 4 ++-- test_regress/t/t_force_unpacked_unsup.v | 2 +- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/test_regress/t/t_force_unpacked_struct.py b/test_regress/t/t_force_unpacked_struct.py index d4f986441..8a938befd 100755 --- a/test_regress/t/t_force_unpacked_struct.py +++ b/test_regress/t/t_force_unpacked_struct.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_force_unpacked_struct.v b/test_regress/t/t_force_unpacked_struct.v index c956cd9c9..fb404a23f 100644 --- a/test_regress/t/t_force_unpacked_struct.v +++ b/test_regress/t/t_force_unpacked_struct.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2026 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_force_unpacked_unsup.v b/test_regress/t/t_force_unpacked_unsup.v index b3f0bc456..27562ed45 100644 --- a/test_regress/t/t_force_unpacked_unsup.v +++ b/test_regress/t/t_force_unpacked_unsup.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain -// SPDX-FileCopyrightText: 2025 Antmicro +// SPDX-FileCopyrightText: 2026 Antmicro // SPDX-License-Identifier: CC0-1.0 // verilog_format: off