From 15ad3f46be13cb2a24ea9e7089c497e4a0e52842 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Tue, 28 Apr 2020 21:15:20 -0400
Subject: [PATCH] Fix logical not optimization with empty begin, #2291.

---
 Changes                     |  2 ++
 src/V3Const.cpp             |  3 ++-
 test_regress/t/t_if_swap.pl | 17 +++++++++++++++++
 test_regress/t/t_if_swap.v  | 24 ++++++++++++++++++++++++
 4 files changed, 45 insertions(+), 1 deletion(-)
 create mode 100755 test_regress/t/t_if_swap.pl
 create mode 100644 test_regress/t/t_if_swap.v

diff --git a/Changes b/Changes
index d77e97f71..58c8272c2 100644
--- a/Changes
+++ b/Changes
@@ -38,6 +38,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ****  Fix error on unpacked connecting to packed, #2288. [Joseph Shaker]
 
+****  Fix logical not optimization with empty begin, #2291. [Baltazar Ortiz]
+
 
 * Verilator 4.032 2020-04-04
 
diff --git a/src/V3Const.cpp b/src/V3Const.cpp
index c36ae1f9d..7418df2fa 100644
--- a/src/V3Const.cpp
+++ b/src/V3Const.cpp
@@ -1954,7 +1954,8 @@ private:
                         || VN_IS(nodep->condp(), LogNot))
                        && nodep->ifsp() && nodep->elsesp()) {
                 UINFO(4, "IF(NOT {x})  => IF(x) swapped if/else" << nodep << endl);
-                AstNode* condp = VN_CAST(nodep->condp(), Not)->lhsp()->unlinkFrBackWithNext();
+                AstNode* condp
+                    = VN_CAST(nodep->condp(), NodeUniop)->lhsp()->unlinkFrBackWithNext();
                 AstNode* ifsp = nodep->ifsp()->unlinkFrBackWithNext();
                 AstNode* elsesp = nodep->elsesp()->unlinkFrBackWithNext();
                 AstIf* ifp = new AstIf(nodep->fileline(), condp, elsesp, ifsp);
diff --git a/test_regress/t/t_if_swap.pl b/test_regress/t/t_if_swap.pl
new file mode 100755
index 000000000..29a7fc65c
--- /dev/null
+++ b/test_regress/t/t_if_swap.pl
@@ -0,0 +1,17 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2019 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_if_swap.v b/test_regress/t/t_if_swap.v
new file mode 100644
index 000000000..d1e771433
--- /dev/null
+++ b/test_regress/t/t_if_swap.v
@@ -0,0 +1,24 @@
+module t
+  (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+   integer f;
+
+   always @(posedge clk) begin
+      if (!$feof(f)) begin
+         $display("Doing stuff with file.");
+      end
+      // Commenting out these two lines fixes the fault
+      else begin
+      end
+      if (!$feof(f)) begin
+      end
+      else begin
+         $display("Not doing stuff with file.");
+      end
+   end
+
+endmodule