From 15841fe5f663d3e45e2c020cf558e196727d7f1a Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Fri, 4 Apr 2008 18:29:33 +0000
Subject: [PATCH] Support functions with input

git-svn-id: file://localhost/svn/verilator/trunk/verilator@1021 77ca24e4-aefa-0310-84f0-b9a241c72d87
---
 Changes                       |  2 +
 src/verilog.y                 |  9 ++--
 test_regress/t/t_func_plog.pl | 18 +++++++
 test_regress/t/t_func_plog.v  | 97 +++++++++++++++++++++++++++++++++++
 4 files changed, 120 insertions(+), 6 deletions(-)
 create mode 100755 test_regress/t/t_func_plog.pl
 create mode 100644 test_regress/t/t_func_plog.v

diff --git a/Changes b/Changes
index 445ef1020..dde190844 100644
--- a/Changes
+++ b/Changes
@@ -16,6 +16,8 @@ indicates the contributor was also the author of the fix; Thanks!
      Previously they threw fatal errors, which in most cases is correct
      according to spec, but can be incorrect in presence of parameter values.
 
+**** Support functions with "input integer".  [Johan Wouters]
+
 **** Ignore delays attached to gate UDPs.  [Stefan Thiede]
 
 **** Fix SystemVerilog parameterized defines with `` expansion,
diff --git a/src/verilog.y b/src/verilog.y
index f995df9b8..1abb9a053 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -530,8 +530,8 @@ regsigList:	regsig  				{ $$ = $1; }
 	|	regsigList ',' regsig		       	{ $$ = $1;$1->addNext($3); }
 	;
 
-portV2kDecl:	varRESET varInput  v2kNetDeclE signingE regrangeE portV2kSig	{ $$ = $6; }
-	|	varRESET varInout  v2kNetDeclE signingE regrangeE portV2kSig	{ $$ = $6; }
+portV2kDecl:	varRESET varInput  v2kVarDeclE signingE regrangeE portV2kSig	{ $$ = $6; }
+	|	varRESET varInout  v2kVarDeclE signingE regrangeE portV2kSig	{ $$ = $6; }
 	|	varRESET varOutput v2kVarDeclE signingE regrangeE portV2kSig	{ $$ = $6; }
 	;
 
@@ -581,11 +581,8 @@ signingE:	/*empty*/ 				{ }
 	|	yUNSIGNED				{ VARSIGNED(false); }
 	;
 
-v2kNetDeclE:	/*empty*/ 				{ }
+v2kVarDeclE:	/*empty*/ 				{ }
 	|	varNet 					{ }
-	;
-
-v2kVarDeclE:	v2kNetDeclE 				{ }
 	|	varReg 					{ }
 	;
 
diff --git a/test_regress/t/t_func_plog.pl b/test_regress/t/t_func_plog.pl
new file mode 100755
index 000000000..7bfdbe852
--- /dev/null
+++ b/test_regress/t/t_func_plog.pl
@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_func_plog.v b/test_regress/t/t_func_plog.v
new file mode 100644
index 000000000..1975cdb92
--- /dev/null
+++ b/test_regress/t/t_func_plog.v
@@ -0,0 +1,97 @@
+// $Id$
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2003 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer 	cyc=0;
+   reg [63:0] 	crc;
+   reg [63:0] 	sum;
+   reg 		rst_n;
+
+   // Take CRC data and apply to testblock inputs
+
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire [2:0]		pos;			// From test of Test.v
+   // End of automatics
+
+   Test test (
+	      // Outputs
+	      .pos			(pos[2:0]),
+	      /*AUTOINST*/
+	      // Inputs
+	      .clk			(clk),
+	      .rst_n			(rst_n));
+
+   // Aggregate outputs into a single result vector
+   wire [63:0] result = {61'h0, pos};
+
+   // What checksum will we end up with
+`define EXPECTED_SUM 64'h039ea4d039c2e70b
+
+   // Test loop
+   always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
+      $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+`endif
+      cyc <= cyc + 1;
+      crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+      sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+      rst_n <= ~1'b0;
+      if (cyc==0) begin
+	 // Setup
+	 crc <= 64'h5aef0c8d_d70a4497;
+	 rst_n <= ~1'b1;
+      end
+      else if (cyc<10) begin
+	 sum <= 64'h0;
+	 rst_n <= ~1'b1;
+      end
+      else if (cyc<90) begin
+      end
+      else if (cyc==99) begin
+	 $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+	 if (crc !== 64'hc77bb9b3784ea091) $stop;
+	 if (sum !== `EXPECTED_SUM) $stop;
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+      end
+   end
+
+endmodule
+
+module Test
+  #(parameter SAMPLE_WIDTH = 4 )
+   (
+`ifdef verilator  // UNSUPPORTED
+    output reg [2:0]         pos,
+`else
+    output reg [log2(SAMPLE_WIDTH)-1:0]         pos,
+`endif
+    // System
+    input 	clk,
+    input 	rst_n
+    );
+
+   function integer log2(input integer arg);
+      begin
+	 for(log2=0; arg>0; log2=log2+1)
+	   arg = (arg >> 1);
+      end
+   endfunction
+
+   always @ (posedge clk or negedge  rst_n)
+     if (!rst_n) begin
+	pos   <= 0;
+     end
+     else begin
+	pos <= pos + 1;
+     end
+endmodule