diff --git a/test_regress/t/t_vpi_finish.pl b/test_regress/t/t_vpi_finish.pl
index 050052f66..77affd6a5 100755
--- a/test_regress/t/t_vpi_finish.pl
+++ b/test_regress/t/t_vpi_finish.pl
@@ -11,7 +11,8 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 scenarios(simulator => 1);
 
 compile(
-    v_flags2 => ["--vpi t/t_vpi_finish_c.cpp"],
+    v_flags2 => ["t/t_vpi_finish_c.cpp"],
+    verilator_flags2 => ["--vpi"],
     );
 
 execute(
diff --git a/test_regress/t/t_vpi_get.v b/test_regress/t/t_vpi_get.v
index de893386b..93191301c 100644
--- a/test_regress/t/t_vpi_get.v
+++ b/test_regress/t/t_vpi_get.v
@@ -9,7 +9,7 @@
 `ifdef USE_VPI_NOT_DPI
 //We call it via $c so we can verify DPI isn't required - see bug572
 `else
-import "DPI-C" context function integer mon_check();
+import "DPI-C" context function int mon_check();
 `endif
 
 `ifdef VERILATOR_COMMENTS
diff --git a/test_regress/t/t_vpi_memory.v b/test_regress/t/t_vpi_memory.v
index de2d2b4a7..c16a59cb5 100644
--- a/test_regress/t/t_vpi_memory.v
+++ b/test_regress/t/t_vpi_memory.v
@@ -9,7 +9,7 @@
 `ifdef USE_VPI_NOT_DPI
 //We call it via $c so we can verify DPI isn't required - see bug572
 `else
-import "DPI-C" context function integer mon_check();
+import "DPI-C" context function int mon_check();
 `endif
 
 module t (/*AUTOARG*/
diff --git a/test_regress/t/t_vpi_module.v b/test_regress/t/t_vpi_module.v
index e3490e5a4..3ef25ea4b 100644
--- a/test_regress/t/t_vpi_module.v
+++ b/test_regress/t/t_vpi_module.v
@@ -9,7 +9,7 @@
 `ifdef USE_VPI_NOT_DPI
 //We call it via $c so we can verify DPI isn't required - see bug572
 `else
-import "DPI-C" context function integer mon_check();
+import "DPI-C" context function int mon_check();
 `endif
 
 module t (/*AUTOARG*/
diff --git a/test_regress/t/t_vpi_param.v b/test_regress/t/t_vpi_param.v
index 082658ff6..4ae1dbb47 100644
--- a/test_regress/t/t_vpi_param.v
+++ b/test_regress/t/t_vpi_param.v
@@ -9,7 +9,7 @@
 `ifdef USE_VPI_NOT_DPI
 //We call it via $c so we can verify DPI isn't required - see bug572
 `else
-import "DPI-C" context function integer mon_check();
+import "DPI-C" context function int mon_check();
 `endif
 
 
diff --git a/test_regress/t/t_vpi_stop_bad.pl b/test_regress/t/t_vpi_stop_bad.pl
index 89f7e8b16..061b4561c 100755
--- a/test_regress/t/t_vpi_stop_bad.pl
+++ b/test_regress/t/t_vpi_stop_bad.pl
@@ -11,11 +11,12 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 scenarios(simulator => 1);
 
 compile(
-    v_flags2 => ["--vpi t/t_vpi_stop_bad_c.cpp"],
+    v_flags2 => ["t/t_vpi_stop_bad_c.cpp"],
+    verilator_flags2 => ["--vpi"],
     );
 
 execute(
-    fails => 1,
+    fails => $Self->{vlt_all},
     check_finished => 0,
     expect_filename => $Self->{golden_filename},
     );
diff --git a/test_regress/t/t_vpi_time_cb.v b/test_regress/t/t_vpi_time_cb.v
index a2410c7c5..846302d8a 100644
--- a/test_regress/t/t_vpi_time_cb.v
+++ b/test_regress/t/t_vpi_time_cb.v
@@ -17,101 +17,24 @@ module t (/*AUTOARG*/
    assign clk = clk_r;
 `endif
 
-   reg          onebit          /*verilator public_flat_rw @(posedge clk) */;
-   reg [2:1]    twoone          /*verilator public_flat_rw @(posedge clk) */;
-   reg [2:1]    fourthreetwoone[4:3] /*verilator public_flat_rw @(posedge clk) */;
-
-   reg [61:0]   quads[3:2]      /*verilator public_flat_rw @(posedge clk) */;
-
    reg [31:0]      count        /*verilator public_flat_rd */;
-   reg [31:0]      half_count   /*verilator public_flat_rd */;
-
-   reg [7:0]       text_byte    /*verilator public_flat_rw @(posedge clk) */;
-   reg [15:0]      text_half    /*verilator public_flat_rw @(posedge clk) */;
-   reg [31:0]      text_word    /*verilator public_flat_rw @(posedge clk) */;
-   reg [63:0]      text_long    /*verilator public_flat_rw @(posedge clk) */;
-   reg [511:0]     text         /*verilator public_flat_rw @(posedge clk) */;
 
    integer        status;
 
-   sub sub();
-
    // Test loop
    initial begin
       count = 0;
-      onebit = 1'b0;
-      fourthreetwoone[3] = 0; // stop icarus optimizing away
-      text_byte = "B";
-      text_half = "Hf";
-      text_word = "Word";
-      text_long = "Long64b";
-      text = "Verilog Test module";
-
-/*
-      if (status!=0) begin
-         $write("%%Error: t_vpi_var.cpp:%0d: C Test failed\n", status);
-         $stop;
-      end
-      $write("%%Info: Checking results\n");
-      if (onebit != 1'b1) $stop;
-      if (quads[2] != 62'h12819213_abd31a1c) $stop;
-      if (quads[3] != 62'h1c77bb9b_3784ea09) $stop;
-      if (text_byte != "A") $stop;
-      if (text_half != "T2") $stop;
-      if (text_word != "Tree") $stop;
-      if (text_long != "44Four44") $stop;
-      if (text != "lorem ipsum") $stop;
- */
    end
 
    always @(posedge clk) begin
+`ifdef TEST_VERBOSE
+      $display("[%0t] clk", $time);
+`endif
       count <= count + 2;
-      if (count[1])
-        half_count <= half_count + 2;
-
       if (count == 1000) begin
-//       $write("*-* All Finished *-*\n");
+         // See C++ code: $write("*-* All Finished *-*\n");
          $finish;
       end
    end
 
-   genvar i;
-   generate
-      for (i=1; i<=128; i=i+1) begin : arr
-         arr #(.LENGTH(i)) arr();
-      end
-   endgenerate
-
 endmodule : t
-
-module sub;
-   reg subsig1 /*verilator public_flat_rd*/;
-   reg subsig2 /*verilator public_flat_rd*/;
-`ifdef IVERILOG
-   // stop icarus optimizing signals away
-   wire redundant = subsig1 | subsig2;
-`endif
-endmodule : sub
-
-module arr;
-
-   parameter LENGTH = 1;
-
-   reg [LENGTH-1:0] sig /*verilator public_flat_rw*/;
-   reg [LENGTH-1:0] rfr /*verilator public_flat_rw*/;
-
-   reg            check /*verilator public_flat_rw*/;
-   reg          verbose /*verilator public_flat_rw*/;
-
-   initial begin
-      sig = {LENGTH{1'b0}};
-      rfr = {LENGTH{1'b0}};
-   end
-
-   always @(posedge check) begin
-      if (verbose) $display("%m : %x %x", sig, rfr);
-      if (check && sig != rfr) $stop;
-      check <= 0;
-   end
-
-endmodule : arr
diff --git a/test_regress/t/t_vpi_unimpl.v b/test_regress/t/t_vpi_unimpl.v
index 978303008..ffad82c75 100644
--- a/test_regress/t/t_vpi_unimpl.v
+++ b/test_regress/t/t_vpi_unimpl.v
@@ -9,7 +9,7 @@
 `ifdef VERILATOR
 //We call it via $c so we can verify DPI isn't required - see bug572
 `else
-import "DPI-C" context function integer mon_check();
+import "DPI-C" context function int mon_check();
 `endif
 
 module t (/*AUTOARG*/
diff --git a/test_regress/t/t_vpi_var.v b/test_regress/t/t_vpi_var.v
index 89160dc60..88c9612a6 100644
--- a/test_regress/t/t_vpi_var.v
+++ b/test_regress/t/t_vpi_var.v
@@ -9,7 +9,7 @@
 `ifdef USE_VPI_NOT_DPI
 //We call it via $c so we can verify DPI isn't required - see bug572
 `else
-import "DPI-C" context function integer mon_check();
+import "DPI-C" context function int mon_check();
 `endif
 
 module t (/*AUTOARG*/
diff --git a/test_regress/t/t_vpi_zero_time_cb.v b/test_regress/t/t_vpi_zero_time_cb.v
index f88aa8e8c..846302d8a 100644
--- a/test_regress/t/t_vpi_zero_time_cb.v
+++ b/test_regress/t/t_vpi_zero_time_cb.v
@@ -17,101 +17,24 @@ module t (/*AUTOARG*/
    assign clk = clk_r;
 `endif
 
-   reg          onebit          /*verilator public_flat_rw @(posedge clk) */;
-   reg [2:1]    twoone          /*verilator public_flat_rw @(posedge clk) */;
-   reg [2:1]    fourthreetwoone[4:3] /*verilator public_flat_rw @(posedge clk) */;
-
-   reg [61:0]   quads[3:2]      /*verilator public_flat_rw @(posedge clk) */;
-
    reg [31:0]      count        /*verilator public_flat_rd */;
-   reg [31:0]      half_count   /*verilator public_flat_rd */;
-
-   reg [7:0]       text_byte    /*verilator public_flat_rw @(posedge clk) */;
-   reg [15:0]      text_half    /*verilator public_flat_rw @(posedge clk) */;
-   reg [31:0]      text_word    /*verilator public_flat_rw @(posedge clk) */;
-   reg [63:0]      text_long    /*verilator public_flat_rw @(posedge clk) */;
-   reg [511:0]     text         /*verilator public_flat_rw @(posedge clk) */;
 
    integer        status;
 
-   sub sub();
-
    // Test loop
    initial begin
       count = 0;
-      onebit = 1'b0;
-      fourthreetwoone[3] = 0;  // stop icarus optimizing away
-      text_byte = "B";
-      text_half = "Hf";
-      text_word = "Word";
-      text_long = "Long64b";
-      text = "Verilog Test module";
-
-/*
-      if (status!=0) begin
-         $write("%%Error: t_vpi_var.cpp:%0d: C Test failed\n", status);
-         $stop;
-      end
-      $write("%%Info: Checking results\n");
-      if (onebit != 1'b1) $stop;
-      if (quads[2] != 62'h12819213_abd31a1c) $stop;
-      if (quads[3] != 62'h1c77bb9b_3784ea09) $stop;
-      if (text_byte != "A") $stop;
-      if (text_half != "T2") $stop;
-      if (text_word != "Tree") $stop;
-      if (text_long != "44Four44") $stop;
-      if (text != "lorem ipsum") $stop;
- */
    end
 
    always @(posedge clk) begin
+`ifdef TEST_VERBOSE
+      $display("[%0t] clk", $time);
+`endif
       count <= count + 2;
-      if (count[1])
-        half_count <= half_count + 2;
-
       if (count == 1000) begin
-//       $write("*-* All Finished *-*\n");
+         // See C++ code: $write("*-* All Finished *-*\n");
          $finish;
       end
    end
 
-   genvar i;
-   generate
-      for (i=1; i<=128; i=i+1) begin : arr
-         arr #(.LENGTH(i)) arr();
-      end
-   endgenerate
-
 endmodule : t
-
-module sub;
-   reg subsig1 /*verilator public_flat_rd*/;
-   reg subsig2 /*verilator public_flat_rd*/;
-`ifdef IVERILOG
-   // stop icarus optimizing signals away
-   wire redundant = subsig1 | subsig2;
-`endif
-endmodule : sub
-
-module arr;
-
-   parameter LENGTH = 1;
-
-   reg [LENGTH-1:0] sig /*verilator public_flat_rw*/;
-   reg [LENGTH-1:0] rfr /*verilator public_flat_rw*/;
-
-   reg            check /*verilator public_flat_rw*/;
-   reg          verbose /*verilator public_flat_rw*/;
-
-   initial begin
-      sig = {LENGTH{1'b0}};
-      rfr = {LENGTH{1'b0}};
-   end
-
-   always @(posedge check) begin
-      if (verbose) $display("%m : %x %x", sig, rfr);
-      if (check && sig != rfr) $stop;
-      check <= 0;
-   end
-
-endmodule : arr