From 140671300c28179f453e197bd6c41b5e34eb9cb9 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 7 Jun 2020 11:58:53 -0400 Subject: [PATCH] Internals: Pass parser celldefine state through FileLine. No functional change intended. --- src/V3Error.h | 7 +++++-- src/V3FileLine.h | 2 ++ src/V3ParseImp.h | 4 ---- src/verilog.l | 4 ++-- src/verilog.y | 4 ++-- 5 files changed, 11 insertions(+), 10 deletions(-) diff --git a/src/V3Error.h b/src/V3Error.h index f86d5888f..b44bab0bf 100644 --- a/src/V3Error.h +++ b/src/V3Error.h @@ -44,6 +44,7 @@ public: EC_FATALSRC, // Kill the program, for internal source errors EC_ERROR, // General error out, can't suppress // Boolean information we track per-line, but aren't errors + I_CELLDEFINE, // Inside cell define from `celldefine/`endcelldefine I_COVERAGE, // Coverage is on/off from /*verilator coverage_on/off*/ I_TRACING, // Tracing is on/off from /*verilator tracing_on/off*/ I_LINT, // All lint messages @@ -140,7 +141,7 @@ public: // Leading spaces indicate it can't be disabled. " MIN", " INFO", " FATAL", " FATALEXIT", " FATALSRC", " ERROR", // Boolean - " I_COVERAGE", " I_TRACING", " I_LINT", " I_DEF_NETTYPE_WIRE", + " I_CELLDEFINE", " I_COVERAGE", " I_TRACING", " I_LINT", " I_DEF_NETTYPE_WIRE", // Errors "DETECTARRAY", "PORTSHORT", "TASKNSVAR", // Warnings @@ -170,7 +171,9 @@ public: return names[m_e]; } // Warnings that default to off - bool defaultsOff() const { return (m_e == IMPERFECTSCH || styleError()); } + bool defaultsOff() const { + return (m_e == IMPERFECTSCH || m_e == I_CELLDEFINE || styleError()); + } // Warnings that warn about nasty side effects bool dangerous() const { return (m_e == COMBDLY); } // Warnings we'll present to the user as errors diff --git a/src/V3FileLine.h b/src/V3FileLine.h index 579e3cb75..ef195d246 100644 --- a/src/V3FileLine.h +++ b/src/V3FileLine.h @@ -218,6 +218,8 @@ public: bool lastWarnWaived() { return m_waive; } // Specific flag ACCESSORS/METHODS + bool celldefineOn() const { return m_warnOn.test(V3ErrorCode::I_CELLDEFINE); } + void celldefineOn(bool flag) { warnOn(V3ErrorCode::I_CELLDEFINE, flag); } bool coverageOn() const { return m_warnOn.test(V3ErrorCode::I_COVERAGE); } void coverageOn(bool flag) { warnOn(V3ErrorCode::I_COVERAGE, flag); } bool tracingOn() const { return m_warnOn.test(V3ErrorCode::I_TRACING); } diff --git a/src/V3ParseImp.h b/src/V3ParseImp.h index 51e73b82e..46a66c382 100644 --- a/src/V3ParseImp.h +++ b/src/V3ParseImp.h @@ -107,7 +107,6 @@ class V3ParseImp { static V3ParseImp* s_parsep; // Current THIS, bison() isn't class based FileLine* m_fileline; // Filename/linenumber currently active - bool m_inCellDefine; // Inside a `celldefine bool m_inLibrary; // Currently reading a library vs. regular file int m_inBeginKwd; // Inside a `begin_keywords int m_lastVerilogState; // Last LEX state in `begin_keywords @@ -214,8 +213,6 @@ public: FileLine* fileline() const { return m_fileline; } AstNetlist* rootp() const { return m_rootp; } FileLine* copyOrSameFileLine() { return fileline()->copyOrSameFileLine(); } - bool inCellDefine() const { return m_inCellDefine; } - void inCellDefine(bool flag) { m_inCellDefine = flag; } bool inLibrary() const { return m_inLibrary; } VOptionBool unconnectedDrive() const { return m_unconnectedDrive; } void unconnectedDrive(const VOptionBool flag) { m_unconnectedDrive = flag; } @@ -244,7 +241,6 @@ public: , m_symp(parserSymp) { m_fileline = NULL; m_lexerp = NULL; - m_inCellDefine = false; m_inLibrary = false; m_inBeginKwd = 0; m_lastVerilogState = stateVerilogRecent(); diff --git a/src/verilog.l b/src/verilog.l index 1b1a93a3e..f2b25b9c4 100644 --- a/src/verilog.l +++ b/src/verilog.l @@ -929,7 +929,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} { "`accelerate" { FL_FWD; FL_BRK; } // Verilog-XL compatibility "`autoexpand_vectornets" { FL_FWD; FL_BRK; } // Verilog-XL compatibility - "`celldefine" { FL_FWD; PARSEP->inCellDefine(true); FL_BRK; } + "`celldefine" { FL_FWD; PARSEP->fileline()->celldefineOn(true); FL_BRK; } "`default_decay_time"{ws}+[^\n\r]* { FL_FWD; FL_BRK; } // Verilog spec - delays only "`default_nettype"{ws}+"wire" { FL_FWD; PARSEP->fileline()->warnOn(V3ErrorCode::I_DEF_NETTYPE_WIRE, true); FL_BRK; } "`default_nettype"{ws}+"none" { FL_FWD; PARSEP->fileline()->warnOn(V3ErrorCode::I_DEF_NETTYPE_WIRE, false); FL_BRK; } @@ -943,7 +943,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} "`delay_mode_zero" { FL_FWD; FL_BRK; } // Verilog spec - delays only "`disable_portfaults" { FL_FWD; FL_BRK; } // Verilog-XL compatibility "`enable_portfaults" { FL_FWD; FL_BRK; } // Verilog-XL compatibility - "`endcelldefine" { FL_FWD; PARSEP->inCellDefine(false); FL_BRK; } + "`endcelldefine" { FL_FWD; PARSEP->fileline()->celldefineOn(false); FL_BRK; } "`endprotect" { FL_FWD; FL_BRK; } "`expand_vectornets" { FL_FWD; FL_BRK; } // Verilog-XL compatibility "`inline" { FL_FWD; FL_BRK; } diff --git a/src/verilog.y b/src/verilog.y index df07fb93a..8773299ff 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -1170,7 +1170,7 @@ modFront: yMODULE lifetimeE idAny { $$ = new AstModule($3,*$3); $$->lifetime($2); - $$->inLibrary(PARSEP->inLibrary() || PARSEP->inCellDefine()); + $$->inLibrary(PARSEP->inLibrary() || $$->fileline()->celldefineOn()); $$->modTrace(GRAMMARP->allTracingOn($$->fileline())); $$->timeunit(PARSEP->timeLastUnit()); $$->unconnectedDrive(PARSEP->unconnectedDrive()); @@ -1463,7 +1463,7 @@ pgmFront: yPROGRAM lifetimeE idAny/*new_program*/ { $$ = new AstModule($3,*$3); $$->lifetime($2); - $$->inLibrary(PARSEP->inLibrary() || PARSEP->inCellDefine()); + $$->inLibrary(PARSEP->inLibrary() || $$->fileline()->celldefineOn()); $$->modTrace(GRAMMARP->allTracingOn($$->fileline())); $$->timeunit(PARSEP->timeLastUnit()); PARSEP->rootp()->addModulep($$);