diff --git a/test_regress/t/t_trace_lib.v b/test_regress/t/t_trace_lib.v
new file mode 100644
index 000000000..74bfb198c
--- /dev/null
+++ b/test_regress/t/t_trace_lib.v
@@ -0,0 +1,60 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain.
+// SPDX-FileCopyrightText: 2026 Wilson Snyder
+// SPDX-License-Identifier: CC0-1.0
+
+`ifdef TOP
+module t(
+   input clk
+);
+
+   logic [7:0] in0 = 8'd020;
+   logic [7:0] in1 = 8'd100;
+   wire [7:0] out0;
+   wire [7:0] out1;
+   int count = 0;
+
+   sub0 i_sub0(.clk(clk), .in(in0), .out(out0));
+   sub1 i_sub1(.clk(clk), .in(in1), .out(out1));
+
+   always_ff @(posedge clk) begin
+      count <= count + 1;
+      in0 <= in0 + 8'd1;
+      in1 <= in1 + 8'd2;
+      if (count == 3) begin
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+
+endmodule
+`endif
+
+`ifdef SUB0
+module sub0(
+   input wire clk,
+   input wire [7:0] in,
+   output wire [7:0] out
+);
+
+   logic [7:0] ff;
+   always_ff @(posedge clk) ff <= in + 8'd1;
+   assign out = ff;
+
+endmodule
+`endif
+
+`ifdef SUB1
+module sub1(
+   input wire clk,
+   input wire [7:0] in,
+   output wire [7:0] out
+);
+
+   logic [7:0] ff;
+   always_ff @(posedge clk) ff <= in + 8'd2;
+   assign out = ff;
+
+endmodule
+`endif
diff --git a/test_regress/t/t_trace_lib_default_fst.out b/test_regress/t/t_trace_lib_default_fst.out
new file mode 100644
index 000000000..c8d98349d
--- /dev/null
+++ b/test_regress/t/t_trace_lib_default_fst.out
@@ -0,0 +1,123 @@
+$date
+Sat Mar 21 21:35:43 2026
+
+$end
+$version
+Generated by VerilatedFst
+$end
+$timescale
+1ps
+$end
+ $scope module top $end
+  $var wire 1 ! clk $end
+  $scope module t $end
+   $var wire 1 ! clk $end
+   $var logic 8 " in0 [7:0] $end
+   $var logic 8 # in1 [7:0] $end
+   $var wire 8 $ out0 [7:0] $end
+   $var wire 8 % out1 [7:0] $end
+   $var int 32 & count [31:0] $end
+   $scope module i_sub0 $end
+    $var wire 1 ' clk $end
+    $var wire 8 ( in [7:0] $end
+    $var wire 8 ) out [7:0] $end
+    $var logic 8 * ff [7:0] $end
+   $upscope $end
+   $scope module i_sub1 $end
+    $var wire 1 + clk $end
+    $var wire 8 , in [7:0] $end
+    $var wire 8 - out [7:0] $end
+    $var logic 8 . ff [7:0] $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+b00000000 .
+b00000000 -
+b01100100 ,
+0+
+b00000000 *
+b00000000 )
+b00010100 (
+0'
+b00000000000000000000000000000000 &
+b00000000 %
+b00000000 $
+b01100100 #
+b00010100 "
+0!
+$end
+#10
+1!
+b00010101 "
+b01100110 #
+b00010101 $
+b01100110 %
+b00000000000000000000000000000001 &
+1'
+b00010101 (
+b00010101 )
+b00010101 *
+1+
+b01100110 ,
+b01100110 -
+b01100110 .
+#15
+0+
+0'
+0!
+#20
+1!
+1'
+1+
+b01101000 .
+b01101000 -
+b01101000 ,
+b00010110 *
+b00010110 )
+b00010110 (
+b00000000000000000000000000000010 &
+b01101000 %
+b00010110 $
+b01101000 #
+b00010110 "
+#25
+0+
+0'
+0!
+#30
+1!
+1'
+1+
+b00010111 "
+b01101010 #
+b00010111 $
+b01101010 %
+b00000000000000000000000000000011 &
+b00010111 (
+b00010111 )
+b00010111 *
+b01101010 ,
+b01101010 -
+b01101010 .
+#35
+0+
+0'
+0!
+#40
+1!
+1'
+1+
+b01101100 .
+b01101100 -
+b01101100 ,
+b00011000 *
+b00011000 )
+b00011000 (
+b00000000000000000000000000000100 &
+b01101100 %
+b00011000 $
+b01101100 #
+b00011000 "
diff --git a/test_regress/t/t_trace_lib_default_fst.py b/test_regress/t/t_trace_lib_default_fst.py
new file mode 100755
index 000000000..5d5e0a225
--- /dev/null
+++ b/test_regress/t/t_trace_lib_default_fst.py
@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_lib_common
+
+test.priority(10)
+test.scenarios('vlt_all')
+
+trace_lib_common.run(test)
diff --git a/test_regress/t/t_trace_lib_default_saif.out b/test_regress/t/t_trace_lib_default_saif.out
new file mode 100644
index 000000000..0b2fe9447
--- /dev/null
+++ b/test_regress/t/t_trace_lib_default_saif.out
@@ -0,0 +1,141 @@
+// Generated by verilated_saif
+(SAIFILE
+(SAIFVERSION "2.0")
+(DIRECTION "backward")
+(PROGRAM_NAME "Verilator")
+(DIVIDER / )
+(TIMESCALE 1ps)
+(DURATION 40)
+ (INSTANCE top
+  (NET
+   (clk (T0 25) (T1 15) (TZ 0) (TX 0) (TB 0) (TC 7))
+  )
+  (INSTANCE t
+   (NET
+    (clk (T0 25) (T1 15) (TZ 0) (TX 0) (TB 0) (TC 7))
+    (in0\[0\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 4))
+    (in0\[1\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2))
+    (in0\[2\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+    (in0\[3\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (in0\[4\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (in0\[5\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (in0\[6\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (in0\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (in1\[0\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (in1\[1\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 4))
+    (in1\[2\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3))
+    (in1\[3\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (in1\[4\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (in1\[5\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (in1\[6\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (in1\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (out0\[0\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 4))
+    (out0\[1\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2))
+    (out0\[2\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 2))
+    (out0\[3\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (out0\[4\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (out0\[5\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (out0\[6\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (out0\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (out1\[0\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (out1\[1\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 4))
+    (out1\[2\] (T0 30) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 3))
+    (out1\[3\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (out1\[4\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (out1\[5\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (out1\[6\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (out1\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (count\[0\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 4))
+    (count\[1\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2))
+    (count\[2\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (count\[3\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (count\[4\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (count\[5\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (count\[6\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (count\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (count\[8\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (count\[9\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (count\[10\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (count\[11\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (count\[12\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (count\[13\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (count\[14\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (count\[15\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (count\[16\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (count\[17\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (count\[18\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (count\[19\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (count\[20\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (count\[21\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (count\[22\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (count\[23\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (count\[24\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (count\[25\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (count\[26\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (count\[27\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (count\[28\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (count\[29\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (count\[30\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (count\[31\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   )
+   (INSTANCE i_sub0
+    (NET
+     (clk (T0 25) (T1 15) (TZ 0) (TX 0) (TB 0) (TC 7))
+     (in\[0\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 4))
+     (in\[1\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2))
+     (in\[2\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+     (in\[3\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (in\[4\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (in\[5\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (in\[6\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (in\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (out\[0\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 4))
+     (out\[1\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2))
+     (out\[2\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 2))
+     (out\[3\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (out\[4\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (out\[5\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (out\[6\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (out\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (ff\[0\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 4))
+     (ff\[1\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2))
+     (ff\[2\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 2))
+     (ff\[3\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (ff\[4\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (ff\[5\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (ff\[6\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (ff\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    )
+   )
+   (INSTANCE i_sub1
+    (NET
+     (clk (T0 25) (T1 15) (TZ 0) (TX 0) (TB 0) (TC 7))
+     (in\[0\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (in\[1\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 4))
+     (in\[2\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (in\[3\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (in\[4\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (in\[5\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (in\[6\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (in\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (out\[0\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (out\[1\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 4))
+     (out\[2\] (T0 30) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (out\[3\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (out\[4\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (out\[5\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (out\[6\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (out\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (ff\[0\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (ff\[1\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 4))
+     (ff\[2\] (T0 30) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (ff\[3\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (ff\[4\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (ff\[5\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (ff\[6\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (ff\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    )
+   )
+  )
+ )
+)
diff --git a/test_regress/t/t_trace_lib_default_saif.py b/test_regress/t/t_trace_lib_default_saif.py
new file mode 100755
index 000000000..5d5e0a225
--- /dev/null
+++ b/test_regress/t/t_trace_lib_default_saif.py
@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_lib_common
+
+test.priority(10)
+test.scenarios('vlt_all')
+
+trace_lib_common.run(test)
diff --git a/test_regress/t/t_trace_lib_default_vcd.out b/test_regress/t/t_trace_lib_default_vcd.out
new file mode 100644
index 000000000..1c6e991bd
--- /dev/null
+++ b/test_regress/t/t_trace_lib_default_vcd.out
@@ -0,0 +1,115 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module top $end
+  $var wire 1 " clk $end
+  $scope module t $end
+   $var wire 1 " clk $end
+   $var wire 8 # in0 [7:0] $end
+   $var wire 8 $ in1 [7:0] $end
+   $var wire 8 % out0 [7:0] $end
+   $var wire 8 & out1 [7:0] $end
+   $var wire 32 ' count [31:0] $end
+   $scope module i_sub0 $end
+    $var wire 1 ( clk $end
+    $var wire 8 ) in [7:0] $end
+    $var wire 8 * out [7:0] $end
+    $var wire 8 + ff [7:0] $end
+   $upscope $end
+   $scope module i_sub1 $end
+    $var wire 1 , clk $end
+    $var wire 8 - in [7:0] $end
+    $var wire 8 . out [7:0] $end
+    $var wire 8 / ff [7:0] $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+0"
+b00010100 #
+b01100100 $
+b00000000 %
+b00000000 &
+b00000000000000000000000000000000 '
+0(
+b00010100 )
+b00000000 *
+b00000000 +
+0,
+b01100100 -
+b00000000 .
+b00000000 /
+#10
+1"
+b00010101 #
+b01100110 $
+b00010101 %
+b01100110 &
+b00000000000000000000000000000001 '
+1(
+b00010101 )
+b00010101 *
+b00010101 +
+1,
+b01100110 -
+b01100110 .
+b01100110 /
+#15
+0"
+0(
+0,
+#20
+1"
+b00010110 #
+b01101000 $
+b00010110 %
+b01101000 &
+b00000000000000000000000000000010 '
+1(
+b00010110 )
+b00010110 *
+b00010110 +
+1,
+b01101000 -
+b01101000 .
+b01101000 /
+#25
+0"
+0(
+0,
+#30
+1"
+b00010111 #
+b01101010 $
+b00010111 %
+b01101010 &
+b00000000000000000000000000000011 '
+1(
+b00010111 )
+b00010111 *
+b00010111 +
+1,
+b01101010 -
+b01101010 .
+b01101010 /
+#35
+0"
+0(
+0,
+#40
+1"
+b00011000 #
+b01101100 $
+b00011000 %
+b01101100 &
+b00000000000000000000000000000100 '
+1(
+b00011000 )
+b00011000 *
+b00011000 +
+1,
+b01101100 -
+b01101100 .
+b01101100 /
diff --git a/test_regress/t/t_trace_lib_default_vcd.py b/test_regress/t/t_trace_lib_default_vcd.py
new file mode 100755
index 000000000..5d5e0a225
--- /dev/null
+++ b/test_regress/t/t_trace_lib_default_vcd.py
@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_lib_common
+
+test.priority(10)
+test.scenarios('vlt_all')
+
+trace_lib_common.run(test)
diff --git a/test_regress/t/t_trace_lib_notop_fst.out b/test_regress/t/t_trace_lib_notop_fst.out
new file mode 100644
index 000000000..2ea266a51
--- /dev/null
+++ b/test_regress/t/t_trace_lib_notop_fst.out
@@ -0,0 +1,123 @@
+$date
+Sat Mar 21 21:35:35 2026
+
+$end
+$version
+Generated by VerilatedFst
+$end
+$timescale
+1ps
+$end
+ $scope module $rootio $end
+  $var wire 1 ! clk $end
+ $upscope $end
+ $scope module t $end
+  $var wire 1 ! clk $end
+  $var logic 8 " in0 [7:0] $end
+  $var logic 8 # in1 [7:0] $end
+  $var wire 8 $ out0 [7:0] $end
+  $var wire 8 % out1 [7:0] $end
+  $var int 32 & count [31:0] $end
+  $scope module i_sub0 $end
+   $var wire 1 ' clk $end
+   $var wire 8 ( in [7:0] $end
+   $var wire 8 ) out [7:0] $end
+   $var logic 8 * ff [7:0] $end
+  $upscope $end
+  $scope module i_sub1 $end
+   $var wire 1 + clk $end
+   $var wire 8 , in [7:0] $end
+   $var wire 8 - out [7:0] $end
+   $var logic 8 . ff [7:0] $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+b00000000 .
+b00000000 -
+b01100100 ,
+0+
+b00000000 *
+b00000000 )
+b00010100 (
+0'
+b00000000000000000000000000000000 &
+b00000000 %
+b00000000 $
+b01100100 #
+b00010100 "
+0!
+$end
+#10
+1!
+b00010101 "
+b01100110 #
+b00010101 $
+b01100110 %
+b00000000000000000000000000000001 &
+1'
+b00010101 (
+b00010101 )
+b00010101 *
+1+
+b01100110 ,
+b01100110 -
+b01100110 .
+#15
+0+
+0'
+0!
+#20
+1!
+1'
+1+
+b01101000 .
+b01101000 -
+b01101000 ,
+b00010110 *
+b00010110 )
+b00010110 (
+b00000000000000000000000000000010 &
+b01101000 %
+b00010110 $
+b01101000 #
+b00010110 "
+#25
+0+
+0'
+0!
+#30
+1!
+1'
+1+
+b00010111 "
+b01101010 #
+b00010111 $
+b01101010 %
+b00000000000000000000000000000011 &
+b00010111 (
+b00010111 )
+b00010111 *
+b01101010 ,
+b01101010 -
+b01101010 .
+#35
+0+
+0'
+0!
+#40
+1!
+1'
+1+
+b01101100 .
+b01101100 -
+b01101100 ,
+b00011000 *
+b00011000 )
+b00011000 (
+b00000000000000000000000000000100 &
+b01101100 %
+b00011000 $
+b01101100 #
+b00011000 "
diff --git a/test_regress/t/t_trace_lib_notop_fst.py b/test_regress/t/t_trace_lib_notop_fst.py
new file mode 100755
index 000000000..5d5e0a225
--- /dev/null
+++ b/test_regress/t/t_trace_lib_notop_fst.py
@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_lib_common
+
+test.priority(10)
+test.scenarios('vlt_all')
+
+trace_lib_common.run(test)
diff --git a/test_regress/t/t_trace_lib_notop_saif.out b/test_regress/t/t_trace_lib_notop_saif.out
new file mode 100644
index 000000000..2a1053d16
--- /dev/null
+++ b/test_regress/t/t_trace_lib_notop_saif.out
@@ -0,0 +1,141 @@
+// Generated by verilated_saif
+(SAIFILE
+(SAIFVERSION "2.0")
+(DIRECTION "backward")
+(PROGRAM_NAME "Verilator")
+(DIVIDER / )
+(TIMESCALE 1ps)
+(DURATION 40)
+ (INSTANCE $rootio
+  (NET
+   (clk (T0 25) (T1 15) (TZ 0) (TX 0) (TB 0) (TC 7))
+  )
+ )
+ (INSTANCE t
+  (NET
+   (clk (T0 25) (T1 15) (TZ 0) (TX 0) (TB 0) (TC 7))
+   (in0\[0\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 4))
+   (in0\[1\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2))
+   (in0\[2\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+   (in0\[3\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
+   (in0\[4\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+   (in0\[5\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (in0\[6\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (in0\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (in1\[0\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (in1\[1\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 4))
+   (in1\[2\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3))
+   (in1\[3\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+   (in1\[4\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (in1\[5\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+   (in1\[6\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+   (in1\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (out0\[0\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 4))
+   (out0\[1\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2))
+   (out0\[2\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 2))
+   (out0\[3\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
+   (out0\[4\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+   (out0\[5\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (out0\[6\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (out0\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (out1\[0\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (out1\[1\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 4))
+   (out1\[2\] (T0 30) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 3))
+   (out1\[3\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+   (out1\[4\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (out1\[5\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+   (out1\[6\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+   (out1\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (count\[0\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 4))
+   (count\[1\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2))
+   (count\[2\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
+   (count\[3\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (count\[4\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (count\[5\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (count\[6\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (count\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (count\[8\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (count\[9\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (count\[10\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (count\[11\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (count\[12\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (count\[13\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (count\[14\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (count\[15\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (count\[16\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (count\[17\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (count\[18\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (count\[19\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (count\[20\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (count\[21\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (count\[22\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (count\[23\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (count\[24\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (count\[25\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (count\[26\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (count\[27\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (count\[28\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (count\[29\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (count\[30\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (count\[31\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+  )
+  (INSTANCE i_sub0
+   (NET
+    (clk (T0 25) (T1 15) (TZ 0) (TX 0) (TB 0) (TC 7))
+    (in\[0\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 4))
+    (in\[1\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2))
+    (in\[2\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+    (in\[3\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (in\[4\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (in\[5\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (in\[6\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (in\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (out\[0\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 4))
+    (out\[1\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2))
+    (out\[2\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 2))
+    (out\[3\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (out\[4\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (out\[5\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (out\[6\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (out\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (ff\[0\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 4))
+    (ff\[1\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2))
+    (ff\[2\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 2))
+    (ff\[3\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (ff\[4\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (ff\[5\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (ff\[6\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (ff\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   )
+  )
+  (INSTANCE i_sub1
+   (NET
+    (clk (T0 25) (T1 15) (TZ 0) (TX 0) (TB 0) (TC 7))
+    (in\[0\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (in\[1\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 4))
+    (in\[2\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3))
+    (in\[3\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (in\[4\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (in\[5\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (in\[6\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (in\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (out\[0\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (out\[1\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 4))
+    (out\[2\] (T0 30) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 3))
+    (out\[3\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (out\[4\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (out\[5\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (out\[6\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (out\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (ff\[0\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (ff\[1\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 4))
+    (ff\[2\] (T0 30) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 3))
+    (ff\[3\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (ff\[4\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (ff\[5\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (ff\[6\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (ff\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   )
+  )
+ )
+)
diff --git a/test_regress/t/t_trace_lib_notop_saif.py b/test_regress/t/t_trace_lib_notop_saif.py
new file mode 100755
index 000000000..5d5e0a225
--- /dev/null
+++ b/test_regress/t/t_trace_lib_notop_saif.py
@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_lib_common
+
+test.priority(10)
+test.scenarios('vlt_all')
+
+trace_lib_common.run(test)
diff --git a/test_regress/t/t_trace_lib_notop_vcd.out b/test_regress/t/t_trace_lib_notop_vcd.out
new file mode 100644
index 000000000..f21132f3a
--- /dev/null
+++ b/test_regress/t/t_trace_lib_notop_vcd.out
@@ -0,0 +1,115 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module $rootio $end
+  $var wire 1 " clk $end
+ $upscope $end
+ $scope module t $end
+  $var wire 1 " clk $end
+  $var wire 8 # in0 [7:0] $end
+  $var wire 8 $ in1 [7:0] $end
+  $var wire 8 % out0 [7:0] $end
+  $var wire 8 & out1 [7:0] $end
+  $var wire 32 ' count [31:0] $end
+  $scope module i_sub0 $end
+   $var wire 1 ( clk $end
+   $var wire 8 ) in [7:0] $end
+   $var wire 8 * out [7:0] $end
+   $var wire 8 + ff [7:0] $end
+  $upscope $end
+  $scope module i_sub1 $end
+   $var wire 1 , clk $end
+   $var wire 8 - in [7:0] $end
+   $var wire 8 . out [7:0] $end
+   $var wire 8 / ff [7:0] $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+0"
+b00010100 #
+b01100100 $
+b00000000 %
+b00000000 &
+b00000000000000000000000000000000 '
+0(
+b00010100 )
+b00000000 *
+b00000000 +
+0,
+b01100100 -
+b00000000 .
+b00000000 /
+#10
+1"
+b00010101 #
+b01100110 $
+b00010101 %
+b01100110 &
+b00000000000000000000000000000001 '
+1(
+b00010101 )
+b00010101 *
+b00010101 +
+1,
+b01100110 -
+b01100110 .
+b01100110 /
+#15
+0"
+0(
+0,
+#20
+1"
+b00010110 #
+b01101000 $
+b00010110 %
+b01101000 &
+b00000000000000000000000000000010 '
+1(
+b00010110 )
+b00010110 *
+b00010110 +
+1,
+b01101000 -
+b01101000 .
+b01101000 /
+#25
+0"
+0(
+0,
+#30
+1"
+b00010111 #
+b01101010 $
+b00010111 %
+b01101010 &
+b00000000000000000000000000000011 '
+1(
+b00010111 )
+b00010111 *
+b00010111 +
+1,
+b01101010 -
+b01101010 .
+b01101010 /
+#35
+0"
+0(
+0,
+#40
+1"
+b00011000 #
+b01101100 $
+b00011000 %
+b01101100 &
+b00000000000000000000000000000100 '
+1(
+b00011000 )
+b00011000 *
+b00011000 +
+1,
+b01101100 -
+b01101100 .
+b01101100 /
diff --git a/test_regress/t/t_trace_lib_notop_vcd.py b/test_regress/t/t_trace_lib_notop_vcd.py
new file mode 100755
index 000000000..5d5e0a225
--- /dev/null
+++ b/test_regress/t/t_trace_lib_notop_vcd.py
@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_lib_common
+
+test.priority(10)
+test.scenarios('vlt_all')
+
+trace_lib_common.run(test)
diff --git a/test_regress/t/trace_lib_common.py b/test_regress/t/trace_lib_common.py
new file mode 100644
index 000000000..fd61a8c83
--- /dev/null
+++ b/test_regress/t/trace_lib_common.py
@@ -0,0 +1,117 @@
+# pylint: disable=R0914
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import os
+import re
+
+
+def run(test, *, verilator_flags2=()):
+    variant, fmt = test.parse_name(r"t_trace_lib_(default|notop)_([a-z]+)")
+
+    # All test use the same SV file
+    test.top_filename = "t/t_trace_lib.v"
+    # Any variations after the format name must yield the exact same trace
+    test.golden_filename = test.py_filename.rpartition(fmt)[0] + fmt + ".out"
+
+    verilator_common_flags = [
+        "--cc",
+        "--trace-threads",
+        "1",
+        f"--trace-{fmt}",
+        "--trace-underscore",  # Should not trace __Vhandle
+        "--trace-max-width",
+        "0",
+        "--trace-max-array",
+        "0",
+        "--trace-structs"
+    ]
+
+    main_top_name = "top"
+    match variant:
+        case "default":
+            pass
+        case "notop":
+            main_top_name = ""
+        case _:
+            test.error(f"Unhandled test variant '{variant}'")
+
+    verilator_common_flags.extend(verilator_flags2)
+
+    # Compile sub0 --lib-create
+    test.vm_prefix = "Vsub0"
+    test.compile(make_main=False,
+                 threads=1,
+                 verilator_make_gmake=False,
+                 verilator_flags2=verilator_common_flags + [
+                     "+define+SUB0",
+                     "--lib-create",
+                     "sub0",
+                     "--top-module",
+                     "sub0",
+                 ])
+    test.run(logfile=test.obj_dir + "/Vsub0_make.log",
+             cmd=[os.environ["MAKE"], "-C", test.obj_dir, "-f", "Vsub0.mk", "libsub0.a"])
+    # Compile sub1 --lib-create
+    test.vm_prefix = "Vsub1"
+    test.compile(make_main=False,
+                 threads=1,
+                 verilator_make_gmake=False,
+                 verilator_flags2=verilator_common_flags + [
+                     "+define+SUB1",
+                     "--lib-create",
+                     "sub1",
+                     "--top-module",
+                     "sub1",
+                 ])
+    test.run(logfile=test.obj_dir + "/Vsub1_make.log",
+             cmd=[os.environ["MAKE"], "-C", test.obj_dir, "-f", "Vsub1.mk", "libsub1.a"])
+    # Compile top with libraries
+    test.vm_prefix = "Vlibs"
+    test.compile(main_top_name=main_top_name,
+                 verilator_flags2=verilator_common_flags + [
+                     "+define+TOP", test.obj_dir + "/sub0.sv", "libsub0.a",
+                     test.obj_dir + "/sub1.sv", "libsub1.a"
+                 ])
+
+    # Compile simply without libraries
+    test.vm_prefix = "Vnonl"
+    test.main_filename = test.obj_dir + "/Vnonl__main.cpp"
+    test.compile(main_top_name=main_top_name,
+                 verilator_flags2=verilator_common_flags +
+                 ["+define+TOP", "+define+SUB0", "+define+SUB1"])
+
+    trace_libs = test.trace_filename.replace("simx", "libs")
+    trace_nonl = test.trace_filename.replace("simx", "nonl")
+
+    # Run the --lib-create model
+    test.execute(executable=test.obj_dir + "/Vlibs")
+    test.run(cmd=["mv", test.trace_filename, trace_libs])
+    # Run the simple model without libraries
+    test.execute(executable=test.obj_dir + "/Vnonl")
+    test.run(cmd=["mv", test.trace_filename, trace_nonl])
+
+    # Scope structure must match exactly, check only in vcd
+    if fmt == "vcd":
+        with open(trace_nonl, 'r', encoding='utf8') as fnonl, \
+             open(trace_libs, 'r', encoding='utf8') as flibs:
+            for la, lb in zip(fnonl, flibs):
+                la = re.sub(r'^(\s*\$var\s+\S+\s+\S+\s+)\S+(.*)$', r'\1CODE\2', la)
+                lb = re.sub(r'^(\s*\$var\s+\S+\s+\S+\s+)\S+(.*)$', r'\1CODE\2', lb)
+                if la != lb:
+                    test.error_keep_going("VCD header mismatch: '{}' !~ '{}'".format(
+                        la.strip(), lb.strip()))
+                if "enddefinitions" in la:
+                    break
+
+    # The two models must match ignoring enum attributes which can differ
+    test.trace_identical(trace_libs, trace_nonl, ignore_attr=True)
+    # The --lib-create must match the reference
+    test.trace_identical(trace_libs, test.golden_filename)
+
+    test.passes()