diff --git a/Changes b/Changes
index 1edeaf179..3e4174b62 100644
--- a/Changes
+++ b/Changes
@@ -5744,7 +5744,7 @@ Verilator 3.104 2003-04-30
 **Major:**
 
 * Indicate direction of ports with VL_IN and VL_OUT.
-* Allow $c32, etc, to specify width of the $c statement for VCS.
+* Allow $c32, etc, to specify width of the $c statement.
 * Numerous performance improvements, worth about 25%
 
 **Minor:**
diff --git a/src/V3Options.cpp b/src/V3Options.cpp
index 7a85c848d..f9502e00c 100644
--- a/src/V3Options.cpp
+++ b/src/V3Options.cpp
@@ -542,7 +542,7 @@ bool V3Options::fileStatNormal(const string& filename) {
 }
 
 string V3Options::fileExists(const string& filename) {
-    // Surprisingly, for VCS and other simulators, this process
+    // Surprisingly, for some other simulators, this process
     // is quite slow; presumably because of re-reading each directory
     // many times.  So we read a whole dir at once and cache it
 
diff --git a/test_regress/t/t_array_packed_sysfunct.v b/test_regress/t/t_array_packed_sysfunct.v
index e31d38929..c380fa898 100644
--- a/test_regress/t/t_array_packed_sysfunct.v
+++ b/test_regress/t/t_array_packed_sysfunct.v
@@ -33,9 +33,7 @@ module t (
 
   initial begin
     `checkh($dimensions (array_unpk), 3);
-`ifndef VCS
     `checkh($unpacked_dimensions (array_unpk), 2);  // IEEE 2009
-`endif
     `checkh($bits (array_unpk), 2*2*2);
     `checkh($low  (array_unpk), 2);
     `checkh($high (array_unpk), 3);
diff --git a/test_regress/t/t_assert_always_unbounded.v b/test_regress/t/t_assert_always_unbounded.v
index 9f41a2627..f408c5885 100644
--- a/test_regress/t/t_assert_always_unbounded.v
+++ b/test_regress/t/t_assert_always_unbounded.v
@@ -35,7 +35,7 @@ module t (
   assert property (@(posedge clk) always [2:$] a_low) else low2_fail_q.push_back(cyc);
 
   // a_drop is high then drops at cyc 5 and stays low: deterministic single
-  // transition, so Verilator and Questa agree on the failing ticks exactly.
+  // transition, so Verilator and others agree on the failing ticks exactly.
   assert property (@(posedge clk) always [2:$] a_drop) else drop_fail_q.push_back(cyc);
 
   always @(posedge clk) begin
@@ -43,12 +43,12 @@ module t (
     if (cyc >= 4) a_drop <= 1'b0;
     if (cyc == 19) begin
       // Counts pinned to Verilator (NFA per-cycle reject). For all-fail windows
-      // Questa is one lower (it does not fire the end-of-sim tick); see the sva
+      // others are one lower (it does not fire the end-of-sim tick); see the sva
       // lessons "multi-cycle end-of-simulation offset" note.
-      `checkd(high_fail_q.size(), 0);  // Questa: 0
-      `checkd(low0_fail_q.size(), 20);  // Questa: 19
-      `checkd(low2_fail_q.size(), 18);  // Questa: 17
-      `checkd(drop_fail_q[0], 5);  // first fail tick: a_drop sampled low from cyc 5
+      `checkd(high_fail_q.size(), 0);
+      `checkd(low0_fail_q.size(), 20);  // All others: 19
+      `checkd(low2_fail_q.size(), 18);  // All others: 17
+      `checkd(drop_fail_q[0], 5);  // All others: 6; first fail tick: a_drop sampled low from cyc 5
       $write("*-* All Finished *-*\n");
       $finish;
     end
diff --git a/test_regress/t/t_assert_bang_in_seq.v b/test_regress/t/t_assert_bang_in_seq.v
index b0c831229..784dd338a 100644
--- a/test_regress/t/t_assert_bang_in_seq.v
+++ b/test_regress/t/t_assert_bang_in_seq.v
@@ -66,12 +66,12 @@ module t (
     end
     else if (cyc == 99) begin
       `checkh(crc, 64'hc77bb9b3784ea091);
-      `checkd(count_fail1, 66);  // Questa: 66
-      `checkd(count_fail2, 69);  // Questa: 69
-      `checkd(count_fail3, 26);  // Questa: 26
-      `checkd(count_fail4, 66);  // Questa: 66
-      `checkd(count_fail5, 80);  // Questa: 80
-      `checkd(count_fail6, 27);  // Questa: 27
+      `checkd(count_fail1, 66);
+      `checkd(count_fail2, 69);
+      `checkd(count_fail3, 26);
+      `checkd(count_fail4, 66);
+      `checkd(count_fail5, 80);
+      `checkd(count_fail6, 27);
       $write("*-* All Finished *-*\n");
       $finish;
     end
diff --git a/test_regress/t/t_assert_consec_rep.v b/test_regress/t/t_assert_consec_rep.v
index 8a4d87040..206b49886 100644
--- a/test_regress/t/t_assert_consec_rep.v
+++ b/test_regress/t/t_assert_consec_rep.v
@@ -95,23 +95,23 @@ module t (
     end
     else if (cyc == 99) begin
       `checkh(crc, 64'hc77bb9b3784ea091);
-      `checkd(count_fail1, 5);    // Questa: 5
-      `checkd(count_fail2, 25);   // Questa: 25
-      `checkd(count_fail3, 9);    // Questa: 9
-      `checkd(count_fail4, 49);   // Questa: 49
-      `checkd(count_fail5, 0);    // Questa: 0
-      // NFA merge-node range [*M:N] over-counts rejects (Questa: 51); match
+      `checkd(count_fail1, 5);
+      `checkd(count_fail2, 25);  // One other sim: 19
+      `checkd(count_fail3, 9);
+      `checkd(count_fail4, 49);
+      `checkd(count_fail5, 0);
+      // NFA merge-node range [*M:N] over-counts rejects; match
       // detection is correct, only reject counting is imprecise
-      `checkd(count_fail6, 59);
-      `checkd(count_fail7, 51);   // Questa: 51
-      `checkd(count_fail8, 20);   // Questa: 20
+      `checkd(count_fail6, 59);  // All other sims: 51
+      `checkd(count_fail7, 51);
+      `checkd(count_fail8, 20);
       // IEEE 1800-2023 16.9.2 permits empty match of [*0]; NFA reports
-      // rejects on each tick while Questa suppresses (Questa: 20)
-      `checkd(count_fail9, 49);
-      `checkd(count_fail10, 59);  // Questa: 59
+      // rejects on each tick while others suppress
+      `checkd(count_fail9, 49);  // Most others: 20, one other 49
+      `checkd(count_fail10, 59);
       // a[*] ##1 b: NFA treats unbounded [*] as liveness (no reject);
-      // Questa treats as definite antecedent (Questa: 29)
-      `checkd(count_fail11, 0);
+      // Should be definite antecedent
+      `checkd(count_fail11, 0);  // All other sims: 29
       $write("*-* All Finished *-*\n");
       $finish;
     end
diff --git a/test_regress/t/t_assert_consec_rep_large.v b/test_regress/t/t_assert_consec_rep_large.v
index 359537ce7..4df36f7bc 100644
--- a/test_regress/t/t_assert_consec_rep_large.v
+++ b/test_regress/t/t_assert_consec_rep_large.v
@@ -40,8 +40,8 @@ module t (
     else if (cyc == 99) begin
       `checkh(crc, 64'hc77bb9b3784ea091);
       `checkd(count_fail_257, 0);
-      // Questa: 31 -- pre-existing ~26.5% NFA reject gap on |-> ##1 [*N]
-      `checkd(count_fail_513, 23);
+      // Mismatch due to pre-existing ~26.5% NFA reject gap on |-> ##1 [*N]
+      `checkd(count_fail_513, 23);  // All other sims: 31
       $write("*-* All Finished *-*\n");
       $finish;
     end
diff --git a/test_regress/t/t_assert_ctl_lock.v b/test_regress/t/t_assert_ctl_lock.v
index 59c98a006..c47e3b341 100644
--- a/test_regress/t/t_assert_ctl_lock.v
+++ b/test_regress/t/t_assert_ctl_lock.v
@@ -5,6 +5,8 @@
 // SPDX-License-Identifier: CC0-1.0
 
 // verilog_format: off
+`define stop $stop
+`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
 `ifdef verilator
  `define no_optimize(v) $c(v)
 `else
@@ -12,7 +14,7 @@
 `endif
 // verilog_format: on
 
-module t (  /*AUTOARG*/);
+module t;
   logic clk = 0;
   int imm_fails = 0, conc_fails = 0;
   logic a = 1'b1;  // antecedent always true
@@ -58,11 +60,8 @@ module t (  /*AUTOARG*/);
   end
 
   final begin
-    // Concrete counts cross-checked against Questa 2022.3: imm_fails=5 conc_fails=7.
-    if (imm_fails != 5 || conc_fails != 7) begin
-      $display("%%Error: imm_fails=%0d (exp 5) conc_fails=%0d (exp 7)", imm_fails, conc_fails);
-      $stop;
-    end
+    `checkd(imm_fails, 5);
+    `checkd(conc_fails, 7);  // Other sims: 7 or 1
     $write("*-* All Finished *-*\n");
   end
 endmodule
diff --git a/test_regress/t/t_assert_goto_rep.v b/test_regress/t/t_assert_goto_rep.v
index f926a3b5b..1a209444b 100644
--- a/test_regress/t/t_assert_goto_rep.v
+++ b/test_regress/t/t_assert_goto_rep.v
@@ -75,14 +75,14 @@ module t (
     end
     else if (cyc == 99) begin
       `checkh(crc, 64'hc77bb9b3784ea091);
-      `checkd(count_fail1, 20);  // Questa: 20
-      `checkd(count_fail2, 25);  // Questa: 25
-      `checkd(count_fail3, 19);  // Questa: 19
-      `checkd(count_fail4, 0);  // Questa: 0
-      `checkd(count_fail5, 20);  // Questa: 20
-      `checkd(count_fail6, 25);  // Questa: 25
-      `checkd(count_fail7, 20);  // Questa: 20
-      `checkd(count_fail8, 20);  // Questa: 20
+      `checkd(count_fail1, 20);
+      `checkd(count_fail2, 25);
+      `checkd(count_fail3, 19);
+      `checkd(count_fail4, 0);
+      `checkd(count_fail5, 20);
+      `checkd(count_fail6, 25);
+      `checkd(count_fail7, 20);
+      `checkd(count_fail8, 20);
       $write("*-* All Finished *-*\n");
       $finish;
     end
diff --git a/test_regress/t/t_assert_nonconsec_rep.v b/test_regress/t/t_assert_nonconsec_rep.v
index 6d759b9c2..c69db8bf9 100644
--- a/test_regress/t/t_assert_nonconsec_rep.v
+++ b/test_regress/t/t_assert_nonconsec_rep.v
@@ -56,10 +56,10 @@ module t (
     end
     else if (cyc == 99) begin
       `checkh(crc, 64'hc77bb9b3784ea091);
-      `checkd(count_fail1, 34);  // Questa: 29
-      `checkd(count_fail2, 27);  // Questa: 32
-      `checkd(count_fail3, 25);  // Questa: 29
-      `checkd(count_fail4, 0);  // Questa: 0
+      `checkd(count_fail1, 34);  // Other sims: 29, one other: 20
+      `checkd(count_fail2, 27);  // Other sims: 32, one other: 25
+      `checkd(count_fail3, 25);  // Other sims: 29, one other: 25
+      `checkd(count_fail4, 0);
       $write("*-* All Finished *-*\n");
       $finish;
     end
diff --git a/test_regress/t/t_assert_procedural_gated.v b/test_regress/t/t_assert_procedural_gated.v
index 9ed88121f..56e38ed41 100644
--- a/test_regress/t/t_assert_procedural_gated.v
+++ b/test_regress/t/t_assert_procedural_gated.v
@@ -57,9 +57,8 @@ module t (
     end
     else if (cyc == 99) begin
       `checkh(crc, 64'hc77bb9b3784ea091);
-      // Questa 2022.3 golden: count_gated=5, count_ref=12.
-      `checkd(count_gated, 5);
-      `checkd(count_ref, 12);
+      `checkd(count_gated, 5);  // Other sims same, one other: 4
+      `checkd(count_ref, 12);  // Other sims same, one other: 10
       $write("*-* All Finished *-*\n");
       $finish;
     end
diff --git a/test_regress/t/t_assert_seq_clocking.v b/test_regress/t/t_assert_seq_clocking.v
index b835acb85..9c59d7287 100644
--- a/test_regress/t/t_assert_seq_clocking.v
+++ b/test_regress/t/t_assert_seq_clocking.v
@@ -44,10 +44,9 @@ module t (
   end
 
   // Counts read in final (Postponed) to avoid same-timestep races.
-  // Concrete Verilator counts; Questa: fails_single=17 fails_multi=17
   final begin
-    `checkd(fails_single, 17);
-    `checkd(fails_multi, 17);
+    `checkd(fails_single, 17);  // Other sims: 0
+    `checkd(fails_multi, 17);  // Other sims: 0
     $write("*-* All Finished *-*\n");
   end
 endmodule
diff --git a/test_regress/t/t_constraint_dist_foreach_if.v b/test_regress/t/t_constraint_dist_foreach_if.v
index a8eaedb24..5d6f1b2ec 100644
--- a/test_regress/t/t_constraint_dist_foreach_if.v
+++ b/test_regress/t/t_constraint_dist_foreach_if.v
@@ -8,7 +8,8 @@
 // values only within the declared distribution and cover all buckets.
 
 // verilog_format: off
-`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
+`define stop $stop
+`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
 // verilog_format: on
 
 // foreach (a[i]) if (gate) a[i] dist {...}
diff --git a/test_regress/t/t_cover_property.v b/test_regress/t/t_cover_property.v
index 40089451c..d68118d96 100644
--- a/test_regress/t/t_cover_property.v
+++ b/test_regress/t/t_cover_property.v
@@ -60,18 +60,17 @@ module t (
     // A cover of an implication counts only non-vacuous matches (IEEE
     // 1800-2023 16.15.2): the antecedent must match. So it is identical to the
     // corresponding sequence cover, not the vacuous implication value.
-    `checkd(n_imp_no, n_seq)
-    `checkd(n_imp_ov, n_seq0)
+    `checkd(n_imp_no, n_seq);  // Other sims: pass, 73
+    `checkd(n_imp_ov, n_seq0);  // Other sims: pass, 45
     // A named-property cover lowers the same implication, so it also counts
     // non-vacuously (regression guard for the property-inlining path).
-    `checkd(n_named, n_imp_no)
-    // Pinned Verilator counts; Questa golden cross-checked.
-    `checkd(n_imp_no, 28)  // Questa: 28
-    `checkd(n_imp_ov, 27)  // Questa: 27
-    `checkd(n_seq, 28)  // Questa: 28
-    `checkd(n_seq0, 27)  // Questa: 27
-    `checkd(n_bool, 55)  // Questa: 54
-    `checkd(n_named, 28)  // Questa: 28
+    `checkd(n_named, n_imp_no);
+    `checkd(n_imp_no, 28);
+    `checkd(n_imp_ov, 27);  // Other sims: pass, 73
+    `checkd(n_seq, 28);  // Other sims: 45, 27
+    `checkd(n_seq0, 27);
+    `checkd(n_bool, 55);  // Other sims: pass, 25
+    `checkd(n_named, 28);  // Other sims: 73, 54, 54
   end
 
 endmodule
diff --git a/test_regress/t/t_cover_sequence.v b/test_regress/t/t_cover_sequence.v
index 42f39949e..79516a81c 100644
--- a/test_regress/t/t_cover_sequence.v
+++ b/test_regress/t/t_cover_sequence.v
@@ -69,22 +69,21 @@ module t (
 
   // Read the counters in 'final', not the clocked block: a same-cycle read of a
   // cover counter races the cover's increment under --threads (vltmt). Verilator
-  // counts one more end-of-match than Questa 2022.3 on some forms at the
-  // simulation boundary; the Questa value is noted per check.
+  // counts one more end-of-match than others on some forms.
   final begin
 `ifdef TEST_VERBOSE
     $write("simple=%0d clocked=%0d clk_dis=%0d def_dis=%0d range=%0d 2=%0d 3=%0d\n", hit_simple,
            hit_clocked, hit_clocked_disable, hit_default_disable, hit_consrep_range, hit_consrep_2,
            hit_consrep_3);
 `endif
-    `checkd(hit_simple, 96);  // Questa: 95
-    `checkd(hit_clocked, 149);  // Questa: 149
-    `checkd(hit_clocked_disable, 27);  // Questa: 27
-    `checkd(hit_default_disable, 30);  // Questa: 30
-    `checkd(hit_consrep_2, 30);  // Questa: 29
-    `checkd(hit_consrep_3, 14);  // Questa: 13
+    `checkd(hit_simple, 96);  // Other sims: 5, 95
+    `checkd(hit_clocked, 149);
+    `checkd(hit_clocked_disable, 27);
+    `checkd(hit_default_disable, 30);
+    `checkd(hit_consrep_2, 30);  // Other sims: 29
+    `checkd(hit_consrep_3, 14);  // Other sims: 13
     // a[*2:3] == a[*2] or a[*3] (IEEE 1800-2023 16.9.2)
-    `checkd(hit_consrep_range, hit_consrep_2 + hit_consrep_3);  // 44; Questa: 42
+    `checkd(hit_consrep_range, hit_consrep_2 + hit_consrep_3);
     $write("*-* All Finished *-*\n");
   end
 endmodule
diff --git a/test_regress/t/t_forceable_unpacked.v b/test_regress/t/t_forceable_unpacked.v
index 5e0048563..3b3cd23a0 100644
--- a/test_regress/t/t_forceable_unpacked.v
+++ b/test_regress/t/t_forceable_unpacked.v
@@ -5,7 +5,8 @@
 // SPDX-License-Identifier: CC0-1.0
 
 // verilog_format: off
-`define checkh(g,e) do if ((g) !==(e)) begin $write("%%Error: %s:%0d: got=%x exp=%x\n", `__FILE__,`__LINE__, (g),(e)); $stop; end while(0)
+`define stop $stop
+`define checkh(g,e) do if ((g) !==(e)) begin $write("%%Error: %s:%0d: got=%x exp=%x\n", `__FILE__,`__LINE__, (g),(e)); `stop; end while(0)
 
 `ifdef CMT
  `define FORCEABLE /*verilator forceable*/
diff --git a/test_regress/t/t_gen_for.v b/test_regress/t/t_gen_for.v
index 47d7ba1a7..006b9f83a 100644
--- a/test_regress/t/t_gen_for.v
+++ b/test_regress/t/t_gen_for.v
@@ -97,8 +97,6 @@ module paramed (  /*AUTOARG*/
     // No else
   endgenerate
 
-`ifndef NC  // for(genvar) unsupported
-`ifndef ATSIM  // for(genvar) unsupported
   generate
     // Empty loop body, local genvar
     for (genvar j = 0; j < 3; j = j + 1) begin
@@ -107,8 +105,6 @@ module paramed (  /*AUTOARG*/
     for (genvar j = 0; j < 5; j = j + 1) begin
     end
   endgenerate
-`endif
-`endif
 
   generate
   endgenerate
diff --git a/test_regress/t/t_gen_intdot.v b/test_regress/t/t_gen_intdot.v
index d00c7028a..248616e8e 100644
--- a/test_regress/t/t_gen_intdot.v
+++ b/test_regress/t/t_gen_intdot.v
@@ -10,30 +10,34 @@ module t (
     input clk
 );
 
-  integer      cyc = 0;
+  integer cyc = 0;
 
-  wire         out;
-  reg          in;
+  wire out;
+  reg in;
 
-  Genit g (.clk(clk), .value(in), .result(out));
+  Genit g (
+      .clk(clk),
+      .value(in),
+      .result(out)
+  );
 
-  always @ (posedge clk) begin
+  always @(posedge clk) begin
     //$write("[%0t] cyc==%0d %x %x\n", $time, cyc, in, out);
     cyc <= cyc + 1;
-    if (cyc==0) begin
+    if (cyc == 0) begin
       // Setup
       in <= 1'b1;
     end
-    else if (cyc==1) begin
+    else if (cyc == 1) begin
       in <= 1'b0;
     end
-    else if (cyc==2) begin
+    else if (cyc == 2) begin
       if (out != 1'b1) $stop;
     end
-    else if (cyc==3) begin
+    else if (cyc == 3) begin
       if (out != 1'b0) $stop;
     end
-    else if (cyc==9) begin
+    else if (cyc == 9) begin
       $write("*-* All Finished *-*\n");
       $finish;
     end
@@ -41,7 +45,11 @@ module t (
 
 endmodule
 
-module Generate (clk, value, result);
+module Generate (
+    clk,
+    value,
+    result
+);
   input clk;
   input value;
   output result;
@@ -50,63 +58,73 @@ module Generate (clk, value, result);
 
   assign result = Internal;
 
-  always @(posedge clk)
-    Internal <= value;
+  always @(posedge clk) Internal <= value;
 endmodule
 
-module Checker (clk, value);
+module Checker (
+    clk,
+    value
+);
   input clk, value;
 
   always @(posedge clk) begin
-    $write ("[%0t] value=%h\n", $time, value);
+    $write("[%0t] value=%h\n", $time, value);
   end
 
 endmodule
 
-module Test (clk, value, result);
+module Test (
+    clk,
+    value,
+    result
+);
   input clk;
   input value;
   output result;
 
-  Generate gen (clk, value, result);
-  Checker  chk (clk, gen.Internal);
+  Generate gen (
+      clk,
+      value,
+      result
+  );
+  Checker chk (
+      clk,
+      gen.Internal
+  );
 
 endmodule
 
-module Genit (clk, value, result);
+module Genit (
+    clk,
+    value,
+    result
+);
   input clk;
   input value;
   output result;
 
-`ifndef ATSIM  // else unsupported
- `ifndef NC  // else unsupported
-  `ifndef IVERILOG  // else unsupported
-  `define WITH_FOR_GENVAR
-  `endif
- `endif
-`endif
-
-`define WITH_GENERATE
+  `define WITH_GENERATE
 `ifdef WITH_GENERATE
- `ifndef WITH_FOR_GENVAR
   genvar i;
- `endif
   generate
-    for (
- `ifdef WITH_FOR_GENVAR
-        genvar
- `endif
-        i = 0; i < 1; i = i + 1)
-      begin : foo
-        Test tt (clk, value, result);
-      end
+    for (genvar i = 0; i < 1; i = i + 1) begin : foo
+      Test tt (
+          clk,
+          value,
+          result
+      );
+    end
   endgenerate
 `else
-  Test tt (clk, value, result);
+  Test tt (
+      clk,
+      value,
+      result
+  );
 `endif
 
   wire Result2 = t.g.foo[0].tt.gen.Internal;  // Works - Do not change!
-  always @ (posedge clk) begin
+  always @(posedge clk) begin
     $write("[%0t] Result2 = %x\n", $time, Result2);
   end
 
diff --git a/test_regress/t/t_inst_signed.v b/test_regress/t/t_inst_signed.v
index bd46592dd..bfb24f007 100644
--- a/test_regress/t/t_inst_signed.v
+++ b/test_regress/t/t_inst_signed.v
@@ -34,9 +34,9 @@ module t (
     if (sgn_wide[2:0] != 3'sh7) $stop;
     if (unsgn_wide[2:0] != 3'h7) $stop;
     // Simulators differ here.
-    if (sgn_wide !== 8'sbzzzzz111  // z-extension - NC
-        && sgn_wide !== 8'sb11111111)
-      $stop;  // sign extension - VCS
+    if (sgn_wide !== 8'sbzzzzz111  // z-extension - some others
+        && sgn_wide !== 8'sb11111111)  // sign extension - some others
+      $stop;
     if (unsgn_wide !== 8'sbzzzzz111 && unsgn_wide !== 8'sb00000111) $stop;
     cyc <= cyc + 1;
     if (cyc == 3) begin
diff --git a/test_regress/t/t_interface2.v b/test_regress/t/t_interface2.v
index e11f71b1f..52c3ac79e 100644
--- a/test_regress/t/t_interface2.v
+++ b/test_regress/t/t_interface2.v
@@ -12,7 +12,7 @@ module t (
 
   counter_io c1_data();
   counter_io c2_data();
-  //counter_io c3_data;        // IEEE illegal, and VCS doesn't allow non-() as it does with cells
+  // counter_io c3_data;  // IEEE illegal
   counter_io c3_data();
 
   counter_ansi  c1 (.clkm(clk),
diff --git a/test_regress/t/t_interface_array_nocolon.v b/test_regress/t/t_interface_array_nocolon.v
index a5af54af4..c8015b005 100644
--- a/test_regress/t/t_interface_array_nocolon.v
+++ b/test_regress/t/t_interface_array_nocolon.v
@@ -37,7 +37,6 @@ module t;
 
   initial begin
     // Check numbering with 0 first
-    // NC has a bug here
     if (foos[0].x !== 1'b1) $stop;
     if (foos[1].x !== 1'b1) $stop;
     if (foos[2].x !== 1'b0) $stop;
diff --git a/test_regress/t/t_interface_virtual_sub_iface_method.v b/test_regress/t/t_interface_virtual_sub_iface_method.v
index 6cf486f5b..d5d9a59fe 100644
--- a/test_regress/t/t_interface_virtual_sub_iface_method.v
+++ b/test_regress/t/t_interface_virtual_sub_iface_method.v
@@ -4,7 +4,8 @@
 // SPDX-FileCopyrightText: 2026 PlanV GmbH
 // SPDX-License-Identifier: CC0-1.0
 // verilog_format: off
-`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
+`define stop $stop
+`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
 // verilog_format: on
 
 interface inner_if;
diff --git a/test_regress/t/t_math_pow.v b/test_regress/t/t_math_pow.v
index 72a617697..35aab1cb3 100644
--- a/test_regress/t/t_math_pow.v
+++ b/test_regress/t/t_math_pow.v
@@ -244,9 +244,7 @@ module t (
       `checkh(67'h0 ** 21'h0, 67'h1);
       `checkh(67'sh0 ** 21'sh0, 67'sh1);
       `checkh(67'h10 ** 21'h0, 67'h1);
-`ifndef VCS
       `checkh(61'h7ab3811219 ** 21'ha6e30, 61'h01ea58c703687e81);
-`endif
       if (cyc==0) begin end
       else if (cyc==1) begin a <= 67'h0; b <= 67'h0; end
       else if (cyc==2) begin a <= 67'h0; b <= 67'h3; end
diff --git a/test_regress/t/t_math_pow3.v b/test_regress/t/t_math_pow3.v
index b591618b3..f0c18f8b6 100644
--- a/test_regress/t/t_math_pow3.v
+++ b/test_regress/t/t_math_pow3.v
@@ -16,22 +16,21 @@ module t;
 
   // verilog_format: off
   initial begin
-    // NC=67b6cfc1b29a21  VCS=c1b29a20(wrong)   IV=67b6cfc1b29a21  Verilator=67b6cfc1b29a21
     $display("15 ** 14    = %0x  expect 67b6cfc1b29a21", 64'b1111 ** 64'b1110);
-    // NC=1   VCS=0  IV=0   Verilator=1 (wrong,fixed)
     $display("15 **-4'sd2 = %0x expect 0 (per IEEE negative power)", ((-4'd1 ** -4'sd2)));
-    // NC=1   VCS=0  IV=67b6cfc1b29a21(wrong)  Verilator=1
     $display("15 ** 14    = %0x expect 1 (LSB 4-bits of 67b6cfc1b29a21)", ((-4'd1 ** -4'd2)));
-    // NC=1   VCS=0  IV=67b6cfc1b29a21(wrong)  Verilator=1
     $display("15 ** 14    = %0x expect 1 (LSB 4-bits of 67b6cfc1b29a21)", ((4'd15 ** 4'd14)));
-    // NC=8765432187654321  VCS=8765432187654000(wrong) IV=8765432187654321   Verilator=8765432187654321
     $display("64'big ** 1 = %0x  expect %0x", 64'h8765432187654321 ** 1, 64'h8765432187654321);
     $display("\n");
 
     `checkh( (64'b1111 ** 64'b1110),  64'h67b6cfc1b29a21);
+`ifndef NC
     `checkh( (-4'd1 ** -4'sd2),       4'h0);  //bug730
+`endif
+`ifndef VCS
     `checkh( (-4'd1 ** -4'd2),                4'h1);
     `checkh( (4'd15 ** 4'd14),                4'h1);
+`endif
     `checkh( (64'h8765432187654321 ** 4'h1), 64'h8765432187654321);
 
     `checkh((-8'sh3 **  8'h3) ,  8'he5 );  // a**b  (-27)
@@ -70,13 +69,23 @@ module t;
     `checkh(( 8'h3  ** -8'sh0),  8'h1 );  // a**0 always 1
     `checkh(( 8'sh3 ** -8'sh0),  8'h1 );  // a**0 always 1
 
-    `checkh((-8'sh3 ** -8'sh3),  8'h0 );  // 0 (a<-1)    // NCVERILOG bug
+`ifndef NC
+    `checkh((-8'sh3 ** -8'sh3),  8'h0 );  // 0 (a<-1)
+`endif
+`ifndef IVERILOG
+`ifndef QUESTA
+`ifndef VCS
     `checkh((-8'sh1 ** -8'sh2),  8'h1 );  // -1^odd=-1, -1^even=1
     `checkh((-8'sh1 ** -8'sh3),  8'hff);  // -1^odd=-1, -1^even=1
-//    `checkh(( 8'h0  ** -8'sh3),  8'hx );  // x  // NCVERILOG bug
+`endif
+`endif
+`endif
+//    `checkh(( 8'h0  ** -8'sh3),  8'hx );  // x
     `checkh(( 8'h1  ** -8'sh3),  8'h1 );  // 1**b always 1
-    `checkh(( 8'h3  ** -8'sh3),  8'h0 );  // 0  // NCVERILOG bug
-    `checkh(( 8'sh3 ** -8'sh3),  8'h0 );  // 0  // NCVERILOG bug
+`ifndef NC
+    `checkh(( 8'h3  ** -8'sh3),  8'h0 );  // 0
+    `checkh(( 8'sh3 ** -8'sh3),  8'h0 );  // 0
+`endif
 
 
     if (fail) $stop;
diff --git a/test_regress/t/t_math_signed4.v b/test_regress/t/t_math_signed4.v
index bb5d83602..05b7e6f7c 100644
--- a/test_regress/t/t_math_signed4.v
+++ b/test_regress/t/t_math_signed4.v
@@ -97,11 +97,7 @@ module t;
 
     // bug754
     w5_u = 4'sb0010 << -2'sd1;  // << 3
-`ifdef VCS
-    `checkh(w5_u, 5'b00000);  // VCS E-2014.03 bug
-`else
-    `checkh(w5_u, 5'b10000);  // VCS E-2014.03 bug
-`endif
+    `checkh(w5_u, 5'b10000);
     w5_u = 4'sb1000 << 0;  // Sign extends
     `checkh(w5_u, 5'b11000);
 
diff --git a/test_regress/t/t_math_signed5.v b/test_regress/t/t_math_signed5.v
index b87b854f2..aa9a68d79 100644
--- a/test_regress/t/t_math_signed5.v
+++ b/test_regress/t/t_math_signed5.v
@@ -47,11 +47,7 @@ module t (  /*AUTOARG*/
   initial begin
     // verilator lint_off STMTDLY
     #1;
-`ifdef VCS  // I-2014.03
-    `checkh({a, b, c, d, e, f, g}, 7'b1101111);
-`else
     `checkh({a, b, c, d, e, f, g}, 7'b1101011);
-`endif
 
     //======================================================================
 
@@ -76,20 +72,11 @@ module t (  /*AUTOARG*/
     w4_u = ((5'b0 == (5'sb11111 >>> 3'd7)));  // Exp 0     Vlt 0
     `checkh(w4_u, 4'b0001);
     w4_u = ((5'b01111 == (5'sb11111 / 5'sd2)));  // Strength-reduces to >>>
-`ifdef VCS  // I-2014.03
-    `checkh(w4_u, 4'b0000);  // Wrong, gets 5'b0==..., unsigned does not propagate
-`else
-    `checkh(w4_u, 4'b0001);  // NC-Verilog, Modelsim, XSim, ...
-`endif
+    `checkh(w4_u, 4'b0001);
 
-    // Does == sign propagate from lhs to rhs?  Yes, but not in VCS
+    // Does == sign propagate from lhs to rhs?
     w4_u = ((5'b01010 == (5'sb11111 / 5'sd3)));    // Exp 0     Vlt 0  // Must be signed result (-1/3) to make this result zero
-`ifdef VCS  // I-2014.03
-    `checkh(w4_u, 4'b0000);  // Wrong, gets 5'b0==..., unsigned does not propagate
-    // Somewhat questionable, as spec says division signed depends on only LHS and RHS, however differs from others
-`else
-    `checkh(w4_u, 4'b0001);  // NC-Verilog, Modelsim, XSim, ...
-`endif
+    `checkh(w4_u, 4'b0001);
 
     w4_u = (1'b0+(5'sb11111 >>> 3'd7));        // Exp 00000 Vlt 000000 Actually the signedness of result does NOT matter
     `checkh(w4_u, 4'b0000);
diff --git a/test_regress/t/t_math_svl2.v b/test_regress/t/t_math_svl2.v
index b6049d112..1d62f7006 100644
--- a/test_regress/t/t_math_svl2.v
+++ b/test_regress/t/t_math_svl2.v
@@ -19,15 +19,11 @@ module t (
         if ('1 !== {66{1'b1}}) $stop;
         if ('x !== {66{1'bx}}) $stop;
         if ('z !== {66{1'bz}}) $stop;
-`ifndef NC  // NC-Verilog 5.50-s09 chokes on this test
         if ("\v" != 8'd11) $stop;
         if ("\f" != 8'd12) $stop;
         if ("\a" != 8'd7) $stop;
         if ("\x9a" != 8'h9a) $stop;
         if ("\xf1" != 8'hf1) $stop;
-`endif
-      end
-      if (cyc == 8) begin
       end
       if (cyc == 9) begin
         $write("*-* All Finished *-*\n");
diff --git a/test_regress/t/t_modport_export_task.v b/test_regress/t/t_modport_export_task.v
index 848c05ccf..0016f7a3d 100644
--- a/test_regress/t/t_modport_export_task.v
+++ b/test_regress/t/t_modport_export_task.v
@@ -5,7 +5,8 @@
 // SPDX-License-Identifier: CC0-1.0
 
 // verilog_format: off
-`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0)
+`define stop $stop
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
 // verilog_format: on
 
 interface bus_if;
diff --git a/test_regress/t/t_param_first.v b/test_regress/t/t_param_first.v
index eea84e2c3..6ded92a93 100644
--- a/test_regress/t/t_param_first.v
+++ b/test_regress/t/t_param_first.v
@@ -63,12 +63,11 @@ module t (
   parameter THREE_2WIDE = 2'b11;
   parameter ALSO_THREE_WIDE = THREE_BITS_WIDE;
   parameter THREEPP_32_WIDE = 2 * 8 * 2 + 3;
-  parameter THREEPP_3_WIDE = 3'd4 * 3'd4 * 3'd2 + 3'd3;  // Yes folks VCS says 3 bits wide
+  parameter THREEPP_3_WIDE = 3'd4 * 3'd4 * 3'd2 + 3'd3;
 
   // Width propagation doesn't care about LHS vs RHS
   // But the width of a RHS/LHS on a upper node does affect lower nodes;
   // Thus must double-descend in width analysis.
-  // VCS 7.0.1 is broken on this test!
   parameter T10 = (3'h7 + 3'h7) + 4'h0;  //initial if (T10!==4'd14) $stop;
   parameter T11 = 4'h0 + (3'h7 + 3'h7);  //initial if (T11!==4'd14) $stop;
 
diff --git a/test_regress/t/t_prop_always.v b/test_regress/t/t_prop_always.v
index 52cfea02c..f389a3a8c 100644
--- a/test_regress/t/t_prop_always.v
+++ b/test_regress/t/t_prop_always.v
@@ -43,11 +43,9 @@ module t (
 
   // Constant-false: every attempt fails.
   assert property (@(posedge clk) always [0:3] a_low)
-    ;
   else low_bounded_fail_q.push_back(cyc);
 
   assert property (@(posedge clk) always [0:0] a_low)
-    ;
   else low_degenerate_fail_q.push_back(cyc);
 
   // CRC-driven random input: window [cyc..cyc+3] of a_rand.
@@ -76,21 +74,21 @@ module t (
     crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
     if (cyc == 19) begin
       // Constant-true window [0:3]: K=0..16 succeed at cyc K+3 = 3..19.
-      `checkd(high_bounded_pass_q.size(), 17);
-      `checkd(high_bounded_pass_q[0], 3);
+      `checkd(high_bounded_pass_q.size(), 17);  // Other sims: 16
+      `checkd(high_bounded_pass_q[0], 3);  // Other sims: 4
       `checkd(high_bounded_pass_q[$], 19);
       // Degenerate [0:0]: K=0..19 succeed at cyc K = 0..19.
-      `checkd(high_degenerate_pass_q.size(), 20);
-      `checkd(high_degenerate_pass_q[0], 0);
+      `checkd(high_degenerate_pass_q.size(), 20);  // Other sims: 19
+      `checkd(high_degenerate_pass_q[0], 0);  // Other sims: 0, 1
       `checkd(high_degenerate_pass_q[$], 19);
       // Constant-false: every attempt fails immediately.
-      `checkd(low_bounded_fail_q.size(), 20);
-      `checkd(low_degenerate_fail_q.size(), 20);
-      // CRC + disable streams: counts pinned (cross-checked against Questa).
+      `checkd(low_bounded_fail_q.size(), 20);  // Other sims: 19
+      `checkd(low_degenerate_fail_q.size(), 20);  // Other sims: 19
+      // CRC + disable streams
       `checkd(rand_bounded_pass_q.size(), 0);
-      `checkd(rand_bounded_fail_q.size(), 20);
+      `checkd(rand_bounded_fail_q.size(), 20);  // Other sims: 19, 11
       `checkd(disable_bounded_pass_q.size(), 0);
-      `checkd(disable_bounded_fail_q.size(), 13);
+      `checkd(disable_bounded_fail_q.size(), 13);  // Other sims: 5, 6
       $write("*-* All Finished *-*\n");
       $finish;
     end
diff --git a/test_regress/t/t_prop_followed_by.v b/test_regress/t/t_prop_followed_by.v
index c1e5778a6..6cc11045a 100644
--- a/test_regress/t/t_prop_followed_by.v
+++ b/test_regress/t/t_prop_followed_by.v
@@ -4,11 +4,10 @@
 // SPDX-FileCopyrightText: 2026 PlanV GmbH
 // SPDX-License-Identifier: CC0-1.0
 
-`define checkd(gotv, expv) \
-  do if ((gotv) !== (expv)) begin \
-    $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__, `__LINE__, (gotv), (expv)); \
-    $stop; \
-  end while (0);
+// verilog_format: off
+`define stop $stop
+`define checkd(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+// verilog_format: on
 
 module t (
     input clk
@@ -54,13 +53,11 @@ module t (
     cyc <= cyc + 1;
     crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
     if (cyc == 32) begin
-      // Counts are deterministic for this CRC seed. Questa reference run
-      // (IEEE 1800-2023 16.12.9) reports ovl=28, novl=19, impl=9, nimp=0; the
       // ovl/novl deltas vs Verilator are 1-cycle preponed-sampling differences.
       $display("ovl=%0d novl=%0d impl=%0d nimp=%0d wide=%0d", ovl_f, novl_f, impl_f, nimp_f,
                wide_f);
-      `checkd(ovl_f, 29);
-      `checkd(novl_f, 20);
+      `checkd(ovl_f, 29);  // Other sims: 28, one other sim: 5
+      `checkd(novl_f, 20);  // Other sims: 19
       `checkd(impl_f, 9);
       `checkd(nimp_f, 0);
       `checkd(wide_f, 0);
diff --git a/test_regress/t/t_property_accept_reject_on.v b/test_regress/t/t_property_accept_reject_on.v
index 1affe217c..080af892c 100644
--- a/test_regress/t/t_property_accept_reject_on.v
+++ b/test_regress/t/t_property_accept_reject_on.v
@@ -94,16 +94,16 @@ module t (
     end
     else if (cyc == 99) begin
       `checkh(crc, 64'hc77bb9b3784ea091);
-      `checkd(count_fail1, 28);  // Questa: 14
-      `checkd(count_fail2, 64);  // Questa: 64
-      `checkd(count_fail3, 28);  // Questa: 14
-      `checkd(count_fail4, 64);  // Questa: 64
-      `checkd(count_fail5, 45);  // Questa: 31
-      `checkd(count_fail6, 64);  // Questa: 59
-      `checkd(count_fail7, 28);  // Questa: 14
-      `checkd(count_fail8, 13);  // Questa: 10
-      `checkd(count_fail9, 28);  // Questa: 14
-      `checkd(count_fail10, 28);  // Questa: 14
+      `checkd(count_fail1, 28);  // Other sims: 14, one other: 15
+      `checkd(count_fail2, 64);  // One other sim: 66
+      `checkd(count_fail3, 28);  // Other sims: 14
+      `checkd(count_fail4, 64);
+      `checkd(count_fail5, 45);  // Other sims: 31, one other: 32
+      `checkd(count_fail6, 64);  // Other sims: 59, one other: 60
+      `checkd(count_fail7, 28);  // Other sims: 14, one other: 15
+      `checkd(count_fail8, 13);  // Other sims: 10
+      `checkd(count_fail9, 28);  // Other sims: 14, one other: 15
+      `checkd(count_fail10, 28);  // Other sims: 14
       $write("*-* All Finished *-*\n");
       $finish;
     end
diff --git a/test_regress/t/t_property_disable_iff_held.v b/test_regress/t/t_property_disable_iff_held.v
index 04530fc6e..37fa06461 100644
--- a/test_regress/t/t_property_disable_iff_held.v
+++ b/test_regress/t/t_property_disable_iff_held.v
@@ -46,20 +46,12 @@ module t (
     cyc <= cyc + 1;
     crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
     if (cyc == 99) begin
-      `checkd(n_held_assert, 0);  // Questa: 0
-      `checkd(n_held_cover, 0);  // Questa: 0
-      `checkd(n_ctrl_assert, 58);  // Questa: 58
-      `checkd(n_ctrl_cover, 26);  // Questa: 26
+      `checkd(n_held_assert, 0);
+      `checkd(n_held_cover, 0);
+      `checkd(n_ctrl_assert, 58);
+      `checkd(n_ctrl_cover, 26);  // Others: 26, One other: 0
       $write("*-* All Finished *-*\n");
       $finish;
     end
   end
 endmodule
-
-`ifndef VERILATOR
-module wrap;
-  logic clk = 0;
-  always #5 clk = ~clk;
-  t inst (.clk(clk));
-endmodule
-`endif
diff --git a/test_regress/t/t_property_until_implication.v b/test_regress/t/t_property_until_implication.v
index 6023ac501..2f345677f 100644
--- a/test_regress/t/t_property_until_implication.v
+++ b/test_regress/t/t_property_until_implication.v
@@ -50,12 +50,12 @@ module t (
       crc <= 64'h5aef0c8d_d70a4497;
     end
     else if (cyc == 99) begin
-      // Counts reflect NFA per-cycle reject aggregation, not Questa's
+      // Counts reflect NFA per-cycle reject aggregation, not some other sim's
       // per-attempt action_block firing; the two differ by a small constant
       // (see PR description for the model gap). Test is a regression for
       // "no internal error on `until` as |=> consequent" (issue #7548).
-      `checkd(fail_nonoverlap, 7);
-      `checkd(fail_overlap, 22);
+      `checkd(fail_nonoverlap, 7);  // Other sims: 8, one other: 7
+      `checkd(fail_overlap, 22);  // Other sims: 24, one other: 22
       $write("*-* All Finished *-*\n");
       $finish;
     end
diff --git a/test_regress/t/t_randsequence.v b/test_regress/t/t_randsequence.v
index 739178d02..7d00d9e15 100644
--- a/test_regress/t/t_randsequence.v
+++ b/test_regress/t/t_randsequence.v
@@ -7,8 +7,9 @@
 // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 // verilog_format: off
-`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
-`define check_range(gotv,minv,maxv) do if ((gotv) < (minv) || (gotv) > (maxv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d-%0d\n", `__FILE__,`__LINE__, (gotv), (minv), (maxv)); $stop; end while(0);
+`define stop $stop
+`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+`define check_range(gotv,minv,maxv) do if ((gotv) < (minv) || (gotv) > (maxv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d-%0d\n", `__FILE__,`__LINE__, (gotv), (minv), (maxv)); `stop; end while(0);
 `define check_within_30_percent(gotv,val) `check_range((gotv), (val) * 70 / 100, (val) * 130 / 100)
 // verilog_format: on
 
diff --git a/test_regress/t/t_randsequence_func.v b/test_regress/t/t_randsequence_func.v
index ac06220bc..2374251af 100644
--- a/test_regress/t/t_randsequence_func.v
+++ b/test_regress/t/t_randsequence_func.v
@@ -7,7 +7,8 @@
 // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 // verilog_format: off
-`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
+`define stop $stop
+`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
 // verilog_format: on
 
 module t;
diff --git a/test_regress/t/t_randsequence_randjoin.v b/test_regress/t/t_randsequence_randjoin.v
index 47bd297c2..d0d2febcd 100644
--- a/test_regress/t/t_randsequence_randjoin.v
+++ b/test_regress/t/t_randsequence_randjoin.v
@@ -7,8 +7,9 @@
 // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 // verilog_format: off
-`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
-`define check_range(gotv,minv,maxv) do if ((gotv) < (minv) || (gotv) > (maxv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d-%0d\n", `__FILE__,`__LINE__, (gotv), (minv), (maxv)); $stop; end while(0);
+`define stop $stop
+`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+`define check_range(gotv,minv,maxv) do if ((gotv) < (minv) || (gotv) > (maxv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d-%0d\n", `__FILE__,`__LINE__, (gotv), (minv), (maxv)); `stop; end while(0);
 `define check_within_30_percent(gotv,val) `check_range((gotv), (val) * 70 / 100, (val) * 130 / 100)
 // verilog_format: on
 
diff --git a/test_regress/t/t_randsequence_svtests.v b/test_regress/t/t_randsequence_svtests.v
index dd087d63b..b4c549148 100644
--- a/test_regress/t/t_randsequence_svtests.v
+++ b/test_regress/t/t_randsequence_svtests.v
@@ -4,7 +4,8 @@
 // SPDX-License-Identifier: ISC
 
 // verilog_format: off
-`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
+`define stop $stop
+`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
 // verilog_format: on
 
 module t;
diff --git a/test_regress/t/t_sequence_intersect_nevermatch.v b/test_regress/t/t_sequence_intersect_nevermatch.v
index 17887e184..38abde53a 100644
--- a/test_regress/t/t_sequence_intersect_nevermatch.v
+++ b/test_regress/t/t_sequence_intersect_nevermatch.v
@@ -5,7 +5,8 @@
 // SPDX-License-Identifier: CC0-1.0
 
 // verilog_format: off
-`define checkd(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
+`define stop $stop
+`define checkd(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
 // verilog_format: on
 
 module t (
@@ -51,7 +52,8 @@ module t (
   else f_dis <= f_dis + 1;
 
   final begin
-    `checkd(f_fix, 0);  // Questa: 0
-    `checkd(f_dis, 0);  // Questa: 0
+    // TODO need better non-zero test
+    `checkd(f_fix, 0);
+    `checkd(f_dis, 0);
   end
 endmodule
diff --git a/test_regress/t/t_sequence_intersect_varlen.v b/test_regress/t/t_sequence_intersect_varlen.v
index 402560af3..72eaa8601 100644
--- a/test_regress/t/t_sequence_intersect_varlen.v
+++ b/test_regress/t/t_sequence_intersect_varlen.v
@@ -5,7 +5,8 @@
 // SPDX-License-Identifier: CC0-1.0
 
 // verilog_format: off
-`define checkd(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
+`define stop $stop
+`define checkd(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
 // verilog_format: on
 
 module t (
@@ -25,7 +26,7 @@ module t (
   int f_collapse = 0;
   int f_over = 0;
 
-  always_ff @(posedge clk) begin
+  always @(posedge clk) begin
     cyc <= cyc + 1;
     crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
     if (cyc == 99) begin
@@ -63,9 +64,9 @@ module t (
   else f_over <= f_over + 1;
 
   final begin
-    `checkd(f_var, 7);  // Questa: 7
-    `checkd(f_ieee, 41);  // Questa: 41
-    `checkd(f_collapse, 0);  // Questa: 0
-    `checkd(f_over, 84);  // Questa: 84
+    `checkd(f_var, 7);
+    `checkd(f_ieee, 41);
+    `checkd(f_collapse, 0);
+    `checkd(f_over, 84);
   end
 endmodule
diff --git a/test_regress/t/t_sequence_sexpr_throughout.v b/test_regress/t/t_sequence_sexpr_throughout.v
index a2b17ef46..8b9fe3cfa 100644
--- a/test_regress/t/t_sequence_sexpr_throughout.v
+++ b/test_regress/t/t_sequence_sexpr_throughout.v
@@ -74,7 +74,7 @@ module t (
   // by the throughout-drop check.
   cover property (@(posedge clk) a throughout (b ##1 c));
 
-  always_ff @(posedge clk) begin
+  always @(posedge clk) begin
 `ifdef TEST_VERBOSE
     $write("[%0t] cyc==%0d crc=%x cond=%b a=%b b=%b c=%b\n",
            $time, cyc, crc, cond, a, b, c);
@@ -85,15 +85,15 @@ module t (
       crc <= 64'h5aef0c8d_d70a4497;
     end else if (cyc == 99) begin
       `checkh(crc, 64'hc77bb9b3784ea091);
-      `checkd(count_fail1, 28);  // Questa: 28
-      `checkd(count_fail2, 33);  // Questa: 33
-      `checkd(count_fail3, 31);  // Questa: 31
-      `checkd(count_fail4, 35);  // Questa: 35
+      `checkd(count_fail1, 28);
+      `checkd(count_fail2, 33);
+      `checkd(count_fail3, 31);
+      `checkd(count_fail4, 35);
       // count_fail5: NFA undercounts by 12; throughout+temporal-and first-step
       // rejection is a known limitation of the SAnd combiner architecture
       // (propagating isTopLevelStep causes double-counting; fix is future work).
-      `checkd(count_fail5, 25);  // Questa: 36
-      `checkd(count_fail6, 33);  // Questa: 33
+      `checkd(count_fail5, 25);  // All other sims: 36
+      `checkd(count_fail6, 33);
       $write("*-* All Finished *-*\n");
       $finish;
     end
diff --git a/test_regress/t/t_sequence_within.v b/test_regress/t/t_sequence_within.v
index dcffaae56..e8d73ad61 100644
--- a/test_regress/t/t_sequence_within.v
+++ b/test_regress/t/t_sequence_within.v
@@ -11,9 +11,6 @@
 // verilog_format: on
 
 // IEEE 1800-2023 16.9.10: seq1 within seq2
-// CRC-driven random stimulus. Each property has a counter; at cyc==99 we
-// `checkd` against Verilator's actual count and record the Questa golden
-// value in a trailing comment for cross-simulator reference.
 
 module t (
     input clk
@@ -93,7 +90,7 @@ module t (
 
   initial $assertvacuousoff;
 
-  always_ff @(posedge clk) begin
+  always @(posedge clk) begin
     cyc <= cyc + 1;
     crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
 
@@ -103,30 +100,20 @@ module t (
     else if (cyc == 99) begin
       `checkh(crc, 64'hc77bb9b3784ea091);
       // p1/p2/p5 use |->; the NFA currently fires the pass action on
-      // vacuous passes too, so counts are inflated vs. Questa. Pre-existing
+      // vacuous passes too, so counts are inflated vs. others. Pre-existing
       // engine-wide behavior, not within-specific.
-      `checkd(count_p1, 23);  // Questa: 23
-      `checkd(count_p2, 44);  // Questa: 44
-      `checkd(count_p3, 25);  // Questa: 20
-      `checkd(count_p4, 23);  // Questa: 22
-      `checkd(count_p5, 26);  // Questa: 26
-      `checkd(count_p6, 21);  // Questa: 16
-      `checkd(count_p7, 15);  // Questa: 9
-      `checkd(count_p8, 15);  // Questa: 4
-      `checkd(count_p9, 15);  // Questa: 10
-      `checkd(count_p10, 23);  // Questa: 15
+      `checkd(count_p1, 23);  // Other sims: 23, or 16
+      `checkd(count_p2, 44);  // Other sims: 44, or 21
+      `checkd(count_p3, 25);  // Other sims: 20
+      `checkd(count_p4, 23);  // Other sims: 22
+      `checkd(count_p5, 26);
+      `checkd(count_p6, 21);  // Other sims: 16
+      `checkd(count_p7, 15);  // Other sims: 9
+      `checkd(count_p8, 15);  // Other sims: 4
+      `checkd(count_p9, 15);  // Other sims: 10
+      `checkd(count_p10, 23);  // Other sims: 15
       $write("*-* All Finished *-*\n");
       $finish;
     end
   end
 endmodule
-
-// Harness for stand-alone simulators (e.g. QuestaSim). Verilator uses
-// test_regress's built-in clock shell and ignores this module.
-`ifndef VERILATOR
-module wrap;
-  logic clk = 0;
-  always #5 clk = ~clk;
-  t inst (.clk(clk));
-endmodule
-`endif
diff --git a/test_regress/t/t_sv_cpu.py b/test_regress/t/t_sv_cpu.py
index dcc41dab2..0eb062f2a 100755
--- a/test_regress/t/t_sv_cpu.py
+++ b/test_regress/t/t_sv_cpu.py
@@ -14,23 +14,22 @@ test.scenarios('simulator')
 # 22-Mar-2012: Modifications for this test contributed by Jeremy Bennett,
 # Embecosm.
 
-test.compile(
-    # Taken from the original VCS command line.
-    v_flags2=[
-        "t/t_sv_cpu_code/timescale.sv", "t/t_sv_cpu_code/program_h.sv",
-        "t/t_sv_cpu_code/pads_h.sv", "t/t_sv_cpu_code/ports_h.sv", "t/t_sv_cpu_code/pinout_h.sv",
-        "t/t_sv_cpu_code/genbus_if.sv", "t/t_sv_cpu_code/pads_if.sv", "t/t_sv_cpu_code/adrdec.sv",
-        "t/t_sv_cpu_code/pad_gpio.sv", "t/t_sv_cpu_code/pad_vdd.sv", "t/t_sv_cpu_code/pad_gnd.sv",
-        "t/t_sv_cpu_code/pads.sv", "t/t_sv_cpu_code/ports.sv", "t/t_sv_cpu_code/ac_dig.sv",
-        "t/t_sv_cpu_code/ac_ana.sv", "t/t_sv_cpu_code/ac.sv", "t/t_sv_cpu_code/cpu.sv",
-        "t/t_sv_cpu_code/chip.sv"
-    ],
-    vcs_flags2=["-R -sverilog +memcbk -y t/t_sv_cpu_code +libext+.sv+ +incdir+t/t_sv_cpu_code"],
-    verilator_flags2=[
-        "-y t/t_sv_cpu_code +libext+.sv+ +incdir+t/t_sv_cpu_code --top-module t",
-        "--timescale-override 1ns/1ps"
-    ],
-    iv_flags2=["-yt/t_sv_cpu_code -It/t_sv_cpu_code -Y.sv"])
+test.compile(v_flags2=[
+    "t/t_sv_cpu_code/timescale.sv", "t/t_sv_cpu_code/program_h.sv", "t/t_sv_cpu_code/pads_h.sv",
+    "t/t_sv_cpu_code/ports_h.sv", "t/t_sv_cpu_code/pinout_h.sv", "t/t_sv_cpu_code/genbus_if.sv",
+    "t/t_sv_cpu_code/pads_if.sv", "t/t_sv_cpu_code/adrdec.sv", "t/t_sv_cpu_code/pad_gpio.sv",
+    "t/t_sv_cpu_code/pad_vdd.sv", "t/t_sv_cpu_code/pad_gnd.sv", "t/t_sv_cpu_code/pads.sv",
+    "t/t_sv_cpu_code/ports.sv", "t/t_sv_cpu_code/ac_dig.sv", "t/t_sv_cpu_code/ac_ana.sv",
+    "t/t_sv_cpu_code/ac.sv", "t/t_sv_cpu_code/cpu.sv", "t/t_sv_cpu_code/chip.sv"
+],
+             vcs_flags2=[
+                 "-R -sverilog +memcbk -y t/t_sv_cpu_code +libext+.sv+ +incdir+t/t_sv_cpu_code"
+             ],
+             verilator_flags2=[
+                 "-y t/t_sv_cpu_code +libext+.sv+ +incdir+t/t_sv_cpu_code --top-module t",
+                 "--timescale-override 1ns/1ps"
+             ],
+             iv_flags2=["-yt/t_sv_cpu_code -It/t_sv_cpu_code -Y.sv"])
 
 test.execute()
 
diff --git a/test_regress/t/t_sys_file_scan_delay.v b/test_regress/t/t_sys_file_scan_delay.v
index f1db0a34e..efb4e4659 100644
--- a/test_regress/t/t_sys_file_scan_delay.v
+++ b/test_regress/t/t_sys_file_scan_delay.v
@@ -6,7 +6,7 @@
 
 // verilog_format: off
 `define stop $stop
-`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
 // verilog_format: on
 
 module t;
diff --git a/test_regress/t/t_tagged_case.out b/test_regress/t/t_tagged_case.out
index e7965a85d..edec504d1 100644
--- a/test_regress/t/t_tagged_case.out
+++ b/test_regress/t/t_tagged_case.out
@@ -11,142 +11,142 @@
 %Error-UNSUPPORTED: t/t_tagged_case.v:65:5: Unsupported: void (for tagged unions)
    65 |     void    Invalid;
       |     ^~~~
-%Error-UNSUPPORTED: t/t_tagged_case.v:71:5: Unsupported: void (for tagged unions)
-   71 |     void      Invalid;
+%Error-UNSUPPORTED: t/t_tagged_case.v:73:5: Unsupported: void (for tagged unions)
+   73 |     void      Invalid;
       |     ^~~~
-%Error-UNSUPPORTED: t/t_tagged_case.v:80:5: Unsupported: void (for tagged unions)
-   80 |     void      Invalid;
+%Error-UNSUPPORTED: t/t_tagged_case.v:82:5: Unsupported: void (for tagged unions)
+   82 |     void      Invalid;
       |     ^~~~
-%Error-UNSUPPORTED: t/t_tagged_case.v:87:5: Unsupported: void (for tagged unions)
-   87 |     void   Invalid;
+%Error-UNSUPPORTED: t/t_tagged_case.v:89:5: Unsupported: void (for tagged unions)
+   89 |     void   Invalid;
       |     ^~~~
-%Error-UNSUPPORTED: t/t_tagged_case.v:93:5: Unsupported: void (for tagged unions)
-   93 |     void  Invalid;
+%Error-UNSUPPORTED: t/t_tagged_case.v:95:5: Unsupported: void (for tagged unions)
+   95 |     void  Invalid;
       |     ^~~~
-%Error-UNSUPPORTED: t/t_tagged_case.v:102:5: Unsupported: void (for tagged unions)
-  102 |     void  Invalid;
+%Error-UNSUPPORTED: t/t_tagged_case.v:104:5: Unsupported: void (for tagged unions)
+  104 |     void  Invalid;
       |     ^~~~
-%Error-UNSUPPORTED: t/t_tagged_case.v:126:9: Unsupported: tagged union
-  126 |     v = tagged Invalid;
+%Error-UNSUPPORTED: t/t_tagged_case.v:128:9: Unsupported: tagged union
+  128 |     v = tagged Invalid;
       |         ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_case.v:128:5: Unsupported: case matches (for tagged union)
-  128 |     case (v) matches
+%Error-UNSUPPORTED: t/t_tagged_case.v:130:5: Unsupported: case matches (for tagged union)
+  130 |     case (v) matches
       |     ^~~~
-%Error-UNSUPPORTED: t/t_tagged_case.v:129:7: Unsupported: tagged union
-  129 |       tagged Invalid : result = 1;
+%Error-UNSUPPORTED: t/t_tagged_case.v:131:7: Unsupported: tagged union
+  131 |       tagged Invalid : result = 1;
       |       ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_case.v:130:7: Unsupported: tagged pattern
-  130 |       tagged Valid .n : result = n;
+%Error-UNSUPPORTED: t/t_tagged_case.v:132:7: Unsupported: tagged pattern
+  132 |       tagged Valid .n : result = n;
       |       ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_case.v:130:20: Unsupported: pattern variable
-  130 |       tagged Valid .n : result = n;
+%Error-UNSUPPORTED: t/t_tagged_case.v:132:20: Unsupported: pattern variable
+  132 |       tagged Valid .n : result = n;
       |                    ^
-%Error-UNSUPPORTED: t/t_tagged_case.v:135:9: Unsupported: tagged union
-  135 |     v = tagged Valid (123);
+%Error-UNSUPPORTED: t/t_tagged_case.v:137:9: Unsupported: tagged union
+  137 |     v = tagged Valid (123);
       |         ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_case.v:137:5: Unsupported: case matches (for tagged union)
-  137 |     case (v) matches
+%Error-UNSUPPORTED: t/t_tagged_case.v:139:5: Unsupported: case matches (for tagged union)
+  139 |     case (v) matches
       |     ^~~~
-%Error-UNSUPPORTED: t/t_tagged_case.v:138:7: Unsupported: tagged union
-  138 |       tagged Invalid : result = -1;
+%Error-UNSUPPORTED: t/t_tagged_case.v:140:7: Unsupported: tagged union
+  140 |       tagged Invalid : result = -1;
       |       ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_case.v:139:7: Unsupported: tagged pattern
-  139 |       tagged Valid .n : result = n;
+%Error-UNSUPPORTED: t/t_tagged_case.v:141:7: Unsupported: tagged pattern
+  141 |       tagged Valid .n : result = n;
       |       ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_case.v:139:20: Unsupported: pattern variable
-  139 |       tagged Valid .n : result = n;
+%Error-UNSUPPORTED: t/t_tagged_case.v:141:20: Unsupported: pattern variable
+  141 |       tagged Valid .n : result = n;
       |                    ^
-%Error-UNSUPPORTED: t/t_tagged_case.v:144:10: Unsupported: tagged union
-  144 |     wt = tagged Wide60 (60'hFEDCBA987654321);
+%Error-UNSUPPORTED: t/t_tagged_case.v:146:10: Unsupported: tagged union
+  146 |     wt = tagged Wide60 (60'hFEDCBA987654321);
       |          ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_case.v:146:5: Unsupported: case matches (for tagged union)
-  146 |     case (wt) matches
+%Error-UNSUPPORTED: t/t_tagged_case.v:148:5: Unsupported: case matches (for tagged union)
+  148 |     case (wt) matches
       |     ^~~~
-%Error-UNSUPPORTED: t/t_tagged_case.v:147:7: Unsupported: tagged union
-  147 |       tagged Invalid : wide60_result = 0;
+%Error-UNSUPPORTED: t/t_tagged_case.v:149:7: Unsupported: tagged union
+  149 |       tagged Invalid : wide60_result = 0;
       |       ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_case.v:148:7: Unsupported: tagged pattern
-  148 |       tagged Wide60 .w : wide60_result = w;
+%Error-UNSUPPORTED: t/t_tagged_case.v:150:7: Unsupported: tagged pattern
+  150 |       tagged Wide60 .w : wide60_result = w;
       |       ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_case.v:148:21: Unsupported: pattern variable
-  148 |       tagged Wide60 .w : wide60_result = w;
+%Error-UNSUPPORTED: t/t_tagged_case.v:150:21: Unsupported: pattern variable
+  150 |       tagged Wide60 .w : wide60_result = w;
       |                     ^
-%Error-UNSUPPORTED: t/t_tagged_case.v:154:10: Unsupported: tagged union
-  154 |     wt = tagged Wide90 (90'hDE_ADBEEFCA_FEBABE12_3456);
+%Error-UNSUPPORTED: t/t_tagged_case.v:158:10: Unsupported: tagged union
+  158 |     wt = tagged Wide90 (90'hDE_ADBEEFCA_FEBABE12_3456);
       |          ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_case.v:156:5: Unsupported: case matches (for tagged union)
-  156 |     case (wt) matches
+%Error-UNSUPPORTED: t/t_tagged_case.v:160:5: Unsupported: case matches (for tagged union)
+  160 |     case (wt) matches
       |     ^~~~
-%Error-UNSUPPORTED: t/t_tagged_case.v:157:7: Unsupported: tagged union
-  157 |       tagged Invalid : wide90_result = 0;
+%Error-UNSUPPORTED: t/t_tagged_case.v:161:7: Unsupported: tagged union
+  161 |       tagged Invalid : wide90_result = 0;
       |       ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_case.v:158:7: Unsupported: tagged pattern
-  158 |       tagged Wide90 .w : wide90_result = w;
+%Error-UNSUPPORTED: t/t_tagged_case.v:162:7: Unsupported: tagged pattern
+  162 |       tagged Wide90 .w : wide90_result = w;
       |       ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_case.v:158:21: Unsupported: pattern variable
-  158 |       tagged Wide90 .w : wide90_result = w;
+%Error-UNSUPPORTED: t/t_tagged_case.v:162:21: Unsupported: pattern variable
+  162 |       tagged Wide90 .w : wide90_result = w;
       |                     ^
-%Error-UNSUPPORTED: t/t_tagged_case.v:164:10: Unsupported: tagged union
-  164 |     wt = tagged Byte8NonZeroLSB (8'hA5);
+%Error-UNSUPPORTED: t/t_tagged_case.v:170:10: Unsupported: tagged union
+  170 |     wt = tagged Byte8NonZeroLSB (8'hA5);
       |          ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_case.v:166:5: Unsupported: case matches (for tagged union)
-  166 |     case (wt) matches
+%Error-UNSUPPORTED: t/t_tagged_case.v:172:5: Unsupported: case matches (for tagged union)
+  172 |     case (wt) matches
       |     ^~~~
-%Error-UNSUPPORTED: t/t_tagged_case.v:167:7: Unsupported: tagged pattern
-  167 |       tagged Byte8NonZeroLSB .b : result = b;
+%Error-UNSUPPORTED: t/t_tagged_case.v:173:7: Unsupported: tagged pattern
+  173 |       tagged Byte8NonZeroLSB .b : result = b;
       |       ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_case.v:167:30: Unsupported: pattern variable
-  167 |       tagged Byte8NonZeroLSB .b : result = b;
+%Error-UNSUPPORTED: t/t_tagged_case.v:173:30: Unsupported: pattern variable
+  173 |       tagged Byte8NonZeroLSB .b : result = b;
       |                              ^
-%Error-UNSUPPORTED: t/t_tagged_case.v:173:10: Unsupported: tagged union
-  173 |     wt = tagged Word32LittleEndian (32'hDEADBEEF);
+%Error-UNSUPPORTED: t/t_tagged_case.v:179:10: Unsupported: tagged union
+  179 |     wt = tagged Word32LittleEndian (32'hDEADBEEF);
       |          ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_case.v:175:5: Unsupported: case matches (for tagged union)
-  175 |     case (wt) matches
+%Error-UNSUPPORTED: t/t_tagged_case.v:181:5: Unsupported: case matches (for tagged union)
+  181 |     case (wt) matches
       |     ^~~~
-%Error-UNSUPPORTED: t/t_tagged_case.v:176:7: Unsupported: tagged pattern
-  176 |       tagged Word32LittleEndian .w : result = w;
+%Error-UNSUPPORTED: t/t_tagged_case.v:182:7: Unsupported: tagged pattern
+  182 |       tagged Word32LittleEndian .w : result = w;
       |       ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_case.v:176:33: Unsupported: pattern variable
-  176 |       tagged Word32LittleEndian .w : result = w;
+%Error-UNSUPPORTED: t/t_tagged_case.v:182:33: Unsupported: pattern variable
+  182 |       tagged Word32LittleEndian .w : result = w;
       |                                 ^
-%Error-UNSUPPORTED: t/t_tagged_case.v:182:10: Unsupported: tagged union
-  182 |     at = tagged Arr '{10, 20, 30, 40};
+%Error-UNSUPPORTED: t/t_tagged_case.v:188:10: Unsupported: tagged union
+  188 |     at = tagged Arr '{10, 20, 30, 40};
       |          ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_case.v:184:5: Unsupported: case matches (for tagged union)
-  184 |     case (at) matches
+%Error-UNSUPPORTED: t/t_tagged_case.v:190:5: Unsupported: case matches (for tagged union)
+  190 |     case (at) matches
       |     ^~~~
-%Error-UNSUPPORTED: t/t_tagged_case.v:185:7: Unsupported: tagged union
-  185 |       tagged Invalid : result = -1;
+%Error-UNSUPPORTED: t/t_tagged_case.v:191:7: Unsupported: tagged union
+  191 |       tagged Invalid : result = -1;
       |       ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_case.v:186:7: Unsupported: tagged pattern
-  186 |       tagged Scalar .s : result = s;
+%Error-UNSUPPORTED: t/t_tagged_case.v:192:7: Unsupported: tagged pattern
+  192 |       tagged Scalar .s : result = s;
       |       ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_case.v:186:21: Unsupported: pattern variable
-  186 |       tagged Scalar .s : result = s;
+%Error-UNSUPPORTED: t/t_tagged_case.v:192:21: Unsupported: pattern variable
+  192 |       tagged Scalar .s : result = s;
       |                     ^
-%Error-UNSUPPORTED: t/t_tagged_case.v:187:7: Unsupported: tagged pattern
-  187 |       tagged Arr .a : result = a[0] + a[1] + a[2] + a[3];
+%Error-UNSUPPORTED: t/t_tagged_case.v:193:7: Unsupported: tagged pattern
+  193 |       tagged Arr .a : result = a[0] + a[1] + a[2] + a[3];
       |       ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_case.v:187:18: Unsupported: pattern variable
-  187 |       tagged Arr .a : result = a[0] + a[1] + a[2] + a[3];
+%Error-UNSUPPORTED: t/t_tagged_case.v:193:18: Unsupported: pattern variable
+  193 |       tagged Arr .a : result = a[0] + a[1] + a[2] + a[3];
       |                  ^
-%Error-UNSUPPORTED: t/t_tagged_case.v:192:13: Unsupported: tagged union
-  192 |     instr = tagged Jmp (tagged JmpC '{2'd1, 10'd256});
+%Error-UNSUPPORTED: t/t_tagged_case.v:198:13: Unsupported: tagged union
+  198 |     instr = tagged Jmp (tagged JmpC '{2'd1, 10'd256});
       |             ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_case.v:192:25: Unsupported: tagged union
-  192 |     instr = tagged Jmp (tagged JmpC '{2'd1, 10'd256});
+%Error-UNSUPPORTED: t/t_tagged_case.v:198:25: Unsupported: tagged union
+  198 |     instr = tagged Jmp (tagged JmpC '{2'd1, 10'd256});
       |                         ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_case.v:194:5: Unsupported: case matches (for tagged union)
-  194 |     case (instr) matches
+%Error-UNSUPPORTED: t/t_tagged_case.v:200:5: Unsupported: case matches (for tagged union)
+  200 |     case (instr) matches
       |     ^~~~
-%Error-UNSUPPORTED: t/t_tagged_case.v:195:7: Unsupported: tagged pattern
-  195 |       tagged Add .* : result = -1;
+%Error-UNSUPPORTED: t/t_tagged_case.v:201:7: Unsupported: tagged pattern
+  201 |       tagged Add .* : result = -1;
       |       ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_case.v:195:18: Unsupported: pattern wildcard
-  195 |       tagged Add .* : result = -1;
+%Error-UNSUPPORTED: t/t_tagged_case.v:201:18: Unsupported: pattern wildcard
+  201 |       tagged Add .* : result = -1;
       |                  ^~
-%Error-UNSUPPORTED: t/t_tagged_case.v:196:7: Unsupported: tagged union
-  196 |       tagged Jmp (tagged JmpU .a) : result = a;
+%Error-UNSUPPORTED: t/t_tagged_case.v:202:7: Unsupported: tagged union
+  202 |       tagged Jmp (tagged JmpU .a) : result = a;
       |       ^~~~~~
 %Error: Exiting due to
diff --git a/test_regress/t/t_tagged_case.v b/test_regress/t/t_tagged_case.v
index a2ebf02fc..ebf466c59 100644
--- a/test_regress/t/t_tagged_case.v
+++ b/test_regress/t/t_tagged_case.v
@@ -63,7 +63,9 @@ module t;
   // Tagged union with chandle member
   typedef union tagged {
     void    Invalid;
+`ifndef QUESTA
     chandle Handle;
+`endif
   } ChandleType;
 
   // Tagged union with class reference member
@@ -148,7 +150,9 @@ module t;
       tagged Wide60 .w : wide60_result = w;
       default : wide60_result = 0;
     endcase
+`ifndef QUESTA
     `checkh(wide60_result, 60'hFEDCBA987654321);
+`endif
 
     // Test 4: Wide type case matching - 90-bit
     wt = tagged Wide90 (90'hDE_ADBEEFCA_FEBABE12_3456);
@@ -158,7 +162,9 @@ module t;
       tagged Wide90 .w : wide90_result = w;
       default : wide90_result = 0;
     endcase
+`ifndef QUESTA
     `checkh(wide90_result, 90'hDE_ADBEEFCA_FEBABE12_3456);
+`endif
 
     // Test 5: Non-zero LSB case match
     wt = tagged Byte8NonZeroLSB (8'hA5);
@@ -203,7 +209,9 @@ module t;
     result = 0;
     case (cht) matches
       tagged Invalid : result = 1;
+`ifndef QUESTA
       tagged Handle .* : result = 2;  // Wildcard - can't bind chandle
+`endif
     endcase
     `checkh(result, 1);
 
@@ -213,9 +221,9 @@ module t;
     result = 0;
     case (clt) matches
       tagged Invalid : result = -1;
-      tagged Obj .o : result = o.value;
+      tagged Obj : result = 2;
     endcase
-    `checkh(result, 42);
+    `checkh(result, 2);
 
     // Test 11: Real member case matching
     rt = tagged Invalid;
diff --git a/test_regress/t/t_tagged_if.out b/test_regress/t/t_tagged_if.out
index 31b7cc0bb..db7e619f6 100644
--- a/test_regress/t/t_tagged_if.out
+++ b/test_regress/t/t_tagged_if.out
@@ -1,14 +1,14 @@
-%Error-UNSUPPORTED: t/t_tagged_if.v:218:37: Unsupported: &&& expression
-  218 |     if (instr matches tagged Jmp .j &&&
+%Error-UNSUPPORTED: t/t_tagged_if.v:226:37: Unsupported: &&& expression
+  226 |     if (instr matches tagged Jmp .j &&&
       |                                     ^~~
                     ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
-%Error-UNSUPPORTED: t/t_tagged_if.v:228:35: Unsupported: &&& expression
-  228 |     if (v matches tagged Valid .n &&& (n > 50))
+%Error-UNSUPPORTED: t/t_tagged_if.v:236:35: Unsupported: &&& expression
+  236 |     if (v matches tagged Valid .n &&& (n > 50))
       |                                   ^~~
-%Error-UNSUPPORTED: t/t_tagged_if.v:237:35: Unsupported: &&& expression
-  237 |     if (v matches tagged Valid .n &&& (n > 50))
+%Error-UNSUPPORTED: t/t_tagged_if.v:245:35: Unsupported: &&& expression
+  245 |     if (v matches tagged Valid .n &&& (n > 50))
       |                                   ^~~
-%Error-UNSUPPORTED: t/t_tagged_if.v:266:37: Unsupported: &&& expression
-  266 |     if (instr matches tagged Jmp .j &&&
+%Error-UNSUPPORTED: t/t_tagged_if.v:274:37: Unsupported: &&& expression
+  274 |     if (instr matches tagged Jmp .j &&&
       |                                     ^~~
 %Error: Exiting due to
diff --git a/test_regress/t/t_tagged_if.v b/test_regress/t/t_tagged_if.v
index 46be66135..269219f9d 100644
--- a/test_regress/t/t_tagged_if.v
+++ b/test_regress/t/t_tagged_if.v
@@ -61,10 +61,12 @@ module t;
   } Instr;
 
   // Tagged union with chandle member
+`ifndef QUESTA
   typedef union tagged {
     void    Invalid;
     chandle Handle;
   } ChandleType;
+`endif
 
   // Tagged union with class reference member
   typedef union tagged {
@@ -108,7 +110,9 @@ module t;
   WideType wt;
   ArrayType at;
   Instr instr;
+`ifndef QUESTA
   ChandleType cht;
+`endif
   ClassType clt;
   TestClass obj;
   RealType rt;
@@ -156,7 +160,9 @@ module t;
       wide60_result = w;
     else
       wide60_result = 0;
+`ifndef QUESTA
     `checkh(wide60_result, 60'hFEDCBA987654321);
+`endif
 
     // Test 5: Wide type if matching - 90-bit
     wt = tagged Wide90 (90'hDE_ADBEEFCA_FEBABE12_3456);
@@ -165,7 +171,9 @@ module t;
       wide90_result = w;
     else
       wide90_result = 0;
+`ifndef QUESTA
     `checkh(wide90_result, 90'hDE_ADBEEFCA_FEBABE12_3456);
+`endif
 
     // Test 6: Non-zero LSB if match
     wt = tagged Byte8NonZeroLSB (8'hA5);
@@ -291,6 +299,7 @@ module t;
       result = 2;
     `checkh(result, 1);
 
+`ifndef QUESTA
     // Test 19: Chandle member if matching
     cht = tagged Invalid;
     result = 0;
@@ -307,6 +316,7 @@ module t;
     else
       result = 2;
     `checkh(result, 1);
+`endif
 
     // Test 20: Class reference member if matching
     obj = new(42);
@@ -320,8 +330,8 @@ module t;
 
     clt = tagged Obj (obj);
     result = 0;
-    if (clt matches tagged Obj .o)
-      result = o.value;
+    if (clt matches tagged Obj)
+      result = 42;
     else
       result = -1;
     `checkh(result, 42);
diff --git a/test_regress/t/t_tagged_union.out b/test_regress/t/t_tagged_union.out
index ab08889dc..d31a3fdfa 100644
--- a/test_regress/t/t_tagged_union.out
+++ b/test_regress/t/t_tagged_union.out
@@ -8,145 +8,145 @@
 %Error-UNSUPPORTED: t/t_tagged_union.v:57:5: Unsupported: void (for tagged unions)
    57 |     void           Invalid;
       |     ^~~~
-%Error-UNSUPPORTED: t/t_tagged_union.v:79:5: Unsupported: void (for tagged unions)
-   79 |     void    Invalid;
+%Error-UNSUPPORTED: t/t_tagged_union.v:80:5: Unsupported: void (for tagged unions)
+   80 |     void    Invalid;
       |     ^~~~
-%Error-UNSUPPORTED: t/t_tagged_union.v:85:5: Unsupported: void (for tagged unions)
-   85 |     void      Invalid;
+%Error-UNSUPPORTED: t/t_tagged_union.v:87:5: Unsupported: void (for tagged unions)
+   87 |     void      Invalid;
       |     ^~~~
-%Error-UNSUPPORTED: t/t_tagged_union.v:94:5: Unsupported: void (for tagged unions)
-   94 |     void      Invalid;
+%Error-UNSUPPORTED: t/t_tagged_union.v:96:5: Unsupported: void (for tagged unions)
+   96 |     void      Invalid;
       |     ^~~~
-%Error-UNSUPPORTED: t/t_tagged_union.v:101:5: Unsupported: void (for tagged unions)
-  101 |     void   Invalid;
+%Error-UNSUPPORTED: t/t_tagged_union.v:103:5: Unsupported: void (for tagged unions)
+  103 |     void   Invalid;
       |     ^~~~
-%Error-UNSUPPORTED: t/t_tagged_union.v:107:5: Unsupported: void (for tagged unions)
-  107 |     void  Invalid;
+%Error-UNSUPPORTED: t/t_tagged_union.v:109:5: Unsupported: void (for tagged unions)
+  109 |     void  Invalid;
       |     ^~~~
-%Error-UNSUPPORTED: t/t_tagged_union.v:116:5: Unsupported: void (for tagged unions)
-  116 |     void  Invalid;
+%Error-UNSUPPORTED: t/t_tagged_union.v:118:5: Unsupported: void (for tagged unions)
+  118 |     void  Invalid;
       |     ^~~~
-%Error-UNSUPPORTED: t/t_tagged_union.v:137:11: Unsupported: tagged union
-  137 |     vi1 = tagged Invalid;
-      |           ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_union.v:138:11: Unsupported: tagged union
-  138 |     vi2 = tagged Invalid;
-      |           ^~~~~~
 %Error-UNSUPPORTED: t/t_tagged_union.v:141:11: Unsupported: tagged union
-  141 |     vi1 = tagged Valid (42);
+  141 |     vi1 = tagged Invalid;
       |           ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_union.v:144:11: Unsupported: tagged union
-  144 |     vi2 = tagged Valid (23 + 34);
+%Error-UNSUPPORTED: t/t_tagged_union.v:142:11: Unsupported: tagged union
+  142 |     vi2 = tagged Invalid;
       |           ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_union.v:148:10: Unsupported: tagged union
-  148 |     mt = tagged Invalid;
+%Error-UNSUPPORTED: t/t_tagged_union.v:145:11: Unsupported: tagged union
+  145 |     vi1 = tagged Valid (42);
+      |           ^~~~~~
+%Error-UNSUPPORTED: t/t_tagged_union.v:148:11: Unsupported: tagged union
+  148 |     vi2 = tagged Valid (23 + 34);
+      |           ^~~~~~
+%Error-UNSUPPORTED: t/t_tagged_union.v:152:10: Unsupported: tagged union
+  152 |     mt = tagged Invalid;
       |          ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_union.v:150:10: Unsupported: tagged union
-  150 |     mt = tagged IntVal (32'h12345678);
+%Error-UNSUPPORTED: t/t_tagged_union.v:154:10: Unsupported: tagged union
+  154 |     mt = tagged IntVal (32'h12345678);
       |          ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_union.v:153:10: Unsupported: tagged union
-  153 |     mt = tagged ShortVal (16'hABCD);
+%Error-UNSUPPORTED: t/t_tagged_union.v:157:10: Unsupported: tagged union
+  157 |     mt = tagged ShortVal (16'hABCD);
       |          ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_union.v:156:10: Unsupported: tagged union
-  156 |     mt = tagged ByteVal (8'h5A);
-      |          ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_union.v:159:10: Unsupported: tagged union
-  159 |     mt = tagged BitVal (1'b1);
+%Error-UNSUPPORTED: t/t_tagged_union.v:160:10: Unsupported: tagged union
+  160 |     mt = tagged ByteVal (8'h5A);
       |          ^~~~~~
 %Error-UNSUPPORTED: t/t_tagged_union.v:163:10: Unsupported: tagged union
-  163 |     mt = tagged Byte8NonZeroLSB (8'hA5);
+  163 |     mt = tagged BitVal (1'b1);
       |          ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_union.v:166:10: Unsupported: tagged union
-  166 |     mt = tagged Word16NonZeroLSB (16'h1234);
+%Error-UNSUPPORTED: t/t_tagged_union.v:167:10: Unsupported: tagged union
+  167 |     mt = tagged Byte8NonZeroLSB (8'hA5);
       |          ^~~~~~
 %Error-UNSUPPORTED: t/t_tagged_union.v:170:10: Unsupported: tagged union
-  170 |     mt = tagged Word32LittleEndian (32'hDEADBEEF);
+  170 |     mt = tagged Word16NonZeroLSB (16'h1234);
       |          ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_union.v:173:10: Unsupported: tagged union
-  173 |     mt = tagged Word16LittleEndian (16'hCAFE);
+%Error-UNSUPPORTED: t/t_tagged_union.v:174:10: Unsupported: tagged union
+  174 |     mt = tagged Word32LittleEndian (32'hDEADBEEF);
       |          ^~~~~~
 %Error-UNSUPPORTED: t/t_tagged_union.v:177:10: Unsupported: tagged union
-  177 |     mt = tagged Wide60 (60'hFEDCBA987654321);
+  177 |     mt = tagged Word16LittleEndian (16'hCAFE);
       |          ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_union.v:180:10: Unsupported: tagged union
-  180 |     mt = tagged Wide60NonZeroLSB (60'h123456789ABCDEF);
+%Error-UNSUPPORTED: t/t_tagged_union.v:181:10: Unsupported: tagged union
+  181 |     mt = tagged Wide60 (60'hFEDCBA987654321);
       |          ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_union.v:183:10: Unsupported: tagged union
-  183 |     mt = tagged Wide60LittleEndian (60'hABCDEF012345678);
+%Error-UNSUPPORTED: t/t_tagged_union.v:184:10: Unsupported: tagged union
+  184 |     mt = tagged Wide60NonZeroLSB (60'h123456789ABCDEF);
       |          ^~~~~~
 %Error-UNSUPPORTED: t/t_tagged_union.v:187:10: Unsupported: tagged union
-  187 |     mt = tagged Wide90 (90'hFF_FFFFFFFF_FFFFFFFF_FFFF);
+  187 |     mt = tagged Wide60LittleEndian (60'hABCDEF012345678);
       |          ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_union.v:190:10: Unsupported: tagged union
-  190 |     mt = tagged Wide90NonZeroLSB (90'hDE_ADBEEFCA_FEBABE12_3456);
+%Error-UNSUPPORTED: t/t_tagged_union.v:191:10: Unsupported: tagged union
+  191 |     mt = tagged Wide90 (90'hFF_FFFFFFFF_FFFFFFFF_FFFF);
       |          ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_union.v:193:10: Unsupported: tagged union
-  193 |     mt = tagged Wide90LittleEndian (90'h11_11111122_22222233_3333);
+%Error-UNSUPPORTED: t/t_tagged_union.v:194:10: Unsupported: tagged union
+  194 |     mt = tagged Wide90NonZeroLSB (90'hDE_ADBEEFCA_FEBABE12_3456);
       |          ^~~~~~
 %Error-UNSUPPORTED: t/t_tagged_union.v:197:10: Unsupported: tagged union
-  197 |     at = tagged Invalid;
+  197 |     mt = tagged Wide90LittleEndian (90'h11_11111122_22222233_3333);
       |          ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_union.v:199:10: Unsupported: tagged union
-  199 |     at = tagged Scalar (999);
+%Error-UNSUPPORTED: t/t_tagged_union.v:201:10: Unsupported: tagged union
+  201 |     at = tagged Invalid;
       |          ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_union.v:202:10: Unsupported: tagged union
-  202 |     at = tagged UnpackedArr '{100, 200, 300, 400};
+%Error-UNSUPPORTED: t/t_tagged_union.v:203:10: Unsupported: tagged union
+  203 |     at = tagged Scalar (999);
       |          ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_union.v:208:10: Unsupported: tagged union
-  208 |     at = tagged UnpackedArr2D '{'{32'hA, 32'hB, 32'hC}, '{32'hD, 32'hE, 32'hF}};
+%Error-UNSUPPORTED: t/t_tagged_union.v:206:10: Unsupported: tagged union
+  206 |     at = tagged UnpackedArr '{100, 200, 300, 400};
       |          ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_union.v:217:13: Unsupported: tagged union
-  217 |     instr = tagged Add '{5'd1, 5'd2, 5'd3};
+%Error-UNSUPPORTED: t/t_tagged_union.v:212:10: Unsupported: tagged union
+  212 |     at = tagged UnpackedArr2D '{'{32'hA, 32'hB, 32'hC}, '{32'hD, 32'hE, 32'hF}};
+      |          ^~~~~~
+%Error-UNSUPPORTED: t/t_tagged_union.v:221:13: Unsupported: tagged union
+  221 |     instr = tagged Add '{5'd1, 5'd2, 5'd3};
       |             ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_union.v:223:13: Unsupported: tagged union
-  223 |     instr = tagged Add '{reg2:5'd10, regd:5'd20, reg1:5'd5};
+%Error-UNSUPPORTED: t/t_tagged_union.v:227:13: Unsupported: tagged union
+  227 |     instr = tagged Add '{reg2:5'd10, regd:5'd20, reg1:5'd5};
       |             ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_union.v:229:13: Unsupported: tagged union
-  229 |     instr = tagged Jmp (tagged JmpU 10'd512);
-      |             ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_union.v:229:25: Unsupported: tagged union
-  229 |     instr = tagged Jmp (tagged JmpU 10'd512);
-      |                         ^~~~~~
 %Error-UNSUPPORTED: t/t_tagged_union.v:233:13: Unsupported: tagged union
-  233 |     instr = tagged Jmp (tagged JmpC '{2'd1, 10'd256});
+  233 |     instr = tagged Jmp (tagged JmpU 10'd512);
       |             ^~~~~~
 %Error-UNSUPPORTED: t/t_tagged_union.v:233:25: Unsupported: tagged union
-  233 |     instr = tagged Jmp (tagged JmpC '{2'd1, 10'd256});
+  233 |     instr = tagged Jmp (tagged JmpU 10'd512);
       |                         ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_union.v:238:13: Unsupported: tagged union
-  238 |     instr = tagged Jmp (tagged JmpC '{cc:2'd3, addr:10'd100});
+%Error-UNSUPPORTED: t/t_tagged_union.v:237:13: Unsupported: tagged union
+  237 |     instr = tagged Jmp (tagged JmpC '{2'd1, 10'd256});
       |             ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_union.v:238:25: Unsupported: tagged union
-  238 |     instr = tagged Jmp (tagged JmpC '{cc:2'd3, addr:10'd100});
+%Error-UNSUPPORTED: t/t_tagged_union.v:237:25: Unsupported: tagged union
+  237 |     instr = tagged Jmp (tagged JmpC '{2'd1, 10'd256});
+      |                         ^~~~~~
+%Error-UNSUPPORTED: t/t_tagged_union.v:242:13: Unsupported: tagged union
+  242 |     instr = tagged Jmp (tagged JmpC '{cc:2'd3, addr:10'd100});
+      |             ^~~~~~
+%Error-UNSUPPORTED: t/t_tagged_union.v:242:25: Unsupported: tagged union
+  242 |     instr = tagged Jmp (tagged JmpC '{cc:2'd3, addr:10'd100});
       |                         ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_union.v:243:11: Unsupported: tagged union
-  243 |     cht = tagged Invalid;
-      |           ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_union.v:244:11: Unsupported: tagged union
-  244 |     cht = tagged Handle (null);
-      |           ^~~~~~
 %Error-UNSUPPORTED: t/t_tagged_union.v:248:11: Unsupported: tagged union
-  248 |     clt = tagged Invalid;
+  248 |     cht = tagged Invalid;
       |           ^~~~~~
 %Error-UNSUPPORTED: t/t_tagged_union.v:249:11: Unsupported: tagged union
-  249 |     clt = tagged Obj (obj);
+  249 |     cht = tagged Handle (null);
       |           ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_union.v:253:10: Unsupported: tagged union
-  253 |     rt = tagged Invalid;
+%Error-UNSUPPORTED: t/t_tagged_union.v:254:11: Unsupported: tagged union
+  254 |     clt = tagged Invalid;
+      |           ^~~~~~
+%Error-UNSUPPORTED: t/t_tagged_union.v:255:11: Unsupported: tagged union
+  255 |     clt = tagged Obj (obj);
+      |           ^~~~~~
+%Error-UNSUPPORTED: t/t_tagged_union.v:259:10: Unsupported: tagged union
+  259 |     rt = tagged Invalid;
       |          ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_union.v:254:10: Unsupported: tagged union
-  254 |     rt = tagged RealVal (3.14159);
+%Error-UNSUPPORTED: t/t_tagged_union.v:260:10: Unsupported: tagged union
+  260 |     rt = tagged RealVal (3.14159);
       |          ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_union.v:258:10: Unsupported: tagged union
-  258 |     rt = tagged ShortRealVal (2.5);
+%Error-UNSUPPORTED: t/t_tagged_union.v:264:10: Unsupported: tagged union
+  264 |     rt = tagged ShortRealVal (2.5);
       |          ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_union.v:262:10: Unsupported: tagged union
-  262 |     st = tagged Invalid;
+%Error-UNSUPPORTED: t/t_tagged_union.v:268:10: Unsupported: tagged union
+  268 |     st = tagged Invalid;
       |          ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_union.v:263:10: Unsupported: tagged union
-  263 |     st = tagged StrVal ("hello");
+%Error-UNSUPPORTED: t/t_tagged_union.v:269:10: Unsupported: tagged union
+  269 |     st = tagged StrVal ("hello");
       |          ^~~~~~
-%Error-UNSUPPORTED: t/t_tagged_union.v:267:10: Unsupported: tagged union
-  267 |     et = tagged Invalid;
+%Error-UNSUPPORTED: t/t_tagged_union.v:273:10: Unsupported: tagged union
+  273 |     et = tagged Invalid;
       |          ^~~~~~
 %Error: Exiting due to
diff --git a/test_regress/t/t_tagged_union.v b/test_regress/t/t_tagged_union.v
index 59642f503..4ce7fe866 100644
--- a/test_regress/t/t_tagged_union.v
+++ b/test_regress/t/t_tagged_union.v
@@ -75,10 +75,12 @@ module t;
   } Instr;
 
   // Tagged union with chandle member
+`ifndef QUESTA
   typedef union tagged {
     void    Invalid;
     chandle Handle;
   } ChandleType;
+`endif
 
   // Tagged union with class reference member
   typedef union tagged {
@@ -122,7 +124,9 @@ module t;
   MultiType mt;
   ArrayType at;
   Instr instr;
+`ifndef QUESTA
   ChandleType cht;
+`endif
   ClassType clt;
   TestClass obj;
   RealType rt;
@@ -239,9 +243,11 @@ module t;
     `checkh(instr.Jmp.JmpC.cc, 2'd3);
     `checkh(instr.Jmp.JmpC.addr, 10'd100);
 
+`ifndef QUESTA
     // Test 13: Chandle member
     cht = tagged Invalid;
     cht = tagged Handle (null);
+`endif
 
     // Test 14: Class reference member
     obj = new(42);
diff --git a/test_regress/t/t_vpi_force.v b/test_regress/t/t_vpi_force.v
index ae4913926..fcfa1b5fb 100644
--- a/test_regress/t/t_vpi_force.v
+++ b/test_regress/t/t_vpi_force.v
@@ -175,8 +175,7 @@ typedef enum byte {
   //   - Continuous assignments do not work
   //   - vpi_handle_by_multi_index is not implemented
   //   - vpi_handle_by_name and vpi_handle_by_index fail with negative indices
-  //  Hence, these signals are excluded from testing with Icarus. Recommend
-  //  Xcelium for cross-checking results.
+  //  Hence, these signals are excluded from testing with Icarus.
 `ifndef IVERILOG
   // Force the entire packed array (no partial forcing possible, because
   // partial indexing only works for bits, not dimension slices)
@@ -2422,10 +2421,8 @@ $dumpfile(`STRINGIFY(`TEST_DUMPFILE));
     svReleaseValues();
     #8 svCheckValuesReleased();
 
-    // Icarus does not support forcing single bits through VPI
-`ifndef IVERILOG
-    // Xcelium supports forcing single bits through VPI, but crashes on some signals
-`ifndef XRUN
+`ifndef IVERILOG  // Does not support forcing single bits through VPI
+`ifndef XRUN  // Supports forcing single bits through VPI, but crashes on some signals
 
     // Force single bit through VPI, release through VPI
     if (`verbose) $display("*** Forcing single bit through VPI, releasing through VPI ***");