diff --git a/test_regress/t/t_param_pattern2.py b/test_regress/t/t_param_pattern2.py
new file mode 100755
index 000000000..f989a35fb
--- /dev/null
+++ b/test_regress/t/t_param_pattern2.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile()
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_param_pattern2.v b/test_regress/t/t_param_pattern2.v
new file mode 100644
index 000000000..672b40fd2
--- /dev/null
+++ b/test_regress/t/t_param_pattern2.v
@@ -0,0 +1,21 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2021 by Ryszard Rozak.
+// SPDX-License-Identifier: CC0-1.0
+
+module dut(output int x);
+   parameter int P [5];
+   assign x = P[2];
+endmodule
+
+module t();
+   int o;
+   dut #(.P('{1, 2, 3, 4, 5})) u_dut(.x(o));
+
+   initial begin
+      if (o !== 3) $stop;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule