From 10e34ca48e27216b2b047b33768d7ab5d9e3b57f Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Wed, 31 Oct 2007 20:29:07 +0000 Subject: [PATCH] Support "#delay ;" with associated STMTDLY warning. git-svn-id: file://localhost/svn/verilator/trunk/verilator@965 77ca24e4-aefa-0310-84f0-b9a241c72d87 --- Changes | 2 ++ bin/verilator | 10 ++++++++++ src/V3Error.h | 3 ++- src/verilog.y | 13 ++++++++----- test_regress/t/t_delay.pl | 3 ++- test_regress/t/t_delay.v | 4 ++-- test_regress/t/t_delay_stmtdly_bad.pl | 20 ++++++++++++++++++++ 7 files changed, 46 insertions(+), 9 deletions(-) create mode 100755 test_regress/t/t_delay_stmtdly_bad.pl diff --git a/Changes b/Changes index e41de2bd7..b38a7d12e 100644 --- a/Changes +++ b/Changes @@ -5,6 +5,8 @@ indicates the contributor was also the author of the fix; Thanks! * Verilator 3.65**** +*** Support "#delay ;" with associated STMTDLY warning. + **** Fix divide-by-zero errors in constant propagator. [Rodney Sinclair] **** Fix wrong result with obscure signed-shift underneath a "? :". diff --git a/bin/verilator b/bin/verilator index 6952c81b4..4e8bfb5c6 100755 --- a/bin/verilator +++ b/bin/verilator @@ -1718,6 +1718,16 @@ not really needed. The best solution is to insure that each module is in a unique file by the same name. Otherwise, make sure all library files are read in as libraries with -v, instead of automatically with -y. +=item STMTDLY + +Warns that you have a statement with a delayed time in front of it, for +example: + + #100 $finish; + +Ignoring this warning may make Verilator simulations differ from other +simulators. + =item TASKNSVAR Error when a call to a task or function has a output from that task tied to diff --git a/src/V3Error.h b/src/V3Error.h index ef569c953..3e5c5cc2a 100644 --- a/src/V3Error.h +++ b/src/V3Error.h @@ -48,6 +48,7 @@ public: CASEX, // Casex CMPCONST, // Comparison is constant due to limited range COMBDLY, // Combinatorial delayed assignment + STMTDLY, // Delayed statement GENCLK, // Generated Clock IMPLICIT, // Implicit wire IMPURE, // Impure function not being inlined @@ -76,7 +77,7 @@ public: " FIRST_WARN", "BLKANDNBLK", "CASEINCOMPLETE", "CASEOVERLAP", "CASEX", "CMPCONST", - "COMBDLY", "GENCLK", "IMPLICIT", "IMPURE", + "COMBDLY", "STMTDLY", "GENCLK", "IMPLICIT", "IMPURE", "MULTIDRIVEN", "UNDRIVEN", "UNOPT", "UNOPTFLAT", "UNSIGNED", "UNUSED", "VARHIDDEN", "WIDTH", diff --git a/src/verilog.y b/src/verilog.y index 2d31d0758..587ab68bd 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -284,7 +284,7 @@ class AstSenTree; %token yPSL_BRA "{" %token yPSL_KET "}" -%token ';' '=' ',' '(' '.' '!' '~' '[' '@' +%token ';' '=' ',' '(' '.' '!' '~' '[' '@' '#' // [* is not a operator, as "[ * ]" is legal // [= and [-> could be repitition operators, but to match [* we don't add them. @@ -332,6 +332,7 @@ class AstSenTree; %type generateRegion %type genItem genItemList genItemBegin genItemBlock genTopBlock genCaseListE genCaseList %type dlyTerm +%type delay %type sigAndAttr sigId sigIdRange sigList regsig regsigList regSigId %type netSig netSigList %type rangeListE regrangeE anyrange rangeList delayrange portRangeE @@ -639,10 +640,10 @@ delayE: /* empty */ { } | delay { } /* ignored */ ; -delay: '#' dlyTerm { } /* ignored */ - | '#' '(' dlyInParen ')' { } /* ignored */ - | '#' '(' dlyInParen ',' dlyInParen ')' { } /* ignored */ - | '#' '(' dlyInParen ',' dlyInParen ',' dlyInParen ')' { } /* ignored */ +delay: '#' dlyTerm { $$ = $1; } /* ignored */ + | '#' '(' dlyInParen ')' { $$ = $1; } /* ignored */ + | '#' '(' dlyInParen ',' dlyInParen ')' { $$ = $1; } /* ignored */ + | '#' '(' dlyInParen ',' dlyInParen ',' dlyInParen ')' { $$ = $1; } /* ignored */ ; dlyTerm: yaID { $$ = NULL; } @@ -829,6 +830,8 @@ stmt: ';' { $$ = NULL; } | labeledStmt { $$ = $1; } | yaID ':' labeledStmt { $$ = new AstBegin($2, *$1, $3); } /*S05 block creation rule*/ + | delay stmtBlock { $$ = $2; $1->v3warn(STMTDLY,"Ignoring delay on this delayed statement.\n"); } + | varRefDotBit yP_LTE delayE expr ';' { $$ = new AstAssignDly($2,$1,$4); } | varRefDotBit '=' delayE expr ';' { $$ = new AstAssign($2,$1,$4); } | varRefDotBit '=' yD_FOPEN '(' expr ',' expr ')' ';' { $$ = new AstFOpen($3,$1,$5,$7); } diff --git a/test_regress/t/t_delay.pl b/test_regress/t/t_delay.pl index 9a7e1014a..03c734192 100755 --- a/test_regress/t/t_delay.pl +++ b/test_regress/t/t_delay.pl @@ -1,6 +1,6 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ +# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can @@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } # General Public License or the Perl Artistic License. compile ( + v_flags2 => [$Last_Self->{v3}?'-Wno-STMTDLY':''], ); execute ( diff --git a/test_regress/t/t_delay.v b/test_regress/t/t_delay.v index 98f681a13..9975014e7 100644 --- a/test_regress/t/t_delay.v +++ b/test_regress/t/t_delay.v @@ -1,4 +1,4 @@ -// $Id:$ +// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -30,7 +30,7 @@ module t (/*AUTOARG*/ else if (cyc==3) begin if (dly0 !== 32'h23) $stop; $write("*-* All Finished *-*\n"); - $finish; + #100 $finish; end end diff --git a/test_regress/t/t_delay_stmtdly_bad.pl b/test_regress/t/t_delay_stmtdly_bad.pl new file mode 100755 index 000000000..b11fce807 --- /dev/null +++ b/test_regress/t/t_delay_stmtdly_bad.pl @@ -0,0 +1,20 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } +# $Id$ +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# General Public License or the Perl Artistic License. + +top_filename("t/t_delay.v"); + +compile ( + fails=>1, + expect=> +'%Warning-STMTDLY: t/t_delay.v:\d+: Ignoring delay on this delayed statement. +.*%Error: Exiting due to.*', + ) if $Last_Self->{v3}; + +ok(1); +1;