diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index 14a72ca74..1c7e0cb0b 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -3188,6 +3188,10 @@ class WidthVisitor final : public VNVisitor {
                                       nodep->name(), withp};
             newp->dtypeFrom(adtypep);
             if (!nodep->firstAbovep()) newp->dtypeSetVoid();
+        } else if (nodep->name() == "map") {
+            nodep->v3warn(E_UNSUPPORTED,
+                          "Unsupported: Wildcard array 'map' method (IEEE 1800-2023 7.12.5)");
+            nodep->dtypeFrom(adtypep->subDTypep());  // Best guess
         } else {
             nodep->v3error("Unknown wildcard associative array method " << nodep->prettyNameQ());
             nodep->dtypeFrom(adtypep->subDTypep());  // Best guess
@@ -3287,6 +3291,10 @@ class WidthVisitor final : public VNVisitor {
                                       nodep->name(), withp};
             newp->dtypep(queueDTypeIndexedBy(adtypep->keyDTypep()));
             if (!nodep->firstAbovep()) newp->dtypeSetVoid();
+        } else if (nodep->name() == "map") {
+            nodep->v3warn(E_UNSUPPORTED,
+                          "Unsupported: Associative array 'map' method (IEEE 1800-2023 7.12.5)");
+            nodep->dtypeFrom(adtypep->subDTypep());  // Best guess
         } else {
             nodep->v3error("Unknown built-in associative array method " << nodep->prettyNameQ());
             nodep->dtypeFrom(adtypep->subDTypep());  // Best guess
@@ -3379,6 +3387,10 @@ class WidthVisitor final : public VNVisitor {
                                       nodep->name(), withp};
             newp->dtypep(newp->findQueueIndexDType());
             if (!nodep->firstAbovep()) newp->dtypeSetVoid();
+        } else if (nodep->name() == "map") {
+            nodep->v3warn(E_UNSUPPORTED,
+                          "Unsupported: Array 'map' method (IEEE 1800-2023 7.12.5)");
+            nodep->dtypeFrom(adtypep->subDTypep());  // Best guess
         }
         return newp;
     }
diff --git a/test_regress/t/t_array_method_map.out b/test_regress/t/t_array_method_map.out
new file mode 100644
index 000000000..62e0a3186
--- /dev/null
+++ b/test_regress/t/t_array_method_map.out
@@ -0,0 +1,10 @@
+%Error-UNSUPPORTED: t/t_array_method_map.v:17:15: Unsupported: Array 'map' method (IEEE 1800-2023 7.12.5)
+                                                : ... note: In instance 't'
+   17 |       res = a.map(el) with (el == 200);
+      |               ^~~
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Error: t/t_array_method_map.v:17:15: Unknown built-in array method 'map'
+                                    : ... note: In instance 't'
+   17 |       res = a.map(el) with (el == 200);
+      |               ^~~
+%Error: Exiting due to
diff --git a/test_regress/t/t_array_method_map.pl b/test_regress/t/t_array_method_map.pl
new file mode 100755
index 000000000..bd07fc421
--- /dev/null
+++ b/test_regress/t/t_array_method_map.pl
@@ -0,0 +1,23 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2023 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    fails => $Self->{vlt_all},
+    expect_filename => $Self->{golden_filename},
+    );
+
+execute(
+    check_finished => 1,
+    ) if !$Self->{vlt_all};
+
+ok(1);
+1;
diff --git a/test_regress/t/t_array_method_map.v b/test_regress/t/t_array_method_map.v
new file mode 100644
index 000000000..6f92b158b
--- /dev/null
+++ b/test_regress/t/t_array_method_map.v
@@ -0,0 +1,23 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2024 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+`define stop $stop
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
+
+module t (/*AUTOARG*/);
+
+   initial begin
+      int res[];
+      int a[3] = '{100, 200, 300};
+
+      // TODO results not known to be correct
+      res = a.map(el) with (el == 200);
+      `checkh(res.size, 3);
+      `checkh(res[0], 0);
+      `checkh(res[1], 1);
+      `checkh(res[2], 0);
+   end
+endmodule
diff --git a/test_regress/t/t_assoc_method_map.out b/test_regress/t/t_assoc_method_map.out
new file mode 100644
index 000000000..61d553d8b
--- /dev/null
+++ b/test_regress/t/t_assoc_method_map.out
@@ -0,0 +1,6 @@
+%Error-UNSUPPORTED: t/t_assoc_method_map.v:17:15: Unsupported: Associative array 'map' method (IEEE 1800-2023 7.12.5)
+                                                : ... note: In instance 't'
+   17 |       res = a.map(el) with (el == 2);
+      |               ^~~
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Error: Exiting due to
diff --git a/test_regress/t/t_assoc_method_map.pl b/test_regress/t/t_assoc_method_map.pl
new file mode 100755
index 000000000..63947fd00
--- /dev/null
+++ b/test_regress/t/t_assoc_method_map.pl
@@ -0,0 +1,19 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2019 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+lint(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_assoc_method_map.v b/test_regress/t/t_assoc_method_map.v
new file mode 100644
index 000000000..4ccf66cbb
--- /dev/null
+++ b/test_regress/t/t_assoc_method_map.v
@@ -0,0 +1,23 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2024 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+`define stop $stop
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
+
+module t (/*AUTOARG*/);
+
+   initial begin
+      int res[];
+      int a[int] = '{1: 100, 2: 200, 3: 300};
+
+      // TODO results not known to be correct
+      res = a.map(el) with (el == 2);
+      `checkh(res.size, 3);
+      `checkh(res[0], 0);
+      `checkh(res[1], 1);
+      `checkh(res[2], 0);
+   end
+endmodule
diff --git a/test_regress/t/t_assoc_wildcard_map.out b/test_regress/t/t_assoc_wildcard_map.out
new file mode 100644
index 000000000..aa3a972bb
--- /dev/null
+++ b/test_regress/t/t_assoc_wildcard_map.out
@@ -0,0 +1,6 @@
+%Error-UNSUPPORTED: t/t_assoc_wildcard_map.v:17:15: Unsupported: Wildcard array 'map' method (IEEE 1800-2023 7.12.5)
+                                                  : ... note: In instance 't'
+   17 |       res = a.map(el) with (el == 2);
+      |               ^~~
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Error: Exiting due to
diff --git a/test_regress/t/t_assoc_wildcard_map.pl b/test_regress/t/t_assoc_wildcard_map.pl
new file mode 100755
index 000000000..63947fd00
--- /dev/null
+++ b/test_regress/t/t_assoc_wildcard_map.pl
@@ -0,0 +1,19 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2019 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+lint(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_assoc_wildcard_map.v b/test_regress/t/t_assoc_wildcard_map.v
new file mode 100644
index 000000000..3ab61e1df
--- /dev/null
+++ b/test_regress/t/t_assoc_wildcard_map.v
@@ -0,0 +1,23 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2023 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+`define stop $stop
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
+
+module t (/*AUTOARG*/);
+
+   initial begin
+      int res[];
+      int a [*] = '{1: 100, 2: 200, 3: 300};
+
+      // TODO results not known to be correct
+      res = a.map(el) with (el == 2);
+      `checkh(res.size, 3);
+      `checkh(res[0], 0);
+      `checkh(res[1], 1);
+      `checkh(res[2], 0);
+   end
+endmodule