diff --git a/bin/verilator b/bin/verilator index 31879c192..b886d5b40 100755 --- a/bin/verilator +++ b/bin/verilator @@ -4740,6 +4740,34 @@ Warns that an instance has a pin which is not connected to another signal. Disabled by default as this is a code style warning; it will simulate correctly. +=item PINNOTFOUND + +Warns that an instance port or Parameter was not found in the module being +instanciated. Please note that Verilator raises these errors also on instances +that should be disabled by generate/if/endgenerate constructs: + + module a; + localparam A=1; + generate + if (A==0) begin + b b_inst1 (.x(1'b0)); // nonexistent port + b #(.PX(1'b0)) b_inst2 (); // nonexistent parameter + end + endgenerate + endmodule + + module b; + endmodule + +In the example above, b is instantiated with a port named x, but module b has +no such port. In the next line, b is instantiated again with +a nonexistent parameter PX. Technically, this code is incorrect because of +this, but other tools may ignore it because module b is not instantiated +due to the generate/if condition being false. + +It is possible to disable the error above using: +/* verilator lint_off PINNOTFOUND */ + =item PKGNODECL Error that a package/class appears to have been referenced that has not yet diff --git a/docs/CONTRIBUTORS b/docs/CONTRIBUTORS index cc4c8292c..a85ea0582 100644 --- a/docs/CONTRIBUTORS +++ b/docs/CONTRIBUTORS @@ -82,6 +82,7 @@ Tobias Wölfel Todd Strader Tomasz Gorochowik Tymoteusz Blazejczyk +Udi Finkelstein Unai Martinez-Corral Vassilis Papaefstathiou Veripool API Bot diff --git a/src/V3Error.h b/src/V3Error.h index eb3ec178d..100573296 100644 --- a/src/V3Error.h +++ b/src/V3Error.h @@ -101,9 +101,10 @@ public: MULTIDRIVEN, // Driven from multiple blocks MULTITOP, // Multiple top level modules NOLATCH, // No latch detected in always_latch block + PINCONNECTEMPTY,// Cell pin connected by name with empty reference PINMISSING, // Cell pin not specified PINNOCONNECT, // Cell pin not connected - PINCONNECTEMPTY,// Cell pin connected by name with empty reference + PINNOTFOUND, // instance port name not found in it's module PKGNODECL, // Error: Package/class needs to be predeclared PROCASSWIRE, // Procedural assignment on wire RANDC, // Unsupported: 'randc' converted to 'rand' @@ -166,8 +167,8 @@ public: "IMPERFECTSCH", "IMPLICIT", "IMPORTSTAR", "IMPURE", "INCABSPATH", "INFINITELOOP", "INITIALDLY", "INSECURE", "LATCH", "LITENDIAN", "MODDUP", - "MULTIDRIVEN", "MULTITOP","NOLATCH", - "PINMISSING", "PINNOCONNECT", "PINCONNECTEMPTY", "PKGNODECL", "PROCASSWIRE", + "MULTIDRIVEN", "MULTITOP","NOLATCH", "PINCONNECTEMPTY", + "PINMISSING", "PINNOCONNECT", "PINNOTFOUND", "PKGNODECL", "PROCASSWIRE", "RANDC", "REALCVT", "REDEFMACRO", "SELRANGE", "SHORTREAL", "SPLITVAR", "STMTDLY", "SYMRSVDWORD", "SYNCASYNCNET", "TICKCOUNT", "TIMESCALEMOD", @@ -190,7 +191,8 @@ public: // Later -Werror- options may make more of these. bool pretendError() const { return (m_e == ASSIGNIN || m_e == BLKANDNBLK || m_e == BLKLOOPINIT || m_e == CONTASSREG - || m_e == IMPURE || m_e == PKGNODECL || m_e == PROCASSWIRE); // Says IEEE + || m_e == IMPURE || m_e == PINNOTFOUND || m_e == PKGNODECL + || m_e == PROCASSWIRE); // Says IEEE } // Warnings to mention manual bool mentionManual() const { diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp index 6bc5d26ea..d5d5d0748 100644 --- a/src/V3LinkDot.cpp +++ b/src/V3LinkDot.cpp @@ -2023,9 +2023,10 @@ private: LinkNodeMatcherVarParam()) : m_statep->suggestSymFlat(m_pinSymp, nodep->name(), LinkNodeMatcherVarIO())); - nodep->v3error(ucfirst(whatp) - << " not found: " << nodep->prettyNameQ() << '\n' - << (suggest.empty() ? "" : nodep->warnMore() + suggest)); + nodep->v3warn(PINNOTFOUND, + ucfirst(whatp) + << " not found: " << nodep->prettyNameQ() << '\n' + << (suggest.empty() ? "" : nodep->warnMore() + suggest)); } else if (AstVar* refp = VN_CAST(foundp->nodep(), Var)) { if (!refp->isIO() && !refp->isParam() && !refp->isIfaceRef()) { nodep->v3error(ucfirst(whatp) << " is not an in/out/inout/param/interface: " diff --git a/test_regress/t/t_class_param_bad.out b/test_regress/t/t_class_param_bad.out index 20b89cfa7..83375ea19 100644 --- a/test_regress/t/t_class_param_bad.out +++ b/test_regress/t/t_class_param_bad.out @@ -1,8 +1,8 @@ -%Error: t/t_class_param_bad.v:12:11: Parameter pin not found: 'PARAMBAD' - : ... Suggested alternative: 'PARAMB' +%Error-PINNOTFOUND: t/t_class_param_bad.v:12:11: Parameter pin not found: 'PARAMBAD' + : ... Suggested alternative: 'PARAMB' 12 | Cls #(.PARAMBAD(1)) c; | ^~~~~~~~ -%Error: t/t_class_param_bad.v:13:14: Parameter pin not found: '__paramNumber2' +%Error-PINNOTFOUND: t/t_class_param_bad.v:13:14: Parameter pin not found: '__paramNumber2' 13 | Cls #(13, 1) cd; | ^ %Error: Exiting due to diff --git a/test_regress/t/t_lint_pindup_bad.out b/test_regress/t/t_lint_pindup_bad.out index 0e4832769..a34830565 100644 --- a/test_regress/t/t_lint_pindup_bad.out +++ b/test_regress/t/t_lint_pindup_bad.out @@ -8,12 +8,12 @@ t/t_lint_pindup_bad.v:20:10: ... Location of original pin connection 20 | .i(i), | ^ -%Error: t/t_lint_pindup_bad.v:22:10: Pin not found: 'nexist' - : ... Suggested alternative: 'exists' +%Error-PINNOTFOUND: t/t_lint_pindup_bad.v:22:10: Pin not found: 'nexist' + : ... Suggested alternative: 'exists' 22 | .nexist(i2) | ^~~~~~ -%Error: t/t_lint_pindup_bad.v:16:9: Parameter pin not found: 'NEXIST' - : ... Suggested alternative: 'EXIST' +%Error-PINNOTFOUND: t/t_lint_pindup_bad.v:16:9: Parameter pin not found: 'NEXIST' + : ... Suggested alternative: 'EXIST' 16 | .NEXIST(1), | ^~~~~~ %Error: t/t_lint_pindup_bad.v:17:9: Duplicate parameter pin connection: 'P' diff --git a/test_regress/t/t_lint_pinnotfound.pl b/test_regress/t/t_lint_pinnotfound.pl new file mode 100755 index 000000000..7314796b8 --- /dev/null +++ b/test_regress/t/t_lint_pinnotfound.pl @@ -0,0 +1,13 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +lint( + ); + +ok(1); +1; diff --git a/test_regress/t/t_lint_pinnotfound.v b/test_regress/t/t_lint_pinnotfound.v new file mode 100644 index 000000000..63f611b10 --- /dev/null +++ b/test_regress/t/t_lint_pinnotfound.v @@ -0,0 +1,20 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +/* verilator lint_off PINNOTFOUND */ +module a; +localparam A=1; +generate +if (A==0) +begin +b b_inst1 (.x(1'b0)); // nonexistent port +b #(.PX(1'b0)) b_inst2 (); // nonexistent parameter +end +endgenerate +endmodule + +module b; +endmodule diff --git a/test_regress/t/t_lint_pinnotfound_bad.out b/test_regress/t/t_lint_pinnotfound_bad.out new file mode 100644 index 000000000..e10eaa161 --- /dev/null +++ b/test_regress/t/t_lint_pinnotfound_bad.out @@ -0,0 +1,7 @@ +%Error-PINNOTFOUND: t/t_lint_pinnotfound_bad.v:12:13: Pin not found: 'x' + 12 | b b_inst1 (.x(1'b0)); + | ^ +%Error-PINNOTFOUND: t/t_lint_pinnotfound_bad.v:13:6: Parameter pin not found: 'PX' + 13 | b #(.PX(1'b0)) b_inst2 (); + | ^~ +%Error: Exiting due to diff --git a/test_regress/t/t_lint_pinnotfound_bad.pl b/test_regress/t/t_lint_pinnotfound_bad.pl new file mode 100755 index 000000000..a60503a1f --- /dev/null +++ b/test_regress/t/t_lint_pinnotfound_bad.pl @@ -0,0 +1,19 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(linter => 1); + +lint( + fails => 1, + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_lint_pinnotfound_bad.v b/test_regress/t/t_lint_pinnotfound_bad.v new file mode 100644 index 000000000..c7128a41a --- /dev/null +++ b/test_regress/t/t_lint_pinnotfound_bad.v @@ -0,0 +1,19 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module a; +localparam A=1; +generate +if (A==0) +begin +b b_inst1 (.x(1'b0)); // nonexistent port +b #(.PX(1'b0)) b_inst2 (); // nonexistent parameter +end +endgenerate +endmodule + +module b; +endmodule