diff --git a/src/V3Inst.cpp b/src/V3Inst.cpp index b9d8f6d90..cf3906851 100644 --- a/src/V3Inst.cpp +++ b/src/V3Inst.cpp @@ -320,7 +320,7 @@ private: if (!nodep->exprp()) return; // No-connect if (m_cellRangep) { UINFO(4, " PIN " << nodep << endl); - const int pinwidth = nodep->modVarp()->width(); + const int modwidth = nodep->modVarp()->width(); const int expwidth = nodep->exprp()->width(); const std::pair pinDim = nodep->modVarp()->dtypep()->dimensions(false); @@ -328,7 +328,7 @@ private: = nodep->exprp()->dtypep()->dimensions(false); UINFO(4, " PINVAR " << nodep->modVarp() << endl); UINFO(4, " EXP " << nodep->exprp() << endl); - UINFO(4, " pinwidth ew=" << expwidth << " pw=" << pinwidth << " ed=" << expDim.first + UINFO(4, " modwidth ew=" << expwidth << " pw=" << modwidth << " ed=" << expDim.first << "," << expDim.second << " pd=" << pinDim.first << "," << pinDim.second << endl); if (expDim.first == pinDim.first && expDim.second == pinDim.second + 1) { @@ -341,11 +341,11 @@ private: AstNode* exprp = nodep->exprp()->unlinkFrBack(); exprp = new AstArraySel(exprp->fileline(), exprp, arraySelNum); nodep->exprp(exprp); - } else if (expwidth == pinwidth) { + } else if (expwidth == modwidth) { // NOP: Arrayed instants: widths match so connect to each instance - } else if (expwidth == pinwidth * m_cellRangep->elementsConst()) { + } else if (expwidth == modwidth * m_cellRangep->elementsConst()) { // Arrayed instants: one bit for each of the instants (each - // assign is 1 pinwidth wide) + // assign is 1 modwidth wide) if (m_cellRangep->littleEndian()) { nodep->exprp()->v3warn(LITENDIAN, "Little endian instance range connecting to " "vector: left < right of instance range: [" @@ -362,7 +362,7 @@ private: "with output connections to non-wires."); // Note spec allows more complicated matches such as slices and such } - exprp = new AstSel(exprp->fileline(), exprp, pinwidth * m_instSelNum, pinwidth); + exprp = new AstSel(exprp->fileline(), exprp, modwidth * m_instSelNum, modwidth); nodep->exprp(exprp); } else { nodep->v3fatalSrc("Width mismatch; V3Width should have errored out."); diff --git a/src/V3Width.cpp b/src/V3Width.cpp index 1fdc45c57..50c829293 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -4403,26 +4403,26 @@ private: modDTypep = modDTypep->skipRefp(); conDTypep = conDTypep->skipRefp(); AstNodeDType* subDTypep = modDTypep; - const int pinwidth = modDTypep->width(); + const int modwidth = modDTypep->width(); const int conwidth = conDTypep->width(); if (conDTypep == modDTypep // If match, we're golden || similarDTypeRecurse(conDTypep, modDTypep)) { userIterateAndNext(nodep->exprp(), WidthVP(subDTypep, FINAL).p()); } else if (m_cellp->rangep()) { const int numInsts = m_cellp->rangep()->elementsConst(); - if (conwidth == pinwidth) { + if (conwidth == modwidth) { // Arrayed instants: widths match so connect to each instance subDTypep = conDTypep; // = same expr dtype - } else if (conwidth == numInsts * pinwidth) { + } else if (conwidth == numInsts * modwidth) { // Arrayed instants: one bit for each of the instants (each - // assign is 1 pinwidth wide) + // assign is 1 modwidth wide) subDTypep = conDTypep; // = same expr dtype (but numInst*pin_dtype) } else { // Must be a error according to spec // (Because we need to know if to connect to one or all instants) nodep->v3error(ucfirst(nodep->prettyOperatorName()) << " as part of a module instance array" - << " requires " << pinwidth << " or " << pinwidth * numInsts + << " requires " << modwidth << " or " << modwidth * numInsts << " bits, but connection's " << nodep->exprp()->prettyTypeName() << " generates " << conwidth << " bits. (IEEE 1800-2017 23.3.3)"); @@ -4438,12 +4438,12 @@ private: << " data type but connection is " << conDTypep->prettyDTypeNameQ() << " data type."); } else if (nodep->modVarp()->isTristate()) { - if (pinwidth != conwidth) { + if (modwidth != conwidth) { // Ideally should call pinReconnectSimple which would tolerate this // then have a conversion warning nodep->v3warn(E_UNSUPPORTED, "Unsupported: " << ucfirst(nodep->prettyOperatorName()) - << " to inout signal requires " << pinwidth + << " to inout signal requires " << modwidth << " bits, but connection's " << nodep->exprp()->prettyTypeName() << " generates " << conwidth << " bits."); @@ -4524,9 +4524,9 @@ private: // Very much like like an pin const AstNodeDType* const conDTypep = nodep->exprp()->dtypep(); const int numInsts = nodep->rangep()->elementsConst(); - const int pinwidth = numInsts; + const int modwidth = numInsts; const int conwidth = conDTypep->width(); - if (conwidth == 1 && pinwidth > 1) { // Multiple connections + if (conwidth == 1 && modwidth > 1) { // Multiple connections AstNodeDType* const subDTypep = nodep->findLogicDType(1, 1, conDTypep->numeric()); userIterateAndNext(nodep->exprp(), WidthVP(subDTypep, FINAL).p()); AstNode* const newp = new AstReplicate(nodep->fileline(),