From 0e0ce2be52dbed8ad0ce48db90e7a27643992e4a Mon Sep 17 00:00:00 2001
From: Ryszard Rozak <rrozak@antmicro.com>
Date: Fri, 25 Sep 2026 15:43:55 +0200
Subject: [PATCH] Fix mis-setting of process state from FINISHED to KILLED
 (#8506)

Signed-off-by: Ryszard Rozak <rrozak@antmicro.com>
---
 include/verilated_timing.cpp              |  7 +++--
 test_regress/t/t_process_kill_finished.py | 18 ++++++++++++
 test_regress/t/t_process_kill_finished.v  | 36 +++++++++++++++++++++++
 3 files changed, 59 insertions(+), 2 deletions(-)
 create mode 100755 test_regress/t/t_process_kill_finished.py
 create mode 100644 test_regress/t/t_process_kill_finished.v

diff --git a/include/verilated_timing.cpp b/include/verilated_timing.cpp
index 55ebda85e..dfaa2eb8b 100644
--- a/include/verilated_timing.cpp
+++ b/include/verilated_timing.cpp
@@ -296,8 +296,11 @@ void VlProcess::forkSyncOnKillClear(VlForkSyncState* forkSyncp) {
 }
 
 void VlProcess::state(int s) {
-    if (s == KILLED && m_state != KILLED && m_state != FINISHED && m_forkSyncOnKillp
-        && !m_forkSyncOnKillDone) {
+    if (completed()) {
+        // We can't change the sttaus of completed process
+        return;
+    }
+    if (s == KILLED && m_forkSyncOnKillp && !m_forkSyncOnKillDone) {
         m_forkSyncOnKillDone = true;
         m_state = s;
         m_forkSyncOnKillp->done();
diff --git a/test_regress/t/t_process_kill_finished.py b/test_regress/t/t_process_kill_finished.py
new file mode 100755
index 000000000..6fe7d000c
--- /dev/null
+++ b/test_regress/t/t_process_kill_finished.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile(verilator_flags2=["--binary"])
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_process_kill_finished.v b/test_regress/t/t_process_kill_finished.v
new file mode 100644
index 000000000..9b9f76119
--- /dev/null
+++ b/test_regress/t/t_process_kill_finished.v
@@ -0,0 +1,36 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain.
+// SPDX-FileCopyrightText: 2026 Antmicro
+// SPDX-License-Identifier: CC0-1.0
+
+
+module t;
+  process proc;
+
+  initial begin
+    fork
+      begin
+        proc = process::self();
+        fork
+          begin
+            #5;
+          end
+        join_none
+        #1;
+      end
+      #10;
+    join_any
+
+    #1;
+    if (proc.status() != process::FINISHED) $stop;
+    disable fork;
+    if (proc.status() != process::FINISHED) $stop;
+
+    proc.kill();
+    if (proc.status() != process::FINISHED) $stop;
+
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+endmodule