From 0c0a588b55d8eee009cfea99776ada3eae877d98 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Wed, 16 Sep 2009 10:32:14 -0400 Subject: [PATCH] Support generate for var++, var--, ++var, --var. --- Changes | 2 + src/verilog.y | 37 +++++++-------- test_regress/.gitignore | 1 + test_regress/driver.pl | 7 +-- test_regress/t/t_gen_inc.pl | 18 +++++++ test_regress/t/t_gen_inc.v | 93 +++++++++++++++++++++++++++++++++++++ 6 files changed, 136 insertions(+), 22 deletions(-) create mode 100755 test_regress/t/t_gen_inc.pl create mode 100644 test_regress/t/t_gen_inc.v diff --git a/Changes b/Changes index 65b6838ef..6ec992dba 100644 --- a/Changes +++ b/Changes @@ -7,6 +7,8 @@ indicates the contributor was also the author of the fix; Thanks! ** Add --bbox-sys option to blackbox $system calls. +** Support generate for var++, var--, ++var, --var. + *** Improved warning when "do" used as identifier. **** Fix tracing escaped dotted identifiers, bug107. diff --git a/src/verilog.y b/src/verilog.y index d706d9d9b..0a21aea7b 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -1105,24 +1105,23 @@ genvar_initialization: // ==IEEE: genvar_initalization ; genvar_iteration: // ==IEEE: genvar_iteration - varRefBase '=' expr { $$ = new AstAssign($2,$1,$3); } - //UNSUP id '=' expr { UNSUP } - //UNSUP id yP_PLUSEQ expr { UNSUP } - //UNSUP id yP_MINUSEQ expr { UNSUP } - //UNSUP id yP_TIMESEQ expr { UNSUP } - //UNSUP id yP_DIVEQ expr { UNSUP } - //UNSUP id yP_MODEQ expr { UNSUP } - //UNSUP id yP_ANDEQ expr { UNSUP } - //UNSUP id yP_OREQ expr { UNSUP } - //UNSUP id yP_XOREQ expr { UNSUP } - //UNSUP id yP_SLEFTEQ expr { UNSUP } - //UNSUP id yP_SRIGHTEQ expr { UNSUP } - //UNSUP id yP_SSRIGHTEQ expr { UNSUP } + varRefBase '=' expr { $$ = new AstAssign($2,$1,$3); } + | varRefBase yP_PLUSEQ expr { $$ = new AstAssign($2,$1,new AstAdd ($2,$1->cloneTree(true),$3)); } + | varRefBase yP_MINUSEQ expr { $$ = new AstAssign($2,$1,new AstSub ($2,$1->cloneTree(true),$3)); } + | varRefBase yP_TIMESEQ expr { $$ = new AstAssign($2,$1,new AstMul ($2,$1->cloneTree(true),$3)); } + | varRefBase yP_DIVEQ expr { $$ = new AstAssign($2,$1,new AstDiv ($2,$1->cloneTree(true),$3)); } + | varRefBase yP_MODEQ expr { $$ = new AstAssign($2,$1,new AstModDiv ($2,$1->cloneTree(true),$3)); } + | varRefBase yP_ANDEQ expr { $$ = new AstAssign($2,$1,new AstAnd ($2,$1->cloneTree(true),$3)); } + | varRefBase yP_OREQ expr { $$ = new AstAssign($2,$1,new AstOr ($2,$1->cloneTree(true),$3)); } + | varRefBase yP_XOREQ expr { $$ = new AstAssign($2,$1,new AstXor ($2,$1->cloneTree(true),$3)); } + | varRefBase yP_SLEFTEQ expr { $$ = new AstAssign($2,$1,new AstShiftL ($2,$1->cloneTree(true),$3)); } + | varRefBase yP_SRIGHTEQ expr { $$ = new AstAssign($2,$1,new AstShiftR ($2,$1->cloneTree(true),$3)); } + | varRefBase yP_SSRIGHTEQ expr { $$ = new AstAssign($2,$1,new AstShiftRS($2,$1->cloneTree(true),$3)); } // // inc_or_dec_operator - //UNSUP yP_PLUSPLUS id { UNSUP } - //UNSUP yP_MINUSMINUS id { UNSUP } - //UNSUP id yP_PLUSPLUS { UNSUP } - //UNSUP id yP_MINUSMINUS { UNSUP } + | yP_PLUSPLUS varRefBase { $$ = new AstAssign($1,$2,new AstAdd ($1,$2->cloneTree(true),new AstConst($1,V3Number($1,"'b1")))); } + | yP_MINUSMINUS varRefBase { $$ = new AstAssign($1,$2,new AstSub ($1,$2->cloneTree(true),new AstConst($1,V3Number($1,"'b1")))); } + | varRefBase yP_PLUSPLUS { $$ = new AstAssign($2,$1,new AstAdd ($2,$1->cloneTree(true),new AstConst($2,V3Number($2,"'b1")))); } + | varRefBase yP_MINUSMINUS { $$ = new AstAssign($2,$1,new AstSub ($2,$1->cloneTree(true),new AstConst($2,V3Number($2,"'b1")))); } ; case_generate_itemListE: // IEEE: [{ case_generate_itemList }] @@ -1701,8 +1700,8 @@ system_t_call: // IEEE: system_tf_call (as task) ; system_f_call: // IEEE: system_tf_call (as func) - yD_aIGNORE '(' ')' { $$ = new AstConst($1,V3Number($1,0,0)); } // Unsized 0 - | yD_aIGNORE '(' exprList ')' { $$ = new AstConst($1,V3Number($1,0,0)); } // Unsized 0 + yD_aIGNORE '(' ')' { $$ = new AstConst($1,V3Number($1,"'b0")); } // Unsized 0 + | yD_aIGNORE '(' exprList ')' { $$ = new AstConst($1,V3Number($1,"'b0")); } // Unsized 0 // | yD_BITS '(' expr ')' { $$ = new AstAttrOf($1,AstAttrType::BITS,$3); } | yD_C '(' cStrList ')' { $$ = (v3Global.opt.ignc() ? NULL : new AstUCFunc($1,$3)); } diff --git a/test_regress/.gitignore b/test_regress/.gitignore index cf09e2ba2..5725b867c 100644 --- a/test_regress/.gitignore +++ b/test_regress/.gitignore @@ -10,3 +10,4 @@ simx* ncverilog.* INCA_libs logs +.vcsmx_rebuild diff --git a/test_regress/driver.pl b/test_regress/driver.pl index f1060b065..0200f5eb7 100755 --- a/test_regress/driver.pl +++ b/test_regress/driver.pl @@ -236,7 +236,7 @@ sub new { sim_time => 1000, benchmark => $opt_benchmark, # All compilers - v_flags => [split(/\s+/,(" -f input.vc --debug-check" + v_flags => [split(/\s+/,(" -f input.vc " .($opt_verbose ? " +define+TEST_VERBOSE=1":"") .($opt_benchmark ? " +define+TEST_BENCHMARK=$opt_benchmark":"") .($opt_trace ? " +define+WAVES=1":"") @@ -245,7 +245,7 @@ sub new { v_other_filenames => [], # After the filename so we can spec multiple files # VCS vcs => 0, - vcs_flags => [split(/\s+/,"+cli -I +define+vcs+1 -q +v2k")], + vcs_flags => [split(/\s+/,"+cli -I +define+vcs+1 -q -sverilog")], vcs_flags2 => [], # Overridden in some sim files # NC nc => 0, @@ -255,7 +255,8 @@ sub new { # Verilator 'v3' => 0, verilator_flags => ["-cc", - "-Mdir $self->{obj_dir}"], + "-Mdir $self->{obj_dir}", + "--debug-check"], verilator_flags2 => [], verilator_make_gcc => 1, verilated_debug => $Opt_Verilated_Debug, diff --git a/test_regress/t/t_gen_inc.pl b/test_regress/t/t_gen_inc.pl new file mode 100755 index 000000000..7058e622f --- /dev/null +++ b/test_regress/t/t_gen_inc.pl @@ -0,0 +1,18 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +compile ( + ); + +execute ( + check_finished=>1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_gen_inc.v b/test_regress/t/t_gen_inc.v new file mode 100644 index 000000000..e95644c9c --- /dev/null +++ b/test_regress/t/t_gen_inc.v @@ -0,0 +1,93 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + integer cyc=0; + + genvar g; + + reg [31:0] gen_pre_PLUSPLUS = 32'h0; + reg [31:0] gen_pre_MINUSMINUS = 32'h0; + reg [31:0] gen_post_PLUSPLUS = 32'h0; + reg [31:0] gen_post_MINUSMINUS = 32'h0; + reg [31:0] gen_PLUSEQ = 32'h0; + reg [31:0] gen_MINUSEQ = 32'h0; + reg [31:0] gen_TIMESEQ = 32'h0; + reg [31:0] gen_DIVEQ = 32'h0; + reg [31:0] gen_MODEQ = 32'h0; + reg [31:0] gen_ANDEQ = 32'h0; + reg [31:0] gen_OREQ = 32'h0; + reg [31:0] gen_XOREQ = 32'h0; + reg [31:0] gen_SLEFTEQ = 32'h0; + reg [31:0] gen_SRIGHTEQ = 32'h0; + reg [31:0] gen_SSRIGHTEQ = 32'h0; + + generate + for (g=8; g<=16; ++g) always @(posedge clk) gen_pre_PLUSPLUS[g] = 1'b1; + for (g=16; g>=8; --g) always @(posedge clk) gen_pre_MINUSMINUS[g] = 1'b1; + for (g=8; g<=16; g++) always @(posedge clk) gen_post_PLUSPLUS[g] = 1'b1; + for (g=16; g>=8; g--) always @(posedge clk) gen_post_MINUSMINUS[g] = 1'b1; + for (g=8; g<=16; g+=2) always @(posedge clk) gen_PLUSEQ[g] = 1'b1; + for (g=16; g>=8; g-=2) always @(posedge clk) gen_MINUSEQ[g] = 1'b1; +`ifndef verilator //UNSUPPORTED + for (g=8; g<=16; g*=2) always @(posedge clk) gen_TIMESEQ[g] = 1'b1; + for (g=16; g>=8; g/=2) always @(posedge clk) gen_DIVEQ[g] = 1'b1; + for (g=15; g>8; g%=8) always @(posedge clk) gen_MODEQ[g] = 1'b1; + for (g=7; g>4; g&=4) always @(posedge clk) gen_ANDEQ[g] = 1'b1; + for (g=1; g<=1; g|=2) always @(posedge clk) gen_OREQ[g] = 1'b1; + for (g=7; g==7; g^=2) always @(posedge clk) gen_XOREQ[g] = 1'b1; + for (g=8; g<=16; g<<=2) always @(posedge clk) gen_SLEFTEQ[g] = 1'b1; + for (g=16; g>=8; g>>=2) always @(posedge clk) gen_SRIGHTEQ[g] = 1'b1; + for (g=16; g>=8; g>>>=2) always @(posedge clk) gen_SSRIGHTEQ[g] = 1'b1; +`endif + endgenerate + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc == 3) begin +`ifdef TEST_VERBOSE + $write("gen_pre_PLUSPLUS %b\n", gen_pre_PLUSPLUS); + $write("gen_pre_MINUSMINUS %b\n", gen_pre_MINUSMINUS); + $write("gen_post_PLUSPLUS %b\n", gen_post_PLUSPLUS); + $write("gen_post_MINUSMINUS %b\n", gen_post_MINUSMINUS); + $write("gen_PLUSEQ %b\n", gen_PLUSEQ); + $write("gen_MINUSEQ %b\n", gen_MINUSEQ); + $write("gen_TIMESEQ %b\n", gen_TIMESEQ); + $write("gen_DIVEQ %b\n", gen_DIVEQ); + $write("gen_MODEQ %b\n", gen_MODEQ); + $write("gen_ANDEQ %b\n", gen_ANDEQ); + $write("gen_OREQ %b\n", gen_OREQ); + $write("gen_XOREQ %b\n", gen_XOREQ); + $write("gen_SLEFTEQ %b\n", gen_SLEFTEQ); + $write("gen_SRIGHTEQ %b\n", gen_SRIGHTEQ); + $write("gen_SSRIGHTEQ %b\n", gen_SSRIGHTEQ); +`endif + if (gen_pre_PLUSPLUS !== 32'b00000000000000011111111100000000) $stop; + if (gen_pre_MINUSMINUS !== 32'b00000000000000011111111100000000) $stop; + if (gen_post_PLUSPLUS !== 32'b00000000000000011111111100000000) $stop; + if (gen_post_MINUSMINUS!== 32'b00000000000000011111111100000000) $stop; + if (gen_PLUSEQ !== 32'b00000000000000010101010100000000) $stop; + if (gen_MINUSEQ !== 32'b00000000000000010101010100000000) $stop; +`ifndef verilator //UNSUPPORTED + if (gen_TIMESEQ !== 32'b00000000000000010000000100000000) $stop; + if (gen_DIVEQ !== 32'b00000000000000010000000100000000) $stop; + if (gen_MODEQ !== 32'b00000000000000001000000000000000) $stop; + if (gen_ANDEQ !== 32'b00000000000000000000000010000000) $stop; + if (gen_OREQ !== 32'b00000000000000000000000000000010) $stop; + if (gen_XOREQ !== 32'b00000000000000000000000010000000) $stop; + if (gen_SLEFTEQ !== 32'b00000000000000000000000100000000) $stop; + if (gen_SRIGHTEQ !== 32'b00000000000000010000000000000000) $stop; + if (gen_SSRIGHTEQ !== 32'b00000000000000010000000000000000) $stop; +`endif + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule