diff --git a/docs/internals.rst b/docs/internals.rst index 99295c218..3ce56b65d 100644 --- a/docs/internals.rst +++ b/docs/internals.rst @@ -450,7 +450,7 @@ as defined in the standard: - All other logic is assigned to the 'nba' region. For completeness, note that a subset of the 'act' region logic, specifically, -the logic related to the pre-assignments of NBA updates (i.e., AstAssignPre +the logic related to the pre-assignments of NBA updates (i.e., AstAlwaysPre nodes), is handled separately, but is executed as part of the 'act' region. Also note that all logic representing the committing of an NBA (i.e., Ast*Post) diff --git a/src/V3AstNodeOther.h b/src/V3AstNodeOther.h index 821e2bf0c..a3786d519 100644 --- a/src/V3AstNodeOther.h +++ b/src/V3AstNodeOther.h @@ -2551,6 +2551,14 @@ public: : ASTGEN_SUPER_AlwaysPostponed(fl, stmtsp) {} ASTGEN_MEMBERS_AstAlwaysPostponed; }; +class AstAlwaysPre final : public AstNodeProcedure { + // Like always but 'pre' scheduled, e.g. for implementing NBAs + +public: + explicit AstAlwaysPre(FileLine* fl) + : ASTGEN_SUPER_AlwaysPre(fl, nullptr) {} + ASTGEN_MEMBERS_AstAlwaysPre; +}; class AstAlwaysReactive final : public AstNodeProcedure { // Like always but Reactive scheduling region // @astgen op1 := sentreep : Optional[AstSenTree] // Sensitivity list, removed in V3Active diff --git a/src/V3AstNodeStmt.h b/src/V3AstNodeStmt.h index 4a3783276..154578d43 100644 --- a/src/V3AstNodeStmt.h +++ b/src/V3AstNodeStmt.h @@ -1162,28 +1162,6 @@ public: } bool brokeLhsMustBeLvalue() const override { return true; } }; -class AstAssignPost final : public AstNodeAssign { - // Like Assign, but predelayed assignment requiring special order handling -public: - AstAssignPost(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp) - : ASTGEN_SUPER_AssignPost(fl, lhsp, rhsp) {} - ASTGEN_MEMBERS_AstAssignPost; - AstNodeAssign* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override { - return new AstAssignPost{fileline(), lhsp, rhsp}; - } - bool brokeLhsMustBeLvalue() const override { return true; } -}; -class AstAssignPre final : public AstNodeAssign { - // Like Assign, but predelayed assignment requiring special order handling -public: - AstAssignPre(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp) - : ASTGEN_SUPER_AssignPre(fl, lhsp, rhsp) {} - ASTGEN_MEMBERS_AstAssignPre; - AstNodeAssign* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override { - return new AstAssignPre{fileline(), lhsp, rhsp}; - } - bool brokeLhsMustBeLvalue() const override { return true; } -}; class AstAssignVarScope final : public AstNodeAssign { // Assign two VarScopes to each other public: diff --git a/src/V3Delayed.cpp b/src/V3Delayed.cpp index 463d9fe8a..a11d01410 100644 --- a/src/V3Delayed.cpp +++ b/src/V3Delayed.cpp @@ -593,11 +593,15 @@ class DelayedVisitor final : public VNVisitor { activep->senTreeStorep(vscpInfo.senTreep()); scopep->addBlocksp(activep); // Add 'Pre' scheduled 'shadowVariable = originalVariable' assignment - activep->addStmtsp(new AstAssignPre{flp, new AstVarRef{flp, shadowVscp, VAccess::WRITE}, - new AstVarRef{flp, vscp, VAccess::READ}}); + AstAlwaysPre* const prep = new AstAlwaysPre{flp}; + activep->addStmtsp(prep); + prep->addStmtsp(new AstAssign{flp, new AstVarRef{flp, shadowVscp, VAccess::WRITE}, + new AstVarRef{flp, vscp, VAccess::READ}}); // Add 'Post' scheduled 'originalVariable = shadowVariable' assignment - activep->addStmtsp(new AstAssignPost{flp, new AstVarRef{flp, vscp, VAccess::WRITE}, - new AstVarRef{flp, shadowVscp, VAccess::READ}}); + AstAlwaysPost* const postp = new AstAlwaysPost{flp}; + activep->addStmtsp(postp); + postp->addStmtsp(new AstAssign{flp, new AstVarRef{flp, vscp, VAccess::WRITE}, + new AstVarRef{flp, shadowVscp, VAccess::READ}}); } void convertSchemeShadowVar(AstAssignDly* nodep, AstVarScope* vscp, VarScopeInfo& vscpInfo) { UASSERT_OBJ(vscpInfo.m_scheme == Scheme::ShadowVar, vscp, "Inconsistent NBA scheme"); @@ -735,9 +739,10 @@ class DelayedVisitor final : public VNVisitor { new AstAssign{flp, new AstVarRef{flp, flagVscp, VAccess::WRITE}, new AstConst{flp, AstConst::BitTrue{}}}); // Add the 'Pre' scheduled reset for the flag - vscpInfo.flagSharedKit().activep->addStmtsp( - new AstAssignPre{flp, new AstVarRef{flp, flagVscp, VAccess::WRITE}, - new AstConst{flp, AstConst::BitFalse{}}}); + AstAlwaysPre* const prep = new AstAlwaysPre{flp}; + vscpInfo.flagSharedKit().activep->addStmtsp(prep); + prep->addStmtsp(new AstAssign{flp, new AstVarRef{flp, flagVscp, VAccess::WRITE}, + new AstConst{flp, AstConst::BitFalse{}}}); // Add the 'Post' scheduled commit AstIf* const ifp = new AstIf{flp, new AstVarRef{flp, flagVscp, VAccess::READ}}; vscpInfo.flagSharedKit().postp->addStmtsp(ifp); @@ -1164,8 +1169,9 @@ class DelayedVisitor final : public VNVisitor { return new AstVarRef{flp, dlyvscp, access}; }; - AstAssignPre* const prep = new AstAssignPre{flp, dlyRef(VAccess::WRITE), - new AstConst{flp, AstConst::BitFalse{}}}; + AstAlwaysPre* const prep = new AstAlwaysPre{flp}; + prep->addStmtsp(new AstAssign{flp, dlyRef(VAccess::WRITE), + new AstConst{flp, AstConst::BitFalse{}}}); AstAlwaysPost* const postp = new AstAlwaysPost{flp}; { AstIf* const ifp = new AstIf{flp, dlyRef(VAccess::READ)}; @@ -1295,8 +1301,7 @@ class DelayedVisitor final : public VNVisitor { } // Pre/Post logic are created here and their content need no further changes, so ignore. - void visit(AstAssignPre*) override {} - void visit(AstAssignPost*) override {} + void visit(AstAlwaysPre*) override {} void visit(AstAlwaysPost*) override {} //-------------------- diff --git a/src/V3EmitV.cpp b/src/V3EmitV.cpp index 1990c54c9..5608c19d9 100644 --- a/src/V3EmitV.cpp +++ b/src/V3EmitV.cpp @@ -132,6 +132,16 @@ class EmitVBaseVisitorConst VL_NOT_FINAL : public VNVisitorConst { iterateAndNextConstNull(nodep->stmtsp()); putqs(nodep, "end\n"); } + void visit(AstAlwaysPre* nodep) override { + putfs(nodep, "always /* PRE */ begin\n"); + iterateAndNextConstNull(nodep->stmtsp()); + putqs(nodep, "end\n"); + } + void visit(AstAlwaysPost* nodep) override { + putfs(nodep, "always /* POST */ begin\n"); + iterateAndNextConstNull(nodep->stmtsp()); + putqs(nodep, "end\n"); + } void visit(AstAlwaysPublic* nodep) override { putfs(nodep, "/*verilator public_flat_rw "); if (m_sentreep) { diff --git a/src/V3GraphTest.cpp b/src/V3GraphTest.cpp index 6cf2498e7..1c4cab516 100644 --- a/src/V3GraphTest.cpp +++ b/src/V3GraphTest.cpp @@ -188,7 +188,7 @@ public: V3GraphTestVertex* const posedge = n = new V3GraphTestVertex{gp, "*posedge clk*"}; { new V3GraphEdge{gp, clk, n, 2}; } - // AssignPre's VarRefs on LHS: generate special BLK + // AlwaysPre's VarRefs on LHS: generate special BLK // normal: VarRefs on LHS: generate normal // underSBlock: VarRefs on RHS: consume 'pre' (required to save cutable tests) n = new V3GraphTestVertex{gp, "a_dlylogic_sensitive_vertex -// For AssignPre's +// For AlwaysPre's // Add vertex for this logic // Add edge logic_sensitive_vertex->logic_vertex // Add edge logic_consumed_var_PREVAR->logic_vertex @@ -38,11 +38,11 @@ // Add vertex for this logic // Add edge logic_sensitive_vertex->logic_vertex // Add edge logic_generated_var_PREORDER->logic_vertex -// This ensures the AssignPre gets scheduled before this logic +// This ensures the AlwaysPre gets scheduled before this logic // Add edge logic_vertex->consumed_var_PREVAR // Add edge logic_vertex->consumed_var_POSTVAR // Add edge logic_vertex->logic_generated_var (same as if comb) -// For AssignPost's +// For AlwaysPost's // Add vertex for this logic // Add edge logic_sensitive_vertex->logic_vertex // Add edge logic_consumed_var->logic_vertex (same as if comb) diff --git a/src/V3OrderGraph.h b/src/V3OrderGraph.h index 697aa2fe3..9f2386724 100644 --- a/src/V3OrderGraph.h +++ b/src/V3OrderGraph.h @@ -34,13 +34,13 @@ // roles are: // // OrderVarStdVertex: Data dependencies for combinational logic and delayed assignment -// updates (AssignPost). +// updates (AlwaysPost). // OrderVarPostVertex: Ensures all sequential logic blocks reading a signal do so before any // combinational or delayed assignments update that signal. -// OrderVarPordVertex: Ensures a _d = _q AssignPre used to implement delayed (non-blocking) +// OrderVarPordVertex: Ensures a _d = _q AlwaysPre used to implement delayed (non-blocking) // assignments is the first write of a _d, before any sequential blocks // write to that _d. -// OrderVarPreVertex: This is an optimization. Try to ensure that a _d = _q AssignPre is the +// OrderVarPreVertex: This is an optimization. Try to ensure that a _d = _q AlwaysPre is the // last read of a _q, after all reads of that _q by sequential logic. The // model is still correct if we cannot satisfy this due to other interfering // constraints. If respecting this constraint is possible, then combined diff --git a/src/V3OrderGraphBuilder.cpp b/src/V3OrderGraphBuilder.cpp index 58711906c..7080c0406 100644 --- a/src/V3OrderGraphBuilder.cpp +++ b/src/V3OrderGraphBuilder.cpp @@ -102,8 +102,8 @@ class OrderGraphBuilder final : public VNVisitor { AstSenTree* m_hybridp = nullptr; bool m_inClocked = false; // Underneath clocked AstActive - bool m_inPre = false; // Underneath AstAssignPre - bool m_inPost = false; // Underneath AstAssignPost/AstAlwaysPost + bool m_inPre = false; // Underneath AlwaysPre + bool m_inPost = false; // Underneath AstAlwaysPost std::function m_readTriggersCombLogic; // METHODS @@ -232,7 +232,7 @@ class OrderGraphBuilder final : public VNVisitor { // Add edge from produced VarPostVertex -> to producing LogicVertex OrderVarVertex* const postVxp = getVarVertex(varscp, VarVertexType::POST); m_graphp->addHardEdge(postVxp, m_logicVxp, WEIGHT_POST); - } else if (m_inPre) { // AstAssignPre + } else if (m_inPre) { // AstAlwaysPre // Add edge from producing LogicVertex -> produced VarPordVertex OrderVarVertex* const ordVxp = getVarVertex(varscp, VarVertexType::PORD); m_graphp->addHardEdge(m_logicVxp, ordVxp, WEIGHT_NORMAL); @@ -271,7 +271,7 @@ class OrderGraphBuilder final : public VNVisitor { m_graphp->addHardEdge(varVxp, m_logicVxp, WEIGHT_MEDIUM); } } else if (m_inPre) { - // AstAssignPre logic + // AstAlwaysPre logic // Add edge from consumed VarPreVertex -> to consuming LogicVertex // This one is cutable (vs the producer) as there's only one such consumer, // but may be many producers @@ -281,7 +281,7 @@ class OrderGraphBuilder final : public VNVisitor { // Sequential (clocked) logic // Add edge from consuming LogicVertex -> to consumed VarPreVertex // Generation of 'pre' because we want to indicate it should be before - // AstAssignPre + // AstAlwaysPre OrderVarVertex* const preVxp = getVarVertex(varscp, VarVertexType::PRE); m_graphp->addHardEdge(m_logicVxp, preVxp, WEIGHT_NORMAL); // Add edge from consuming LogicVertex -> to consumed VarPostVertex @@ -305,6 +305,12 @@ class OrderGraphBuilder final : public VNVisitor { void visit(AstAlways* nodep) override { // iterateLogic(nodep); } + void visit(AstAlwaysPre* nodep) override { + UASSERT_OBJ(!m_inPre, nodep, "Should not nest"); + VL_RESTORER(m_inPre); + m_inPre = true; + iterateLogic(nodep); + } void visit(AstAlwaysPost* nodep) override { UASSERT_OBJ(!m_inPost, nodep, "Should not nest"); VL_RESTORER(m_inPost); @@ -326,18 +332,6 @@ class OrderGraphBuilder final : public VNVisitor { iterateLogic(nodep); } void visit(AstAssignW* nodep) override { iterateLogic(nodep); } - void visit(AstAssignPre* nodep) override { - UASSERT_OBJ(!m_inPre, nodep, "Should not nest"); - VL_RESTORER(m_inPre); - m_inPre = true; - iterateLogic(nodep); - } - void visit(AstAssignPost* nodep) override { - UASSERT_OBJ(!m_inPost, nodep, "Should not nest"); - VL_RESTORER(m_inPost); - m_inPost = true; - iterateLogic(nodep); - } //--- Verilator concoctions void visit(AstAlwaysPublic* nodep) override { // diff --git a/src/V3Sched.cpp b/src/V3Sched.cpp index d19bebba0..8e4c4f528 100644 --- a/src/V3Sched.cpp +++ b/src/V3Sched.cpp @@ -107,12 +107,13 @@ void invertAndMergeSenTreeMap( AstSenTree* findTriggeredIface(const AstVarScope* vscp, const VirtIfaceTriggers::IfaceSensMap& vifTrigged, const VirtIfaceTriggers::IfaceMemberSensMap& vifMemberTriggered) { + UASSERT_OBJ(vscp->varp()->sensIfacep(), vscp, "Not an virtual interface trigger"); const auto ifaceIt = vifTrigged.find(vscp->varp()->sensIfacep()); if (ifaceIt != vifTrigged.end()) return ifaceIt->second; for (const auto& memberIt : vifMemberTriggered) { if (memberIt.first.m_ifacep == vscp->varp()->sensIfacep()) { return memberIt.second; } } - return nullptr; + vscp->v3fatalSrc("Did not find virtual interface trigger"); } //============================================================================ diff --git a/src/V3Sched.h b/src/V3Sched.h index 1f0e0ffb1..da51a597b 100644 --- a/src/V3Sched.h +++ b/src/V3Sched.h @@ -94,7 +94,7 @@ struct LogicClasses final { // Combinational (including hybrid) logic, and clocked logic in partitioned to compute all clock // signals in the 'act' region. For details see the internals documentation. struct LogicRegions final { - LogicByScope m_pre; // AstAssignPre logic in 'act' region + LogicByScope m_pre; // AstAlwaysPre logic in 'act' region LogicByScope m_act; // 'act' region logic LogicByScope m_nba; // 'nba' region logic LogicByScope m_obs; // AstAlwaysObserved logic in 'obs' region diff --git a/src/V3SchedPartition.cpp b/src/V3SchedPartition.cpp index 28048f098..2923e800f 100644 --- a/src/V3SchedPartition.cpp +++ b/src/V3SchedPartition.cpp @@ -26,7 +26,7 @@ // is then assigned to the 'act' region, and all other logic is assigned to // the 'nba' region. // -// For later practical purposes, AstAssignPre logic that would be assigned to +// For later practical purposes, AstAlwaysPre logic that would be assigned to // the 'act' region is returned separately. Nevertheless, this logic is part of // the 'act' region. // @@ -241,8 +241,7 @@ class SchedGraphBuilder final : public VNVisitor { void visit(AstAlwaysPublic* nodep) override { visitLogic(nodep); } // Pre and Post logic are handled separately - void visit(AstAssignPre* nodep) override {} - void visit(AstAssignPost* nodep) override {} + void visit(AstAlwaysPre* nodep) override {} void visit(AstAlwaysPost* nodep) override {} // LCOV_EXCL_START @@ -375,14 +374,14 @@ LogicRegions partition(LogicByScope& clockedLogic, LogicByScope& combinationalLo markVars(activep); } - // AstAssignPre, AstAssignPost and AstAlwaysPost should only appear under a clocked + // AstAlwaysPre and AstAlwaysPost should only appear under a clocked // AstActive, and should be the only thing left at this point. for (const auto& pair : clockedLogic) { AstScope* const scopep = pair.first; AstActive* const activep = pair.second; for (AstNode *nodep = activep->stmtsp(), *nextp; nodep; nodep = nextp) { nextp = nodep->nextp(); - if (AstAssignPre* const logicp = VN_CAST(nodep, AssignPre)) { + if (AstAlwaysPre* const logicp = VN_CAST(nodep, AlwaysPre)) { bool toActiveRegion = false; logicp->foreach([&](const AstNodeVarRef* vrefp) { AstVarScope* const vscp = vrefp->varScopep(); @@ -398,7 +397,7 @@ LogicRegions partition(LogicByScope& clockedLogic, LogicByScope& combinationalLo logicp->unlinkFrBack(); lbs.add(scopep, activep->sentreep(), logicp); } else { - UASSERT_OBJ(VN_IS(nodep, AssignPost) || VN_IS(nodep, AlwaysPost), nodep, + UASSERT_OBJ(VN_IS(nodep, AlwaysPost), nodep, "Unexpected node type " << nodep->typeName()); nodep->unlinkFrBack(); result.m_nba.add(scopep, activep->sentreep(), nodep); diff --git a/src/V3SchedVirtIface.cpp b/src/V3SchedVirtIface.cpp index b1c5125ff..996dc9357 100644 --- a/src/V3SchedVirtIface.cpp +++ b/src/V3SchedVirtIface.cpp @@ -19,7 +19,7 @@ // Each interface type written to via virtual interface, or written to normally but read via // virtual interface: // Create a trigger var for it -// Each AssignW, AssignPost: +// Each AssignW: // If it writes to a virtual interface, or to a variable read via virtual interface: // Convert to an always // Each statement: @@ -150,6 +150,11 @@ private: m_trigAssignIfacep = nullptr; VL_RESTORER(m_trigAssignMemberVarp); m_trigAssignMemberVarp = nullptr; + // Not sure if needed, but be paranoid to match previous behavior as didn't optimize + // before .. + if (VN_IS(nodep, AlwaysPost) && writesToVirtIface(nodep)) { + nodep->foreach([](AstVarRef* refp) { refp->varScopep()->optimizeLifePost(false); }); + } iterateChildren(nodep); } void visit(AstCFunc* nodep) override { @@ -167,20 +172,6 @@ private: nodep->convertToAlways(); } } - void visit(AstAssignPost* nodep) override { - if (writesToVirtIface(nodep)) { - // Not sure if needed, but be paranoid to match previous behavior as didn't optimize - // before .. - nodep->foreach([](AstVarRef* refp) { refp->varScopep()->optimizeLifePost(false); }); - // Convert to always, as we have to assign the trigger var - FileLine* const flp = nodep->fileline(); - AstAlwaysPost* const postp = new AstAlwaysPost{flp}; - nodep->replaceWith(postp); - postp->addStmtsp( - new AstAssign{flp, nodep->lhsp()->unlinkFrBack(), nodep->rhsp()->unlinkFrBack()}); - VL_DO_DANGLING(nodep->deleteTree(), nodep); - } - } void visit(AstNodeIf* nodep) override { unsupportedWriteToVirtIface(nodep->condp(), "if condition"); { diff --git a/src/V3Width.cpp b/src/V3Width.cpp index 6a7fd368c..70f52ac73 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -5374,7 +5374,6 @@ class WidthVisitor final : public VNVisitor { // handled in each visitor. // Then LHS sign-extends only if *RHS* is signed assertAtStatement(nodep); - // UINFOTREE(1, nodep, "", "AssignPre"); { // UINFOTREE(1, nodep, "", "assin:"); userIterateAndNext(nodep->lhsp(), WidthVP{SELF, BOTH}.p()); diff --git a/test_regress/t/t_json_only_debugcheck.out b/test_regress/t/t_json_only_debugcheck.out index 9451c4e7f..779a57ae3 100644 --- a/test_regress/t/t_json_only_debugcheck.out +++ b/test_regress/t/t_json_only_debugcheck.out @@ -1161,14 +1161,14 @@ {"type":"VAR","name":"__Vtemp_3","addr":"(UR)","loc":"d,90:123,90:124","dtypep":"(RB)","origName":"__Vtemp_3","isSc":false,"isPrimaryIO":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"NONE","varType":"STMTTEMP","dtypeName":"string","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ], "stmtsp": [ - {"type":"ASSIGNPRE","name":"","addr":"(VR)","loc":"d,23:17,23:20","dtypep":"(R)", + {"type":"ASSIGN","name":"","addr":"(VR)","loc":"d,23:17,23:20","dtypep":"(R)", "rhsp": [ {"type":"VARREF","name":"t.cyc","addr":"(WR)","loc":"d,23:17,23:20","dtypep":"(R)","access":"RD","varp":"(Q)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "lhsp": [ {"type":"VARREF","name":"__Vdly__t.cyc","addr":"(XR)","loc":"d,23:17,23:20","dtypep":"(R)","access":"WR","varp":"(MR)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": []}, - {"type":"ASSIGNPRE","name":"","addr":"(YR)","loc":"d,24:9,24:10","dtypep":"(AC)", + {"type":"ASSIGN","name":"","addr":"(YR)","loc":"d,24:9,24:10","dtypep":"(AC)", "rhsp": [ {"type":"VARREF","name":"t.e","addr":"(ZR)","loc":"d,24:9,24:10","dtypep":"(AC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], @@ -2507,14 +2507,14 @@ ]} ]} ]}, - {"type":"ASSIGNPOST","name":"","addr":"(JKB)","loc":"d,23:17,23:20","dtypep":"(R)", + {"type":"ASSIGN","name":"","addr":"(JKB)","loc":"d,23:17,23:20","dtypep":"(R)", "rhsp": [ {"type":"VARREF","name":"__Vdly__t.cyc","addr":"(KKB)","loc":"d,23:17,23:20","dtypep":"(R)","access":"RD","varp":"(MR)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "lhsp": [ {"type":"VARREF","name":"t.cyc","addr":"(LKB)","loc":"d,23:17,23:20","dtypep":"(R)","access":"WR","varp":"(Q)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": []}, - {"type":"ASSIGNPOST","name":"","addr":"(MKB)","loc":"d,24:9,24:10","dtypep":"(AC)", + {"type":"ASSIGN","name":"","addr":"(MKB)","loc":"d,24:9,24:10","dtypep":"(AC)", "rhsp": [ {"type":"VARREF","name":"__Vdly__t.e","addr":"(NKB)","loc":"d,24:9,24:10","dtypep":"(AC)","access":"RD","varp":"(PR)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], diff --git a/test_regress/t/t_xml_debugcheck.out b/test_regress/t/t_xml_debugcheck.out index ca34646a2..afb850422 100644 --- a/test_regress/t/t_xml_debugcheck.out +++ b/test_regress/t/t_xml_debugcheck.out @@ -711,14 +711,14 @@ - + - - + + - + @@ -1510,14 +1510,14 @@ - + - - + + - +