diff --git a/docs/guide/extensions.rst b/docs/guide/extensions.rst index 6d764d840..9150597f5 100644 --- a/docs/guide/extensions.rst +++ b/docs/guide/extensions.rst @@ -697,3 +697,10 @@ or "`ifdef`"'s may break other tools. following loop at the same statement level should always be fully unrolled by Verilator, ignoring :vlopt:`--unroll-count`. This is similar to clang's ``#pragma clang loop unroll(full)``. + +$get_initial_random_seed() + Returns an integer with the initial random seed used for the simulation. + This is the value provided via the :vlopt:`+verilator+seed+\` + runtime option. If no seed is specified, it returns the default + initialization seed (typically 0). + Note that this is not defined by IEEE 1800-2023, but most simulators support it. diff --git a/src/V3AstNodeExpr.h b/src/V3AstNodeExpr.h index 46c350aa2..26f7cdbc8 100644 --- a/src/V3AstNodeExpr.h +++ b/src/V3AstNodeExpr.h @@ -1616,6 +1616,24 @@ public: string emitC() override { V3ERROR_NA_RETURN(""); } bool cleanOut() const override { return true; } }; +class AstGetInitialRandomSeed final : public AstNodeExpr { + // Verilog $get_initial_random_seed() +public: + explicit AstGetInitialRandomSeed(FileLine* fl) + : ASTGEN_SUPER_GetInitialRandomSeed(fl) { + dtypeSetSigned32(); + } + ASTGEN_MEMBERS_AstGetInitialRandomSeed; + string emitVerilog() override { return "$get_initial_random_seed()"; } + string emitC() final override { V3ERROR_NA_RETURN(""); } + bool cleanOut() const override { return true; } + bool isGateOptimizable() const override { return false; } + bool isPredictOptimizable() const override { return true; } + bool isPure() override { return true; } + bool isSystemFunc() const override { return true; } + int instrCount() const override { return INSTR_COUNT_PLI; } + bool sameNode(const AstNode* /*samep*/) const override { return true; } +}; class AstImplication final : public AstNodeExpr { // Verilog Implication Operator // Nonoverlapped "|=>" @@ -5839,5 +5857,4 @@ public: && name() == asamep->name() && dotted() == asamep->dotted()); } }; - #endif // Guard diff --git a/src/V3EmitCFunc.h b/src/V3EmitCFunc.h index ba1826a63..6566b715a 100644 --- a/src/V3EmitCFunc.h +++ b/src/V3EmitCFunc.h @@ -1341,6 +1341,9 @@ public: / v3Global.rootp()->timeprecision().multiplier())); puts(")"); } + void visit(AstGetInitialRandomSeed* nodep) override { + putns(nodep, "vlSymsp->_vm_contextp__->randSeed()"); + } void visit(AstTimeFormat* nodep) override { putns(nodep, "VL_TIMEFORMAT_IINI("); if (nodep->unitsp()) { diff --git a/src/V3Simulate.h b/src/V3Simulate.h index 27aec9c54..506f3e0df 100644 --- a/src/V3Simulate.h +++ b/src/V3Simulate.h @@ -1368,6 +1368,7 @@ private: if (jumpingOver()) return; knownBadNodeType(nodep); } + void visit(AstGetInitialRandomSeed* nodep) override { badNodeType(nodep); } // ==== // default // These types are definitely not reducible diff --git a/src/V3Width.cpp b/src/V3Width.cpp index ad8607d69..513f4cb89 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -500,6 +500,7 @@ class WidthVisitor final : public VNVisitor { void visit(AstTime* nodep) override { nodep->dtypeSetUInt64(); } void visit(AstTimeD* nodep) override { nodep->dtypeSetDouble(); } void visit(AstTimePrecision* nodep) override { nodep->dtypeSetSigned32(); } + void visit(AstGetInitialRandomSeed* nodep) override { nodep->dtypeSetSigned32(); } void visit(AstTimeUnit* nodep) override { nodep->replaceWith( new AstConst{nodep->fileline(), AstConst::Signed32{}, nodep->timeunit().powerOfTen()}); diff --git a/src/verilog.l b/src/verilog.l index 2a8e62b1f..7a47a7c43 100644 --- a/src/verilog.l +++ b/src/verilog.l @@ -528,6 +528,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} "$fell" { FL; return yD_FELL; } "$fell_gclk" { FL; return yD_FELL_GCLK; } "$future_gclk" { FL; return yD_FUTURE_GCLK; } + "$get_initial_random_seed" { FL; return yD_GET_INITIAL_RANDOM_SEED; } "$get_coverage" { FL; STR; ERROR_RSVD_WORD("IEEE 1800-2005"); return yaD_PLI; } "$high" { FL; return yD_HIGH; } "$increment" { FL; return yD_INCREMENT; } diff --git a/src/verilog.y b/src/verilog.y index 156ae003e..f6e7c21d9 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -690,6 +690,7 @@ BISONPRE_VERSION(3.7,%define api.header.include {"V3ParseBison.h"}) %token yD_FWRITEB "$fwriteb" %token yD_FWRITEH "$fwriteh" %token yD_FWRITEO "$fwriteo" +%token yD_GET_INITIAL_RANDOM_SEED "$get_initial_random_seed" %token yD_GLOBAL_CLOCK "$global_clock" %token yD_HIGH "$high" %token yD_HYPOT "$hypot" @@ -776,7 +777,6 @@ BISONPRE_VERSION(3.7,%define api.header.include {"V3ParseBison.h"}) %token yD_WRITEMEMB "$writememb" %token yD_WRITEMEMH "$writememh" %token yD_WRITEO "$writeo" - %token yVL_CLOCKER "/*verilator clocker*/" %token yVL_CLOCK_ENABLE "/*verilator clock_enable*/" %token yVL_COVERAGE_BLOCK_OFF "/*verilator coverage_block_off*/" @@ -4458,6 +4458,7 @@ system_f_or_t_expr_call: // IEEE: part of system_tf_call (can be tas | yD_FSCANF '(' expr ',' str commaVRDListE ')' { $$ = new AstFScanF{$1, *$5, $3, $6}; } | yD_FSEEK '(' expr ',' expr ',' expr ')' { $$ = new AstFSeek{$1, $3, $5, $7}; } | yD_FTELL '(' expr ')' { $$ = new AstFTell{$1, $3}; } + | yD_GET_INITIAL_RANDOM_SEED parenE { $$ = new AstGetInitialRandomSeed{$1}; } | yD_GLOBAL_CLOCK parenE { $$ = GRAMMARP->createGlobalClockParseRef($1); } | yD_HIGH '(' exprOrDataType ')' { $$ = new AstAttrOf{$1, VAttrType::DIM_HIGH, $3, nullptr}; } | yD_HIGH '(' exprOrDataType ',' expr ')' { $$ = new AstAttrOf{$1, VAttrType::DIM_HIGH, $3, $5}; } diff --git a/test_regress/t/t_sys_get_init_seed.out b/test_regress/t/t_sys_get_init_seed.out new file mode 100644 index 000000000..e69de29bb diff --git a/test_regress/t/t_sys_get_init_seed.py b/test_regress/t/t_sys_get_init_seed.py new file mode 100755 index 000000000..872720ddf --- /dev/null +++ b/test_regress/t/t_sys_get_init_seed.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=False, expect_filename=test.golden_filename) +test.compile(verilator_flags2=['--binary']) +test.execute(all_run_flags=['+verilator+seed+22']) + +test.passes() diff --git a/test_regress/t/t_sys_get_init_seed.v b/test_regress/t/t_sys_get_init_seed.v new file mode 100644 index 000000000..2db9a1145 --- /dev/null +++ b/test_regress/t/t_sys_get_init_seed.v @@ -0,0 +1,32 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Srinivasan Venkataramanan +// SPDX-License-Identifier: CC0-1.0 + +class my_c; + rand bit [5:0] b1; + + function void post_randomize(); + $info ("Random value generated as: 0x%h", b1); + endfunction : post_randomize + +endclass : my_c + +module tb (); + int seed = 1; + + my_c my_c_0; + + initial begin + my_c_0 = new(); + /* verilator lint_off WIDTHTRUNC */ + a1 : assert (my_c_0.randomize()); + #5; + seed = $get_initial_random_seed(); + $display("get_initial_random_seed=%0d", seed); + $write("*-* All Finished *-*\n"); + $finish(2); + end + +endmodule