diff --git a/docs/guide/exe_verilator.rst b/docs/guide/exe_verilator.rst index 66e822bdd..69b3dae79 100644 --- a/docs/guide/exe_verilator.rst +++ b/docs/guide/exe_verilator.rst @@ -1224,7 +1224,8 @@ Summary: sc_biguint between 65 and 512, and sc_bv from 513 upwards. When combined with the :vlopt:`--pins-sc-uint` combination, it results in sc_uint being used between 2 and 64 and sc_biguint being used between 65 - and 512. + and 512. Use the :option:`/*verilator&32;sc_biguint*/` metacomment to + selectively set specific signals to `sc_biguint` for any width. .. option:: --pins-sc-uint @@ -2441,9 +2442,13 @@ The grammar of control commands is as follows: following :code:`` can contain :code:`*` and :code:`?` wildcard characters that match any substring or any single character respectively. -.. option:: sc_bv -module "" [-function ""] -var "" +.. option:: sc_biguint -module "" -var "" -.. option:: sc_bv -module "" [-task ""] -var "" + Sets the input/output signal to be of :code:`sc_biguint<{width}>` type. + This metacomment works for signals of any width. + Same as :option:`/*verilator&32;sc_biguint*/`metacomment. + +.. option:: sc_bv -module "" -var "" Sets the port to be of :code:`sc_bv<{width}>` type, instead of bool, uint32_t, or uint64_t. Same as :option:`/*verilator&32;sc_bv*/` diff --git a/docs/guide/extensions.rst b/docs/guide/extensions.rst index 21df64361..7eb81b363 100644 --- a/docs/guide/extensions.rst +++ b/docs/guide/extensions.rst @@ -546,6 +546,15 @@ or "`ifdef`"'s may break other tools. Terminates the previous `/*verilator public*_on*/` directive; see above. +.. option:: /*verilator&32;sc_biguint*/ + + Used after a port declaration. It sets the port to be of + :code:`sc_biguint<{width}>` type, for signals of any width. + This may be useful if the port width is parameterized and the + instantiating C++ code always wants to have a sc_biguint accept any width. + In general, you should avoid using this attribute when unnecessary, as + the performance decreases significantly with increasing usage of sc_biguint. + .. option:: /*verilator&32;sc_bv*/ Used after a port declaration. It sets the port to be of diff --git a/include/verilated_funcs.h b/include/verilated_funcs.h index 2354a5fea..6cc93652c 100644 --- a/include/verilated_funcs.h +++ b/include/verilated_funcs.h @@ -490,6 +490,10 @@ static inline void VL_ASSIGNBIT_WO(int bit, WDataOutP owp) VL_MT_SAFE { { (vvar) = VL_CLEAN_II((obits), (obits), (svar).read().to_uint()); } #define VL_ASSIGN_QSU(obits, vvar, svar) \ { (vvar) = VL_CLEAN_QQ((obits), (obits), (svar).read().to_uint64()); } +#define VL_ASSIGN_ISB(obits, vvar, svar) \ + { (vvar) = VL_CLEAN_II((obits), (obits), (svar).read().to_uint()); } +#define VL_ASSIGN_QSB(obits, vvar, svar) \ + { (vvar) = VL_CLEAN_QQ((obits), (obits), (svar).read().to_uint64()); } #define VL_ASSIGN_WSB(obits, owp, svar) \ { \ const int words = VL_WORDS_I(obits); \ diff --git a/src/V3AstAttr.h b/src/V3AstAttr.h index 8e0f8bdc9..9ba1ca65b 100644 --- a/src/V3AstAttr.h +++ b/src/V3AstAttr.h @@ -316,6 +316,7 @@ public: VAR_PUBLIC_FLAT_RD, // V3LinkParse moves to AstVar::sigPublic VAR_PUBLIC_FLAT_RW, // V3LinkParse moves to AstVar::sigPublic VAR_ISOLATE_ASSIGNMENTS, // V3LinkParse moves to AstVar::attrIsolateAssign + VAR_SC_BIGUINT, // V3LinkParse moves to AstVar::attrScBigUint VAR_SC_BV, // V3LinkParse moves to AstVar::attrScBv VAR_SFORMAT, // V3LinkParse moves to AstVar::attrSFormat VAR_SPLIT_VAR // V3LinkParse moves to AstVar::attrSplitVar @@ -336,7 +337,7 @@ public: "TYPEID", "TYPENAME", "VAR_BASE", "VAR_FORCEABLE", "VAR_PORT_DTYPE", "VAR_PUBLIC", "VAR_PUBLIC_FLAT", "VAR_PUBLIC_FLAT_RD", "VAR_PUBLIC_FLAT_RW", - "VAR_ISOLATE_ASSIGNMENTS", "VAR_SC_BV", "VAR_SFORMAT", + "VAR_ISOLATE_ASSIGNMENTS", "VAR_SC_BIGUINT", "VAR_SC_BV", "VAR_SFORMAT", "VAR_SPLIT_VAR" }; // clang-format on diff --git a/src/V3AstNodeOther.h b/src/V3AstNodeOther.h index bc5b9f661..aeac0d27a 100644 --- a/src/V3AstNodeOther.h +++ b/src/V3AstNodeOther.h @@ -1845,6 +1845,7 @@ class AstVar final : public AstNode { bool m_funcLocalSticky : 1; // As m_funcLocal but remains set if var is moved to a static bool m_funcReturn : 1; // Return variable for a function bool m_attrScBv : 1; // User force bit vector attribute + bool m_attrScBigUint : 1; // User force sc_biguint attribute bool m_attrIsolateAssign : 1; // User isolate_assignments attribute bool m_attrSFormat : 1; // User sformat attribute bool m_attrSplitVar : 1; // declared with split_var metacomment @@ -1895,6 +1896,7 @@ class AstVar final : public AstNode { m_funcLocalSticky = false; m_funcReturn = false; m_attrScBv = false; + m_attrScBigUint = false; m_attrIsolateAssign = false; m_attrSFormat = false; m_attrSplitVar = false; @@ -2025,6 +2027,7 @@ public: void sensIfacep(AstIface* nodep) { m_sensIfacep = nodep; } void attrFileDescr(bool flag) { m_fileDescr = flag; } void attrScBv(bool flag) { m_attrScBv = flag; } + void attrScBigUint(bool flag) { m_attrScBigUint = flag; } void attrIsolateAssign(bool flag) { m_attrIsolateAssign = flag; } void attrSFormat(bool flag) { m_attrSFormat = flag; } void attrSplitVar(bool flag) { m_attrSplitVar = flag; } @@ -2167,6 +2170,7 @@ public: bool isPullup() const { return m_isPullup; } bool isPulldown() const { return m_isPulldown; } bool attrScBv() const { return m_attrScBv; } + bool attrScBigUint() const { return m_attrScBigUint; } bool attrFileDescr() const { return m_fileDescr; } bool attrSFormat() const { return m_attrSFormat; } bool attrSplitVar() const { return m_attrSplitVar; } diff --git a/src/V3AstNodes.cpp b/src/V3AstNodes.cpp index f18be3c40..195fc31b7 100644 --- a/src/V3AstNodes.cpp +++ b/src/V3AstNodes.cpp @@ -518,6 +518,8 @@ bool AstVar::isScUintBool() const { return (isSc() && v3Global.opt.pinsScUintBool() && width() == 1); } bool AstVar::isScBigUint() const { + // Pragma has the highest priority + if (m_attrScBigUint) return true; return ((isSc() && v3Global.opt.pinsScBigUint() && width() >= 65 && width() <= 512) && !isScBv()); } diff --git a/src/V3LinkParse.cpp b/src/V3LinkParse.cpp index 8e05441f8..efaff396b 100644 --- a/src/V3LinkParse.cpp +++ b/src/V3LinkParse.cpp @@ -478,6 +478,10 @@ class LinkParseVisitor final : public VNVisitor { m_varp->attrSplitVar(true); } VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); + } else if (nodep->attrType() == VAttrType::VAR_SC_BIGUINT) { + UASSERT_OBJ(m_varp, nodep, "Attribute not attached to variable"); + m_varp->attrScBigUint(true); + VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); } else if (nodep->attrType() == VAttrType::VAR_SC_BV) { UASSERT_OBJ(m_varp, nodep, "Attribute not attached to variable"); m_varp->attrScBv(true); diff --git a/src/verilog.l b/src/verilog.l index 80969768b..426ed4e65 100644 --- a/src/verilog.l +++ b/src/verilog.l @@ -135,6 +135,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} "public_flat_rd" { FL; return yVLT_PUBLIC_FLAT_RD; } "public_flat_rw" { FL; return yVLT_PUBLIC_FLAT_RW; } "public_module" { FL; return yVLT_PUBLIC_MODULE; } + "sc_biguint" { FL; return yVLT_SC_BIGUINT; } "sc_bv" { FL; return yVLT_SC_BV; } "sformat" { FL; return yVLT_SFORMAT; } "split_var" { FL; return yVLT_SPLIT_VAR; } @@ -815,6 +816,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} "/*verilator public_module*/" { FL; return yVL_PUBLIC_MODULE; } "/*verilator public_on*/" { FL; return yVL_PUBLIC_ON; } "/*verilator public_off*/" { FL; return yVL_PUBLIC_OFF; } // terminates previous 'verilator public*_on' + "/*verilator sc_biguint*/" { FL; return yVL_SC_BIGUINT; } "/*verilator sc_bv*/" { FL; return yVL_SC_BV; } "/*verilator sc_clock*/" { FL; yylval.fl->v3warn(DEPRECATED, "sc_clock is ignored"); FL_BRK; } "/*verilator sformat*/" { FL; return yVL_SFORMAT; } diff --git a/src/verilog.y b/src/verilog.y index 264bb3403..64e57038d 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -262,6 +262,7 @@ BISONPRE_VERSION(3.7,%define api.header.include {"V3ParseBison.h"}) %token yVLT_PUBLIC_FLAT_RD "public_flat_rd" %token yVLT_PUBLIC_FLAT_RW "public_flat_rw" %token yVLT_PUBLIC_MODULE "public_module" +%token yVLT_SC_BIGUINT "sc_biguint" %token yVLT_SC_BV "sc_bv" %token yVLT_SFORMAT "sformat" %token yVLT_SPLIT_VAR "split_var" @@ -792,6 +793,7 @@ BISONPRE_VERSION(3.7,%define api.header.include {"V3ParseBison.h"}) %token yVL_PUBLIC_ON "/*verilator public_on*/" %token yVL_PUBLIC_OFF "/*verilator public_off*/" %token yVL_PUBLIC_MODULE "/*verilator public_module*/" +%token yVL_SC_BIGUINT "/*verilator sc_biguint*/" %token yVL_SC_BV "/*verilator sc_bv*/" %token yVL_SFORMAT "/*verilator sformat*/" %token yVL_SPLIT_VAR "/*verilator split_var*/" @@ -3028,6 +3030,7 @@ sigAttr: | yVL_PUBLIC_FLAT_RD { $$ = new AstAttrOf{$1, VAttrType::VAR_PUBLIC_FLAT_RD}; v3Global.dpi(true); } | yVL_PUBLIC_FLAT_RW attr_event_controlE { $$ = new AstAttrOf{$1, VAttrType::VAR_PUBLIC_FLAT_RW}; v3Global.dpi(true); DEL($2); } | yVL_ISOLATE_ASSIGNMENTS { $$ = new AstAttrOf{$1, VAttrType::VAR_ISOLATE_ASSIGNMENTS}; } + | yVL_SC_BIGUINT { $$ = new AstAttrOf{$1, VAttrType::VAR_SC_BIGUINT}; } | yVL_SC_BV { $$ = new AstAttrOf{$1, VAttrType::VAR_SC_BV}; } | yVL_SFORMAT { $$ = new AstAttrOf{$1, VAttrType::VAR_SFORMAT}; } | yVL_SPLIT_VAR { $$ = new AstAttrOf{$1, VAttrType::VAR_SPLIT_VAR}; } @@ -8146,6 +8149,7 @@ vltVarAttrFront: | yVLT_PUBLIC_FLAT { $$ = VAttrType::VAR_PUBLIC_FLAT; v3Global.dpi(true); } | yVLT_PUBLIC_FLAT_RD { $$ = VAttrType::VAR_PUBLIC_FLAT_RD; v3Global.dpi(true); } | yVLT_PUBLIC_FLAT_RW { $$ = VAttrType::VAR_PUBLIC_FLAT_RW; v3Global.dpi(true); } + | yVLT_SC_BIGUINT { $$ = VAttrType::VAR_SC_BIGUINT; } | yVLT_SC_BV { $$ = VAttrType::VAR_SC_BV; } | yVLT_SFORMAT { $$ = VAttrType::VAR_SFORMAT; } | yVLT_SPLIT_VAR { $$ = VAttrType::VAR_SPLIT_VAR; } diff --git a/test_regress/t/t_var_pins_sc1.py b/test_regress/t/t_var_pins_sc1.py index 3fdd5bb81..7e9d114a9 100755 --- a/test_regress/t/t_var_pins_sc1.py +++ b/test_regress/t/t_var_pins_sc1.py @@ -33,6 +33,8 @@ hgrep(r'sc_core::sc_in\s>\s+&ibv1;') hgrep(r'sc_core::sc_in\s>\s+&ibv16;') hgrep(r'sc_core::sc_in\s>\s+&ibv1_vlt;') hgrep(r'sc_core::sc_in\s>\s+&ibv16_vlt;') +hgrep(r'sc_core::sc_in\s>\s+&ibu1_vlt;') +hgrep(r'sc_core::sc_in\s>\s+&ibu16_vlt;') hgrep(r'sc_core::sc_out\s>\s+&o1;') hgrep(r'sc_core::sc_out\s>\s+&o8;') @@ -45,6 +47,22 @@ hgrep(r'sc_core::sc_out\s>\s+&obv16;') hgrep(r'sc_core::sc_out\s>\s+&obv1_vlt;') hgrep(r'sc_core::sc_out\s>\s+&obv16_vlt;') +# sc_biguint pragma overrides `-pins-bv 1` flag +hgrep(r'sc_core::sc_in\s>\s+&ibu1;') +hgrep(r'sc_core::sc_in\s>\s+&ibu8;') +hgrep(r'sc_core::sc_in\s>\s+&ibu16;') +hgrep(r'sc_core::sc_in\s>\s+&ibu64;') +hgrep(r'sc_core::sc_in\s>\s+&ibu512;') +hgrep(r'sc_core::sc_in\s>\s+&ibu1_vlt;') +hgrep(r'sc_core::sc_in\s>\s+&ibu16_vlt;') +hgrep(r'sc_core::sc_out\s>\s+&obu1;') +hgrep(r'sc_core::sc_out\s>\s+&obu8;') +hgrep(r'sc_core::sc_out\s>\s+&obu16;') +hgrep(r'sc_core::sc_out\s>\s+&obu64;') +hgrep(r'sc_core::sc_out\s>\s+&obu512;') +hgrep(r'sc_core::sc_out\s>\s+&obu1_vlt;') +hgrep(r'sc_core::sc_out\s>\s+&obu16_vlt;') + test.execute() test.passes() diff --git a/test_regress/t/t_var_pins_sc2.py b/test_regress/t/t_var_pins_sc2.py index 845b9ddc9..8cf009783 100755 --- a/test_regress/t/t_var_pins_sc2.py +++ b/test_regress/t/t_var_pins_sc2.py @@ -45,6 +45,21 @@ hgrep(r'sc_core::sc_out\s>\s+&obv16;') hgrep(r'sc_core::sc_out\s>\s+&obv1_vlt;') hgrep(r'sc_core::sc_out\s>\s+&obv16_vlt;') +# sc_biguint pragma overrides `-pins-bv 2` flag +hgrep(r'sc_core::sc_in\s>\s+&ibu8;') +hgrep(r'sc_core::sc_in\s>\s+&ibu16;') +hgrep(r'sc_core::sc_in\s>\s+&ibu64;') +hgrep(r'sc_core::sc_in\s>\s+&ibu512;') +hgrep(r'sc_core::sc_in\s>\s+&ibu1_vlt;') +hgrep(r'sc_core::sc_in\s>\s+&ibu16_vlt;') +hgrep(r'sc_core::sc_out\s>\s+&obu1;') +hgrep(r'sc_core::sc_out\s>\s+&obu8;') +hgrep(r'sc_core::sc_out\s>\s+&obu16;') +hgrep(r'sc_core::sc_out\s>\s+&obu64;') +hgrep(r'sc_core::sc_out\s>\s+&obu512;') +hgrep(r'sc_core::sc_out\s>\s+&obu1_vlt;') +hgrep(r'sc_core::sc_out\s>\s+&obu16_vlt;') + test.execute() test.passes() diff --git a/test_regress/t/t_var_pins_sc32.py b/test_regress/t/t_var_pins_sc32.py index 43b22fcd8..55d5fc5c2 100755 --- a/test_regress/t/t_var_pins_sc32.py +++ b/test_regress/t/t_var_pins_sc32.py @@ -45,6 +45,19 @@ hgrep(r'sc_core::sc_out\s>\s+&obv16;') hgrep(r'sc_core::sc_out\s>\s+&obv1_vlt;') hgrep(r'sc_core::sc_out\s>\s+&obv16_vlt;') +# sc_biguint pragma overrides `-pins-bv 32` flag +hgrep(r'sc_core::sc_in\s>\s+&ibu64;') +hgrep(r'sc_core::sc_in\s>\s+&ibu512;') +hgrep(r'sc_core::sc_in\s>\s+&ibu1_vlt;') +hgrep(r'sc_core::sc_in\s>\s+&ibu16_vlt;') +hgrep(r'sc_core::sc_out\s>\s+&obu1;') +hgrep(r'sc_core::sc_out\s>\s+&obu8;') +hgrep(r'sc_core::sc_out\s>\s+&obu16;') +hgrep(r'sc_core::sc_out\s>\s+&obu64;') +hgrep(r'sc_core::sc_out\s>\s+&obu512;') +hgrep(r'sc_core::sc_out\s>\s+&obu1_vlt;') +hgrep(r'sc_core::sc_out\s>\s+&obu16_vlt;') + test.execute() test.passes() diff --git a/test_regress/t/t_var_pins_sc64.py b/test_regress/t/t_var_pins_sc64.py index e51114c44..b550f6899 100755 --- a/test_regress/t/t_var_pins_sc64.py +++ b/test_regress/t/t_var_pins_sc64.py @@ -45,6 +45,22 @@ hgrep(r'sc_core::sc_out\s>\s+&obv16;') hgrep(r'sc_core::sc_out\s>\s+&obv1_vlt;') hgrep(r'sc_core::sc_out\s>\s+&obv16_vlt;') +# sc_biguint pragma overrides `-pins-bv 64` flag +hgrep(r'sc_core::sc_in\s>\s+&ibu1;') +hgrep(r'sc_core::sc_in\s>\s+&ibu8;') +hgrep(r'sc_core::sc_in\s>\s+&ibu16;') +hgrep(r'sc_core::sc_in\s>\s+&ibu64;') +hgrep(r'sc_core::sc_in\s>\s+&ibu512;') +hgrep(r'sc_core::sc_in\s>\s+&ibu1_vlt;') +hgrep(r'sc_core::sc_in\s>\s+&ibu16_vlt;') +hgrep(r'sc_core::sc_out\s>\s+&obu1;') +hgrep(r'sc_core::sc_out\s>\s+&obu8;') +hgrep(r'sc_core::sc_out\s>\s+&obu16;') +hgrep(r'sc_core::sc_out\s>\s+&obu64;') +hgrep(r'sc_core::sc_out\s>\s+&obu512;') +hgrep(r'sc_core::sc_out\s>\s+&obu1_vlt;') +hgrep(r'sc_core::sc_out\s>\s+&obu16_vlt;') + test.execute() test.passes() diff --git a/test_regress/t/t_var_pins_sc_biguint.py b/test_regress/t/t_var_pins_sc_biguint.py index 9bfab903b..7336b83fd 100755 --- a/test_regress/t/t_var_pins_sc_biguint.py +++ b/test_regress/t/t_var_pins_sc_biguint.py @@ -43,6 +43,20 @@ hgrep(r'sc_core::sc_out\s>\s+&o513;') hgrep(r'sc_core::sc_out\s>\s+&obv1;') hgrep(r'sc_core::sc_out\s>\s+&obv16;') +# sc_biguint pragma overrides `--pins-sc-biguint` flag +hgrep(r'sc_core::sc_in\s>\s+&ibu1;') +hgrep(r'sc_core::sc_in\s>\s+&ibu8;') +hgrep(r'sc_core::sc_in\s>\s+&ibu16;') +hgrep(r'sc_core::sc_in\s>\s+&ibu64;') +hgrep(r'sc_core::sc_in\s>\s+&ibu512;') +hgrep(r'sc_core::sc_in\s>\s+&ibu601;') +hgrep(r'sc_core::sc_out\s>\s+&obu1;') +hgrep(r'sc_core::sc_out\s>\s+&obu8;') +hgrep(r'sc_core::sc_out\s>\s+&obu16;') +hgrep(r'sc_core::sc_out\s>\s+&obu64;') +hgrep(r'sc_core::sc_out\s>\s+&obu512;') +hgrep(r'sc_core::sc_out\s>\s+&obu601;') + test.execute() test.passes() diff --git a/test_regress/t/t_var_pins_sc_uint.py b/test_regress/t/t_var_pins_sc_uint.py index 8ad431263..0836de46a 100755 --- a/test_regress/t/t_var_pins_sc_uint.py +++ b/test_regress/t/t_var_pins_sc_uint.py @@ -43,6 +43,19 @@ hgrep(r'sc_core::sc_out\s>\s+&o513;') hgrep(r'sc_core::sc_out\s>\s+&obv1;') hgrep(r'sc_core::sc_out\s>\s+&obv16;') +# sc_biguint pragma overrides `--pins-sc-uint` flag +hgrep(r'sc_core::sc_in\s>\s+&ibu8;') +hgrep(r'sc_core::sc_in\s>\s+&ibu16;') +hgrep(r'sc_core::sc_in\s>\s+&ibu64;') +hgrep(r'sc_core::sc_in\s>\s+&ibu512;') +hgrep(r'sc_core::sc_in\s>\s+&ibu601;') +hgrep(r'sc_core::sc_out\s>\s+&obu1;') +hgrep(r'sc_core::sc_out\s>\s+&obu8;') +hgrep(r'sc_core::sc_out\s>\s+&obu16;') +hgrep(r'sc_core::sc_out\s>\s+&obu64;') +hgrep(r'sc_core::sc_out\s>\s+&obu512;') +hgrep(r'sc_core::sc_out\s>\s+&obu601;') + test.execute() test.passes() diff --git a/test_regress/t/t_var_pins_sc_uint_biguint.py b/test_regress/t/t_var_pins_sc_uint_biguint.py index 1ebd47243..5f7abceda 100755 --- a/test_regress/t/t_var_pins_sc_uint_biguint.py +++ b/test_regress/t/t_var_pins_sc_uint_biguint.py @@ -44,6 +44,19 @@ hgrep(r'sc_core::sc_out\s>\s+&o513;') hgrep(r'sc_core::sc_out\s>\s+&obv1;') hgrep(r'sc_core::sc_out\s>\s+&obv16;') +hgrep(r'sc_core::sc_in\s>\s+&ibu1;') +hgrep(r'sc_core::sc_in\s>\s+&ibu8;') +hgrep(r'sc_core::sc_in\s>\s+&ibu16;') +hgrep(r'sc_core::sc_in\s>\s+&ibu64;') +hgrep(r'sc_core::sc_in\s>\s+&ibu512;') +hgrep(r'sc_core::sc_out\s>\s+&obu1;') +hgrep(r'sc_core::sc_out\s>\s+&obu8;') +hgrep(r'sc_core::sc_out\s>\s+&obu16;') +hgrep(r'sc_core::sc_out\s>\s+&obu64;') +hgrep(r'sc_core::sc_out\s>\s+&obu512;') +hgrep(r'sc_core::sc_in\s>\s+&ibu601;') +hgrep(r'sc_core::sc_out\s>\s+&obu601;') + test.execute() test.passes() diff --git a/test_regress/t/t_var_pins_sc_uint_bool.py b/test_regress/t/t_var_pins_sc_uint_bool.py index 8809d0bd4..e2b556580 100755 --- a/test_regress/t/t_var_pins_sc_uint_bool.py +++ b/test_regress/t/t_var_pins_sc_uint_bool.py @@ -39,6 +39,18 @@ hgrep(r'sc_core::sc_out\s>\s+&o65;') hgrep(r'sc_core::sc_out\s>\s+&o128;') hgrep(r'sc_core::sc_out\s>\s+&o513;') +# sc_biguint pragma overrides `--pins-sc-uint-bool` flag +hgrep(r'sc_core::sc_in\s>\s+&ibu1;') +hgrep(r'sc_core::sc_in\s>\s+&ibu8;') +hgrep(r'sc_core::sc_in\s>\s+&ibu16;') +hgrep(r'sc_core::sc_in\s>\s+&ibu64;') +hgrep(r'sc_core::sc_in\s>\s+&ibu512;') +hgrep(r'sc_core::sc_out\s>\s+&obu1;') +hgrep(r'sc_core::sc_out\s>\s+&obu8;') +hgrep(r'sc_core::sc_out\s>\s+&obu16;') +hgrep(r'sc_core::sc_out\s>\s+&obu64;') +hgrep(r'sc_core::sc_out\s>\s+&obu512;') + test.execute() test.passes() diff --git a/test_regress/t/t_var_pins_scui.py b/test_regress/t/t_var_pins_scui.py index 02fa69cb8..c3600fa8a 100755 --- a/test_regress/t/t_var_pins_scui.py +++ b/test_regress/t/t_var_pins_scui.py @@ -40,6 +40,29 @@ test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_out\s>\s+&obv16;') +# sc_biguint pragma should override `--pins-uint8` flag +test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", + r'sc_core::sc_in\s>\s+&ibu1;') +test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", + r'sc_core::sc_in\s>\s+&ibu8;') +test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", + r'sc_core::sc_in\s>\s+&ibu16;') +test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", + r'sc_core::sc_in\s>\s+&ibu64;') +test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", + r'sc_core::sc_in\s>\s+&ibu512;') + +test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", + r'sc_core::sc_out\s>\s+&obu1;') +test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", + r'sc_core::sc_out\s>\s+&obu8;') +test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", + r'sc_core::sc_out\s>\s+&obu16;') +test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", + r'sc_core::sc_out\s>\s+&obu64;') +test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", + r'sc_core::sc_out\s>\s+&obu512;') + test.execute() test.passes() diff --git a/test_regress/t/t_var_pinsizes.v b/test_regress/t/t_var_pinsizes.v index 335f0b097..20621c891 100644 --- a/test_regress/t/t_var_pinsizes.v +++ b/test_regress/t/t_var_pinsizes.v @@ -8,9 +8,13 @@ module t (/*AUTOARG*/ // Outputs - o1, o8, o16, o32, o64, o65, o128, o513, o1a2, o94a3, obv1, obv16, obv1_vlt, obv16_vlt, + o1, o8, o16, o32, o64, o65, o128, o513, o1a2, o94a3, + obv1, obv16, obv1_vlt, obv16_vlt, + obu1, obu8, obu16, obu64, obu512, obu1_vlt, obu16_vlt, obu601, // Inputs - clk, i1, i8, i16, i32, i64, i65, i128, i513, i1a2, i94a3, ibv1, ibv16, ibv1_vlt, ibv16_vlt + clk, i1, i8, i16, i32, i64, i65, i128, i513, i1a2, i94a3, + ibv1, ibv16, ibv1_vlt, ibv16_vlt, + ibu1, ibu8, ibu16, ibu64, ibu512, ibu1_vlt, ibu16_vlt, ibu601 ); input clk; @@ -47,6 +51,24 @@ module t (/*AUTOARG*/ output logic [0:0] obv1_vlt; output logic [15:0] obv16_vlt; + input ibu1 /*verilator sc_biguint*/; + input [7:0] ibu8 /*verilator sc_biguint*/; + input [15:0] ibu16 /*verilator sc_biguint*/; + input [63:0] ibu64 /*verilator sc_biguint*/; + input [511:0] ibu512 /*verilator sc_biguint*/; + input ibu1_vlt; + input [15:0] ibu16_vlt; + input [600:0] ibu601 /*verilator sc_biguint*/; + + output logic obu1 /*verilator sc_biguint*/; + output logic [7:0] obu8 /*verilator sc_biguint*/; + output logic [15:0] obu16 /*verilator sc_biguint*/; + output logic [63:0] obu64 /*verilator sc_biguint*/; + output logic [511:0] obu512 /*verilator sc_biguint*/; + output logic obu1_vlt; + output logic [15:0] obu16_vlt; + output logic [600:0] obu601 /*verilator sc_biguint*/; + always @ (posedge clk) begin o1 <= i1; o8 <= i8; @@ -62,6 +84,14 @@ module t (/*AUTOARG*/ obv16_vlt <= ibv16_vlt; o1a2 <= i1a2; o94a3 <= i94a3; + obu1 <= ibu1; + obu8 <= ibu8; + obu16 <= ibu16; + obu64 <= ibu64; + obu512 <= ibu512; + obu1_vlt <= ibu1_vlt; + obu16_vlt <= ibu16_vlt; + obu601 <= ibu601; end endmodule diff --git a/test_regress/t/t_var_pinsizes.vlt b/test_regress/t/t_var_pinsizes.vlt index 9387fc27d..40e17265b 100644 --- a/test_regress/t/t_var_pinsizes.vlt +++ b/test_regress/t/t_var_pinsizes.vlt @@ -9,3 +9,7 @@ sc_bv -module "t" -var "ibv1_vlt" sc_bv -module "*" -var "ibv16_vlt" sc_bv -module "*" -var "obv*_vlt" + +sc_biguint -module "t" -var "ibu1_vlt" +sc_biguint -module "*" -var "ibu16_vlt" +sc_biguint -module "*" -var "obu*_vlt" diff --git a/test_regress/t/t_vlt_var_sc_biguint_bad.out b/test_regress/t/t_vlt_var_sc_biguint_bad.out new file mode 100644 index 000000000..b7f9444b8 --- /dev/null +++ b/test_regress/t/t_vlt_var_sc_biguint_bad.out @@ -0,0 +1,8 @@ +%Error: t/t_vlt_var_sc_biguint_bad.vlt:9:1: 'VAR_SC_BIGUINT' attribute does not accept -param/-port + 9 | sc_biguint -module "top" -param "*" + | ^~~~~~~~~~ + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error: t/t_vlt_var_sc_biguint_bad.vlt:10:1: 'VAR_SC_BIGUINT' attribute does not accept -param/-port + 10 | sc_biguint -module "top" -port "*" + | ^~~~~~~~~~ +%Error: Exiting due to diff --git a/test_regress/t/t_vlt_var_sc_biguint_bad.py b/test_regress/t/t_vlt_var_sc_biguint_bad.py new file mode 100755 index 000000000..f9df35643 --- /dev/null +++ b/test_regress/t/t_vlt_var_sc_biguint_bad.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2025 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +# Doesn't matter which one +test.top_filename = "t/t_vlt_public_spec.v" + +test.compile(verilator_flags2=[test.name + ".vlt"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_vlt_var_sc_biguint_bad.vlt b/test_regress/t/t_vlt_var_sc_biguint_bad.vlt new file mode 100644 index 000000000..5f0ac35b3 --- /dev/null +++ b/test_regress/t/t_vlt_var_sc_biguint_bad.vlt @@ -0,0 +1,10 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2025 by Antmicro. +// SPDX-License-Identifier: CC0-1.0 + +`verilator_config + +sc_biguint -module "top" -param "*" +sc_biguint -module "top" -port "*"