diff --git a/test_regress/t/t_assert_synth_full.out b/test_regress/t/t_assert_synth_full.out new file mode 100644 index 000000000..9f6e561ed --- /dev/null +++ b/test_regress/t/t_assert_synth_full.out @@ -0,0 +1,3 @@ +[40] %Error: t_assert_synth.v:30: Assertion failed in top.t: synthesis full_case, but non-match found +%Error: t/t_assert_synth.v:30: Verilog $stop +Aborting... diff --git a/test_regress/t/t_assert_synth_full.pl b/test_regress/t/t_assert_synth_full.pl index eb9239199..163cd8d1a 100755 --- a/test_regress/t/t_assert_synth_full.pl +++ b/test_regress/t/t_assert_synth_full.pl @@ -20,8 +20,7 @@ compile( execute( check_finished => 0, fails => $Self->{vlt_all}, - expect => -'%Error: t_assert_synth.v:30: Assertion failed in top.t: synthesis full_case' + expect_filename => $Self->{golden_filename}, ); ok(1); diff --git a/test_regress/t/t_assert_synth_parallel.out b/test_regress/t/t_assert_synth_parallel.out new file mode 100644 index 000000000..bb79253ff --- /dev/null +++ b/test_regress/t/t_assert_synth_parallel.out @@ -0,0 +1,3 @@ +[40] %Error: t_assert_synth.v:49: Assertion failed in top.t: synthesis parallel_case, but multiple matches found +%Error: t/t_assert_synth.v:49: Verilog $stop +Aborting... diff --git a/test_regress/t/t_assert_synth_parallel.pl b/test_regress/t/t_assert_synth_parallel.pl index 628288ac8..a6845dce7 100755 --- a/test_regress/t/t_assert_synth_parallel.pl +++ b/test_regress/t/t_assert_synth_parallel.pl @@ -20,8 +20,7 @@ compile( execute( check_finished => 0, fails => $Self->{vlt_all}, - expect => -'%Error: t_assert_synth.v:\d+: Assertion failed in top.t: synthesis parallel_case' + expect_filename => $Self->{golden_filename}, ); ok(1); diff --git a/test_regress/t/t_assert_synth_parallel_vlt.out b/test_regress/t/t_assert_synth_parallel_vlt.out new file mode 100644 index 000000000..d72e3e98a --- /dev/null +++ b/test_regress/t/t_assert_synth_parallel_vlt.out @@ -0,0 +1,3 @@ +[40] %Error: t_assert_synth.v:54: Assertion failed in top.t: synthesis parallel_case, but multiple matches found +%Error: t/t_assert_synth.v:54: Verilog $stop +Aborting... diff --git a/test_regress/t/t_assert_synth_parallel_vlt.pl b/test_regress/t/t_assert_synth_parallel_vlt.pl index c9cd46167..14d807904 100755 --- a/test_regress/t/t_assert_synth_parallel_vlt.pl +++ b/test_regress/t/t_assert_synth_parallel_vlt.pl @@ -20,8 +20,7 @@ compile( execute( check_finished => 0, fails => $Self->{vlt_all}, - expect => -'%Error: t_assert_synth.v:\d+: Assertion failed in top.t: synthesis parallel_case' + expect_filename => $Self->{golden_filename}, ); ok(1); diff --git a/test_regress/t/t_preproc_inc_bad.out b/test_regress/t/t_preproc_inc_bad.out new file mode 100644 index 000000000..e715854ad --- /dev/null +++ b/test_regress/t/t_preproc_inc_bad.out @@ -0,0 +1,5 @@ +%Error: t/t_preproc_inc_inc_bad.vh:10: syntax error, unexpected endmodule, expecting IDENTIFIER +endmodule +^~~~~~~~~ + t/t_preproc_inc_bad.v:9: ... note: In file included from t_preproc_inc_bad.v +%Error: Exiting due to diff --git a/test_regress/t/t_preproc_inc_bad.pl b/test_regress/t/t_preproc_inc_bad.pl index ec7744e00..b06182c25 100755 --- a/test_regress/t/t_preproc_inc_bad.pl +++ b/test_regress/t/t_preproc_inc_bad.pl @@ -12,8 +12,7 @@ scenarios(vlt => 1); lint( fails => 1, # The .vh file has the error, not the .v file - expect => -'%Error: t/t_preproc_inc_inc_bad.vh:10: syntax error, unexpected endmodule, expecting IDENTIFIER' + expect_filename => $Self->{golden_filename}, ); ok(1); diff --git a/test_regress/t/t_sys_readmem_bad_addr.out b/test_regress/t/t_sys_readmem_bad_addr.out new file mode 100644 index 000000000..4ccbe65e9 --- /dev/null +++ b/test_regress/t/t_sys_readmem_bad_addr.out @@ -0,0 +1,2 @@ +%Error: t/t_sys_readmem_bad_addr.mem:8: $readmem file address beyond bounds of array +Aborting... diff --git a/test_regress/t/t_sys_readmem_bad_addr.pl b/test_regress/t/t_sys_readmem_bad_addr.pl index 8e05d5ac6..066bf0da6 100755 --- a/test_regress/t/t_sys_readmem_bad_addr.pl +++ b/test_regress/t/t_sys_readmem_bad_addr.pl @@ -14,8 +14,7 @@ compile( execute( fails => $Self->{vlt_all}, - expect => -'%Error: t/t_sys_readmem_bad_addr.mem:\d+: \$readmem file address beyond bounds of array', + expect_filename => $Self->{golden_filename}, ); ok(1); diff --git a/test_regress/t/t_sys_readmem_bad_digit.out b/test_regress/t/t_sys_readmem_bad_digit.out new file mode 100644 index 000000000..3077426de --- /dev/null +++ b/test_regress/t/t_sys_readmem_bad_digit.out @@ -0,0 +1,2 @@ +%Error: t/t_sys_readmem_bad_digit.mem:7: $readmemb (binary) file contains hex characters +Aborting... diff --git a/test_regress/t/t_sys_readmem_bad_digit.pl b/test_regress/t/t_sys_readmem_bad_digit.pl index d8a51828e..066bf0da6 100755 --- a/test_regress/t/t_sys_readmem_bad_digit.pl +++ b/test_regress/t/t_sys_readmem_bad_digit.pl @@ -14,8 +14,7 @@ compile( execute( fails => $Self->{vlt_all}, - expect => -'%Error: t/t_sys_readmem_bad_digit.mem:\d+: \$readmemb \(binary\) file contains hex characters', + expect_filename => $Self->{golden_filename}, ); ok(1); diff --git a/test_regress/t/t_sys_readmem_bad_end.out b/test_regress/t/t_sys_readmem_bad_end.out new file mode 100644 index 000000000..e372a3ac1 --- /dev/null +++ b/test_regress/t/t_sys_readmem_bad_end.out @@ -0,0 +1,2 @@ +%Error: t/t_sys_readmem_bad_end.mem:11: $readmem file ended before specified final address (IEEE 2017 21.4) +Aborting... diff --git a/test_regress/t/t_sys_readmem_bad_end.pl b/test_regress/t/t_sys_readmem_bad_end.pl index debf6df30..066bf0da6 100755 --- a/test_regress/t/t_sys_readmem_bad_end.pl +++ b/test_regress/t/t_sys_readmem_bad_end.pl @@ -14,8 +14,7 @@ compile( execute( fails => $Self->{vlt_all}, - expect => -'%Error: t/t_sys_readmem_bad_end.mem:\d+: \$readmem file ended before specified final address', + expect_filename => $Self->{golden_filename}, ); ok(1); diff --git a/test_regress/t/t_sys_readmem_bad_notfound.out b/test_regress/t/t_sys_readmem_bad_notfound.out new file mode 100644 index 000000000..317be5d9a --- /dev/null +++ b/test_regress/t/t_sys_readmem_bad_notfound.out @@ -0,0 +1,2 @@ +%Error: t/t_sys_readmem_bad_NOTFOUND.mem:0: $readmem file not found +Aborting... diff --git a/test_regress/t/t_sys_readmem_bad_notfound.pl b/test_regress/t/t_sys_readmem_bad_notfound.pl index 499e85c9f..066bf0da6 100755 --- a/test_regress/t/t_sys_readmem_bad_notfound.pl +++ b/test_regress/t/t_sys_readmem_bad_notfound.pl @@ -14,8 +14,7 @@ compile( execute( fails => $Self->{vlt_all}, - expect => -'%Error: t/t_sys_readmem_bad_NOTFOUND.mem:\d+: \$readmem file not found', + expect_filename => $Self->{golden_filename}, ); ok(1); diff --git a/test_regress/t/t_uniqueif_fail1.out b/test_regress/t/t_uniqueif_fail1.out new file mode 100644 index 000000000..281b18073 --- /dev/null +++ b/test_regress/t/t_uniqueif_fail1.out @@ -0,0 +1,4 @@ +testing fail 1: 1 +[10] %Error: t_uniqueif.v:73: Assertion failed in top.t: 'unique if' statement violated +%Error: t/t_uniqueif.v:73: Verilog $stop +Aborting... diff --git a/test_regress/t/t_uniqueif_fail1.pl b/test_regress/t/t_uniqueif_fail1.pl index 0f4d84c8b..b6bf6bc60 100755 --- a/test_regress/t/t_uniqueif_fail1.pl +++ b/test_regress/t/t_uniqueif_fail1.pl @@ -20,10 +20,7 @@ compile( execute( fails => $Self->{vlt_all}, - expect => -'.*%Error: t_uniqueif.v:\d+: Assertion failed in top.t: \'unique if\' statement violated -%Error: t/t_uniqueif.v:\d+: Verilog \$stop -.*', + expect_filename => $Self->{golden_filename}, ); ok(1); diff --git a/test_regress/t/t_uniqueif_fail2.out b/test_regress/t/t_uniqueif_fail2.out new file mode 100644 index 000000000..a98f79a6d --- /dev/null +++ b/test_regress/t/t_uniqueif_fail2.out @@ -0,0 +1,3 @@ +[10] %Error: t_uniqueif.v:81: Assertion failed in top.t: 'unique if' statement violated +%Error: t/t_uniqueif.v:81: Verilog $stop +Aborting... diff --git a/test_regress/t/t_uniqueif_fail2.pl b/test_regress/t/t_uniqueif_fail2.pl index 49fd1027f..2acdb6f37 100755 --- a/test_regress/t/t_uniqueif_fail2.pl +++ b/test_regress/t/t_uniqueif_fail2.pl @@ -20,10 +20,7 @@ compile( execute( fails => $Self->{vlt_all}, - expect => -'.*%Error: t_uniqueif.v:\d+: Assertion failed in top.t: \'unique if\' statement violated -%Error: t/t_uniqueif.v:\d+: Verilog \$stop -.*', + expect_filename => $Self->{golden_filename}, ); ok(1); diff --git a/test_regress/t/t_uniqueif_fail3.out b/test_regress/t/t_uniqueif_fail3.out new file mode 100644 index 000000000..ee89720b9 --- /dev/null +++ b/test_regress/t/t_uniqueif_fail3.out @@ -0,0 +1,3 @@ +[10] %Error: t_uniqueif.v:89: Assertion failed in top.t: 'unique if' statement violated +%Error: t/t_uniqueif.v:89: Verilog $stop +Aborting... diff --git a/test_regress/t/t_uniqueif_fail3.pl b/test_regress/t/t_uniqueif_fail3.pl index 5ac0fa625..0d91054e7 100755 --- a/test_regress/t/t_uniqueif_fail3.pl +++ b/test_regress/t/t_uniqueif_fail3.pl @@ -20,10 +20,7 @@ compile( execute( fails => $Self->{vlt_all}, - expect => -'.*%Error: t_uniqueif.v:\d+: Assertion failed in top.t: \'unique if\' statement violated -%Error: t/t_uniqueif.v:\d+: Verilog \$stop -.*', + expect_filename => $Self->{golden_filename}, ); ok(1); diff --git a/test_regress/t/t_uniqueif_fail4.out b/test_regress/t/t_uniqueif_fail4.out new file mode 100644 index 000000000..58bf8d268 --- /dev/null +++ b/test_regress/t/t_uniqueif_fail4.out @@ -0,0 +1,3 @@ +[10] %Error: t_uniqueif.v:101: Assertion failed in top.t: 'unique if' statement violated +%Error: t/t_uniqueif.v:101: Verilog $stop +Aborting... diff --git a/test_regress/t/t_uniqueif_fail4.pl b/test_regress/t/t_uniqueif_fail4.pl index 70f1622db..62fefae6c 100755 --- a/test_regress/t/t_uniqueif_fail4.pl +++ b/test_regress/t/t_uniqueif_fail4.pl @@ -20,10 +20,7 @@ compile( execute( fails => $Self->{vlt_all}, - expect => -'.*%Error: t_uniqueif.v:\d+: Assertion failed in top.t: \'unique if\' statement violated -%Error: t/t_uniqueif.v:\d+: Verilog \$stop -.*', + expect_filename => $Self->{golden_filename}, ); ok(1); diff --git a/test_regress/t/t_var_overwidth_bad.out b/test_regress/t/t_var_overwidth_bad.out new file mode 100644 index 000000000..c4b17aece --- /dev/null +++ b/test_regress/t/t_var_overwidth_bad.out @@ -0,0 +1,2 @@ +%Error: unknown:0: Testbench C set input 'clk' to value that overflows what the signal's width can fit +Aborting... diff --git a/test_regress/t/t_var_overwidth_bad.pl b/test_regress/t/t_var_overwidth_bad.pl index ae65608f2..8bd3599dc 100755 --- a/test_regress/t/t_var_overwidth_bad.pl +++ b/test_regress/t/t_var_overwidth_bad.pl @@ -16,9 +16,7 @@ compile( execute( fails => 1, - expect => -qr{%Error: unknown:0: Testbench C set input 'clk' to value that overflows what the signal's width can fit -Aborting....*} + expect_filename => $Self->{golden_filename}, ); ok(1);