diff --git a/src/verilog.y b/src/verilog.y
index 31dd8f000..4a79cc2eb 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -302,8 +302,8 @@ class AstSenTree;
 %token<fl>		yALWAYS_LATCH	"always_latch"
 %token<fl>		yAND		"and"
 %token<fl>		yASSERT		"assert"
-%token<fl>		yASSUME		"assume"
 %token<fl>		yASSIGN		"assign"
+%token<fl>		yASSUME		"assume"
 %token<fl>		yAUTOMATIC	"automatic"
 %token<fl>		yBEGIN		"begin"
 %token<fl>		yBIND		"bind"