diff --git a/.github/workflows/contributor.yml b/.github/workflows/contributor.yml index 7904a333b..80e0f9805 100644 --- a/.github/workflows/contributor.yml +++ b/.github/workflows/contributor.yml @@ -14,4 +14,4 @@ jobs: runs-on: ubuntu-22.04 steps: - uses: actions/checkout@v4 - - run: test_regress/t/t_dist_contributors.pl + - run: test_regress/t/t_dist_contributors.py diff --git a/Changes b/Changes index c8472df19..34e5f038c 100644 --- a/Changes +++ b/Changes @@ -11,6 +11,10 @@ contributors that suggested a given feature are shown in []. Thanks! Verilator 5.029 devel ========================== +**Major:** + +* Self-tests have been converted to Python, run `{testname}.py` instead of `{testname}.pl`. + **Minor:** * Support IEEE-compliant intra-assign delays (#3711) (#5441). [Krzysztof Bieganski, Antmicro Ltd.] diff --git a/Makefile.in b/Makefile.in index bda52e1bc..30f42e5e4 100644 --- a/Makefile.in +++ b/Makefile.in @@ -52,6 +52,7 @@ INSTALL_PROGRAM = @INSTALL_PROGRAM@ INSTALL_DATA = @INSTALL_DATA@ MAKEINFO = makeinfo POD2TEXT = pod2text +PYTHON3 = @PYTHON3@ MKINSTALLDIRS = $(SHELL) $(srcdir)/src/mkinstalldirs # Version (for docs/guide/conf.py) @@ -156,7 +157,7 @@ msg_test: all_nomsg .PHONY: test ifeq ($(CFG_WITH_LONGTESTS),yes) # Local... Else don't burden users test: smoke-test test_regress -# examples is part of test_regress's test_regress/t/t_a2_examples.pl +# examples is part of test_regress's test_regress/t/t_a2_examples.py # (because that allows it to run in parallel with other test_regress's) else test: smoke-test examples @@ -168,8 +169,8 @@ endif @echo smoke-test: all_nomsg - test_regress/t/t_a1_first_cc.pl - test_regress/t/t_a2_first_sc.pl + test_regress/t/t_a1_first_cc.py + test_regress/t/t_a2_first_sc.py test_regress: all_nomsg $(MAKE) -C test_regress @@ -412,7 +413,7 @@ analyzer-include: scan-build $(MAKE) -k examples format: - $(MAKE) -j 4 clang-format yapf format-pl-exec + $(MAKE) -j 4 clang-format yapf format-exec CLANGFORMAT = clang-format-14 CLANGFORMAT_FLAGS = -i @@ -423,6 +424,7 @@ clang-format: || echo "*** You are not using clang-format-14, indents may differ from master's ***" $(CLANGFORMAT) $(CLANGFORMAT_FLAGS) $(CLANGFORMAT_FILES) +# Python programs, subject to format and lint PY_PROGRAMS = \ bin/verilator_ccache_report \ bin/verilator_difftree \ @@ -441,6 +443,7 @@ PY_PROGRAMS = \ src/flexfix \ src/vlcovgen \ src/.gdbinit.py \ + test_regress/*.py \ test_regress/t/*.pf \ nodist/clang_check_attributes \ nodist/code_coverage \ @@ -450,36 +453,44 @@ PY_PROGRAMS = \ nodist/install_test \ nodist/log_changes \ +# Python files, subject to format but not lint PY_FILES = \ $(PY_PROGRAMS) \ nodist/code_coverage.dat \ + test_regress/t/*.py \ -PY_FILES_NOLINT = \ +# Python files, test_regress tests +PY_TEST_FILES = \ + test_regress/t/*.py \ YAPF = yapf3 YAPF_FLAGS = -i --parallel yapf: - $(YAPF) $(YAPF_FLAGS) $(PY_FILES) $(PY_FILES_NOLINT) + $(YAPF) $(YAPF_FLAGS) $(PY_FILES) PYLINT = pylint -PYLINT_FLAGS = --score=n --disable=R0801 +PYLINT_FLAGS = --recursive=n --score=n --disable=R0801 +PYLINT_TEST_FLAGS = $(PYLINT_FLAGS) --disable=C0103,C0114,C0116,C0209,C0411,C0413,C0301,R0801,R0912,R0915,R0916,R1702,W0511,W0621 RUFF = ruff RUFF_FLAGS = check --ignore=E402,E501,E701 # "make -k" so can see all tool result errors lint-py: - $(MAKE) -k lint-py-pylint lint-py-ruff + $(MAKE) -k lint-py-pylint lint-py-pylint-tests lint-py-ruff lint-py-pylint: $(PYLINT) $(PYLINT_FLAGS) $(PY_PROGRAMS) +lint-py-pylint-tests: + $(PYLINT) $(PYLINT_TEST_FLAGS) $(PY_TEST_FILES) | $(PYTHON3) nodist/lint_py_test_filter + lint-py-ruff: $(RUFF) $(RUFF_FLAGS) $(PY_PROGRAMS) -format-pl-exec: - -chmod a+x test_regress/t/*.pl +format-exec: + -chmod a+x test_regress/t/*.py install-msg: @echo diff --git a/ci/ci-install.bash b/ci/ci-install.bash index 0b1439f8f..37a4feaed 100755 --- a/ci/ci-install.bash +++ b/ci/ci-install.bash @@ -68,9 +68,6 @@ if [ "$CI_BUILD_STAGE_NAME" = "build" ]; then sudo apt-get install bear mold || sudo apt-get install bear mold fi - if [ "$COVERAGE" = 1 ]; then - yes yes | sudo cpan -fi Parallel::Forker - fi elif [ "$CI_OS_NAME" = "osx" ]; then brew update brew install ccache perl gperftools @@ -94,7 +91,7 @@ elif [ "$CI_BUILD_STAGE_NAME" = "test" ]; then # libfl-dev needed for internal coverage's test runs sudo apt-get install gdb gtkwave lcov libfl-dev ccache jq z3 || sudo apt-get install gdb gtkwave lcov libfl-dev ccache jq z3 - # Required for test_regress/t/t_dist_attributes.pl + # Required for test_regress/t/t_dist_attributes.py if [ "$CI_RUNS_ON" = "ubuntu-22.04" ] || [ "$CI_RUNS_ON" = "ubuntu-24.04" ]; then sudo apt-get install python3-clang mold || sudo apt-get install python3-clang mold @@ -114,10 +111,6 @@ elif [ "$CI_BUILD_STAGE_NAME" = "test" ]; then fatal "Unknown os: '$CI_OS_NAME'" fi # Common installs - if [ "$CI_RUNS_ON" != "ubuntu-14.04" ]; then - CI_CPAN_REPO=https://cpan.org - fi - yes yes | sudo cpan -M $CI_CPAN_REPO -fi Parallel::Forker install-vcddiff # Workaround -fsanitize=address crash sudo sysctl -w vm.mmap_rnd_bits=28 diff --git a/ci/ci-script.bash b/ci/ci-script.bash index eabffb991..bd9c9d41c 100755 --- a/ci/ci-script.bash +++ b/ci/ci-script.bash @@ -61,6 +61,7 @@ elif [ "$CI_BUILD_STAGE_NAME" = "test" ]; then # Run tests export VERILATOR_TEST_NO_CONTRIBUTORS=1 # Separate workflow check + export VERILATOR_TEST_NO_LINT_PY=1 # Separate workflow check if [ "$CI_OS_NAME" = "osx" ]; then export VERILATOR_TEST_NO_GDB=1 # Pain to get GDB to work on OS X diff --git a/ci/docker/buildenv/Dockerfile b/ci/docker/buildenv/Dockerfile index 88e39b85f..7e13feca8 100644 --- a/ci/docker/buildenv/Dockerfile +++ b/ci/docker/buildenv/Dockerfile @@ -51,8 +51,6 @@ RUN apt-get update \ WORKDIR /tmp -RUN cpan install -fi Parallel::Forker - RUN git clone https://github.com/veripool/vcddiff.git && \ make -C vcddiff && \ cp -p vcddiff/vcddiff /usr/local/bin/vcddiff && \ diff --git a/configure.ac b/configure.ac index dc0c1248f..1a8206609 100644 --- a/configure.ac +++ b/configure.ac @@ -199,6 +199,8 @@ AC_PATH_PROG(PYTHON3,python3) if test "x$PYTHON3" = "x" ; then AC_MSG_ERROR([Cannot find "python3" in your PATH, please install it]) fi +python3_version=$($PYTHON3 --version | head -1) +AC_MSG_RESULT([$PYTHON3 --version = $python3_version]) AC_PATH_PROG(LEX,flex) if test "x$LEX" = "x" ; then diff --git a/docs/guide/contributing.rst b/docs/guide/contributing.rst index d8f6dc35e..aea0059f5 100644 --- a/docs/guide/contributing.rst +++ b/docs/guide/contributing.rst @@ -29,18 +29,18 @@ directory, as follows: .. code-block:: bash cd test_regress - cp -p t/t_EXAMPLE.pl t/t_BUG.pl + cp -p t/t_EXAMPLE.py t/t_BUG.py cp -p t/t_EXAMPLE.v t/t_BUG.v There are many hints on how to write a good test in the -:file:`test_regress/driver.pl` documentation which can be seen by running: +:file:`test_regress/driver.py` documentation which can be seen by running: .. code-block:: bash cd $VERILATOR_ROOT # Need the original distribution kit - test_regress/driver.pl --help + test_regress/driver.py --help -Edit :file:`t/t_BUG.pl` to suit your example; you can do anything you want +Edit :file:`t/t_BUG.py` to suit your example; you can do anything you want in the Verilog code there; just make sure it retains the single clk input and no outputs. Now, the following should fail: @@ -48,15 +48,15 @@ and no outputs. Now, the following should fail: cd $VERILATOR_ROOT # Need the original distribution kit cd test_regress - t/t_BUG.pl # Run on Verilator - t/t_BUG.pl --debug # Run on Verilator, passing --debug to Verilator - t/t_BUG.pl --vcs # Run on VCS simulator - t/t_BUG.pl --nc|--iv|--ghdl # Likewise on other simulators + t/t_BUG.py # Run on Verilator + t/t_BUG.py --debug # Run on Verilator, passing --debug to Verilator + t/t_BUG.py --vcs # Run on VCS simulator + t/t_BUG.py --nc|--iv|--ghdl # Likewise on other simulators The test driver accepts a number of options, many of which mirror the main Verilator options. For example the previous test could have been run with debugging enabled. The full set of test options can be seen by running -:command:`driver.pl --help` as shown above. +:command:`driver.py --help` as shown above. Finally, report the bug at `Verilator Issues `_. The bug will become publicly visible; if diff --git a/docs/guide/install.rst b/docs/guide/install.rst index ecc06bc48..6bcc43f10 100644 --- a/docs/guide/install.rst +++ b/docs/guide/install.rst @@ -130,7 +130,6 @@ Those developing Verilator itself may also want these (see internals.rst): sudo pip3 install sphinx sphinx_rtd_theme sphinxcontrib-spelling breathe ruff sudo pip3 install git+https://github.com/antmicro/astsee.git cpan install Pod::Perldoc - cpan install Parallel::Forker Install SystemC diff --git a/docs/internals.rst b/docs/internals.rst index 89502b1d9..ba88d7976 100644 --- a/docs/internals.rst +++ b/docs/internals.rst @@ -1472,9 +1472,6 @@ For all tests to pass, you must install the following packages: - SystemC to compile the SystemC outputs, see http://systemc.org -- Parallel::Forker from CPAN to run tests in parallel; you can install - this with e.g. "sudo cpan install Parallel::Forker". - - vcddiff to find differences in VCD outputs. See the readme at https://github.com/veripool/vcddiff @@ -1484,7 +1481,7 @@ For all tests to pass, you must install the following packages: Controlling the Test Driver --------------------------- -The test driver script `driver.pl` runs tests; see the `Test Driver` +The test driver script `driver.py` runs tests; see the `Test Driver` section. The individual test drivers are written in Perl; see `Test Language`. @@ -1497,7 +1494,7 @@ A specific regression test can be executed manually. To start the :: - test_regress/t/t_EXAMPLE.pl + test_regress/t/t_EXAMPLE.py Regression Testing for Developers @@ -1517,13 +1514,6 @@ Developers will also want to call ./configure with two extra flags: disabled by default, as SystemC installation problems would otherwise falsely indicate a Verilator problem. -When enabling the long tests, some additional Perl modules are needed, -which you can install using cpan. - -:: - - cpan install Parallel::Forker - There are some traps to avoid when running regression tests - When checking the MANIFEST, the test will fail on unexpected code in the @@ -1871,7 +1861,7 @@ represent the pointers (``op1p``, ``op2p``, etc) between the nodes. Debugging with GDB ------------------ -The `driver.pl` script accepts ``--debug --gdb`` to start +The `driver.py` script accepts ``--debug --gdb`` to start Verilator under gdb and break when an error is hit, or the program is about to exit. You can also use ``--debug --gdbbt`` to just backtrace and then exit gdb. To debug the Verilated executable, use ``--gdbsim``. @@ -1882,7 +1872,7 @@ can use ``--debug`` and look at the underlying invocation of :: - t/t_alw_dly.pl --debug + t/t_alw_dly.py --debug shows it invokes the command: @@ -1979,7 +1969,7 @@ Generally, what would you do to add a new feature? Follow the convention described above about the AstNode type hierarchy. Ordering of definitions is enforced by ``astgen``. -5. Now you can run ``test_regress/t/t_.pl --debug`` and it'll +5. Now you can run ``test_regress/t/t_.py --debug`` and it'll probably fail, but you'll see a ``test_regress/obj_dir/t_/*.tree`` file which you can examine to see if the parsing worked. See also the sections above on debugging. @@ -2028,7 +2018,7 @@ IEEE 1800-2023 33 Config Test Driver =========== -This section documents the test driver script, `driver.pl`. driver.pl +This section documents the test driver script, `driver.py`. driver.py invokes Verilator or another simulator on each test file. For test file contents description see `Test Language`. @@ -2040,7 +2030,7 @@ the regression tests with OBJCACHE enabled and in parallel on a machine with many cores. See the -j option and OBJCACHE environment variable. -driver.pl Non-Scenario Arguments +driver.py Non-Scenario Arguments -------------------------------- --benchmark [] @@ -2129,7 +2119,7 @@ driver.pl Non-Scenario Arguments For tests using the standard C++ wrapper, enable runtime debug mode. -driver.pl Scenario Arguments +driver.py Scenario Arguments ---------------------------- The following options control which simulator is used, and which tests are @@ -2171,7 +2161,7 @@ simultaneously. Run Xilinx XSim simulator tests. -driver.pl Environment +driver.py Environment --------------------- HARNESS_UPDATE_GOLDEN @@ -2231,30 +2221,30 @@ VERILATOR_XVLOG Test Language ============= -This section describes the format of the ``test_regress/t/*.pl`` test -language files, executed by `driver.pl`. +This section describes the format of the ``test_regress/t/*.py`` test +language files, executed by `driver.py`. Test Language Summary --------------------- For convenience, a summary of the most commonly used features is provided here, with a reference in a later section. All test files typically have a -call to the ``lint`` or ``compile`` subroutine to compile the test. For -run-time tests, this is followed by a call to the ``execute`` -subroutine. Both of these functions can optionally be provided with -arguments specifying additional options. +call to the ``test.lint`` or ``test.compile`` methods to compile the +test. For run-time tests, this is followed by a call to the +``test.execute`` method. Both of these functions can optionally be provided +with arguments specifying additional options. -If those complete, the script calls ``ok`` to increment the count of -successful tests and then returns 1 as its result. +If those complete, the script calls ``test.passes`` to increment the count +of successful tests. -The driver.pl script assumes by default that the source Verilog file name +The driver.py script assumes by default that the source Verilog file name matches the test script name. So a test whose driver is -``t/t_mytest.pl`` will expect a Verilog source file ``t/t_mytest.v``. +``t/t_mytest.py`` will expect a Verilog source file ``t/t_mytest.v``. This can be changed using the ``top_filename`` subroutine, for example :: - top_filename("t/t_myothertest.v"); + test.top_filename = "t/t_myothertest.v" By default, all tests will run with major simulators (Icarus Verilog, NC, VCS, ModelSim, etc.) as well as Verilator, to allow results to be @@ -2263,26 +2253,25 @@ can use the following: :: - scenarios(vlt => 1); + test.scenarios('vlt') -Of the many options that can be set through arguments to ``compiler`` and -``execute``, the following are particularly useful: +Of the many options that can be set through arguments to ``test.compiler`` +and ``test.execute``, the following are particularly useful: ``verilator_flags2`` A list of flags to be passed to verilator when compiling. ``fails`` - Set to 1 to indicate that the compilation or execution is intended to fail. + Set true to indicate that the compilation or execution is intended to fail. For example, the following would specify that compilation requires two defines and is expected to fail. :: - compile( + test.compile( verilator_flags2 => ["-DSMALL_CLOCK -DGATED_COMMENT"], - fails => 1, - ); + fails = True) Hints On Writing Tests ---------------------- @@ -2295,10 +2284,10 @@ same name as the test, but with .cpp as suffix :: - compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"], ); + test.compile( + make_top_shell=False, + make_main=False, + verilator_flags2=["--exe", test.t_dir + "/" + test.name + ".cpp"]) Tests should be self-checking, rather than producing lots of output. If a test succeeds it should print ``*-* All Finished *-*`` to standard output @@ -2338,9 +2327,8 @@ compile time, it is the only option. For example: :: compile( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); + fails=True, + expect_filename=test.golden_filename) Note ``expect_filename`` strips some debugging information from the logfile when comparing. @@ -2349,9 +2337,9 @@ when comparing. Test Language Compile/Lint/Run Arguments ---------------------------------------- -This section describes common arguments to ``compile()``, ``lint()``, and -``run()``. The full list of arguments can be found by looking at the -``driver.pl`` source code. +This section describes common arguments to ``test.compile``, ``test.lint``, +and ``test.run``. The full list of arguments can be found by looking at +the ``driver.py`` source code. all_run_flags A list of flags to be passed when running the simulator (Verilated model diff --git a/nodist/code_coverage b/nodist/code_coverage index ce7e5270f..2b9a59fb9 100755 --- a/nodist/code_coverage +++ b/nodist/code_coverage @@ -350,10 +350,10 @@ SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""") parser.add_argument('--debug', action='store_true', help='enable debug') parser.add_argument('--hashset', action='store', - help='pass test hashset onto driver.pl test harness') + help='pass test hashset onto driver.py test harness') parser.add_argument('--scenarios', action='store', - help='pass test scenarios onto driver.pl test harness') + help='pass test scenarios onto driver.py test harness') parser.add_argument('--stages', '--stage', action='store', diff --git a/nodist/lint_py_test_filter b/nodist/lint_py_test_filter new file mode 100755 index 000000000..813d11fc0 --- /dev/null +++ b/nodist/lint_py_test_filter @@ -0,0 +1,59 @@ +#!/usr/bin/env python3 +# pylint: disable= +###################################################################### + +import argparse +import re +import sys + +SUPPRESSES = [ + "**********", + "E0602: Undefined variable 'test' (undefined-variable)", + "E0602: Undefined variable 're' (undefined-variable)", + "E0602: Undefined variable 'os' (undefined-variable)", + "E0602: Undefined variable 'glob' (undefined-variable)", + "W0611: Unused import vltest_bootstrap (unused-import)", + ] + +###################################################################### + +def process(): + anymsg = False + for line in sys.stdin: + line = line.rstrip(); + show = True + for msg in SUPPRESSES: + if msg in line: + show = False + continue + if show: + print(line) + anymsg = True + + if anymsg: + sys.exit("%Error: See messages above") + +####################################################################### +####################################################################### + +parser = argparse.ArgumentParser( + allow_abbrev=False, + formatter_class=argparse.RawDescriptionHelpFormatter, + description="""lint_py_test_filter is used to filter +pylint output for expected errors in Verilator test_regress/*.py tests.""", + epilog="""Copyright 2024-2024 by Wilson Snyder. This program is free software; you +can redistribute it and/or modify it under the terms of either the GNU +Lesser General Public License Version 3 or the Perl Artistic License +Version 2.0. + +SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""") + +parser.add_argument('--debug', action='store_true', help='enable debug') + +Args = parser.parse_args() +process() + +###################################################################### +# Local Variables: +# compile-command: "cd .. ; make lint-py-pylint-tests" +# End: diff --git a/test_regress/CMakeLists.txt b/test_regress/CMakeLists.txt index ad09a1282..be1adb6ed 100644 --- a/test_regress/CMakeLists.txt +++ b/test_regress/CMakeLists.txt @@ -19,7 +19,7 @@ set(TEST_REQUIRED_VARS NAME CSOURCES OPT_FAST OPT_GLOBAL VERILATOR_SOURCES SYSTEMC VERBOSE VERILATION) foreach(var ${TEST_REQUIRED_VARS}) if (NOT DEFINED TEST_${var}) - message(FATAL_ERROR "TEST_${var} not defined. This CMakeLists.txt file is meant to be run by driver.pl.") + message(FATAL_ERROR "TEST_${var} not defined. This CMakeLists.txt file is meant to be run by driver.py.") endif() endforeach() diff --git a/test_regress/Makefile b/test_regress/Makefile index 0497590c1..509d2624a 100644 --- a/test_regress/Makefile +++ b/test_regress/Makefile @@ -48,30 +48,30 @@ DRIVER_HASHSET ?= .PHONY: test test: - $(PERL) driver.pl $(DRIVER_FLAGS) $(SCENARIOS) $(DRIVER_HASHSET) + $(PYTHON3) driver.py $(DRIVER_FLAGS) $(SCENARIOS) $(DRIVER_HASHSET) ###################################################################### vcs: - $(PERL) driver.pl $(DRIVER_FLAGS) --vcs --stop + $(PYTHON3) driver.py $(DRIVER_FLAGS) --vcs --stop ###################################################################### nc: - $(PERL) driver.pl $(DRIVER_FLAGS) --nc --stop + $(PYTHON3) driver.py $(DRIVER_FLAGS) --nc --stop ###################################################################### vlt: - $(PERL) driver.pl $(DRIVER_FLAGS) --vlt --stop + $(PYTHON3) driver.py $(DRIVER_FLAGS) --vlt --stop vltmt: - $(PERL) driver.pl $(DRIVER_FLAGS) --vltmt --stop + $(PYTHON3) driver.py $(DRIVER_FLAGS) --vltmt --stop ###################################################################### random: - $(PERL) driver.pl $(DRIVER_FLAGS) --optimize : --stop + $(PYTHON3) driver.py $(DRIVER_FLAGS) --optimize : --stop random_forever: while ( VERILATOR_NO_DEBUG=1 CPPFLAGS_ADD=-Wno-error $(MAKE) random ) ; do \ diff --git a/test_regress/driver.py b/test_regress/driver.py new file mode 100755 index 000000000..a180611f6 --- /dev/null +++ b/test_regress/driver.py @@ -0,0 +1,2830 @@ +#!/usr/bin/env python3 +# pylint: disable=C0103,C0114,C0115,C0116,C0209,C0302,R0902,R0903,R0904,R0912,R0913,R0914,R0915,R0916,W0212,W0511,W0603,W1201 +###################################################################### + +import argparse +import collections +import glob +import hashlib +import json +import logging +import multiprocessing +import os +import pickle +import platform +import re +import runpy +import shutil +import signal +import subprocess +import sys +import time + +from functools import lru_cache # Eventually use python 3.9's cache +from pprint import pformat, pprint +from packaging import version + +if False: # pylint: disable=using-constant-test + pprint(pformat("Ignored")) # Prevent unused warning + +# Map of all scenarios, with the names used to enable them +All_Scenarios = { + # yapf: disable + 'dist': ['dist'], + 'atsim': ['simulator', 'simulator_st', 'atsim'], + 'ghdl': ['linter', 'simulator', 'simulator_st', 'ghdl'], + 'iv': ['simulator', 'simulator_st', 'iv'], + 'ms': ['linter', 'simulator', 'simulator_st', 'ms'], + 'nc': ['linter', 'simulator', 'simulator_st', 'nc'], + 'vcs': ['linter', 'simulator', 'simulator_st', 'vcs'], + 'xrun': ['linter', 'simulator', 'simulator_st', 'xrun'], + 'xsim': ['linter', 'simulator', 'simulator_st', 'xsim'], + 'vlt': ['linter', 'simulator', 'simulator_st', 'vlt_all', 'vlt'], + 'vltmt': ['simulator', 'vlt_all', 'vltmt'], + # yapf: enable +} + +# Globals +test = None +Arg_Tests = [] +Arg_Driver_Verilator_Flags = [] + +# So an 'import vltest_bootstrap' inside test files will do nothing +sys.modules['vltest_bootstrap'] = {} + +####################################################################### +####################################################################### +# Decorators + + +class staticproperty(property): + + def __get__(self, owner_self, owner_cls): + return self.fget() + + +####################################################################### +####################################################################### +# VtOs -- OS extensions + + +class VtOs: + + @staticmethod + def delenv(var: str) -> None: + """Delete environment variable, if exists""" + if var in os.environ: + del os.environ[var] + + @staticmethod + def getenv_def(var: str, default=None) -> str: + """Return environment variable, returning default if does not exist""" + if var in os.environ: + return os.environ[var] + return default + + @staticmethod + def mkdir_ok(path: str) -> None: + """Make directory, no error if exists""" + try: + os.mkdir(path) + except FileExistsError: + pass + + @staticmethod + def run_capture(command: str, check=True) -> str: + """Run a command and return results""" + proc = subprocess.run([command], capture_output=True, text=True, shell=True, check=False) + if check and proc.returncode: + sys.exit("%Error: command failed '" + command + "':\n" + proc.stderr + proc.stdout) + return str(proc.stdout) + + @staticmethod + def unlink_ok(filename: str) -> None: + """Unlink a file, no error if fails""" + try: + os.unlink(filename) + except OSError: + pass + + +####################################################################### +####################################################################### +# Capabilities -- What OS/Verilator is built to support + + +class Capabilities: + + # @lru_cache(maxsize=1024) broken with @staticmethod on older pythons we use + _cached_cmake_version = None + _cached_cxx_version = None + _cached_have_coroutines = None + _cached_have_gdb = None + _cached_have_sc = None + _cached_have_solver = None + _cached_make_version = None + + @staticproperty + def cmake_version() -> str: # pylint: disable=no-method-argument + if Capabilities._cached_cmake_version is None: + out = VtOs.run_capture('cmake --version', check=False) + match = re.search(r'cmake version (\d+)\.(\d+)', out, re.IGNORECASE) + if match: + Capabilities._cached_cmake_version = match.group(1) + "." + match.group(2) + else: + Capabilities._cached_cmake_version = 0 + return Capabilities._cached_cmake_version + + @staticproperty + def cxx_version() -> str: # pylint: disable=no-method-argument + if Capabilities._cached_cxx_version is None: + Capabilities._cached_cxx_version = VtOs.run_capture(os.environ['MAKE'] + " -C " + + os.environ['TEST_REGRESS'] + + " -f Makefile print-cxx-version", + check=False) + + return Capabilities._cached_cxx_version + + @staticproperty + def have_coroutines() -> bool: # pylint: disable=no-method-argument + if Capabilities._cached_have_coroutines is None: + Capabilities._cached_have_coroutines = bool( + Capabilities._verilator_get_supported('COROUTINES')) + return Capabilities._cached_have_coroutines + + @staticproperty + def have_gdb() -> bool: # pylint: disable=no-method-argument + if Capabilities._cached_have_gdb is None: + out = VtOs.run_capture('gdb --version 2>/dev/null', check=False) + Capabilities._cached_have_gdb = bool('Copyright' in out) + return Capabilities._cached_have_gdb + + @staticproperty + def have_sc() -> bool: # pylint: disable=no-method-argument + if Capabilities._cached_have_sc is None: + if 'SYSTEMC' in os.environ: + Capabilities._cached_have_sc = True + elif 'SYSTEMC_INCLUDE' in os.environ: + Capabilities._cached_have_sc = True + elif 'CFG_HAVE_SYSTEMC' in os.environ: + Capabilities._cached_have_sc = True + else: + Capabilities._cached_have_sc = bool( + Capabilities._verilator_get_supported('SYSTEMC')) + return Capabilities._cached_have_sc + + @staticproperty + def have_solver() -> bool: # pylint: disable=no-method-argument + if Capabilities._cached_have_solver is None: + out = VtOs.run_capture('(z3 --help || cvc5 --help || cvc4 --help) 2>/dev/null', + check=False) + Capabilities._cached_have_solver = bool('Usage' in out) + return Capabilities._cached_have_solver + + @staticproperty + @lru_cache(maxsize=1024) + def make_version() -> str: # pylint: disable=no-method-argument + if Capabilities._cached_make_version is None: + out = VtOs.run_capture(os.environ['MAKE'] + ' --version', check=False) + match = re.search(r'make ([0-9]+\.[0-9]+)', out, flags=re.IGNORECASE) + if match: + Capabilities._cached_make_version = match.group(1) + else: + Capabilities._cached_make_version = -1 + return Capabilities._cached_make_version + + # Fetch + @staticmethod + def warmup_cache() -> None: + _ignore = Capabilities.have_coroutines + _ignore = Capabilities.have_gdb + _ignore = Capabilities.have_sc + _ignore = Capabilities.have_solver + + # Internals + + @staticmethod + def _verilator_get_supported(feature) -> str: + # Returns if given feature is supported + cmd = "perl " + os.environ['VERILATOR_ROOT'] + "/bin/verilator -get-supported " + feature + out = VtOs.run_capture(cmd, check=False).strip() + if out == '1': + return True + if out in ('', '0'): + return False + sys.exit("%Error: couldn't verilator_get_supported: " + cmd + "\n" + out) + + +####################################################################### +####################################################################### +# Forker class - run multprocess pool of processes +# Similar interface to Perl's Parallel::Forker. + + +class Forker: + + class Process: + + def __init__(self, _id, name, scenario, rerun_skipping, run_pre_start, run_on_start, + run_on_finish): + self.fail_max_skip = False + self.id = _id + self.name = name + self.scenario = scenario + self.rerun_skipping = rerun_skipping + self.run_pre_start = run_pre_start + self.run_on_start = run_on_start + self.run_on_finish = run_on_finish + self.mprocess = None # Set once call run() + + @property + def pid(self) -> int: + return self.mprocess.pid + + @property + def exitcode(self) -> int: + return self.mprocess.exitcode + + def __init__(self, max_processes): + self._max_processes = max_processes + self._id_next = 0 + self._left = collections.deque() # deque of Process + self._running = {} # key of pid, value of Process + + def is_any_left(self) -> bool: + return len(self._left) > 0 or self.num_running() > 0 + + def max_proc(self, n: int) -> None: + self._max_processes = n + + def poll(self) -> None: + # We don't use SIGCHLD as conflicted with other handler, instead just poll + completed = [] # Need two passes to avoid changing the list we are iterating + nrunning = 0 + for process in self._running.values(): + if process.exitcode is not None: + completed.append(process) + else: + nrunning += 1 + for process in completed: + self._finished(process) + while len(self._left) and nrunning < self._max_processes: + process = self._left.pop() + self._run(process) + nrunning += 1 + + def running(self) -> list: + return self._running.values() + + def num_running(self) -> int: + return len(self._running) + + def schedule(self, name, scenario, rerun_skipping, run_pre_start, run_on_start, run_on_finish): + # print("-Forker::schedule: [" + name + "]") + process = Forker.Process(self._id_next, + name=name, + scenario=scenario, + rerun_skipping=rerun_skipping, + run_pre_start=run_pre_start, + run_on_start=run_on_start, + run_on_finish=run_on_finish) + self._id_next += 1 + self._left.append(process) + + def kill_tree_all(self) -> None: + # print("-Forker: kill_tree_all") + for process in self._running.values(): + process.mprocess.kill() + + def _run(self, process) -> None: + # print("-Forker: [" + process.name + "] run_pre_start") + process.run_pre_start(process) + + ctx = multiprocessing.get_context('fork') + process.mprocess = ctx.Process(target=lambda: self.child_start(process)) + process.mprocess.start() + + # print("-Forker: [" + process.name + "] RUNNING pid=" + str(process.pid)) + self._running[process.pid] = process + + @staticmethod + def child_start(process) -> None: + # Runs in context of child + # print("-Forker: [" + process.name + "] run_on_start") + process.run_on_start(process) + # print("-Forker: [" + process.name + "] FINISHED run_on_start") + sys.exit(0) + # Don't close anything + + def _finished(self, process) -> None: + del self._running[process.pid] + # print("-Forker: [" + process.name + "] run_on_finish exitcode=" + str(process.exitcode)) + process.run_on_finish(process) + process.mprocess.close() + + +####################################################################### +####################################################################### +# Runner class + + +class Runner: + + def __init__(self, driver_log_filename, quiet, ok_cnt=0, fail1_cnt=0, skip_cnt=0): + self.driver_log_filename = driver_log_filename + self.quiet = quiet + # Counts + self.all_cnt = 0 + self.left_cnt = 0 + self.ok_cnt = ok_cnt + self.fail1_cnt = fail1_cnt + self.fail_cnt = 0 + self.skip_cnt = skip_cnt + self.skip_msgs = [] + self.fail_msgs = [] + self.fail_tests = [] + self._last_proc_finish_time = 0 + self._last_summary_time = 0 + self._last_summary_left = 0 + self._running_ids = {} + self._msg_fail_max_skip = False + Runner.runner = self + + def one_test(self, py_filename: str, scenario: str, rerun_skipping=False) -> None: + self.all_cnt += 1 + self.left_cnt += 1 + forker.schedule(name=py_filename, + scenario=scenario, + rerun_skipping=rerun_skipping, + run_pre_start=self._run_pre_start_static, + run_on_start=self._run_on_start_static, + run_on_finish=self._run_on_finish_static) + + @staticmethod + def _run_pre_start_static(process) -> None: + Runner.runner._run_pre_start(process) # pylint: disable=protected-access + + def _run_pre_start(self, process) -> None: + # Running in context of parent, before run_on_start + # Make an identifier that is unique across all current running jobs + i = 1 + while i in self._running_ids: + i += 1 + process.running_id = i + self._running_ids[process.running_id] = 1 + if Args.fail_max and Args.fail_max <= self.fail_cnt: + if not self._msg_fail_max_skip: + self._msg_fail_max_skip = True + print("== Too many test failures; exceeded --fail-max\n", file=sys.stderr) + process.fail_max_skip = 1 + + @staticmethod + def _run_on_start_static(process) -> None: + Runner.runner._run_on_start(process) # pylint: disable=protected-access + + def _run_on_start(self, process) -> None: + # Running in context of child, so can't pass data to parent directly + if self.quiet: + sys.stdout = open(os.devnull, 'w') # pylint: disable=R1732,unspecified-encoding + sys.stderr = open(os.devnull, 'w') # pylint: disable=R1732,unspecified-encoding + + print("=" * 70) + global test + test = VlTest(py_filename=process.name, + scenario=process.scenario, + running_id=process.running_id) + test.oprint("=" * 50) + test._prep() + if process.rerun_skipping: + print(" ---------- Earlier logfiles below; test was rerunnable = 0\n") + os.system("cat $test->{obj_dir}/*.log") + print(" ---------- Earlier logfiles above; test was rerunnable = 0\n") + elif process.fail_max_skip: + test.skip("Too many test failures; exceeded --fail-max") + else: + VtOs.unlink_ok(test._status_filename) + test._read() + # Don't put anything other than _exit after _read, + # as may call _exit via another path + test._exit() + + @staticmethod + def _run_on_finish_static(process) -> None: + Runner.runner._run_on_finish(process) # pylint: disable=protected-access + + def _run_on_finish(self, process) -> None: + # Running in context of parent + global test + test = VlTest(py_filename=process.name, + scenario=process.scenario, + running_id=process.running_id) + test._read_status() + if test.ok: + self.ok_cnt += 1 + elif test._scenario_off and not test.errors: + pass + elif test._skips and not test.errors and not test.errors_keep_going: + self.skip_msgs.append("\t#" + test.soprint("-Skip: " + test._skips)) + self.skip_cnt += 1 + else: + error_msg = test.errors if test.errors else test.errors_keep_going + test.oprint("FAILED: " + error_msg) + j = " -j" if Args.jobs else "" + makecmd = VtOs.getenv_def('VERILATOR_MAKE', os.environ['MAKE']) + j + " &&" + upperdir = 'test_regress/' if re.search(r'test_regress', os.getcwd()) else '' + self.fail_msgs.append("\t#" + test.soprint("%Error: " + error_msg) + "\t\t" + makecmd + + " " + upperdir + test.py_filename + + ' '.join(self._manual_args()) + " --" + test.scenario + "\n") + self.fail_tests.append(test) + self.fail_cnt += 1 + self.report(self.driver_log_filename) + other = "" + for proc in forker.running(): + other += " " + proc.name + if other != "" and not Args.quiet: + test.oprint("Simultaneous running tests:" + other) + if Args.stop: + sys.exit("%Error: --stop and errors found\n") + + self.left_cnt -= 1 + self._last_proc_finish_time = time.time() + if process.running_id: + del self._running_ids[process.running_id] + + def wait_and_report(self) -> None: + self.print_summary(force=True) + # Wait for all children to finish + while forker.is_any_left(): + forker.poll() + if not interactive_debugger: + self.print_summary(force=False) + time.sleep(0.1) + self.report(None) + self.report(self.driver_log_filename) + + def report(self, filename: str) -> None: + if filename: + with open(filename, "w", encoding="utf8") as fh: + self._report_fh(fh) + else: + self._report_fh(sys.stdout) + + def _report_fh(self, fh) -> None: + fh.write("\n") + fh.write('=' * 70 + "\n") + for f in sorted(self.fail_msgs): + fh.write(f.strip() + "\n") + for f in sorted(self.skip_msgs): + fh.write(f.strip() + "\n") + if self.fail_cnt: + sumtxt = 'FAILED' + elif self.skip_cnt: + sumtxt = 'PASSED w/SKIPS' + else: + sumtxt = 'PASSED' + fh.write("==TESTS DONE, " + sumtxt + ": " + self.sprint_summary() + "\n") + + def print_summary(self, force=False): + change = self._last_summary_left != self.left_cnt + if (force or ((time.time() - self._last_summary_time) >= 15) + or (not self.quiet and change)): + self._last_summary_left = self.left_cnt + self._last_summary_time = time.time() + print("==SUMMARY: " + self.sprint_summary(), file=sys.stderr) + + if (self._last_proc_finish_time != 0 + and ((time.time() - self._last_proc_finish_time) > 15)): + self._last_proc_finish_time = time.time() + other = "" + for proc in forker.running(): + other += " " + proc.name + print("==STILL RUNNING:" + other, file=sys.stderr) + + @staticmethod + def _py_filename_adjust(py_filename: str, + tdir_def: str) -> list: # Return (py_filename, t_dir) + for tdir in Test_Dirs: # pylint: disable=redefined-outer-name + # t_dir used both absolutely and under obj_dir + try_py_filename = tdir + "/" + os.path.basename(py_filename) + if os.path.exists(try_py_filename): + # Note most tests require error messages of the form t/x.v + # Therefore py_filename must be t/ for local tests + # t_dir must be absolute - used under t or under obj_dir + tdir_abs = os.path.abspath(tdir) + return (try_py_filename, tdir_abs) + return (py_filename, os.path.abspath(tdir_def)) + + def sprint_summary(self) -> str: + delta = time.time() - Start + # Fudge of 120% works out about right so ETA correctly predicts completion time + eta = 1.2 * ((self.all_cnt * (delta / ((self.all_cnt - self.left_cnt) + 0.001))) - delta) + if delta < 10: + eta = 0 + out = "" + if self.left_cnt: + out += "Left " + str(self.left_cnt) + " " + out += "Passed " + str(self.ok_cnt) + # Ordered below most severe to least severe + out += " Failed " + str(self.fail_cnt) + if self.fail1_cnt: + out += " Failed-First " + str(self.fail1_cnt) + if self.skip_cnt: + out += " Skipped " + str(self.skip_cnt) + if forker.num_running(): + out += " Running " + str(forker.num_running()) + if self.left_cnt > 10 and eta > 10: + out += " Eta %d:%02d" % (int(eta / 60), eta % 60) + out += " Time %d:%02d" % (int(delta / 60), delta % 60) + return out + + def _manual_args(self) -> str: + # Return command line with scenarios stripped + out = [] + for oarg in Orig_ARGV_Sw: + showarg = True + for val in All_Scenarios.values(): + for allscarg in val: + if oarg == "--" + allscarg: + showarg = False + # Also strip certain flags that per-test debugging won't want + if showarg and oarg != '--rerun' and oarg != '--quiet': + out.append(oarg) + return out + + +####################################################################### +####################################################################### +# Test exceptions + + +class VtSkipException(Exception): + pass + + +class VtErrorException(Exception): + pass + + +####################################################################### +####################################################################### +# Test class + + +class VlTest: + + _file_contents_cache = {} + + # @lru_cache(maxsize=1024) broken with @staticmethod on older pythons we use + _cached_aslr_off = None + _cached_cfg_with_ccache = None + + def __init__(self, py_filename, scenario, running_id): + self.py_filename = py_filename # Name of .py file to get setup from + self.running_id = running_id + self.scenario = scenario + + self._have_solver_called = False + self._inputs = {} + self._ok = False + self._scenario_off = False # scenarios() didn't match running scenario + self._skips = None + + match = re.match(r'^(.*/)?([^/]*)\.py', self.py_filename) + self.name = match.group(2) # Name of this test + + self.benchmark = Args.benchmark + self.benchmarksim = False + self.clean_command = None + self.context_threads = 0 # Number of threads to allocate in the context + self.errors = None + self.errors_keep_going = None + self.main_time_multiplier = 1 + self.make_main = 1 # Make __main.cpp + self.make_pli = 0 # need to compile pli + self.make_top_shell = 1 # Make a default __top.v file + self.rerunnable = True # Rerun if fails + self.sc_time_resolution = "SC_PS" # Keep - PS is SystemC default + self.sim_time = 1100 # simulation time units for main wrapper + self.threads = -1 # --threads (negative means auto based on scenario) + self.verbose = Args.verbose + self.verilated_randReset = "" + self.vm_prefix = "V" + self.name + + # Make e.g. self.vlt, self.vltmt etc + self.vlt = False # Set below also + self.vltmt = False # Set below also + self.xsim = False # Set below also + for ascenario in All_Scenarios: + self.__dict__[ascenario] = False + self.__dict__[scenario] = True + self.vlt_all = self.vlt or self.vltmt # Any Verilator scenario + + (self.py_filename, self.t_dir) = Runner._py_filename_adjust(self.py_filename, ".") + for tdir in Test_Dirs: # pylint: disable=redefined-outer-name + # t_dir used both absolutely and under obj_dir + self.t_dir = None + if os.path.exists(tdir + "/" + self.name + ".py"): + # Note most tests require error messages of the form t/x.v + # Therefore py_filename must be t/ for local tests + self.py_filename = os.path.relpath(tdir + "/" + self.name + ".py") + # t_dir must be absolute - used under t or under obj_dir + self.t_dir = os.path.abspath(tdir) + break + + if not self.t_dir: + sys.exit("%Error: Can't locate dir for " + self.name) + + scen_dir = os.path.relpath(self.t_dir + "/../obj_" + self.scenario) + # Simplify filenames on local runs + scen_dir = re.sub(r'^t/\.\./', '', scen_dir) + # Not mkpath so error if try to build somewhere odd + VtOs.mkdir_ok(scen_dir) + self.obj_dir = scen_dir + "/" + self.name + + define_opt = self._define_opt_calc() + + # All compilers + self.v_flags = [] + if self.xsim: + self.v_flags += ["-f input.xsim.vc"] + elif os.path.exists('input.vc'): + self.v_flags += ["-f input.vc"] + if not re.search(r'/test_regress', self.t_dir): # Don't include standard dir, only site's + self.v_flags += ["+incdir+" + self.t_dir + " -y " + self.t_dir] + self.v_flags += [define_opt + "TEST_OBJ_DIR=" + self.obj_dir] + if Args.verbose: + self.v_flags += [define_opt + "TEST_VERBOSE=1"] + if Args.benchmark: + self.v_flags += [define_opt + "TEST_BENCHMARK=Args.benchmark"] + if Args.trace: + self.v_flags += [define_opt + "WAVES=1"] + + self.v_flags2 = [] # Overridden in some sim files + self.v_other_filenames = [] + self.all_run_flags = [] + + self.pli_flags = [ + "-I" + os.environ['VERILATOR_ROOT'] + "/include/vltstd", "-fPIC", "-shared" + ] + if platform.system() == 'Darwin': + self.pli_flags += ["-Wl,-undefined,dynamic_lookup"] + else: + self.pli_flags += ["-rdynamic"] + if Args.verbose: + self.pli_flags += ["-DTEST_VERBOSE=1"] + self.pli_flags += ["-o", self.obj_dir + "/libvpi.so"] + + self.tool_c_flags = [] + # ATSIM + self.atsim_define = 'ATSIM' + self.atsim_flags = [ + "-c", "+sv", "+define+ATSIM", ("+sv_dir+" + self.obj_dir + "/.athdl_compile") + ] + self.atsim_flags2 = [] # Overridden in some sim files + self.atsim_run_flags = [] + # GHDL + self.ghdl_define = 'GHDL' + self.ghdl_work_dir = self.obj_dir + "/ghdl_compile" + self.ghdl_flags = [("-v" if Args.debug else ""), + ("--workdir=" + self.obj_dir + "/ghdl_compile")] + self.ghdl_flags2 = [] # Overridden in some sim files + self.ghdl_run_flags = [] + # IV + self.iv_define = 'IVERILOG' + self.iv_flags = ["+define+IVERILOG", "-g2012", ("-o" + self.obj_dir + "/simiv")] + self.iv_flags2 = [] # Overridden in some sim files + self.iv_run_flags = [] + # VCS + self.vcs_define = 'VCS' + self.vcs_flags = [ + "+vcs+lic+wait", "+cli", "-debug_access", "+define+VCS+1", "-q", "-sverilog", + "-CFLAGS", "'-DVCS'" + ] + self.vcs_flags2 = [] # Overridden in some sim files + self.vcs_run_flags = ["+vcs+lic_wait"] + # NC + self.nc_define = 'NC' + self.nc_flags = [ + "+licqueue", "+nowarn+LIBNOU", "+define+NC=1", "-q", "+assert", "+sv", "-c", + ("+access+r" if Args.trace else "") + ] + self.nc_flags2 = [] # Overridden in some sim files + self.nc_run_flags = ["+licqueue", "-q", "+assert", "+sv", "-R"] + # ModelSim + self.ms_define = 'MS' + self.ms_flags = [ + "-sv", "-work", (self.obj_dir + "/work"), "+define+MS=1", "-ccflags", '\"-DMS=1\"' + ] + self.ms_flags2 = [] # Overridden in some sim files + self.ms_run_flags = ["-lib", self.obj_dir + "/work", "-c", "-do", "'run -all;quit'"] + # XSim + self.xsim_define = 'XSIM' + self.xsim_flags = [ + "--nolog", "--sv", "--define", "XSIM", "--work", + (self.name + "=" + self.obj_dir + "/xsim") + ] + self.xsim_flags2 = [] # Overridden in some sim files + self.xsim_run_flags = [ + "--nolog", "--runall", "--lib", (self.name + "=" + self.obj_dir + "/xsim"), + (" --debug all" if Args.trace else "") + ] + self.xsim_run_flags2 = [] # Overridden in some sim files + # Xcelium (xrun) + self.xrun = 0 + self.xrun_define = 'XRUN' + self.xrun_flags = [] # Doesn't really have a compile step + self.xrun_flags2 = [] # Overridden in some sim files + self.xrun_run_flags = [ + "-64", "-access", "+rwc", "-newsv", "-sv", "-xmlibdirname", self.obj_dir + "/work", + "-l", self.obj_dir + "/history", "-quiet", "-plinowarn" + ] + # Verilator + self.verilator_define = 'VERILATOR' + self.verilator_flags = [ + "-cc", + "-Mdir", + self.obj_dir, + "--fdedup", # As currently disabled unless -O3 + "--debug-check", + "--comp-limit-members", + "10" + ] + self.verilator_flags2 = [] + self.verilator_flags3 = ["--clk clk"] + self.verilator_make_gmake = True + self.verilator_make_cmake = False + self.verilated_debug = Args.verilated_debug + + self._status_filename = self.obj_dir + "/V" + self.name + ".status" + self.coverage_filename = self.obj_dir + "/coverage.dat" + self.golden_filename = re.sub(r'\.py$', '.out', self.py_filename) + self.main_filename = self.obj_dir + "/" + self.vm_prefix + "__main.cpp" + self.run_log_filename = self.obj_dir + "/vlt_sim.log" + self.stats = self.obj_dir + "/V" + self.name + "__stats.txt" + self.top_filename = re.sub(r'\.py$', '', self.py_filename) + '.' + self.v_suffix + self.pli_filename = re.sub(r'\.py$', '', self.py_filename) + '.cpp' + self.top_shell_filename = self.obj_dir + "/" + self.vm_prefix + "__top.v" + + def _define_opt_calc(self) -> str: + return "--define " if self.xsim else "+define+" + + def init_benchmarksim(self) -> None: + # Simulations with benchmarksim enabled append to the same file between runs. + # Test files must ensure a clean benchmark data file before executing tests. + filename = self.benchmarksim_filename + with open(filename, 'w', encoding="utf8") as fh: + fh.write("# Verilator simulation benchmark data\n") + fh.write("# Test name: " + self.name + "\n") + fh.write("# Top file: " + self.top_filename + "\n") + fh.write("evals, time[s]\n") + + def soprint(self, message: str) -> str: + message = message.rstrip() + "\n" + message = self.scenario + "/" + self.name + ": " + message + return message + + def oprint(self, message: str) -> None: + message = message.rstrip() + "\n" + print(self.soprint(message), end="") + + def error(self, message: str) -> None: + """Called from tests as: error("Reason message") + Newline is optional. Only first line is passed to summaries + Throws a VtErrorException, so rest of testing is not executed""" + message = message.rstrip() + "\n" + print("%Warning: " + self.scenario + "/" + self.name + ": " + message, + file=sys.stderr, + end="") + if not self.errors: + message = re.sub(r'\n.*', '\n', message) + self.errors = message + raise VtErrorException + + def error_keep_going(self, message: str) -> None: + """Called from tests as: error_keep_going("Reason message") + Newline is optional. Only first line is passed to summaries""" + message = message.rstrip() + "\n" + print("%Warning: " + self.scenario + "/" + self.name + ": " + message, + file=sys.stderr, + end="") + if not self.errors_keep_going: + message = re.sub(r'\n.*', '\n', message) + self.errors_keep_going = message + + def skip(self, message: str) -> None: + """Called from tests as: skip("Reason message"[, ...]) + Newline is optional. Only first line is passed to summaries. + Throws a VtSkipException, so rest of testing is not executed""" + message = message.rstrip() + "\n" + print("-Skip: " + self.scenario + "/" + self.name + ": " + message, + file=sys.stderr, + end="") + if not self._skips: + message = re.sub(r'\n.*', '\n', message) + self._skips = message + raise VtSkipException + + def scenarios(self, *scenario_list) -> None: + """Called from tests as: scenarios() to + specify which scenarios this test runs under. Where ... is + one cases listed in All_Scenarios. + All scenarios must be on one line; this is parsed outside Python.""" + enabled_scenarios = {} + for param in scenario_list: + hit = False + for allsc, allscs in All_Scenarios.items(): + for allscarg in allscs: + if param == allscarg: + hit = True + enabled_scenarios[allsc] = True + if not hit: + self.error("scenarios(...) has unknown scenario '" + param + "'") + + if not enabled_scenarios.get(self.scenario, None): + self._scenario_off = True + self.skip("scenario '" + self.scenario + "' not enabled for test") + # self._exit() implied by skip's exception + + @staticmethod + def _prefilter_scenario(py_filename: str, scenario: str) -> bool: + """Read a python file to see if scenarios require it to be run. + Much faster than parsing the file for a runtime check.""" + (py_filename, _) = Runner._py_filename_adjust(py_filename, ".") + with open(py_filename, 'r', encoding="utf-8") as fh: + for line in fh: + m = re.search(r'^\s*test.scenarios\((.*?)\)', line) + if m: + for param in re.findall(r"""["']([^,]*)["']""", m.group(1)): + for allscarg in All_Scenarios[scenario]: + if param == allscarg: + return True + return False + + def _prep(self) -> None: + VtOs.mkdir_ok(self.obj_dir) # Ok if already exists + + def _read(self) -> None: + if not os.path.exists(self.py_filename): + self.error("Can't open " + self.py_filename) + return + global test + test = self + sys.path.append(self.t_dir) # To find vltest_bootstrap.py + # print("_read/exec py_filename=" + self.py_filename) + # print("_read/exec dir=", ' '.join(dir())) + # print("_read/exec vars=", ' '.join(vars().keys())) + # print("_read/exec globals=", ' '.join(globals().keys())) + # print("_read/exec locals=", ' '.join(locals().keys())) + try: + runpy.run_path(self.py_filename, globals()) + except (VtErrorException, VtSkipException): + pass + + def _exit(self): + if self.ok: + self.oprint("Self PASSED") + elif self._skips and not self.errors: + self.oprint("-Skip: " + self._skips) + else: + # If no worse errors, promote errors_keep_going to normal errors + if not self.errors and self.errors_keep_going: + self.errors = self.errors_keep_going + if not self.errors: + self.error("Missing ok") + self.oprint("%Error: " + self.errors) + self._write_status() + sys.exit(0) + + def _write_status(self) -> None: + with open(self._status_filename, "wb") as fh: + pass_to_driver = { + '_ok': self._ok, + '_scenario_off': self._scenario_off, + '_skips': self._skips, + 'errors': self.errors, + } + pickle.dump(pass_to_driver, fh) + + def _read_status(self) -> None: + filename = self._status_filename + if not os.path.isfile(filename): + self.error_keep_going("Child test did not return status (test has Python error?): " + + self.py_filename) + return + with open(filename, "rb") as fh: + dic = pickle.load(fh) + for k in dic.keys(): + # print("_read_status " + filename + ".test['" + k + "]=" + pformat(dic[k])) + setattr(self, k, dic[k]) + + #---------------------------------------------------------------------- + # Methods invoked by tests + + def clean(self) -> None: + """Called on a rerun to cleanup files.""" + if self.clean_command: + os.system(self.clean_command) + # Prevents false-failures when switching compilers + # Remove old results to force hard rebuild + os.system('/bin/rm -rf ' + self.obj_dir + '__fail1') + os.system('/bin/mv ' + self.obj_dir + ' ' + self.obj_dir + '__fail1') + + def clean_objs(self) -> None: + os.system("/bin/rm -rf " + ' '.join(glob.glob(self.obj_dir + "/*"))) + + def _checkflags(self, param): + checkflags = ( + ' ' + ' '.join(param['v_flags']) + # + ' ' + ' '.join(param['v_flags2']) + # + ' ' + ' '.join(param['verilator_flags']) + # + ' ' + ' '.join(param['verilator_flags2']) + # + ' ' + ' '.join(param['verilator_flags3']) + ' ') + return checkflags + + def compile_vlt_cmd(self, **kwargs) -> list: + """Return default command list to run verilator""" + param = {'stdout_filename': None} + param.update(vars(self)) + param.update(kwargs) + vlt_cmd = [ + "perl", os.environ["VERILATOR_ROOT"] + "/bin/verilator", + *self._compile_vlt_flags(**param), param['top_filename'], *param['v_other_filenames'] + ] + if param['stdout_filename']: + vlt_cmd += ["> " + param['stdout_filename']] + return vlt_cmd + + def _compile_vlt_flags(self, **param) -> list: + checkflags = self._checkflags(param) + d_verilator_flags = ' ' + ' '.join(self.driver_verilator_flags) + ' ' + + self.pins_sc_uint_bool = ( # pylint: disable=attribute-defined-outside-init + bool( + re.search(r'-pins-sc-uint-bool\b', checkflags) + or re.search(r'-pins-sc-uint-bool\b', d_verilator_flags))) + self.savable = ( # pylint: disable=attribute-defined-outside-init + bool(re.search(r'-savable\b', checkflags))) + self.coverage = ( # pylint: disable=attribute-defined-outside-init + bool(re.search(r'-coverage\b', checkflags))) + self.sanitize = param.get('sanitize', None) # pylint: disable=attribute-defined-outside-init + self.sc = ( # pylint: disable=attribute-defined-outside-init + bool(re.search(r'-sc\b', checkflags))) + self.timing = ( # pylint: disable=attribute-defined-outside-init + bool(re.search(r'( -?-timing\b| -?-binary\b)', checkflags))) + self.trace = ( # pylint: disable=attribute-defined-outside-init + bool(Args.trace or re.search(r'-trace\b|-trace-fst\b', checkflags))) + + if re.search(r'-trace-fst', checkflags): + if self.sc: + self.trace_format = 'fst-sc' # pylint: disable=attribute-defined-outside-init + else: + self.trace_format = 'fst-c' # pylint: disable=attribute-defined-outside-init + elif self.sc: + self.trace_format = 'vcd-sc' # pylint: disable=attribute-defined-outside-init + else: + self.trace_format = 'vcd-c' # pylint: disable=attribute-defined-outside-init + + if param.get('benchmarksim', None): + self.benchmarksim = True # pylint: disable=attribute-defined-outside-init + + verilator_flags = [*param.get('verilator_flags', "")] + if Args.gdb: + verilator_flags += ["--gdb"] + if Args.gdbbt: + verilator_flags += ["--gdbbt"] + if Args.rr: + verilator_flags += ["--rr"] + if Args.trace: + verilator_flags += ["--trace"] + if Args.gdbsim or Args.rrsim: + verilator_flags += ["-CFLAGS -ggdb -LDFLAGS -ggdb"] + verilator_flags += ["--x-assign unique"] # More likely to be buggy + + if param['vltmt']: + verilator_flags += ["--debug-partition"] + if param['threads'] >= 0: + verilator_flags += ["--threads", str(param['threads'])] + if param['vltmt'] and re.search(r'-trace-fst ', checkflags): + verilator_flags += ["--trace-threads 2"] + if self.sanitize: + verilator_flags += [ + "-CFLAGS -fsanitize=address,undefined -LDFLAGS -fsanitize=address,undefined" + ] + if param['verilator_make_cmake']: + verilator_flags += ["--make cmake"] + if param['verilator_make_gmake']: + verilator_flags += ["--make gmake"] + if param['make_main'] and param['verilator_make_gmake']: + verilator_flags += ["--exe"] + if param['make_main'] and param['verilator_make_gmake']: + verilator_flags += ["../" + self.main_filename] + + cmdargs = [ + "--prefix", + param['vm_prefix'], + *verilator_flags, + *param['verilator_flags2'], + *param['verilator_flags3'], + *param['v_flags'], + *param['v_flags2'], + # Flags from driver cmdline override default flags and + # flags from the test itself + *self.driver_verilator_flags, + ] + return cmdargs + + def lint(self, **kwargs) -> None: + """Run a linter. Arguments similar to run(); default arguments are from self""" + param = {} + param.update(vars(self)) + param.update({ # Lint-specific default overrides + 'make_main': False, + 'make_top_shell': False, + 'verilator_flags2': ["--lint-only"], + 'verilator_make_gmake': False + }) + param.update(kwargs) + self.compile(**param) + + def compile(self, **kwargs) -> None: + """Run simulation compiler. Arguments similar to run(); default arguments are from self""" + param = { + 'expect': None, + 'expect_filename': None, + 'fails': False, + 'make_flags': [], + 'tee': True, + 'timing_loop': False, + } + param.update(vars(self)) + param.update(kwargs) + + if self.verbose: + self.oprint("Compile") + + if param['vlt'] and param['threads'] > 1: + self.error("'threads =' argument must be <= 1 for vlt scenario") + # Compute automatic parameter values + checkflags = self._checkflags(param) + if re.search(r'(^|\s)-?-threads\s', checkflags): + self.error("Specify threads via 'threads=' argument, not as a command line option") + + if param['threads'] < 0 and param['vltmt']: + param['threads'] = calc_threads(Vltmt_Threads) + if not param['context_threads']: + param['context_threads'] = param['threads'] if (param['threads'] >= 1) else 1 + if re.search(r'( -?-main\b| -?-binary\b)', checkflags): + param['make_main'] = False + if re.search(r'( -?-build\b| -?-binary\b)', checkflags): + param['verilator_make_cmake'] = False + param['verilator_make_gmake'] = False + self.threads = param['threads'] + self.context_threads = param['context_threads'] + + self.compile_vlt_cmd(**param) + + if not re.search(r'TEST_DUMPFILE', ' '.join(self.v_flags)): + self.v_flags += [self._define_opt_calc() + "TEST_DUMPFILE=" + self.trace_filename] + + if not param['make_top_shell']: + self.top_shell_filename = "" + else: + self.top_shell_filename = self.obj_dir + "/" + self.vm_prefix + "__top." + self.v_suffix + param['top_shell_filename'] = self.top_shell_filename + + if param['atsim']: + tool_define = param['atsim_define'] + self._make_top(param['make_top_shell']) + self.run(logfile=self.obj_dir + "/atsim_compile.log", + fails=param['fails'], + cmd=[ + VtOs.getenv_def('VERILATOR_ATSIM', "atsim"), + ' '.join(param['atsim_flags']), + ' '.join(param['atsim_flags2']), + ' '.join(param['v_flags']), + ' '.join(param['v_flags2']), + param['top_filename'], + param['top_shell_filename'], + ' '.join(param['v_other_filenames']), + ]) + elif param['ghdl']: + tool_define = param['ghdl_define'] + VtOs.mkdir_ok(self.ghdl_work_dir) + self._make_top(param['make_top_shell']) + tool_exe = VtOs.getenv_def('VERILATOR_GHDL', "ghdl") + self.run( + logfile=self.obj_dir + "/ghdl_compile.log", + fails=param['fails'], + cmd=[ + tool_exe, + # Add -c here, as having -c twice freaks it out + ("" if re.search(r' -c\b', tool_exe) else "-c"), + ' '.join(param['ghdl_flags']), + ' '.join(param['ghdl_flags2']), + #' '.join(param['v_flags']), # Not supported + #' '.join(param['v_flags2']), # Not supported + param['top_filename'], + param['top_shell_filename'], + ' '.join(param['v_other_filenames']), + "-e t", + ]) + elif param['vcs']: + tool_define = param['vcs_define'] + self._make_top(param['make_top_shell']) + self.run(logfile=self.obj_dir + "/vcs_compile.log", + fails=param['fails'], + cmd=[ + VtOs.getenv_def('VERILATOR_VCS', "vcs"), + ' '.join(param['vcs_flags']), + ' '.join(param['vcs_flags2']), + ("-CFLAGS -DTEST_VERBOSE=1" if Args.verbose else ""), + ' '.join(param['v_flags']), + ' '.join(param['v_flags2']), + param['top_filename'], + param['top_shell_filename'], + ' '.join(param['v_other_filenames']), + ]) + elif param['nc']: + tool_define = param['nc_define'] + self._make_top(param['make_top_shell']) + self.run(logfile=self.obj_dir + "/nc_compile.log", + fails=param['fails'], + cmd=[ + VtOs.getenv_def('VERILATOR_NCVERILOG', "ncverilog"), + ' '.join(param['nc_flags']), + ' '.join(param['nc_flags2']), + ' '.join(param['v_flags']), + ' '.join(param['v_flags2']), + param['top_filename'], + param['top_shell_filename'], + ' '.join(param['v_other_filenames']), + ]) + elif param['ms']: + tool_define = param['ms_define'] + self._make_top(param['make_top_shell']) + self.run(logfile=self.obj_dir + "/ms_compile.log", + fails=param['fails'], + cmd=[ + ("vlib " + self.obj_dir + "/work && "), + VtOs.getenv_def('VERILATOR_MODELSIM', "vlog"), + ' '.join(param['ms_flags']), + ' '.join(param['ms_flags2']), + ' '.join(param['v_flags']), + ' '.join(param['v_flags2']), + param['top_filename'], + param['top_shell_filename'], + ]) + elif param['iv']: + tool_define = param['iv_define'] + self._make_top(param['make_top_shell']) + cmd = (VtOs.getenv_def('VERILATOR_IVERILOG', "iverilog"), ' '.join(param['iv_flags']), + ' '.join(param['iv_flags2']), ' '.join(param['v_flags']), + ' '.join(param['v_flags2']), param['top_filename'], param['top_shell_filename'], + ' '.join(param['v_other_filenames'])) + cmd = list(map(lambda str: re.sub(r'\+define\+', '-D ', str), cmd)) + self.run(logfile=self.obj_dir + "/iv_compile.log", fails=param['fails'], cmd=cmd) + elif param['xrun']: + tool_define = param['xrun_define'] + self._make_top(param['make_top_shell']) + elif param['xsim']: + tool_define = param['xsim_define'] + self._make_top(param['make_top_shell']) + self.run(logfile=self.obj_dir + "/xsim_compile.log", + fails=param['fails'], + cmd=[ + VtOs.getenv_def('VERILATOR_XVLOG', "xvlog"), + ' '.join(param['xsim_flags']), + ' '.join(param['xsim_flags2']), + ' '.join(param['v_flags']), + ' '.join(param['v_flags2']), + param['top_filename'], + param['top_shell_filename'], + ]) + elif param['vlt_all']: + tool_define = param['verilator_define'] + + if self.sc and not self.have_sc: + self.skip("Test requires SystemC; ignore error since not installed\n") + return + + if self.timing and not self.have_coroutines: + self.skip("Test requires Coroutines; ignore error since not available\n") + return + + if param['verilator_make_cmake'] and not self.have_cmake: + self.skip( + "Test requires CMake; ignore error since not available or version too old\n") + return + + if not param['fails'] and param['make_main']: + self._make_main(param['timing_loop']) + + if (param['verilator_make_gmake'] + or (not param['verilator_make_gmake'] and not param['verilator_make_cmake'])): + vlt_cmd = self.compile_vlt_cmd(**param) + if self.verbose: + self.oprint("Running Verilator (gmake)") + if Args.verilation: + self.run(logfile=self.obj_dir + "/vlt_compile.log", + fails=param['fails'], + tee=param['tee'], + expect=param['expect'], + expect_filename=param['expect_filename'], + verilator_run=True, + cmd=vlt_cmd) + + if param['verilator_make_cmake']: + vlt_args = self._compile_vlt_flags(**param) + if self.verbose: + self.oprint("Running cmake") + VtOs.mkdir_ok(self.obj_dir) + csources = [] + if param['make_main']: + csources.append(self.main_filename) + self.run( + logfile=self.obj_dir + "/vlt_cmake.log", + fails=param['fails'], + tee=param['tee'], + expect=param['expect'], + expect_filename=param['expect_filename'], + verilator_run=True, + cmd=[ + "cd \"" + self.obj_dir + "\" && cmake", + "\"" + self.t_dir + "/..\"", + "-DTEST_VERILATOR_ROOT=" + os.environ['VERILATOR_ROOT'], + "-DTEST_NAME=" + self.name, + "-DTEST_CSOURCES=\"" + ' '.join(csources) + "\"", + "-DTEST_VERILATOR_ARGS=\"" + ' '.join(vlt_args) + "\"", + "-DTEST_VERILATOR_SOURCES=\"" + param['top_filename'] + ' ' + + ' '.join(param['v_other_filenames']) + "\"", + "-DTEST_VERBOSE=\"" + ("1" if self.verbose else "0") + "\"", + "-DTEST_SYSTEMC=\"" + ("1" if self.sc else "0") + "\"", + "-DCMAKE_PREFIX_PATH=\"" + + (VtOs.getenv_def('SYSTEMC_INCLUDE', VtOs.getenv_def('SYSTEMC', '')) + + "/..\""), + "-DTEST_OPT_FAST=\"" + ("-Os" if param['benchmark'] else "-O0") + "\"", + "-DTEST_OPT_GLOBAL=\"" + ("-Os" if param['benchmark'] else "-O0") + "\"", + "-DTEST_VERILATION=\"" + ("1" if Args.verilation else "0") + "\"", + ]) + + if not param['fails'] and param['verilator_make_gmake']: + if self.verbose: + self.oprint("Running make (gmake)") + self.run( + logfile=self.obj_dir + "/vlt_gcc.log", + entering=self.obj_dir, + cmd=[ + os.environ['MAKE'], + "-C " + self.obj_dir, + "-f " + os.path.abspath(os.path.dirname(__file__)) + "/Makefile_obj", + ("" if self.verbose else "--no-print-directory"), + "VM_PREFIX=" + self.vm_prefix, + "TEST_OBJ_DIR=" + self.obj_dir, + "CPPFLAGS_DRIVER=-D" + self.name.upper(), + ("CPPFLAGS_DRIVER2=-DTEST_VERBOSE=1" if self.verbose else ""), + ("" if param['benchmark'] else "OPT_FAST=-O0"), + ("" if param['benchmark'] else "OPT_GLOBAL=-O0"), + self.vm_prefix, # bypass default rule, as we don't need archive + *param['make_flags'], + ]) + + if not param['fails'] and param['verilator_make_cmake']: + if self.verbose: + self.oprint("Running cmake --build") + self.run(logfile=self.obj_dir + "/vlt_cmake_build.log", + cmd=[ + "cmake", + "--build", + self.obj_dir, + ("--verbose" if self.verbose else ""), + ]) + else: + self.error("No compile step defined for '%s' scenario" % self.scenario()) + + if param['make_pli']: + if self.verbose: + self.oprint("Compile vpi") + cmd = [ + os.environ['CXX'], *param['pli_flags'], "-D" + tool_define, "-DIS_VPI", + VtOs.getenv_def('CFLAGS', ''), self.pli_filename + ] + self.run(logfile=self.obj_dir + "/pli_compile.log", fails=param['fails'], cmd=cmd) + + def execute(self, **kwargs) -> None: + """Run simulation executable. + Arguments similar to run(); default arguments are from self""" + # Default arguments are from self + # params may be expect or {tool}_expect + param = { + 'aslr_off': False, + 'entering': False, + 'check_finished': False, + 'executable': None, + 'expect': None, + 'expect_filename': None, + 'fails': False, + 'run_env': '', + 'tee': False, + } + param.update(vars(self)) + param.update(kwargs) + + if self.verbose: + self.oprint("Run") + + if not self.verbose: + os.environ['SYSTEMC_DISABLE_COPYRIGHT_MESSAGE'] = 'DISABLE' + else: + VtOs.delenv('SYSTEMC_DISABLE_COPYRIGHT_MESSAGE') + + if not self._have_solver_called: + os.environ['VERILATOR_SOLVER'] = "test.py-file-needs-have_solver()-call" + + if param['check_finished'] is None and not param['fails']: + param['check_finished'] = 1 + + run_env = param['run_env'] + if run_env: + run_env = run_env + ' ' + + if param['atsim']: + self.run( + logfile=self.obj_dir + "/atsim_sim.log", + fails=param['fails'], + cmd=[ + "echo q | " + run_env + self.obj_dir + "/athdl_sv", + ' '.join(param['atsim_run_flags']), + ' '.join(param['all_run_flags']), + ], + *param, + expect=param['atsim_run_expect'], # non-verilator expect isn't the same + expect_filename=param['atsim_run_expect_filename'], + ) + elif param['ghdl']: + self.run( + logfile=self.obj_dir + "/ghdl_sim.log", + fails=param['fails'], + cmd=[ + run_env + self.obj_dir + "/simghdl", + ' '.join(param['ghdl_run_flags']), + ' '.join(param['all_run_flags']), + ], + *param, + expect=param['ghdl_run_expect'], # non-verilator expect isn't the same + expect_filename=param['ghdl_run_expect_filename'], + ) + elif param['iv']: + cmd = [ + run_env + self.obj_dir + "/simiv", + ' '.join(param['iv_run_flags']), + ' '.join(param['all_run_flags']), + ] + if param['use_libvpi']: + # Don't enter command line on $stop, include vpi + cmd += ["vvp -n -m " + self.obj_dir + "/libvpi.so"] + self.run( + logfile=self.obj_dir + "/iv_sim.log", + fails=param['fails'], + cmd=cmd, + *param, + expect=param['iv_run_expect'], # non-verilator expect isn't the same + expect_filename=param['iv_run_expect_filename'], + ) + elif param['ms']: + pli_opt = "" + if param['use_libvpi']: + pli_opt = "-pli " + self.obj_dir + "/libvpi.so" + self.run( + logfile=self.obj_dir + "/ms_sim.log", + fails=param['fails'], + cmd=[ + "echo q | " + run_env + VtOs.getenv_def('VERILATOR_MODELSIM', "vsim"), + ' '.join(param['ms_run_flags']), ' '.join(param['all_run_flags']), pli_opt, + (" top") + ], + *param, + expect=param['ms_run_expect'], # non-verilator expect isn't the same + expect_filename=param['ms_expect_filename'], + ) + elif param['nc']: + self.run( + logfile=self.obj_dir + "/nc_sim.log", + fails=param['fails'], + cmd=[ + "echo q | " + run_env + VtOs.getenv_def('VERILATOR_NCVERILOG', "ncverilog"), + ' '.join(param['nc_run_flags']), + ' '.join(param['all_run_flags']), + ], + *param, + expect=param['nc_run_expect'], # non-verilator expect isn't the same + expect_filename=param['nc_run_expect_filename'], + ) + elif param['vcs']: + # my $fh = IO::File->new(">simv.key") or die "%Error: $! simv.key," + # fh.print("quit\n"); fh.close() + self.run( + logfile=self.obj_dir + "/vcs_sim.log", + cmd=[ + "echo q | " + run_env + "./simv", + ' '.join(param['vcs_run_flags']), + ' '.join(param['all_run_flags']), + ], + *param, + expect=param['vcs_run_expect'], # non-verilator expect isn't the same + expect_filename=param['vcs_run_expect_filename'], + ) + elif param['xrun']: + pli_opt = "" + if param['use_libvpi']: + pli_opt = "-loadvpi " + self.obj_dir + "/libvpi.so:vpi_compat_bootstrap" + self.run( + logfile=self.obj_dir + "/xrun_sim.log", + fails=param['fails'], + cmd=[ + "echo q | " + run_env + VtOs.getenv_def('VERILATOR_XRUN', "xrun"), + ' '.join(param['xrun_run_flags']), + ' '.join(param['xrun_flags2']), + ' '.join(param['all_run_flags']), + pli_opt, + param['top_filename'], + ], + *param, + expect=param['xrun_run_expect'], # non-verilator expect isn't the same + expect_filename=param['xrun_run_expect_filename'], + ) + elif param['xsim']: + self.run( + logfile=self.obj_dir + "/xsim_sim.log", + fails=param['fails'], + cmd=[ + run_env + VtOs.getenv_def('VERILATOR_XELAB', "xelab"), + ' '.join(param['xsim_run_flags']), ' '.join(param['xsim_run_flags2']), + ' '.join(param['all_run_flags']), (" " + self.name + ".top") + ], + *param, + expect=param['xsim_run_expect'], # non-verilator expect isn't the same + expect_filename=param['xsim_expect_filename'], + ) + elif param['vlt_all']: + if not param['executable']: + param['executable'] = self.obj_dir + "/" + param['vm_prefix'] + debugger = "" + if Args.gdbsim: + debugger = VtOs.getenv_def('VERILATOR_GDB', "gdb") + " " + elif Args.rrsim: + debugger = "rr record " + self.run( + cmd=[ + (run_env + debugger + param['executable'] + + (" -ex 'run " if Args.gdbsim else "")), + *param['all_run_flags'], + ("'" if Args.gdbsim else ""), + ], + aslr_off=param['aslr_off'], # Disable address space layour randomization + check_finished=param['check_finished'], # Check for All Finished + entering=param['entering'], # Print entering directory information + expect=param['expect'], + expect_filename=param['expect_filename'], + fails=param['fails'], + logfile=param.get('logfile', self.obj_dir + "/vlt_sim.log"), + tee=param['tee'], + verilator_run=True, + ) + else: + self.error("No execute step for this simulator") + + #--------------------------------------------------------------- + # Accessors + + @property + def aslr_off(self) -> str: + if VlTest._cached_aslr_off is None: + out = VtOs.run_capture('setarch --addr-no-randomize echo OK 2>/dev/null`', check=False) + if re.search(r'OK', out): + VlTest._cached_aslr_off = "setarch --addr-no-randomize " + else: + VlTest._cached_aslr_off = "" + return VlTest._cached_aslr_off + + @property + def benchmarksim_filename(self) -> str: + return self.obj_dir + "/" + self.name + "_benchmarksim.csv" + + @property + def driver_verilator_flags(self) -> list: + return Arg_Driver_Verilator_Flags + + @property + def get_default_vltmt_threads(self) -> int: + return Vltmt_Threads + + @property + def ok(self) -> bool: + if self.errors or self.errors_keep_going or self._skips: + self._ok = False + return self._ok + + def passes(self, is_ok=True): + if not self.errors: + self._ok = is_ok + + @property + def too_few_cores(self) -> bool: + return calc_threads(Vltmt_Threads) < Vltmt_Threads + + @property + def trace_filename(self) -> str: + if re.match(r'^fst', self.trace_format): + return self.obj_dir + "/simx.fst" + return self.obj_dir + "/simx.vcd" + + def skip_if_too_few_cores(self) -> None: + if self.too_few_cores: + self.skip("Skipping due to too few cores") + + @property + def v_suffix(self) -> str: + return "v" + + @property + def wno_unopthreads_for_few_cores(self) -> str: + if self.too_few_cores: + print("Too few cores, using -Wno-UNOPTTHREADS") + return "-Wno-UNOPTTHREADS" + return "" + + #--------------------------------------------------------------- + # Capabilities + + @property + def cmake_version(self) -> str: + return Capabilities.cmake_version + + @property + def cxx_version(self) -> str: + return Capabilities.cxx_version + + @property + def have_cmake(self) -> bool: + ver = Capabilities.cmake_version + return ver and version.parse(ver) >= version.parse("3.8") + + @property + def have_coroutines(self) -> bool: + return Capabilities.have_coroutines + + @property + def have_gdb(self) -> bool: + return Capabilities.have_gdb + + @property + def have_sc(self) -> bool: + return Capabilities.have_sc + + @property + def have_solver(self) -> bool: + self._have_solver_called = True + return Capabilities.have_solver + + @property + def make_version(self) -> str: + return Capabilities.make_version + + #--------------------------------------------------------------- + # OS functions + + def getenv_def(self, var: str, default=None) -> str: + """Return environment variable, returning default if does not exist""" + return VtOs.getenv_def(var, default) + + def mkdir_ok(self, filename) -> None: + """Make directory, no error if exists""" + if test.verbose: + print("\tmkdir " + filename) + VtOs.mkdir_ok(filename) + + def run_capture(self, cmd: str, check=True) -> str: + """Run a command and return results""" + if test.verbose: + print("\t" + cmd) + return VtOs.run_capture(cmd, check=check) + + def setenv(self, var: str, val: str) -> None: + """Set enviornment variable""" + print("\texport %s='%s'" % (var, val)) + os.environ[var] = val + + def unlink_ok(self, filename) -> None: + """Unlink a file, no error if fails""" + if test.verbose: + print("\trm " + filename) + VtOs.unlink_ok(filename) + + #---------------------------------------------------------------------- + + def run( + self, # + cmd: list, + aslr_off=False, # Disable address space layour randomization + check_finished=False, # Check for All Finished + entering=None, # Print entering directory information + expect=None, # Regexp to expect in output + expect_filename=None, # Filename that should match logfile + fails=False, # Command should fail + logfile=None, # Filename to write putput to + tee=True, + verilator_run=False) -> str: # Move gcov data to parallel area + + try: + command = ' '.join(cmd) + except TypeError: + print('run(cmd=' + pformat(cmd)) + command = ' '.join(cmd) + + if aslr_off and aslr_off != "": + prefix = self.aslr_off + if prefix: + command = prefix + " " + command + + if Args.benchmark and re.match(r'^cd ', command): + command = "time " + command + + if verilator_run: + # Gcov fails when parallel jobs write same data file, + # so we make sure .gcda output dir is unique across all running jobs. + # We can't just put each one in an unique obj_dir as it uses too much disk. + # Must use absolute path as some execute()s have different PWD + self.setenv('GCOV_PREFIX_STRIP', '99') + self.setenv('GCOV_PREFIX', + os.path.abspath(__file__ + "/../obj_dist/gcov_" + str(self.running_id))) + VtOs.mkdir_ok(os.environ['GCOV_PREFIX']) + else: + VtOs.delenv('GCOV_PREFIX_STRIP') + VtOs.delenv('GCOV_PREFIX') + + print("\t" + command + ((" > " + logfile) if logfile else "")) + + if entering: + print("driver: Entering directory '" + os.path.abspath(entering) + "'") + + # Execute command redirecting output, keeping order between stderr and stdout. + # Must do low-level IO so GCC interaction works (can't be line-based) + status = None + if True: # process_caller_block # pylint: disable=using-constant-test + + logfh = None + if logfile: + logfh = open(logfile, 'wb') # pylint: disable=consider-using-with + + with subprocess.Popen(command, + shell=True, + bufsize=0, + stdout=subprocess.PIPE, + stderr=subprocess.STDOUT) as proc: + + rawbuf = bytearray(2048) + + while proc.poll() is None: + got = proc.stdout.readinto(rawbuf) + if got: + data = rawbuf[0:got] + if tee: + sys.stdout.write(data.decode()) + if interactive_debugger: + sys.stdout.flush() + if logfh: + logfh.write(data) + + if logfh: + logfh.close() + + rc = proc.returncode # Negative if killed by signal + if (rc in ( + -4, # SIGILL + -8, # SIGFPA + -11)): # SIGSEGV + self.error("Exec failed with core dump") + status = 10 + elif rc: + status = 10 + else: + status = 0 + + sys.stdout.flush() + sys.stderr.flush() + + if entering: + print("driver: Leaving directory '" + os.path.abspath(entering) + "'") + + if not fails and status: + firstline = "" + if logfile: + with open(logfile, 'r', encoding="utf8") as fh: + firstline = fh.read() + firstline = firstline.strip() + firstline = re.sub(r'(^|\n)- [^\n]+', '\1', firstline) # Debug message + self.error("Exec of " + cmd[0] + " failed: " + firstline) + if fails and status: + print("(Exec expected to fail, and did.)") + if fails and not status: + self.error("Exec of " + cmd[0] + " ok, but expected to fail") + if self.errors or self._skips: + return False + + # Read the log file a couple of times to allow for NFS delays + if check_finished or expect: + for tryn in range(self.tries() - 1, -1, -1): + if tryn != self.tries() - 1: + time.sleep(1) + moretry = tryn != 0 + if self._run_log_try(cmd, logfile, check_finished, moretry, expect): + break + if expect_filename: + self.files_identical(logfile, expect_filename, is_logfile=True) + return False + + return True + + def _run_log_try(self, cmd: str, logfile: str, check_finished: bool, moretry: bool, + expect) -> None: + with open(logfile, 'r', encoding='latin-1', newline='\n') as fh: + if not fh and moretry: + return True + wholefile = str(fh.read()) + + # Finished? + if check_finished and not re.search(r'\*\-\* All Finished \*\-\*', wholefile): + if moretry: + return True + self.error("Missing '*-* All Finished *-*'") + if expect: + # Strip debugging comments + # See also files_identical + wholefile = re.sub(r'^- [^\n]+\n', '', wholefile) + wholefile = re.sub(r'^- [a-z.0-9]+:\d+:[^\n]+\n', '', wholefile) + wholefile = re.sub(r'^dot [^\n]+\n', '', wholefile) + wholefile = re.sub(r'^==[0-9]+== [^\n]+\n', '', wholefile) # Valgrind + # Compare + quoted = (re.escape(expect) or self._try_regex(wholefile, expect) == 1 + or re.search(expect, wholefile)) + ok = (wholefile == expect or self._try_regex(wholefile, expect) == 1 + or re.search(quoted, wholefile)) + if not ok: + #print("**BAD " + self.name + " " + logfile + " MT " + moretry + " " + try) + if moretry: + return True + self.error("Miscompares in output from " + cmd[0]) + if ok < 1: + self.error("Might be error in regexp format") + print("GOT:") + print(wholefile) + print("ENDGOT") + print("EXPECT:") + print(expect) + print("ENDEXPECT") + + return False + + ####################################################################### + # Little utilities + + @staticmethod + def _try_regex(text: str, regex) -> None: + # Try to eval a regexp + # Returns: + # 1 if $text ~= /$regex/ms + # 0 if no match + # -1 if $regex is invalid, doesn't compile + try: + m = re.search(regex, text) + return 1 if m else 0 + except re.error: + return -1 + + def _make_main(self, timing_loop: bool) -> None: + if timing_loop and self.sc: + self.error("Cannot use timing loop and SystemC together!") + + self._read_inputs_v() + + filename = self.main_filename + with open(filename, "w", encoding="utf8") as fh: + + fh.write("// Test defines\n") + fh.write("#define MAIN_TIME_MULTIPLIER " + + str(int(round(self.main_time_multiplier, 0))) + "\n") + + fh.write("#include \n") + if self.benchmarksim: + fh.write("#include \n") + fh.write("#include \n") + fh.write("#include \n") + + fh.write("// OS header\n") + fh.write('#include "verilatedos.h"' + "\n") + + fh.write("// Generated header\n") + fh.write('#include "' + self.vm_prefix + '.h"' + "\n") + + fh.write("// General headers\n") + fh.write('#include "verilated.h"' + "\n") + if self.sc: + fh.write('#include "systemc.h"' + "\n") + if self.trace and self.trace_format == 'fst-c': + fh.write("#include \"verilated_fst_c.h\"\n") + if self.trace and self.trace_format == 'fst-sc': + fh.write("#include \"verilated_fst_sc.h\"\n") + if self.trace and self.trace_format == 'vcd-c': + fh.write("#include \"verilated_vcd_c.h\"\n") + if self.trace and self.trace_format == 'vcd-sc': + fh.write("#include \"verilated_vcd_sc.h\"\n") + if self.savable: + fh.write("#include \"verilated_save.h\"\n") + + fh.write("std::unique_ptr<" + self.vm_prefix + "> topp;\n") + + if self.savable: + fh.write("\n") + fh.write("void save_model(const char* filenamep) {\n") + fh.write(" VL_PRINTF(\"Saving model to '%s'\\n\", filenamep);\n") + fh.write(" VerilatedSave os;\n") + fh.write(" os.open(filenamep);\n") + fh.write(" os << *topp;\n") + fh.write(" os.close();\n") + fh.write("}\n") + fh.write("\n") + fh.write("void restore_model(const char* filenamep) {\n") + fh.write(" VL_PRINTF(\"Restoring model from '%s'\\n\", filenamep);\n") + fh.write(" VerilatedRestore os;\n") + fh.write(" os.open(filenamep);\n") + fh.write(" os >> *topp;\n") + fh.write(" os.close();\n") + fh.write("}\n") + + #### Main + if self.sc: + fh.write("extern int sc_main(int argc, char** argv);\n") + fh.write("int sc_main(int argc, char** argv) {\n") + if 'fastclk' in self._inputs: + if self.pins_sc_uint_bool: + fh.write(" sc_signal> fastclk;\n") + else: + fh.write(" sc_signal fastclk;\n") + if 'clk' in self._inputs: + if self.pins_sc_uint_bool: + fh.write(" sc_signal> clk;\n") + else: + fh.write(" sc_signal clk;\n") + fh.write(" sc_set_time_resolution(1, " + self.sc_time_resolution + ");\n") + fh.write(" sc_time sim_time(" + str(self.sim_time) + ", " + + self.sc_time_resolution + ");\n") + else: + fh.write("int main(int argc, char** argv) {\n") + fh.write(" uint64_t sim_time = " + str(self.sim_time) + ";\n") + + fh.write( + " const std::unique_ptr contextp{new VerilatedContext};\n") + fh.write(" contextp->threads(" + str(self.context_threads) + ");\n") + fh.write(" contextp->commandArgs(argc, argv);\n") + fh.write(" contextp->debug(" + ('1' if self.verilated_debug else '0') + ");\n") + fh.write(" srand48(5);\n") # Ensure determinism + if self.verilated_randReset is not None and self.verilated_randReset != "": + fh.write(" contextp->randReset(" + str(self.verilated_randReset) + ");\n") + fh.write(" topp.reset(new " + self.vm_prefix + "{\"top\"});\n") + if self.verilated_debug: + fh.write(" contextp->internalsDump()\n;") + + if self.sc: + if 'fastclk' in self._inputs: + fh.write(" topp->fastclk(fastclk);\n") + if 'clk' in self._inputs: + fh.write(" topp->clk(clk);\n") + setp = "" + else: + fh.write(" topp->eval();\n") + setp = "topp->" + + if self.benchmarksim: + fh.write(" std::chrono::time_point starttime;\n") + fh.write(" bool warm = false;\n") + fh.write(" uint64_t n_evals = 0;\n") + + if self.trace: + fh.write("\n") + fh.write("#if VM_TRACE\n") + fh.write(" contextp->traceEverOn(true);\n") + if self.trace_format == 'fst-c': + fh.write(" std::unique_ptr tfp{new VerilatedFstC};\n") + if self.trace_format == 'fst-sc': + fh.write(" std::unique_ptr tfp{new VerilatedFstSc};\n") + if self.trace_format == 'vcd-c': + fh.write(" std::unique_ptr tfp{new VerilatedVcdC};\n") + if self.trace_format == 'vcd-sc': + fh.write(" std::unique_ptr tfp{new VerilatedVcdSc};\n") + if self.sc: + fh.write(" sc_core::sc_start(sc_core::SC_ZERO_TIME);" + + " // Finish elaboration before trace and open\n") + fh.write(" topp->trace(tfp.get(), 99);\n") + fh.write(" tfp->open(\"" + self.trace_filename + "\");\n") + + if self.trace and not self.sc: + fh.write(" if (tfp) tfp->dump(contextp->time());\n") + fh.write("#endif\n") + + if self.savable: + fh.write(" const char* save_time_strp" + " = contextp->commandArgsPlusMatch(\"save_time=\");\n") + fh.write(" unsigned int save_time = !save_time_strp[0]" + " ? 0 : std::atoi(save_time_strp + std::strlen(\"+save_time=\"));\n") + fh.write(" const char* save_restore_strp" + " = contextp->commandArgsPlusMatch(\"save_restore=\");\n") + fh.write(" unsigned int save_restore = !save_restore_strp[0] ? 0 : 1;\n") + + if self.savable: + fh.write(" if (save_restore) {\n") + fh.write(" restore_model(\"" + self.obj_dir + "/saved.vltsv\");\n") + fh.write(" } else {\n") + else: + fh.write(" {\n") + + if 'fastclk' in self._inputs: + fh.write(" " + setp + "fastclk = false;\n") + if 'clk' in self._inputs: + fh.write(" " + setp + "clk = false;\n") + if not timing_loop: + self._print_advance_time(fh, 10, None) + fh.write(" }\n") + + timestamp = "sc_time_stamp()" if self.sc else "contextp->time()" + + fh.write(" while (") + if not timing_loop or 'clk' in self._inputs: + fh.write("(" + timestamp + " < sim_time * MAIN_TIME_MULTIPLIER) && ") + fh.write("!contextp->gotFinish()) {\n") + + if timing_loop: + fh.write(" topp->eval();\n") + if self.trace: + fh.write("#if VM_TRACE\n") + fh.write(" if (tfp) tfp->dump(contextp->time());\n") + fh.write("#endif // VM_TRACE\n") + if 'clk' in self._inputs: + fh.write(" const uint64_t cycles" + " = contextp->time() / MAIN_TIME_MULTIPLIER;\n") + fh.write(" uint64_t new_time = (cycles + 1) * MAIN_TIME_MULTIPLIER;\n") + fh.write(" if (topp->eventsPending() &&\n") + fh.write(" topp->nextTimeSlot()" + " / MAIN_TIME_MULTIPLIER <= cycles) {\n") + fh.write(" new_time = topp->nextTimeSlot();\n") + fh.write(" } else {\n") + if self.pins_sc_uint_bool: + fh.write(" " + setp + "clk.write(!" + setp + "clk.read());\n") + else: + fh.write(" " + setp + "clk = !" + setp + "clk;\n") + fh.write(" }\n") + fh.write(" contextp->time(new_time);\n") + else: + fh.write(" if (!topp->eventsPending()) break;\n") + fh.write(" contextp->time(topp->nextTimeSlot());\n") + else: + for i in range(5): + action = False + if 'fastclk' in self._inputs: + if self.pins_sc_uint_bool: + fh.write(" " + setp + "fastclk.write(!" + setp + + "fastclk.read());\n") + else: + fh.write(" " + setp + "fastclk = !" + setp + "fastclk;\n") + action = True + if i == 0 and 'clk' in self._inputs: + if self.pins_sc_uint_bool: + fh.write(" " + setp + "clk.write(!" + setp + "clk.read());\n") + else: + fh.write(" " + setp + "clk = !" + setp + "clk;\n") + action = True + if self.savable: + fh.write(" if (save_time && " + timestamp + " == save_time) {\n") + fh.write(" save_model(\"" + self.obj_dir + "/saved.vltsv\");\n") + fh.write(" printf(\"Exiting after save_model\\n\");\n") + fh.write(" topp.reset(nullptr);\n") + fh.write(" return 0;\n") + fh.write(" }\n") + self._print_advance_time(fh, 1, action) + if self.benchmarksim: + fh.write(" if (VL_UNLIKELY(!warm)) {\n") + fh.write(" starttime = std::chrono::steady_clock::now();\n") + fh.write(" warm = true;\n") + fh.write(" } else {\n") + fh.write(" ++n_evals;\n") + fh.write(" }\n") + + fh.write(" }\n") + + if self.benchmarksim: + fh.write(" {\n") + fh.write(" const std::chrono::duration exec_s" + " = std::chrono::steady_clock::now() - starttime;\n") + fh.write(" std::ofstream benchfile(\"" + self.benchmarksim_filename + + "\", std::ofstream::out | std::ofstream::app);\n") + fh.write(" benchfile << std::fixed << std::setprecision(9)" + " << n_evals << \",\" << exec_s.count() << std::endl;\n") + fh.write(" benchfile.close();\n") + fh.write(" }\n") + + fh.write(" if (!contextp->gotFinish()) {\n") + fh.write(' vl_fatal(__FILE__, __LINE__, "main",' + + ' "%Error: Timeout; never got a $finish");' + "\n") + fh.write(" }\n") + fh.write(" topp->final();\n") + fh.write("\n") + + if self.coverage: + fh.write("#if VM_COVERAGE\n") + fh.write(" contextp->coveragep()->write(\"" + self.coverage_filename + "\");\n") + fh.write("#endif // VM_COVERAGE\n") + + if self.trace: + fh.write("#if VM_TRACE\n") + fh.write(" if (tfp) tfp->close();\n") + fh.write(" tfp.reset();\n") + fh.write("#endif // VM_TRACE\n") + + fh.write(" topp.reset();\n") + fh.write(" return 0;\n") + fh.write("}\n") + + def _print_advance_time(self, fh, timeinc: str, action: bool) -> None: + setp = "" if self.sc else "topp->" + if self.sc: + fh.write(" sc_start(" + str(timeinc) + " * MAIN_TIME_MULTIPLIER, " + + self.sc_time_resolution + ");\n") + else: + if action: + fh.write(" " + setp + "eval();\n") + if self.trace and not self.sc: + fh.write("#if VM_TRACE\n") + fh.write(" if (tfp) tfp->dump(contextp->time());\n") + fh.write("#endif // VM_TRACE\n") + fh.write(" contextp->timeInc(" + str(timeinc) + " * MAIN_TIME_MULTIPLIER);\n") + + ####################################################################### + + def _make_top(self, needed=True) -> None: + if not needed: + return + self._make_top_v() + + def _make_top_v(self) -> None: + self._read_inputs_v() + + with open(self.top_shell_filename(), 'w', encoding="utf8") as fh: + fh.write("module top;\n") + for inp in sorted(self._inputs.keys()): + fh.write(" reg " + inp + ";\n") + # Inst + fh.write(" t t (\n") + comma = "" + for inp in sorted(self._inputs.keys()): + fh.write(" " + comma + "." + inp + " (" + inp + ")\n") + comma = "," + fh.write(" );\n") + + # Waves + fh.write("\n") + fh.write("`ifdef WAVES\n") + fh.write(" initial begin\n") + fh.write(" $display(\"-Tracing Waves to Dumpfile: " + self.trace_filename + + "\");\n") + fh.write(" $dumpfile(\"" + self.trace_filename + "\");\n") + fh.write(" $dumpvars(0, top);\n") + fh.write(" end\n") + fh.write("`endif\n") + + # Test + fh.write("\n") + fh.write(" initial begin\n") + if 'fastclk' in self._inputs: + fh.write(" fastclk = 0;\n") + if 'clk' in self._inputs: + fh.write(" clk = 0;\n") + fh.write(" #10;\n") + if 'fastclk' in self._inputs: + fh.write(" fastclk = 1;\n") + if 'clk' in self._inputs: + fh.write(" clk = 1;\n") + fh.write(" while (" + time + " < " + self.sim_time + ") begin\n") + for i in range(6): + fh.write(" #1;\n") + if 'fastclk' in self._inputs: + fh.write(" fastclk = !fastclk;\n") + if i == 4 and 'clk' in self._inputs: + fh.write(" clk = !clk;\n") + fh.write(" end\n") + fh.write(" end\n") + + fh.write("endmodule\n") + + ####################################################################### + + def _read_inputs_v(self) -> None: + filename = self.top_filename + if not os.path.exists(filename): + filename = self.t_dir + '/' + filename + with open(filename, 'r', encoding="utf8") as fh: + get_sigs = True + inputs = {} + for line in fh: + if get_sigs: + m = re.match(r'^\s*input\s*(\S+)\s*(\/[^\/]+\/|)\s*;', line) + if m: + inputs[m.group(1)] = m.group(1) + if re.match(r'^\s*(function|task|endmodule)', line): + get_sigs = False + # Ignore any earlier inputs; Module 't' has precedence + if re.match(r'^\s*module\s+t\b', line): + inputs = {} + get_sigs = True + for sig, val in inputs.items(): + self._inputs[sig] = val + + ####################################################################### + # File utilities + + def files_identical(self, fn1: str, fn2: str, is_logfile=False) -> None: + """Test if two files have identical contents""" + for tryn in range(self.tries() - 1, -1, -1): + if tryn != self.tries() - 1: + time.sleep(1) + moretry = tryn != 0 + if not self._files_identical_try( + fn1=fn1, fn2=fn2, is_logfile=is_logfile, moretry=moretry): + break + + def _files_identical_try(self, fn1: str, fn2: str, is_logfile: bool, moretry: bool) -> bool: + try: + f1 = open( # pylint: disable=consider-using-with + fn1, 'r', encoding='latin-1', newline='\n') + except FileNotFoundError: + f1 = None + if not moretry: + self.error("Files_identical file does not exist: " + fn1) + return True + try: + f2 = open( # pylint: disable=consider-using-with + fn2, 'r', encoding='latin-1', newline='\n') + except FileNotFoundError: + f2 = None + if 'HARNESS_UPDATE_GOLDEN' not in os.environ: + if not moretry: + self.error("Files_identical file does not exist: " + fn2) + return True + ok = self._files_identical_reader(f1, + f2, + fn1=fn1, + fn2=fn2, + is_logfile=is_logfile, + moretry=moretry) + if f1: + f1.close() + if f2: + f2.close() + return ok + + def _files_identical_reader(self, f1, f2, fn1: str, fn2: str, is_logfile: bool, + moretry: bool) -> None: + l1s = f1.readlines() + l2s = f2.readlines() if f2 else [] + # print(" rawGOT="+pformat(l1s)+"\n rawEXP="+pformat(l2s)) + if is_logfile: + l1o = [] + for line in l1s: + if (re.match(r'^- [^\n]+\n', line) or re.match(r'^- [a-z.0-9]+:\d+:[^\n]+\n', line) + or re.match(r'^-node:', line) or re.match(r'^dot [^\n]+\n', line) + or re.match(r'^Aborted \(core dumped\)', line) + or re.match(r'^dot [^\n]+\n', line) + or re.match(r'^In file: .*\/sc_.*:\d+', line) + or re.match(r'^libgcov.*', line) + or re.match(r'--- \/tmp\/', line) # t_difftree.py + or re.match(r'\+\+\+ \/tmp\/', line) # t_difftree.py + or re.match(r'^==[0-9]+== ?[^\n]*\n', line)): # valgrind + continue + # Don't put control chars or unstable lines into source repository + while True: + (line, didn) = re.subn(r'(Internal Error: [^\n]+?\.(cpp|h)):[0-9]+', r'\1:#', + line) + if not didn: + break + # --vlt vs --vltmt run differences + line = re.sub(r'^-V\{t[0-9]+,[0-9]+\}', '-V{t#,#}', line) + line = re.sub(r'\r', '<#013>', line) + line = re.sub(r'Command Failed[^\n]+', 'Command Failed', line) + line = re.sub(r'Version: Verilator[^\n]+', 'Version: Verilator ###', line) + line = re.sub(r'CPU Time: +[0-9.]+ seconds[^\n]+', 'CPU Time: ###', line) + line = re.sub(r'\?v=[0-9.]+', '?v=latest', line) # warning URL + line = re.sub(r'_h[0-9a-f]{8}_', '_h########_', line) + line = re.sub(r'%Error: /[^: ]+/([^/:])', r'%Error: .../\1', + line) # Avoid absolute paths + line = re.sub(r' \/[^ ]+\/verilated_std.sv', ' verilated_std.sv', line) + # + (line, n) = re.subn(r'Exiting due to.*', r"Exiting due to", line) + if n: + l1o.append(line) + break # Trunc rest + l1o.append(line) + # + l1s = l1o + + for lineno_m1 in range(0, max(len(l1s), len(l2s))): + l1 = l1s[lineno_m1] if lineno_m1 < len(l1s) else "*EOF*\n" + l2 = l2s[lineno_m1] if lineno_m1 < len(l2s) else "*EOF*\n" + if l1 != l2: + # print(" clnGOT="+pformat(l1s)+"\n clnEXP="+pformat(l2s)) + if moretry: + return True + self.error_keep_going("Line " + str(lineno_m1) + " miscompares; " + fn1 + " != " + + fn2) + for c in range(min(len(l1), len(l2))): + if ord(l1[c]) != ord(l2[c]): + print("Miscompare starts at column " + str(c) + + (" w/ F1(got)=0x%02x F2(exp)=0x%02x" % (ord(l1[c]), ord(l2[c]))), + file=sys.stderr) + break + print("F1(got): " + l1 + "F2(exp): " + l2, file=sys.stderr) + if 'HARNESS_UPDATE_GOLDEN' in os.environ: # Update golden files with current + print("%Warning: HARNESS_UPDATE_GOLDEN set: cp " + fn1 + " " + fn2, + file=sys.stderr) + with open(fn2, 'w', encoding="utf8") as fhw: + fhw.write(''.join(l1s)) + else: + print("To update reference: HARNESS_UPDATE_GOLDEN=1 {command} or --golden", + file=sys.stderr) + return False + + return True + + def files_identical_sorted(self, fn1: str, fn2: str, is_logfile=False) -> None: + """Test if two files, after sorting both, have identical contents""" + # Set LC_ALL as suggested in the sort manpage to avoid sort order + # changes from the locale. + os.environ['LC_ALL'] = 'C' + fn1sort = fn1 + '.sort' + self.run(cmd=['sort', fn1, "> " + fn1sort]) + self.files_identical(fn1sort, fn2, is_logfile) + + def copy_if_golden(self, fn1: str, fn2: str) -> None: + """Copy a file if updating golden .out files""" + if 'HARNESS_UPDATE_GOLDEN' in os.environ: # Update golden files with current + print("%Warning: HARNESS_UPDATE_GOLDEN set: cp " + fn1 + " " + fn2, file=sys.stderr) + shutil.copy(fn1, fn2) + + def vcd_identical(self, fn1: str, fn2: str) -> None: + """Test if two VCD files have logically-identical contents""" + # vcddiff to check transitions, if installed + cmd = "vcddiff --help" + out = test.run_capture(cmd, check=True) + cmd = 'vcddiff ' + fn1 + ' ' + fn2 + out = test.run_capture(cmd, check=True) + if out != "": + cmd = 'vcddiff ' + fn2 + " " + fn1 # Reversed arguments + out = VtOs.run_capture(cmd, check=False) + if out != "": + print(out) + self.copy_if_golden(fn1, fn2) + self.error("VCD miscompares " + fn2 + " " + fn1) + + # vcddiff doesn't check module and variable scope, so check that + # Also provides backup if vcddiff not installed + h1 = self._vcd_read(fn1) + h2 = self._vcd_read(fn2) + a = json.dumps(h1, sort_keys=True, indent=1) + b = json.dumps(h2, sort_keys=True, indent=1) + if a != b: + self.copy_if_golden(fn1, fn2) + self.error("VCD hier miscompares " + fn1 + " " + fn2 + "\nGOT=" + a + "\nEXP=" + b + + "\n") + + def fst2vcd(self, fn1: str, fn2: str) -> None: + cmd = "fst2vcd -h" + out = VtOs.run_capture(cmd, check=False) + if out == "" or not re.search(r'Usage:', out): + self.skip("No fst2vcd installed") + return + + cmd = 'fst2vcd -e -f "' + fn1 + '" -o "' + fn2 + '"' + print("\t " + cmd + "\n") # Always print to help debug race cases + out = VtOs.run_capture(cmd, check=False) + print(out) + + def fst_identical(self, fn1: str, fn2: str) -> None: + """Test if two FST files have logically-identical contents""" + tmp = fn1 + ".vcd" + self.fst2vcd(fn1, tmp) + self.vcd_identical(tmp, fn2) + + def _vcd_read(self, filename: str) -> str: + data = {} + with open(filename, 'r', encoding='latin-1') as fh: + hier_stack = ["TOP"] + var = [] + for line in fh: + match1 = re.search(r'\$scope (module|struct|interface)\s+(\S+)', line) + match2 = re.search(r'(\$var (\S+)\s+\d+\s+)\S+\s+(\S+)', line) + match3 = re.search(r'(\$attrbegin .* \$end)', line) + line = line.rstrip() + # print("VR"+ ' '*len(hier_stack) +" L " + line) + if match1: # $scope + name = match1.group(2) + # print("VR"+ ' '*len(hier_stack) +" scope " + line) + hier_stack += [name] + scope = '.'.join(hier_stack) + data[scope] = match1.group(1) + " " + name + elif match2: # $var + # print("VR"+ ' '*len(hier_stack) +" var " + line) + scope = '.'.join(hier_stack) + var = match2.group(2) + data[scope + "." + var] = match2.group(1) + match2.group(3) + elif match3: # $attrbegin + # print("VR"+ ' '*len(hier_stack) +" attr " + line) + if var: + scope = '.'.join(hier_stack) + data[scope + "." + var + "#"] = match3.group(1) + elif re.search(r'\$enddefinitions', line): + break + n = len(re.findall(r'\$upscope', line)) + if n: + for i in range(0, n): # pylint: disable=unused-variable + # print("VR"+ ' '*len(hier_stack) +" upscope " + line) + hier_stack.pop() + return data + + def inline_checks(self) -> None: + covfn = self.coverage_filename + contents = self.file_contents(covfn) + + if self.verbose: + self.oprint("Extract checks") + with open(self.top_filename, 'r', encoding="utf8") as fh: + flineno = 0 + for line in fh: + flineno += 1 + if re.search(r'CHECK', line): + match1 = re.search( + r'CHECK_COVER *\( *((-|[0-9])+) *,' + r'*"([^"]+)" *, *("([^"]+)" *,|) *(\d+) *\)', line) + match2 = re.search(r'CHECK_COVER_MISSING *\( *((-|[0-9])+) *\)', line) + if match1: + lineno = flineno + int(match1.group(1)) + hier = match1.group(3) + comment = match1.group(5) + count = match1.group(6) + regexp = "\001l\002" + str(lineno) + if comment: + regexp += ".*\001o\002" + re.escape(comment) + if hier: + regexp += ".*\001h\002" + re.escape(hier) + regexp += ".*' " + str(count) + if not re.search(regexp, contents): + self.error("CHECK_COVER: " + covfn + ":" + str(flineno) + + ": Regexp not found: " + regexp + "\n" + "From " + + self.top_filename + ": " + line) + elif match2: + lineno = flineno + int(match2.group(1)) + regexp = "\001l\002" + str(lineno) + if re.search(regexp, contents): + self.error("CHECK_COVER_MISSING: " + covfn + ":" + str(flineno) + + ": Regexp found: " + regexp + "\n" + "From " + + self.top_filename + ": " + line) + else: + self.error(self.top_filename + ":" + str(flineno) + + ": Unknown CHECK request: " + line) + + @staticmethod + def cfg_with_ccache() -> bool: + if VlTest._cached_cfg_with_ccache is None: + mkf = VlTest._file_contents_static(os.environ['VERILATOR_ROOT'] + + "/include/verilated.mk") + VlTest._cached_cfg_with_ccache = bool(re.match(r'OBJCACHE \?= ccache', mkf)) + return VlTest._cached_cfg_with_ccache + + @staticmethod + def tries() -> int: + # Number of retries when reading logfiles, generally only need many + # retries when system is busy running a lot of tests + if not forker.running: + return 2 + if len(Arg_Tests) > 3: + return 7 + return 2 + + def glob_some(self, pattern: str) -> list: + """Return list of filenames matching a glob, with at least one match required.""" + files = glob.glob(pattern) + # print("glob_some('" + pattern + "') files =\n " + pformat(files)) + if not files: + self.error("glob_one: pattern '" + pattern + "' does not match any files") + return ['No_file_found'] + return sorted(files) + + def glob_one(self, pattern: str) -> str: + """Return a filename matching a glob, with exactly one match required.""" + files = self.glob_some(pattern) + if files and len(files) > 1: + msg = "glob_one: pattern '" + pattern + "' matches multiple files:\n" + for file in files: + msg += file + "\n" + self.error(msg) + return 'Multiple_files_found' + return files[0] + + def file_grep_not(self, filename: str, regexp) -> None: + contents = self.file_contents(filename) + if contents == "_Already_Errored_": + return + if re.search(regexp, contents, re.MULTILINE): + self.error("File_grep_not: " + filename + ": Regexp found: '" + regexp + "'") + + def file_grep(self, filename: str, regexp, expvalue=None) -> list: + contents = self.file_contents(filename) + if contents == "_Already_Errored_": + return None + match = re.search(regexp, contents, re.MULTILINE) + if not match: + self.error("File_grep: " + filename + ": Regexp not found: " + regexp) + return None + if expvalue and str(expvalue) != match.group(1): + self.error("File_grep: " + filename + ": Got='" + match.group(1) + "' Expected='" + + str(expvalue) + "' in regexp: '" + regexp + "'") + return None + return [match.groups()] + + def file_grep_count(self, filename: str, regexp, expcount: int) -> None: + contents = self.file_contents(filename) + if contents == "_Already_Errored_": + return + count = len(re.findall(regexp, contents)) + if expcount != count: + self.error("File_grep_count: " + filename + ": Got='" + count + "' Expected='" + + expcount + "' in regexp: '" + regexp + "'") + + def file_grep_any(self, filenames: list, regexp, expvalue=None) -> None: + for filename in filenames: + contents = self.file_contents(filename) + if contents == "_Already_Errored_": + return + match = re.search(regexp, contents) + if match: + if expvalue and str(expvalue) != match.group(1): + self.error("file_grep: " + filename + ": Got='" + match.group(1) + + "' Expected='" + str(expvalue) + "' in regexp: " + regexp) + return + msg = "file_grep_any: Regexp '" + regexp + "' not found in any of the following files:\n" + for filename in filenames: + msg += filename + "\n" + self.error(msg) + + def file_contents(self, filename: str) -> str: + if filename not in self._file_contents_cache: + if not os.path.exists(filename): + self._file_contents_cache[filename] = "_Already_Errored_" + self.error("File_contents file not found: " + filename) + else: + with open(filename, 'r', encoding='latin-1') as fh: + self._file_contents_cache[filename] = str(fh.read()) + return self._file_contents_cache[filename] + + @staticmethod + def _file_contents_static(filename: str) -> str: + if filename not in VlTest._file_contents_cache: + if not os.path.exists(filename): + VlTest._file_contents_cache[filename] = "_Already_Errored_" + sys.exit("_file_contents_static file not found: " + filename) + else: + with open(filename, 'r', encoding='latin-1') as fh: + VlTest._file_contents_cache[filename] = str(fh.read()) + return VlTest._file_contents_cache[filename] + + def write_wholefile(self, filename: str, contents: str) -> None: + with open(filename, 'wb') as fh: + fh.write(contents.encode('latin-1')) + if filename in self._file_contents_cache: + del self._file_contents_cache[filename] + + def file_sed(self, in_filename: str, out_filename, edit_lambda) -> None: + contents = self.file_contents(in_filename) + contents = edit_lambda(contents) + self.write_wholefile(out_filename, contents) + + def extract( + self, + in_filename: str, + out_filename: str, + regexp=r'.*', + lineno_adjust=-9999, # + lines=None) -> None: #'#, #-#' + temp_fn = out_filename + temp_fn = re.sub(r'.*/', '', temp_fn) + temp_fn = self.obj_dir + "/" + temp_fn + + out = [] + emph = "" + lineno = 0 + lineno_out = 0 + with open(in_filename, 'r', encoding="latin-1") as fh: + for line in fh: + lineno += 1 + if re.search(regexp, line) and self._lineno_match(lineno, lines): + match = re.search(r't/[A-Za-z0-9_]+.v:(\d+):(\d+):', line) + if match: + mlineno = int(match.group(1)) + lineno_adjust + col = int(match.group(2)) + mlineno = max(1, mlineno) + line = re.sub(r't/[A-Za-z0-9_]+.v:(\d+):(\d+):', + 'example.v:' + str(mlineno) + ':' + str(col), line) + out.append(" " + line) + lineno_out += 1 + if '<--' in line: + if emph: + emph += "," + emph += str(lineno_out) + + with open(temp_fn, 'w', encoding="latin-1") as fhw: + lang = " sv" if re.search(r'\.s?vh?$', in_filename) else "" + fhw.write(".. comment: generated by " + self.name + "\n") + fhw.write(".. code-block::" + lang + "\n") + if lang != "" and len(out) > 1: + fhw.write(" :linenos:\n") + if emph: + fhw.write(" :emphasize-lines: " + emph + "\n") + fhw.write("\n") + for line in out: + fhw.write(line) + + self.files_identical(temp_fn, out_filename) + + @staticmethod + def _lineno_match(lineno: int, lines: str) -> bool: + if not lines: + return True + for lc in lines.split(','): + match1 = re.match(r'^(\d+)$', lc) + match2 = re.match(r'^(\d+)-(\d+)$', lc) + if match1 and int(match1.group(1)) == lineno: + return True + if match2 and int(match2.group(1)) <= lineno <= int(match2.group(2)): + return True + return False + + +###################################################################### +###################################################################### +# Global Functions + + +def calc_jobs() -> int: + ok_threads = max_procs() + print("driver.py: Found %d cores, using -j %d" % (ok_threads, ok_threads)) + return ok_threads + + +def calc_threads(default_threads) -> int: + ok_threads = max_procs() + return ok_threads if (ok_threads < default_threads) else default_threads + + +def _calc_hashset() -> list: + match = re.match(r'^(\d+)/(\d+)$', Args.hashset) + if not match: + sys.exit("%Error: Need number/number format for --hashset: " + Args.hashset) + setn = int(match.group(1)) + nsets = int(match.group(2)) + new = [] + global Arg_Tests + for t in Arg_Tests: + checksum = int(hashlib.sha256(t.encode("utf-8")).hexdigest()[0:4], 16) + if (setn % nsets) == (checksum % nsets): + new.append(t) + Arg_Tests = new + + +####################################################################### +####################################################################### +# Verilator utilities + + +@lru_cache(maxsize=1) +def max_procs() -> int: + procs = multiprocessing.cpu_count() + if procs < 2: + print("driver.py: Python didn't find at least two CPUs") + return procs + + +def _parameter(param: str) -> None: + global _Parameter_Next_Level + if _Parameter_Next_Level: + if not re.match(r'^(\d+)$', _Parameter_Next_Level): + sys.exit("%Error: Expected number following " + _Parameter_Next_Level + ": " + param) + Arg_Driver_Verilator_Flags.append(param) + _Parameter_Next_Level = None + elif re.search(r'\.py', param): + Arg_Tests.append(param) + elif re.match(r'^-?(-debugi|-dumpi)', param): + Arg_Driver_Verilator_Flags.append(param) + _Parameter_Next_Level = param + elif re.match(r'^-?(-W||-debug-check)', param): + Arg_Driver_Verilator_Flags.append(param) + else: + sys.exit("%Error: Unknown parameter: " + param) + + +def run_them() -> None: + VtOs.mkdir_ok("obj_dist") + timestart = time.strftime("%Y%m%d_%H%M%S") + + runner = Runner(driver_log_filename="obj_dist/driver_" + timestart + ".log", quiet=Args.quiet) + for test_py in Arg_Tests: + for scenario in sorted(set(Args.scenarios)): + if VlTest._prefilter_scenario(test_py, scenario): + runner.one_test(py_filename=test_py, scenario=scenario) + runner.wait_and_report() + + if Args.rerun and runner.fail_cnt: + print('=' * 70) + print('=' * 70) + print("RERUN ==\n") + + # Avoid parallel run to ensure that isn't causing problems + # If > 10 failures something more wrong and get results quickly + if runner.fail_cnt < 10: + forker.max_proc(1) + + orig_runner = runner + runner = Runner(driver_log_filename="obj_dist/driver_" + timestart + "_rerun.log", + quiet=False, + fail1_cnt=orig_runner.fail_cnt, + ok_cnt=orig_runner.ok_cnt, + skip_cnt=orig_runner.skip_cnt) + for ftest in orig_runner.fail_tests: + # Reschedule test + if ftest.rerunnable: + ftest.clean() + runner.one_test(py_filename=ftest.py_filename, + scenario=ftest.scenario, + rerun_skipping=not ftest.rerunnable) + + runner.wait_and_report() + + if runner.fail_cnt: + sys.exit(10) + + +###################################################################### +###################################################################### +# Globals + +os.environ['PYTHONUNBUFFERED'] = "1" + +if ('VERILATOR_ROOT' not in os.environ) and os.path.isfile('../bin/verilator'): + os.environ['VERILATOR_ROOT'] = os.getcwd() + "/.." +if 'MAKE' not in os.environ: + os.environ['MAKE'] = "make" +if 'CXX' not in os.environ: + os.environ['CXX'] = "c++" +if 'TEST_REGRESS' in os.environ: + sys.exit("%Error: TEST_REGRESS environment variable is already set") +os.environ['TEST_REGRESS'] = os.getcwd() + +forker = None +Start = time.time() +Vltmt_Threads = 3 +_Parameter_Next_Level = None + + +def sig_term(signum, env) -> None: # pylint: disable=unused-argument + if forker: + forker.kill_tree_all() + sys.exit("Quitting...") + + +signal.signal(signal.SIGTERM, sig_term) + +Orig_ARGV_Sw = [] +for arg in sys.argv: + if re.match(r'^-', arg) and not re.match(r'^-j', arg): + Orig_ARGV_Sw.append(arg) + +#--------------------------------------------------------------------- + +parser = argparse.ArgumentParser( + allow_abbrev=False, + formatter_class=argparse.RawDescriptionHelpFormatter, + description="""Run Verilator regression tests""", + epilog="""driver.py invokes Verilator or another simulator on each test file. +See docs/internals.rst in the distribution for more information. + +Copyright 2024-2024 by Wilson Snyder. This program is free software; you +can redistribute it and/or modify it under the terms of either the GNU +Lesser General Public License Version 3 or the Perl Artistic License +Version 2.0. + +SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""") + +parser.add_argument('--benchmark', action='store', help='enable benchmarking') +parser.add_argument('--debug', action='store_const', const=9, help='enable debug') +# --debugi: see _parameter() +parser.add_argument('--fail-max', + action='store', + default=None, + help='run Verilator executable with gdb') +parser.add_argument('--gdb', action='store_true', help='run Verilator executable with gdb') +parser.add_argument('--gdbbt', + action='store_true', + help='run Verilated executable with gdb and backtrace') +parser.add_argument('--gdbsim', action='store_true', help='run Verilated executable with gdb') +parser.add_argument('--golden', '--gold', action='store_true', help='update golden .out files') +parser.add_argument('--hashset', action='store', help='split tests based on /') +parser.add_argument('--jobs', + '-j', + action='store', + default=0, + type=int, + help='parallel job count (0=cpu count)') +parser.add_argument('--quiet', + action='store_true', + help='suppress output except failures and progress') +parser.add_argument('--rerun', action='store_true', help='rerun all tests that fail') +parser.add_argument('--rr', action='store_true', help='run Verilator executable with rr') +parser.add_argument('--rrsim', action='store_true', help='run Verilated executable with rr') +parser.add_argument('--sanitize', action='store_true', help='run address sanitizer') +parser.add_argument('--site', action='store_true', help='include VERILATOR_TEST_SITE test list') +parser.add_argument('--stop', action='store_true', help='stop on the first error') +parser.add_argument('--trace', action='store_true', help='enable simulator waveform tracing') +parser.add_argument('--verbose', action='store_true', help='compile and run test in verbose mode') +parser.add_argument( + '--verilation', # -no-verilation undocumented debugging + action='store_true', + default=True, + help="don't run verilator compile() phase") +parser.add_argument('--verilated-debug', + action='store_true', + help='enable Verilated executable debug') +## Scenarios +for scen, v in All_Scenarios.items(): + parser.add_argument('--' + scen, + dest='scenarios', + action='append_const', + const=scen, + help='scenario-enable ' + scen) + +(Args, rest) = parser.parse_known_intermixed_args() + +for arg in rest: + _parameter(arg) + +if Args.debug: + Arg_Driver_Verilator_Flags.append("--debug --no-skip-identical") + logging.basicConfig(level=logging.DEBUG) + logging.info("In driver.py, ARGV=" + pformat(sys.argv)) + +if Args.golden: + os.environ['HARNESS_UPDATE_GOLDEN'] = '1' +if Args.jobs == 0: + Args.jobs = calc_jobs() +if not Args.scenarios: + Args.scenarios = [] + Args.scenarios.append('dist') + Args.scenarios.append('vlt') + +interactive_debugger = Args.gdb or Args.gdbsim or Args.rr or Args.rrsim +if Args.jobs > 1 and interactive_debugger: + sys.exit("%Error: Unable to use -j > 1 with --gdb* and --rr* options") + +forker = Forker(Args.jobs) + +Test_Dirs = ["t"] +if 'VERILATOR_TESTS_SITE' in os.environ: + if Args.site or len(Arg_Tests) >= 1: + for tdir in os.environ['VERILATOR_TESTS_SITE'].split(':'): + Test_Dirs.append(tdir) + +if not Arg_Tests: # Run everything + uniq = {} + for tdir in Test_Dirs: + # Uniquify by inode, so different paths to same place get combined + stats = os.stat(tdir) + if stats.st_ino not in uniq: + uniq[stats.st_ino] = 1 + Arg_Tests += sorted(glob.glob(tdir + "/t_*.py")) +if Args.hashset: + _calc_hashset() + +if len(Arg_Tests) >= 2 and Args.jobs >= 2: + # Read supported into master process, so don't call every subprocess + Capabilities.warmup_cache() + # Without this tests such as t_debug_sigsegv_bt_bad.py will occasionally + # block on input and cause a SIGSTOP, then a "fg" was needed to resume testing. + print("== Many jobs; redirecting STDIN", file=sys.stderr) + # + sys.stdin = open("/dev/null", 'r', encoding="utf8") # pylint: disable=consider-using-with + +run_them() diff --git a/test_regress/t/t_EXAMPLE.pl b/test_regress/t/t_EXAMPLE.pl deleted file mode 100755 index 3708008f8..000000000 --- a/test_regress/t/t_EXAMPLE.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_EXAMPLE.py b/test_regress/t/t_EXAMPLE.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_EXAMPLE.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_a1_first_cc.pl b/test_regress/t/t_a1_first_cc.pl deleted file mode 100755 index 8d895e8e6..000000000 --- a/test_regress/t/t_a1_first_cc.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# show-config: This test runs the very first time we've executed Verilator -# after building so we make sure to run with --gdbbt, so if it dumps we'll -# get a trace. - -scenarios(simulator => 1); - -$DEBUG_QUIET = "--debug --debugi 0 --gdbbt --no-dump-tree"; - -run(cmd => ["perl", "$ENV{VERILATOR_ROOT}/bin/verilator", $DEBUG_QUIET, "-V"], - verilator_run => 1, - ); - -compile( - verilator_flags2 => [$DEBUG_QUIET, "--trace"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_a1_first_cc.py b/test_regress/t/t_a1_first_cc.py new file mode 100755 index 000000000..fd253303d --- /dev/null +++ b/test_regress/t/t_a1_first_cc.py @@ -0,0 +1,33 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +# show-config: This test runs the very first time we've executed Verilator +# after building so we make sure to run with --gdbbt, so if it dumps we'll +# get a trace. + +import vltest_bootstrap + +test.scenarios('vlt') + +DEBUG_QUIET = "--debug --debugi 0 --gdbbt --no-dump-tree" + +test.run( + cmd=[ + "perl", + os.environ["VERILATOR_ROOT"] + "/bin/verilator", # + DEBUG_QUIET, + "-V" + ], + verilator_run=True) + +test.compile(verilator_flags2=[DEBUG_QUIET, "--trace"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_a2_first_sc.pl b/test_regress/t/t_a2_first_sc.pl deleted file mode 100755 index b5406187a..000000000 --- a/test_regress/t/t_a2_first_sc.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# This test runs the very first time we've executed Verilator --sc -# after building so we make sure to run with --gdbbt, so if it dumps we'll -# get a trace. - -scenarios(simulator => 1); - -top_filename("t/t_a1_first_cc.v"); - -$DEBUG_QUIET = "--debug --debugi 0 --gdbbt --no-dump-tree"; - -compile( - verilator_flags2 => [$DEBUG_QUIET, "-sc --trace"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_a2_first_sc.py b/test_regress/t/t_a2_first_sc.py new file mode 100755 index 000000000..f8123f6db --- /dev/null +++ b/test_regress/t/t_a2_first_sc.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +# This test runs the very first time we've executed Verilator --sc +# after building so we make sure to run with --gdbbt, so if it dumps we'll +# get a trace. + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_a1_first_cc.v" + +DEBUG_QUIET = "--debug --debugi 0 --gdbbt --no-dump-tree" + +test.compile(verilator_flags2=[DEBUG_QUIET, "-sc --trace"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_a3_selftest.pl b/test_regress/t/t_a3_selftest.pl deleted file mode 100755 index a0a71531c..000000000 --- a/test_regress/t/t_a3_selftest.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_EXAMPLE.v"); - -compile( - verilator_flags2 => ['--debug-self-test'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -ok(1); -1; diff --git a/test_regress/t/t_a3_selftest.py b/test_regress/t/t_a3_selftest.py new file mode 100755 index 000000000..dc4bcb78f --- /dev/null +++ b/test_regress/t/t_a3_selftest.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_EXAMPLE.v" + +test.compile(verilator_flags2=['--debug-self-test'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.passes() diff --git a/test_regress/t/t_a3_selftest_thread.pl b/test_regress/t/t_a3_selftest_thread.pl deleted file mode 100755 index a47da043c..000000000 --- a/test_regress/t/t_a3_selftest_thread.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_EXAMPLE.v"); - -lint( - v_flags => ["--lint-only --verilate-jobs 2 --debug-self-test"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_a3_selftest_thread.py b/test_regress/t/t_a3_selftest_thread.py new file mode 100755 index 000000000..6f8a00043 --- /dev/null +++ b/test_regress/t/t_a3_selftest_thread.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vltmt') +test.top_filename = "t/t_EXAMPLE.v" + +test.lint(v_flags=["--lint-only --verilate-jobs 2 --debug-self-test"]) + +test.passes() diff --git a/test_regress/t/t_a5_attributes_include.pl b/test_regress/t/t_a5_attributes_include.pl deleted file mode 100755 index 3ae096f50..000000000 --- a/test_regress/t/t_a5_attributes_include.pl +++ /dev/null @@ -1,49 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(dist => 1); -rerunnable(0); - -my $root = ".."; - -if ($ENV{VERILATOR_TEST_NO_ATTRIBUTES}) { - skip("Skipping due to VERILATOR_TEST_NO_ATTRIBUTES"); -} elsif (!-r "$root/.git") { - skip("Not in a git repository"); -} else { - check(); -} -sub check { - my $root = ".."; - # some of the files are only used in Verilation - # and are only in "include" folder - my @srcfiles = glob("$root/include/*.cpp"); - my $srcfiles_str = join(" ", @srcfiles); - my $clang_args = "-I$root/include/ -I$root/include/vltstd/ -fcoroutines-ts"; - - sub run_clang_check { - { - my $cmd = qq{python3 -c "from clang.cindex import Index; index = Index.create(); print(\\"Clang imported\\")";}; - print "\t$cmd\n" if $::Debug; - my $out = `$cmd`; - if (!$out || $out !~ /Clang imported/) { skip("No libclang installed\n"); return 1; } - } - run(logfile => $Self->{run_log_filename}, - tee => 1, - cmd => ["python3", "$root/nodist/clang_check_attributes --verilator-root=$root --cxxflags='$clang_args' $srcfiles_str"]); - - file_grep($Self->{run_log_filename}, "Number of functions reported unsafe: 0"); - } - - run_clang_check(); -} - -ok(1); -1; diff --git a/test_regress/t/t_a5_attributes_include.py b/test_regress/t/t_a5_attributes_include.py new file mode 100755 index 000000000..730a6d447 --- /dev/null +++ b/test_regress/t/t_a5_attributes_include.py @@ -0,0 +1,50 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') +test.rerunnable = False + +root = ".." + + +def have_clang_check(): + cmd = 'python3 -c "from clang.cindex import Index; index = Index.create(); print(\\"Clang imported\\")";' + if test.verbose: + print("\t" + cmd) + nout = test.run_capture(cmd, check=False) + if not nout or not re.search(r'Clang imported', nout): + return False + return True + + +if 'VERILATOR_TEST_NO_ATTRIBUTES' in os.environ: + test.skip("Skipping due to VERILATOR_TEST_NO_ATTRIBUTES") +if not os.path.exists(root + "/src/obj_dbg/compile_commands.json"): + test.skip("compile_commands.json not found. Please install 'bear > 3.0' and rebuild Verilator") +if not have_clang_check(): + test.skip("No libclang installed\n") + +# some of the files are only used in Verilation +# and are only in "include" folder +srcfiles = test.glob_some(root + "/include/*.cpp") +srcfiles_str = " ".join(srcfiles) +clang_args = "-I" + root + "/include/ -I" + root + "/include/vltstd/ -fcoroutines-ts" + +test.run(logfile=test.run_log_filename, + tee=True, + cmd=["python3", root + "/nodist/clang_check_attributes", + "--verilator-root=" + root, + "--cxxflags='" + clang_args + "'", + srcfiles_str]) # yapf:disable + +test.file_grep(test.run_log_filename, r'Number of functions reported unsafe: +(\d+)', 0) + +test.passes() diff --git a/test_regress/t/t_a5_attributes_src.pl b/test_regress/t/t_a5_attributes_src.pl deleted file mode 100755 index df7f4d841..000000000 --- a/test_regress/t/t_a5_attributes_src.pl +++ /dev/null @@ -1,51 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(dist => 1); -rerunnable(0); -my $root = ".."; -if ($ENV{VERILATOR_TEST_NO_ATTRIBUTES}) { - skip("Skipping due to VERILATOR_TEST_NO_ATTRIBUTES"); -} elsif (! -e "$root/src/obj_dbg/compile_commands.json") { - skip("compile_commands.json not found. Please install 'bear > 3.0' and rebuild Verilator."); -} else { - check(); -} -sub check { - # some of the files are only used in Verilation - # and are only in "include" folder - my @srcfiles = grep { !/\/(V3Const|Vlc\w*|\w*_test|\w*_sc|\w*.yy).cpp$/ } - glob("$root/src/*.cpp $root/src/obj_dbg/V3Const__gen.cpp"); - my $srcfiles_str = join(" ", @srcfiles); - - sub run_clang_check { - { - my $cmd = qq{python3 -c "from clang.cindex import Index; index = Index.create(); print(\\"Clang imported\\")";}; - print "\t$cmd\n" if $::Debug; - my $out = `$cmd`; - if (!$out || $out !~ /Clang imported/) { skip("No libclang installed\n"); return 1; } - } - run(logfile => $Self->{run_log_filename}, - tee => 1, - cmd => ["python3", - "$root/nodist/clang_check_attributes", - "--verilator-root=$root", - "--compilation-root=$root/src/obj_dbg", - "--compile-commands-dir=$root/src/obj_dbg", - "$srcfiles_str"]); - - file_grep($Self->{run_log_filename}, "Number of functions reported unsafe: 0"); - } - - run_clang_check(); -} - -ok(1); -1; diff --git a/test_regress/t/t_a5_attributes_src.py b/test_regress/t/t_a5_attributes_src.py new file mode 100755 index 000000000..3c55ea4e2 --- /dev/null +++ b/test_regress/t/t_a5_attributes_src.py @@ -0,0 +1,52 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') +test.rerunnable = False + +root = ".." + + +def have_clang_check(): + cmd = 'python3 -c "from clang.cindex import Index; index = Index.create(); print(\\"Clang imported\\")";' + if test.verbose: + print("\t" + cmd) + nout = test.run_capture(cmd, check=False) + if not nout or not re.search(r'Clang imported', nout): + return False + return True + + +if 'VERILATOR_TEST_NO_ATTRIBUTES' in os.environ: + test.skip("Skipping due to VERILATOR_TEST_NO_ATTRIBUTES") +if not os.path.exists(root + "/src/obj_dbg/compile_commands.json"): + test.skip("compile_commands.json not found. Please install 'bear > 3.0' and rebuild Verilator") +if not have_clang_check(): + test.skip("No libclang installed\n") + +# some of the files are only used in Verilation +# and are only in "include" folder +srcfiles = test.glob_some(root + "/src/*.cpp") + test.glob_some(root + + "/src/obj_dbg/V3Const__gen.cpp") +srcfiles = [f for f in srcfiles if re.search(r'\/(V3Const|Vlc\w*|\w*_test|\w*_sc|\w*.yy).cpp$', f)] +srcfiles_str = " ".join(srcfiles) + +test.run(logfile=test.run_log_filename, + tee=True, + cmd=["python3", root + "/nodist/clang_check_attributes", + "--verilator-root=" + root, + "--compilation-root=" + root + "/src/obj_dbg", + "--compile-commands-dir=" + root + "/src/obj_dbg", + srcfiles_str]) # yapf:disable + +test.file_grep(test.run_log_filename, r'Number of functions reported unsafe: +(\d+)', 0) + +test.passes() diff --git a/test_regress/t/t_a6_examples.pl b/test_regress/t/t_a6_examples.pl deleted file mode 100755 index c2b374144..000000000 --- a/test_regress/t/t_a6_examples.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(dist => 1); - -$Self->{clean_command} = 'rm -rf ../examples/*/build ../examples/*/obj*'; - -my @examples = sort(glob("../examples/*")); -for my $example (@examples) { - run(cmd => ["$ENV{MAKE} -C $example"]); -} - -ok(1); -1; diff --git a/test_regress/t/t_a6_examples.py b/test_regress/t/t_a6_examples.py new file mode 100755 index 000000000..8d2bb7005 --- /dev/null +++ b/test_regress/t/t_a6_examples.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +test.clean_command = '/bin/rm -rf ../examples/*/build ../examples/*/obj*' + +root = ".." + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +examples = sorted(test.glob_some(root + "/examples/*")) +for example in examples: + test.run(cmd=[os.environ["MAKE"], "-C", example]) + +test.passes() diff --git a/test_regress/t/t_alias2_unsup.pl b/test_regress/t/t_alias2_unsup.pl deleted file mode 100755 index 06b988a99..000000000 --- a/test_regress/t/t_alias2_unsup.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_alias2_unsup.py b/test_regress/t/t_alias2_unsup.py new file mode 100755 index 000000000..272fc1280 --- /dev/null +++ b/test_regress/t/t_alias2_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_alias_unsup.pl b/test_regress/t/t_alias_unsup.pl deleted file mode 100755 index 06b988a99..000000000 --- a/test_regress/t/t_alias_unsup.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_alias_unsup.py b/test_regress/t/t_alias_unsup.py new file mode 100755 index 000000000..272fc1280 --- /dev/null +++ b/test_regress/t/t_alias_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_abs.pl b/test_regress/t/t_altera_lpm_abs.pl deleted file mode 100755 index e079ef062..000000000 --- a/test_regress/t/t_altera_lpm_abs.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_abs.py b/test_regress/t/t_altera_lpm_abs.py new file mode 100755 index 000000000..72661f8d6 --- /dev/null +++ b/test_regress/t/t_altera_lpm_abs.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_add_sub.pl b/test_regress/t/t_altera_lpm_add_sub.pl deleted file mode 100755 index e079ef062..000000000 --- a/test_regress/t/t_altera_lpm_add_sub.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_add_sub.py b/test_regress/t/t_altera_lpm_add_sub.py new file mode 100755 index 000000000..72661f8d6 --- /dev/null +++ b/test_regress/t/t_altera_lpm_add_sub.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_and.pl b/test_regress/t/t_altera_lpm_and.pl deleted file mode 100755 index e079ef062..000000000 --- a/test_regress/t/t_altera_lpm_and.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_and.py b/test_regress/t/t_altera_lpm_and.py new file mode 100755 index 000000000..72661f8d6 --- /dev/null +++ b/test_regress/t/t_altera_lpm_and.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_bustri.pl b/test_regress/t/t_altera_lpm_bustri.pl deleted file mode 100755 index e079ef062..000000000 --- a/test_regress/t/t_altera_lpm_bustri.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_bustri.py b/test_regress/t/t_altera_lpm_bustri.py new file mode 100755 index 000000000..72661f8d6 --- /dev/null +++ b/test_regress/t/t_altera_lpm_bustri.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_clshift.pl b/test_regress/t/t_altera_lpm_clshift.pl deleted file mode 100755 index e079ef062..000000000 --- a/test_regress/t/t_altera_lpm_clshift.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_clshift.py b/test_regress/t/t_altera_lpm_clshift.py new file mode 100755 index 000000000..72661f8d6 --- /dev/null +++ b/test_regress/t/t_altera_lpm_clshift.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_compare.pl b/test_regress/t/t_altera_lpm_compare.pl deleted file mode 100755 index e079ef062..000000000 --- a/test_regress/t/t_altera_lpm_compare.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_compare.py b/test_regress/t/t_altera_lpm_compare.py new file mode 100755 index 000000000..72661f8d6 --- /dev/null +++ b/test_regress/t/t_altera_lpm_compare.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_constant.pl b/test_regress/t/t_altera_lpm_constant.pl deleted file mode 100755 index e079ef062..000000000 --- a/test_regress/t/t_altera_lpm_constant.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_constant.py b/test_regress/t/t_altera_lpm_constant.py new file mode 100755 index 000000000..72661f8d6 --- /dev/null +++ b/test_regress/t/t_altera_lpm_constant.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_counter.pl b/test_regress/t/t_altera_lpm_counter.pl deleted file mode 100755 index 3f4aa0eed..000000000 --- a/test_regress/t/t_altera_lpm_counter.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}", "--binary --no-timing"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_counter.py b/test_regress/t/t_altera_lpm_counter.py new file mode 100755 index 000000000..8863b8607 --- /dev/null +++ b/test_regress/t/t_altera_lpm_counter.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module, "--binary --no-timing"]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_decode.pl b/test_regress/t/t_altera_lpm_decode.pl deleted file mode 100755 index e079ef062..000000000 --- a/test_regress/t/t_altera_lpm_decode.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_decode.py b/test_regress/t/t_altera_lpm_decode.py new file mode 100755 index 000000000..72661f8d6 --- /dev/null +++ b/test_regress/t/t_altera_lpm_decode.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_divide.pl b/test_regress/t/t_altera_lpm_divide.pl deleted file mode 100755 index e079ef062..000000000 --- a/test_regress/t/t_altera_lpm_divide.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_divide.py b/test_regress/t/t_altera_lpm_divide.py new file mode 100755 index 000000000..72661f8d6 --- /dev/null +++ b/test_regress/t/t_altera_lpm_divide.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_ff.pl b/test_regress/t/t_altera_lpm_ff.pl deleted file mode 100755 index e079ef062..000000000 --- a/test_regress/t/t_altera_lpm_ff.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_ff.py b/test_regress/t/t_altera_lpm_ff.py new file mode 100755 index 000000000..72661f8d6 --- /dev/null +++ b/test_regress/t/t_altera_lpm_ff.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_fifo.pl b/test_regress/t/t_altera_lpm_fifo.pl deleted file mode 100755 index e079ef062..000000000 --- a/test_regress/t/t_altera_lpm_fifo.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_fifo.py b/test_regress/t/t_altera_lpm_fifo.py new file mode 100755 index 000000000..72661f8d6 --- /dev/null +++ b/test_regress/t/t_altera_lpm_fifo.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_fifo_dc.pl b/test_regress/t/t_altera_lpm_fifo_dc.pl deleted file mode 100755 index e079ef062..000000000 --- a/test_regress/t/t_altera_lpm_fifo_dc.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_fifo_dc.py b/test_regress/t/t_altera_lpm_fifo_dc.py new file mode 100755 index 000000000..72661f8d6 --- /dev/null +++ b/test_regress/t/t_altera_lpm_fifo_dc.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_inv.pl b/test_regress/t/t_altera_lpm_inv.pl deleted file mode 100755 index e079ef062..000000000 --- a/test_regress/t/t_altera_lpm_inv.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_inv.py b/test_regress/t/t_altera_lpm_inv.py new file mode 100755 index 000000000..72661f8d6 --- /dev/null +++ b/test_regress/t/t_altera_lpm_inv.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_latch.pl b/test_regress/t/t_altera_lpm_latch.pl deleted file mode 100755 index e079ef062..000000000 --- a/test_regress/t/t_altera_lpm_latch.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_latch.py b/test_regress/t/t_altera_lpm_latch.py new file mode 100755 index 000000000..72661f8d6 --- /dev/null +++ b/test_regress/t/t_altera_lpm_latch.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_mult.pl b/test_regress/t/t_altera_lpm_mult.pl deleted file mode 100755 index e079ef062..000000000 --- a/test_regress/t/t_altera_lpm_mult.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_mult.py b/test_regress/t/t_altera_lpm_mult.py new file mode 100755 index 000000000..72661f8d6 --- /dev/null +++ b/test_regress/t/t_altera_lpm_mult.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_mult_noinl.pl b/test_regress/t/t_altera_lpm_mult_noinl.pl deleted file mode 100755 index 63f8aa315..000000000 --- a/test_regress/t/t_altera_lpm_mult_noinl.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; -$module =~ s/_noinl//; - -compile( - verilator_flags2 => ["--top-module ${module}", "-fno-inline"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_mult_noinl.py b/test_regress/t/t_altera_lpm_mult_noinl.py new file mode 100755 index 000000000..82c1fef6a --- /dev/null +++ b/test_regress/t/t_altera_lpm_mult_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) +module = re.sub(r'_noinl', '', module) + +test.compile(verilator_flags2=["--top-module", module, "-fno-inline"]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_mux.pl b/test_regress/t/t_altera_lpm_mux.pl deleted file mode 100755 index e079ef062..000000000 --- a/test_regress/t/t_altera_lpm_mux.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_mux.py b/test_regress/t/t_altera_lpm_mux.py new file mode 100755 index 000000000..72661f8d6 --- /dev/null +++ b/test_regress/t/t_altera_lpm_mux.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_or.pl b/test_regress/t/t_altera_lpm_or.pl deleted file mode 100755 index e079ef062..000000000 --- a/test_regress/t/t_altera_lpm_or.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_or.py b/test_regress/t/t_altera_lpm_or.py new file mode 100755 index 000000000..72661f8d6 --- /dev/null +++ b/test_regress/t/t_altera_lpm_or.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_ram_dp.pl b/test_regress/t/t_altera_lpm_ram_dp.pl deleted file mode 100755 index e079ef062..000000000 --- a/test_regress/t/t_altera_lpm_ram_dp.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_ram_dp.py b/test_regress/t/t_altera_lpm_ram_dp.py new file mode 100755 index 000000000..72661f8d6 --- /dev/null +++ b/test_regress/t/t_altera_lpm_ram_dp.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_ram_dq.pl b/test_regress/t/t_altera_lpm_ram_dq.pl deleted file mode 100755 index e079ef062..000000000 --- a/test_regress/t/t_altera_lpm_ram_dq.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_ram_dq.py b/test_regress/t/t_altera_lpm_ram_dq.py new file mode 100755 index 000000000..72661f8d6 --- /dev/null +++ b/test_regress/t/t_altera_lpm_ram_dq.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_ram_io.pl b/test_regress/t/t_altera_lpm_ram_io.pl deleted file mode 100755 index e079ef062..000000000 --- a/test_regress/t/t_altera_lpm_ram_io.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_ram_io.py b/test_regress/t/t_altera_lpm_ram_io.py new file mode 100755 index 000000000..72661f8d6 --- /dev/null +++ b/test_regress/t/t_altera_lpm_ram_io.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_rom.pl b/test_regress/t/t_altera_lpm_rom.pl deleted file mode 100755 index e079ef062..000000000 --- a/test_regress/t/t_altera_lpm_rom.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_rom.py b/test_regress/t/t_altera_lpm_rom.py new file mode 100755 index 000000000..72661f8d6 --- /dev/null +++ b/test_regress/t/t_altera_lpm_rom.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_shiftreg.pl b/test_regress/t/t_altera_lpm_shiftreg.pl deleted file mode 100755 index e079ef062..000000000 --- a/test_regress/t/t_altera_lpm_shiftreg.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_shiftreg.py b/test_regress/t/t_altera_lpm_shiftreg.py new file mode 100755 index 000000000..72661f8d6 --- /dev/null +++ b/test_regress/t/t_altera_lpm_shiftreg.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_xor.pl b/test_regress/t/t_altera_lpm_xor.pl deleted file mode 100755 index e079ef062..000000000 --- a/test_regress/t/t_altera_lpm_xor.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_altera_lpm.v"); -(my $module = $Self->{name}) =~ s/.*t_altera_//; - -compile( - verilator_flags2 => ["--top-module ${module}"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_altera_lpm_xor.py b/test_regress/t/t_altera_lpm_xor.py new file mode 100755 index 000000000..72661f8d6 --- /dev/null +++ b/test_regress/t/t_altera_lpm_xor.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) + +test.compile(verilator_flags2=["--top-module", module]) + +test.passes() diff --git a/test_regress/t/t_alw_combdly.pl b/test_regress/t/t_alw_combdly.pl deleted file mode 100755 index fdc76316a..000000000 --- a/test_regress/t/t_alw_combdly.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_alw_combdly.py b/test_regress/t/t_alw_combdly.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_alw_combdly.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_alw_dly.pl b/test_regress/t/t_alw_dly.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_alw_dly.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_alw_dly.py b/test_regress/t/t_alw_dly.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_alw_dly.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_alw_noreorder.pl b/test_regress/t/t_alw_noreorder.pl deleted file mode 100755 index c77549922..000000000 --- a/test_regress/t/t_alw_noreorder.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_alw_reorder.v"); -compile( - verilator_flags2 => ["--stats -fno-reorder"], - ); - -file_grep($Self->{stats}, qr/Optimizations, Split always\s+(\d+)/, 0); -# Here we should see some dly vars since reorder is disabled. -# (Whereas our twin test, t_alw_reorder, should see no dly vars -# since it enables the reorder step.) -my @files = glob_all("$Self->{obj_dir}/$Self->{vm_prefix}___024root*.cpp"); -file_grep_any(\@files, qr/dly__t__DOT__v1/); -file_grep_any(\@files, qr/dly__t__DOT__v2/); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_alw_noreorder.py b/test_regress/t/t_alw_noreorder.py new file mode 100755 index 000000000..a64bbc380 --- /dev/null +++ b/test_regress/t/t_alw_noreorder.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_alw_reorder.v" +test.compile(verilator_flags2=["--stats -fno-reorder"]) + +test.file_grep(test.stats, r'Optimizations, Split always\s+(\d+)', 0) +# Here we should see some dly vars since reorder is disabled. +# (Whereas our twin test, t_alw_reorder, should see no dly vars +# since it enables the reorder step.) +files = test.glob_some(test.obj_dir + "/" + test.vm_prefix + "___024root*.cpp") +test.file_grep_any(files, r'dly__t__DOT__v1') +test.file_grep_any(files, r'dly__t__DOT__v2') + +test.execute() + +test.passes() diff --git a/test_regress/t/t_alw_nosplit.pl b/test_regress/t/t_alw_nosplit.pl deleted file mode 100755 index 8bc2c80e2..000000000 --- a/test_regress/t/t_alw_nosplit.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, Split always\s+(\d+)/, 0); -} - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_alw_nosplit.py b/test_regress/t/t_alw_nosplit.py new file mode 100755 index 000000000..e719df544 --- /dev/null +++ b/test_regress/t/t_alw_nosplit.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats"]) + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, Split always\s+(\d+)', 0) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_alw_reorder.pl b/test_regress/t/t_alw_reorder.pl deleted file mode 100755 index 31a6b80c9..000000000 --- a/test_regress/t/t_alw_reorder.pl +++ /dev/null @@ -1,34 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -file_grep($Self->{stats}, qr/Optimizations, Split always\s+(\d+)/, 0); -# Important: if reorder succeeded, we should see no dly vars. -# Equally important: twin test t_alw_noreorder should see dly vars, -# is identical to this test except for disabling the reorder step. -foreach my $file ( - glob_all("$Self->{obj_dir}/$Self->{vm_prefix}*.h"), - glob_all("$Self->{obj_dir}/$Self->{vm_prefix}*.cpp") - ) { - file_grep_not($file, qr/dly__t__DOT__v1/); - file_grep_not($file, qr/dly__t__DOT__v2/); - file_grep_not($file, qr/dly__t__DOT__v3/); -} - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_alw_reorder.py b/test_regress/t/t_alw_reorder.py new file mode 100755 index 000000000..d61a33150 --- /dev/null +++ b/test_regress/t/t_alw_reorder.py @@ -0,0 +1,29 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(verilator_flags2=["--stats"]) + +test.file_grep(test.stats, r'Optimizations, Split always\s+(\d+)', 0) + +# Important: if reorder succeeded, we should see no dly vars. +# Equally important: twin test t_alw_noreorder should see dly vars, +# is identical to this test except for disabling the reorder step. +for filename in (test.glob_some(test.obj_dir + "/" + test.vm_prefix + "*.h") + + test.glob_some(test.obj_dir + "/" + test.vm_prefix + "*.cpp")): + test.file_grep_not(filename, r'dly__t__DOT__v1') + test.file_grep_not(filename, r'dly__t__DOT__v2') + test.file_grep_not(filename, r'dly__t__DOT__v3') + +test.execute() + +test.passes() diff --git a/test_regress/t/t_alw_split.pl b/test_regress/t/t_alw_split.pl deleted file mode 100755 index 082357d85..000000000 --- a/test_regress/t/t_alw_split.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, Split always\s+(\d+)/, 4); -} - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_alw_split.py b/test_regress/t/t_alw_split.py new file mode 100755 index 000000000..08fff24cc --- /dev/null +++ b/test_regress/t/t_alw_split.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats"]) + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, Split always\s+(\d+)', 4) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_alw_split_cond.pl b/test_regress/t/t_alw_split_cond.pl deleted file mode 100755 index 552bd97db..000000000 --- a/test_regress/t/t_alw_split_cond.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_alw_split_cond.py b/test_regress/t/t_alw_split_cond.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_alw_split_cond.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_alw_split_rst.pl b/test_regress/t/t_alw_split_rst.pl deleted file mode 100755 index 19a8ccb53..000000000 --- a/test_regress/t/t_alw_split_rst.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--stats", - $Self->wno_unopthreads_for_few_cores()] - ); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, Split always\s+(\d+)/, 12); -} - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_alw_split_rst.py b/test_regress/t/t_alw_split_rst.py new file mode 100755 index 000000000..f801e0883 --- /dev/null +++ b/test_regress/t/t_alw_split_rst.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats", test.wno_unopthreads_for_few_cores]) + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, Split always\s+(\d+)', 12) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_alw_splitord.pl b/test_regress/t/t_alw_splitord.pl deleted file mode 100755 index 89d592cbf..000000000 --- a/test_regress/t/t_alw_splitord.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, Split always\s+(\d+)/, 5); -} - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_alw_splitord.py b/test_regress/t/t_alw_splitord.py new file mode 100755 index 000000000..0324c5dd2 --- /dev/null +++ b/test_regress/t/t_alw_splitord.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats"]) + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, Split always\s+(\d+)', 5) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_array_backw_index_bad.pl b/test_regress/t/t_array_backw_index_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_array_backw_index_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_array_backw_index_bad.py b/test_regress/t/t_array_backw_index_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_array_backw_index_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_array_compare.pl b/test_regress/t/t_array_compare.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_array_compare.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_array_compare.py b/test_regress/t/t_array_compare.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_array_compare.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_array_in_struct.pl b/test_regress/t/t_array_in_struct.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_array_in_struct.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_array_in_struct.py b/test_regress/t/t_array_in_struct.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_array_in_struct.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_array_index_increment.pl b/test_regress/t/t_array_index_increment.pl deleted file mode 100755 index 3a732a7dc..000000000 --- a/test_regress/t/t_array_index_increment.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_array_index_increment.py b/test_regress/t/t_array_index_increment.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_array_index_increment.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_array_list_bad.pl b/test_regress/t/t_array_list_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_array_list_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_array_list_bad.py b/test_regress/t/t_array_list_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_array_list_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_array_mda.pl b/test_regress/t/t_array_mda.pl deleted file mode 100755 index 56363dab6..000000000 --- a/test_regress/t/t_array_mda.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_array_mda.py b/test_regress/t/t_array_mda.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_array_mda.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_array_method.pl b/test_regress/t/t_array_method.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_array_method.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_array_method.py b/test_regress/t/t_array_method.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_array_method.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_array_method_bad.pl b/test_regress/t/t_array_method_bad.pl deleted file mode 100755 index c65314f7b..000000000 --- a/test_regress/t/t_array_method_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_array_method_bad.py b/test_regress/t/t_array_method_bad.py new file mode 100755 index 000000000..efe8cc01c --- /dev/null +++ b/test_regress/t/t_array_method_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_array_method_map.pl b/test_regress/t/t_array_method_map.pl deleted file mode 100755 index 7d0a36d0d..000000000 --- a/test_regress/t/t_array_method_map.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -execute( - ) if !$Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_array_method_map.py b/test_regress/t/t_array_method_map.py new file mode 100755 index 000000000..966dc53da --- /dev/null +++ b/test_regress/t/t_array_method_map.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) + +if not test.vlt_all: + test.execute() + +test.passes() diff --git a/test_regress/t/t_array_method_unsup.pl b/test_regress/t/t_array_method_unsup.pl deleted file mode 100755 index 7d0a36d0d..000000000 --- a/test_regress/t/t_array_method_unsup.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -execute( - ) if !$Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_array_method_unsup.py b/test_regress/t/t_array_method_unsup.py new file mode 100755 index 000000000..966dc53da --- /dev/null +++ b/test_regress/t/t_array_method_unsup.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) + +if not test.vlt_all: + test.execute() + +test.passes() diff --git a/test_regress/t/t_array_packed_endian.pl b/test_regress/t/t_array_packed_endian.pl deleted file mode 100755 index 56363dab6..000000000 --- a/test_regress/t/t_array_packed_endian.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_array_packed_endian.py b/test_regress/t/t_array_packed_endian.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_array_packed_endian.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_array_packed_sysfunct.pl b/test_regress/t/t_array_packed_sysfunct.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_array_packed_sysfunct.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_array_packed_sysfunct.py b/test_regress/t/t_array_packed_sysfunct.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_array_packed_sysfunct.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_array_packed_write_read.pl b/test_regress/t/t_array_packed_write_read.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_array_packed_write_read.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_array_packed_write_read.py b/test_regress/t/t_array_packed_write_read.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_array_packed_write_read.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_array_pattern_2d.pl b/test_regress/t/t_array_pattern_2d.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_array_pattern_2d.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_array_pattern_2d.py b/test_regress/t/t_array_pattern_2d.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_array_pattern_2d.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_array_pattern_bad.pl b/test_regress/t/t_array_pattern_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_array_pattern_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_array_pattern_bad.py b/test_regress/t/t_array_pattern_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_array_pattern_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_array_pattern_bad2.pl b/test_regress/t/t_array_pattern_bad2.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_array_pattern_bad2.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_array_pattern_bad2.py b/test_regress/t/t_array_pattern_bad2.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_array_pattern_bad2.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_array_pattern_bad3.pl b/test_regress/t/t_array_pattern_bad3.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_array_pattern_bad3.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_array_pattern_bad3.py b/test_regress/t/t_array_pattern_bad3.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_array_pattern_bad3.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_array_pattern_packed.pl b/test_regress/t/t_array_pattern_packed.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_array_pattern_packed.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_array_pattern_packed.py b/test_regress/t/t_array_pattern_packed.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_array_pattern_packed.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_array_pattern_unpacked.pl b/test_regress/t/t_array_pattern_unpacked.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_array_pattern_unpacked.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_array_pattern_unpacked.py b/test_regress/t/t_array_pattern_unpacked.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_array_pattern_unpacked.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_array_query.pl b/test_regress/t/t_array_query.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_array_query.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_array_query.py b/test_regress/t/t_array_query.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_array_query.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_array_query_with.pl b/test_regress/t/t_array_query_with.pl deleted file mode 100755 index f96aad9b7..000000000 --- a/test_regress/t/t_array_query_with.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--assert'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_array_query_with.py b/test_regress/t/t_array_query_with.py new file mode 100755 index 000000000..2c4ffdce2 --- /dev/null +++ b/test_regress/t/t_array_query_with.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--assert']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_array_rev.pl b/test_regress/t/t_array_rev.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_array_rev.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_array_rev.py b/test_regress/t/t_array_rev.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_array_rev.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_array_type_methods.pl b/test_regress/t/t_array_type_methods.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_array_type_methods.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_array_type_methods.py b/test_regress/t/t_array_type_methods.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_array_type_methods.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_array_unpacked_public.pl b/test_regress/t/t_array_unpacked_public.pl deleted file mode 100755 index 8ba96647b..000000000 --- a/test_regress/t/t_array_unpacked_public.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--public-flat-rw"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_array_unpacked_public.py b/test_regress/t/t_array_unpacked_public.py new file mode 100755 index 000000000..31843bd7b --- /dev/null +++ b/test_regress/t/t_array_unpacked_public.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--public-flat-rw"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_arraysel_wide.pl b/test_regress/t/t_arraysel_wide.pl deleted file mode 100755 index 552bd97db..000000000 --- a/test_regress/t/t_arraysel_wide.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_arraysel_wide.py b/test_regress/t/t_arraysel_wide.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_arraysel_wide.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_assert_basic.pl b/test_regress/t/t_assert_basic.pl deleted file mode 100755 index 4a1de974b..000000000 --- a/test_regress/t/t_assert_basic.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--assert'], - nc_flags2 => ['+assert'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_basic.py b/test_regress/t/t_assert_basic.py new file mode 100755 index 000000000..d97aaff01 --- /dev/null +++ b/test_regress/t/t_assert_basic.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--assert'], nc_flags2=['+assert']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assert_basic_cover.pl b/test_regress/t/t_assert_basic_cover.pl deleted file mode 100755 index df070b2ca..000000000 --- a/test_regress/t/t_assert_basic_cover.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_assert_basic.v"); - -compile( - verilator_flags2 => ['--assert --cc --coverage-user'], - ); - -execute( - ); - -#Needs work -print "-Info: NOT checking for coverage\n"; -#file_grep($Self->{coverage_filename}, qr/t=>'psl_cover',o=>'cover',c=>2\);/); -#file_grep($Self->{coverage_filename}, qr/DefaultClock.*,c=>1\);/); -#file_grep($Self->{coverage_filename}, qr/ToggleLogIf.*,c=>9\);/); - -ok(1); -1; diff --git a/test_regress/t/t_assert_basic_cover.py b/test_regress/t/t_assert_basic_cover.py new file mode 100755 index 000000000..045f31a9c --- /dev/null +++ b/test_regress/t/t_assert_basic_cover.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_assert_basic.v" + +test.compile(verilator_flags2=['--assert --cc --coverage-user']) + +test.execute() + +#Needs work +print("-Info: NOT checking for coverage") +#test.file_grep(test.coverage_filename, r't=>'psl_cover',o=>'cover',c=>2\);') +#test.file_grep(test.coverage_filename, r'DefaultClock.*,c=>1\);') +#test.file_grep(test.coverage_filename, r'ToggleLogIf.*,c=>9\);') + +test.passes() diff --git a/test_regress/t/t_assert_basic_fail.pl b/test_regress/t/t_assert_basic_fail.pl deleted file mode 100755 index 6e51b415d..000000000 --- a/test_regress/t/t_assert_basic_fail.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_assert_basic.v"); - -compile( - v_flags2 => ['+define+FAILING_ASSERTIONS', - ($Self->{vlt_all} ? '--assert' - : ($Self->{nc} ? '+assert' : ''))], - fails => $Self->{nc}, - ); - -execute( - fails => $Self->{vlt_all}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_basic_fail.py b/test_regress/t/t_assert_basic_fail.py new file mode 100755 index 000000000..08961e17e --- /dev/null +++ b/test_regress/t/t_assert_basic_fail.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_assert_basic.v" + +test.compile(v_flags2=[ + '+define+FAILING_ASSERTIONS', ('--assert' if test.vlt_all else ('+assert' if test.nc else '')) +], + fails=test.nc) + +test.execute(fails=test.vlt_all) + +test.passes() diff --git a/test_regress/t/t_assert_basic_off.pl b/test_regress/t/t_assert_basic_off.pl deleted file mode 100755 index 4689e5db2..000000000 --- a/test_regress/t/t_assert_basic_off.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_assert_basic.v"); - -compile( - v_flags2 => [], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_basic_off.py b/test_regress/t/t_assert_basic_off.py new file mode 100755 index 000000000..cd9e8e0c5 --- /dev/null +++ b/test_regress/t/t_assert_basic_off.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_assert_basic.v" + +test.compile(v_flags2=[]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assert_casez.pl b/test_regress/t/t_assert_casez.pl deleted file mode 100755 index c4cff0d55..000000000 --- a/test_regress/t/t_assert_casez.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--assert'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_casez.py b/test_regress/t/t_assert_casez.py new file mode 100755 index 000000000..2c4ffdce2 --- /dev/null +++ b/test_regress/t/t_assert_casez.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--assert']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assert_clock_event_unsup.pl b/test_regress/t/t_assert_clock_event_unsup.pl deleted file mode 100755 index 1e3627720..000000000 --- a/test_regress/t/t_assert_clock_event_unsup.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - expect_filename => $Self->{golden_filename}, - verilator_flags2 => ['--assert'], - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_clock_event_unsup.py b/test_regress/t/t_assert_clock_event_unsup.py new file mode 100755 index 000000000..7e5bcdfe5 --- /dev/null +++ b/test_regress/t/t_assert_clock_event_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert'], fails=True) + +test.passes() diff --git a/test_regress/t/t_assert_comp.pl b/test_regress/t/t_assert_comp.pl deleted file mode 100755 index 4a1de974b..000000000 --- a/test_regress/t/t_assert_comp.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--assert'], - nc_flags2 => ['+assert'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_comp.py b/test_regress/t/t_assert_comp.py new file mode 100755 index 000000000..d97aaff01 --- /dev/null +++ b/test_regress/t/t_assert_comp.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--assert'], nc_flags2=['+assert']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assert_comp_bad.pl b/test_regress/t/t_assert_comp_bad.pl deleted file mode 100755 index 3bc6896ac..000000000 --- a/test_regress/t/t_assert_comp_bad.pl +++ /dev/null @@ -1,68 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -my $root = ".."; - -if (!-r "$root/.git") { - skip("Not in a git repository"); -} else { - compile( - verilator_flags2 => ['--assert'], - nc_flags2 => ['+assert'], - vcs_flags2 => ['-assert svaext'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - - extract( - in => $Self->{top_filename}, - out => "../docs/gen/ex_USERWARN_faulty.rst", - regexp => qr/\$warn.*User/); - - extract( - in => $Self->{top_filename}, - out => "../docs/gen/ex_USERERROR_faulty.rst", - regexp => qr/\$error.*User/); - - extract( - in => $Self->{top_filename}, - out => "../docs/gen/ex_USERINFO_faulty.rst", - regexp => qr/\$info.*User/); - - extract( - in => $Self->{top_filename}, - out => "../docs/gen/ex_USERFATAL_faulty.rst", - regexp => qr/\$fatal.*User/); - - extract( - in => $Self->{golden_filename}, - out => "../docs/gen/ex_USERWARN_msg.rst", - regexp => qr/USERWARN:.* User/); - - extract( - in => $Self->{golden_filename}, - out => "../docs/gen/ex_USERERROR_msg.rst", - regexp => qr/USERERROR:.* User/); - - extract( - in => $Self->{golden_filename}, - out => "../docs/gen/ex_USERINFO_msg.rst", - regexp => qr/-Info:.* User/); - - extract( - in => $Self->{golden_filename}, - out => "../docs/gen/ex_USERFATAL_msg.rst", - regexp => qr/USERFATAL:.* User/); -} - -ok(1); -1; diff --git a/test_regress/t/t_assert_comp_bad.py b/test_regress/t/t_assert_comp_bad.py new file mode 100755 index 000000000..12cec4f93 --- /dev/null +++ b/test_regress/t/t_assert_comp_bad.py @@ -0,0 +1,57 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +root = ".." + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +test.compile(verilator_flags2=['--assert'], + nc_flags2=['+assert'], + vcs_flags2=['-assert svaext'], + fails=True, + expect_filename=test.golden_filename) + +test.extract(in_filename=test.top_filename, + out_filename="../docs/gen/ex_USERWARN_faulty.rst", + regexp=r'\$warn.*User') + +test.extract(in_filename=test.top_filename, + out_filename="../docs/gen/ex_USERERROR_faulty.rst", + regexp=r'\$error.*User') + +test.extract(in_filename=test.top_filename, + out_filename="../docs/gen/ex_USERINFO_faulty.rst", + regexp=r'\$info.*User') + +test.extract(in_filename=test.top_filename, + out_filename="../docs/gen/ex_USERFATAL_faulty.rst", + regexp=r'\$fatal.*User') + +test.extract(in_filename=test.golden_filename, + out_filename="../docs/gen/ex_USERWARN_msg.rst", + regexp=r'USERWARN:.* User') + +test.extract(in_filename=test.golden_filename, + out_filename="../docs/gen/ex_USERERROR_msg.rst", + regexp=r'USERERROR:.* User') + +test.extract(in_filename=test.golden_filename, + out_filename="../docs/gen/ex_USERINFO_msg.rst", + regexp=r'-Info:.* User') + +test.extract(in_filename=test.golden_filename, + out_filename="../docs/gen/ex_USERFATAL_msg.rst", + regexp=r'USERFATAL:.* User') + +test.passes() diff --git a/test_regress/t/t_assert_cover.pl b/test_regress/t/t_assert_cover.pl deleted file mode 100755 index c7ab619ce..000000000 --- a/test_regress/t/t_assert_cover.pl +++ /dev/null @@ -1,47 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_assert_cover.v"); - -compile( - verilator_flags2 => ['--assert --cc --coverage-user'], - nc_flags2 => ["+nccovoverwrite +nccoverage+all +nccovtest+$Self->{name}"] - ); - -execute( - ); - -if ($Self->{nc}) { - my $name = $Self->{name}; - my $cf = "$Self->{obj_dir}/${name}__nccover.cf"; - { - my $fh = IO::File->new(">$cf") or die "%Error: $! writing $cf,"; - $fh->printf("report_summary -module *\n"); - $fh->printf("report_detail -both -instance *\n"); - $fh->printf("report_html -both -instance * > $Self->{obj_dir}/${name}__nccover.html\n"); - $fh->close; - } - run(logfile => "$Self->{obj_dir}/${name}__nccover.log", - tee => 0, - cmd => [($ENV{VERILATOR_ICCR} || 'iccr'), - "-test ${name} ${cf}"]); -} - -file_grep($Self->{run_log_filename}, qr/COVER: Cyc==4/); -file_grep($Self->{run_log_filename}, qr/COVER: Cyc==5/); -file_grep($Self->{run_log_filename}, qr/COVER: Cyc==6/); - -# Allow old SystemC::Coverage format dump, or new binary dump -file_grep($Self->{coverage_filename}, qr/(cyc_eq_5.*,c=>[^0]|cyc_eq_5.* [1-9][0-9]*\n)/); - -ok(1); -1; diff --git a/test_regress/t/t_assert_cover.py b/test_regress/t/t_assert_cover.py new file mode 100755 index 000000000..4c62fcc22 --- /dev/null +++ b/test_regress/t/t_assert_cover.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_assert_cover.v" + +test.compile(verilator_flags2=['--assert --cc --coverage-user'], + nc_flags2=["+nccovoverwrite +nccoverage+all +nccovtest+" + test.name]) + +test.execute() + +if test.nc: + cf = test.obj_dir + "/" + test.name + "__nccover.cf" + + with open(cf, 'w', encoding="utf8") as fh: + fh.write("report_summary -module *\n") + fh.write("report_detail -both -instance *\n") + fh.write("report_html -both -instance * > " + test.obj_dir + "/" + test.name + + "__nccover.html\n") + + test.run(logfile=test.obj_dir + "/" + test.name + "__nccover.log", + tee=False, + cmd=[test.getenv_def("VERILATOR_ICCR", 'iccr'), "-test", test.name, cf]) + +test.file_grep(test.run_log_filename, r'COVER: Cyc==4') +test.file_grep(test.run_log_filename, r'COVER: Cyc==5') +test.file_grep(test.run_log_filename, r'COVER: Cyc==6') + +# Allow old SystemC::Coverage format dump, or new binary dump +test.file_grep(test.coverage_filename, r'(cyc_eq_5.*,c=>[^0]|cyc_eq_5.* [1-9][0-9]*\n)') + +test.passes() diff --git a/test_regress/t/t_assert_cover_off.pl b/test_regress/t/t_assert_cover_off.pl deleted file mode 100755 index 99d3e7613..000000000 --- a/test_regress/t/t_assert_cover_off.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_assert_cover.v"); - -compile( - v_flags2 => [], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_cover_off.py b/test_regress/t/t_assert_cover_off.py new file mode 100755 index 000000000..356558121 --- /dev/null +++ b/test_regress/t/t_assert_cover_off.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_assert_cover.v" + +test.compile(v_flags2=[]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assert_ctl_arg.pl b/test_regress/t/t_assert_ctl_arg.pl deleted file mode 100755 index c669fed5e..000000000 --- a/test_regress/t/t_assert_ctl_arg.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--assert", "--timing", "--coverage-user", "--exe $Self->{t_dir}/$Self->{name}.cpp"], - nc_flags2 => ["+nccovoverwrite", "+nccoverage+all", "+nccovtest+$Self->{name}"], - ); - -execute( - all_run_flags => ["+verilator+error+limit+100"], - expect_filename => $Self->{golden_filename}, - ); - -files_identical($Self->{coverage_filename}, "$Self->{t_dir}/t_assert_ctl_arg_coverage.out"); - -ok(1); -1; diff --git a/test_regress/t/t_assert_ctl_arg.py b/test_regress/t/t_assert_ctl_arg.py new file mode 100755 index 000000000..812f7c3a0 --- /dev/null +++ b/test_regress/t/t_assert_ctl_arg.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile( + make_top_shell=False, + make_main=False, + verilator_flags2=["--assert", "--timing", "--coverage-user", "--exe", test.pli_filename], + nc_flags2=["+nccovoverwrite", "+nccoverage+all", "+nccovtest+" + test.name]) + +test.execute(all_run_flags=["+verilator+error+limit+100"], expect_filename=test.golden_filename) + +test.files_identical(test.coverage_filename, test.t_dir + "/t_assert_ctl_arg_coverage.out") + +test.passes() diff --git a/test_regress/t/t_assert_ctl_arg_noinl.pl b/test_regress/t/t_assert_ctl_arg_noinl.pl deleted file mode 100755 index 32cb9b25f..000000000 --- a/test_regress/t/t_assert_ctl_arg_noinl.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t_assert_ctl_arg.v"); -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => [ - "--assert", "--timing", "--coverage-user", "--exe $Self->{t_dir}/t_assert_ctl_arg.cpp", "-fno-inline" - ], - nc_flags2 => ["+nccovoverwrite", "+nccoverage+all", "+nccovtest+$Self->{name}"], - ); - -execute( - all_run_flags => ["+verilator+error+limit+100"], - expect_filename => "$Self->{t_dir}/t_assert_ctl_arg.out", - ); - -files_identical($Self->{coverage_filename}, "$Self->{t_dir}/t_assert_ctl_arg_coverage.out"); - -ok(1); -1; diff --git a/test_regress/t/t_assert_ctl_arg_noinl.py b/test_regress/t/t_assert_ctl_arg_noinl.py new file mode 100755 index 000000000..b36df045f --- /dev/null +++ b/test_regress/t/t_assert_ctl_arg_noinl.py @@ -0,0 +1,28 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t_assert_ctl_arg.v" + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=[ + "--assert", "--timing", "--coverage-user", "--exe", + test.t_dir + "/t_assert_ctl_arg.cpp", "-fno-inline" + ], + nc_flags2=["+nccovoverwrite", "+nccoverage+all", "+nccovtest+" + test.name]) + +test.execute(all_run_flags=["+verilator+error+limit+100"], + expect_filename=test.t_dir + "/t_assert_ctl_arg.out") + +test.files_identical(test.coverage_filename, test.t_dir + "/t_assert_ctl_arg_coverage.out") + +test.passes() diff --git a/test_regress/t/t_assert_ctl_arg_unsup.pl b/test_regress/t/t_assert_ctl_arg_unsup.pl deleted file mode 100755 index 147dcdcd9..000000000 --- a/test_regress/t/t_assert_ctl_arg_unsup.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_ctl_arg_unsup.py b/test_regress/t/t_assert_ctl_arg_unsup.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_assert_ctl_arg_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_assert_ctl_concurrent.pl b/test_regress/t/t_assert_ctl_concurrent.pl deleted file mode 100755 index 0c233b39d..000000000 --- a/test_regress/t/t_assert_ctl_concurrent.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["--exe --main --timing --assert"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_ctl_concurrent.py b/test_regress/t/t_assert_ctl_concurrent.py new file mode 100755 index 000000000..bf8998d5c --- /dev/null +++ b/test_regress/t/t_assert_ctl_concurrent.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--exe --main --timing --assert"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assert_ctl_concurrent_noinl.pl b/test_regress/t/t_assert_ctl_concurrent_noinl.pl deleted file mode 100755 index a29b835a4..000000000 --- a/test_regress/t/t_assert_ctl_concurrent_noinl.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -top_filename("t_assert_ctl_concurrent.v"); -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["--exe --main --timing --assert --fno-inline"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_ctl_concurrent_noinl.py b/test_regress/t/t_assert_ctl_concurrent_noinl.py new file mode 100755 index 000000000..d96a4a589 --- /dev/null +++ b/test_regress/t/t_assert_ctl_concurrent_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t_assert_ctl_concurrent.v" + +test.compile(verilator_flags2=["--exe --main --timing --assert --fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assert_ctl_immediate.pl b/test_regress/t/t_assert_ctl_immediate.pl deleted file mode 100755 index 55081d509..000000000 --- a/test_regress/t/t_assert_ctl_immediate.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ['--assert', '--timing'], - ); - -execute( - all_run_flags => ["+verilator+error+limit+100"], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_ctl_immediate.py b/test_regress/t/t_assert_ctl_immediate.py new file mode 100755 index 000000000..cbd7dd9cc --- /dev/null +++ b/test_regress/t/t_assert_ctl_immediate.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['--assert', '--timing']) + +test.execute(all_run_flags=["+verilator+error+limit+100"], expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_assert_ctl_immediate_noinl.pl b/test_regress/t/t_assert_ctl_immediate_noinl.pl deleted file mode 100755 index 925795a67..000000000 --- a/test_regress/t/t_assert_ctl_immediate_noinl.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -top_filename("t_assert_ctl_immediate.v"); -golden_filename("t/t_assert_ctl_immediate.out"); -scenarios(vlt => 1); - -compile( - verilator_flags2 => ['--assert --timing --fno-inline'], - ); - -execute( - all_run_flags => ["+verilator+error+limit+100"], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_ctl_immediate_noinl.py b/test_regress/t/t_assert_ctl_immediate_noinl.py new file mode 100755 index 000000000..be07788c3 --- /dev/null +++ b/test_regress/t/t_assert_ctl_immediate_noinl.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t_assert_ctl_immediate.v" +test.golden_filename = "t/t_assert_ctl_immediate.out" + +test.compile(verilator_flags2=['--assert --timing --fno-inline']) + +test.execute(all_run_flags=["+verilator+error+limit+100"], expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_assert_ctl_unsup.pl b/test_regress/t/t_assert_ctl_unsup.pl deleted file mode 100755 index b3b9ca877..000000000 --- a/test_regress/t/t_assert_ctl_unsup.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ['--assert'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_ctl_unsup.py b/test_regress/t/t_assert_ctl_unsup.py new file mode 100755 index 000000000..0275f2df9 --- /dev/null +++ b/test_regress/t/t_assert_ctl_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=['--assert'], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_assert_disable_bad.pl b/test_regress/t/t_assert_disable_bad.pl deleted file mode 100755 index 1f68597d8..000000000 --- a/test_regress/t/t_assert_disable_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - expect_filename => $Self->{golden_filename}, - verilator_flags2 => ['--assert'], - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_disable_bad.py b/test_regress/t/t_assert_disable_bad.py new file mode 100755 index 000000000..7e5bcdfe5 --- /dev/null +++ b/test_regress/t/t_assert_disable_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert'], fails=True) + +test.passes() diff --git a/test_regress/t/t_assert_disable_iff.pl b/test_regress/t/t_assert_disable_iff.pl deleted file mode 100755 index cb17e1fb7..000000000 --- a/test_regress/t/t_assert_disable_iff.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--assert --cc --coverage-user'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_disable_iff.py b/test_regress/t/t_assert_disable_iff.py new file mode 100755 index 000000000..b17623e03 --- /dev/null +++ b/test_regress/t/t_assert_disable_iff.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--assert --cc --coverage-user']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assert_disabled.pl b/test_regress/t/t_assert_disabled.pl deleted file mode 100755 index 2e1aeae86..000000000 --- a/test_regress/t/t_assert_disabled.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_assert_on.v"); - -compile(); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_disabled.py b/test_regress/t/t_assert_disabled.py new file mode 100755 index 000000000..b45b81326 --- /dev/null +++ b/test_regress/t/t_assert_disabled.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_assert_on.v" + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assert_dup_bad.pl b/test_regress/t/t_assert_dup_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_assert_dup_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_dup_bad.py b/test_regress/t/t_assert_dup_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_assert_dup_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_assert_elab.pl b/test_regress/t/t_assert_elab.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_assert_elab.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_elab.py b/test_regress/t/t_assert_elab.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_assert_elab.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assert_elab_bad.pl b/test_regress/t/t_assert_elab_bad.pl deleted file mode 100755 index 586badd6b..000000000 --- a/test_regress/t/t_assert_elab_bad.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_assert_elab.v"); -unlink("$Self->{obj_dir}/t_assert_elab_bad.log"); - - -compile( - v_flags2 => ['+define+FAILING_ASSERTIONS', - $Self->{vlt_all} ? '--assert' : ($Self->{nc} ? '+assert':'')], - fails => 1, -); - -execute( - fails => $Self->{vlt_all}, -); - -file_grep("$Self->{obj_dir}/vlt_compile.log", -qr/%Warning-USERFATAL: "Parameter 5 is invalid...string and constant both work"/); - -ok(1); -1; diff --git a/test_regress/t/t_assert_elab_bad.py b/test_regress/t/t_assert_elab_bad.py new file mode 100755 index 000000000..ec8e7f2c3 --- /dev/null +++ b/test_regress/t/t_assert_elab_bad.py @@ -0,0 +1,27 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_assert_elab.v" + +test.unlink_ok(test.obj_dir + "/t_assert_elab_bad.log") + +test.compile(v_flags2=[ + '+define+FAILING_ASSERTIONS', ('--assert' if test.vlt_all else ('+assert' if test.nc else '')) +], + fails=True) + +test.execute(fails=test.vlt_all) + +test.file_grep(test.obj_dir + "/vlt_compile.log", + r'%Warning-USERFATAL: "Parameter 5 is invalid...string and constant both work"') + +test.passes() diff --git a/test_regress/t/t_assert_enabled_bad.pl b/test_regress/t/t_assert_enabled_bad.pl deleted file mode 100755 index 689a3b7e2..000000000 --- a/test_regress/t/t_assert_enabled_bad.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_assert_on.v"); - -compile( - verilator_flags2 => ['--assert'], - nc_flags2 => ['+assert'], - ); - -execute( - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_enabled_bad.py b/test_regress/t/t_assert_enabled_bad.py new file mode 100755 index 000000000..aa290b7d0 --- /dev/null +++ b/test_regress/t/t_assert_enabled_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_assert_on.v" + +test.compile(verilator_flags2=['--assert'], nc_flags2=['+assert']) + +test.execute(fails=True) + +test.passes() diff --git a/test_regress/t/t_assert_enabled_off.pl b/test_regress/t/t_assert_enabled_off.pl deleted file mode 100755 index 13894bf05..000000000 --- a/test_regress/t/t_assert_enabled_off.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_assert_on.v"); - -compile( - verilator_flags2 => ["--assert"], - ); - -execute( - all_run_flags => ["+verilator+noassert"], -); - -ok(1); -1; diff --git a/test_regress/t/t_assert_enabled_off.py b/test_regress/t/t_assert_enabled_off.py new file mode 100755 index 000000000..f2cce0678 --- /dev/null +++ b/test_regress/t/t_assert_enabled_off.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_assert_on.v" + +test.compile(verilator_flags2=["--assert"]) + +test.execute(all_run_flags=["+verilator+noassert"]) + +test.passes() diff --git a/test_regress/t/t_assert_enabled_on_bad.pl b/test_regress/t/t_assert_enabled_on_bad.pl deleted file mode 100755 index 6e1aa5190..000000000 --- a/test_regress/t/t_assert_enabled_on_bad.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_assert_on.v"); - -compile( - verilator_flags2 => ["--assert"], - ); - -execute( - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_enabled_on_bad.py b/test_regress/t/t_assert_enabled_on_bad.py new file mode 100755 index 000000000..5789d18b7 --- /dev/null +++ b/test_regress/t/t_assert_enabled_on_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_assert_on.v" + +test.compile(verilator_flags2=["--assert"]) + +test.execute(fails=True) + +test.passes() diff --git a/test_regress/t/t_assert_iff.pl b/test_regress/t/t_assert_iff.pl deleted file mode 100755 index cb17e1fb7..000000000 --- a/test_regress/t/t_assert_iff.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--assert --cc --coverage-user'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_iff.py b/test_regress/t/t_assert_iff.py new file mode 100755 index 000000000..b17623e03 --- /dev/null +++ b/test_regress/t/t_assert_iff.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--assert --cc --coverage-user']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assert_iff_bad1.pl b/test_regress/t/t_assert_iff_bad1.pl deleted file mode 100755 index 3959b8306..000000000 --- a/test_regress/t/t_assert_iff_bad1.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename('t_assert_iff.v'); - -compile( - verilator_flags2 => ['--assert --cc --coverage-user -DFAIL1'], - ); - -execute( - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_iff_bad1.py b/test_regress/t/t_assert_iff_bad1.py new file mode 100755 index 000000000..0855ac24f --- /dev/null +++ b/test_regress/t/t_assert_iff_bad1.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = 't_assert_iff.v' + +test.compile(verilator_flags2=['--assert --cc --coverage-user -DFAIL1']) + +test.execute(fails=True) + +test.passes() diff --git a/test_regress/t/t_assert_iff_bad2.pl b/test_regress/t/t_assert_iff_bad2.pl deleted file mode 100755 index f71edd058..000000000 --- a/test_regress/t/t_assert_iff_bad2.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename('t_assert_iff.v'); - -compile( - verilator_flags2 => ['--assert --cc --coverage-user -DFAIL2'], - ); - -execute( - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_iff_bad2.py b/test_regress/t/t_assert_iff_bad2.py new file mode 100755 index 000000000..6d25b802f --- /dev/null +++ b/test_regress/t/t_assert_iff_bad2.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = 't_assert_iff.v' + +test.compile(verilator_flags2=['--assert --cc --coverage-user -DFAIL2']) + +test.execute(fails=True) + +test.passes() diff --git a/test_regress/t/t_assert_iff_clk_unsup.pl b/test_regress/t/t_assert_iff_clk_unsup.pl deleted file mode 100755 index 1e3627720..000000000 --- a/test_regress/t/t_assert_iff_clk_unsup.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - expect_filename => $Self->{golden_filename}, - verilator_flags2 => ['--assert'], - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_iff_clk_unsup.py b/test_regress/t/t_assert_iff_clk_unsup.py new file mode 100755 index 000000000..7e5bcdfe5 --- /dev/null +++ b/test_regress/t/t_assert_iff_clk_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert'], fails=True) + +test.passes() diff --git a/test_regress/t/t_assert_imm_nz_bad.pl b/test_regress/t/t_assert_imm_nz_bad.pl deleted file mode 100755 index 9841a8c0f..000000000 --- a/test_regress/t/t_assert_imm_nz_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - expect_filename => $Self->{golden_filename}, - verilator_flags2 => ['--assert'], - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_imm_nz_bad.py b/test_regress/t/t_assert_imm_nz_bad.py new file mode 100755 index 000000000..7e5bcdfe5 --- /dev/null +++ b/test_regress/t/t_assert_imm_nz_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert'], fails=True) + +test.passes() diff --git a/test_regress/t/t_assert_implication.pl b/test_regress/t/t_assert_implication.pl deleted file mode 100755 index 92b0eed7a..000000000 --- a/test_regress/t/t_assert_implication.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--assert --cc'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_implication.py b/test_regress/t/t_assert_implication.py new file mode 100755 index 000000000..724621ce6 --- /dev/null +++ b/test_regress/t/t_assert_implication.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--assert --cc']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assert_implication_bad.pl b/test_regress/t/t_assert_implication_bad.pl deleted file mode 100755 index 9b934c0ec..000000000 --- a/test_regress/t/t_assert_implication_bad.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_assert_implication.v"); - -compile( - v_flags2 => ['+define+FAIL_ASSERT_1'], - verilator_flags2 => ['--assert --cc'], - ); - -execute( - ); - -# We expect to get a message when this assert fires: -file_grep($Self->{run_log_filename}, qr/wrong implication/); - -ok(1); -1; diff --git a/test_regress/t/t_assert_implication_bad.py b/test_regress/t/t_assert_implication_bad.py new file mode 100755 index 000000000..873345737 --- /dev/null +++ b/test_regress/t/t_assert_implication_bad.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_assert_implication.v" + +test.compile(v_flags2=['+define+FAIL_ASSERT_1'], verilator_flags2=['--assert --cc']) + +test.execute() + +# We expect to get a message when this assert fires: +test.file_grep(test.run_log_filename, r'wrong implication') + +test.passes() diff --git a/test_regress/t/t_assert_inside_cond.pl b/test_regress/t/t_assert_inside_cond.pl deleted file mode 100755 index 1b42241ea..000000000 --- a/test_regress/t/t_assert_inside_cond.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["-x-assign 0 --assert +define+T_ASSERT_INSIDE_COND"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_inside_cond.py b/test_regress/t/t_assert_inside_cond.py new file mode 100755 index 000000000..1a2dfabae --- /dev/null +++ b/test_regress/t/t_assert_inside_cond.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["-x-assign 0 --assert +define+T_ASSERT_INSIDE_COND"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assert_inside_cond_bad.pl b/test_regress/t/t_assert_inside_cond_bad.pl deleted file mode 100755 index 59d4ea08c..000000000 --- a/test_regress/t/t_assert_inside_cond_bad.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_assert_inside_cond.v"); - -compile( - verilator_flags2 => ["-x-assign 0 --assert +define+T_ASSERT_INSIDE_COND_BAD"], - ); - -execute( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_inside_cond_bad.py b/test_regress/t/t_assert_inside_cond_bad.py new file mode 100755 index 000000000..8f955b403 --- /dev/null +++ b/test_regress/t/t_assert_inside_cond_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_assert_inside_cond.v" + +test.compile(verilator_flags2=["-x-assign 0 --assert +define+T_ASSERT_INSIDE_COND_BAD"]) + +test.execute(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_assert_named_property.pl b/test_regress/t/t_assert_named_property.pl deleted file mode 100755 index f96aad9b7..000000000 --- a/test_regress/t/t_assert_named_property.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--assert'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_named_property.py b/test_regress/t/t_assert_named_property.py new file mode 100755 index 000000000..2c4ffdce2 --- /dev/null +++ b/test_regress/t/t_assert_named_property.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--assert']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assert_past.pl b/test_regress/t/t_assert_past.pl deleted file mode 100755 index f96aad9b7..000000000 --- a/test_regress/t/t_assert_past.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--assert'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_past.py b/test_regress/t/t_assert_past.py new file mode 100755 index 000000000..2c4ffdce2 --- /dev/null +++ b/test_regress/t/t_assert_past.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--assert']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assert_procedural_clk_bad.pl b/test_regress/t/t_assert_procedural_clk_bad.pl deleted file mode 100755 index 1e3627720..000000000 --- a/test_regress/t/t_assert_procedural_clk_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - expect_filename => $Self->{golden_filename}, - verilator_flags2 => ['--assert'], - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_procedural_clk_bad.py b/test_regress/t/t_assert_procedural_clk_bad.py new file mode 100755 index 000000000..7e5bcdfe5 --- /dev/null +++ b/test_regress/t/t_assert_procedural_clk_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert'], fails=True) + +test.passes() diff --git a/test_regress/t/t_assert_property.pl b/test_regress/t/t_assert_property.pl deleted file mode 100755 index 92b0eed7a..000000000 --- a/test_regress/t/t_assert_property.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--assert --cc'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_property.py b/test_regress/t/t_assert_property.py new file mode 100755 index 000000000..724621ce6 --- /dev/null +++ b/test_regress/t/t_assert_property.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--assert --cc']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assert_property_fail_1.pl b/test_regress/t/t_assert_property_fail_1.pl deleted file mode 100755 index e3ba3d21e..000000000 --- a/test_regress/t/t_assert_property_fail_1.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_assert_property.v"); - -compile( - v_flags2 => ['+define+FAIL_ASSERT_1'], - verilator_flags2 => ['--assert --cc'], - ); - -execute( - ); - -# We expect to get a message when this assert fires: -file_grep($Self->{run_log_filename}, qr/cyc != 3/); - -ok(1); -1; diff --git a/test_regress/t/t_assert_property_fail_1.py b/test_regress/t/t_assert_property_fail_1.py new file mode 100755 index 000000000..64539f556 --- /dev/null +++ b/test_regress/t/t_assert_property_fail_1.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_assert_property.v" + +test.compile(v_flags2=['+define+FAIL_ASSERT_1'], verilator_flags2=['--assert --cc']) + +test.execute() + +# We expect to get a message when this assert fires: +test.file_grep(test.run_log_filename, r'cyc != 3') + +test.passes() diff --git a/test_regress/t/t_assert_property_fail_2_bad.pl b/test_regress/t/t_assert_property_fail_2_bad.pl deleted file mode 100755 index f12587b25..000000000 --- a/test_regress/t/t_assert_property_fail_2_bad.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_assert_property.v"); - -compile( - v_flags2 => ['+define+FAIL_ASSERT_2'], - verilator_flags2 => ['--assert --cc'], - ); - -execute( - fails => 1 - ); - -file_grep($Self->{run_log_filename}, qr/'assert' failed/); - -ok(1); -1; diff --git a/test_regress/t/t_assert_property_fail_2_bad.py b/test_regress/t/t_assert_property_fail_2_bad.py new file mode 100755 index 000000000..f89198139 --- /dev/null +++ b/test_regress/t/t_assert_property_fail_2_bad.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_assert_property.v" + +test.compile(v_flags2=['+define+FAIL_ASSERT_2'], verilator_flags2=['--assert --cc']) + +test.execute(fails=True) + +test.file_grep(test.run_log_filename, r"'assert' failed") + +test.passes() diff --git a/test_regress/t/t_assert_property_pexpr_unsup.pl b/test_regress/t/t_assert_property_pexpr_unsup.pl deleted file mode 100755 index fa4fb8b52..000000000 --- a/test_regress/t/t_assert_property_pexpr_unsup.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - expect_filename => $Self->{golden_filename}, - verilator_flags2 => ['--assert --error-limit 1000'], - fails => $Self->{vlt_all}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_property_pexpr_unsup.py b/test_regress/t/t_assert_property_pexpr_unsup.py new file mode 100755 index 000000000..7b40cd490 --- /dev/null +++ b/test_regress/t/t_assert_property_pexpr_unsup.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(expect_filename=test.golden_filename, + verilator_flags2=['--assert --error-limit 1000'], + fails=test.vlt_all) + +test.passes() diff --git a/test_regress/t/t_assert_property_untyped.pl b/test_regress/t/t_assert_property_untyped.pl deleted file mode 100755 index f96aad9b7..000000000 --- a/test_regress/t/t_assert_property_untyped.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--assert'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_property_untyped.py b/test_regress/t/t_assert_property_untyped.py new file mode 100755 index 000000000..2c4ffdce2 --- /dev/null +++ b/test_regress/t/t_assert_property_untyped.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--assert']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assert_property_untyped_unsup.pl b/test_regress/t/t_assert_property_untyped_unsup.pl deleted file mode 100755 index 1e3627720..000000000 --- a/test_regress/t/t_assert_property_untyped_unsup.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - expect_filename => $Self->{golden_filename}, - verilator_flags2 => ['--assert'], - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_property_untyped_unsup.py b/test_regress/t/t_assert_property_untyped_unsup.py new file mode 100755 index 000000000..7e5bcdfe5 --- /dev/null +++ b/test_regress/t/t_assert_property_untyped_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert'], fails=True) + +test.passes() diff --git a/test_regress/t/t_assert_property_var_unsup.pl b/test_regress/t/t_assert_property_var_unsup.pl deleted file mode 100755 index 7284ec30e..000000000 --- a/test_regress/t/t_assert_property_var_unsup.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - expect_filename => $Self->{golden_filename}, - verilator_flags2 => ['--assert --error-limit 1000'], - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_property_var_unsup.py b/test_regress/t/t_assert_property_var_unsup.py new file mode 100755 index 000000000..25f9960b8 --- /dev/null +++ b/test_regress/t/t_assert_property_var_unsup.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(expect_filename=test.golden_filename, + verilator_flags2=['--assert --error-limit 1000'], + fails=True) + +test.passes() diff --git a/test_regress/t/t_assert_question.pl b/test_regress/t/t_assert_question.pl deleted file mode 100755 index c4cff0d55..000000000 --- a/test_regress/t/t_assert_question.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--assert'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_question.py b/test_regress/t/t_assert_question.py new file mode 100755 index 000000000..2c4ffdce2 --- /dev/null +++ b/test_regress/t/t_assert_question.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--assert']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assert_recursive_property_unsup.pl b/test_regress/t/t_assert_recursive_property_unsup.pl deleted file mode 100755 index 8e28a9204..000000000 --- a/test_regress/t/t_assert_recursive_property_unsup.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - expect_filename=>$Self->{golden_filename}, - verilator_flags2=> ['--assert'], - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_recursive_property_unsup.py b/test_regress/t/t_assert_recursive_property_unsup.py new file mode 100755 index 000000000..7e5bcdfe5 --- /dev/null +++ b/test_regress/t/t_assert_recursive_property_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert'], fails=True) + +test.passes() diff --git a/test_regress/t/t_assert_sampled.pl b/test_regress/t/t_assert_sampled.pl deleted file mode 100755 index f96aad9b7..000000000 --- a/test_regress/t/t_assert_sampled.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--assert'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_sampled.py b/test_regress/t/t_assert_sampled.py new file mode 100755 index 000000000..2c4ffdce2 --- /dev/null +++ b/test_regress/t/t_assert_sampled.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--assert']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assert_synth.pl b/test_regress/t/t_assert_synth.pl deleted file mode 100755 index 4a1de974b..000000000 --- a/test_regress/t/t_assert_synth.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--assert'], - nc_flags2 => ['+assert'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_synth.py b/test_regress/t/t_assert_synth.py new file mode 100755 index 000000000..d97aaff01 --- /dev/null +++ b/test_regress/t/t_assert_synth.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--assert'], nc_flags2=['+assert']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assert_synth_full.pl b/test_regress/t/t_assert_synth_full.pl deleted file mode 100755 index be8b7d192..000000000 --- a/test_regress/t/t_assert_synth_full.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_assert_synth.v"); - -compile( - v_flags2 => ['+define+FAILING_FULL +define+ATTRIBUTES'], - verilator_flags2 => ['--assert'], - nc_flags2 => ['+assert'], - ); - -execute( - check_finished => 0, - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_synth_full.py b/test_regress/t/t_assert_synth_full.py new file mode 100755 index 000000000..5d213121c --- /dev/null +++ b/test_regress/t/t_assert_synth_full.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_assert_synth.v" + +test.compile(v_flags2=['+define+FAILING_FULL +define+ATTRIBUTES'], + verilator_flags2=['--assert'], + nc_flags2=['+assert']) + +test.execute(check_finished=False, fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_assert_synth_full_vlt.pl b/test_regress/t/t_assert_synth_full_vlt.pl deleted file mode 100755 index 14827a677..000000000 --- a/test_regress/t/t_assert_synth_full_vlt.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_assert_synth.v"); - -compile( - v_flags2 => ['+define+FAILING_FULL', "t/t_assert_synth_full.vlt"], - verilator_flags2 => ['--assert'], - nc_flags2 => ['+assert'], - ); - -execute( - check_finished => 0, - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_synth_full_vlt.py b/test_regress/t/t_assert_synth_full_vlt.py new file mode 100755 index 000000000..39ceee722 --- /dev/null +++ b/test_regress/t/t_assert_synth_full_vlt.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_assert_synth.v" + +test.compile(v_flags2=['+define+FAILING_FULL', "t/t_assert_synth_full.vlt"], + verilator_flags2=['--assert'], + nc_flags2=['+assert']) + +test.execute(check_finished=False, fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_assert_synth_off.pl b/test_regress/t/t_assert_synth_off.pl deleted file mode 100755 index 671c77de6..000000000 --- a/test_regress/t/t_assert_synth_off.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_assert_synth.v"); - -compile( - v_flags2 => ['+define+FAILING_FULL', - '+define+FAILING_PARALLEL', - '+define+FAILING_OH', - '+define+FAILING_OC', - ], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_synth_off.py b/test_regress/t/t_assert_synth_off.py new file mode 100755 index 000000000..ce86721c2 --- /dev/null +++ b/test_regress/t/t_assert_synth_off.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_assert_synth.v" + +test.compile(v_flags2=[ + '+define+FAILING_FULL', '+define+FAILING_PARALLEL', '+define+FAILING_OH', '+define+FAILING_OC' +]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assert_synth_parallel.pl b/test_regress/t/t_assert_synth_parallel.pl deleted file mode 100755 index 40cb662f1..000000000 --- a/test_regress/t/t_assert_synth_parallel.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_assert_synth.v"); - -compile( - v_flags2 => ['+define+FAILING_PARALLEL', '+define+ATTRIBUTES'], - verilator_flags2 => ['--assert'], - nc_flags2 => ['+assert'], - ); - -execute( - check_finished => 0, - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_synth_parallel.py b/test_regress/t/t_assert_synth_parallel.py new file mode 100755 index 000000000..1218cfb79 --- /dev/null +++ b/test_regress/t/t_assert_synth_parallel.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_assert_synth.v" + +test.compile(v_flags2=['+define+FAILING_PARALLEL', '+define+ATTRIBUTES'], + verilator_flags2=['--assert'], + nc_flags2=['+assert']) + +test.execute(check_finished=False, fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_assert_synth_parallel_vlt.pl b/test_regress/t/t_assert_synth_parallel_vlt.pl deleted file mode 100755 index 782d98d15..000000000 --- a/test_regress/t/t_assert_synth_parallel_vlt.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_assert_synth.v"); - -compile( - v_flags2 => ['+define+FAILING_PARALLEL', "t/t_assert_synth_parallel.vlt"], - verilator_flags2 => ['--assert'], - nc_flags2 => ['+assert'], - ); - -execute( - check_finished => 0, - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_synth_parallel_vlt.py b/test_regress/t/t_assert_synth_parallel_vlt.py new file mode 100755 index 000000000..72f8e67fc --- /dev/null +++ b/test_regress/t/t_assert_synth_parallel_vlt.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_assert_synth.v" + +test.compile(v_flags2=['+define+FAILING_PARALLEL', "t/t_assert_synth_parallel.vlt"], + verilator_flags2=['--assert'], + nc_flags2=['+assert']) + +test.execute(check_finished=False, fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_assert_unique_case.pl b/test_regress/t/t_assert_unique_case.pl deleted file mode 100755 index 7290dd960..000000000 --- a/test_regress/t/t_assert_unique_case.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); -top_filename("t/t_assert_unique_case_bad.v"); - -compile( - verilator_flags2 => ["-x-assign 0 --assert-case --no-stop-fail +define+NO_STOP_FAIL"], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_unique_case.py b/test_regress/t/t_assert_unique_case.py new file mode 100755 index 000000000..a76d4eb50 --- /dev/null +++ b/test_regress/t/t_assert_unique_case.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_assert_unique_case_bad.v" + +test.compile(verilator_flags2=["-x-assign 0 --assert-case --no-stop-fail +define+NO_STOP_FAIL"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_assert_unique_case_bad.pl b/test_regress/t/t_assert_unique_case_bad.pl deleted file mode 100755 index 70f34a0e1..000000000 --- a/test_regress/t/t_assert_unique_case_bad.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["-x-assign 0 --assert"], - ); - -execute( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assert_unique_case_bad.py b/test_regress/t/t_assert_unique_case_bad.py new file mode 100755 index 000000000..3924fa02d --- /dev/null +++ b/test_regress/t/t_assert_unique_case_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["-x-assign 0 --assert"]) + +test.execute(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_assign_expr.pl b/test_regress/t/t_assign_expr.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_assign_expr.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_assign_expr.py b/test_regress/t/t_assign_expr.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_assign_expr.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assign_inline.pl b/test_regress/t/t_assign_inline.pl deleted file mode 100755 index 0d9c5f833..000000000 --- a/test_regress/t/t_assign_inline.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["-O0 -fgate"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_assign_inline.py b/test_regress/t/t_assign_inline.py new file mode 100755 index 000000000..6a30330fc --- /dev/null +++ b/test_regress/t/t_assign_inline.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["-O0 -fgate"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assign_on_rhs_of_nonblocking_unsup.pl b/test_regress/t/t_assign_on_rhs_of_nonblocking_unsup.pl deleted file mode 100755 index 35d749208..000000000 --- a/test_regress/t/t_assign_on_rhs_of_nonblocking_unsup.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assign_on_rhs_of_nonblocking_unsup.py b/test_regress/t/t_assign_on_rhs_of_nonblocking_unsup.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_assign_on_rhs_of_nonblocking_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_assign_slice_overflow.pl b/test_regress/t/t_assign_slice_overflow.pl deleted file mode 100755 index 6e1338f8e..000000000 --- a/test_regress/t/t_assign_slice_overflow.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_assign_slice_overflow.py b/test_regress/t/t_assign_slice_overflow.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_assign_slice_overflow.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assign_slice_overflow_ox.pl b/test_regress/t/t_assign_slice_overflow_ox.pl deleted file mode 100755 index 5f530b6de..000000000 --- a/test_regress/t/t_assign_slice_overflow_ox.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t_assign_slice_overflow.v"); - -compile( - verilator_flags2 => ["-fno-expand"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_assign_slice_overflow_ox.py b/test_regress/t/t_assign_slice_overflow_ox.py new file mode 100755 index 000000000..b1371a321 --- /dev/null +++ b/test_regress/t/t_assign_slice_overflow_ox.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t_assign_slice_overflow.v" + +test.compile(verilator_flags2=["-fno-expand"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assigndly_dynamic.pl b/test_regress/t/t_assigndly_dynamic.pl deleted file mode 100755 index f8708065f..000000000 --- a/test_regress/t/t_assigndly_dynamic.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_assigndly_dynamic.py b/test_regress/t/t_assigndly_dynamic.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_assigndly_dynamic.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assigndly_dynamic_delay.pl b/test_regress/t/t_assigndly_dynamic_delay.pl deleted file mode 100755 index 16306c340..000000000 --- a/test_regress/t/t_assigndly_dynamic_delay.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_assigndly_dynamic.v"); - -compile( - verilator_flags2 => ["--exe --main --timing +define+WITH_DELAY"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_assigndly_dynamic_delay.py b/test_regress/t/t_assigndly_dynamic_delay.py new file mode 100755 index 000000000..6fc5a819d --- /dev/null +++ b/test_regress/t/t_assigndly_dynamic_delay.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_assigndly_dynamic" + +test.compile(verilator_flags2=["--exe --main --timing +define+WITH_DELAY"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assigndly_dynamic_nofork.pl b/test_regress/t/t_assigndly_dynamic_nofork.pl deleted file mode 100755 index f3611f5c0..000000000 --- a/test_regress/t/t_assigndly_dynamic_nofork.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_assigndly_task.v"); - -compile( - verilator_flags2 => ["--timing"], - ); - -foreach my $file ( - glob_all("$Self->{obj_dir}/$Self->{vm_prefix}*.h"), - glob_all("$Self->{obj_dir}/$Self->{vm_prefix}*.cpp") - ) { - file_grep_not($file, qr/__Vfork_/); -} - -ok(1); -1; diff --git a/test_regress/t/t_assigndly_dynamic_nofork.py b/test_regress/t/t_assigndly_dynamic_nofork.py new file mode 100755 index 000000000..999869c5c --- /dev/null +++ b/test_regress/t/t_assigndly_dynamic_nofork.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_assigndly_task.v" + +test.compile(verilator_flags2=["--timing"]) + +for filename in (test.glob_some(test.obj_dir + "/" + test.vm_prefix + "*.h") + + test.glob_some(test.obj_dir + "/" + test.vm_prefix + "*.cpp")): + test.file_grep_not(filename, r'__Vfork_') + +test.passes() diff --git a/test_regress/t/t_assigndly_dynamic_notiming_bad.pl b/test_regress/t/t_assigndly_dynamic_notiming_bad.pl deleted file mode 100755 index bf0b971e2..000000000 --- a/test_regress/t/t_assigndly_dynamic_notiming_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint( - verilator_flags2 => ["--no-timing"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assigndly_dynamic_notiming_bad.py b/test_regress/t/t_assigndly_dynamic_notiming_bad.py new file mode 100755 index 000000000..6f71603b5 --- /dev/null +++ b/test_regress/t/t_assigndly_dynamic_notiming_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(verilator_flags2=["--no-timing"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_assigndly_task.pl b/test_regress/t/t_assigndly_task.pl deleted file mode 100755 index da2e37bda..000000000 --- a/test_regress/t/t_assigndly_task.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_assigndly_task.py b/test_regress/t/t_assigndly_task.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_assigndly_task.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_assoc.pl b/test_regress/t/t_assoc.pl deleted file mode 100755 index 56363dab6..000000000 --- a/test_regress/t/t_assoc.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_assoc.py b/test_regress/t/t_assoc.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_assoc.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assoc2.pl b/test_regress/t/t_assoc2.pl deleted file mode 100755 index 56363dab6..000000000 --- a/test_regress/t/t_assoc2.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_assoc2.py b/test_regress/t/t_assoc2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_assoc2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assoc_compare.pl b/test_regress/t/t_assoc_compare.pl deleted file mode 100755 index 56363dab6..000000000 --- a/test_regress/t/t_assoc_compare.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_assoc_compare.py b/test_regress/t/t_assoc_compare.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_assoc_compare.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assoc_method.pl b/test_regress/t/t_assoc_method.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_assoc_method.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_assoc_method.py b/test_regress/t/t_assoc_method.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_assoc_method.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assoc_method_bad.pl b/test_regress/t/t_assoc_method_bad.pl deleted file mode 100755 index 63947fd00..000000000 --- a/test_regress/t/t_assoc_method_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assoc_method_bad.py b/test_regress/t/t_assoc_method_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_assoc_method_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_assoc_method_map.pl b/test_regress/t/t_assoc_method_map.pl deleted file mode 100755 index 63947fd00..000000000 --- a/test_regress/t/t_assoc_method_map.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assoc_method_map.py b/test_regress/t/t_assoc_method_map.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_assoc_method_map.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_assoc_nokey_bad.pl b/test_regress/t/t_assoc_nokey_bad.pl deleted file mode 100755 index c42f6c90d..000000000 --- a/test_regress/t/t_assoc_nokey_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assoc_nokey_bad.py b/test_regress/t/t_assoc_nokey_bad.py new file mode 100755 index 000000000..dece38f4e --- /dev/null +++ b/test_regress/t/t_assoc_nokey_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_assoc_ref_type.pl b/test_regress/t/t_assoc_ref_type.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_assoc_ref_type.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_assoc_ref_type.py b/test_regress/t/t_assoc_ref_type.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_assoc_ref_type.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assoc_wildcard.pl b/test_regress/t/t_assoc_wildcard.pl deleted file mode 100755 index 56363dab6..000000000 --- a/test_regress/t/t_assoc_wildcard.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_assoc_wildcard.py b/test_regress/t/t_assoc_wildcard.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_assoc_wildcard.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_assoc_wildcard_bad.pl b/test_regress/t/t_assoc_wildcard_bad.pl deleted file mode 100755 index 63947fd00..000000000 --- a/test_regress/t/t_assoc_wildcard_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assoc_wildcard_bad.py b/test_regress/t/t_assoc_wildcard_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_assoc_wildcard_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_assoc_wildcard_map.pl b/test_regress/t/t_assoc_wildcard_map.pl deleted file mode 100755 index 63947fd00..000000000 --- a/test_regress/t/t_assoc_wildcard_map.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_assoc_wildcard_map.py b/test_regress/t/t_assoc_wildcard_map.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_assoc_wildcard_map.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_assoc_wildcard_method.pl b/test_regress/t/t_assoc_wildcard_method.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_assoc_wildcard_method.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_assoc_wildcard_method.py b/test_regress/t/t_assoc_wildcard_method.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_assoc_wildcard_method.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_attr_parenstar.pl b/test_regress/t/t_attr_parenstar.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_attr_parenstar.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_attr_parenstar.py b/test_regress/t/t_attr_parenstar.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_attr_parenstar.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_bench_mux4k.pl b/test_regress/t/t_bench_mux4k.pl deleted file mode 100755 index 0fb4a2670..000000000 --- a/test_regress/t/t_bench_mux4k.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["--stats", - $Self->wno_unopthreads_for_few_cores()] - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_bench_mux4k.py b/test_regress/t/t_bench_mux4k.py new file mode 100755 index 000000000..1141bf9d2 --- /dev/null +++ b/test_regress/t/t_bench_mux4k.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["--stats", test.wno_unopthreads_for_few_cores]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_bench_mux4k_onecpu.pl b/test_regress/t/t_bench_mux4k_onecpu.pl deleted file mode 100755 index bd7cdca4e..000000000 --- a/test_regress/t/t_bench_mux4k_onecpu.pl +++ /dev/null @@ -1,32 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_bench_mux4k.v"); - -compile( - v_flags2 => ["--stats", - $Self->wno_unopthreads_for_few_cores()] - ); - -# WSL2 gives a warning and we must skip the test: -# "physcpubind: 0 1 2 3 ...\n No NUMA support available on this system." -my $nout = `numactl --show`; -if ($nout !~ /cpu/ || $nout =~ /No NUMA support available/i) { - skip("No numactl available"); -} else { - execute( - run_env => 'numactl -m 0 -C 0,0,0,0,0,0,0,0', - ); - ok(1); -} - -1; diff --git a/test_regress/t/t_bench_mux4k_onecpu.py b/test_regress/t/t_bench_mux4k_onecpu.py new file mode 100755 index 000000000..d71cf4d42 --- /dev/null +++ b/test_regress/t/t_bench_mux4k_onecpu.py @@ -0,0 +1,27 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_bench_mux4k.v" + +test.compile(v_flags2=["--stats", test.wno_unopthreads_for_few_cores]) + +# WSL2 gives a warning and we must skip the test: +# "physcpubind: 0 1 2 3 ...\n No NUMA support available on this system." +nout = test.run_capture("numactl --show", check=False) + +if not nout or not re.search(r'cpu', nout) or re.search(r'No NUMA support available', nout, + re.IGNORECASE): + test.skip("No numactl available") + +test.execute(run_env='numactl -m 0 -C 0,0,0,0,0,0,0,0') + +test.passes() diff --git a/test_regress/t/t_benchmarksim.pl b/test_regress/t/t_benchmarksim.pl deleted file mode 100755 index bbf27bbc7..000000000 --- a/test_regress/t/t_benchmarksim.pl +++ /dev/null @@ -1,52 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -# Use any top file -top_filename("t/t_gen_alw.v"); - -init_benchmarksim(); - -# As an example, compile and simulate the top file with varying optimization level -my @l_opt = (1, 2, 3); - -foreach my $l_opt (@l_opt) { - compile( - benchmarksim => 1, - v_flags2 => ["-O$l_opt"] - ); - - execute( - ); -} - -my $fh = IO::File->new("<" . benchmarksim_filename()) or error("Benchmark data file not found"); -my $lines = 0; -while (defined(my $line = $fh->getline)) { - if ($line =~ /^#/) { next; } - if ($lines == 0) { - error("Expected header but found $line") if $line ne "evals, time[s]\n"; - } else { - my @data = grep {$_ != ""} ($line =~ /(\d*\.?\d*)/g); - error("Expected 2 tokens on line " . $lines . " but got " . scalar(@data)) if scalar(@data) != 2; - my $cycles = $data[0]; - my $time = $data[1]; - error("Invalid data on line " . $lines) if $cycles <= 0.0 || $time <= 0.0; - } - $lines += 1; -} -my $n_lines_expected = scalar(@l_opt) + 1; - -error("Expected " . $n_lines_expected . " lines but found " . $lines) - if int($lines) != int($n_lines_expected); - -1; -ok(1); diff --git a/test_regress/t/t_benchmarksim.py b/test_regress/t/t_benchmarksim.py new file mode 100755 index 000000000..966eea90c --- /dev/null +++ b/test_regress/t/t_benchmarksim.py @@ -0,0 +1,54 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_gen_alw.v" # Use any top file + +test.init_benchmarksim() + +# As an example, compile and simulate the top file with varying optimization level +l_opts = [1, 2, 3] + +for l_opt in l_opts: + test.compile(benchmarksim=1, v_flags2=["-O" + str(l_opt)]) + + test.execute() + +filename = test.benchmarksim_filename +gotn = 0 +with open(filename, 'r', encoding="utf8") as fh: + lineno = 0 + headered = False + for line in fh: + lineno += 1 + if re.match(r'^#', line): + continue + if not headered: + headered = True + if not re.search(r'evals, ', line): + test.error(filename + ":" + str(lineno) + ": Expected header but found: " + line) + else: + m = re.search(r'(\d+\.?\d*),(\d+\.?\d*)', line) + if not m: + test.error(filename + ":" + str(lineno) + ": Expected 2 tokens on line: " + line) + continue + cycles = float(m.group(1)) + time = float(m.group(2)) + if cycles <= 0.0 or time <= 0.0: + test.error(filename + ":" + str(lineno) + ": Invalid data on line: " + line) + continue + gotn += 1 + +n_lines_expected = len(l_opts) +if gotn != int(n_lines_expected): + test.error("Expected " + str(n_lines_expected) + " lines but found " + str(gotn)) + +test.passes() diff --git a/test_regress/t/t_bigmem_bad.pl b/test_regress/t/t_bigmem_bad.pl deleted file mode 100755 index 66a4e492d..000000000 --- a/test_regress/t/t_bigmem_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_bigmem_bad.py b/test_regress/t/t_bigmem_bad.py new file mode 100755 index 000000000..dece38f4e --- /dev/null +++ b/test_regress/t/t_bigmem_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_bind.pl b/test_regress/t/t_bind.pl deleted file mode 100755 index fdc76316a..000000000 --- a/test_regress/t/t_bind.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_bind.py b/test_regress/t/t_bind.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_bind.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_bind2.pl b/test_regress/t/t_bind2.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_bind2.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_bind2.py b/test_regress/t/t_bind2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_bind2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_bind_nfound.pl b/test_regress/t/t_bind_nfound.pl deleted file mode 100755 index 7918d5f13..000000000 --- a/test_regress/t/t_bind_nfound.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_bind_nfound.py b/test_regress/t/t_bind_nfound.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_bind_nfound.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_bitsel_concat.pl b/test_regress/t/t_bitsel_concat.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_bitsel_concat.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_bitsel_concat.py b/test_regress/t/t_bitsel_concat.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_bitsel_concat.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_bitsel_const_bad.pl b/test_regress/t/t_bitsel_const_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_bitsel_const_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_bitsel_const_bad.py b/test_regress/t/t_bitsel_const_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_bitsel_const_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_bitsel_enum.pl b/test_regress/t/t_bitsel_enum.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_bitsel_enum.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_bitsel_enum.py b/test_regress/t/t_bitsel_enum.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_bitsel_enum.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_bitsel_slice.pl b/test_regress/t/t_bitsel_slice.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_bitsel_slice.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_bitsel_slice.py b/test_regress/t/t_bitsel_slice.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_bitsel_slice.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_bitsel_struct.pl b/test_regress/t/t_bitsel_struct.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_bitsel_struct.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_bitsel_struct.py b/test_regress/t/t_bitsel_struct.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_bitsel_struct.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_bitsel_struct2.pl b/test_regress/t/t_bitsel_struct2.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_bitsel_struct2.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_bitsel_struct2.py b/test_regress/t/t_bitsel_struct2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_bitsel_struct2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_bitsel_struct3.pl b/test_regress/t/t_bitsel_struct3.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_bitsel_struct3.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_bitsel_struct3.py b/test_regress/t/t_bitsel_struct3.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_bitsel_struct3.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_bitsel_wire_array_bad.pl b/test_regress/t/t_bitsel_wire_array_bad.pl deleted file mode 100755 index af94708c0..000000000 --- a/test_regress/t/t_bitsel_wire_array_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -# Compile time only test - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_bitsel_wire_array_bad.py b/test_regress/t/t_bitsel_wire_array_bad.py new file mode 100755 index 000000000..d0fba6a98 --- /dev/null +++ b/test_regress/t/t_bitsel_wire_array_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +# Compile time only test + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_blocking.pl b/test_regress/t/t_blocking.pl deleted file mode 100755 index fdc76316a..000000000 --- a/test_regress/t/t_blocking.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_blocking.py b/test_regress/t/t_blocking.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_blocking.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_bug3180.pl b/test_regress/t/t_bug3180.pl deleted file mode 100755 index 79556a789..000000000 --- a/test_regress/t/t_bug3180.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['-Wall -Wno-DECLFILENAME --coverage-line'], - ); - -ok(1); -1; diff --git a/test_regress/t/t_bug3180.py b/test_regress/t/t_bug3180.py new file mode 100755 index 000000000..eb6589504 --- /dev/null +++ b/test_regress/t/t_bug3180.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['-Wall -Wno-DECLFILENAME --coverage-line']) + +test.passes() diff --git a/test_regress/t/t_c_this.pl b/test_regress/t/t_c_this.pl deleted file mode 100755 index 7fa144221..000000000 --- a/test_regress/t/t_c_this.pl +++ /dev/null @@ -1,36 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile(); - -if ($Self->{vlt_all}) { - # The word 'this' (but only the whole word 'this' should have been replaced - # in the contents. - my $has_this = 0; - my $has_xthis = 0; - my $has_thisx = 0; - my $has_xthisx = 0; - for my $file (glob_all("$Self->{obj_dir}/$Self->{vm_prefix}___024root__DepSet_*__0.cpp")) { - my $text = file_contents($file); - $has_this = 1 if ($text =~ m/\bthis->clk\b/); - $has_xthis = 1 if ($text =~ m/\bxthis\b/); - $has_thisx = 1 if ($text =~ m/\bthisx\b/); - $has_xthisx = 1 if ($text =~ m/\bxthisx\b/); - } - error("Some file has 'this->clk'") if $has_this; - error("No file has 'xthis'") if !$has_xthis; - error("No file has 'thisx'") if !$has_thisx; - error("No file has 'xthisx'") if !$has_xthisx; -} - -ok(1); -1; diff --git a/test_regress/t/t_c_this.py b/test_regress/t/t_c_this.py new file mode 100755 index 000000000..bdbed8811 --- /dev/null +++ b/test_regress/t/t_c_this.py @@ -0,0 +1,44 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +if test.vlt_all: + # The word 'this' (but only the whole word 'this' should have been replaced + # in the contents. + has_this = False + has_xthis = False + has_thisx = False + has_xthisx = False + for filename in test.glob_some(test.obj_dir + "/" + test.vm_prefix + + "___024root__DepSet_*__0.cpp"): + text = test.file_contents(filename) + if re.search(r'\bthis->clk\b', text): + has_this = True + if re.search(r'\bxthis\b', text): + has_xthis = True + if re.search(r'\bthisx\b', text): + has_thisx = True + if re.search(r'\bxthisx\b', text): + has_xthisx = True + + if has_this: + test.error("Some file has 'this->clk'") + if not has_xthis: + test.error("No file has 'xthis'") + if not has_thisx: + test.error("No file has 'thisx'") + if not has_xthisx: + test.error("No file has 'xthisx'") + +test.passes() diff --git a/test_regress/t/t_case_66bits.pl b/test_regress/t/t_case_66bits.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_case_66bits.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_66bits.py b/test_regress/t/t_case_66bits.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_case_66bits.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_case_66bits_noexpand.pl b/test_regress/t/t_case_66bits_noexpand.pl deleted file mode 100755 index 97922bc33..000000000 --- a/test_regress/t/t_case_66bits_noexpand.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_case_66bits.v"); - -compile( - verilator_flags2 => ['-fno-expand'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_66bits_noexpand.py b/test_regress/t/t_case_66bits_noexpand.py new file mode 100755 index 000000000..2316143be --- /dev/null +++ b/test_regress/t/t_case_66bits_noexpand.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_case_66bits.v" + +test.compile(verilator_flags2=['-fno-expand']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_case_auto1.pl b/test_regress/t/t_case_auto1.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_case_auto1.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_auto1.py b/test_regress/t/t_case_auto1.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_case_auto1.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_case_deep.pl b/test_regress/t/t_case_deep.pl deleted file mode 100755 index 1185a445f..000000000 --- a/test_regress/t/t_case_deep.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--compiler msvc"], # We have deep expressions we want to test - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_deep.py b/test_regress/t/t_case_deep.py new file mode 100755 index 000000000..95c3e8bca --- /dev/null +++ b/test_regress/t/t_case_deep.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + # We have deep expressions we want to test + verilator_flags2=["--compiler msvc"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_case_default_bad.pl b/test_regress/t/t_case_default_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_case_default_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_default_bad.py b/test_regress/t/t_case_default_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_case_default_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_case_dupitems.pl b/test_regress/t/t_case_dupitems.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_case_dupitems.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_dupitems.py b/test_regress/t/t_case_dupitems.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_case_dupitems.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_case_duplicated_if.pl b/test_regress/t/t_case_duplicated_if.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_case_duplicated_if.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_duplicated_if.py b/test_regress/t/t_case_duplicated_if.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_case_duplicated_if.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_case_enum_complete.pl b/test_regress/t/t_case_enum_complete.pl deleted file mode 100755 index 59837c4db..000000000 --- a/test_regress/t/t_case_enum_complete.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only -Wwarn-CASEINCOMPLETE"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_enum_complete.py b/test_regress/t/t_case_enum_complete.py new file mode 100755 index 000000000..03bb69a41 --- /dev/null +++ b/test_regress/t/t_case_enum_complete.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only -Wwarn-CASEINCOMPLETE"]) + +test.passes() diff --git a/test_regress/t/t_case_enum_complete_wildcard.pl b/test_regress/t/t_case_enum_complete_wildcard.pl deleted file mode 100755 index 59837c4db..000000000 --- a/test_regress/t/t_case_enum_complete_wildcard.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only -Wwarn-CASEINCOMPLETE"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_enum_complete_wildcard.py b/test_regress/t/t_case_enum_complete_wildcard.py new file mode 100755 index 000000000..03bb69a41 --- /dev/null +++ b/test_regress/t/t_case_enum_complete_wildcard.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only -Wwarn-CASEINCOMPLETE"]) + +test.passes() diff --git a/test_regress/t/t_case_enum_emptyish.pl b/test_regress/t/t_case_enum_emptyish.pl deleted file mode 100755 index 1185a445f..000000000 --- a/test_regress/t/t_case_enum_emptyish.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--compiler msvc"], # We have deep expressions we want to test - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_enum_emptyish.py b/test_regress/t/t_case_enum_emptyish.py new file mode 100755 index 000000000..539f320b1 --- /dev/null +++ b/test_regress/t/t_case_enum_emptyish.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + # We have deep expressions we want to test) + verilator_flags2=["--compiler msvc"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_case_enum_incomplete_bad.pl b/test_regress/t/t_case_enum_incomplete_bad.pl deleted file mode 100755 index 1d5773686..000000000 --- a/test_regress/t/t_case_enum_incomplete_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ['--assert'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_enum_incomplete_bad.py b/test_regress/t/t_case_enum_incomplete_bad.py new file mode 100755 index 000000000..0275f2df9 --- /dev/null +++ b/test_regress/t/t_case_enum_incomplete_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=['--assert'], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_case_enum_incomplete_wildcard_bad.pl b/test_regress/t/t_case_enum_incomplete_wildcard_bad.pl deleted file mode 100755 index 1d5773686..000000000 --- a/test_regress/t/t_case_enum_incomplete_wildcard_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ['--assert'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_enum_incomplete_wildcard_bad.py b/test_regress/t/t_case_enum_incomplete_wildcard_bad.py new file mode 100755 index 000000000..0275f2df9 --- /dev/null +++ b/test_regress/t/t_case_enum_incomplete_wildcard_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=['--assert'], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_case_genx_bad.pl b/test_regress/t/t_case_genx_bad.pl deleted file mode 100755 index 35d749208..000000000 --- a/test_regress/t/t_case_genx_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_genx_bad.py b/test_regress/t/t_case_genx_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_case_genx_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_case_group.pl b/test_regress/t/t_case_group.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_case_group.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_group.py b/test_regress/t/t_case_group.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_case_group.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_case_huge.pl b/test_regress/t/t_case_huge.pl deleted file mode 100755 index a3d78fffd..000000000 --- a/test_regress/t/t_case_huge.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -if ($Self->{vlt}) { - file_grep($Self->{stats}, qr/Optimizations, Tables created\s+(\d+)/, 10); - file_grep($Self->{stats}, qr/Optimizations, Combined CFuncs\s+(\d+)/, 8); -} elsif ($Self->{vltmt}) { - file_grep($Self->{stats}, qr/Optimizations, Tables created\s+(\d+)/, 10); - file_grep($Self->{stats}, qr/Optimizations, Combined CFuncs\s+(\d+)/, 9); -} - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_huge.py b/test_regress/t/t_case_huge.py new file mode 100755 index 000000000..7b6f76fea --- /dev/null +++ b/test_regress/t/t_case_huge.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats"]) + +if test.vlt: + test.file_grep(test.stats, r'Optimizations, Tables created\s+(\d+)', 10) + test.file_grep(test.stats, r'Optimizations, Combined CFuncs\s+(\d+)', 8) +elif test.vltmt: + test.file_grep(test.stats, r'Optimizations, Tables created\s+(\d+)', 10) + test.file_grep(test.stats, r'Optimizations, Combined CFuncs\s+(\d+)', 9) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_case_incrdecr.pl b/test_regress/t/t_case_incrdecr.pl deleted file mode 100755 index e7aecd291..000000000 --- a/test_regress/t/t_case_incrdecr.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--trace --fno-split -x-assign 0"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_incrdecr.py b/test_regress/t/t_case_incrdecr.py new file mode 100755 index 000000000..30ddf27c9 --- /dev/null +++ b/test_regress/t/t_case_incrdecr.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--trace --fno-split -x-assign 0"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_case_inside.pl b/test_regress/t/t_case_inside.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_case_inside.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_inside.py b/test_regress/t/t_case_inside.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_case_inside.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_case_inside_bad.pl b/test_regress/t/t_case_inside_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_case_inside_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_inside_bad.py b/test_regress/t/t_case_inside_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_case_inside_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_case_itemwidth.pl b/test_regress/t/t_case_itemwidth.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_case_itemwidth.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_itemwidth.py b/test_regress/t/t_case_itemwidth.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_case_itemwidth.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_case_nest.pl b/test_regress/t/t_case_nest.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_case_nest.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_nest.py b/test_regress/t/t_case_nest.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_case_nest.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_case_onehot.pl b/test_regress/t/t_case_onehot.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_case_onehot.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_onehot.py b/test_regress/t/t_case_onehot.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_case_onehot.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_case_orig.pl b/test_regress/t/t_case_orig.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_case_orig.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_orig.py b/test_regress/t/t_case_orig.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_case_orig.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_case_overlap_bad.pl b/test_regress/t/t_case_overlap_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_case_overlap_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_overlap_bad.py b/test_regress/t/t_case_overlap_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_case_overlap_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_case_reducer.pl b/test_regress/t/t_case_reducer.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_case_reducer.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_reducer.py b/test_regress/t/t_case_reducer.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_case_reducer.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_case_string.pl b/test_regress/t/t_case_string.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_case_string.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_string.py b/test_regress/t/t_case_string.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_case_string.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_case_string2.pl b/test_regress/t/t_case_string2.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_case_string2.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_string2.py b/test_regress/t/t_case_string2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_case_string2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_case_unique_many.pl b/test_regress/t/t_case_unique_many.pl deleted file mode 100755 index b82179a46..000000000 --- a/test_regress/t/t_case_unique_many.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--assert"], - sanitize => 0, # GCC 11.4.0 hang bug - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_unique_many.py b/test_regress/t/t_case_unique_many.py new file mode 100755 index 000000000..15e80d521 --- /dev/null +++ b/test_regress/t/t_case_unique_many.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--assert"], sanitize=False) # GCC 11.4.0 hang bug + +test.execute() + +test.passes() diff --git a/test_regress/t/t_case_wild.pl b/test_regress/t/t_case_wild.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_case_wild.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_wild.py b/test_regress/t/t_case_wild.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_case_wild.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_case_write1.pl b/test_regress/t/t_case_write1.pl deleted file mode 100755 index 0dcb23db5..000000000 --- a/test_regress/t/t_case_write1.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--stats -O3 -x-assign fast"], - ); - -execute( - ); - -files_identical("$Self->{obj_dir}/$Self->{name}_logger.log", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_case_write1.py b/test_regress/t/t_case_write1.py new file mode 100755 index 000000000..37d0f7a42 --- /dev/null +++ b/test_regress/t/t_case_write1.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats -O3 -x-assign fast"]) + +test.execute() + +test.files_identical(test.obj_dir + "/" + test.name + "_logger.log", test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_case_write1_noexpand.pl b/test_regress/t/t_case_write1_noexpand.pl deleted file mode 100755 index b80d2e08e..000000000 --- a/test_regress/t/t_case_write1_noexpand.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_case_write1.v"); - -compile( - verilator_flags2 => ['-fno-expand'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_write1_noexpand.py b/test_regress/t/t_case_write1_noexpand.py new file mode 100755 index 000000000..3ed6fde1c --- /dev/null +++ b/test_regress/t/t_case_write1_noexpand.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_case_write1.v" + +test.compile(verilator_flags2=['-fno-expand']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_case_write2.pl b/test_regress/t/t_case_write2.pl deleted file mode 100755 index 0dcb23db5..000000000 --- a/test_regress/t/t_case_write2.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--stats -O3 -x-assign fast"], - ); - -execute( - ); - -files_identical("$Self->{obj_dir}/$Self->{name}_logger.log", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_case_write2.py b/test_regress/t/t_case_write2.py new file mode 100755 index 000000000..37d0f7a42 --- /dev/null +++ b/test_regress/t/t_case_write2.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats -O3 -x-assign fast"]) + +test.execute() + +test.files_identical(test.obj_dir + "/" + test.name + "_logger.log", test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_case_x.pl b/test_regress/t/t_case_x.pl deleted file mode 100755 index e22d62a51..000000000 --- a/test_regress/t/t_case_x.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--x-assign 0"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_x.py b/test_regress/t/t_case_x.py new file mode 100755 index 000000000..8aee590f3 --- /dev/null +++ b/test_regress/t/t_case_x.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--x-assign 0"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_case_x_bad.pl b/test_regress/t/t_case_x_bad.pl deleted file mode 100755 index 35d749208..000000000 --- a/test_regress/t/t_case_x_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_x_bad.py b/test_regress/t/t_case_x_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_case_x_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_case_zx_bad.pl b/test_regress/t/t_case_zx_bad.pl deleted file mode 100755 index 35d749208..000000000 --- a/test_regress/t/t_case_zx_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_case_zx_bad.py b/test_regress/t/t_case_zx_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_case_zx_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_cast.pl b/test_regress/t/t_cast.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_cast.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_cast.py b/test_regress/t/t_cast.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_cast.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_cast_class.pl b/test_regress/t/t_cast_class.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_cast_class.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_cast_class.py b/test_regress/t/t_cast_class.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_cast_class.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_cast_class_incompat_bad.pl b/test_regress/t/t_cast_class_incompat_bad.pl deleted file mode 100755 index 9c9fb65a0..000000000 --- a/test_regress/t/t_cast_class_incompat_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_cast_class_incompat_bad.py b/test_regress/t/t_cast_class_incompat_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_cast_class_incompat_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_cast_param_logic.pl b/test_regress/t/t_cast_param_logic.pl deleted file mode 100755 index 09b2ce4eb..000000000 --- a/test_regress/t/t_cast_param_logic.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - ); - -ok(1); -1; diff --git a/test_regress/t/t_cast_param_logic.py b/test_regress/t/t_cast_param_logic.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_cast_param_logic.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_cast_param_type.pl b/test_regress/t/t_cast_param_type.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_cast_param_type.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_cast_param_type.py b/test_regress/t/t_cast_param_type.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_cast_param_type.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_cast_size_bad.pl b/test_regress/t/t_cast_size_bad.pl deleted file mode 100755 index 9c9fb65a0..000000000 --- a/test_regress/t/t_cast_size_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_cast_size_bad.py b/test_regress/t/t_cast_size_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_cast_size_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_cast_types.pl b/test_regress/t/t_cast_types.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_cast_types.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_cast_types.py b/test_regress/t/t_cast_types.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_cast_types.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_castdyn.pl b/test_regress/t/t_castdyn.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_castdyn.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_castdyn.py b/test_regress/t/t_castdyn.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_castdyn.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_castdyn_bbox.pl b/test_regress/t/t_castdyn_bbox.pl deleted file mode 100755 index 3c7a5909b..000000000 --- a/test_regress/t/t_castdyn_bbox.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -top_filename("t/t_castdyn.v"); - -lint( - verilator_flags2 => ['-bbox-unsup'], - ); - -ok(1); -1; diff --git a/test_regress/t/t_castdyn_bbox.py b/test_regress/t/t_castdyn_bbox.py new file mode 100755 index 000000000..3bc0aac7a --- /dev/null +++ b/test_regress/t/t_castdyn_bbox.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_castdyn.v" + +test.lint(verilator_flags2=['-bbox-unsup']) + +test.passes() diff --git a/test_regress/t/t_castdyn_castconst_bad.pl b/test_regress/t/t_castdyn_castconst_bad.pl deleted file mode 100755 index 35d749208..000000000 --- a/test_regress/t/t_castdyn_castconst_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_castdyn_castconst_bad.py b/test_regress/t/t_castdyn_castconst_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_castdyn_castconst_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_castdyn_enum.pl b/test_regress/t/t_castdyn_enum.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_castdyn_enum.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_castdyn_enum.py b/test_regress/t/t_castdyn_enum.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_castdyn_enum.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_castdyn_run_bad.pl b/test_regress/t/t_castdyn_run_bad.pl deleted file mode 100755 index 8b1946a7b..000000000 --- a/test_regress/t/t_castdyn_run_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_castdyn_run_bad.py b/test_regress/t/t_castdyn_run_bad.py new file mode 100755 index 000000000..2fdd6e92d --- /dev/null +++ b/test_regress/t/t_castdyn_run_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_castdyn_unsup_bad.pl b/test_regress/t/t_castdyn_unsup_bad.pl deleted file mode 100755 index 35d749208..000000000 --- a/test_regress/t/t_castdyn_unsup_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_castdyn_unsup_bad.py b/test_regress/t/t_castdyn_unsup_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_castdyn_unsup_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_ccache_report.pl b/test_regress/t/t_ccache_report.pl deleted file mode 100755 index 90c5004a2..000000000 --- a/test_regress/t/t_ccache_report.pl +++ /dev/null @@ -1,49 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -if (!$Self->cfg_with_ccache) { - skip("Requires configuring with ccache"); -} -else { - top_filename("t_a1_first_cc.v"); - - # This test requires rebuilding the object files to check the ccache log - foreach my $filename (glob("$Self->{obj_dir}/*.o")) { - print "rm $filename\n" if $Self->{verbose}; - unlink $filename; - } - - compile( - verilator_flags2 => ['--trace'], - make_flags => "ccache-report" - ); - - my $report = "$Self->{obj_dir}/$Self->{vm_prefix}__ccache_report.txt"; - - # We do not actually want to make this test depend on whether the file was - # cached or not, so trim the report to ignore actual caching behaviour - run(cmd => ["sed", "-i", "-e", "'s/ : .*/ : IGNORED/; /|/s/.*/IGNORED/;'", $report]); - files_identical($report, "t/$Self->{name}__ccache_report_initial.out"); - - # Now rebuild again (should be all up to date) - run( - logfile => "$Self->{obj_dir}/rebuild.log", - cmd => ["make", "-C", $Self->{obj_dir}, - "-f", "$Self->{vm_prefix}.mk", - $Self->{vm_prefix}, "ccache-report"] - ); - - files_identical($report, "t/$Self->{name}__ccache_report_rebuild.out"); -} - -ok(1); -1; diff --git a/test_regress/t/t_ccache_report.py b/test_regress/t/t_ccache_report.py new file mode 100755 index 000000000..56d6a44af --- /dev/null +++ b/test_regress/t/t_ccache_report.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t_a1_first_cc.v" + +if not test.cfg_with_ccache: + test.skip("Requires configuring with ccache") + +# This test requires rebuilding the object files to check the ccache log +for filename in glob.glob(test.obj_dir + "/*.o"): + test.unlink_ok(filename) + +test.compile(verilator_flags2=['--trace'], make_flags=["ccache-report"]) + +report = test.obj_dir + "/" + test.vm_prefix + "__ccache_report.txt" + +# We do not actually want to make this test depend on whether the file was +# cached or not, so trim the report to ignore actual caching behaviour +test.run(cmd=["sed", "-i", "-e", "'s/ : .*/ : IGNORED/; /|/s/.*/IGNORED/;'", report]) +test.files_identical(report, "t/" + test.name + "__ccache_report_initial.out") + +# Now rebuild again (should be all up to date) +test.run(logfile=test.obj_dir + "/rebuild.log", + cmd=[ + "make", "-C " + test.obj_dir, "-f " + test.vm_prefix + ".mk", test.vm_prefix, + "ccache-report" + ]) + +test.files_identical(report, "t/" + test.name + "__ccache_report_rebuild.out") + +test.passes() diff --git a/test_regress/t/t_cellarray.pl b/test_regress/t/t_cellarray.pl deleted file mode 100755 index 8bc9f4cab..000000000 --- a/test_regress/t/t_cellarray.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["--stats -fno-dfg"], - ); - -execute( - ); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, Gate assign merged\s+(\d+)/, 28); -} - -ok(1); -1; diff --git a/test_regress/t/t_cellarray.py b/test_regress/t/t_cellarray.py new file mode 100755 index 000000000..402425622 --- /dev/null +++ b/test_regress/t/t_cellarray.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["--stats -fno-dfg"]) + +test.execute() + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, Gate assign merged\s+(\d+)', 28) + +test.passes() diff --git a/test_regress/t/t_checker.pl b/test_regress/t/t_checker.pl deleted file mode 100755 index c578092c4..000000000 --- a/test_regress/t/t_checker.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ['--assert'], - expect_filename => $Self->{golden_filename}, - fails => $Self->{vlt_all}, - ); - -#execute( -# ); - -ok(1); -1; diff --git a/test_regress/t/t_checker.py b/test_regress/t/t_checker.py new file mode 100755 index 000000000..c735f5265 --- /dev/null +++ b/test_regress/t/t_checker.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['--assert'], + expect_filename=test.golden_filename, + fails=test.vlt_all) + +#test.execute() + +test.passes() diff --git a/test_regress/t/t_chg_first.pl b/test_regress/t/t_chg_first.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_chg_first.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_chg_first.py b/test_regress/t/t_chg_first.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_chg_first.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class1.pl b/test_regress/t/t_class1.pl deleted file mode 100755 index ba0cd2b16..000000000 --- a/test_regress/t/t_class1.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class1.py b/test_regress/t/t_class1.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_class1.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class2.pl b/test_regress/t/t_class2.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_class2.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class2.py b/test_regress/t/t_class2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_assign_bad.pl b/test_regress/t/t_class_assign_bad.pl deleted file mode 100755 index c35c8bc93..000000000 --- a/test_regress/t/t_class_assign_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_assign_bad.py b/test_regress/t/t_class_assign_bad.py new file mode 100755 index 000000000..efe8cc01c --- /dev/null +++ b/test_regress/t/t_class_assign_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_assign_cond.pl b/test_regress/t/t_class_assign_cond.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_class_assign_cond.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_assign_cond.py b/test_regress/t/t_class_assign_cond.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_assign_cond.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_assign_cond_bad.pl b/test_regress/t/t_class_assign_cond_bad.pl deleted file mode 100755 index c35c8bc93..000000000 --- a/test_regress/t/t_class_assign_cond_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_assign_cond_bad.py b/test_regress/t/t_class_assign_cond_bad.py new file mode 100755 index 000000000..efe8cc01c --- /dev/null +++ b/test_regress/t/t_class_assign_cond_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_builtin_bad.pl b/test_regress/t/t_class_builtin_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_class_builtin_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_builtin_bad.py b/test_regress/t/t_class_builtin_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_builtin_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_capitalization.pl b/test_regress/t/t_class_capitalization.pl deleted file mode 100755 index 3708008f8..000000000 --- a/test_regress/t/t_class_capitalization.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_capitalization.py b/test_regress/t/t_class_capitalization.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_capitalization.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_class.pl b/test_regress/t/t_class_class.pl deleted file mode 100755 index 6ad7137de..000000000 --- a/test_regress/t/t_class_class.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_class.py b/test_regress/t/t_class_class.py new file mode 100755 index 000000000..710a094ab --- /dev/null +++ b/test_regress/t/t_class_class.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_compare.pl b/test_regress/t/t_class_compare.pl deleted file mode 100755 index 56363dab6..000000000 --- a/test_regress/t/t_class_compare.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_compare.py b/test_regress/t/t_class_compare.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_compare.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_const.pl b/test_regress/t/t_class_const.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_class_const.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_const.py b/test_regress/t/t_class_const.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_const.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_copy.pl b/test_regress/t/t_class_copy.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_class_copy.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_copy.py b/test_regress/t/t_class_copy.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_copy.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_copy2.pl b/test_regress/t/t_class_copy2.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_class_copy2.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_copy2.py b/test_regress/t/t_class_copy2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_copy2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_copy_bad.pl b/test_regress/t/t_class_copy_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_class_copy_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_copy_bad.py b/test_regress/t/t_class_copy_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_copy_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_diamond.pl b/test_regress/t/t_class_diamond.pl deleted file mode 100755 index 3708008f8..000000000 --- a/test_regress/t/t_class_diamond.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_diamond.py b/test_regress/t/t_class_diamond.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_diamond.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_dict.pl b/test_regress/t/t_class_dict.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_class_dict.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_dict.py b/test_regress/t/t_class_dict.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_dict.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_enum.pl b/test_regress/t/t_class_enum.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_class_enum.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_enum.py b/test_regress/t/t_class_enum.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_enum.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_extends.pl b/test_regress/t/t_class_extends.pl deleted file mode 100755 index e6e437a60..000000000 --- a/test_regress/t/t_class_extends.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_flags => 'VM_PARALLEL_BUILDS=1', # bug2775 - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_extends.py b/test_regress/t/t_class_extends.py new file mode 100755 index 000000000..952d410ef --- /dev/null +++ b/test_regress/t/t_class_extends.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_flags=['VM_PARALLEL_BUILDS=1']) # bug2775) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_extends1.pl b/test_regress/t/t_class_extends1.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_class_extends1.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_extends1.py b/test_regress/t/t_class_extends1.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_extends1.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_extends2.pl b/test_regress/t/t_class_extends2.pl deleted file mode 100755 index e6e437a60..000000000 --- a/test_regress/t/t_class_extends2.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_flags => 'VM_PARALLEL_BUILDS=1', # bug2775 - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_extends2.py b/test_regress/t/t_class_extends2.py new file mode 100755 index 000000000..952d410ef --- /dev/null +++ b/test_regress/t/t_class_extends2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_flags=['VM_PARALLEL_BUILDS=1']) # bug2775) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_extends_alias_unsup.pl b/test_regress/t/t_class_extends_alias_unsup.pl deleted file mode 100755 index 376c2d2ee..000000000 --- a/test_regress/t/t_class_extends_alias_unsup.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_extends_alias_unsup.py b/test_regress/t/t_class_extends_alias_unsup.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_extends_alias_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_extends_aliased_real_bad.pl b/test_regress/t/t_class_extends_aliased_real_bad.pl deleted file mode 100755 index 376c2d2ee..000000000 --- a/test_regress/t/t_class_extends_aliased_real_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_extends_aliased_real_bad.py b/test_regress/t/t_class_extends_aliased_real_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_extends_aliased_real_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_extends_bad.pl b/test_regress/t/t_class_extends_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_class_extends_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_extends_bad.py b/test_regress/t/t_class_extends_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_extends_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_extends_colon.pl b/test_regress/t/t_class_extends_colon.pl deleted file mode 100755 index e6e437a60..000000000 --- a/test_regress/t/t_class_extends_colon.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_flags => 'VM_PARALLEL_BUILDS=1', # bug2775 - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_extends_colon.py b/test_regress/t/t_class_extends_colon.py new file mode 100755 index 000000000..952d410ef --- /dev/null +++ b/test_regress/t/t_class_extends_colon.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_flags=['VM_PARALLEL_BUILDS=1']) # bug2775) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_extends_int_param_bad.pl b/test_regress/t/t_class_extends_int_param_bad.pl deleted file mode 100755 index 376c2d2ee..000000000 --- a/test_regress/t/t_class_extends_int_param_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_extends_int_param_bad.py b/test_regress/t/t_class_extends_int_param_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_extends_int_param_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_extends_nf_bad.pl b/test_regress/t/t_class_extends_nf_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_class_extends_nf_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_extends_nf_bad.py b/test_regress/t/t_class_extends_nf_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_extends_nf_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_extends_param.pl b/test_regress/t/t_class_extends_param.pl deleted file mode 100755 index 176f35697..000000000 --- a/test_regress/t/t_class_extends_param.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile(); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_extends_param.py b/test_regress/t/t_class_extends_param.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_extends_param.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_extends_param_unused.pl b/test_regress/t/t_class_extends_param_unused.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_class_extends_param_unused.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_extends_param_unused.py b/test_regress/t/t_class_extends_param_unused.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_extends_param_unused.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_extends_protect_ids.pl b/test_regress/t/t_class_extends_protect_ids.pl deleted file mode 100755 index c8b311329..000000000 --- a/test_regress/t/t_class_extends_protect_ids.pl +++ /dev/null @@ -1,33 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -# This test makes randomly named .cpp/.h files, which tend to collect, so remove them first -foreach my $filename (glob ("$Self->{obj_dir}/*_PS*.cpp" - . " $Self->{obj_dir}/*_PS*.h" - . " $Self->{obj_dir}/*.d" )) { - print "rm $filename\n" if $Self->{verbose}; - unlink $filename; -} - -top_filename("t/t_class_extends.v"); - -compile( - make_flags => 'VM_PARALLEL_BUILDS=1', # bug2775 - verilator_flags2 => ["--protect-ids", - "--protect-key SECRET_KEY"] - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_extends_protect_ids.py b/test_regress/t/t_class_extends_protect_ids.py new file mode 100755 index 000000000..f6fa53979 --- /dev/null +++ b/test_regress/t/t_class_extends_protect_ids.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_class_extends.v" + +# This test makes randomly named .cpp/.h files, which tend to collect, so remove them first +for filename in (glob.glob(test.obj_dir + "/*_PS*.cpp") + glob.glob(test.obj_dir + "/*_PS*.h") + + glob.glob(test.obj_dir + "/*.d")): + test.unlink_ok(filename) + +test.compile( + make_flags=['VM_PARALLEL_BUILDS=1'], # bug2775 + verilator_flags2=["--protect-ids", "--protect-key SECRET_KEY"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_extends_rec_bad.pl b/test_regress/t/t_class_extends_rec_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_class_extends_rec_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_extends_rec_bad.py b/test_regress/t/t_class_extends_rec_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_extends_rec_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_extends_this.pl b/test_regress/t/t_class_extends_this.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_class_extends_this.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_extends_this.py b/test_regress/t/t_class_extends_this.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_extends_this.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_extends_this3.pl b/test_regress/t/t_class_extends_this3.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_class_extends_this3.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_extends_this3.py b/test_regress/t/t_class_extends_this3.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_extends_this3.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_extends_this_protect_ids.pl b/test_regress/t/t_class_extends_this_protect_ids.pl deleted file mode 100755 index e9d578e68..000000000 --- a/test_regress/t/t_class_extends_this_protect_ids.pl +++ /dev/null @@ -1,32 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -# This test makes randomly named .cpp/.h files, which tend to collect, so remove them first -foreach my $filename (glob ("$Self->{obj_dir}/*_PS*.cpp" - . " $Self->{obj_dir}/*_PS*.h" - . " $Self->{obj_dir}/*.d" )) { - print "rm $filename\n" if $Self->{verbose}; - unlink $filename; -} - -top_filename("t/t_class_extends_this.v"); - -compile( - verilator_flags2 => ["--protect-ids", - "--protect-key SECRET_KEY"] - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_extends_this_protect_ids.py b/test_regress/t/t_class_extends_this_protect_ids.py new file mode 100755 index 000000000..8ed657472 --- /dev/null +++ b/test_regress/t/t_class_extends_this_protect_ids.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_class_extends_this.v" + +# This test makes randomly named .cpp/.h files, which tend to collect, so remove them first +for filename in (glob.glob(test.obj_dir + "/*_PS*.cpp") + glob.glob(test.obj_dir + "/*_PS*.h") + + glob.glob(test.obj_dir + "/*.d")): + test.unlink_ok(filename) + +test.compile(verilator_flags2=["--protect-ids", "--protect-key SECRET_KEY"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_extends_vsyment.pl b/test_regress/t/t_class_extends_vsyment.pl deleted file mode 100755 index 8eeb2a6f6..000000000 --- a/test_regress/t/t_class_extends_vsyment.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_extends_vsyment.py b/test_regress/t/t_class_extends_vsyment.py new file mode 100755 index 000000000..0b27c3dc0 --- /dev/null +++ b/test_regress/t/t_class_extends_vsyment.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_class_extern.pl b/test_regress/t/t_class_extern.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_class_extern.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_extern.py b/test_regress/t/t_class_extern.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_extern.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_extern_bad.pl b/test_regress/t/t_class_extern_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_class_extern_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_extern_bad.py b/test_regress/t/t_class_extern_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_extern_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_field_name.pl b/test_regress/t/t_class_field_name.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_class_field_name.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_field_name.py b/test_regress/t/t_class_field_name.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_field_name.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_format.pl b/test_regress/t/t_class_format.pl deleted file mode 100755 index ae71f01e3..000000000 --- a/test_regress/t/t_class_format.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_format.py b/test_regress/t/t_class_format.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_class_format.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_forward.pl b/test_regress/t/t_class_forward.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_class_forward.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_forward.py b/test_regress/t/t_class_forward.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_forward.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_func_arg_unused.pl b/test_regress/t/t_class_func_arg_unused.pl deleted file mode 100755 index e22e7f5d9..000000000 --- a/test_regress/t/t_class_func_arg_unused.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_func_arg_unused.py b/test_regress/t/t_class_func_arg_unused.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_func_arg_unused.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_func_dot.pl b/test_regress/t/t_class_func_dot.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_class_func_dot.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_func_dot.py b/test_regress/t/t_class_func_dot.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_func_dot.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_fwd_cc.pl b/test_regress/t/t_class_fwd_cc.pl deleted file mode 100755 index aca1cb3c1..000000000 --- a/test_regress/t/t_class_fwd_cc.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_fwd_cc.py b/test_regress/t/t_class_fwd_cc.py new file mode 100755 index 000000000..f81c3d68d --- /dev/null +++ b/test_regress/t/t_class_fwd_cc.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_class_if_assign.pl b/test_regress/t/t_class_if_assign.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_class_if_assign.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_if_assign.py b/test_regress/t/t_class_if_assign.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_if_assign.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_imp2.pl b/test_regress/t/t_class_imp2.pl deleted file mode 100755 index 3708008f8..000000000 --- a/test_regress/t/t_class_imp2.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_imp2.py b/test_regress/t/t_class_imp2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_imp2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_inc.pl b/test_regress/t/t_class_inc.pl deleted file mode 100755 index e22e7f5d9..000000000 --- a/test_regress/t/t_class_inc.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_inc.py b/test_regress/t/t_class_inc.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_inc.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_local.pl b/test_regress/t/t_class_local.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_class_local.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_local.py b/test_regress/t/t_class_local.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_local.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_local_bad.pl b/test_regress/t/t_class_local_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_class_local_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_local_bad.py b/test_regress/t/t_class_local_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_local_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_local_protect_ids.pl b/test_regress/t/t_class_local_protect_ids.pl deleted file mode 100755 index 9c7ba366c..000000000 --- a/test_regress/t/t_class_local_protect_ids.pl +++ /dev/null @@ -1,32 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -# This test makes randomly named .cpp/.h files, which tend to collect, so remove them first -foreach my $filename (glob ("$Self->{obj_dir}/*_PS*.cpp" - . " $Self->{obj_dir}/*_PS*.h" - . " $Self->{obj_dir}/*.d")) { - print "rm $filename\n" if $Self->{verbose}; - unlink $filename; -} - -top_filename("t/t_class_local.v"); - -compile( - verilator_flags2 => ["--protect-ids", - "--protect-key SECRET_KEY"] - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_local_protect_ids.py b/test_regress/t/t_class_local_protect_ids.py new file mode 100755 index 000000000..81b18d6cc --- /dev/null +++ b/test_regress/t/t_class_local_protect_ids.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_class_local.v" + +# This test makes randomly named .cpp/.h files, which tend to collect, so remove them first +for filename in (glob.glob(test.obj_dir + "/*_PS*.cpp") + glob.glob(test.obj_dir + "/*_PS*.h") + + glob.glob(test.obj_dir + "/*.d")): + test.unlink_ok(filename) + +test.compile(verilator_flags2=["--protect-ids", "--protect-key SECRET_KEY"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_member_bad.pl b/test_regress/t/t_class_member_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_class_member_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_member_bad.py b/test_regress/t/t_class_member_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_member_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_member_bad2.pl b/test_regress/t/t_class_member_bad2.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_class_member_bad2.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_member_bad2.py b/test_regress/t/t_class_member_bad2.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_member_bad2.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_member_sens.pl b/test_regress/t/t_class_member_sens.pl deleted file mode 100755 index 3f06e52ad..000000000 --- a/test_regress/t/t_class_member_sens.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - sanitize => 1, - ); - -execute( - aslr_off => 1, # Some GCC versions hit an address-sanitizer bug otherwise - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_member_sens.py b/test_regress/t/t_class_member_sens.py new file mode 100755 index 000000000..de7e2e82d --- /dev/null +++ b/test_regress/t/t_class_member_sens.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(sanitize=True) + +test.execute(aslr_off=True) # Some GCC versions hit an address-sanitizer bug otherwise) + +test.passes() diff --git a/test_regress/t/t_class_member_var_virt_bad.pl b/test_regress/t/t_class_member_var_virt_bad.pl deleted file mode 100755 index 376c2d2ee..000000000 --- a/test_regress/t/t_class_member_var_virt_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_member_var_virt_bad.py b/test_regress/t/t_class_member_var_virt_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_member_var_virt_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_membersel_int.pl b/test_regress/t/t_class_membersel_int.pl deleted file mode 100755 index e22e7f5d9..000000000 --- a/test_regress/t/t_class_membersel_int.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_membersel_int.py b/test_regress/t/t_class_membersel_int.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_membersel_int.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_method.pl b/test_regress/t/t_class_method.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_class_method.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_method.py b/test_regress/t/t_class_method.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_method.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_method_bad.pl b/test_regress/t/t_class_method_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_class_method_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_method_bad.py b/test_regress/t/t_class_method_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_method_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_method_str_literal.pl b/test_regress/t/t_class_method_str_literal.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_class_method_str_literal.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_method_str_literal.py b/test_regress/t/t_class_method_str_literal.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_method_str_literal.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_method_struct.pl b/test_regress/t/t_class_method_struct.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_class_method_struct.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_method_struct.py b/test_regress/t/t_class_method_struct.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_method_struct.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_mispure_bad.pl b/test_regress/t/t_class_mispure_bad.pl deleted file mode 100755 index 9c9fb65a0..000000000 --- a/test_regress/t/t_class_mispure_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_mispure_bad.py b/test_regress/t/t_class_mispure_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_mispure_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_misstatic_bad.pl b/test_regress/t/t_class_misstatic_bad.pl deleted file mode 100755 index 9c9fb65a0..000000000 --- a/test_regress/t/t_class_misstatic_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_misstatic_bad.py b/test_regress/t/t_class_misstatic_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_misstatic_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_mod_bad.pl b/test_regress/t/t_class_mod_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_class_mod_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_mod_bad.py b/test_regress/t/t_class_mod_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_mod_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_module.pl b/test_regress/t/t_class_module.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_class_module.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_module.py b/test_regress/t/t_class_module.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_module.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_name.pl b/test_regress/t/t_class_name.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_class_name.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_name.py b/test_regress/t/t_class_name.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_name.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_nested_link.pl b/test_regress/t/t_class_nested_link.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_class_nested_link.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_nested_link.py b/test_regress/t/t_class_nested_link.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_nested_link.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_new.pl b/test_regress/t/t_class_new.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_class_new.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_new.py b/test_regress/t/t_class_new.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_new.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_new_bad.pl b/test_regress/t/t_class_new_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_class_new_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_new_bad.py b/test_regress/t/t_class_new_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_new_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_new_default.pl b/test_regress/t/t_class_new_default.pl deleted file mode 100755 index 009248fc5..000000000 --- a/test_regress/t/t_class_new_default.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_new_default.py b/test_regress/t/t_class_new_default.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_class_new_default.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_new_noparen.pl b/test_regress/t/t_class_new_noparen.pl deleted file mode 100755 index e22e7f5d9..000000000 --- a/test_regress/t/t_class_new_noparen.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_new_noparen.py b/test_regress/t/t_class_new_noparen.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_new_noparen.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_new_ref_bad.pl b/test_regress/t/t_class_new_ref_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_class_new_ref_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_new_ref_bad.py b/test_regress/t/t_class_new_ref_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_new_ref_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_new_return.pl b/test_regress/t/t_class_new_return.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_class_new_return.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_new_return.py b/test_regress/t/t_class_new_return.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_new_return.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_new_this.pl b/test_regress/t/t_class_new_this.pl deleted file mode 100755 index 3708008f8..000000000 --- a/test_regress/t/t_class_new_this.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_new_this.py b/test_regress/t/t_class_new_this.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_new_this.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_null_bad.pl b/test_regress/t/t_class_null_bad.pl deleted file mode 100755 index 8b1946a7b..000000000 --- a/test_regress/t/t_class_null_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_null_bad.py b/test_regress/t/t_class_null_bad.py new file mode 100755 index 000000000..2fdd6e92d --- /dev/null +++ b/test_regress/t/t_class_null_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_null_struct.pl b/test_regress/t/t_class_null_struct.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_class_null_struct.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_null_struct.py b/test_regress/t/t_class_null_struct.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_null_struct.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_override.pl b/test_regress/t/t_class_override.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_class_override.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_override.py b/test_regress/t/t_class_override.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_override.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_override_bad.pl b/test_regress/t/t_class_override_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_class_override_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_override_bad.py b/test_regress/t/t_class_override_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_override_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_package.pl b/test_regress/t/t_class_package.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_class_package.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_package.py b/test_regress/t/t_class_package.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_package.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_packed.pl b/test_regress/t/t_class_packed.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_class_packed.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_packed.py b/test_regress/t/t_class_packed.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_packed.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_param.pl b/test_regress/t/t_class_param.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_class_param.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param.py b/test_regress/t/t_class_param.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_param.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_param_bad1.pl b/test_regress/t/t_class_param_bad1.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_class_param_bad1.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_bad1.py b/test_regress/t/t_class_param_bad1.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_param_bad1.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_param_bad2.pl b/test_regress/t/t_class_param_bad2.pl deleted file mode 100755 index 44783b1f6..000000000 --- a/test_regress/t/t_class_param_bad2.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_bad2.py b/test_regress/t/t_class_param_bad2.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_param_bad2.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_param_bad_paren.pl b/test_regress/t/t_class_param_bad_paren.pl deleted file mode 100755 index 44783b1f6..000000000 --- a/test_regress/t/t_class_param_bad_paren.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_bad_paren.py b/test_regress/t/t_class_param_bad_paren.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_param_bad_paren.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_param_circ_bad.pl b/test_regress/t/t_class_param_circ_bad.pl deleted file mode 100755 index c35c8bc93..000000000 --- a/test_regress/t/t_class_param_circ_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_circ_bad.py b/test_regress/t/t_class_param_circ_bad.py new file mode 100755 index 000000000..efe8cc01c --- /dev/null +++ b/test_regress/t/t_class_param_circ_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_param_comma_bad.pl b/test_regress/t/t_class_param_comma_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_class_param_comma_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_comma_bad.py b/test_regress/t/t_class_param_comma_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_param_comma_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_param_enum.pl b/test_regress/t/t_class_param_enum.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_class_param_enum.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_enum.py b/test_regress/t/t_class_param_enum.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_param_enum.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_param_enum_bad.pl b/test_regress/t/t_class_param_enum_bad.pl deleted file mode 100755 index c35c8bc93..000000000 --- a/test_regress/t/t_class_param_enum_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_enum_bad.py b/test_regress/t/t_class_param_enum_bad.py new file mode 100755 index 000000000..efe8cc01c --- /dev/null +++ b/test_regress/t/t_class_param_enum_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_param_extends.pl b/test_regress/t/t_class_param_extends.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_class_param_extends.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_extends.py b/test_regress/t/t_class_param_extends.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_param_extends.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_param_extends2.pl b/test_regress/t/t_class_param_extends2.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_class_param_extends2.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_extends2.py b/test_regress/t/t_class_param_extends2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_param_extends2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_param_extends3.pl b/test_regress/t/t_class_param_extends3.pl deleted file mode 100755 index e22e7f5d9..000000000 --- a/test_regress/t/t_class_param_extends3.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_extends3.py b/test_regress/t/t_class_param_extends3.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_param_extends3.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_param_func_return.pl b/test_regress/t/t_class_param_func_return.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_class_param_func_return.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_func_return.py b/test_regress/t/t_class_param_func_return.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_param_func_return.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_param_lvalue.pl b/test_regress/t/t_class_param_lvalue.pl deleted file mode 100755 index 13587bf85..000000000 --- a/test_regress/t/t_class_param_lvalue.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_lvalue.py b/test_regress/t/t_class_param_lvalue.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_class_param_lvalue.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_class_param_mod.pl b/test_regress/t/t_class_param_mod.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_class_param_mod.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_mod.py b/test_regress/t/t_class_param_mod.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_param_mod.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_param_nconst_bad.pl b/test_regress/t/t_class_param_nconst_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_class_param_nconst_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_nconst_bad.py b/test_regress/t/t_class_param_nconst_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_param_nconst_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_param_nested_bad.pl b/test_regress/t/t_class_param_nested_bad.pl deleted file mode 100755 index c35c8bc93..000000000 --- a/test_regress/t/t_class_param_nested_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_nested_bad.py b/test_regress/t/t_class_param_nested_bad.py new file mode 100755 index 000000000..efe8cc01c --- /dev/null +++ b/test_regress/t/t_class_param_nested_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_param_noinit.pl b/test_regress/t/t_class_param_noinit.pl deleted file mode 100755 index e22e7f5d9..000000000 --- a/test_regress/t/t_class_param_noinit.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_noinit.py b/test_regress/t/t_class_param_noinit.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_param_noinit.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_param_noinit_bad.pl b/test_regress/t/t_class_param_noinit_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_class_param_noinit_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_noinit_bad.py b/test_regress/t/t_class_param_noinit_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_param_noinit_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_param_override_local_bad.pl b/test_regress/t/t_class_param_override_local_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_class_param_override_local_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_override_local_bad.py b/test_regress/t/t_class_param_override_local_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_class_param_override_local_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_param_pkg.pl b/test_regress/t/t_class_param_pkg.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_class_param_pkg.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_pkg.py b/test_regress/t/t_class_param_pkg.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_param_pkg.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_param_subtype_bad_paren.pl b/test_regress/t/t_class_param_subtype_bad_paren.pl deleted file mode 100755 index 13944a9e5..000000000 --- a/test_regress/t/t_class_param_subtype_bad_paren.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -top_filename("t/t_class_param_subtype.v"); - -lint( - fails => 1, - v_flags2 => ['+define+BAD_PAREN'], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_subtype_bad_paren.py b/test_regress/t/t_class_param_subtype_bad_paren.py new file mode 100755 index 000000000..6b8a1cf07 --- /dev/null +++ b/test_regress/t/t_class_param_subtype_bad_paren.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_class_param_subtype.v" + +test.lint(fails=True, v_flags2=['+define+BAD_PAREN'], expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_param_subtype_constsim.pl b/test_regress/t/t_class_param_subtype_constsim.pl deleted file mode 100755 index 7eb36922e..000000000 --- a/test_regress/t/t_class_param_subtype_constsim.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_class_param_subtype.v"); - -compile( - v_flags2 => ['+define+CONSTSIM'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_subtype_constsim.py b/test_regress/t/t_class_param_subtype_constsim.py new file mode 100755 index 000000000..cc356de23 --- /dev/null +++ b/test_regress/t/t_class_param_subtype_constsim.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_class_param_subtype.v" + +test.compile(v_flags2=['+define+CONSTSIM']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_param_type.pl b/test_regress/t/t_class_param_type.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_class_param_type.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_type.py b/test_regress/t/t_class_param_type.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_param_type.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_param_typedef.pl b/test_regress/t/t_class_param_typedef.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_class_param_typedef.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_typedef.py b/test_regress/t/t_class_param_typedef.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_param_typedef.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_param_typedef2.pl b/test_regress/t/t_class_param_typedef2.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_class_param_typedef2.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_typedef2.py b/test_regress/t/t_class_param_typedef2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_param_typedef2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_param_unused_default.pl b/test_regress/t/t_class_param_unused_default.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_class_param_unused_default.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_unused_default.py b/test_regress/t/t_class_param_unused_default.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_param_unused_default.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_param_virtual_bad.pl b/test_regress/t/t_class_param_virtual_bad.pl deleted file mode 100755 index 009248fc5..000000000 --- a/test_regress/t/t_class_param_virtual_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_param_virtual_bad.py b/test_regress/t/t_class_param_virtual_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_class_param_virtual_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_ref_as_arg_cast.pl b/test_regress/t/t_class_ref_as_arg_cast.pl deleted file mode 100755 index 8c2ca139b..000000000 --- a/test_regress/t/t_class_ref_as_arg_cast.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_ref_as_arg_cast.py b/test_regress/t/t_class_ref_as_arg_cast.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_class_ref_as_arg_cast.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_class_short_circuit.pl b/test_regress/t/t_class_short_circuit.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_class_short_circuit.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_short_circuit.py b/test_regress/t/t_class_short_circuit.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_short_circuit.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_split.pl b/test_regress/t/t_class_split.pl deleted file mode 100755 index 622e28033..000000000 --- a/test_regress/t/t_class_split.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--output-split 10'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_split.py b/test_regress/t/t_class_split.py new file mode 100755 index 000000000..628bb8901 --- /dev/null +++ b/test_regress/t/t_class_split.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--output-split 10']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_static.pl b/test_regress/t/t_class_static.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_class_static.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_static.py b/test_regress/t/t_class_static.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_static.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_static_member.pl b/test_regress/t/t_class_static_member.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_class_static_member.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_static_member.py b/test_regress/t/t_class_static_member.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_static_member.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_static_member_pkg.pl b/test_regress/t/t_class_static_member_pkg.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_class_static_member_pkg.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_static_member_pkg.py b/test_regress/t/t_class_static_member_pkg.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_static_member_pkg.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_static_member_sel.pl b/test_regress/t/t_class_static_member_sel.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_class_static_member_sel.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_static_member_sel.py b/test_regress/t/t_class_static_member_sel.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_static_member_sel.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_static_method.pl b/test_regress/t/t_class_static_method.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_class_static_method.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_static_method.py b/test_regress/t/t_class_static_method.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_static_method.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_static_method_protect_ids.pl b/test_regress/t/t_class_static_method_protect_ids.pl deleted file mode 100755 index 355c2140c..000000000 --- a/test_regress/t/t_class_static_method_protect_ids.pl +++ /dev/null @@ -1,32 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -# This test makes randomly named .cpp/.h files, which tend to collect, so remove them first -foreach my $filename (glob ("$Self->{obj_dir}/*_PS*.cpp" - . " $Self->{obj_dir}/*_PS*.h" - . " $Self->{obj_dir}/*.d")) { - print "rm $filename\n" if $Self->{verbose}; - unlink $filename; -} - -top_filename("t/t_class_static_method.v"); - -compile( - verilator_flags2 => ["--protect-ids", - "--protect-key SECRET_KEY"] - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_static_method_protect_ids.py b/test_regress/t/t_class_static_method_protect_ids.py new file mode 100755 index 000000000..955f1a347 --- /dev/null +++ b/test_regress/t/t_class_static_method_protect_ids.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_class_static_method.v" + +# This test makes randomly named .cpp/.h files, which tend to collect, so remove them first +for filename in (glob.glob(test.obj_dir + "/*_PS*.cpp") + glob.glob(test.obj_dir + "/*_PS*.h") + + glob.glob(test.obj_dir + "/*.d")): + test.unlink_ok(filename) + +test.compile(verilator_flags2=["--protect-ids", "--protect-key SECRET_KEY"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_static_order.pl b/test_regress/t/t_class_static_order.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_class_static_order.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_static_order.py b/test_regress/t/t_class_static_order.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_static_order.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_super_bad.pl b/test_regress/t/t_class_super_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_class_super_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_super_bad.py b/test_regress/t/t_class_super_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_super_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_super_bad2.pl b/test_regress/t/t_class_super_bad2.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_class_super_bad2.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_super_bad2.py b/test_regress/t/t_class_super_bad2.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_super_bad2.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_super_new.pl b/test_regress/t/t_class_super_new.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_class_super_new.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_super_new.py b/test_regress/t/t_class_super_new.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_super_new.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_super_new2.pl b/test_regress/t/t_class_super_new2.pl deleted file mode 100755 index e22e7f5d9..000000000 --- a/test_regress/t/t_class_super_new2.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_super_new2.py b/test_regress/t/t_class_super_new2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_super_new2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_super_new_bad_nfirst.pl b/test_regress/t/t_class_super_new_bad_nfirst.pl deleted file mode 100755 index 44783b1f6..000000000 --- a/test_regress/t/t_class_super_new_bad_nfirst.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_super_new_bad_nfirst.py b/test_regress/t/t_class_super_new_bad_nfirst.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_super_new_bad_nfirst.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_this_constructor.pl b/test_regress/t/t_class_this_constructor.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_class_this_constructor.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_this_constructor.py b/test_regress/t/t_class_this_constructor.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_this_constructor.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_typedef.pl b/test_regress/t/t_class_typedef.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_class_typedef.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_typedef.py b/test_regress/t/t_class_typedef.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_typedef.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_unsup_bad.pl b/test_regress/t/t_class_unsup_bad.pl deleted file mode 100755 index 009248fc5..000000000 --- a/test_regress/t/t_class_unsup_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_unsup_bad.py b/test_regress/t/t_class_unsup_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_class_unsup_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_uses_this.pl b/test_regress/t/t_class_uses_this.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_class_uses_this.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_uses_this.py b/test_regress/t/t_class_uses_this.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_uses_this.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_uses_this_bad.pl b/test_regress/t/t_class_uses_this_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_class_uses_this_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_uses_this_bad.py b/test_regress/t/t_class_uses_this_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_class_uses_this_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_virtual.pl b/test_regress/t/t_class_virtual.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_class_virtual.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_virtual.py b/test_regress/t/t_class_virtual.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_virtual.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_virtual_bad.pl b/test_regress/t/t_class_virtual_bad.pl deleted file mode 100755 index 009248fc5..000000000 --- a/test_regress/t/t_class_virtual_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_virtual_bad.py b/test_regress/t/t_class_virtual_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_class_virtual_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_virtual_chain_ctor.pl b/test_regress/t/t_class_virtual_chain_ctor.pl deleted file mode 100755 index 5b8136393..000000000 --- a/test_regress/t/t_class_virtual_chain_ctor.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_class_virtual_chain_ctor.py b/test_regress/t/t_class_virtual_chain_ctor.py new file mode 100755 index 000000000..f81c3d68d --- /dev/null +++ b/test_regress/t/t_class_virtual_chain_ctor.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_class_virtual_protect_ids.pl b/test_regress/t/t_class_virtual_protect_ids.pl deleted file mode 100755 index c55d84b2e..000000000 --- a/test_regress/t/t_class_virtual_protect_ids.pl +++ /dev/null @@ -1,32 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -# This test makes randomly named .cpp/.h files, which tend to collect, so remove them first -foreach my $filename (glob ("$Self->{obj_dir}/*_PS*.cpp" - . " $Self->{obj_dir}/*_PS*.h" - . " $Self->{obj_dir}/*.d")) { - print "rm $filename\n" if $Self->{verbose}; - unlink $filename; -} - -top_filename("t/t_class_virtual.v"); - -compile( - verilator_flags2 => ["--protect-ids", - "--protect-key SECRET_KEY"] - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_virtual_protect_ids.py b/test_regress/t/t_class_virtual_protect_ids.py new file mode 100755 index 000000000..b42e1e842 --- /dev/null +++ b/test_regress/t/t_class_virtual_protect_ids.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_class_virtual.v" + +# This test makes randomly named .cpp/.h files, which tend to collect, so remove them first +for filename in (glob.glob(test.obj_dir + "/*_PS*.cpp") + glob.glob(test.obj_dir + "/*_PS*.h") + + glob.glob(test.obj_dir + "/*.d")): + test.unlink_ok(filename) + +test.compile(verilator_flags2=["--protect-ids", "--protect-key SECRET_KEY"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_virtual_pure.pl b/test_regress/t/t_class_virtual_pure.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_class_virtual_pure.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_virtual_pure.py b/test_regress/t/t_class_virtual_pure.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_virtual_pure.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_virtual_pure_bad.pl b/test_regress/t/t_class_virtual_pure_bad.pl deleted file mode 100755 index 009248fc5..000000000 --- a/test_regress/t/t_class_virtual_pure_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_virtual_pure_bad.py b/test_regress/t/t_class_virtual_pure_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_class_virtual_pure_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_vparam.pl b/test_regress/t/t_class_vparam.pl deleted file mode 100755 index 5a84db80d..000000000 --- a/test_regress/t/t_class_vparam.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_vparam.py b/test_regress/t/t_class_vparam.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_vparam.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_wide.pl b/test_regress/t/t_class_wide.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_class_wide.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_class_wide.py b/test_regress/t/t_class_wide.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_class_wide.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clk_2in.pl b/test_regress/t/t_clk_2in.pl deleted file mode 100755 index 76c7a9459..000000000 --- a/test_regress/t/t_clk_2in.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe", "$Self->{t_dir}/$Self->{name}.cpp"], - vcs_flags2 => ['-assert'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_2in.py b/test_regress/t/t_clk_2in.py new file mode 100755 index 000000000..69b0d367c --- /dev/null +++ b/test_regress/t/t_clk_2in.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--exe", test.pli_filename], + vcs_flags2=['-assert']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clk_2in_vec.pl b/test_regress/t/t_clk_2in_vec.pl deleted file mode 100755 index 4cd9d0b10..000000000 --- a/test_regress/t/t_clk_2in_vec.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_clk_2in.v"); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ["+define+T_CLK_2IN_VEC=1"], - verilator_flags2 => ["--exe $Self->{t_dir}/t_clk_2in.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_2in_vec.py b/test_regress/t/t_clk_2in_vec.py new file mode 100755 index 000000000..5939f11bf --- /dev/null +++ b/test_regress/t/t_clk_2in_vec.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_clk_2in.cpp" +test.top_filename = "t/t_clk_2in.v" + +test.compile(make_top_shell=False, + make_main=False, + v_flags2=["+define+T_CLK_2IN_VEC=1"], + verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clk_concat.pl b/test_regress/t/t_clk_concat.pl deleted file mode 100755 index d368bec92..000000000 --- a/test_regress/t/t_clk_concat.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - verilator_flags2 => ["+define+ATTRIBUTES --no-json-edit-nums"], - ); - -if ($Self->{vlt_all}) { - file_grep("$out_filename", qr/{"type":"VAR","name":"clk0",.*"loc":"e,74:[^"]*",.*"origName":"clk0",.*"direction":"INPUT",.*"isSigPublic":true,.*"attrClocker":"clker",.*"varType":"PORT",.*"dtypeName":"logic"/); - file_grep("$out_filename", qr/{"type":"VAR","name":"clk1",.*"loc":"e,75:[^"]*",.*"origName":"clk1",.*"direction":"INPUT",.*"isSigPublic":true,.*"attrClocker":"clker",.*"varType":"PORT",.*"dtypeName":"logic"/); - file_grep("$out_filename", qr/{"type":"VAR","name":"clk2",.*"loc":"e,76:[^"]*",.*"origName":"clk2",.*"direction":"INPUT",.*"isSigPublic":true,.*"attrClocker":"clker",.*"varType":"PORT",.*"dtypeName":"logic"/); -} - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_concat.py b/test_regress/t/t_clk_concat.py new file mode 100755 index 000000000..66ab4b571 --- /dev/null +++ b/test_regress/t/t_clk_concat.py @@ -0,0 +1,34 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(verilator_flags2=["+define+ATTRIBUTES --no-json-edit-nums"]) + +if test.vlt_all: + test.file_grep( + out_filename, + r'{"type":"VAR","name":"clk0",.*"loc":"e,74:[^"]*",.*"origName":"clk0",.*"direction":"INPUT",.*"isSigPublic":true,.*"attrClocker":"clker",.*"varType":"PORT",.*"dtypeName":"logic"' + ) + test.file_grep( + out_filename, + r'{"type":"VAR","name":"clk1",.*"loc":"e,75:[^"]*",.*"origName":"clk1",.*"direction":"INPUT",.*"isSigPublic":true,.*"attrClocker":"clker",.*"varType":"PORT",.*"dtypeName":"logic"' + ) + test.file_grep( + out_filename, + r'{"type":"VAR","name":"clk2",.*"loc":"e,76:[^"]*",.*"origName":"clk2",.*"direction":"INPUT",.*"isSigPublic":true,.*"attrClocker":"clker",.*"varType":"PORT",.*"dtypeName":"logic"' + ) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clk_concat2.pl b/test_regress/t/t_clk_concat2.pl deleted file mode 100755 index 72847408e..000000000 --- a/test_regress/t/t_clk_concat2.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_concat2.py b/test_regress/t/t_clk_concat2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_clk_concat2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clk_concat3.pl b/test_regress/t/t_clk_concat3.pl deleted file mode 100755 index 72847408e..000000000 --- a/test_regress/t/t_clk_concat3.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_concat3.py b/test_regress/t/t_clk_concat3.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_clk_concat3.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clk_concat4.pl b/test_regress/t/t_clk_concat4.pl deleted file mode 100755 index 72847408e..000000000 --- a/test_regress/t/t_clk_concat4.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_concat4.py b/test_regress/t/t_clk_concat4.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_clk_concat4.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clk_concat5.pl b/test_regress/t/t_clk_concat5.pl deleted file mode 100755 index 72847408e..000000000 --- a/test_regress/t/t_clk_concat5.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_concat5.py b/test_regress/t/t_clk_concat5.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_clk_concat5.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clk_concat6.pl b/test_regress/t/t_clk_concat6.pl deleted file mode 100755 index 72847408e..000000000 --- a/test_regress/t/t_clk_concat6.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_concat6.py b/test_regress/t/t_clk_concat6.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_clk_concat6.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clk_concat_vlt.pl b/test_regress/t/t_clk_concat_vlt.pl deleted file mode 100755 index 6839c65f2..000000000 --- a/test_regress/t/t_clk_concat_vlt.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_clk_concat.v"); -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - verilator_flags2 => ["--no-json-edit-nums", "t/t_clk_concat.vlt"], - ); - -if ($Self->{vlt_all}) { - file_grep("$out_filename", qr/{"type":"VAR","name":"clk0",.*"loc":"f,78:[^"]*",.*"origName":"clk0",.*"direction":"INPUT",.*"isSigPublic":true,.*"attrClocker":"clker",.*"varType":"PORT",.*"dtypeName":"logic"/); - file_grep("$out_filename", qr/{"type":"VAR","name":"clk1",.*"loc":"f,79:[^"]*",.*"origName":"clk1",.*"direction":"INPUT",.*"isSigPublic":true,.*"attrClocker":"clker",.*"varType":"PORT",.*"dtypeName":"logic"/); - file_grep("$out_filename", qr/{"type":"VAR","name":"clk2",.*"loc":"f,80:[^"]*",.*"origName":"clk2",.*"direction":"INPUT",.*"isSigPublic":true,.*"attrClocker":"clker",.*"varType":"PORT",.*"dtypeName":"logic"/); - file_grep("$out_filename", qr/{"type":"VAR","name":"data_in",.*"loc":"f,82:[^"]*",.*"origName":"data_in",.*"direction":"INPUT",.*"isSigPublic":true,.*"attrClocker":"non_clker",.*"varType":"PORT",.*"dtypeName":"logic"/); -} - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_concat_vlt.py b/test_regress/t/t_clk_concat_vlt.py new file mode 100755 index 000000000..b634813cc --- /dev/null +++ b/test_regress/t/t_clk_concat_vlt.py @@ -0,0 +1,39 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_clk_concat.v" + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(verilator_flags2=["--no-json-edit-nums", "t/t_clk_concat.vlt"]) + +if test.vlt_all: + test.file_grep( + out_filename, + r'{"type":"VAR","name":"clk0",.*"loc":"f,78:[^"]*",.*"origName":"clk0",.*"direction":"INPUT",.*"isSigPublic":true,.*"attrClocker":"clker",.*"varType":"PORT",.*"dtypeName":"logic"' + ) + test.file_grep( + out_filename, + r'{"type":"VAR","name":"clk1",.*"loc":"f,79:[^"]*",.*"origName":"clk1",.*"direction":"INPUT",.*"isSigPublic":true,.*"attrClocker":"clker",.*"varType":"PORT",.*"dtypeName":"logic"' + ) + test.file_grep( + out_filename, + r'{"type":"VAR","name":"clk2",.*"loc":"f,80:[^"]*",.*"origName":"clk2",.*"direction":"INPUT",.*"isSigPublic":true,.*"attrClocker":"clker",.*"varType":"PORT",.*"dtypeName":"logic"' + ) + test.file_grep( + out_filename, + r'{"type":"VAR","name":"data_in",.*"loc":"f,82:[^"]*",.*"origName":"data_in",.*"direction":"INPUT",.*"isSigPublic":true,.*"attrClocker":"non_clker",.*"varType":"PORT",.*"dtypeName":"logic"' + ) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clk_condflop.pl b/test_regress/t/t_clk_condflop.pl deleted file mode 100755 index 72847408e..000000000 --- a/test_regress/t/t_clk_condflop.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_condflop.py b/test_regress/t/t_clk_condflop.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_clk_condflop.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clk_dpulse.pl b/test_regress/t/t_clk_dpulse.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_clk_dpulse.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_dpulse.py b/test_regress/t/t_clk_dpulse.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_clk_dpulse.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clk_dsp.pl b/test_regress/t/t_clk_dsp.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_clk_dsp.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_dsp.py b/test_regress/t/t_clk_dsp.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_clk_dsp.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clk_first.pl b/test_regress/t/t_clk_first.pl deleted file mode 100755 index d432d4358..000000000 --- a/test_regress/t/t_clk_first.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - verilator_flags2 => ["+define+ATTRIBUTES=1"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_first.py b/test_regress/t/t_clk_first.py new file mode 100755 index 000000000..88dfd68d3 --- /dev/null +++ b/test_regress/t/t_clk_first.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["+define+ATTRIBUTES=1"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clk_first_bad.pl b/test_regress/t/t_clk_first_bad.pl deleted file mode 100755 index 7061aebc4..000000000 --- a/test_regress/t/t_clk_first_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_clk_first_deprecated.v"); - -lint( - verilator_flags2 => ["--lint-only"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_first_bad.py b/test_regress/t/t_clk_first_bad.py new file mode 100755 index 000000000..d6fa215bd --- /dev/null +++ b/test_regress/t/t_clk_first_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_clk_first_deprecated.v" + +test.lint(verilator_flags2=["--lint-only"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_clk_first_deprecated.pl b/test_regress/t/t_clk_first_deprecated.pl deleted file mode 100755 index 600551635..000000000 --- a/test_regress/t/t_clk_first_deprecated.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only", "-Wno-DEPRECATED"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_first_deprecated.py b/test_regress/t/t_clk_first_deprecated.py new file mode 100755 index 000000000..c6aee9ea5 --- /dev/null +++ b/test_regress/t/t_clk_first_deprecated.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only", "-Wno-DEPRECATED"]) + +test.passes() diff --git a/test_regress/t/t_clk_gate_ext.pl b/test_regress/t/t_clk_gate_ext.pl deleted file mode 100755 index 56363dab6..000000000 --- a/test_regress/t/t_clk_gate_ext.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_gate_ext.py b/test_regress/t/t_clk_gate_ext.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_clk_gate_ext.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clk_gater.pl b/test_regress/t/t_clk_gater.pl deleted file mode 100755 index 8aa5977f9..000000000 --- a/test_regress/t/t_clk_gater.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--stats", - $Self->wno_unopthreads_for_few_cores()] - ); - -execute( - ); - -if ($Self->{vlt_all}) { - #Optimization is disabled - #file_grep ($Self->{stats}, qr/Optimizations, Gaters inserted\s+(\d+)/, 3); -} - -ok(1); -1; diff --git a/test_regress/t/t_clk_gater.py b/test_regress/t/t_clk_gater.py new file mode 100755 index 000000000..507391524 --- /dev/null +++ b/test_regress/t/t_clk_gater.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats", test.wno_unopthreads_for_few_cores]) + +test.execute() + +#Optimization is disabled +#test.file_grep(test.stats, r'Optimizations, Gaters inserted\s+(\d+)'i, 3) + +test.passes() diff --git a/test_regress/t/t_clk_gen.pl b/test_regress/t/t_clk_gen.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_clk_gen.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_gen.py b/test_regress/t/t_clk_gen.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_clk_gen.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clk_inp_init.pl b/test_regress/t/t_clk_inp_init.pl deleted file mode 100755 index 76ac18c8e..000000000 --- a/test_regress/t/t_clk_inp_init.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2018 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the -# GNU Lesser General Public License Version 3 or the Perl Artistic -# License Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile(make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"]); - -execute(); - -ok(1); -1; diff --git a/test_regress/t/t_clk_inp_init.py b/test_regress/t/t_clk_inp_init.py new file mode 100755 index 000000000..f840b04dc --- /dev/null +++ b/test_regress/t/t_clk_inp_init.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the +# GNU Lesser General Public License Version 3 or the Perl Artistic +# License Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clk_latch.pl b/test_regress/t/t_clk_latch.pl deleted file mode 100755 index 72847408e..000000000 --- a/test_regress/t/t_clk_latch.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_latch.py b/test_regress/t/t_clk_latch.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_clk_latch.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clk_latch_edgestyle.pl b/test_regress/t/t_clk_latch_edgestyle.pl deleted file mode 100755 index 9d5407406..000000000 --- a/test_regress/t/t_clk_latch_edgestyle.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_clk_latch.v"); - - -compile( - v_flags2 => ['+define+EDGE_DETECT_STYLE'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_latch_edgestyle.py b/test_regress/t/t_clk_latch_edgestyle.py new file mode 100755 index 000000000..395d09419 --- /dev/null +++ b/test_regress/t/t_clk_latch_edgestyle.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_clk_latch.v" + +test.compile(v_flags2=['+define+EDGE_DETECT_STYLE']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clk_latchgate.pl b/test_regress/t/t_clk_latchgate.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_clk_latchgate.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_latchgate.py b/test_regress/t/t_clk_latchgate.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_clk_latchgate.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clk_powerdn.pl b/test_regress/t/t_clk_powerdn.pl deleted file mode 100755 index 72847408e..000000000 --- a/test_regress/t/t_clk_powerdn.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_powerdn.py b/test_regress/t/t_clk_powerdn.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_clk_powerdn.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clk_scope_bad.pl b/test_regress/t/t_clk_scope_bad.pl deleted file mode 100755 index cc34dc85f..000000000 --- a/test_regress/t/t_clk_scope_bad.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_clk_scope_bad.py b/test_regress/t/t_clk_scope_bad.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_clk_scope_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_clk_vecgen1.pl b/test_regress/t/t_clk_vecgen1.pl deleted file mode 100755 index a492c0fef..000000000 --- a/test_regress/t/t_clk_vecgen1.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_clk_vecgen1.v"); - -compile( - v_flags2 => ['+define+T_TEST1',], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_vecgen1.py b/test_regress/t/t_clk_vecgen1.py new file mode 100755 index 000000000..12a6cc2e5 --- /dev/null +++ b/test_regress/t/t_clk_vecgen1.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_clk_vecgen1.v" + +test.compile(v_flags2=['+define+T_TEST1']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clk_vecgen2.pl b/test_regress/t/t_clk_vecgen2.pl deleted file mode 100755 index 6c97739ae..000000000 --- a/test_regress/t/t_clk_vecgen2.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_clk_vecgen1.v"); - -compile( - v_flags2 => ['+define+T_TEST2',], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_vecgen2.py b/test_regress/t/t_clk_vecgen2.py new file mode 100755 index 000000000..6c46e2c7c --- /dev/null +++ b/test_regress/t/t_clk_vecgen2.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_clk_vecgen1.v" + +test.compile(v_flags2=['+define+T_TEST2']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clk_vecgen3.pl b/test_regress/t/t_clk_vecgen3.pl deleted file mode 100755 index 83795701c..000000000 --- a/test_regress/t/t_clk_vecgen3.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_clk_vecgen1.v"); - -compile( - v_flags2 => ['+define+T_TEST3',], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_clk_vecgen3.py b/test_regress/t/t_clk_vecgen3.py new file mode 100755 index 000000000..7e8939ce1 --- /dev/null +++ b/test_regress/t/t_clk_vecgen3.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_clk_vecgen1.v" + +test.compile(v_flags2=['+define+T_TEST3']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clocked_release_combo.pl b/test_regress/t/t_clocked_release_combo.pl deleted file mode 100755 index e22e7f5d9..000000000 --- a/test_regress/t/t_clocked_release_combo.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_clocked_release_combo.py b/test_regress/t/t_clocked_release_combo.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_clocked_release_combo.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clocker.pl b/test_regress/t/t_clocker.pl deleted file mode 100755 index b5a64c09f..000000000 --- a/test_regress/t/t_clocker.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--trace"] - ); - -execute( - ); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_clocker.py b/test_regress/t/t_clocker.py new file mode 100755 index 000000000..b03987abd --- /dev/null +++ b/test_regress/t/t_clocker.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--trace"]) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_clocking_bad1.pl b/test_regress/t/t_clocking_bad1.pl deleted file mode 100755 index 8ab3c0995..000000000 --- a/test_regress/t/t_clocking_bad1.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--timing"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_clocking_bad1.py b/test_regress/t/t_clocking_bad1.py new file mode 100755 index 000000000..7bf848e53 --- /dev/null +++ b/test_regress/t/t_clocking_bad1.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--timing"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_clocking_bad2.pl b/test_regress/t/t_clocking_bad2.pl deleted file mode 100755 index 8ab3c0995..000000000 --- a/test_regress/t/t_clocking_bad2.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--timing"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_clocking_bad2.py b/test_regress/t/t_clocking_bad2.py new file mode 100755 index 000000000..7bf848e53 --- /dev/null +++ b/test_regress/t/t_clocking_bad2.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--timing"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_clocking_bad3.pl b/test_regress/t/t_clocking_bad3.pl deleted file mode 100755 index 8ab3c0995..000000000 --- a/test_regress/t/t_clocking_bad3.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--timing"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_clocking_bad3.py b/test_regress/t/t_clocking_bad3.py new file mode 100755 index 000000000..7bf848e53 --- /dev/null +++ b/test_regress/t/t_clocking_bad3.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--timing"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_clocking_bad4.pl b/test_regress/t/t_clocking_bad4.pl deleted file mode 100755 index 8ab3c0995..000000000 --- a/test_regress/t/t_clocking_bad4.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--timing"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_clocking_bad4.py b/test_regress/t/t_clocking_bad4.py new file mode 100755 index 000000000..7bf848e53 --- /dev/null +++ b/test_regress/t/t_clocking_bad4.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--timing"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_clocking_bad5.pl b/test_regress/t/t_clocking_bad5.pl deleted file mode 100755 index 7fdfc93e0..000000000 --- a/test_regress/t/t_clocking_bad5.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--timing"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_clocking_bad5.py b/test_regress/t/t_clocking_bad5.py new file mode 100755 index 000000000..7bf848e53 --- /dev/null +++ b/test_regress/t/t_clocking_bad5.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--timing"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_clocking_concat.pl b/test_regress/t/t_clocking_concat.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_clocking_concat.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_clocking_concat.py b/test_regress/t/t_clocking_concat.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_clocking_concat.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clocking_empty_block.pl b/test_regress/t/t_clocking_empty_block.pl deleted file mode 100755 index 21a2189cc..000000000 --- a/test_regress/t/t_clocking_empty_block.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_clocking_empty_block.py b/test_regress/t/t_clocking_empty_block.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_clocking_empty_block.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clocking_inout.pl b/test_regress/t/t_clocking_inout.pl deleted file mode 100755 index ceff37cca..000000000 --- a/test_regress/t/t_clocking_inout.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - make_main => 0, - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_clocking_inout.py b/test_regress/t/t_clocking_inout.py new file mode 100755 index 000000000..d05629d98 --- /dev/null +++ b/test_regress/t/t_clocking_inout.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"], make_main=False) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clocking_notiming.pl b/test_regress/t/t_clocking_notiming.pl deleted file mode 100755 index bf475c910..000000000 --- a/test_regress/t/t_clocking_notiming.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint( - verilator_flags2 => ["--no-timing"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_clocking_notiming.py b/test_regress/t/t_clocking_notiming.py new file mode 100755 index 000000000..6f71603b5 --- /dev/null +++ b/test_regress/t/t_clocking_notiming.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(verilator_flags2=["--no-timing"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_clocking_out_on_change.pl b/test_regress/t/t_clocking_out_on_change.pl deleted file mode 100755 index 505f31969..000000000 --- a/test_regress/t/t_clocking_out_on_change.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_clocking_out_on_change.py b/test_regress/t/t_clocking_out_on_change.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_clocking_out_on_change.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clocking_react.pl b/test_regress/t/t_clocking_react.pl deleted file mode 100755 index fe3509614..000000000 --- a/test_regress/t/t_clocking_react.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_clocking_react.py b/test_regress/t/t_clocking_react.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_clocking_react.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clocking_sched.pl b/test_regress/t/t_clocking_sched.pl deleted file mode 100755 index 405890497..000000000 --- a/test_regress/t/t_clocking_sched.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename} - ); - -ok(1); -1; diff --git a/test_regress/t/t_clocking_sched.py b/test_regress/t/t_clocking_sched.py new file mode 100755 index 000000000..97abb660e --- /dev/null +++ b/test_regress/t/t_clocking_sched.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_clocking_sched_timing.pl b/test_regress/t/t_clocking_sched_timing.pl deleted file mode 100755 index e4560fa2d..000000000 --- a/test_regress/t/t_clocking_sched_timing.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_clocking_sched.v"); - -compile( - timing_loop => 1, - verilator_flags2 => ["--timing"], - ); - -execute( - expect_filename => $Self->{golden_filename} - ); - -ok(1); -1; diff --git a/test_regress/t/t_clocking_sched_timing.py b/test_regress/t/t_clocking_sched_timing.py new file mode 100755 index 000000000..5737cc7a9 --- /dev/null +++ b/test_regress/t/t_clocking_sched_timing.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_clocking_sched.v" + +test.compile(timing_loop=True, verilator_flags2=["--timing"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_clocking_sched_timing_forkproc.pl b/test_regress/t/t_clocking_sched_timing_forkproc.pl deleted file mode 100755 index 8b9e6c2da..000000000 --- a/test_regress/t/t_clocking_sched_timing_forkproc.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -scenarios(vlt => 1); - -top_filename("t/t_clocking_sched.v"); - -compile( - timing_loop => 1, - verilator_flags2 => ["--timing"], - ); - -execute( - expect_filename => $Self->{golden_filename} - ); - -ok(1); -1; diff --git a/test_regress/t/t_clocking_sched_timing_forkproc.py b/test_regress/t/t_clocking_sched_timing_forkproc.py new file mode 100755 index 000000000..25f9bb0ff --- /dev/null +++ b/test_regress/t/t_clocking_sched_timing_forkproc.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_clocking_sched.v" + +test.compile(timing_loop=True, verilator_flags2=["--timing"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_clocking_timing1.pl b/test_regress/t/t_clocking_timing1.pl deleted file mode 100755 index 2c5396212..000000000 --- a/test_regress/t/t_clocking_timing1.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_clocking_timing.v"); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_clocking_timing1.py b/test_regress/t/t_clocking_timing1.py new file mode 100755 index 000000000..01e5d2048 --- /dev/null +++ b/test_regress/t/t_clocking_timing1.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_clocking_timing.v" + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clocking_timing2.pl b/test_regress/t/t_clocking_timing2.pl deleted file mode 100755 index 76d8dd682..000000000 --- a/test_regress/t/t_clocking_timing2.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_clocking_timing.v"); - -compile( - verilator_flags2 => ["--exe --main --timing -DTEST_INPUT_SKEW=12 -DTEST_OUTPUT_SKEW=16"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_clocking_timing2.py b/test_regress/t/t_clocking_timing2.py new file mode 100755 index 000000000..702df2678 --- /dev/null +++ b/test_regress/t/t_clocking_timing2.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_clocking_timing.v" + +test.compile(verilator_flags2=["--exe --main --timing -DTEST_INPUT_SKEW=12 -DTEST_OUTPUT_SKEW=16"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clocking_unsup1.pl b/test_regress/t/t_clocking_unsup1.pl deleted file mode 100755 index 8ab3c0995..000000000 --- a/test_regress/t/t_clocking_unsup1.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--timing"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_clocking_unsup1.py b/test_regress/t/t_clocking_unsup1.py new file mode 100755 index 000000000..7bf848e53 --- /dev/null +++ b/test_regress/t/t_clocking_unsup1.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--timing"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_clocking_unsup2.pl b/test_regress/t/t_clocking_unsup2.pl deleted file mode 100755 index 8ab3c0995..000000000 --- a/test_regress/t/t_clocking_unsup2.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--timing"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_clocking_unsup2.py b/test_regress/t/t_clocking_unsup2.py new file mode 100755 index 000000000..7bf848e53 --- /dev/null +++ b/test_regress/t/t_clocking_unsup2.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--timing"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_clocking_virtual.pl b/test_regress/t/t_clocking_virtual.pl deleted file mode 100755 index b6b6711d8..000000000 --- a/test_regress/t/t_clocking_virtual.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_clocking_virtual.py b/test_regress/t/t_clocking_virtual.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_clocking_virtual.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_clocking_xref.pl b/test_regress/t/t_clocking_xref.pl deleted file mode 100755 index b6b6711d8..000000000 --- a/test_regress/t/t_clocking_xref.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_clocking_xref.py b/test_regress/t/t_clocking_xref.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_clocking_xref.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_comb_input_0.pl b/test_regress/t/t_comb_input_0.pl deleted file mode 100755 index c4b5c5d1a..000000000 --- a/test_regress/t/t_comb_input_0.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - #make_top_shell => 0, - make_main => 0, - v_flags2 => ["--exe", "$Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_comb_input_0.py b/test_regress/t/t_comb_input_0.py new file mode 100755 index 000000000..74e183dab --- /dev/null +++ b/test_regress/t/t_comb_input_0.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile( + #make_top_shell = False, + make_main=False, + v_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_comb_input_1.pl b/test_regress/t/t_comb_input_1.pl deleted file mode 100755 index c4b5c5d1a..000000000 --- a/test_regress/t/t_comb_input_1.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - #make_top_shell => 0, - make_main => 0, - v_flags2 => ["--exe", "$Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_comb_input_1.py b/test_regress/t/t_comb_input_1.py new file mode 100755 index 000000000..74e183dab --- /dev/null +++ b/test_regress/t/t_comb_input_1.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile( + #make_top_shell = False, + make_main=False, + v_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_comb_input_2.pl b/test_regress/t/t_comb_input_2.pl deleted file mode 100755 index c4b5c5d1a..000000000 --- a/test_regress/t/t_comb_input_2.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - #make_top_shell => 0, - make_main => 0, - v_flags2 => ["--exe", "$Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_comb_input_2.py b/test_regress/t/t_comb_input_2.py new file mode 100755 index 000000000..74e183dab --- /dev/null +++ b/test_regress/t/t_comb_input_2.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile( + #make_top_shell = False, + make_main=False, + v_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_comb_loop_through_unpacked_array.pl b/test_regress/t/t_comb_loop_through_unpacked_array.pl deleted file mode 100755 index c7f63144c..000000000 --- a/test_regress/t/t_comb_loop_through_unpacked_array.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Geza Lore. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - verilator_flags2 => ["-Wno-UNOPTFLAT"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_comb_loop_through_unpacked_array.py b/test_regress/t/t_comb_loop_through_unpacked_array.py new file mode 100755 index 000000000..41b8d5138 --- /dev/null +++ b/test_regress/t/t_comb_loop_through_unpacked_array.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(verilator_flags2=["-Wno-UNOPTFLAT"]) + +test.passes() diff --git a/test_regress/t/t_compiler_include.pl b/test_regress/t/t_compiler_include.pl deleted file mode 100755 index b79c0e8ee..000000000 --- a/test_regress/t/t_compiler_include.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe", "$Self->{t_dir}/$Self->{name}.cpp", "--compiler-include $Self->{t_dir}/t_compiler_include.h", "--output-split 0"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_compiler_include.py b/test_regress/t/t_compiler_include.py new file mode 100755 index 000000000..f2d4a6302 --- /dev/null +++ b/test_regress/t/t_compiler_include.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=[ + "--exe", test.pli_filename, "--compiler-include", + test.t_dir + "/t_compiler_include.h", "--output-split 0" + ]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_compiler_include_dpi.pl b/test_regress/t/t_compiler_include_dpi.pl deleted file mode 100755 index 6fe56c461..000000000 --- a/test_regress/t/t_compiler_include_dpi.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); -top_filename("t/t_compiler_include_dpi.v"); - -compile( - v_flags2 => ["t/t_compiler_include_dpi.cpp"], - verilator_flags2 => ["-Wall -Wno-DECLFILENAME --compiler-include $Self->{t_dir}/t_compiler_include_dpi.h --output-split 0"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_compiler_include_dpi.py b/test_regress/t/t_compiler_include_dpi.py new file mode 100755 index 000000000..b1b215937 --- /dev/null +++ b/test_regress/t/t_compiler_include_dpi.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_compiler_include_dpi.v" + +test.compile(v_flags2=["t/t_compiler_include_dpi.cpp"], + verilator_flags2=[ + "-Wall -Wno-DECLFILENAME --compiler-include", + test.t_dir + "/t_compiler_include_dpi.h --output-split 0" + ]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_compiler_include_dpi_split.pl b/test_regress/t/t_compiler_include_dpi_split.pl deleted file mode 100755 index 65239dd1e..000000000 --- a/test_regress/t/t_compiler_include_dpi_split.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); -top_filename("t/t_compiler_include_dpi.v"); - -compile( - v_flags2 => ["t/t_compiler_include_dpi.cpp"], - verilator_flags2 => ["-Wall -Wno-DECLFILENAME --compiler-include $Self->{t_dir}/t_compiler_include_dpi.h --output-split 1"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_compiler_include_dpi_split.py b/test_regress/t/t_compiler_include_dpi_split.py new file mode 100755 index 000000000..97b694be1 --- /dev/null +++ b/test_regress/t/t_compiler_include_dpi_split.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_compiler_include_dpi.v" + +test.compile(v_flags2=["t/t_compiler_include_dpi.cpp"], + verilator_flags2=[ + "-Wall -Wno-DECLFILENAME --compiler-include", + test.t_dir + "/t_compiler_include_dpi.h --output-split 1" + ]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_compiler_include_split.pl b/test_regress/t/t_compiler_include_split.pl deleted file mode 100755 index b7f54046f..000000000 --- a/test_regress/t/t_compiler_include_split.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); -top_filename("t/t_compiler_include.v"); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe", "$Self->{t_dir}/t_compiler_include.cpp", "--compiler-include $Self->{t_dir}/t_compiler_include.h", "--output-split 1"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_compiler_include_split.py b/test_regress/t/t_compiler_include_split.py new file mode 100755 index 000000000..daae2e49f --- /dev/null +++ b/test_regress/t/t_compiler_include_split.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.pli_filename = "t/t_compiler_include.cpp" +test.top_filename = "t/t_compiler_include.v" + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=[ + "--exe", test.pli_filename, "--compiler-include", + test.t_dir + "/t_compiler_include.h", "--output-split 1" + ]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_concat_large.pl b/test_regress/t/t_concat_large.pl deleted file mode 100755 index fdc76316a..000000000 --- a/test_regress/t/t_concat_large.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_concat_large.py b/test_regress/t/t_concat_large.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_concat_large.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_concat_large_bad.pl b/test_regress/t/t_concat_large_bad.pl deleted file mode 100755 index 53e145105..000000000 --- a/test_regress/t/t_concat_large_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_concat_large_bad.py b/test_regress/t/t_concat_large_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_concat_large_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_concat_link_bad.pl b/test_regress/t/t_concat_link_bad.pl deleted file mode 100755 index 27159da5b..000000000 --- a/test_regress/t/t_concat_link_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_concat_link_bad.py b/test_regress/t/t_concat_link_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_concat_link_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_concat_opt.pl b/test_regress/t/t_concat_opt.pl deleted file mode 100755 index fdc76316a..000000000 --- a/test_regress/t/t_concat_opt.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_concat_opt.py b/test_regress/t/t_concat_opt.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_concat_opt.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_concat_or.pl b/test_regress/t/t_concat_or.pl deleted file mode 100755 index 4409f8046..000000000 --- a/test_regress/t/t_concat_or.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_concat_or.py b/test_regress/t/t_concat_or.py new file mode 100755 index 000000000..f92eef979 --- /dev/null +++ b/test_regress/t/t_concat_or.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only"]) + +test.passes() diff --git a/test_regress/t/t_concat_sel.pl b/test_regress/t/t_concat_sel.pl deleted file mode 100755 index 56363dab6..000000000 --- a/test_regress/t/t_concat_sel.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_concat_sel.py b/test_regress/t/t_concat_sel.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_concat_sel.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_concat_string.pl b/test_regress/t/t_concat_string.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_concat_string.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_concat_string.py b/test_regress/t/t_concat_string.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_concat_string.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_concat_unpack.pl b/test_regress/t/t_concat_unpack.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_concat_unpack.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_concat_unpack.py b/test_regress/t/t_concat_unpack.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_concat_unpack.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_const.pl b/test_regress/t/t_const.pl deleted file mode 100755 index fdc76316a..000000000 --- a/test_regress/t/t_const.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_const.py b/test_regress/t/t_const.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_const.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_const_bad.pl b/test_regress/t/t_const_bad.pl deleted file mode 100755 index 53e145105..000000000 --- a/test_regress/t/t_const_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_const_bad.py b/test_regress/t/t_const_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_const_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_const_bitoptree_bug3096.pl b/test_regress/t/t_const_bitoptree_bug3096.pl deleted file mode 100755 index 6a43c15a1..000000000 --- a/test_regress/t/t_const_bitoptree_bug3096.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2015 by Todd Strader. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - check_finished => 0, - ); - -ok(1); -1; diff --git a/test_regress/t/t_const_bitoptree_bug3096.py b/test_regress/t/t_const_bitoptree_bug3096.py new file mode 100755 index 000000000..1b17842fa --- /dev/null +++ b/test_regress/t/t_const_bitoptree_bug3096.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_top_shell=False, make_main=False, v_flags2=["--exe", test.pli_filename]) + +test.execute(check_finished=False) + +test.passes() diff --git a/test_regress/t/t_const_dec_mixed_bad.pl b/test_regress/t/t_const_dec_mixed_bad.pl deleted file mode 100755 index 35d749208..000000000 --- a/test_regress/t/t_const_dec_mixed_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_const_dec_mixed_bad.py b/test_regress/t/t_const_dec_mixed_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_const_dec_mixed_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_const_hi.pl b/test_regress/t/t_const_hi.pl deleted file mode 100755 index fdc76316a..000000000 --- a/test_regress/t/t_const_hi.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_const_hi.py b/test_regress/t/t_const_hi.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_const_hi.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_const_no_opt.pl b/test_regress/t/t_const_no_opt.pl deleted file mode 100755 index faaeacfe1..000000000 --- a/test_regress/t/t_const_no_opt.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); -top_filename("t/t_const_opt.v"); - -# Run the same design as t_const_opt.pl without bitopt tree optimization to make sure that the result is same. -compile( - verilator_flags2 => [ - "-Wno-UNOPTTHREADS", - "--stats", - "-fno-const-bit-op-tree", - "$Self->{t_dir}/t_const_opt.cpp", - "-CFLAGS", - "-Wno-tautological-compare" - ], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_const_no_opt.py b/test_regress/t/t_const_no_opt.py new file mode 100755 index 000000000..94595165c --- /dev/null +++ b/test_regress/t/t_const_no_opt.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_const_opt.v" + +# Run the same design as t_const_opt.py without bitopt tree optimization to make sure that the result is same. +test.compile(verilator_flags2=[ + "-Wno-UNOPTTHREADS", "--stats", "-fno-const-bit-op-tree", test.t_dir + + "/t_const_opt.cpp", "-CFLAGS", "-Wno-tautological-compare" +]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_const_op_red_scope.pl b/test_regress/t/t_const_op_red_scope.pl deleted file mode 100755 index 6e1338f8e..000000000 --- a/test_regress/t/t_const_op_red_scope.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_const_op_red_scope.py b/test_regress/t/t_const_op_red_scope.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_const_op_red_scope.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_const_opt.pl b/test_regress/t/t_const_opt.pl deleted file mode 100755 index 20198090d..000000000 --- a/test_regress/t/t_const_opt.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["-Wno-UNOPTTHREADS", "-fno-dfg", - "--stats", "$Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - ); - -if ($Self->{vlt}) { - file_grep($Self->{stats}, qr/Optimizations, Const bit op reduction\s+(\d+)/, 45); -} -ok(1); -1; diff --git a/test_regress/t/t_const_opt.py b/test_regress/t/t_const_opt.py new file mode 100755 index 000000000..29f9350f8 --- /dev/null +++ b/test_regress/t/t_const_opt.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["-Wno-UNOPTTHREADS", "-fno-dfg", "--stats", test.pli_filename]) + +test.execute() + +if test.vlt: + test.file_grep(test.stats, r'Optimizations, Const bit op reduction\s+(\d+)', 45) + +test.passes() diff --git a/test_regress/t/t_const_opt_cov.pl b/test_regress/t/t_const_opt_cov.pl deleted file mode 100755 index 16d9e379a..000000000 --- a/test_regress/t/t_const_opt_cov.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["-Wno-UNOPTTHREADS", "--stats", "--coverage", "--trace"], - ); - -execute( - ); - -if ($Self->{vlt}) { - file_grep($Self->{stats}, qr/Optimizations, Const bit op reduction\s+(\d+)/, 144); -} - -ok(1); -1; diff --git a/test_regress/t/t_const_opt_cov.py b/test_regress/t/t_const_opt_cov.py new file mode 100755 index 000000000..1af2400b7 --- /dev/null +++ b/test_regress/t/t_const_opt_cov.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["-Wno-UNOPTTHREADS", "--stats", "--coverage", "--trace"]) + +test.execute() + +if test.vlt: + test.file_grep(test.stats, r'Optimizations, Const bit op reduction\s+(\d+)', 144) + +test.passes() diff --git a/test_regress/t/t_const_opt_dfg.pl b/test_regress/t/t_const_opt_dfg.pl deleted file mode 100755 index 6cc14eede..000000000 --- a/test_regress/t/t_const_opt_dfg.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); -top_filename("t/t_const_opt.v"); - -compile( - verilator_flags2 => ["-Wno-UNOPTTHREADS", - "--stats", "$Self->{t_dir}/t_const_opt.cpp"], - ); - -execute( - ); - -if ($Self->{vlt}) { - file_grep($Self->{stats}, qr/Optimizations, Const bit op reduction\s+(\d+)/, 40); -} -ok(1); -1; diff --git a/test_regress/t/t_const_opt_dfg.py b/test_regress/t/t_const_opt_dfg.py new file mode 100755 index 000000000..57f6f5232 --- /dev/null +++ b/test_regress/t/t_const_opt_dfg.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_const_opt.v" + +test.compile(verilator_flags2=["-Wno-UNOPTTHREADS", "--stats", test.t_dir + "/t_const_opt.cpp"]) + +test.execute() + +if test.vlt: + test.file_grep(test.stats, r'Optimizations, Const bit op reduction\s+(\d+)', 40) + +test.passes() diff --git a/test_regress/t/t_const_opt_no_expand.pl b/test_regress/t/t_const_opt_no_expand.pl deleted file mode 100755 index 6170fbc47..000000000 --- a/test_regress/t/t_const_opt_no_expand.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); -top_filename("t/t_const_opt.v"); - -compile( - verilator_flags2 => ["-Wno-UNOPTTHREADS", "-fno-dfg", "-fno-expand", - "--stats", "$Self->{t_dir}/t_const_opt.cpp"], - ); - -execute( - ); - -if ($Self->{vlt}) { - file_grep($Self->{stats}, qr/Optimizations, Const bit op reduction\s+(\d+)/, 1); -} -ok(1); -1; diff --git a/test_regress/t/t_const_opt_no_expand.py b/test_regress/t/t_const_opt_no_expand.py new file mode 100755 index 000000000..b19ceb1c6 --- /dev/null +++ b/test_regress/t/t_const_opt_no_expand.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_const_opt.v" + +test.compile(verilator_flags2=[ + "-Wno-UNOPTTHREADS", "-fno-dfg", "-fno-expand", "--stats", test.t_dir + "/t_const_opt.cpp" +]) + +test.execute() + +if test.vlt: + test.file_grep(test.stats, r'Optimizations, Const bit op reduction\s+(\d+)', 1) + +test.passes() diff --git a/test_regress/t/t_const_opt_or.pl b/test_regress/t/t_const_opt_or.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_const_opt_or.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_const_opt_or.py b/test_regress/t/t_const_opt_or.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_const_opt_or.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_const_opt_red.pl b/test_regress/t/t_const_opt_red.pl deleted file mode 100755 index ea300f7e8..000000000 --- a/test_regress/t/t_const_opt_red.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["-Wno-UNOPTTHREADS", "--stats"], - ); - -execute( - ); - -if ($Self->{vlt}) { - file_grep($Self->{stats}, qr/Optimizations, Const bit op reduction\s+(\d+)/, 158); -} - -ok(1); -1; diff --git a/test_regress/t/t_const_opt_red.py b/test_regress/t/t_const_opt_red.py new file mode 100755 index 000000000..ab1e823fe --- /dev/null +++ b/test_regress/t/t_const_opt_red.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["-Wno-UNOPTTHREADS", "--stats"]) + +test.execute() + +if test.vlt: + test.file_grep(test.stats, r'Optimizations, Const bit op reduction\s+(\d+)', 158) + +test.passes() diff --git a/test_regress/t/t_const_opt_shortcut.pl b/test_regress/t/t_const_opt_shortcut.pl deleted file mode 100755 index 5f1f10e28..000000000 --- a/test_regress/t/t_const_opt_shortcut.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["t/$Self->{name}.cpp"], - verilator_flags2 => ["-Wno-UNOPTTHREADS", "--stats"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_const_opt_shortcut.py b/test_regress/t/t_const_opt_shortcut.py new file mode 100755 index 000000000..340f595be --- /dev/null +++ b/test_regress/t/t_const_opt_shortcut.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["t/" + test.name + ".cpp"], + verilator_flags2=["-Wno-UNOPTTHREADS", "--stats"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_const_overflow_bad.pl b/test_regress/t/t_const_overflow_bad.pl deleted file mode 100755 index 35d749208..000000000 --- a/test_regress/t/t_const_overflow_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_const_overflow_bad.py b/test_regress/t/t_const_overflow_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_const_overflow_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_const_sel_sel_extend.pl b/test_regress/t/t_const_sel_sel_extend.pl deleted file mode 100755 index 84ae125be..000000000 --- a/test_regress/t/t_const_sel_sel_extend.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Geza Lore. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile(); - -ok(1); -1; diff --git a/test_regress/t/t_const_sel_sel_extend.py b/test_regress/t/t_const_sel_sel_extend.py new file mode 100755 index 000000000..0b27c3dc0 --- /dev/null +++ b/test_regress/t/t_const_sel_sel_extend.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_const_slicesel.pl b/test_regress/t/t_const_slicesel.pl deleted file mode 100755 index becd8a5aa..000000000 --- a/test_regress/t/t_const_slicesel.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl - -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } - -scenarios(linter => 1); - -lint( -); - -ok(1); -1; diff --git a/test_regress/t/t_const_slicesel.py b/test_regress/t/t_const_slicesel.py new file mode 100755 index 000000000..290deb6cd --- /dev/null +++ b/test_regress/t/t_const_slicesel.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 + +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_const_slicesel_bad.pl b/test_regress/t/t_const_slicesel_bad.pl deleted file mode 100755 index 5d84a06aa..000000000 --- a/test_regress/t/t_const_slicesel_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl - -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } - -scenarios(linter => 1); - -lint( - fails => 1 - ); - -ok(1); -1; diff --git a/test_regress/t/t_const_slicesel_bad.py b/test_regress/t/t_const_slicesel_bad.py new file mode 100755 index 000000000..415956256 --- /dev/null +++ b/test_regress/t/t_const_slicesel_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 + +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True) + +test.passes() diff --git a/test_regress/t/t_const_string_func.pl b/test_regress/t/t_const_string_func.pl deleted file mode 100755 index e22e7f5d9..000000000 --- a/test_regress/t/t_const_string_func.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_const_string_func.py b/test_regress/t/t_const_string_func.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_const_string_func.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_constraint.pl b/test_regress/t/t_constraint.pl deleted file mode 100755 index a267ee42b..000000000 --- a/test_regress/t/t_constraint.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_solver) { - skip("No constraint solver installed"); -} else { - compile( - verilator_flags2 => ['-Wno-CONSTRAINTIGN'], - ); - - execute( - ); -} - -ok(1); -1; diff --git a/test_regress/t/t_constraint.py b/test_regress/t/t_constraint.py new file mode 100755 index 000000000..dbae8a1dc --- /dev/null +++ b/test_regress/t/t_constraint.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile(verilator_flags2=['-Wno-CONSTRAINTIGN']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_constraint_foreach.pl b/test_regress/t/t_constraint_foreach.pl deleted file mode 100755 index 1e40acc90..000000000 --- a/test_regress/t/t_constraint_foreach.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_solver) { - skip("No constraint solver installed"); -} else { - compile( - ); - - execute( - ); -} - -ok(1); -1; diff --git a/test_regress/t/t_constraint_foreach.py b/test_regress/t/t_constraint_foreach.py new file mode 100755 index 000000000..a2b131082 --- /dev/null +++ b/test_regress/t/t_constraint_foreach.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_constraint_inheritance.pl b/test_regress/t/t_constraint_inheritance.pl deleted file mode 100755 index 1e40acc90..000000000 --- a/test_regress/t/t_constraint_inheritance.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_solver) { - skip("No constraint solver installed"); -} else { - compile( - ); - - execute( - ); -} - -ok(1); -1; diff --git a/test_regress/t/t_constraint_inheritance.py b/test_regress/t/t_constraint_inheritance.py new file mode 100755 index 000000000..a2b131082 --- /dev/null +++ b/test_regress/t/t_constraint_inheritance.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_constraint_inheritance_with.pl b/test_regress/t/t_constraint_inheritance_with.pl deleted file mode 100755 index 1e40acc90..000000000 --- a/test_regress/t/t_constraint_inheritance_with.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_solver) { - skip("No constraint solver installed"); -} else { - compile( - ); - - execute( - ); -} - -ok(1); -1; diff --git a/test_regress/t/t_constraint_inheritance_with.py b/test_regress/t/t_constraint_inheritance_with.py new file mode 100755 index 000000000..a2b131082 --- /dev/null +++ b/test_regress/t/t_constraint_inheritance_with.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_constraint_json_only.pl b/test_regress/t/t_constraint_json_only.pl deleted file mode 100755 index 89cef23e6..000000000 --- a/test_regress/t/t_constraint_json_only.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - verilator_flags2 => ['--no-std', '--json-only', '--no-json-edit-nums', '-Wno-CONSTRAINTIGN'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -files_identical($out_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_constraint_json_only.py b/test_regress/t/t_constraint_json_only.py new file mode 100755 index 000000000..66928c7bf --- /dev/null +++ b/test_regress/t/t_constraint_json_only.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile( + verilator_flags2=['--no-std', '--json-only', '--no-json-edit-nums', '-Wno-CONSTRAINTIGN'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.files_identical(out_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_constraint_method_bad.pl b/test_regress/t/t_constraint_method_bad.pl deleted file mode 100755 index 66fa61649..000000000 --- a/test_regress/t/t_constraint_method_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_constraint_method_bad.py b/test_regress/t/t_constraint_method_bad.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_constraint_method_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_constraint_mode.pl b/test_regress/t/t_constraint_mode.pl deleted file mode 100755 index 1973412e8..000000000 --- a/test_regress/t/t_constraint_mode.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_solver) { - skip("No constraint solver installed"); -} else { - compile( - ); - - execute( - ); -} - -ok(1); -1; diff --git a/test_regress/t/t_constraint_mode.py b/test_regress/t/t_constraint_mode.py new file mode 100755 index 000000000..a2b131082 --- /dev/null +++ b/test_regress/t/t_constraint_mode.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_constraint_mode_bad.pl b/test_regress/t/t_constraint_mode_bad.pl deleted file mode 100755 index 147dcdcd9..000000000 --- a/test_regress/t/t_constraint_mode_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_constraint_mode_bad.py b/test_regress/t/t_constraint_mode_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_constraint_mode_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_constraint_mode_unsup.pl b/test_regress/t/t_constraint_mode_unsup.pl deleted file mode 100755 index 45e5bcdde..000000000 --- a/test_regress/t/t_constraint_mode_unsup.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_constraint_mode_unsup.py b/test_regress/t/t_constraint_mode_unsup.py new file mode 100755 index 000000000..6585af685 --- /dev/null +++ b/test_regress/t/t_constraint_mode_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_constraint_nosolver_bad.pl b/test_regress/t/t_constraint_nosolver_bad.pl deleted file mode 100755 index 9afe44b86..000000000 --- a/test_regress/t/t_constraint_nosolver_bad.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_constraint.v"); - -compile( - ); - -execute( - run_env => 'VERILATOR_SOLVER=someimaginarysolver', - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_constraint_nosolver_bad.py b/test_regress/t/t_constraint_nosolver_bad.py new file mode 100755 index 000000000..118aafe1b --- /dev/null +++ b/test_regress/t/t_constraint_nosolver_bad.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_constraint.v" + +test.compile() + +test.execute(run_env='VERILATOR_SOLVER=someimaginarysolver', + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_constraint_operators.pl b/test_regress/t/t_constraint_operators.pl deleted file mode 100755 index 1973412e8..000000000 --- a/test_regress/t/t_constraint_operators.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_solver) { - skip("No constraint solver installed"); -} else { - compile( - ); - - execute( - ); -} - -ok(1); -1; diff --git a/test_regress/t/t_constraint_operators.py b/test_regress/t/t_constraint_operators.py new file mode 100755 index 000000000..a2b131082 --- /dev/null +++ b/test_regress/t/t_constraint_operators.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_constraint_state.pl b/test_regress/t/t_constraint_state.pl deleted file mode 100755 index 1973412e8..000000000 --- a/test_regress/t/t_constraint_state.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_solver) { - skip("No constraint solver installed"); -} else { - compile( - ); - - execute( - ); -} - -ok(1); -1; diff --git a/test_regress/t/t_constraint_state.py b/test_regress/t/t_constraint_state.py new file mode 100755 index 000000000..a2b131082 --- /dev/null +++ b/test_regress/t/t_constraint_state.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_constraint_xml.pl b/test_regress/t/t_constraint_xml.pl deleted file mode 100755 index 4cb7c4c79..000000000 --- a/test_regress/t/t_constraint_xml.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml"; - -compile( - verilator_flags2 => ['--no-std', '--xml-only', '-Wno-CONSTRAINTIGN'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -files_identical($out_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_constraint_xml.py b/test_regress/t/t_constraint_xml.py new file mode 100755 index 000000000..118386ead --- /dev/null +++ b/test_regress/t/t_constraint_xml.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +out_filename = test.obj_dir + "/V" + test.name + ".xml" + +test.compile(verilator_flags2=['--no-std', '--xml-only', '-Wno-CONSTRAINTIGN'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.files_identical(out_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_continue_do_while_bad.pl b/test_regress/t/t_continue_do_while_bad.pl deleted file mode 100755 index 8e28a9204..000000000 --- a/test_regress/t/t_continue_do_while_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - expect_filename=>$Self->{golden_filename}, - verilator_flags2=> ['--assert'], - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_continue_do_while_bad.py b/test_regress/t/t_continue_do_while_bad.py new file mode 100755 index 000000000..7e5bcdfe5 --- /dev/null +++ b/test_regress/t/t_continue_do_while_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert'], fails=True) + +test.passes() diff --git a/test_regress/t/t_convert2string.pl b/test_regress/t/t_convert2string.pl deleted file mode 100755 index 3a732a7dc..000000000 --- a/test_regress/t/t_convert2string.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_convert2string.py b/test_regress/t/t_convert2string.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_convert2string.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_cover_assert.pl b/test_regress/t/t_cover_assert.pl deleted file mode 100755 index d76b12847..000000000 --- a/test_regress/t/t_cover_assert.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["-Wall -Wno-DECLFILENAME --coverage"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_cover_assert.py b/test_regress/t/t_cover_assert.py new file mode 100755 index 000000000..5ca9ccb5c --- /dev/null +++ b/test_regress/t/t_cover_assert.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["-Wall -Wno-DECLFILENAME --coverage"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_cover_const_compare.pl b/test_regress/t/t_cover_const_compare.pl deleted file mode 100755 index 25049704b..000000000 --- a/test_regress/t/t_cover_const_compare.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--coverage-line'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_cover_const_compare.py b/test_regress/t/t_cover_const_compare.py new file mode 100755 index 000000000..313bee7b5 --- /dev/null +++ b/test_regress/t/t_cover_const_compare.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--coverage-line']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_cover_lib.pl b/test_regress/t/t_cover_lib.pl deleted file mode 100755 index 898745ee3..000000000 --- a/test_regress/t/t_cover_lib.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - v_flags2 => ["--coverage t/t_cover_lib_c.cpp"], - verilator_flags2 => ["--exe -Wall -Wno-DECLFILENAME"], - make_flags => 'CPPFLAGS_ADD=-DTEST_OBJ_DIR="' . $Self->{obj_dir} . '"', - make_top_shell => 0, - make_main => 0, - ); - -execute( - ); - -files_identical_sorted("$Self->{obj_dir}/coverage1.dat", "t/t_cover_lib_1.out"); -files_identical_sorted("$Self->{obj_dir}/coverage2.dat", "t/t_cover_lib_2.out"); -files_identical_sorted("$Self->{obj_dir}/coverage3.dat", "t/t_cover_lib_3.out"); -files_identical_sorted("$Self->{obj_dir}/coverage4.dat", "t/t_cover_lib_4.out"); -files_identical_sorted("$Self->{obj_dir}/coverage1_per_instance.dat", "t/t_cover_lib_1_per_instance.out"); - -ok(1); -1; diff --git a/test_regress/t/t_cover_lib.py b/test_regress/t/t_cover_lib.py new file mode 100755 index 000000000..e9df3352d --- /dev/null +++ b/test_regress/t/t_cover_lib.py @@ -0,0 +1,28 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(v_flags2=["--coverage t/t_cover_lib_c.cpp"], + verilator_flags2=["--exe -Wall -Wno-DECLFILENAME"], + make_flags=['CPPFLAGS_ADD=-DTEST_OBJ_DIR="' + test.obj_dir + '"'], + make_top_shell=False, + make_main=False) + +test.execute() +test.files_identical_sorted(test.obj_dir + "/coverage1.dat", "t/t_cover_lib_1.out") +test.files_identical_sorted(test.obj_dir + "/coverage2.dat", "t/t_cover_lib_2.out") +test.files_identical_sorted(test.obj_dir + "/coverage3.dat", "t/t_cover_lib_3.out") +test.files_identical_sorted(test.obj_dir + "/coverage4.dat", "t/t_cover_lib_4.out") +test.files_identical_sorted(test.obj_dir + "/coverage1_per_instance.dat", + "t/t_cover_lib_1_per_instance.out") + +test.passes() diff --git a/test_regress/t/t_cover_lib_legacy.pl b/test_regress/t/t_cover_lib_legacy.pl deleted file mode 100755 index 774b47a27..000000000 --- a/test_regress/t/t_cover_lib_legacy.pl +++ /dev/null @@ -1,32 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_cover_lib.v"); - -compile( - v_flags2 => ["--coverage t/t_cover_lib_c.cpp"], - verilator_flags2 => ["--exe -Wall -Wno-DECLFILENAME"], - make_flags => 'CPPFLAGS_ADD=-DTEST_OBJ_DIR="' . $Self->{obj_dir} . '"', - make_top_shell => 0, - make_main => 0, - ); - -execute( - ); - -files_identical_sorted("$Self->{obj_dir}/coverage1.dat", "t/t_cover_lib_1.out"); -files_identical_sorted("$Self->{obj_dir}/coverage2.dat", "t/t_cover_lib_2.out"); -files_identical_sorted("$Self->{obj_dir}/coverage3.dat", "t/t_cover_lib_3.out"); -files_identical_sorted("$Self->{obj_dir}/coverage4.dat", "t/t_cover_lib_4.out"); - -ok(1); -1; diff --git a/test_regress/t/t_cover_lib_legacy.py b/test_regress/t/t_cover_lib_legacy.py new file mode 100755 index 000000000..28ce6b5bf --- /dev/null +++ b/test_regress/t/t_cover_lib_legacy.py @@ -0,0 +1,27 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_cover_lib.v" + +test.compile(v_flags2=["--coverage t/t_cover_lib_c.cpp"], + verilator_flags2=["--exe -Wall -Wno-DECLFILENAME"], + make_flags=['CPPFLAGS_ADD=-DTEST_OBJ_DIR="' + test.obj_dir + '"'], + make_top_shell=False, + make_main=False) + +test.execute() +test.files_identical_sorted(test.obj_dir + "/coverage1.dat", "t/t_cover_lib_1.out") +test.files_identical_sorted(test.obj_dir + "/coverage2.dat", "t/t_cover_lib_2.out") +test.files_identical_sorted(test.obj_dir + "/coverage3.dat", "t/t_cover_lib_3.out") +test.files_identical_sorted(test.obj_dir + "/coverage4.dat", "t/t_cover_lib_4.out") + +test.passes() diff --git a/test_regress/t/t_cover_line_cc.pl b/test_regress/t/t_cover_line_cc.pl deleted file mode 100755 index c287e550c..000000000 --- a/test_regress/t/t_cover_line_cc.pl +++ /dev/null @@ -1,60 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_cover_line.v"); -golden_filename("t/t_cover_line.out"); - -compile( - verilator_flags2 => ['--cc --coverage-line +define+ATTRIBUTE'], - ); - -execute( - ); - -# Read the input .v file and do any CHECK_COVER requests -inline_checks(); - -run(cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator_coverage", - "--annotate-points", - "--annotate", "$Self->{obj_dir}/annotated", - "$Self->{obj_dir}/coverage.dat"], - verilator_run => 1, - ); - -files_identical("$Self->{obj_dir}/annotated/t_cover_line.v", $Self->{golden_filename}); - -# Also try lcov -run(cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator_coverage", - "--write-info", "$Self->{obj_dir}/coverage.info", - "$Self->{obj_dir}/coverage.dat"], - verilator_run => 1, - ); - -files_identical("$Self->{obj_dir}/coverage.info", "t/" . $Self->{name} . ".info.out"); - -# If installed -if (`lcov --version` !~ /version/i - || `genhtml --version` !~ /version ([0-9.]+)/i) { - skip("lcov or genhtml not installed"); -} elsif ($1 < 1.14) { - skip("lcov or genhtml too old (version $1), need version >= 1.14"); -} else { - run(cmd => ["genhtml", - "$Self->{obj_dir}/coverage.info", - "--branch-coverage", - "--output-directory $Self->{obj_dir}/html", - ]); -} - - -ok(1); -1; diff --git a/test_regress/t/t_cover_line_cc.py b/test_regress/t/t_cover_line_cc.py new file mode 100755 index 000000000..5489f8dfc --- /dev/null +++ b/test_regress/t/t_cover_line_cc.py @@ -0,0 +1,51 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_cover_line.v" +test.golden_filename = "t/t_cover_line.out" + +test.compile(verilator_flags2=['--cc --coverage-line +define+ATTRIBUTE']) + +test.execute() + +test.run(cmd=[os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", + "--annotate-points", + "--annotate", test.obj_dir + "/annotated", + test.obj_dir + "/coverage.dat"], + verilator_run=True) # yapf:disable + +test.files_identical(test.obj_dir + "/annotated/t_cover_line.v", test.golden_filename) + +# Also try lcov +test.run(cmd=[os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", + "--write-info", test.obj_dir + "/coverage.info", + test.obj_dir + "/coverage.dat"], + verilator_run=True) # yapf:disable + +test.files_identical(test.obj_dir + "/coverage.info", "t/" + test.name + ".info.out") + +# If installed +nout = test.run_capture("lcov --version", check=False) +version_match = re.search(r'version ([0-9.]+)', nout, re.IGNORECASE) +if not version_match: + test.skip("lcov or genhtml not installed") + +if float(version_match.group(1)) < 1.14: + test.skip("lcov or genhtml too old (version " + version_match.group(1) + + ", need version >= 1.14") + +test.run(cmd=[ + "genhtml", test.obj_dir + "/coverage.info", "--branch-coverage", "--output-directory " + + test.obj_dir + "/html" +]) + +test.passes() diff --git a/test_regress/t/t_cover_line_cc_vlt.pl b/test_regress/t/t_cover_line_cc_vlt.pl deleted file mode 100755 index e5350661a..000000000 --- a/test_regress/t/t_cover_line_cc_vlt.pl +++ /dev/null @@ -1,37 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_cover_line.v"); -golden_filename("t/t_cover_line.out"); - -compile( - verilator_flags2 => ['--cc', '--coverage-line', "t/t_cover_line.vlt"], - ); - -execute( - ); - -# Read the input .v file and do any CHECK_COVER requests -inline_checks(); - -run(cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator_coverage", - "--annotate-points", - "--annotate", "$Self->{obj_dir}/annotated", - "$Self->{obj_dir}/coverage.dat", - ], - verilator_run => 1, - ); - -files_identical("$Self->{obj_dir}/annotated/t_cover_line.v", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_cover_line_cc_vlt.py b/test_regress/t/t_cover_line_cc_vlt.py new file mode 100755 index 000000000..fd97596c4 --- /dev/null +++ b/test_regress/t/t_cover_line_cc_vlt.py @@ -0,0 +1,34 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_cover_line.v" +test.golden_filename = "t/t_cover_line.out" + +test.compile(verilator_flags2=['--cc', '--coverage-line', "t/t_cover_line.vlt"]) + +test.execute() + +# Read the input .v file and do any CHECK_COVER requests +test.inline_checks() + +test.run(cmd=[ + os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", + "--annotate-points", + "--annotate", + test.obj_dir + "/annotated", + test.obj_dir + "/coverage.dat", +], + verilator_run=True) + +test.files_identical(test.obj_dir + "/annotated/t_cover_line.v", test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_cover_line_sc.pl b/test_regress/t/t_cover_line_sc.pl deleted file mode 100755 index bb035a9e5..000000000 --- a/test_regress/t/t_cover_line_sc.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_cover_line.v"); - -compile( - verilator_flags2 => ['--sc --coverage-line +define+ATTRIBUTE'], - ); - -execute( - ); - -# Read the input .v file and do any CHECK_COVER requests -inline_checks(); - -ok(1); -1; diff --git a/test_regress/t/t_cover_line_sc.py b/test_regress/t/t_cover_line_sc.py new file mode 100755 index 000000000..ff73bf508 --- /dev/null +++ b/test_regress/t/t_cover_line_sc.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_cover_line.v" + +test.compile(verilator_flags2=['--sc --coverage-line +define+ATTRIBUTE']) + +test.execute() + +# Read the input .v file and do any CHECK_COVER requests +test.inline_checks() + +test.passes() diff --git a/test_regress/t/t_cover_line_trace.pl b/test_regress/t/t_cover_line_trace.pl deleted file mode 100755 index d55dd46b0..000000000 --- a/test_regress/t/t_cover_line_trace.pl +++ /dev/null @@ -1,34 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_cover_line.v"); - -compile( - verilator_flags2 => ['--cc --coverage-line --trace --trace-coverage +define+ATTRIBUTE'], - ); - -execute( - ); - -run(cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator_coverage", - "--annotate-points", - "--annotate", "$Self->{obj_dir}/annotated", - "$Self->{obj_dir}/coverage.dat", - ], - verilator_run => 1, - ); - -files_identical("$Self->{obj_dir}/annotated/t_cover_line.v", "t/t_cover_line.out"); -vcd_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_cover_line_trace.py b/test_regress/t/t_cover_line_trace.py new file mode 100755 index 000000000..3a2fb4784 --- /dev/null +++ b/test_regress/t/t_cover_line_trace.py @@ -0,0 +1,30 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_cover_line.v" + +test.compile(verilator_flags2=['--cc --coverage-line --trace --trace-coverage +define+ATTRIBUTE']) + +test.execute() + +test.run(cmd=[ + os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", + "--annotate-points", + "--annotate", + test.obj_dir + "/annotated", + test.obj_dir + "/coverage.dat", +], + verilator_run=True) + +test.files_identical(test.obj_dir + "/annotated/t_cover_line.v", "t/t_cover_line.out") +test.vcd_identical(test.trace_filename, test.golden_filename) +test.passes() diff --git a/test_regress/t/t_cover_main.pl b/test_regress/t/t_cover_main.pl deleted file mode 100755 index 8905a293a..000000000 --- a/test_regress/t/t_cover_main.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--binary --coverage-line'], - ); - -execute( - all_run_flags => [" +verilator+coverage+file+$Self->{obj_dir}/coverage_renamed.dat"], - ); - -files_identical_sorted("$Self->{obj_dir}/coverage_renamed.dat", "t/t_cover_main.out"); - -ok(1); -1; diff --git a/test_regress/t/t_cover_main.py b/test_regress/t/t_cover_main.py new file mode 100755 index 000000000..9f3651d02 --- /dev/null +++ b/test_regress/t/t_cover_main.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--binary --coverage-line']) + +test.execute(all_run_flags=[" +verilator+coverage+file+" + test.obj_dir + "/coverage_renamed.dat"]) + +test.files_identical_sorted(test.obj_dir + "/coverage_renamed.dat", "t/t_cover_main.out") +test.passes() diff --git a/test_regress/t/t_cover_sva_notflat.pl b/test_regress/t/t_cover_sva_notflat.pl deleted file mode 100755 index 5b1d83998..000000000 --- a/test_regress/t/t_cover_sva_notflat.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--assert --cc --coverage-user'], - ); - -execute( - ); - -#if ($Self->{nc}) ... # See t_assert_cover.pl for NC version - -# Allow old SystemC::Coverage format dump, or new binary dump -# Check that the hierarchy doesn't include __PVT__ -# Otherwise our coverage reports would look really ugly -if ($Self->{vlt_all}) { - file_grep($Self->{coverage_filename}, qr/(top\.t\.sub.*.cyc_eq_5)/); -} - -ok(1); -1; diff --git a/test_regress/t/t_cover_sva_notflat.py b/test_regress/t/t_cover_sva_notflat.py new file mode 100755 index 000000000..8202ac126 --- /dev/null +++ b/test_regress/t/t_cover_sva_notflat.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--assert --cc --coverage-user']) + +test.execute() + +#if test.nc: ... # See t_assert_cover.py for NC version + +# Allow old SystemC::Coverage format dump, or new binary dump +# Check that the hierarchy doesn't include __PVT__ +# Otherwise our coverage reports would look really ugly +if test.vlt_all: + test.file_grep(test.coverage_filename, r'(top\.t\.sub.*.cyc_eq_5)') + +test.passes() diff --git a/test_regress/t/t_cover_sva_trace.pl b/test_regress/t/t_cover_sva_trace.pl deleted file mode 100755 index b8d398645..000000000 --- a/test_regress/t/t_cover_sva_trace.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_cover_sva_notflat.v"); - -compile( - verilator_flags2 => ['--assert --cc --coverage-user --trace --trace-coverage'], - ); - -execute( - ); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_cover_sva_trace.py b/test_regress/t/t_cover_sva_trace.py new file mode 100755 index 000000000..5e5c25fdb --- /dev/null +++ b/test_regress/t/t_cover_sva_trace.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_cover_sva_notflat.v" + +test.compile(verilator_flags2=['--assert --cc --coverage-user --trace --trace-coverage']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_cover_toggle.pl b/test_regress/t/t_cover_toggle.pl deleted file mode 100755 index 061221eb5..000000000 --- a/test_regress/t/t_cover_toggle.pl +++ /dev/null @@ -1,48 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--cc --coverage-toggle --stats'], - ); - -execute( - ); - -# Read the input .v file and do any CHECK_COVER requests -inline_checks(); - -file_grep_not("$Self->{obj_dir}/coverage.dat", "largeish"); - -file_grep($Self->{stats}, qr/Coverage, Toggle points joined\s+(\d+)/, 23) - if $Self->{vlt_all}; - -run(cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator_coverage", - "--annotate", "$Self->{obj_dir}/annotated", - "$Self->{obj_dir}/coverage.dat", - ], - verilator_run => 1, - ); - -files_identical("$Self->{obj_dir}/annotated/$Self->{name}.v", $Self->{golden_filename}); - -run(cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator_coverage", - "--annotate-points", - "--annotate", "$Self->{obj_dir}/annotated-points", - "$Self->{obj_dir}/coverage.dat", - ], - verilator_run => 1, - ); - -files_identical("$Self->{obj_dir}/annotated-points/$Self->{name}.v", "t/" . $Self->{name} . "_points.out"); - -ok(1); -1; diff --git a/test_regress/t/t_cover_toggle.py b/test_regress/t/t_cover_toggle.py new file mode 100755 index 000000000..a023aa31c --- /dev/null +++ b/test_regress/t/t_cover_toggle.py @@ -0,0 +1,48 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--cc --coverage-toggle --stats']) + +test.execute() + +# Read the input .v file and do any CHECK_COVER requests +test.inline_checks() + +test.file_grep_not(test.obj_dir + "/coverage.dat", "largeish") + +if test.vlt_all: + test.file_grep(test.stats, r'Coverage, Toggle points joined\s+(\d+)', 23) + +test.run(cmd=[ + os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", + "--annotate", + test.obj_dir + "/annotated", + test.obj_dir + "/coverage.dat", +], + verilator_run=True) + +test.files_identical(test.obj_dir + "/annotated/" + test.name + ".v", test.golden_filename) + +test.run(cmd=[ + os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", + "--annotate-points", + "--annotate", + test.obj_dir + "/annotated-points", + test.obj_dir + "/coverage.dat", +], + verilator_run=True) + +test.files_identical(test.obj_dir + "/annotated-points/" + test.name + ".v", + "t/" + test.name + "_points.out") + +test.passes() diff --git a/test_regress/t/t_cover_toggle_min.pl b/test_regress/t/t_cover_toggle_min.pl deleted file mode 100755 index 4563d6c8d..000000000 --- a/test_regress/t/t_cover_toggle_min.pl +++ /dev/null @@ -1,33 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--binary', '--coverage-toggle'], - ); - -execute( - all_run_flags => [" +verilator+coverage+file+$Self->{obj_dir}/coverage.dat"], - ); - -if (-e ("$Self->{obj_dir}/coverage.dat")) { # Don't try to write .info if test was skipped - run(cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator_coverage", - "-write-info", "$Self->{obj_dir}/coverage.info", - "$Self->{obj_dir}/coverage.dat", - ], - verilator_run => 1, - ); - - files_identical("$Self->{obj_dir}/coverage.info", "t/" . $Self->{name} . ".info.out"); -} - -ok(1); -1; diff --git a/test_regress/t/t_cover_toggle_min.py b/test_regress/t/t_cover_toggle_min.py new file mode 100755 index 000000000..83bd0383a --- /dev/null +++ b/test_regress/t/t_cover_toggle_min.py @@ -0,0 +1,29 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--binary', '--coverage-toggle']) + +test.execute(all_run_flags=[" +verilator+coverage+file+" + test.obj_dir + "/coverage.dat"]) + +if os.path.exists(test.obj_dir + "/coverage.dat"): # Don't try to write .info if test was skipped + test.run(cmd=[ + os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", + "-write-info", + test.obj_dir + "/coverage.info", + test.obj_dir + "/coverage.dat", + ], + verilator_run=True) + + test.files_identical(test.obj_dir + "/coverage.info", "t/" + test.name + ".info.out") + +test.passes() diff --git a/test_regress/t/t_cover_toggle_width.pl b/test_regress/t/t_cover_toggle_width.pl deleted file mode 100755 index 0cc96036c..000000000 --- a/test_regress/t/t_cover_toggle_width.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_cover_toggle.v"); - -compile( - verilator_flags2 => ['--cc --coverage-toggle --coverage-max-width 1025'], - ); - -execute( - ); - -file_grep("$Self->{obj_dir}/coverage.dat", "largeish"); - -ok(1); -1; diff --git a/test_regress/t/t_cover_toggle_width.py b/test_regress/t/t_cover_toggle_width.py new file mode 100755 index 000000000..5b1711302 --- /dev/null +++ b/test_regress/t/t_cover_toggle_width.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_cover_toggle.v" + +test.compile(verilator_flags2=['--cc --coverage-toggle --coverage-max-width 1025']) + +test.execute() + +test.file_grep(test.obj_dir + "/coverage.dat", "largeish") + +test.passes() diff --git a/test_regress/t/t_cover_unused_bad.pl b/test_regress/t/t_cover_unused_bad.pl deleted file mode 100755 index 348cfc821..000000000 --- a/test_regress/t/t_cover_unused_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["-Wall -Wno-DECLFILENAME --coverage"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_cover_unused_bad.py b/test_regress/t/t_cover_unused_bad.py new file mode 100755 index 000000000..6818d8256 --- /dev/null +++ b/test_regress/t/t_cover_unused_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["-Wall -Wno-DECLFILENAME --coverage"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_covergroup_unsup.pl b/test_regress/t/t_covergroup_unsup.pl deleted file mode 100755 index 7284ec30e..000000000 --- a/test_regress/t/t_covergroup_unsup.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - expect_filename => $Self->{golden_filename}, - verilator_flags2 => ['--assert --error-limit 1000'], - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_covergroup_unsup.py b/test_regress/t/t_covergroup_unsup.py new file mode 100755 index 000000000..25f9960b8 --- /dev/null +++ b/test_regress/t/t_covergroup_unsup.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(expect_filename=test.golden_filename, + verilator_flags2=['--assert --error-limit 1000'], + fails=True) + +test.passes() diff --git a/test_regress/t/t_cuse_forward.pl b/test_regress/t/t_cuse_forward.pl deleted file mode 100755 index f17d7f547..000000000 --- a/test_regress/t/t_cuse_forward.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_cuse_forward.py b/test_regress/t/t_cuse_forward.py new file mode 100755 index 000000000..0b27c3dc0 --- /dev/null +++ b/test_regress/t/t_cuse_forward.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_cxx_equal_to.pl b/test_regress/t/t_cxx_equal_to.pl deleted file mode 100755 index 0e908b7ed..000000000 --- a/test_regress/t/t_cxx_equal_to.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_cxx_equal_to.v"); - -compile( - verilator_flags2 => ['--binary --timing --trace'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_cxx_equal_to.py b/test_regress/t/t_cxx_equal_to.py new file mode 100755 index 000000000..3ec7b82b4 --- /dev/null +++ b/test_regress/t/t_cxx_equal_to.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_cxx_equal_to.v" + +test.compile(verilator_flags2=['--binary --timing --trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_debug_emitv.pl b/test_regress/t/t_debug_emitv.pl deleted file mode 100755 index 4af48a3e3..000000000 --- a/test_regress/t/t_debug_emitv.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - # We also have dump-tree turned on, so hit a lot of AstNode*::dump() functions - # Likewise XML - v_flags => ["--lint-only --dumpi-tree 9 --dumpi-V3EmitV 9 --debug-emitv"], - ); - -files_identical(glob_one("$Self->{obj_dir}/$Self->{vm_prefix}_*_width.tree.v"), $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_debug_emitv.py b/test_regress/t/t_debug_emitv.py new file mode 100755 index 000000000..6063ac2c8 --- /dev/null +++ b/test_regress/t/t_debug_emitv.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint( + # We also have dump-tree turned on, so hit a lot of AstNode*::dump() functions + # Likewise XML + v_flags=["--lint-only --dumpi-tree 9 --dumpi-V3EmitV 9 --debug-emitv"]) + +test.files_identical(test.glob_one(test.obj_dir + "/" + test.vm_prefix + "_*_width.tree.v"), + test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_debug_emitv_addrids.pl b/test_regress/t/t_debug_emitv_addrids.pl deleted file mode 100755 index 183f2dd13..000000000 --- a/test_regress/t/t_debug_emitv_addrids.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_debug_emitv.v"); - -lint( - # We also have dump-tree turned on, so hit a lot of AstNode*::dump() functions - # Likewise XML - v_flags => ["--lint-only --dumpi-tree 9 --dump-tree-addrids"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_debug_emitv_addrids.py b/test_regress/t/t_debug_emitv_addrids.py new file mode 100755 index 000000000..84634c936 --- /dev/null +++ b/test_regress/t/t_debug_emitv_addrids.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_debug_emitv.v" + +test.lint( + # We also have dump-tree turned on, so hit a lot of AstNode*::dump() functions + # Likewise XML + v_flags=["--lint-only --dumpi-tree 9 --dump-tree-addrids"]) + +test.passes() diff --git a/test_regress/t/t_debug_exit_parse.pl b/test_regress/t/t_debug_exit_parse.pl deleted file mode 100755 index 2d41185e7..000000000 --- a/test_regress/t/t_debug_exit_parse.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t_EXAMPLE.v"); - -lint( - verilator_flags2 => ["--debug-exit-parse"], - expect => '--debug-exit-parse', - ); - -ok(1); -1; diff --git a/test_regress/t/t_debug_exit_parse.py b/test_regress/t/t_debug_exit_parse.py new file mode 100755 index 000000000..527c9eee3 --- /dev/null +++ b/test_regress/t/t_debug_exit_parse.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t_EXAMPLE.v" + +test.lint(verilator_flags2=["--debug-exit-parse"], expect='--debug-exit-parse') + +test.passes() diff --git a/test_regress/t/t_debug_fatalsrc_bad.pl b/test_regress/t/t_debug_fatalsrc_bad.pl deleted file mode 100755 index a0cc619db..000000000 --- a/test_regress/t/t_debug_fatalsrc_bad.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -if (system("gdb --version")) { - skip("No gdb installed"); -} else { - lint( - verilator_flags2 => ["--debug-fatalsrc"], - fails => $Self->{vlt_all}, - expect => -'%Error: Internal Error: .*: --debug-fatal-src -.* See the manual .*', - ); - - ok(1); -} -1; diff --git a/test_regress/t/t_debug_fatalsrc_bad.py b/test_regress/t/t_debug_fatalsrc_bad.py new file mode 100755 index 000000000..924b7c544 --- /dev/null +++ b/test_regress/t/t_debug_fatalsrc_bad.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +if not test.have_gdb: + test.skip("No gdb installed") + +test.lint(verilator_flags2=["--debug-fatalsrc"], + fails=test.vlt_all, + expect="""%Error: Internal Error: .*: --debug-fatal-src +.* See the manual .*""") + +test.passes() diff --git a/test_regress/t/t_debug_fatalsrc_bt_bad.pl b/test_regress/t/t_debug_fatalsrc_bt_bad.pl deleted file mode 100755 index 4471fbf46..000000000 --- a/test_regress/t/t_debug_fatalsrc_bt_bad.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -if ($ENV{VERILATOR_TEST_NO_GDB}) { - skip("Skipping due to VERILATOR_TEST_NO_GDB"); -} elsif (system("gdb --version")) { - skip("No gdb installed"); -} else { - lint( - verilator_flags2 => ["--lint-only --debug --gdbbt --debug-fatalsrc"], - fails => 1, - expect => -'%Error: Internal Error: .*: --debug-fatal-src -.*See the manual .* -.*in V3Options::.* -.*%Error: Command Failed.*', - ); - ok(1); -} - -1; diff --git a/test_regress/t/t_debug_fatalsrc_bt_bad.py b/test_regress/t/t_debug_fatalsrc_bt_bad.py new file mode 100755 index 000000000..95fab9c75 --- /dev/null +++ b/test_regress/t/t_debug_fatalsrc_bt_bad.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +if 'VERILATOR_TEST_NO_GDB' in os.environ: + test.skip("Skipping due to VERILATOR_TEST_NO_GDB") +if not test.have_gdb: + test.skip("No gdb installed") + +test.lint(verilator_flags2=["--lint-only --debug --gdbbt --debug-fatalsrc"], + fails=True, + expect="""%Error: Internal Error: .*: --debug-fatal-src +.*See the manual .* +.*in V3Options::.* +.*%Error: Command Failed.*""") + +test.passes() diff --git a/test_regress/t/t_debug_gate.pl b/test_regress/t/t_debug_gate.pl deleted file mode 100755 index 4867dec5d..000000000 --- a/test_regress/t/t_debug_gate.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - # Check we can call dump() on graph, and other things - v_flags => ["--debug --debugi 0 --debugi-V3Graph 9"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_debug_gate.py b/test_regress/t/t_debug_gate.py new file mode 100755 index 000000000..aa28d966e --- /dev/null +++ b/test_regress/t/t_debug_gate.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile( + # Check we can call dump() on graph, and other things + v_flags=["--debug --debugi 0 --debugi-V3Graph 9"]) + +test.passes() diff --git a/test_regress/t/t_debug_graph_test.pl b/test_regress/t/t_debug_graph_test.pl deleted file mode 100755 index 64bc7a996..000000000 --- a/test_regress/t/t_debug_graph_test.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); -$ENV{VERILATOR_TEST_NO_GDB} and skip("Skipping due to VERILATOR_TEST_NO_GDB"); - -lint( - # Check we can call dump() on graph, and other things - v_flags => ["--lint-only --debug --debugi-V3GraphTest 9 --debug-self-test"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_debug_graph_test.py b/test_regress/t/t_debug_graph_test.py new file mode 100755 index 000000000..d88c7810b --- /dev/null +++ b/test_regress/t/t_debug_graph_test.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +if 'VERILATOR_TEST_NO_GDB' in os.environ: + test.skip("Skipping due to VERILATOR_TEST_NO_GDB") + +test.lint( + # Check we can call dump() on graph, and other things + v_flags=["--lint-only --debug --debugi-V3GraphTest 9 --debug-self-test"]) + +test.passes() diff --git a/test_regress/t/t_debug_inputs.pl b/test_regress/t/t_debug_inputs.pl deleted file mode 100755 index 9b9054d09..000000000 --- a/test_regress/t/t_debug_inputs.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - v_flags => ["--debug --debugi 1 -Wno-MULTITOP t/t_debug_inputs_b.v"], - ); - -file_grep("$Self->{obj_dir}/V$Self->{name}__inputs.vpp", qr/module t_debug_inputs /); -file_grep("$Self->{obj_dir}/V$Self->{name}__inputs.vpp", qr/module t_debug_inputs_a /); -file_grep("$Self->{obj_dir}/V$Self->{name}__inputs.vpp", qr/module t_debug_inputs_b /); - -ok(1); -1; diff --git a/test_regress/t/t_debug_inputs.py b/test_regress/t/t_debug_inputs.py new file mode 100755 index 000000000..eb6b583f6 --- /dev/null +++ b/test_regress/t/t_debug_inputs.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(v_flags=["--debug --debugi 1 -Wno-MULTITOP t/t_debug_inputs_b.v"]) + +test.file_grep(test.obj_dir + "/V" + test.name + "__inputs.vpp", r'module t_debug_inputs ') +test.file_grep(test.obj_dir + "/V" + test.name + "__inputs.vpp", r'module t_debug_inputs_a ') +test.file_grep(test.obj_dir + "/V" + test.name + "__inputs.vpp", r'module t_debug_inputs_b ') + +test.passes() diff --git a/test_regress/t/t_debug_sigsegv_bad.pl b/test_regress/t/t_debug_sigsegv_bad.pl deleted file mode 100755 index ad73ac6f9..000000000 --- a/test_regress/t/t_debug_sigsegv_bad.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -if ($ENV{VERILATOR_TEST_NO_GDB}) { - skip("Skipping due to VERILATOR_TEST_NO_GDB"); -} elsif (system("gdb --version")) { - skip("No gdb installed"); -} else { - lint( - v_flags => ["--debug-sigsegv"], - fails => 1, - sanitize => 0, - expect => -'%Error: Verilator internal fault, sorry. Suggest trying --debug --gdbbt -%Error: Command Failed.*', - ); - - ok(1); -} -1; diff --git a/test_regress/t/t_debug_sigsegv_bad.py b/test_regress/t/t_debug_sigsegv_bad.py new file mode 100755 index 000000000..5dd01cbdf --- /dev/null +++ b/test_regress/t/t_debug_sigsegv_bad.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +if 'VERILATOR_TEST_NO_GDB' in os.environ: + test.skip("Skipping due to VERILATOR_TEST_NO_GDB") +if not test.have_gdb: + test.skip("No gdb installed") + +test.lint(v_flags=["--debug-sigsegv"], + fails=True, + sanitize=0, + expect="""%Error: Verilator internal fault, sorry. Suggest trying --debug --gdbbt +%Error: Command Failed.*""") + +test.passes() diff --git a/test_regress/t/t_debug_sigsegv_bt_bad.pl b/test_regress/t/t_debug_sigsegv_bt_bad.pl deleted file mode 100755 index c6dd7a9a4..000000000 --- a/test_regress/t/t_debug_sigsegv_bt_bad.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); -if ($ENV{VERILATOR_TEST_NO_GDB}) { - skip("Skipping due to VERILATOR_TEST_NO_GDB"); -} elsif (system("gdb --version")) { - skip("No gdb installed"); -} else { - lint( - verilator_flags2 => ["--lint-only --debug --gdbbt --debug-sigsegv"], - sanitize => 0, - fails => $Self->{vlt_all}, - expect => -'.* -Program received signal SIGSEGV, Segmentation fault. -.*in V3Options::.* -.*%Error: Command Failed.*', - ); - - ok(1); -} -1; diff --git a/test_regress/t/t_debug_sigsegv_bt_bad.py b/test_regress/t/t_debug_sigsegv_bt_bad.py new file mode 100755 index 000000000..a8dff0ecc --- /dev/null +++ b/test_regress/t/t_debug_sigsegv_bt_bad.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +if 'VERILATOR_TEST_NO_GDB' in os.environ: + test.skip("Skipping due to VERILATOR_TEST_NO_GDB") +if not test.have_gdb: + test.skip("No gdb installed") + +test.lint(verilator_flags2=["--lint-only --debug --gdbbt --debug-sigsegv"], + sanitize=0, + fails=test.vlt_all, + expect=""".* +Program received signal SIGSEGV, Segmentation fault. +.*in V3Options::.* +.*%Error: Command Failed.*""") + +test.passes() diff --git a/test_regress/t/t_debug_trace.pl b/test_regress/t/t_debug_trace.pl deleted file mode 100755 index e68e695f7..000000000 --- a/test_regress/t/t_debug_trace.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - # Check we can call dump() on graph, and other things - v_flags => ["--trace --debug --debugi 0 --debugi-V3Trace 9"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_debug_trace.py b/test_regress/t/t_debug_trace.py new file mode 100755 index 000000000..ecf01e167 --- /dev/null +++ b/test_regress/t/t_debug_trace.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile( + # Check we can call dump() on graph, and other things + v_flags=["--trace --debug --debugi 0 --debugi-V3Trace 9"]) + +test.passes() diff --git a/test_regress/t/t_debug_width.pl b/test_regress/t/t_debug_width.pl deleted file mode 100755 index b4ae3a10c..000000000 --- a/test_regress/t/t_debug_width.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -top_filename("t/t_const_opt.v"); -scenarios(simulator => 1); - -lint( - verilator_flags2 => ["--lint-only", "--debug-width"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_debug_width.py b/test_regress/t/t_debug_width.py new file mode 100755 index 000000000..73c4e1e72 --- /dev/null +++ b/test_regress/t/t_debug_width.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_const_opt.v" + +test.lint(verilator_flags2=["--lint-only", "--debug-width"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dedupe_clk_gate.pl b/test_regress/t/t_dedupe_clk_gate.pl deleted file mode 100755 index f8f612945..000000000 --- a/test_regress/t/t_dedupe_clk_gate.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - verilator_flags2 => ["--no-json-edit-nums", "--stats"], - ); - -if ($Self->{vlt_all}) { - file_grep("$out_filename", qr/{"type":"VAR","name":"t.f0.clock_gate.clken_latched","addr":"[^"]*","loc":"\w,44:[^"]*","dtypep":"\(\w+\)",.*"origName":"clken_latched",.*"isLatched":true,.*"dtypeName":"logic"/); - file_grep($Self->{stats}, qr/Optimizations, Gate sigs deduped\s+(\d+)/, 4); -} - -ok(1); -1; diff --git a/test_regress/t/t_dedupe_clk_gate.py b/test_regress/t/t_dedupe_clk_gate.py new file mode 100755 index 000000000..29a1ccf68 --- /dev/null +++ b/test_regress/t/t_dedupe_clk_gate.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(verilator_flags2=["--no-json-edit-nums", "--stats"]) + +if test.vlt_all: + test.file_grep( + out_filename, + r'{"type":"VAR","name":"t.f0.clock_gate.clken_latched","addr":"[^"]*","loc":"\w,44:[^"]*","dtypep":"\(\w+\)",.*"origName":"clken_latched",.*"isLatched":true,.*"dtypeName":"logic"' + ) + test.file_grep(test.stats, r'Optimizations, Gate sigs deduped\s+(\d+)', 4) + +test.passes() diff --git a/test_regress/t/t_dedupe_seq_logic.pl b/test_regress/t/t_dedupe_seq_logic.pl deleted file mode 100755 index 4a7c2af27..000000000 --- a/test_regress/t/t_dedupe_seq_logic.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, Gate sigs deduped\s+(\d+)/, 6); -} - -ok(1); -1; diff --git a/test_regress/t/t_dedupe_seq_logic.py b/test_regress/t/t_dedupe_seq_logic.py new file mode 100755 index 000000000..32c90c0e9 --- /dev/null +++ b/test_regress/t/t_dedupe_seq_logic.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats"]) + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, Gate sigs deduped\s+(\d+)', 6) + +test.passes() diff --git a/test_regress/t/t_delay.pl b/test_regress/t/t_delay.pl deleted file mode 100755 index 71ee388a0..000000000 --- a/test_regress/t/t_delay.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['-Wno-STMTDLY -Wno-ASSIGNDLY --no-timing'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_delay.py b/test_regress/t/t_delay.py new file mode 100755 index 000000000..231b3a573 --- /dev/null +++ b/test_regress/t/t_delay.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['-Wno-STMTDLY -Wno-ASSIGNDLY --no-timing']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_delay_compare.pl b/test_regress/t/t_delay_compare.pl deleted file mode 100755 index 11677986e..000000000 --- a/test_regress/t/t_delay_compare.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ) if !$Self->{vlt}; - -ok(1); -1; diff --git a/test_regress/t/t_delay_compare.py b/test_regress/t/t_delay_compare.py new file mode 100755 index 000000000..1806fa071 --- /dev/null +++ b/test_regress/t/t_delay_compare.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +if not test.vlt: + test.execute() + +test.passes() diff --git a/test_regress/t/t_delay_incr.pl b/test_regress/t/t_delay_incr.pl deleted file mode 100755 index 453f07578..000000000 --- a/test_regress/t/t_delay_incr.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--binary --no-timing -Wno-STMTDLY -Wno-ASSIGNDLY'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_delay_incr.py b/test_regress/t/t_delay_incr.py new file mode 100755 index 000000000..621069809 --- /dev/null +++ b/test_regress/t/t_delay_incr.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--binary --no-timing -Wno-STMTDLY -Wno-ASSIGNDLY']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_delay_incr_timing.pl b/test_regress/t/t_delay_incr_timing.pl deleted file mode 100755 index 274248d41..000000000 --- a/test_regress/t/t_delay_incr_timing.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -$Self->{main_time_multiplier} = 10e-7 / 10e-9; - -top_filename("t/t_delay_incr.v"); - -compile( - timing_loop => 1, - verilator_flags2 => ['--binary --timing -Wno-ZERODLY'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_delay_incr_timing.py b/test_regress/t/t_delay_incr_timing.py new file mode 100755 index 000000000..eaed68537 --- /dev/null +++ b/test_regress/t/t_delay_incr_timing.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_delay_incr.v" +test.main_time_multiplier = 10e-7 / 10e-9 + +test.compile(timing_loop=True, verilator_flags2=['--binary --timing -Wno-ZERODLY']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_delay_stmtdly_bad.pl b/test_regress/t/t_delay_stmtdly_bad.pl deleted file mode 100755 index 59820b3fb..000000000 --- a/test_regress/t/t_delay_stmtdly_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_delay.v"); - -lint( - verilator_flags2 => ['--no-timing -Wall -Wno-DECLFILENAME'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_delay_stmtdly_bad.py b/test_regress/t/t_delay_stmtdly_bad.py new file mode 100755 index 000000000..a542f3311 --- /dev/null +++ b/test_regress/t/t_delay_stmtdly_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_delay.v" + +test.lint(verilator_flags2=['--no-timing -Wall -Wno-DECLFILENAME'], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_delay_timing.pl b/test_regress/t/t_delay_timing.pl deleted file mode 100755 index 6608321c0..000000000 --- a/test_regress/t/t_delay_timing.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -$Self->{main_time_multiplier} = 10e-7 / 10e-9; - -top_filename("t/t_delay.v"); - -compile( - timing_loop => 1, - verilator_flags2 => ['--timing -Wno-ZERODLY'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_delay_timing.py b/test_regress/t/t_delay_timing.py new file mode 100755 index 000000000..bcaa61195 --- /dev/null +++ b/test_regress/t/t_delay_timing.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_delay.v" +test.main_time_multiplier = 10e-7 / 10e-9 + +test.compile(timing_loop=True, verilator_flags2=['--timing -Wno-ZERODLY']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_delay_var.pl b/test_regress/t/t_delay_var.pl deleted file mode 100755 index 11677986e..000000000 --- a/test_regress/t/t_delay_var.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ) if !$Self->{vlt}; - -ok(1); -1; diff --git a/test_regress/t/t_delay_var.py b/test_regress/t/t_delay_var.py new file mode 100755 index 000000000..1806fa071 --- /dev/null +++ b/test_regress/t/t_delay_var.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +if not test.vlt: + test.execute() + +test.passes() diff --git a/test_regress/t/t_depth_flop.pl b/test_regress/t/t_depth_flop.pl deleted file mode 100755 index 8b4ad07ec..000000000 --- a/test_regress/t/t_depth_flop.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vltmt => 1); # Note issue shows up with --threads - -compile( - verilator_flags2 => ['--compiler clang -Wno-UNOPTTHREADS'], - threads => 2 - ); - -ok(1); -1; diff --git a/test_regress/t/t_depth_flop.py b/test_regress/t/t_depth_flop.py new file mode 100755 index 000000000..a38d51df9 --- /dev/null +++ b/test_regress/t/t_depth_flop.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vltmt') # Note issue shows up with --threads + +test.compile(verilator_flags2=['--compiler clang -Wno-UNOPTTHREADS'], threads=2) + +test.passes() diff --git a/test_regress/t/t_detectarray_1.pl b/test_regress/t/t_detectarray_1.pl deleted file mode 100755 index fe257bfdf..000000000 --- a/test_regress/t/t_detectarray_1.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["-Wno-UNOPTFLAT"] - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_detectarray_1.py b/test_regress/t/t_detectarray_1.py new file mode 100755 index 000000000..c37bc018e --- /dev/null +++ b/test_regress/t/t_detectarray_1.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["-Wno-UNOPTFLAT"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_detectarray_2.pl b/test_regress/t/t_detectarray_2.pl deleted file mode 100755 index fe257bfdf..000000000 --- a/test_regress/t/t_detectarray_2.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["-Wno-UNOPTFLAT"] - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_detectarray_2.py b/test_regress/t/t_detectarray_2.py new file mode 100755 index 000000000..c37bc018e --- /dev/null +++ b/test_regress/t/t_detectarray_2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["-Wno-UNOPTFLAT"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_detectarray_3.pl b/test_regress/t/t_detectarray_3.pl deleted file mode 100755 index 62f9f689d..000000000 --- a/test_regress/t/t_detectarray_3.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["-Wno-UNOPTFLAT -Wno-WIDTH"] - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_detectarray_3.py b/test_regress/t/t_detectarray_3.py new file mode 100755 index 000000000..bf411aade --- /dev/null +++ b/test_regress/t/t_detectarray_3.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["-Wno-UNOPTFLAT -Wno-WIDTH"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dfg_3676.pl b/test_regress/t/t_dfg_3676.pl deleted file mode 100755 index 84ae125be..000000000 --- a/test_regress/t/t_dfg_3676.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Geza Lore. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile(); - -ok(1); -1; diff --git a/test_regress/t/t_dfg_3676.py b/test_regress/t/t_dfg_3676.py new file mode 100755 index 000000000..0b27c3dc0 --- /dev/null +++ b/test_regress/t/t_dfg_3676.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_dfg_3679.pl b/test_regress/t/t_dfg_3679.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_dfg_3679.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_dfg_3679.py b/test_regress/t/t_dfg_3679.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_dfg_3679.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dfg_3726.pl b/test_regress/t/t_dfg_3726.pl deleted file mode 100755 index 84ae125be..000000000 --- a/test_regress/t/t_dfg_3726.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Geza Lore. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile(); - -ok(1); -1; diff --git a/test_regress/t/t_dfg_3726.py b/test_regress/t/t_dfg_3726.py new file mode 100755 index 000000000..0b27c3dc0 --- /dev/null +++ b/test_regress/t/t_dfg_3726.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_dfg_3817.pl b/test_regress/t/t_dfg_3817.pl deleted file mode 100755 index 31e4367f7..000000000 --- a/test_regress/t/t_dfg_3817.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile(); - -ok(1); -1; diff --git a/test_regress/t/t_dfg_3817.py b/test_regress/t/t_dfg_3817.py new file mode 100755 index 000000000..0b27c3dc0 --- /dev/null +++ b/test_regress/t/t_dfg_3817.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_dfg_3872.pl b/test_regress/t/t_dfg_3872.pl deleted file mode 100755 index 31e4367f7..000000000 --- a/test_regress/t/t_dfg_3872.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile(); - -ok(1); -1; diff --git a/test_regress/t/t_dfg_3872.py b/test_regress/t/t_dfg_3872.py new file mode 100755 index 000000000..0b27c3dc0 --- /dev/null +++ b/test_regress/t/t_dfg_3872.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_dfg_4104.pl b/test_regress/t/t_dfg_4104.pl deleted file mode 100755 index 32bdf873d..000000000 --- a/test_regress/t/t_dfg_4104.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile(); - -ok(1); -1; diff --git a/test_regress/t/t_dfg_4104.py b/test_regress/t/t_dfg_4104.py new file mode 100755 index 000000000..0b27c3dc0 --- /dev/null +++ b/test_regress/t/t_dfg_4104.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_dfg_4943.pl b/test_regress/t/t_dfg_4943.pl deleted file mode 100755 index 019703eb0..000000000 --- a/test_regress/t/t_dfg_4943.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile(); - -ok(1); -1; diff --git a/test_regress/t/t_dfg_4943.py b/test_regress/t/t_dfg_4943.py new file mode 100755 index 000000000..0b27c3dc0 --- /dev/null +++ b/test_regress/t/t_dfg_4943.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_dfg_circular.pl b/test_regress/t/t_dfg_circular.pl deleted file mode 100755 index a4e59f8b5..000000000 --- a/test_regress/t/t_dfg_circular.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Geza Lore. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["--dumpi-dfg 9"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_dfg_circular.py b/test_regress/t/t_dfg_circular.py new file mode 100755 index 000000000..ce29ad309 --- /dev/null +++ b/test_regress/t/t_dfg_circular.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--dumpi-dfg 9"]) + +test.passes() diff --git a/test_regress/t/t_dfg_inline_forced.pl b/test_regress/t/t_dfg_inline_forced.pl deleted file mode 100755 index 3d5530ff3..000000000 --- a/test_regress/t/t_dfg_inline_forced.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_dfg_inline_forced.py b/test_regress/t/t_dfg_inline_forced.py new file mode 100755 index 000000000..0b27c3dc0 --- /dev/null +++ b/test_regress/t/t_dfg_inline_forced.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_dfg_multidriver_dfg_bad.pl b/test_regress/t/t_dfg_multidriver_dfg_bad.pl deleted file mode 100755 index 9325bb095..000000000 --- a/test_regress/t/t_dfg_multidriver_dfg_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Geza Lore. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dfg_multidriver_dfg_bad.py b/test_regress/t/t_dfg_multidriver_dfg_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_dfg_multidriver_dfg_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dfg_multidriver_non_dfg.pl b/test_regress/t/t_dfg_multidriver_non_dfg.pl deleted file mode 100755 index 84ae125be..000000000 --- a/test_regress/t/t_dfg_multidriver_non_dfg.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Geza Lore. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile(); - -ok(1); -1; diff --git a/test_regress/t/t_dfg_multidriver_non_dfg.py b/test_regress/t/t_dfg_multidriver_non_dfg.py new file mode 100755 index 000000000..0b27c3dc0 --- /dev/null +++ b/test_regress/t/t_dfg_multidriver_non_dfg.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_dfg_peephole.pl b/test_regress/t/t_dfg_peephole.pl deleted file mode 100755 index 2017b0d09..000000000 --- a/test_regress/t/t_dfg_peephole.pl +++ /dev/null @@ -1,99 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Geza Lore. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -my $root = ".."; - -if (!-r "$root/.git") { - skip("Not in a git repository"); -} else { - $Self->{sim_time} = 2000000; - - # Read optimizations - my @optimizations = (); - { - my $hdrFile = "../src/V3DfgPeephole.h"; - my $hdrFh = IO::File->new("<$hdrFile") or error("$! $hdrFile"); - my $prevOpt = ""; - my $lineno = 0; - while (defined(my $line = $hdrFh->getline)) { - $lineno = $lineno + 1; - next if $line !~ /^\s*_FOR_EACH_DFG_PEEPHOLE_OPTIMIZATION_APPLY\(macro, (\w+)\)/; - my $opt = $1; - error("$hdrFile:$linenno: '$opt; is not in sorted order") if $prevOpt gt $opt; - $prevOpt = $opt; - push @optimizations, $opt; - } - error("no optimizations defined in $hdrFile") if scalar @optimizations == 0; - } - - # Generate the equivalence checks and declaration boilerplate - my $rdFile = "$Self->{top_filename}"; - my $plistFile = "$Self->{obj_dir}/portlist.vh"; - my $pdeclFile = "$Self->{obj_dir}/portdecl.vh"; - my $checkFile = "$Self->{obj_dir}/checks.h"; - my $rdFh = IO::File->new("<$rdFile") or error("$! $rdFile"); - my $plistFh = IO::File->new(">$plistFile") or error("$! $plistFile"); - my $pdeclFh = IO::File->new(">$pdeclFile") or error("$! $pdeclFile"); - my $checkFh = IO::File->new(">$checkFile") or error("$! $checkFile"); - while (defined(my $line = $rdFh->getline)) { - next if $line !~ /^\s*.*`signal\((\w+),/; - my $signal = $1; - print $plistFh "$signal,\n"; - print $pdeclFh "output $signal;\n"; - print $checkFh "if (ref.$signal != opt.$signal) {\n"; - print $checkFh " std::cout << \"Mismatched $signal\" << std::endl;\n"; - print $checkFh " std::cout << \"Ref: 0x\" << std::hex << (ref.$signal + 0) << std::endl;\n"; - print $checkFh " std::cout << \"Opt: 0x\" << std::hex << (opt.$signal + 0) << std::endl;\n"; - print $checkFh " std::exit(1);\n"; - print $checkFh "}\n"; - } - close $rdFile; - close $wrFile; - - - # Compile un-optimized - compile( - verilator_flags2 => ["--stats", "--build", "-fno-dfg", "+incdir+$Self->{obj_dir}", - "-Mdir", "$Self->{obj_dir}/obj_ref", "--prefix", "Vref"], - ); - - # Compile optimized - also builds executable - compile( - verilator_flags2 => ["--stats", "--build", "--exe", "+incdir+$Self->{obj_dir}", - "-Mdir", "$Self->{obj_dir}/obj_opt", "--prefix", "Vopt", - "-fno-const-before-dfg", # Otherwise V3Const makes testing painful - "--dump-dfg", # To fill code coverage - "-CFLAGS \"-I .. -I ../obj_ref\"", - "../obj_ref/Vref__ALL.a", - "../../t/$Self->{name}.cpp"], - ); - - # Execute test to check equivalence - execute( - executable => "$Self->{obj_dir}/obj_opt/Vopt", - ); - - sub check { - my $name = shift; - $name = lc $name; - $name =~ s/_/ /g; - file_grep("$Self->{obj_dir}/obj_opt/Vopt__stats.txt", qr/DFG\s+(pre|post) inline Peephole, ${name}\s+([1-9]\d*)/); - } - - # Check all optimizations defined in - foreach my $opt (@optimizations) { - check($opt); - } -} - -ok(1); -1; diff --git a/test_regress/t/t_dfg_peephole.py b/test_regress/t/t_dfg_peephole.py new file mode 100755 index 000000000..dcb2cae87 --- /dev/null +++ b/test_regress/t/t_dfg_peephole.py @@ -0,0 +1,106 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.sim_time = 2000000 + +root = ".." + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +# Read optimizations +optimizations = [] + +hdrFile = "../src/V3DfgPeephole.h" +with open(hdrFile, 'r', encoding="utf8") as hdrFh: + prevOpt = "" + lineno = 0 + for line in hdrFh: + lineno += 1 + m = re.search(r'^\s*_FOR_EACH_DFG_PEEPHOLE_OPTIMIZATION_APPLY\(macro, (\w+)\)', line) + if not m: + continue + opt = m.group(1) + if prevOpt > opt: + test.error(hdrFile + ":" + str(lineno) + ": '" + opt + "; is not in sorted order") + prevOpt = opt + optimizations.append(opt) + +if len(optimizations) < 1: + test.error("no optimizations defined in " + hdrFile) + +# Generate the equivalence checks and declaration boilerplate +rdFile = test.top_filename +plistFile = test.obj_dir + "/portlist.vh" +pdeclFile = test.obj_dir + "/portdecl.vh" +checkFile = test.obj_dir + "/checks.h" +with open(rdFile, 'r', encoding="utf8") as rdFh, \ + open(plistFile, 'w', encoding="utf8") as plistFh, \ + open(pdeclFile, 'w', encoding="utf8") as pdeclFh, \ + open(checkFile, 'w', encoding="utf8") as checkFh: + for line in rdFh: + m = re.search(r'^\s*.*`signal\((\w+),', line) + if not m: + continue + sig = m.group(1) + plistFh.write(sig + ",\n") + pdeclFh.write("output " + sig + ";\n") + checkFh.write("if (ref." + sig + " != opt." + sig + ") {\n") + checkFh.write(" std::cout << \"Mismatched " + sig + "\" << std::endl;\n") + checkFh.write(" std::cout << \"Ref: 0x\" << std::hex << (ref." + sig + + " + 0) << std::endl;\n") + checkFh.write(" std::cout << \"Opt: 0x\" << std::hex << (opt." + sig + + " + 0) << std::endl;\n") + checkFh.write(" std::exit(1);\n") + checkFh.write("}\n") + +# Compile un-optimized +test.compile(verilator_flags2=[ + "--stats", + "--build", + "-fno-dfg", + "+incdir+" + test.obj_dir, + "-Mdir", test.obj_dir + "/obj_ref", + "--prefix", "Vref" +]) # yapf:disable + +# Compile optimized - also builds executable +test.compile(verilator_flags2=[ + "--stats", + "--build", + "--exe", + "+incdir+" + test.obj_dir, + "-Mdir", test.obj_dir + "/obj_opt", + "--prefix", "Vopt", + "-fno-const-before-dfg", # Otherwise V3Const makes testing painful + "--dump-dfg", # To fill code coverage + "-CFLAGS \"-I .. -I ../obj_ref\"", + "../obj_ref/Vref__ALL.a", + "../../t/" + test.name + ".cpp" +]) # yapf:disable + +# Execute test to check equivalence +test.execute(executable=test.obj_dir + "/obj_opt/Vopt") + + +def check(name): + name = name.lower() + name = re.sub(r'_', ' ', name) + test.file_grep(test.obj_dir + "/obj_opt/Vopt__stats.txt", + r'DFG\s+(pre|post) inline Peephole, ' + name + r'\s+([1-9]\d*)') + + +# Check all optimizations defined in +for opt in optimizations: + check(opt) + +test.passes() diff --git a/test_regress/t/t_dfg_peephole.v b/test_regress/t/t_dfg_peephole.v index b6745ef93..a453cc51a 100644 --- a/test_regress/t/t_dfg_peephole.v +++ b/test_regress/t/t_dfg_peephole.v @@ -7,11 +7,11 @@ `define signal(name, expr) wire [$bits(expr)-1:0] ``name = expr module t ( -`include "portlist.vh" // Boilerplate generated by t_dfg_peephole.pl +`include "portlist.vh" // Boilerplate generated by t_dfg_peephole.py rand_a, rand_b, srand_a, srand_b ); -`include "portdecl.vh" // Boilerplate generated by t_dfg_peephole.pl +`include "portdecl.vh" // Boilerplate generated by t_dfg_peephole.py input rand_a; input rand_b; diff --git a/test_regress/t/t_dfg_regularize_circular.pl b/test_regress/t/t_dfg_regularize_circular.pl deleted file mode 100755 index 3d5530ff3..000000000 --- a/test_regress/t/t_dfg_regularize_circular.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_dfg_regularize_circular.py b/test_regress/t/t_dfg_regularize_circular.py new file mode 100755 index 000000000..0b27c3dc0 --- /dev/null +++ b/test_regress/t/t_dfg_regularize_circular.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_dfg_regularize_driver_of_sc_var.pl b/test_regress/t/t_dfg_regularize_driver_of_sc_var.pl deleted file mode 100755 index 9158675cc..000000000 --- a/test_regress/t/t_dfg_regularize_driver_of_sc_var.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["--sc"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_dfg_regularize_driver_of_sc_var.py b/test_regress/t/t_dfg_regularize_driver_of_sc_var.py new file mode 100755 index 000000000..01c227501 --- /dev/null +++ b/test_regress/t/t_dfg_regularize_driver_of_sc_var.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--sc"]) + +test.passes() diff --git a/test_regress/t/t_dfg_stats_patterns_post_inline.pl b/test_regress/t/t_dfg_stats_patterns_post_inline.pl deleted file mode 100755 index d417bbaee..000000000 --- a/test_regress/t/t_dfg_stats_patterns_post_inline.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_dfg_stats_patterns.v"); - -compile( - verilator_flags2 => ["--stats --no-skip-identical -fno-dfg-pre-inline"], - ); - -my $f = glob_one("$Self->{obj_dir}/$Self->{vm_prefix}__stats_dfg_patterns*"); -files_identical($f, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_dfg_stats_patterns_post_inline.py b/test_regress/t/t_dfg_stats_patterns_post_inline.py new file mode 100755 index 000000000..0813e38de --- /dev/null +++ b/test_regress/t/t_dfg_stats_patterns_post_inline.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_dfg_stats_patterns.v" + +test.compile(verilator_flags2=["--stats --no-skip-identical -fno-dfg-pre-inline"]) + +fn = test.glob_one(test.obj_dir + "/" + test.vm_prefix + "__stats_dfg_patterns*") +test.files_identical(fn, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dfg_stats_patterns_pre_inline.pl b/test_regress/t/t_dfg_stats_patterns_pre_inline.pl deleted file mode 100755 index c457e5470..000000000 --- a/test_regress/t/t_dfg_stats_patterns_pre_inline.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_dfg_stats_patterns.v"); - -compile( - verilator_flags2 => ["--stats --no-skip-identical -fno-dfg-post-inline"], - ); - -my $f = glob_one("$Self->{obj_dir}/$Self->{vm_prefix}__stats_dfg_patterns*"); -files_identical($f, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_dfg_stats_patterns_pre_inline.py b/test_regress/t/t_dfg_stats_patterns_pre_inline.py new file mode 100755 index 000000000..4fac195a5 --- /dev/null +++ b/test_regress/t/t_dfg_stats_patterns_pre_inline.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_dfg_stats_patterns.v" + +test.compile(verilator_flags2=["--stats --no-skip-identical -fno-dfg-post-inline"]) + +fn = test.glob_one(test.obj_dir + "/" + test.vm_prefix + "__stats_dfg_patterns*") +test.files_identical(fn, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dfg_unhandled.pl b/test_regress/t/t_dfg_unhandled.pl deleted file mode 100755 index f728d1ac4..000000000 --- a/test_regress/t/t_dfg_unhandled.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Geza Lore. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -file_grep($Self->{stats}, qr/Optimizations, DFG pre inline Ast2Dfg, non-representable \(impure\)\s+(\d+)/, 1); - -ok(1); -1; diff --git a/test_regress/t/t_dfg_unhandled.py b/test_regress/t/t_dfg_unhandled.py new file mode 100755 index 000000000..f60c4d682 --- /dev/null +++ b/test_regress/t/t_dfg_unhandled.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--stats"]) + +test.file_grep(test.stats, + r'Optimizations, DFG pre inline Ast2Dfg, non-representable \(impure\)\s+(\d+)', 1) + +test.passes() diff --git a/test_regress/t/t_difftree.pl b/test_regress/t/t_difftree.pl deleted file mode 100755 index da5f5e571..000000000 --- a/test_regress/t/t_difftree.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(dist => 1); - -if (!-x "$ENV{VERILATOR_ROOT}/bin/verilator_difftree") { - skip("No verilator_difftree available") -} -else { - run(cmd => ["cd $Self->{obj_dir} && $ENV{VERILATOR_ROOT}/bin/verilator_difftree" - . " $Self->{t_dir}/t_difftree.a.tree $Self->{t_dir}/t_difftree.b.tree > diff.log"], - check_finished => 0); - - files_identical("$Self->{obj_dir}/diff.log", $Self->{golden_filename}, 'logfile'); -} - -ok(1); - -1; diff --git a/test_regress/t/t_difftree.py b/test_regress/t/t_difftree.py new file mode 100755 index 000000000..38ba0f004 --- /dev/null +++ b/test_regress/t/t_difftree.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +if not os.path.exists(os.environ["VERILATOR_ROOT"] + "/bin/verilator_difftree"): + test.skip("No verilator_difftree available") + +test.run(cmd=[ + "cd " + test.obj_dir + " && " + os.environ["VERILATOR_ROOT"] + "/bin/verilator_difftree", + test.t_dir + "/t_difftree.a.tree", test.t_dir + "/t_difftree.b.tree > diff.log" +], + check_finished=False) + +test.files_identical(test.obj_dir + "/diff.log", test.golden_filename, 'logfile') + +test.passes() diff --git a/test_regress/t/t_disable.pl b/test_regress/t/t_disable.pl deleted file mode 100755 index e68534982..000000000 --- a/test_regress/t/t_disable.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ['--lint-only --timing'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_disable.py b/test_regress/t/t_disable.py new file mode 100755 index 000000000..cf9cba66e --- /dev/null +++ b/test_regress/t/t_disable.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=['--lint-only --timing'], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_disable_fork1.pl b/test_regress/t/t_disable_fork1.pl deleted file mode 100755 index 21a2189cc..000000000 --- a/test_regress/t/t_disable_fork1.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_disable_fork1.py b/test_regress/t/t_disable_fork1.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_disable_fork1.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_disable_fork2.pl b/test_regress/t/t_disable_fork2.pl deleted file mode 100755 index 21a2189cc..000000000 --- a/test_regress/t/t_disable_fork2.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_disable_fork2.py b/test_regress/t/t_disable_fork2.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_disable_fork2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_disable_fork3.pl b/test_regress/t/t_disable_fork3.pl deleted file mode 100755 index 21a2189cc..000000000 --- a/test_regress/t/t_disable_fork3.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_disable_fork3.py b/test_regress/t/t_disable_fork3.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_disable_fork3.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_disable_fork_notiming.pl b/test_regress/t/t_disable_fork_notiming.pl deleted file mode 100755 index 4994b95cb..000000000 --- a/test_regress/t/t_disable_fork_notiming.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint( - expect_filename => $Self->{golden_filename}, - v_flags2 => ["--no-timing"], - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_disable_fork_notiming.py b/test_regress/t/t_disable_fork_notiming.py new file mode 100755 index 000000000..01b7497f3 --- /dev/null +++ b/test_regress/t/t_disable_fork_notiming.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(expect_filename=test.golden_filename, v_flags2=["--no-timing"], fails=True) + +test.passes() diff --git a/test_regress/t/t_disable_iff_multi_bad.pl b/test_regress/t/t_disable_iff_multi_bad.pl deleted file mode 100755 index 7fdfc93e0..000000000 --- a/test_regress/t/t_disable_iff_multi_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--timing"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_disable_iff_multi_bad.py b/test_regress/t/t_disable_iff_multi_bad.py new file mode 100755 index 000000000..7bf848e53 --- /dev/null +++ b/test_regress/t/t_disable_iff_multi_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--timing"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_display.pl b/test_regress/t/t_display.pl deleted file mode 100755 index 0dd6234fe..000000000 --- a/test_regress/t/t_display.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_display.py b/test_regress/t/t_display.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_display.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_display_bad.pl b/test_regress/t/t_display_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_display_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_display_bad.py b/test_regress/t/t_display_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_display_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_display_concat.pl b/test_regress/t/t_display_concat.pl deleted file mode 100755 index ae71f01e3..000000000 --- a/test_regress/t/t_display_concat.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_display_concat.py b/test_regress/t/t_display_concat.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_display_concat.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_display_concat2.pl b/test_regress/t/t_display_concat2.pl deleted file mode 100755 index 56cc415df..000000000 --- a/test_regress/t/t_display_concat2.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_display_concat2.py b/test_regress/t/t_display_concat2.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_display_concat2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_display_cwide_bad.pl b/test_regress/t/t_display_cwide_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_display_cwide_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_display_cwide_bad.py b/test_regress/t/t_display_cwide_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_display_cwide_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_display_esc_bad.pl b/test_regress/t/t_display_esc_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_display_esc_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_display_esc_bad.py b/test_regress/t/t_display_esc_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_display_esc_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_display_impure.pl b/test_regress/t/t_display_impure.pl deleted file mode 100755 index eb8872155..000000000 --- a/test_regress/t/t_display_impure.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_display_impure.py b/test_regress/t/t_display_impure.py new file mode 100755 index 000000000..90d5ab862 --- /dev/null +++ b/test_regress/t/t_display_impure.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_display_io.pl b/test_regress/t/t_display_io.pl deleted file mode 100755 index 6e1338f8e..000000000 --- a/test_regress/t/t_display_io.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_display_io.py b/test_regress/t/t_display_io.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_display_io.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_display_l.pl b/test_regress/t/t_display_l.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_display_l.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_display_l.py b/test_regress/t/t_display_l.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_display_l.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_display_mcd.pl b/test_regress/t/t_display_mcd.pl deleted file mode 100755 index 0dd6234fe..000000000 --- a/test_regress/t/t_display_mcd.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_display_mcd.py b/test_regress/t/t_display_mcd.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_display_mcd.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_display_merge.pl b/test_regress/t/t_display_merge.pl deleted file mode 100755 index f0c4999a0..000000000 --- a/test_regress/t/t_display_merge.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -file_grep("$Self->{obj_dir}/$Self->{vm_prefix}__stats.txt", - qr/Node count, DISPLAY \s+ 44 \s+ 27 \s+ 27 \s+ 6/); - -ok(1); -1; diff --git a/test_regress/t/t_display_merge.py b/test_regress/t/t_display_merge.py new file mode 100755 index 000000000..03f439c26 --- /dev/null +++ b/test_regress/t/t_display_merge.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats"]) + +test.execute(expect_filename=test.golden_filename) + +test.file_grep(test.obj_dir + "/" + test.vm_prefix + "__stats.txt", + r'Node count, DISPLAY \s+ 44 \s+ 27 \s+ 27 \s+ 6') + +test.passes() diff --git a/test_regress/t/t_display_noopt.pl b/test_regress/t/t_display_noopt.pl deleted file mode 100755 index 06f19aed5..000000000 --- a/test_regress/t/t_display_noopt.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_display.v"); -golden_filename("t/t_display.out"); - -compile( - verilator_flags2 => ["-O0"], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_display_noopt.py b/test_regress/t/t_display_noopt.py new file mode 100755 index 000000000..9b159b6ba --- /dev/null +++ b/test_regress/t/t_display_noopt.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_display.v" +test.golden_filename = "t/t_display.out" + +test.compile(verilator_flags2=["-O0"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_display_qqq.pl b/test_regress/t/t_display_qqq.pl deleted file mode 100755 index de696963c..000000000 --- a/test_regress/t/t_display_qqq.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_display_qqq.py b/test_regress/t/t_display_qqq.py new file mode 100755 index 000000000..97abb660e --- /dev/null +++ b/test_regress/t/t_display_qqq.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_display_real.pl b/test_regress/t/t_display_real.pl deleted file mode 100755 index 56cc415df..000000000 --- a/test_regress/t/t_display_real.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_display_real.py b/test_regress/t/t_display_real.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_display_real.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_display_real_noopt.pl b/test_regress/t/t_display_real_noopt.pl deleted file mode 100755 index c01e19b10..000000000 --- a/test_regress/t/t_display_real_noopt.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_display_real.v"); -golden_filename("t/t_display_real.out"); - -compile( - verilator_flags2 => ["-O0"], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_display_real_noopt.py b/test_regress/t/t_display_real_noopt.py new file mode 100755 index 000000000..ad0f55e3e --- /dev/null +++ b/test_regress/t/t_display_real_noopt.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_display_real.v" +test.golden_filename = "t/t_display_real.out" + +test.compile(verilator_flags2=["-O0"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_display_realtime.pl b/test_regress/t/t_display_realtime.pl deleted file mode 100755 index 9a67c9c44..000000000 --- a/test_regress/t/t_display_realtime.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); - -1; diff --git a/test_regress/t/t_display_realtime.py b/test_regress/t/t_display_realtime.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_display_realtime.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_display_recurse.pl b/test_regress/t/t_display_recurse.pl deleted file mode 100755 index e48bd2921..000000000 --- a/test_regress/t/t_display_recurse.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_display_recurse.py b/test_regress/t/t_display_recurse.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_display_recurse.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_display_signed.pl b/test_regress/t/t_display_signed.pl deleted file mode 100755 index 56cc415df..000000000 --- a/test_regress/t/t_display_signed.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_display_signed.py b/test_regress/t/t_display_signed.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_display_signed.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_display_signed_noopt.pl b/test_regress/t/t_display_signed_noopt.pl deleted file mode 100755 index bda9253e2..000000000 --- a/test_regress/t/t_display_signed_noopt.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_display_signed.v"); -golden_filename("t/t_display_signed.out"); - -compile( - verilator_flags2 => ["-O0"], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_display_signed_noopt.py b/test_regress/t/t_display_signed_noopt.py new file mode 100755 index 000000000..e80552d48 --- /dev/null +++ b/test_regress/t/t_display_signed_noopt.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_display_signed.v" +test.golden_filename = "t/t_display_signed.out" + +test.compile(verilator_flags2=["-O0"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_display_string.pl b/test_regress/t/t_display_string.pl deleted file mode 100755 index 56cc415df..000000000 --- a/test_regress/t/t_display_string.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_display_string.py b/test_regress/t/t_display_string.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_display_string.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_display_time.pl b/test_regress/t/t_display_time.pl deleted file mode 100755 index 56cc415df..000000000 --- a/test_regress/t/t_display_time.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_display_time.py b/test_regress/t/t_display_time.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_display_time.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_display_type_bad.pl b/test_regress/t/t_display_type_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_display_type_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_display_type_bad.py b/test_regress/t/t_display_type_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_display_type_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_display_wide.pl b/test_regress/t/t_display_wide.pl deleted file mode 100755 index 56cc415df..000000000 --- a/test_regress/t/t_display_wide.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_display_wide.py b/test_regress/t/t_display_wide.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_display_wide.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dist_attributes_bad.pl b/test_regress/t/t_dist_attributes_bad.pl deleted file mode 100755 index 35579d8f9..000000000 --- a/test_regress/t/t_dist_attributes_bad.pl +++ /dev/null @@ -1,102 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -use Cwd qw(abs_path); -use JSON::PP; -use IO::File; - -scenarios(dist => 1); - -my $root = ".."; - -if ($ENV{VERILATOR_TEST_NO_ATTRIBUTES}) { - skip("Skipping due to VERILATOR_TEST_NO_ATTRIBUTES"); -} elsif (!-r "$root/.git") { - skip("Not in a git repository"); -} else { - check(); -} - -sub gen_compile_commands_json { - my $json = JSON::PP->new->utf8->pretty; - $json->canonical(); # Sort hash keys on ouptut - - my $root_dir = abs_path(".."); - my $srcs_dir = abs_path("./t/t_dist_attributes"); - my @common_args = ("clang++", - "-std=c++14", - "-I$root_dir/include", - "-I$root_dir/src", - "-c"); - - my $ccjson = [ - {"directory" => "$srcs_dir", - "file" => "$srcs_dir/mt_enabled.cpp", - "output" => undef, - "arguments" => [@common_args]}, - {"directory" => "$srcs_dir", - "file" => "$srcs_dir/mt_disabled.cpp", - "output" => undef, - "arguments" => [@common_args]}, - ]; - - my @srcfiles; - foreach my $entry (@$ccjson) { - # Add "output" key - ($entry->{"output"} = $entry->{"file"}) =~ s/\.cpp$/.o/; - # Add "-o src.o src.cpp" arguments - push @{$entry->{"arguments"}}, ("-o", $entry->{"output"}, $entry->{"file"}); - - push @srcfiles, $entry->{"file"}; - } - - return ( - \@srcfiles, - $json->encode($ccjson) - ); -} - -sub check { - my $root = abs_path(".."); - my $ccjson_file = "$Self->{obj_dir}/compile_commands.json"; - my ($srcfiles, $ccjson) = gen_compile_commands_json(); - my $srcfiles_str = join(" ", @$srcfiles); - { - my $fh = IO::File->new(">$ccjson_file") or die "%Error: $! $ccjson_file"; - print $fh $ccjson; - $fh->close(); - } - - sub run_clang_check { - { - my $cmd = qq{python3 -c "from clang.cindex import Index; index = Index.create(); print(\\"Clang imported\\")";}; - print "\t$cmd\n" if $::Debug; - my $out = `$cmd`; - if (!$out || $out !~ /Clang imported/) { skip("No libclang installed\n"); return 1; } - } - run(logfile => $Self->{run_log_filename}, - tee => 1, - # With `--verilator-root` set to the current directory - # (i.e. `test_regress`) the script will skip annotation issues in - # headers from the `../include` directory. - cmd => ["python3", - "$root/nodist/clang_check_attributes", - "--verilator-root=.", - "--compile-commands-dir=$Self->{obj_dir}", - "$srcfiles_str"]); - - files_identical($Self->{run_log_filename}, $Self->{golden_filename}); - } - - run_clang_check(); -} - -ok(1); -1; diff --git a/test_regress/t/t_dist_attributes_bad.py b/test_regress/t/t_dist_attributes_bad.py new file mode 100755 index 000000000..cfcd6e939 --- /dev/null +++ b/test_regress/t/t_dist_attributes_bad.py @@ -0,0 +1,82 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import json +import vltest_bootstrap + +test.scenarios('dist') + +root = ".." + + +def have_clang_check(): + cmd = 'python3 -c "from clang.cindex import Index; index = Index.create(); print(\\"Clang imported\\")";' + if test.verbose: + print("\t" + cmd) + nout = test.run_capture(cmd, check=False) + if not nout or not re.search(r'Clang imported', nout): + return False + return True + + +if 'VERILATOR_TEST_NO_ATTRIBUTES' in os.environ: + test.skip("Skipping due to VERILATOR_TEST_NO_ATTRIBUTES") +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") +if not have_clang_check(): + test.skip("No libclang installed\n") + +aroot = os.path.abspath(root) +ccjson_file = test.obj_dir + "/compile_commands.json" + +aroot_dir = os.path.abspath(root) +srcs_dir = os.path.abspath("./t/t_dist_attributes") +common_args = [ + "clang++", "-std=c++14", "-I" + aroot_dir + "/include", "-I" + aroot_dir + "/src", "-c" +] + +ccjson = [ + { + "directory": srcs_dir, + "file": srcs_dir + "/mt_enabled.cpp", + "output": srcs_dir + "/mt_enabled.o", + "arguments": + [*common_args, "-o", srcs_dir + "/mt_enabled.o", srcs_dir + "/mt_enabled.cpp"] + }, + { + "directory": srcs_dir, + "file": srcs_dir + "/mt_disabled.cpp", + "output": srcs_dir + "/mt_disabled.o", + "arguments": + [*common_args, "-o", srcs_dir + "/mt_enabled.o", srcs_dir + "/mt_enabled.cpp"] + }, +] +ccjson_str = json.dumps(ccjson) + +srcfiles = [] +for entry in ccjson: + srcfiles.append(entry["file"]) +srcfiles_str = ' '.join(srcfiles) + +test.write_wholefile(ccjson_file, ccjson_str) + +test.run( + logfile=test.run_log_filename, + tee=True, + # With `--verilator-root` set to the current directory + # (i.e. `test_regress`) the script will skip annotation issues in + # headers from the `../include` directory. + cmd=[ + "python3", aroot + "/nodist/clang_check_attributes", "--verilator-root=.", + "--compile-commands-dir=" + test.obj_dir, srcfiles_str + ]) + +test.files_identical(test.run_log_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dist_cinclude.pl b/test_regress/t/t_dist_cinclude.pl deleted file mode 100755 index f006eae01..000000000 --- a/test_regress/t/t_dist_cinclude.pl +++ /dev/null @@ -1,61 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -use IO::File; -use File::Spec::Functions 'catfile'; - -scenarios(dist => 1); - -my $root = ".."; -my $Debug; - -if (!-r catfile($root, ".git")) { - skip("Not in a git repository"); -} else { - ### Must trim output before and after our file list - my $files = `cd $root && git ls-files --exclude-standard`; - print "ST $files\n" if $Debug; - foreach my $file (split /\n/, $files) { - next if $file =~ m!include/vltstd/vpi_user.h!; # IEEE Standard file - can't change it - next if $file =~ m!include/gtkwave/!; # Standard file - can't change it - my $filename = catfile($root, $file); - next if !-r $filename; - @lines = split /\n/, file_contents($filename); - @include_lines = grep(/include/, @lines); - foreach my $line (@include_lines) { - my $hit; - $hit = 1 if $line =~ /\bassert\.h/; - $hit = 1 if $line =~ /\bctype\.h/; - $hit = 1 if $line =~ /\berrno\.h/; - $hit = 1 if $line =~ /\bfloat\.h/; - $hit = 1 if $line =~ /\blimits\.h/; - $hit = 1 if $line =~ /\blocale\.h/; - $hit = 1 if $line =~ /\bmath\.h/; - $hit = 1 if $line =~ /\bsetjmp\.h/; - $hit = 1 if $line =~ /\bsignal\.h/; - $hit = 1 if $line =~ /\bstdarg\.h/; - $hit = 1 if $line =~ /\bstdbool\.h/; - $hit = 1 if $line =~ /\bstddef\.h/; - #Not yet: $hit = 1 if $line =~ /\bstdint\.h/; - $hit = 1 if $line =~ /\bstdio\.h/; - $hit = 1 if $line =~ /\bstdlib\.h/; - $hit = 1 if $line =~ /\bstring\.h/; - $hit = 1 if $line =~ /\btime\.h/ && $line !~ m!sys/time.h!; - next if !$hit; - $names{"$filename: $line"} = 1; - } - } - if (keys %names) { - error("Files like stdint.h instead of cstdint:\n ", join("\n ", sort keys %names)); - } -} - -ok(1); -1; diff --git a/test_regress/t/t_dist_cinclude.py b/test_regress/t/t_dist_cinclude.py new file mode 100755 index 000000000..a7ee86009 --- /dev/null +++ b/test_regress/t/t_dist_cinclude.py @@ -0,0 +1,56 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +root = ".." + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +### Must trim output before and after our file list +cmd = "cd " + root + " && git ls-files --exclude-standard" +files = test.run_capture(cmd) +if test.verbose: + print("ST " + files) +names = {} +for filename in files.split(): + if "include/vltstd/vpi_user.h" in filename: # IEEE Standard file - can't change it + continue + if "include/gtkwave/" in filename: # Standard file - can't change it + continue + filename = os.path.join(root, filename) + if not os.path.exists(filename): + continue + with open(filename, 'r', encoding='latin-1') as fh: + for line in fh: + if "include" not in line: + continue + line = line.rstrip() + hit = (re.search(r'\bassert\.h', line) or re.search(r'\bctype\.h', line) + or re.search(r'\berrno\.h', line) or re.search(r'\bfloat\.h', line) + or re.search(r'\blimits\.h', line) or re.search(r'\blocale\.h', line) + or re.search(r'\bmath\.h', line) or re.search(r'\bsetjmp\.h', line) + or re.search(r'\bsignal\.h', line) or re.search(r'\bstdarg\.h', line) + or re.search(r'\bstdbool\.h', line) or re.search(r'\bstddef\.h', line) + or re.search(r'\bstdio\.h', line) or re.search(r'\bstdlib\.h', line) + or re.search(r'\bstring\.h', line) + or (re.search(r'\btime\.h', line) and not re.search(r'sys/time.h', line))) + #Not yet: r'\bstdint\.h' + if not hit: + continue + names[filename + ": " + line] = True + +if len(names): + test.error("Files like stdint.h instead of cstdint:\n " + + "\n ".join(sorted(names.keys()))) + +test.passes() diff --git a/test_regress/t/t_dist_contributors.pl b/test_regress/t/t_dist_contributors.pl deleted file mode 100755 index a4b4db5a4..000000000 --- a/test_regress/t/t_dist_contributors.pl +++ /dev/null @@ -1,85 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -use IO::File; -use strict; -use vars qw($Self); - -scenarios(dist => 1); - -my $root = ".."; -my $Debug; -my %Contributors = ('github action' => 1); -my %Authors; - -if ($ENV{VERILATOR_TEST_NO_CONTRIBUTORS}) { - skip("Skipping due to VERILATOR_TEST_NO_CONTRIBUTORS"); -} elsif (!-r "$root/.git") { - skip("Not in a git repository"); -} else { - check(); -} - -ok(1); -1; - -sub check { - read_contributors("$root/docs/CONTRIBUTORS"); - read_user(); - read_authors(); - for my $author (sort keys %Authors) { - print "Check: $author\n" if $Self->{verbose}; - if (!$Contributors{$author}) { - error("Certify your contribution by sorted-inserting '$author' into docs/CONTRIBUTORS.\n" - . " If '$author' is not your real name, please fix 'name=' in ~/.gitconfig\n" - . " Also check your https://github.com account's Settings->Profile->Name\n" - . " matches your ~/.gitconfig 'name='.\n"); - } - } -} - -sub read_contributors { - my $filename = shift; - my $fh = IO::File->new("<$filename") - or error("$! $filename"); - # Assumes git .mailmap format - while (my $line = ($fh && $fh->getline)) { - while ($line =~ /(.*)/g) { - $line =~ s/ *<[^>]*>//; - $Contributors{$1} = 1; - } - } -} - -sub read_user { - my $changes = `cd $root ; git diff-index --quiet HEAD --`; - chomp $changes; - if (!$changes) { - print "No git changes\n" if $Self->{verbose}; - } else { - # Uncommitted changes, so check the user's git name - my $user = `git config user.name`; - chomp $user; - my $email = `git config user.email`; - chomp $email; - if ($user && $email) { - $Authors{"$user <$email>"} = 1; - } - } -} - -sub read_authors { - # Check recent commits in case did commit - my $git_auths = `git log '--pretty=format:%aN <%aE>' | head -5`; - foreach my $line (split /\n/, $git_auths) { - $line =~ s/ *<[^>]*>//; - $Authors{$line} = 1; - } -} diff --git a/test_regress/t/t_dist_contributors.py b/test_regress/t/t_dist_contributors.py new file mode 100755 index 000000000..f1a1c4664 --- /dev/null +++ b/test_regress/t/t_dist_contributors.py @@ -0,0 +1,75 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +root = ".." + +Contributors = {'github action': True} +Authors = {} + + +def read_contributors(filename): + with open(filename, 'r', encoding="utf8") as fh: + # Assumes git .mailmap format + for line in fh: + line = line.rstrip() + line = re.sub(r' *<[^>]*>', '', line) + Contributors[line] = True + + +def read_user(): + cmd = "cd " + root + " && git diff-index --quiet HEAD --" + changes = test.run_capture(cmd, check=False) + changes = changes.rstrip() + if changes == "": + if test.verbose: + print("No git changes") + else: + # Uncommitted changes, so check the user's git name + user = test.run_capture("git config user.name") + user = user.rstrip() + if user: + Authors[user] = True + + +def read_authors(): + # Check recent commits in case did commit + cmd = "git log '--pretty=format:%aN <%aE>' | head -5" + git_auths = test.run_capture(cmd) + for line in git_auths.splitlines(): + line = re.sub(r' *<[^>]*>', '', line) + Authors[line] = True + + +def check(): + read_contributors(root + "/docs/CONTRIBUTORS") + read_user() + read_authors() + for author in sorted(Authors.keys()): + if test.verbose: + print("Check: " + author) + if author not in Contributors: + test.error("Certify your contribution by sorted-inserting '" + author + + "' into docs/CONTRIBUTORS.\n" + " If '" + author + + "' is not your real name, please fix 'name=' in ~/.gitconfig\n" + " Also check your https://github.com account's Settings->Profile->Name\n" + " matches your ~/.gitconfig 'name='.\n") + + +if 'VERILATOR_TEST_NO_CONTRIBUTORS' in os.environ: + test.skip("Skipping due to VERILATOR_TEST_NO_CONTRIBUTORS") +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +check() +test.passes() diff --git a/test_regress/t/t_dist_copyright.pl b/test_regress/t/t_dist_copyright.pl deleted file mode 100755 index e235a8338..000000000 --- a/test_regress/t/t_dist_copyright.pl +++ /dev/null @@ -1,229 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -use IO::File; -use POSIX qw(strftime); -use strict; -use File::Spec::Functions 'catfile'; - -scenarios(dist => 1); - -our $Release_Ok_Re = qr!(^test_regress/t/|^examples/)!; -our $Exempt_Author_Re = qr!(^ci/|^nodist/fastcov.py|^nodist/fuzzer|^test_regress/t/.*\.(v|cpp|h)$)!; -our $Exempt_Files_Re = qr!(^\.|/\.|\.gitignore$|\.dat|\.gprof|\.mem|\.out$|\.png$|\.tree|\.vc$|\.vcd$|^\.)!; -our @Exempt_Files_List = qw( - Artistic - CITATION.cff - CPPLINT.cfg - LICENSE - README.rst - ci/ci-win-compile.ps1 - ci/ci-win-test.ps1 - ci/codecov - docs/CONTRIBUTING.rst - docs/CONTRIBUTORS - docs/README.rst - docs/_static - docs/gen - docs/spelling.txt - docs/verilated.dox - include/gtkwave - include/vltstd - install-sh - src/mkinstalldirs - test_regress/t/t_altera_lpm.v - test_regress/t/t_flag_f__3.v - test_regress/t/t_fuzz_eof_bad.v - test_regress/t/t_incr_void.v - test_regress/t/t_timing_trace_fst.pl - test_regress/t/t_uvm_pkg_all.vh - test_regress/t/t_uvm_pkg_todo.vh - test_regress/t/t_wrapper_context.pl - test_regress/t/t_wrapper_context_fst.pl - test_regress/t/t_wrapper_context_seq.pl - test_regress/t/t_wrapper_del_context_bad.pl - test_regress/t/tsub/t_flag_f_tsub.v - test_regress/t/tsub/t_flag_f_tsub_inc.v - verilator.pc.in - ); - -our @Exempt_Files_Copyright = qw( - test_regress/t/t_assert_disable_bad.pl - test_regress/t/t_clocking_bad1.pl - test_regress/t/t_clocking_bad2.pl - test_regress/t/t_clocking_bad3.pl - test_regress/t/t_clocking_bad4.pl - test_regress/t/t_clocking_notiming.pl - test_regress/t/t_clocking_timing2.pl - test_regress/t/t_clocking_unsup1.pl - test_regress/t/t_clocking_unsup2.pl - test_regress/t/t_comb_input_0.pl - test_regress/t/t_comb_input_1.pl - test_regress/t/t_comb_input_2.pl - test_regress/t/t_comb_loop_through_unpacked_array.pl - test_regress/t/t_const_bitoptree_bug3096.pl - test_regress/t/t_const_sel_sel_extend.pl - test_regress/t/t_delay_incr_timing.pl - test_regress/t/t_delay_timing.pl - test_regress/t/t_dfg_3676.pl - test_regress/t/t_dfg_3726.pl - test_regress/t/t_dfg_circular.pl - test_regress/t/t_dfg_multidriver_dfg_bad.pl - test_regress/t/t_dfg_multidriver_non_dfg.pl - test_regress/t/t_dfg_peephole.pl - test_regress/t/t_dfg_unhandled.pl - test_regress/t/t_dist_cppstyle.pl - test_regress/t/t_dpi_arg_inout_type.pl - test_regress/t/t_dpi_arg_inout_unpack.pl - test_regress/t/t_dpi_arg_input_type.pl - test_regress/t/t_dpi_arg_input_unpack.pl - test_regress/t/t_dpi_arg_output_type.pl - test_regress/t/t_dpi_arg_output_unpack.pl - test_regress/t/t_dpi_import_hdr_only.pl - test_regress/t/t_dpi_open_query.pl - test_regress/t/t_dpi_result_type.pl - test_regress/t/t_dpi_result_type_bad.pl - test_regress/t/t_dump_dfg.pl - test_regress/t/t_event_control_expr.pl - test_regress/t/t_event_control_expr_unsup.pl - test_regress/t/t_event_control_timing.pl - test_regress/t/t_flag_build_jobs_and_j.pl - test_regress/t/t_flag_prefix.pl - test_regress/t/t_flag_quiet_exit.pl - test_regress/t/t_flag_structs_packed.pl - test_regress/t/t_flag_values_deprecated.pl - test_regress/t/t_fork_timing.pl - test_regress/t/t_format_wide_decimal.pl - test_regress/t/t_gate_basic_timing.pl - test_regress/t/t_gate_delay_unsup.pl - test_regress/t/t_gate_loop.pl - test_regress/t/t_lib.pl - test_regress/t/t_lib_nolib.pl - test_regress/t/t_lib_prot.pl - test_regress/t/t_lib_prot_clk_gated.pl - test_regress/t/t_lib_prot_comb.pl - test_regress/t/t_lib_prot_delay_bad.pl - test_regress/t/t_lib_prot_inout_bad.pl - test_regress/t/t_lib_prot_secret.pl - test_regress/t/t_lib_prot_shared.pl - test_regress/t/t_lint_wait_bad.pl - test_regress/t/t_merge_cond_blowup.pl - test_regress/t/t_merge_cond_bug_3409.pl - test_regress/t/t_merge_cond_no_extend.pl - test_regress/t/t_merge_cond_no_motion.pl - test_regress/t/t_net_delay.pl - test_regress/t/t_net_delay_timing_sc.pl - test_regress/t/t_notiming.pl - test_regress/t/t_notiming_off.pl - test_regress/t/t_order_timing.pl - test_regress/t/t_param_real2_collision.pl - test_regress/t/t_recursive_module_bug.pl - test_regress/t/t_recursive_module_bug_2.pl - test_regress/t/t_sampled_expr_unsup.pl - test_regress/t/t_scheduling_5.pl - test_regress/t/t_scope_map.pl - test_regress/t/t_std_identifier_bad.pl - test_regress/t/t_timing_clkgen_unsup.pl - test_regress/t/t_timing_cmake.pl - test_regress/t/t_timing_debug1.pl - test_regress/t/t_timing_debug2.pl - test_regress/t/t_timing_dpi_unsup.pl - test_regress/t/t_timing_fork_comb.pl - test_regress/t/t_timing_func_bad.pl - test_regress/t/t_timing_intra_assign.pl - test_regress/t/t_timing_localevent_unsup.pl - test_regress/t/t_timing_protect.pl - test_regress/t/t_timing_unset1.pl - test_regress/t/t_timing_unset2.pl - test_regress/t/t_timing_unset3.pl - test_regress/t/t_timing_zerodly_unsup.pl - test_regress/t/t_trace_abort.pl - test_regress/t/t_trace_abort_fst.pl - test_regress/t/t_trace_abort_fst_sc.pl - test_regress/t/t_trace_ascendingrange.pl - test_regress/t/t_trace_ascendingrange_fst.pl - test_regress/t/t_trace_ascendingrange_fst_sc.pl - test_regress/t/t_trace_param_override.pl - test_regress/t/t_trace_timing1.pl - test_regress/t/t_type_param_collision.pl - test_regress/t/t_wait_timing.pl - test_regress/t/t_while_timing_control.pl - test_regress/t/t_x_assign_0.pl - test_regress/t/t_x_assign_1.pl - test_regress/t/t_x_assign_unique_0.pl - test_regress/t/t_x_assign_unique_1.pl - ); - -my $root = ".."; -my $Debug; - -my $Exempt_Files_List_Re = '^(' . join('|', (map { quotemeta $_ } @Exempt_Files_List)) . ")"; - -if (!-r "$root/.git") { - skip("Not in a git repository"); -} else { - my $out = `cd $root && git ls-files --exclude-standard`; - my $year = strftime("%Y", localtime); - my %files; - $out =~ s/\s+/ /g; - foreach my $filename (split /\s+/, $out) { - next if $filename =~ /$Exempt_Files_Re/; - next if $filename =~ /$Exempt_Files_List_Re/; - $files{$filename} = 1; - } - - # Exempt files added before Jun 1 2023, when we added this check - # List hardcoded now, but obtained from: - # $out = `cd $root && git ls-tree -r \`git rev-list -1 --before="Jun 1 2023" HEAD\` --name-only`; - my %oldFile; - foreach my $file (@Exempt_Files_Copyright) { $oldFile{$file} = 1; } - - foreach my $file (sort keys %files) { - my $filename = catfile($root, $file); - next if !-r $filename; - my $fh = IO::File->new("<$filename") or error("$! $filename"); - next if !$fh; - my $spdx; - my $copyright; - my $release; - while (my $line = $fh->getline) { - if ($line =~ /SPDX-License-Identifier:/) { - $spdx = $line; - } elsif ($line =~ /Copyright 20[0-9][0-9]/) { - $copyright = $line; - if ($line =~ /Wilson Snyder/) { - } elsif ($oldFile{$file} && $line =~ /Antmicro|Geza Lore|Todd Strader/) { - } elsif ($file =~ /$Exempt_Author_Re/) { - } else { - my $yeardash = ($file =~ m!test_regress/t!) ? $year : $year."-".$year; - warn " ".$copyright; - error("$file: Please use standard 'Copyright $yeardash by Wilson Snyder'"); - } - } elsif ($line =~ m!Creative Commons Public Domain! - || $line =~ m!freely copied and/or distributed! - || $line =~ m!placed into the Public Domain!) { - $release = 1; - } - } - my $release_note; - if ($release && $file !~ /$Release_Ok_Re/) { - $release_note = " (has copyright release, but not part of $Release_Ok_Re)"; - } - if (!$copyright && (!$release || $release_note)) { - error("$file: Please add standard 'Copyright $year ...', similar to in other files" . $release_note); - } - if (!$spdx) { - error("$file: Please add standard 'SPDX-License_Identifier: ...', similar to in other files"); - } - } -} - -ok(1); -1; diff --git a/test_regress/t/t_dist_copyright.py b/test_regress/t/t_dist_copyright.py new file mode 100755 index 000000000..ef8078a69 --- /dev/null +++ b/test_regress/t/t_dist_copyright.py @@ -0,0 +1,124 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import datetime + +test.scenarios('dist') + +RELEASE_OK_RE = r'(^test_regress/t/.*\.(cpp|h|mk|sv|v|vlt)|^test_regress/t_done/|^examples/)' + +EXEMPT_AUTHOR_RE = r'(^ci/|^nodist/fastcov.py|^nodist/fuzzer|^test_regress/t/.*\.(cpp|h|v|vlt)$)' + +EXEMPT_FILES_RE = r'(^\.|/\.|\.gitignore$|\.dat|\.gprof|\.mem|\.out$|\.png$|\.tree|\.vc$|\.vcd$|^\.)' + +EXEMPT_FILES_LIST = """ + Artistic + CITATION.cff + CPPLINT.cfg + LICENSE + README.rst + ci/ci-win-compile.ps1 + ci/ci-win-test.ps1 + ci/codecov + docs/CONTRIBUTING.rst + docs/CONTRIBUTORS + docs/README.rst + docs/_static + docs/gen + docs/spelling.txt + docs/verilated.dox + include/gtkwave + include/vltstd + install-sh + src/mkinstalldirs + test_regress/t/t_altera_lpm.v + test_regress/t/t_flag_f__3.v + test_regress/t/t_fuzz_eof_bad.v + test_regress/t/t_incr_void.v + test_regress/t/t_timing_trace_fst.pl + test_regress/t/t_uvm_pkg_all.vh + test_regress/t/t_uvm_pkg_todo.vh + test_regress/t/t_wrapper_context.pl + test_regress/t/t_wrapper_context_fst.pl + test_regress/t/t_wrapper_context_seq.pl + test_regress/t/t_wrapper_del_context_bad.pl + test_regress/t/tsub/t_flag_f_tsub.v + test_regress/t/tsub/t_flag_f_tsub_inc.v + verilator.pc.in + """ + +root = ".." + +Exempt_Files_List_Re = list(map(re.escape, EXEMPT_FILES_LIST.split())) +Exempt_Files_List_Re = '^(' + '|'.join(Exempt_Files_List_Re) + ")" +# pprint(Exempt_Files_List_Re) + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +cmd = "cd " + root + " && git ls-files --exclude-standard" +out = test.run_capture(cmd) + +year = datetime.datetime.now().year + +files = {} +out = re.sub(r'\s+', ' ', out) +for filename in out.split(): + if re.search(EXEMPT_FILES_RE, filename): + continue + if re.search(Exempt_Files_List_Re, filename): + continue + files[filename] = True + +for filename in files: + open_filename = os.path.join(root, filename) + if not os.path.exists(open_filename): + continue + with open(open_filename, 'r', encoding="utf8") as fh: + spdx = None + copyright_msg = None + release = False + for line in fh: + line = line.rstrip() + if 'SPDX-License-Identifier:' in line: + spdx = line + elif re.search(r'Copyright 20[0-9][0-9]', line): + copyright_msg = line + if 'Wilson Snyder' in line: + pass + elif re.search(r'\.pl$', filename): + pass + elif re.search(EXEMPT_AUTHOR_RE, filename): + pass + else: + if "test_regress/t" in filename: + yeardash = str(year) + else: + yeardash = str(year) + '-' + str(year) + print(" " + copyright_msg) + test.error_keep_going(filename + ": Please use standard 'Copyright " + + yeardash + " by Wilson Snyder'") + elif (('Creative Commons Public Domain' in line) + or ('freely copied and/or distributed' in line) + or ('placed into the Public Domain' in line)): + release = True + + release_note = "" + if not re.search(RELEASE_OK_RE, filename): + release_note = " (has copyright release, but not part of " + RELEASE_OK_RE + ")" + if not copyright_msg and (not release or release_note): + test.error_keep_going(filename + ": Please add standard 'Copyright " + str(year) + + " ...', similar to in other files" + release_note) + if not spdx: + test.error_keep_going( + filename + + ": Please add standard 'SPDX-License_Identifier: ...', similar to in other files") + +test.passes() diff --git a/test_regress/t/t_dist_cppstyle.pl b/test_regress/t/t_dist_cppstyle.pl deleted file mode 100755 index 222addde0..000000000 --- a/test_regress/t/t_dist_cppstyle.pl +++ /dev/null @@ -1,81 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Primitive C++ style checker -# -# Copyright 2022 by Geza Lore. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(dist => 1); - -my $root = ".."; - -### Must trim output before and after our file list -my %files = %{get_source_files($root)}; - -foreach my $file (sort keys %files) { - my $filename = "$root/$file"; - next if !-f $filename; # git file might be deleted but not yet staged - next unless $file =~ /\.(h|c|cpp)(\.in)?$/; - next if $file =~ /gtkwave/; - - my $contents = file_contents($filename); - - checkPattern($filename, $contents, - qr/[^\/]*virtual[^{};]+override/, - "'virtual' keyword is redundant on 'override' method"); - - checkPattern($filename, $contents, - qr/ \s*(\w+ )*\s*(inline) [^;]+?\([^;]*?\)[^;]+?(?:{|:|=\s*default)/, - "'inline' keyword is redundant on method definitions inside classes"); - - checkPattern($filename, $contents, - qr/(?\n)inline \S+ [^;:(]+::[^;:(]+\([^;]*\)[^;]+{/, - "Use 'inline' only on declaration inside classes (except for template specializatoins)"); - - if ($file =~ /\.(c|cpp)/) { - checkPattern($filename, $contents, - qr/(\w+\s+)*(inline)/, - "'inline' keyword is on functions defined in .cpp files"); - } -} - -ok(1); -1; - -sub get_source_files { - my $root = shift; - my $git_files = `cd $root && git ls-files`; - print "MF $git_files\n" if $Self->{verbose}; - my %files; - foreach my $file (split /\s+/, $git_files) { - next if $file eq ''; - $files{$file} |= 1; - } - return \%files; -} - -sub checkPattern { - my $filename = shift; - my $contents = shift; - my $pattern = shift; - my $message = shift; - - my $lineno = 0; - my $buffer; - foreach my $line (split(/\n/, $contents . "\n\n")) { - ++$lineno; - if ($line ne "") { - # Don't do whole file at once - see issue #4085 - # Build a buffer until a newline so we check a block at a time. - $buffer .= $line . "\n"; - next; - } - if ($buffer =~ s/.*?^($pattern)//sm) { - error("$filename:$lineno: $message"); - } - $buffer = ""; - } -} diff --git a/test_regress/t/t_dist_cppstyle.py b/test_regress/t/t_dist_cppstyle.py new file mode 100755 index 000000000..40815115d --- /dev/null +++ b/test_regress/t/t_dist_cppstyle.py @@ -0,0 +1,77 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Primitive C++ style checker +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +root = ".." + + +def get_source_files(root): + git_files = test.run_capture("cd " + root + " && git ls-files") + if test.verbose: + print("MF " + git_files) + files = {} + for filename in git_files.split(): + if filename == '': + continue + files[filename] = True + return files + + +def check_pattern(filename, contents, pattern, not_pattern, message): + lineno = 0 + buffer = "\n" + for line in contents.splitlines(): + lineno += 1 + if line != "": + # Don't do whole file at once - see issue #4085 + # Build a buffer until a newline so we check a block at a time. + buffer += line + "\n" + continue + if re.search(r"\n" + pattern, buffer): + if not not_pattern or not re.search(not_pattern, buffer): + test.error(filename + ":" + str(lineno) + ": " + message) + buffer = "\n" + + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +files = get_source_files(root) + +for filename in sorted(files.keys()): + filename = os.path.join(root, filename) + if not os.path.exists(filename): # git file might be deleted but not yet staged + continue + if not re.search(r'\.(h|c|cpp)(\.in)?$', filename): + continue + if '/gtkwave/' in filename: + continue + + contents = test.file_contents(filename) + "\n\n" + + check_pattern(filename, contents, r"[^\']*virtual[^{};\n]+override", None, + "'virtual' keyword is redundant on 'override' method") + + check_pattern(filename, contents, + r' \s*(\w+ )*\s*(inline) [^;]+?\([^;]*?\)[^;]+?(?:{|:|=\s*default)', None, + "'inline' keyword is redundant on method definitions inside classes") + + check_pattern( + filename, contents, r'inline \S+ [^;:(]+::[^;:(]+\([^;]*\)[^;]+{', r'template', + "Use 'inline' only on declaration inside classes" + " (except for template specializations)") + + if re.search(r'\.(c|cpp)', filename): + check_pattern(filename, contents, r'(\w+\s+)*(inline)', None, + "'inline' keyword is on functions defined in .cpp files") + +test.passes() diff --git a/test_regress/t/t_dist_docs_style.pl b/test_regress/t/t_dist_docs_style.pl deleted file mode 100755 index 55ce56858..000000000 --- a/test_regress/t/t_dist_docs_style.pl +++ /dev/null @@ -1,68 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Primitive C++ style checker -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(dist => 1); - -my $root = ".."; - -### Must trim output before and after our file list -my %files = %{get_source_files($root)}; - -foreach my $file (sort keys %files) { - my $filename = "$root/$file"; - next if !-f $filename; # git file might be deleted but not yet staged - next unless $file =~ /\.rst$/; - - my $contents = file_contents($filename); - - checkPattern($filename, $contents, - qr/.*[a-z](?{verbose}; - my %files; - foreach my $file (split /\s+/, $git_files) { - next if $file eq ''; - $files{$file} |= 1; - } - return \%files; -} - -sub checkPattern { - my $filename = shift; - my $contents = shift; - my $pattern = shift; - my $message = shift; - - my $offset = 0; - my $buffer = $contents; - while ($buffer =~ s/.*?^($pattern)//sm) { - my $lineno = offset_to_lineno($contents, $offset + $-[-1]); - $offset += $+[1]; - error("$filename:$lineno: $message"); - } -} - -sub offset_to_lineno { - my $contents = shift; - my $offset = shift; - my $count = (substr $contents, 0, $offset) =~ tr/\n//; - return $count + 1; -} diff --git a/test_regress/t/t_dist_docs_style.py b/test_regress/t/t_dist_docs_style.py new file mode 100755 index 000000000..6acdf983e --- /dev/null +++ b/test_regress/t/t_dist_docs_style.py @@ -0,0 +1,61 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Primitive C++ style checker +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +root = ".." + + +def get_source_files(root): + git_files = test.run_capture("cd " + root + " && git ls-files") + if test.verbose: + print("MF " + git_files) + files = {} + for filename in git_files.split(): + if filename == '': + continue + files[filename] = True + return files + + +def check_pattern(filename, contents, pattern, message): + lineno = 1 + buf = contents + while True: + m = re.match(r'^(.*?^(' + pattern + '))(.*)', buf) + if not m: + break + lineno += m.group(1).count("\n") + buf = m.group(3) + test.error(filename + ":" + str(lineno) + ": " + message) + + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +### Must trim output before and after our file list +files = get_source_files(root) + +for filename in sorted(files.keys()): + filename = os.path.join(root, filename) + if not os.path.exists(filename): # git file might be deleted but not yet staged + continue + if not re.search(r'\.rst$', filename): + continue + + contents = test.file_contents(filename) + + check_pattern(filename, contents, r'.*[a-z](? 1); - -my $root = ".."; - -my @Waivers = - ( - '+verilator+prof+threads+file+', # Deprecated - '+verilator+prof+threads+start+', # Deprecated - '+verilator+prof+threads+window+', # Deprecated - '-fno-', # Documented differently - '-no-lineno', # Deprecated - '-no-order-clock-delay', # Deprecated - '-prof-threads', # Deprecated - ); - -my %sums = %{get_summary_opts($root)}; -my %docs = %{get_docs_opts($root)}; - -my %both = (%sums, %docs); -my %waiver = map { $_ => 1; } @Waivers; -foreach my $opt (sort keys %both) { - next if $waiver{$opt}; - my $sum_ok = 0; - my $docs_ok = 0; - for my $alt (alt_names($opt)) { - $sum_ok = 1 if $sums{$alt}; - print "$sum_ok SAC '$opt' -> '$alt'\n" if $Self->{verbose}; - } - $sum_ok = 1 if $opt =~ /-fno-/; # Minimal-documented optimization option - for my $alt (alt_names($opt)) { - $docs_ok = 1 if $docs{$alt}; - print "$sum_ok DAC '$opt' -> '$alt'\n" if $Self->{verbose}; - } - if (!$sum_ok) { - error($docs{$opt}.": Option documented in docs/guide '$opt'" - ." not found in bin/* ARGUMENT SUMMARY documentation"); - } elsif (!$docs_ok) { - error($sums{$opt}.": Option documented in bin/ ARGUMENT SUMMARY '$opt'" - ." not found in docs/guide documentation"); - } else { - print($docs{$opt}.": ok '$opt'\n") if $Self->{verbose}; - } -} - -ok(1); -1; - -sub get_summary_opts { - my $root = shift; - my %args = (); - foreach my $file (glob "$root/bin/*") { - my $fc = file_contents($file); - my $on = 0; - my $lineno = 0; - foreach my $line (split(/\n/, $fc)) { - ++$lineno; - if ($line =~ /ARGUMENT SUMMARY/) { - $on = 1; - } elsif ($line =~ /=head1/) { - $on = 0; - } elsif ($on && $line =~ /^\s+([---+]+[^ ]+)/) { - my $opt = opt_clean($1); - print "S '$opt' $line\n" if $Self->{verbose}; - $args{$opt} = "$file:$lineno"; - } elsif ($line =~ /parser.add_argument\('([---+][^']+)'/) { - my $opt = opt_clean($1); - print "S '$opt' $line\n" if $Self->{verbose}; - $args{$opt} = "$file:$lineno"; - } - } - } - return \%args; -} - -sub get_docs_opts { - my $root = shift; - my %args = (); - foreach my $file (glob "$root/docs/guide/*.rst") { - my $fc = file_contents($file); - my $lineno = 0; - foreach my $line (split(/\n/, $fc)) { - ++$lineno; - if ($line =~ /option:: ([---+]+[^ `]+)/ - || $line =~ /:vlopt:`[^`]+ <([^>]+)>/ - || $line =~ /:vlopt:`([---+]+[^ `]+)/) { - my $opt = opt_clean($1); - print "D '$opt' $line\n" if $Self->{verbose}; - $args{$opt} = "$file:$lineno"; - } - } - } - return \%args; -} - -sub opt_clean { - my $opt = shift; - $opt =~ s/--/-/; - $opt =~ s/<.*//; - $opt =~ s/\\//; - return $opt; -} - -sub alt_names { - my $opt = shift; - my @opts = ($opt); - push @opts, "-no".$opt if $opt =~ /^-/; - push @opts, $1 if $opt =~ /^-no(-.*)/; - return @opts; -} diff --git a/test_regress/t/t_dist_docs_summary.py b/test_regress/t/t_dist_docs_summary.py new file mode 100755 index 000000000..ad2ff316c --- /dev/null +++ b/test_regress/t/t_dist_docs_summary.py @@ -0,0 +1,132 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Primitive C++ style checker +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +root = ".." + +Waivers = [ + '+verilator+prof+threads+file+', # Deprecated + '+verilator+prof+threads+start+', # Deprecated + '+verilator+prof+threads+window+', # Deprecated + '-fno-', # Documented differently + '-no-lineno', # Deprecated + '-no-order-clock-delay', # Deprecated + '-prof-threads', # Deprecated) +] + + +def get_summary_opts(root): + args = {} + for filename in test.glob_some(root + "/bin/*"): + with open(filename, "r", encoding="latin-1") as fh: + on = False + lineno = 0 + for line in fh: + lineno += 1 + line = line.rstrip() + m1 = re.search(r'^\s+((-|\+)+[^ ]+)', line) + m2 = re.search(r"parser.add_argument\('((-|\+)[^']+)'", line) + if re.search(r'ARGUMENT SUMMARY', line): + on = True + elif re.search(r'=head1', line): + on = False + elif on and m1: + opt = opt_clean(m1.group(1)) + if test.verbose: + print("S '" + opt + "' " + line) + args[opt] = filename + ":" + str(lineno) + elif m2: + opt = opt_clean(m2.group(1)) + if test.verbose: + print("S '" + opt + "' " + line) + args[opt] = filename + ":" + str(lineno) + return args + + +def get_docs_opts(root): + args = {} + for filename in test.glob_some(root + "/docs/guide/*.rst"): + with open(filename, "r", encoding="latin-1") as fh: + lineno = 0 + for line in fh: + lineno += 1 + line = line.rstrip() + m = re.search(r'option:: ((-|\+)+[^ `]+)', line) + if not m: + m = re.search(r':vlopt:`[^`]+ <([^>]+)>', line) + if not m: + m = re.search(r':vlopt:`((-|\+)+[^ `]+)', line) + if m: + opt = opt_clean(m.group(1)) + if test.verbose: + print("D '" + opt + "' " + line) + args[opt] = filename + ":" + str(lineno) + return args + + +def opt_clean(opt): + opt = re.sub(r'--', '-', opt) + opt = re.sub(r'<.*', '', opt) + opt = re.sub(r'\\', '', opt) + return opt + + +def alt_names(opt): + opts = [opt] + if re.search(r'^-', opt): + opts.append("-no" + opt) + m = re.search(r'^-no(-.*)', opt) + if m: + opts.append(m.group(1)) + return opts + + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +sums = get_summary_opts(root) +docs = get_docs_opts(root) + +both = {} +both.update(sums) +both.update(docs) + +waiver = {k: 1 for k in Waivers} + +for opt in sorted(both.keys()): + if opt in waiver: + continue + sum_ok = False + docs_ok = False + for alt in alt_names(opt): + if alt in sums: + sum_ok = True + if test.verbose: + print(str(sum_ok) + " SAC '" + opt + "' -> '" + alt + "'") + if re.search(r'-fno-', opt): # Minimal-documented optimization option + sum_ok = True + for alt in alt_names(opt): + if alt in docs: + docs_ok = True + if test.verbose: + print(str(docs_ok) + " DAC '" + opt + "' -> '" + alt + "'") + + if not sum_ok: + test.error(docs[opt] + ": Option documented in docs/guide '" + opt + + "' not found in bin/* ARGUMENT SUMMARY documentation") + elif not docs_ok: + test.error(sums[opt] + ": Option documented in bin/ ARGUMENT SUMMARY '" + opt + + "' not found in docs/guide documentation") + elif test.verbose: + print(": ok '" + opt) + +test.passes() diff --git a/test_regress/t/t_dist_error_format.pl b/test_regress/t/t_dist_error_format.pl deleted file mode 100755 index dd0b32dfa..000000000 --- a/test_regress/t/t_dist_error_format.pl +++ /dev/null @@ -1,79 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -use IO::File; - -scenarios(dist => 1); - -my $root = ".."; -my $Debug; - -if (!-r "$root/.git") { - skip("Not in a git repository"); -} else { - formats(); -} - -ok(1); - -# Check all error messages match our standard format -# This assumes .out files cover all important errors - -sub formats { - my $files = "../test_regress/t/*.out"; - my %warns; - my $lnmatch = 0; - foreach my $file (glob $files) { - my $wholefile = file_contents($file); - $file =~ s!.*/!!; - if ($wholefile =~ /Exiting due to/ - || $wholefile =~ /%(Error|Warning)/) { - my $lineno = 0; - foreach my $line (split /\n/, $wholefile) { - ++$lineno; - $line =~ s/(\$display|\$write).*\".*%(Error|Warning)//; - if ($line =~ /(Error|Warning)/ - && $line !~ /^\s*{verbose}; - } - # Error no fileline - # For testing only: we assume any : is single quoted - elsif ($match =~ /^%(Error|Warning)(-[A-Z0-9_]+)?: [^:']+/) { - print "ok-en $file $line\n" if $Self->{verbose}; - } - else { - #print "FF $file $line\n"; - $warns{$file . ":" . $lineno} = - "Non-standard warning/error: $file:$lineno: $line"; - } - } - } - } - } - $lnmatch or error("Check line number regexp is correct, no matches"); - if (keys %warns) { - # First warning lists everything as that's shown in the driver summary - error($summary . " ", join(' ', sort keys %warns)); - foreach my $file (sort keys %warns) { - error($warns{$file}); - } - } -} - -1; diff --git a/test_regress/t/t_dist_error_format.py b/test_regress/t/t_dist_error_format.py new file mode 100755 index 000000000..473dffb57 --- /dev/null +++ b/test_regress/t/t_dist_error_format.py @@ -0,0 +1,70 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +root = ".." + +# Check all error messages match our standard format +# This assumes .out files cover all important errors + + +def formats(): + files = root + "/test_regress/t/*.out" + warns = {} + lnmatch = 0 + for filename in test.glob_some(files): + wholefile = test.file_contents(filename) + filename = os.path.basename(filename) + if re.search(r'(Exiting due to|%Error|%Warning)', wholefile): + lineno = 0 + for line in wholefile.splitlines(): + lineno += 1 + line = re.sub(r'(\$display|\$write).*\".*%(Error|Warning)', '', line) + if (re.search(r'(Error|Warning)', line) + and not re.search(r'^\s* 1); - -my $root = ".."; -my $Debug; - -if (!-r "$root/.git") { - skip("Not in a git repository"); -} else { - ### Must trim output before and after our file list - my $files = `cd $root && git ls-files --exclude-standard`; - print "ST $files\n" if $Debug; - my %names; - - $files =~ s/\s+/ /g; - my @batch; - my $n = 0; - my $re = qr/(FIX[M]E|BO[Z]O)/; - foreach my $file (split /\s+/, $files) { - my $filename = catfile($root, $file); - next if !-r $filename; - my $wholefile = file_contents($filename); - if ($wholefile =~ /$re/) { - $names{$file} = 1; - } - } - if (scalar(%names) >= 1) { - error("Files with FIX" . "MEs: ", join(' ', sort keys %names)); - } -} - -ok(1); -1; diff --git a/test_regress/t/t_dist_fixme.py b/test_regress/t/t_dist_fixme.py new file mode 100755 index 000000000..9c174e73c --- /dev/null +++ b/test_regress/t/t_dist_fixme.py @@ -0,0 +1,39 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +root = ".." + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +### Must trim output before and after our file list +files = test.run_capture("cd " + root + " && git ls-files --exclude-standard") +if test.verbose: + print("ST " + files) + +names = {} +files = re.sub(r'\s+', ' ', files) + +regex = r'(FIX[M]E|BO[Z]O)' +for filename in files.split(): + filename = os.path.join(root, filename) + if not os.path.exists(filename): + continue + wholefile = test.file_contents(filename) + if re.search(regex, wholefile): + names[filename] = True + +if len(names): + test.error("Files with FIX" + "MEs: " + ' '.join(sorted(names.keys()))) + +test.passes() diff --git a/test_regress/t/t_dist_getsetorder.pl b/test_regress/t/t_dist_getsetorder.pl deleted file mode 100755 index f06501759..000000000 --- a/test_regress/t/t_dist_getsetorder.pl +++ /dev/null @@ -1,60 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Hacky import order checker, used to ensure all getters -# come before setters for consistent codegen when using autocxx (#5182) -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(dist => 1); - -my $root = ".."; - -### Must trim output before and after our file list -my %files = %{get_source_files($root)}; - -foreach my $file (sort keys %files) { - my $filename = "$root/$file"; - next if !-f $filename; # git file might be deleted but not yet staged - next unless $file =~ /include.*verilated.*\.[ch].*$/; - next if $file =~ /gtkwave/; - - my $contents = file_contents($filename); - my %seen_setters; - my %seen_getters; - foreach my $line (split(/\n/, $contents . "\n\n")) { - next if $line =~ /^\s*\/\//; # skip commented lines - if ($line =~ /\s*void\s+([a-zA-Z0-9_]+)\([a-zA-Z0-9_]+.*/) { - my $setter_name = $1; - $seen_setters{$setter_name} = 1; - } else { - next unless $line =~ /\s*[a-zA-Z0-9_]+\s+([a-zA-Z0-9_]+)\(\s*\)/; - my $getter_name = $1; - if ($file =~ /verilated_sc_trace/ and $getter_name == "cycle") { - next; # hardcoded check for cycle() which looks like a setter but isn't - } - if (exists $seen_setters{$getter_name} and not (exists $seen_getters{$getter_name})) { - error("$file: '$getter_name()' came after its setter; suggest swap order"); - } - $seen_getters{$getter_name} = 1; - } - } -} - -ok(1); -1; - -sub get_source_files { - my $root = shift; - my $git_files = `cd $root && git ls-files`; - print "MF $git_files\n" if $Self->{verbose}; - my %files; - foreach my $file (split /\s+/, $git_files) { - next if $file eq ''; - $files{$file} |= 1; - } - return \%files; -} diff --git a/test_regress/t/t_dist_getsetorder.py b/test_regress/t/t_dist_getsetorder.py new file mode 100755 index 000000000..350c77136 --- /dev/null +++ b/test_regress/t/t_dist_getsetorder.py @@ -0,0 +1,78 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Hacky import order checker, used to ensure all getters +# come before setters for consistent codegen when using autocxx (#5182) +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +root = ".." + + +def get_source_files(root): + git_files = test.run_capture("cd " + root + " && git ls-files") + if test.verbose: + print("MF " + git_files) + files = {} + for filename in git_files.split(): + if filename == '': + continue + files[filename] = True + return files + + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +### Must trim output before and after our file list +files = get_source_files(root) + +for filename in sorted(files.keys()): + filename = os.path.join(root, filename) + if not os.path.exists(filename): # git file might be deleted but not yet staged + continue + if not re.search(r'include.*verilated.*\.[ch].*$', filename): + continue + if re.search(r'gtkwave', filename): + continue + + contents = test.file_contents(filename) + "\n\n" + seen_setters = {} + seen_getters = {} + lineno = 0 + for line in contents.splitlines(): + lineno += 1 + if re.search(r'^\s*\/\/', line): # skip commented lines + continue + #print("L "+line) + if re.search(r'^class', line): + seen_setters = {} + seen_getters = {} + if test.verbose: + print("C " + line) + continue + m = re.search(r'\s*void\s+([a-zA-Z0-9_]+)\([a-zA-Z0-9_]+.*', line) + if m: + setter_name = m.group(1) + if test.verbose: + print("S " + setter_name + " " + line) + seen_setters[setter_name] = True + m = re.search(r'\s*[a-zA-Z0-9_]+\s+([a-zA-Z0-9_]+)\(\s*\)', line) + if m: + getter_name = m.group(1) + if getter_name == "cycle" and re.search(r'verilated_sc_trace', filename): + continue # hardcoded check for cycle() which looks like a setter but isn't + if test.verbose: + print("G " + setter_name + " " + line) + if getter_name in seen_setters and getter_name not in seen_getters: + test.error(filename + ":" + str(lineno) + ": '" + getter_name + + "()' came after its setter; swap order") + seen_getters[getter_name] = True + +test.passes() diff --git a/test_regress/t/t_dist_header_cc.pl b/test_regress/t/t_dist_header_cc.pl deleted file mode 100755 index e51a12901..000000000 --- a/test_regress/t/t_dist_header_cc.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - - -use Cwd; - -scenarios(dist => 1); - -my $root = ".."; - -if (!-r "$root/.git") { - skip("Not in a git repository"); -} else { - run(cmd => ["cd $root/src/obj_dbg && $ENV{MAKE} -j 4 -k -f ../Makefile_obj VL_NOOPT=1 header_cc"], - check_finished => 0); -} - -ok(1); -1; diff --git a/test_regress/t/t_dist_header_cc.py b/test_regress/t/t_dist_header_cc.py new file mode 100755 index 000000000..c25395442 --- /dev/null +++ b/test_regress/t/t_dist_header_cc.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +root = ".." + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +test.run(cmd=[ + "cd " + root + "/src/obj_dbg && " + os.environ['MAKE'] + + " -j 4 -k -f ../Makefile_obj VL_NOOPT=1 header_cc" +], + check_finished=False) + +test.passes() diff --git a/test_regress/t/t_dist_install.pl b/test_regress/t/t_dist_install.pl deleted file mode 100755 index 1c92e19ac..000000000 --- a/test_regress/t/t_dist_install.pl +++ /dev/null @@ -1,56 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -use Cwd; - -scenarios(dist => 1); - -my $root = ".."; -my $Debug; - -if (!-r "$root/.git") { - skip("Not in a git repository"); -} else { - my $cwd = getcwd(); - my $destdir = "$cwd/" . $Self->{obj_dir}; - # Start clean - run(cmd => ["rm -rf $destdir && mkdir -p $destdir"], - check_finished => 0); - # Install into temp area - print "Install...\n"; - run(cmd => ["cd $root && $ENV{MAKE} DESTDIR=$destdir install-all"], - check_finished => 0); - - # Check we can run a test - # Unfortunately the prefix was hardcoded in the exec at a different place, - # so we can't do much here. - #print "Check install...\n"; - - # Uninstall - print "Uninstall...\n"; - run(cmd => ["cd $root && $ENV{MAKE} DESTDIR=$destdir uninstall"], - check_finished => 0); - - # Check empty - my @files; - $finds = `find $destdir -type f -print`; - foreach my $file (split /\n/, $finds) { - next if $file =~ /\.status/; # Made by driver.pl, not Verilator - print "\tLEFT: $file\n"; - $file =~ s!^$cwd!.!; - push @files, $file; - } - if ($#files >= 0) { - error("Uninstall missed files: ", join(' ', @files)); - } -} - -ok(1); -1; diff --git a/test_regress/t/t_dist_install.py b/test_regress/t/t_dist_install.py new file mode 100755 index 000000000..84bfabc16 --- /dev/null +++ b/test_regress/t/t_dist_install.py @@ -0,0 +1,53 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +root = ".." + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +cwd = os.getcwd() +destdir = cwd + "/" + test.obj_dir + +# Start clean +test.run(cmd=["rm -rf " + destdir + " && mkdir -p " + destdir], check_finished=False) + +# Install into temp area +print("Install...") +test.run(cmd=["cd " + root + " && " + os.environ["MAKE"] + " DESTDIR=" + destdir + " install-all"], + check_finished=False) + +# Check we can run a test +# Unfortunately the prefix was hardcoded in the exec at a different place, +# so we can't do much here. +#print("Check install...") + +# Uninstall +print("Uninstall...\n") +test.run(cmd=["cd " + root + " && " + os.environ["MAKE"] + " DESTDIR=" + destdir + " uninstall"], + check_finished=False) + +# Check empty +files = [] +finds = test.run_capture("find " + destdir + " -type f -print") +for filename in finds.split(): + if re.search(r'\.status', filename): # Made by driver.py, not Verilator + continue + print("\tLEFT: " + filename) + filename = re.sub(r'^' + re.escape(cwd), '.', filename) + files.append(filename) + +if len(files) > 0: + test.error("Uninstall missed files: " + ' '.join(files)) + +test.passes() diff --git a/test_regress/t/t_dist_lint_py.py b/test_regress/t/t_dist_lint_py.py new file mode 100755 index 000000000..8c8b9a2f6 --- /dev/null +++ b/test_regress/t/t_dist_lint_py.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +root = ".." + +if 'VERILATOR_TEST_NO_LINT_PY' in os.environ: + test.skip("Skipping due to VERILATOR_TEST_NO_LINT_PY") +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +test.run(cmd=["cd " + root + " && make lint-py"]) + +test.passes() diff --git a/test_regress/t/t_dist_pl.py b/test_regress/t/t_dist_pl.py new file mode 100755 index 000000000..03d53d06a --- /dev/null +++ b/test_regress/t/t_dist_pl.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +root = ".." + +for pl in sorted(test.glob_some(root + "/test_regress/t/*.pl")): + if 'bootstrap.pl' in pl: + continue + py = re.sub(r'\.pl', '.py', pl) + test.error_keep_going(pl + ":1: Perl test needs conversion into a Python test '" + + os.path.basename(py) + "'") + +test.passes() diff --git a/test_regress/t/t_dist_portability.pl b/test_regress/t/t_dist_portability.pl deleted file mode 100755 index 7d1ef53b3..000000000 --- a/test_regress/t/t_dist_portability.pl +++ /dev/null @@ -1,111 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -use IO::File; - -scenarios(dist => 1); - -my $root = ".."; -my $Debug; - -if (!-r "$root/.git") { - skip("Not in a git repository"); -} else { - printfll(); - cstr(); - vsnprintf(); - final(); -} - -ok(1); - -sub printfll { - my $files = "src/*.c* src/*.h include/*.c* include/*.h examples/*/*.c* test_regress/t/*.c* test_regress/t/*.h"; - my $cmd = "cd $root && fgrep -n ll $files | sort"; - print "C $cmd\n"; - my $grep = `$cmd`; - my %names; - foreach my $line (split /\n/, $grep) { - next if $line !~ /%[a-z0-9]*ll/; - next if $line =~ /lintok-format-ll/; - print "$line\n"; - if ($line =~ /^([^:]+)/) { - $names{$1} = 1; - } else { - $names{UNKNOWN} = 1; - } - } - if (keys %names) { - error("Files with %ll instead of PRIx64: ", join(' ', sort keys %names)); - } -} - -sub cstr { - my $files = "src/*.c* src/*.h include/*.c* include/*.h examples/*/*.c* test_regress/t/*.c* test_regress/t/*.h"; - my $cmd = "cd $root && grep -n -P 'c_str|begin|end' $files | sort"; - print "C $cmd\n"; - my $grep = `$cmd`; - my %names; - foreach my $line (split /\n/, $grep) { - if ($line =~ /^([^:]+)[^"]*\(\)[a-z0-9_().->]*[.->]+(c_str|r?begin|r?end)\(\)/) { - next if $line =~ /lintok-begin-on-ref/; - print "$line\n"; - $names{$1} = 1; - } - } - if (keys %names) { - error("Files with potential c_str() lifetime issue: ", join(' ', sort keys %names)); - } -} - -sub vsnprintf { - # Note do not do test_regress, as VPI files need to compile without verilatedos.h - my $files = "src/*.c* src/*.h include/*.c* include/*.h examples/*/*.c*"; - my $cmd = "cd $root && grep -n -P '(snprintf|vsnprintf)' $files | sort"; - print "C $cmd\n"; - my $grep = `$cmd`; - my %names; - foreach my $line (split /\n/, $grep) { - if ($line =~ /\b(snprintf|vsnprintf)\b/) { - next if $line =~ /# *define\s*VL_V?SNPRINTF/; - print "$line\n"; - $names{$1} = 1; - } - } - if (keys %names) { - error("Files with vsnprintf, use VL_VSNPRINTF: ", join(' ', sort keys %names)); - } -} - -sub final { - # Note do not do test_regress, as VPI files need to compile without verilatedos.h - my $files = "src/*.c* src/*.h include/*.c* include/*.h"; - my $cmd = "cd $root && grep -n -P '(class|struct)' $files | sort"; - print "C $cmd\n"; - my $grep = `$cmd`; - my %names; - foreach my $line (split /\n/, $grep) { - if ($line =~ /:\s*(class|struct) /) { - next if $line =~ /final|VL_NOT_FINAL/; - next if $line =~ /{}/; # e.g. 'class Foo {};' - next if $line =~ /;/; # e.g. 'class Foo;' - next if $line =~ /(class|struct)\s+{/; # e.g. anon 'class {' - next if $line =~ /struct std::/; - next if $line !~ /{/; - print "$line\n"; - $names{$1} = 1; - } - } - if (keys %names) { - error("Files with classes without final/VL_NOT_FINAL: ", join(' ', sort keys %names)); - } -} - -1; diff --git a/test_regress/t/t_dist_portability.py b/test_regress/t/t_dist_portability.py new file mode 100755 index 000000000..d76293db6 --- /dev/null +++ b/test_regress/t/t_dist_portability.py @@ -0,0 +1,100 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +root = ".." + + +def line_filename(line): + m = re.search(r'^([^:]+)', line) + return m.group(1) if m else 'UNKNOWN' + + +def printfll(): + files = "src/*.c* src/*.h include/*.c* include/*.h examples/*/*.c* test_regress/t/*.c* test_regress/t/*.h" + cmd = "cd " + root + " && fgrep -n ll " + files + " | sort" + grep = test.run_capture(cmd, check=False) + names = {} + for line in grep.splitlines(): + if not re.search(r'%[a-z0-9]*ll', line): + continue + if re.search(r'lintok-format-ll', line): + continue + print(line) + names[line_filename(line)] = True + if len(names): + test.error("Files with %ll instead of PRIx64: " + ' '.join(sorted(names.keys()))) + + +def cstr(): + files = "src/*.c* src/*.h include/*.c* include/*.h examples/*/*.c* test_regress/t/*.c* test_regress/t/*.h" + cmd = "cd " + root + " && grep -n -P 'c_str|begin|end' " + files + " | sort" + grep = test.run_capture(cmd, check=False) + names = {} + for line in grep.splitlines(): + if re.search(r'^([^:]+)[^"]*\(\)[a-z0-9_().->]*[.->]+(c_str|r?begin|r?end)\(\)', line): + if re.search(r'lintok-begin-on-ref', line): + continue + print(line) + names[line_filename(line)] = True + if len(names): + test.error("Files with potential c_str() lifetime issue: " + + ' '.join(sorted(names.keys()))) + + +def vsnprintf(): + # Note do not do test_regress, as VPI files need to compile without verilatedos.h + files = "src/*.c* src/*.h include/*.c* include/*.h examples/*/*.c*" + cmd = "cd " + root + " && grep -n -P '(snprintf|vsnprintf)' " + files + " | sort" + grep = test.run_capture(cmd, check=False) + names = {} + for line in grep.splitlines(): + if re.search(r'\b(snprintf|vsnprintf)\b', line): + if re.search(r'# *define\s*VL_V?SNPRINTF', line): + continue + print(line) + names[line_filename(line)] = True + if len(names): + test.error("Files with vsnprintf, use VL_VSNPRINTF: " + ' '.join(sorted(names.keys()))) + + +def final(): + # Note do not do test_regress, as VPI files need to compile without verilatedos.h + files = "src/*.c* src/*.h include/*.c* include/*.h" + cmd = "cd " + root + " && grep -n -P '(class|struct)' " + files + " | sort" + grep = test.run_capture(cmd, check=False) + names = {} + for line in grep.splitlines(): + if re.search(r':\s*(class|struct) ', line): + if (re.search(r'final|VL_NOT_FINAL', line) # + or re.search(r'{}', line) # e.g. 'class Foo {};' + or re.search(r';', line) # e.g. 'class Foo;' + or re.search(r'(class|struct)\s+{', line) # e.g. anon 'class {' + or re.search(r'struct std::', line) # + or not re.search(r'{', line)): + continue + print(line) + names[line_filename(line)] = True + if len(names): + test.error("Files with classes without final/VL_NOT_FINAL: " + + ' '.join(sorted(names.keys()))) + + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +printfll() +cstr() +vsnprintf() +final() + +test.passes() diff --git a/test_regress/t/t_dist_tabs.pl b/test_regress/t/t_dist_tabs.pl deleted file mode 100755 index bc5f0c1a9..000000000 --- a/test_regress/t/t_dist_tabs.pl +++ /dev/null @@ -1,121 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(dist => 1); - -my $root = ".."; - -my $Make_Style_Re = qr!(Makefile)|(\.mk$)|(\.mk\.in$)!; -my $Tabs_Exempt_Re = qr!(\.out$)|(/gtkwave)|(Makefile)|(\.mk$)|(\.mk\.in$)!; -#my $Wide_Exempt_Re = qr!(\.l$)|(\.y$)!; -my $Wide_Exempt_Re = qr!.*!; # clang-tidy generally cleans up - -if (!-r "$root/.git") { - skip("Not in a git repository"); -} else { - ### Must trim output before and after our file list - my %warns; - my $prefix; - my $summary = ""; - { - my $diff = `cd $root && git diff HEAD`; - #print "DS $diff\n" if $Debug; - my $file; - my $atab; - my $btab; - my $lineno = 0; - foreach my $line ((split /\n/, $diff), "+++ b/_the_end") { - $fline = $line; - $fline =~ s!^(\+)#\t!$1!; # special case, lines starting with #\t are OK in Makefiles - if ($line =~ m!^\+\+\+ b/(.*)!) { - if ($file && !$astab && $bstab - && $file =~ $Make_Style_Re) { - $summary = "File modifications add new stray tabs (please untabify the patch):"; - $warns{$file} = "File modification adds new stray tabs (please untabify the patch): $file"; - } - if ($file && !$atab && $btab - && $file !~ $Tabs_Exempt_Re) { - $summary = "File modifications add new tabs (please untabify the patch):"; - $warns{$file} = "File modification adds new tabs (please untabify the patch): $file"; - } - # Next - $file = $1; - $atab = 0; - $btab = 0; - print " File $file\n" if $Self->{verbose}; - } - elsif ($line =~ m!^@@ -?[0-9]+,?[0-9]* \+?([0-9]+)!) { - $lineno = $1 - 1; - } - elsif ($line =~ m!^ !) { - ++$lineno; - if ($line =~ m!^[- ].*\t!) { - print " Had tabs\n" if $Self->{verbose} && !$atab; - $atab = 1; - } - } - elsif ($fline =~ m!^-.+[^\t]\t!) { - print " Had stray tabs\n" if $Self->{verbose} && !$astab; - $astab = 1; - } - elsif ($fline =~ m!^+.+[^\t]\t!) { - print " Inserts stray tabs\n" if $Self->{verbose} && !$bstab; - $bstab = 1; - } - elsif ($line =~ m!^-.*\t!) { - print " Had tabs\n" if $Self->{verbose} && !$atab; - $atab = 1; - } - elsif ($line =~ m!^\+.*\t!) { - ++$lineno; - print " Inserts tabs\n" if $Self->{verbose} && !$btab; - $btab = 1; - } - elsif ($line =~ m!^\+(.*)!) { - ++$lineno; - if ($line =~ /\r/) { - $summary = "File modification adds carriage return (remove them):" if !$summary; - $warns{$file} = "File modification adds carriage return (remove them): $file:$lineno"; - } - my $len = length($1); - if ($len >= 100 - && $file !~ $Tabs_Exempt_Re - && $file !~ $Wide_Exempt_Re) { - print " Wide $line\n" if $Self->{verbose}; - $summary = "File modification adds a new >100 column line:" if !$summary; - $warns{$file} = "File modification adds a new >100 column line: $file:$lineno"; - } - } - } - } - if (keys %warns) { - # First warning lists everything as that's shown in the driver summary - error($summary . " ", join(' ', sort keys %warns)); - foreach my $file (sort keys %warns) { - error($warns{$file}); - } - } -} - -sub _has_tabs { - my $filename = shift; - my $contents = file_contents($filename); - if ($filename =~ /\.out$/) { - # Ignore golden files - } elsif ($contents =~ /[\001\002\003\004\005\006]/) { - # Ignore binary files - } elsif ($contents =~ /\t/) { - return 1; - } - return 0; -} - -ok(1); -1; diff --git a/test_regress/t/t_dist_untracked.pl b/test_regress/t/t_dist_untracked.pl deleted file mode 100755 index a8f155d03..000000000 --- a/test_regress/t/t_dist_untracked.pl +++ /dev/null @@ -1,60 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(dist => 1); - -my $root = ".."; -my $Debug; - -if (!-r "$root/.git") { - skip("Not in a git repository"); -} else { - ### Must trim output before and after our file list - my %warns; - my $prefix; - my $summary; - { - my $status = `cd $root && git ls-files -o --exclude-standard`; - print "ST $status\n" if $Debug; - foreach my $file (sort split /\n/, $status) { - next if $file =~ /nodist/; - if (_has_tabs("$root/$file")) { - $warns{$file} = "File not in git or .gitignore (with tabs): $file"; - $summary = "Files untracked in git or .gitignore (with tabs):"; - } else { - $warns{$file} = "File not in git or .gitignore: $file"; - $summary ||= "Files untracked in git or .gitignore:"; - } - } - } - if (keys %warns) { - # First warning lists everything as that's shown in the driver summary - error($summary . " ", join(' ', sort keys %warns)); - foreach my $file (sort keys %warns) { - error($warns{$file}); - } - } -} - -sub _has_tabs { - my $filename = shift; - my $contents = file_contents($filename); - if ($filename =~ /\.out$/) { - # Ignore golden files - } elsif ($contents =~ /[\001\002\003\004\005\006]/) { - # Ignore binary files - } elsif ($contents =~ /\t/) { - return 1; - } - return 0; -} - -ok(1); -1; diff --git a/test_regress/t/t_dist_untracked.py b/test_regress/t/t_dist_untracked.py new file mode 100755 index 000000000..15545b1d1 --- /dev/null +++ b/test_regress/t/t_dist_untracked.py @@ -0,0 +1,39 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +root = ".." + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +### Must trim output before and after our file list +warns = {} +summary = None + +status = test.run_capture("cd " + root + " && git ls-files -o --exclude-standard") + +if test.verbose: + print("-ST " + status) +for filename in sorted(status.split()): + if re.search('nodist', filename): + continue + warns[filename] = "File not in git or .gitignore: " + filename + summary = "Files untracked in git or .gitignore:" + +if summary: + # First warning lists everything as that's shown in the driver summary + test.error(summary + " " + ' '.join(sorted(warns.keys()))) + for filename in sorted(warns.keys()): + test.error(warns[filename]) + +test.passes() diff --git a/test_regress/t/t_dist_warn_coverage.pl b/test_regress/t/t_dist_warn_coverage.pl deleted file mode 100755 index e19159d45..000000000 --- a/test_regress/t/t_dist_warn_coverage.pl +++ /dev/null @@ -1,214 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -use IO::File; -use strict; -use vars qw($Self); - -scenarios(dist => 1); - -my $root = ".."; -my $Debug = $Self->{verbose}; -my %Messages; -my %Outputs; - -my %Suppressed; -foreach my $s ( - ' exited with ', # Is hit; driver.pl filters out - 'EOF in unterminated string', # Instead get normal unterminated - 'Enum names without values only allowed on numeric types', # Hard to hit - 'Enum ranges must be integral, per spec', # Hard to hit - 'Return with return value isn\'t underneath a function', # Hard to hit, get other bad return messages - 'Syntax error: Range \':\', \'+:\' etc are not allowed in the instance ', # Instead get syntax error - 'Syntax error parsing real: \'', # Instead can't lex the number - 'Unsupported: Ranges ignored in port-lists', # Hard to hit - 'dynamic new() not expected in this context (expected under an assign)', # Instead get syntax error - # Not yet analyzed - ' loading non-variable', - '--pipe-filter protocol error, unexpected: ', - '/*verilator sformat*/ can only be applied to last argument of ', - 'Argument needed for string.', - 'Array initialization has too few elements, need element ', - 'Assigned pin is neither input nor output', - 'Assignment pattern with no members', - 'Can\'t find varpin scope of ', - 'Can\'t resolve module reference: \'', - 'Cannot write preprocessor output: ', - 'Circular logic when ordering code (non-cutable edge loop)', - 'Define or directive not defined: `', - 'Exceeded limit of ', - 'Extern declaration\'s scope is not a defined class', - 'Format to $display-like function must have constant format string', - 'Forward typedef used as class/package does not resolve to class/package: ', - 'Illegal +: or -: select; type already selected, or bad dimension: ', - 'Illegal bit or array select; type already selected, or bad dimension: ', - 'Illegal range select; type already selected, or bad dimension: ', - 'Interface port ', - 'Member selection of non-struct/union object \'', - 'Modport item is not a function/task: ', - 'Modport item is not a variable: ', - 'Modport item not found: ', - 'Modport not referenced as .', - 'Modport not referenced from underneath an interface: ', - 'Non-interface used as an interface: ', - 'Parameter type pin value isn\'t a type: Param ', - 'Parameter type variable isn\'t a type: Param ', - 'Pattern replication value of 0 is not legal.', - 'Signals inside functions/tasks cannot be marked forceable', - 'Slice size cannot be zero.', - 'Slices of arrays in assignments have different unpacked dimensions, ', - 'String of ', - 'Symbol matching ', - 'Unexpected connection to arrayed port', - 'Unsized numbers/parameters not allowed in streams.', - 'Unsupported RHS tristate construct: ', - 'Unsupported or syntax error: Unsized range in instance or other declaration', - 'Unsupported pullup/down (weak driver) construct.', - 'Unsupported tristate construct (not in propagation graph): ', - 'Unsupported tristate port expression: ', - 'Unsupported/Illegal: Assignment pattern', - 'Unsupported/unknown built-in dynamic array method ', - 'Unsupported: $bits for queue', - 'Unsupported: $c can\'t generate wider than 64 bits', - 'Unsupported: 4-state numbers in this context', - 'Unsupported: Concatenation to form ', - 'Unsupported: Non-variable on LHS of built-in method \'', - 'Unsupported: Only one PSL clock allowed per assertion', - 'Unsupported: Per-bit array instantiations ', - 'Unsupported: Public functions with >64 bit outputs; ', - 'Unsupported: RHS of ==? or !=? must be ', - 'Unsupported: Replication to form ', - 'Unsupported: Shifting of by over 32-bit number isn\'t supported.', - 'Unsupported: Signal strengths are unsupported ', - 'Unsupported: Size-changing cast on non-basic data type', - 'Unsupported: Slice of non-constant bounds', - 'Unsupported: Unclocked assertion', - 'Unsupported: don\'t know how to deal with ', - 'Unsupported: event arrays', - 'Unsupported: modport export', - 'Unsupported: no_inline for tasks', - 'Unsupported: static cast to ', - 'Unsupported: super', - ) { $Suppressed{$s} = 1; } - -if (!-r "$root/.git") { - skip("Not in a git repository"); -} else { - check(); -} - -ok(1); -1; - -sub check { - read_messages(); - read_outputs(); - - print "Number of suppressions = ", scalar(keys %Suppressed), "\n"; - print "Coverage = ", 100 - int(100 * scalar(keys %Suppressed) / scalar(keys %Messages)), "%\n"; - print "\n"; - - print "Checking for v3error/v3warn messages in sources without coverage in test_regress/t/*.out:\n"; - print "(Developers: If a message is impossible, use UASSERT or v3fatalSrc instead of v3error)"; - print "\n"; - - my %used_suppressed; - msg: - for my $msg (sort {$Messages{$a}{fileline} cmp $Messages{$b}{fileline}} keys %Messages) { - my $fileline = $Messages{$msg}{fileline}; - for my $output (keys %Outputs) { - if (index($output, $msg) != -1) { - # print "$fileline: M '$msg' HIT '$output'\n"; - next msg; - } - } - # Some exceptions - next msg if ($msg =~ /internal:/i); - - my $line = $Messages{$msg}{line}; - chomp $line; - $line =~ s/^\s+//; - - if (%Suppressed{$msg}) { - $used_suppressed{$msg} = 1; - print "$fileline: Suppressed check for message in source: '$msg'\n" if $Debug; - } else { - error("$fileline: Missing test_regress/t/*.out test for message in source: '$msg'"); - print(" Line is: ", $line, "\n") if $Debug; - } - } - print "\n"; - - for my $msg (sort keys %Suppressed) { - if (!$used_suppressed{$msg}) { - print "Suppression not used: '$msg'\n"; - } - } - print "\n"; -} - -sub read_messages { - foreach my $filename (glob "$root/src/*") { - my $fh = IO::File->new("<$filename") - or error("$! $filename"); - my $lineno = 0; - my $read_next; - line: - while (my $origline = ($fh && $fh->getline)) { - my $line = $origline; - next if $line =~ m!^\s*//!; - next if $line =~ m!^\s*/\*!; - ++$lineno; - if ($line =~ /\b(v3error|v3warn)\b\($/g) { - $read_next = 1 if $line !~ /LCOV_EXCL_LINE/; - next line; - } - if ($line =~ s/.*\b(v3error|v3warn)\b//g) { - $read_next = 1 if $line !~ /LCOV_EXCL_LINE/; - } - if ($read_next) { - $read_next = 0; - next if $line =~ /LCOV_EXCL_LINE/; - next if $line =~ /\\/; # \" messes up next part - if ($line =~ /"([^"]*)"/) { - my $msg = $1; - my $fileline = $filename . ":" . $lineno; - # print "FFFF $fileline: $msg LL $line\n"; - $Messages{$msg}{fileline} = $fileline; - $Messages{$msg}{line} = $origline; - } - } - } - } - print "Number of messages = ",scalar(keys %Messages), "\n"; -} - -sub read_outputs { - file: - foreach my $filename (glob ("$root/test_regress/t/*.pl" - . " $root/test_regress/t/*.out" - . " $root/docs/gen/*.rst")) { - next if $filename =~ /t_dist_warn_coverage/; # Avoid our own suppressions - my $fh = IO::File->new("<$filename") - or error("$! $filename"); - while (my $line = ($fh && $fh->getline)) { - if ($line =~ /^\$date/) { - # Assume it is a VCD file - next file; - } - $Outputs{$line} = 1; - } - } - print "Number of outputs = ",scalar(keys %Outputs), "\n"; -} - -# Local Variables: -# compile-command:"./t_dist_warn_coverage.pl" -# End: diff --git a/test_regress/t/t_dist_warn_coverage.py b/test_regress/t/t_dist_warn_coverage.py new file mode 100755 index 000000000..9493251d0 --- /dev/null +++ b/test_regress/t/t_dist_warn_coverage.py @@ -0,0 +1,218 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +root = ".." + +Messages = {} +Outputs = {} +Suppressed = {} + +for s in [ + ' exited with ', # Is hit; driver.py filters out + 'EOF in unterminated string', # Instead get normal unterminated + 'Enum names without values only allowed on numeric types', # Hard to hit + 'Enum ranges must be integral, per spec', # Hard to hit + 'Return with return value isn\'t underneath a function', # Hard to hit, get other bad return messages + 'Syntax error: Range \':\', \'+:\' etc are not allowed in the instance ', # Instead get syntax error + 'Syntax error parsing real: \'', # Instead can't lex the number + 'Unsupported: Ranges ignored in port-lists', # Hard to hit + 'dynamic new() not expected in this context (expected under an assign)', # Instead get syntax error + # Not yet analyzed + ' loading non-variable', + '--pipe-filter protocol error, unexpected: ', + '/*verilator sformat*/ can only be applied to last argument of ', + 'Argument needed for string.', + 'Array initialization has too few elements, need element ', + 'Assigned pin is neither input nor output', + 'Assignment pattern with no members', + 'Can\'t find varpin scope of ', + 'Can\'t resolve module reference: \'', + 'Cannot write preprocessor output: ', + 'Circular logic when ordering code (non-cutable edge loop)', + 'Define or directive not defined: `', + 'Exceeded limit of ', + 'Extern declaration\'s scope is not a defined class', + 'Format to $display-like function must have constant format string', + 'Forward typedef used as class/package does not resolve to class/package: ', + 'Illegal +: or -: select; type already selected, or bad dimension: ', + 'Illegal bit or array select; type already selected, or bad dimension: ', + 'Illegal range select; type already selected, or bad dimension: ', + 'Interface port ', + 'Member selection of non-struct/union object \'', + 'Modport item is not a function/task: ', + 'Modport item is not a variable: ', + 'Modport item not found: ', + 'Modport not referenced as .', + 'Modport not referenced from underneath an interface: ', + 'Non-interface used as an interface: ', + 'Parameter type pin value isn\'t a type: Param ', + 'Parameter type variable isn\'t a type: Param ', + 'Pattern replication value of 0 is not legal.', + 'Signals inside functions/tasks cannot be marked forceable', + 'Slice size cannot be zero.', + 'Slices of arrays in assignments have different unpacked dimensions, ', + 'String of ', + 'Symbol matching ', + 'Unexpected connection to arrayed port', + 'Unsized numbers/parameters not allowed in streams.', + 'Unsupported RHS tristate construct: ', + 'Unsupported or syntax error: Unsized range in instance or other declaration', + 'Unsupported pullup/down (weak driver) construct.', + 'Unsupported tristate construct (not in propagation graph): ', + 'Unsupported tristate port expression: ', + 'Unsupported/unknown built-in dynamic array method ', + 'Unsupported: $bits for queue', + 'Unsupported: $c can\'t generate wider than 64 bits', + 'Unsupported: 4-state numbers in this context', + 'Unsupported: Concatenation to form ', + 'Unsupported: Non-variable on LHS of built-in method \'', + 'Unsupported: Only one PSL clock allowed per assertion', + 'Unsupported: Per-bit array instantiations ', + 'Unsupported: Public functions with >64 bit outputs; ', + 'Unsupported: RHS of ==? or !=? must be ', + 'Unsupported: Replication to form ', + 'Unsupported: Shifting of by over 32-bit number isn\'t supported.', + 'Unsupported: Signal strengths are unsupported ', + 'Unsupported: Size-changing cast on non-basic data type', + 'Unsupported: Slice of non-constant bounds', + 'Unsupported: Unclocked assertion', + 'Unsupported: don\'t know how to deal with ', + 'Unsupported: event arrays', + 'Unsupported: modport export', + 'Unsupported: no_inline for tasks', + 'Unsupported: static cast to ', + 'Unsupported: super', +]: + Suppressed[s] = True + + +def read_messages(): + for filename in test.glob_some(root + "/src/*"): + if not os.path.isfile(filename): + continue + with open(filename, 'r', encoding="utf8") as fh: + lineno = 0 + read_next = None + + for origline in fh: + line = origline + lineno += 1 + if re.match(r'^\s*//', line): + continue + if re.match(r'^\s*/\*', line): + continue + if re.search(r'\b(v3error|v3warn)\b\($', line): + if 'LCOV_EXCL_LINE' not in line: + read_next = True + continue + m = re.search(r'.*\b(v3error|v3warn)\b(.*)', line) + if m: + line = m.group(2) + if 'LCOV_EXCL_LINE' not in line: + read_next = True + if read_next: + read_next = False + if 'LCOV_EXCL_LINE' in line: + continue + if "\\" in line: # \" messes up next part + continue + m = re.search(r'"([^"]*)"', line) + if m: + msg = m.group(1) + fileline = filename + ":" + str(lineno) + # print("FFFF " + fileline + ": " + msg + " LL " + line) + Messages[msg] = {} + Messages[msg]['fileline'] = fileline + Messages[msg]['line'] = origline + + print("Number of messages = " + str(len(Messages))) + + +def read_outputs(): + for filename in (test.glob_some(root + "/test_regress/t/*.py") + + test.glob_some(root + "/test_regress/t/*.out") + + test.glob_some(root + "/docs/gen/*.rst")): + if "t_dist_warn_coverage" in filename: # Avoid our own suppressions + continue + with open(filename, 'r', encoding="latin-1") as fh: + for line in fh: + if re.match(r'^\$date', line): # Assume it is a VCD file + break + line = line.lstrip().rstrip() + Outputs[line] = True + + print("Number of outputs = " + str(len(Outputs))) + + +def check(): + read_messages() + read_outputs() + + print("Number of suppressions = " + str(len(Suppressed))) + print("Coverage = ", str(100 - int(100 * len(Suppressed) / len(Messages)))) + print() + + print("Checking for v3error/v3warn messages in sources without") + print("coverage in test_regress/t/*.out:") + print("(Developers: If a message is impossible to test, use UASSERT or") + print("v3fatalSrc instead of v3error)") + print() + + used_suppressed = {} + + for msg in sorted(Messages.keys()): + fileline = Messages[msg]['fileline'] + next_msg = False + for output in Outputs: + if msg in output: + # print(fileline+": M '" + msg + "' HIT '" + output) + next_msg = True + break + + if next_msg: + continue + + # Some exceptions + if re.match(r'internal:', msg, re.IGNORECASE): + continue + + line = Messages[msg]['line'] + line = line.lstrip().rstrip() + + if msg in Suppressed: + used_suppressed[msg] = True + if test.verbose: + print(fileline + ": Suppressed check for message in source: '" + msg + "'") + else: + test.error(fileline + ": Missing test_regress/t/*.out test for message in source: '" + + msg + "'") + if test.verbose: + print(" Line is: " + line) + + print() + for msg in sorted(Suppressed.keys()): + if msg not in used_suppressed: + print("Suppression not used: '" + msg + "'") + print() + + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +check() + +test.passes() + +# Local Variables: +# compile-command:"./t_dist_warn_coverage.py" +# End: diff --git a/test_regress/t/t_dist_whitespace.pl b/test_regress/t/t_dist_whitespace.pl deleted file mode 100755 index f1c28607e..000000000 --- a/test_regress/t/t_dist_whitespace.pl +++ /dev/null @@ -1,112 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(dist => 1); - -my $root = ".."; - -if (!-r "$root/.git") { - skip("Not in a git repository"); -} else { - my $root = ".."; - my $Debug; - - ### Must trim output before and after our file list - my %files = %{get_source_files($root)}; - - my $any = 0; - foreach my $file (sort keys %files) { - my $filename = "$root/$file"; - next if !-f $filename; # git file might be deleted but not yet staged - my $contents = file_contents($filename); - if ($file =~ /(\.out|\.dat)$/) { - # Ignore golden files - next; - } elsif ($contents =~ /[\001\002\003\004\005\006]/) { - # Ignore binary files - next; - } - if ($contents !~ /\n$/s && $contents ne "") { - $warns{$file} = "Missing trailing newline in $file"; - } - if ($contents =~ /[ \t]\n/ - || $contents =~ m/\n\n+$/) { # Regexp repeated below - my $eol_ws_exempt = ($file =~ /spelling.txt$/ - || $file =~ m!/gtkwave/!); - next if $eol_ws_exempt; - if ($ENV{HARNESS_UPDATE_GOLDEN}) { - my $changes = undef; - $changes = 1 if ($contents =~ s/[ \t]+\n/\n/g); - $changes = 1 if (!$eol_ws_exempt && $contents =~ s/\n\n+$/\n/g); - next if (!$changes); - $warns{$file} = "Updated whitespace at $file"; - write_wholefile($filename, $contents); - next; - } - my @lines = split(/\n/, $contents); - my $line_no = 0; - foreach my $line (@lines) { - $line_no++; - # Trim trailing carriage-return (ASCII 0x0d) and form feed (0x0c), - # as we expect a few of those - $line =~ s/[\x{d}\x{c}]//g; - if ($line =~ /\s$/) { - $warns{$file} = "Trailing whitespace at $file:$line_no"; - $warns{$file} .= " (last character is ASCII " . ord(substr($line, -1, 1)) . ")"; - } - } - if ($contents =~ m/\n\n+$/ && !$eol_ws_exempt) { # Regexp repeated above - $warns{$file} = "Trailing newlines at EOF in $file"; - } - } - # Unicode checker; should this be done in another file? - # No way to auto-fix. - # Files with \r are flagged elsewhere, right? - if ($contents =~ /[^[:alnum:][:punct:] \t\r\n]/) { - my $unicode_exempt = ($file =~ /Changes$/ - || $file =~ /CONTRIBUTORS$/ - || $file =~ /contributors.rst$/ - || $file =~ /spelling.txt$/); - next if $unicode_exempt; - $warns{$file} = "Warning: non-ASCII contents in $file\n"; - } - ++$any; - } - $any > 50 or error("Too few source files found"); - - if (keys %warns) { - # First warning lists everything as that's shown in the driver summary - if ($ENV{HARNESS_UPDATE_GOLDEN}) { - error("Updated files with whitespace errors: ", join(' ', sort keys %warns)); - error("To auto-fix: HARNESS_UPDATE_GOLDEN=1 {command} or --golden"); - } else { - error("Files have whitespace errors: ", join(' ', sort keys %warns)); - error("To auto-fix: HARNESS_UPDATE_GOLDEN=1 {command} or --golden"); - } - foreach my $file (sort keys %warns) { - error($warns{$file}); - } - } -} - -ok(1); -1; - -sub get_source_files { - my $root = shift; - my $git_files = `cd $root && git ls-files`; - print "MF $git_files\n" if $Self->{verbose}; - my %files; - foreach my $file (split /\s+/, $git_files) { - next if $file eq ''; - $files{$file} |= 1; - } - return \%files; -} diff --git a/test_regress/t/t_dist_whitespace.py b/test_regress/t/t_dist_whitespace.py new file mode 100755 index 000000000..1c9da5b27 --- /dev/null +++ b/test_regress/t/t_dist_whitespace.py @@ -0,0 +1,115 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +root = ".." + +Tabs_Exempt_Re = r'(\.out$)|(/gtkwave)|(Makefile)|(\.mk$)|(\.mk\.in$)|test_regress/t/t_preproc\.v|install-sh' + + +def get_source_files(root): + git_files = test.run_capture("cd " + root + " && git ls-files") + if test.verbose: + print("MF " + git_files) + files = {} + for filename in git_files.split(): + if filename == '': + continue + files[filename] = True + return files + + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +root = ".." + +files = get_source_files(root) + +warns = {} +fcount = 0 +for filename in sorted(files.keys()): + filename = os.path.join(root, filename) + if not os.path.exists(filename): # git file might be deleted but not yet staged + continue + contents = test.file_contents(filename) + if re.search(r'(\.out|\.dat)$', filename): + continue # Ignore golden files + if re.search(r'[\001\002\003\004\005\006]', contents): + continue # Ignore binary files + if contents != "" and contents[-1] != "\n": + contents += "\n" + warns[filename] = "Missing trailing newline (add one) in " + filename + if "\r" in contents: + contents = re.sub(r'\r', '', contents) + warns[filename] = "Carriage returns (remove them) in: " + filename + if "\f" in contents: + contents = re.sub(r'\f', '', contents) + warns[filename] = "Form-feeds (remove them) in: " + filename + if "\t" in contents and not re.search(Tabs_Exempt_Re, filename): + warns[filename] = "Tabs (cannot --gold fix) in " + filename + + if (re.search(r'[ \t]\n', contents) + or re.search(r'\n\n+$', contents)): # Regexp repeated below + eol_ws_exempt = ('spelling.txt' in filename or '/gtkwave/' in filename) + if eol_ws_exempt: + continue + if 'HARNESS_UPDATE_GOLDEN' in os.environ: + changes = False + (contents, n) = re.subn(r'[ \t]+\n', '\n', contents) + if n: + changes = True + if not eol_ws_exempt: + (contents, n) = re.subn(r'\n\n+$', '\n', contents) + if n: + changes = True + if not changes: + continue + warns[filename] = "Updated whitespace at " + filename + test.write_wholefile(filename, contents) + continue + + lineno = 0 + for line in contents.splitlines(): + lineno += 1 + if re.search(r'\s$', line): + warns[filename] = "Trailing whitespace at " + filename + ":" + str(lineno) + warns[filename] += " (last character is ASCII " + str(ord(line[-1])) + ")" + + if not eol_ws_exempt and re.search(r'\n\n+$', contents): # Regexp repeated above + warns[filename] = "Trailing newlines at EOF in " + filename + + # Unicode checker; should this be done in another file? + # No way to auto-fix. + unicode_exempt = (re.search(r'Changes$', filename) or re.search(r'CONTRIBUTORS$', filename) + or re.search(r'contributors.rst$', filename) + or re.search(r'spelling.txt$', filename)) + if not unicode_exempt and re.search(r'[^ \t\r\n\x20-\x7e]', contents): + warns[filename] = "Warning: non-ASCII contents in " + filename + + fcount += 1 + +if fcount < 50: + test.error("Too few source files found") + +if len(warns): + # First warning lists everything as that's shown in the driver summary + if 'HARNESS_UPDATE_GOLDEN' in os.environ: + test.error("Updated files with whitespace errors: " + ' '.join(sorted(warns.keys()))) + test.error("To auto-fix: HARNESS_UPDATE_GOLDEN=1 {command} or --golden") + else: + test.error("Files have whitespace errors: " + ' '.join(sorted(warns.keys()))) + test.error("To auto-fix: HARNESS_UPDATE_GOLDEN=1 {command} or --golden") + for filename in sorted(warns.keys()): + test.error(warns[filename]) + +test.passes() diff --git a/test_regress/t/t_do_not_convert_to_comb.pl b/test_regress/t/t_do_not_convert_to_comb.pl deleted file mode 100755 index 0e3a18189..000000000 --- a/test_regress/t/t_do_not_convert_to_comb.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -# We must not convert these blocks into combinational blocks -file_grep($Self->{stats}, qr/Scheduling, size of class: combinational\s+(\d+)/, 0); - -ok(1); -1; diff --git a/test_regress/t/t_do_not_convert_to_comb.py b/test_regress/t/t_do_not_convert_to_comb.py new file mode 100755 index 000000000..a5c94d9ff --- /dev/null +++ b/test_regress/t/t_do_not_convert_to_comb.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(verilator_flags2=["--stats"]) + +# We must not convert these blocks into combinational blocks +test.file_grep(test.stats, r'Scheduling, size of class: combinational\s+(\d+)', 0) + +test.passes() diff --git a/test_regress/t/t_do_while.pl b/test_regress/t/t_do_while.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_do_while.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_do_while.py b/test_regress/t/t_do_while.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_do_while.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dos.pl b/test_regress/t/t_dos.pl deleted file mode 100755 index c91292e54..000000000 --- a/test_regress/t/t_dos.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['-Wall -Wno-DECLFILENAME'], # To check EOFNEWLINE with DOS CRs - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_dos.py b/test_regress/t/t_dos.py new file mode 100755 index 000000000..c3fb5ff74 --- /dev/null +++ b/test_regress/t/t_dos.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['-Wall -Wno-DECLFILENAME']) # To check EOFNEWLINE with DOS CRs + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dotfiles.pl b/test_regress/t/t_dotfiles.pl deleted file mode 100755 index e0c05a270..000000000 --- a/test_regress/t/t_dotfiles.pl +++ /dev/null @@ -1,37 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vltmt => 1); - -# Use a top file which we are sure to be parallelizable -top_filename("t/t_gen_alw.v"); - -compile( - v_flags2 => ["--dumpi-graph 6"], - threads => 2 - ); - -foreach my $dotname ("linkcells", "task_call", "gate_graph", "gate_final", - "acyc_simp", "orderg_pre", "orderg_acyc", "orderg_order", "orderg_domain", - "ordermv_initial", "ordermv_hazards", "ordermv_contraction", - "ordermv_transitive1", "orderg_done", "schedule") { - # Some files with identical prefix are generated multiple times during - # Verilation. Ensure that at least one of each $dotname-prefixed file is generated. - @dotFiles = glob("$Self->{obj_dir}/*$dotname.dot"); - if (scalar @dotFiles == 0) { - error("Found no dotfiles with pattern *$dotname.dot"); - } - foreach my $dotFilename (@dotFiles) { - file_grep($dotFilename, qr/digraph v3graph/); - } -} - -ok(1); -1; diff --git a/test_regress/t/t_dotfiles.py b/test_regress/t/t_dotfiles.py new file mode 100755 index 000000000..3930a139e --- /dev/null +++ b/test_regress/t/t_dotfiles.py @@ -0,0 +1,30 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vltmt') + +# Use a top file which we are sure to be parallelizable +test.top_filename = "t/t_gen_alw.v" + +test.compile(v_flags2=["--dumpi-graph 6"], threads=2) + +for dotname in [ + "linkcells", "task_call", "gate_graph", "gate_final", "acyc_simp", "orderg_pre", + "orderg_acyc", "orderg_order", "orderg_domain", "ordermv_initial", "ordermv_hazards", + "ordermv_contraction", "ordermv_transitive1", "orderg_done", "schedule" +]: + # Some files with identical prefix are generated multiple times during + # Verilation. Ensure that at least one of each dotname-prefixed file is generated. + dotFiles = test.glob_some(test.obj_dir + "/*" + dotname + ".dot") + for dotFilename in dotFiles: + test.file_grep(dotFilename, r'digraph v3graph') + +test.passes() diff --git a/test_regress/t/t_dpi_2exp_bad.pl b/test_regress/t/t_dpi_2exp_bad.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_dpi_2exp_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_2exp_bad.py b/test_regress/t/t_dpi_2exp_bad.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_dpi_2exp_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dpi_2exparg_bad.pl b/test_regress/t/t_dpi_2exparg_bad.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_dpi_2exparg_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_2exparg_bad.py b/test_regress/t/t_dpi_2exparg_bad.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_dpi_2exparg_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dpi_accessors.pl b/test_regress/t/t_dpi_accessors.pl deleted file mode 100755 index 90b96520a..000000000 --- a/test_regress/t/t_dpi_accessors.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# 8-Mar-2012: Modifications for this test contributed by Jeremy Bennett and -# Jie Xu. - -scenarios(simulator => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["-Wno-BLKANDNBLK -language 1800-2005 --exe $Self->{t_dir}/$Self->{name}.cpp"], ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_accessors.py b/test_regress/t/t_dpi_accessors.py new file mode 100755 index 000000000..13bbc4ed4 --- /dev/null +++ b/test_regress/t/t_dpi_accessors.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +# 8-Mar-2012: Modifications for this test contributed by Jeremy Bennett and +# Jie Xu. + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["-Wno-BLKANDNBLK -language 1800-2005 --exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_arg_inout_type.pl b/test_regress/t/t_dpi_arg_inout_type.pl deleted file mode 100755 index c945d3a46..000000000 --- a/test_regress/t/t_dpi_arg_inout_type.pl +++ /dev/null @@ -1,42 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if ($Self->{nc}) { - # For NC, compile twice, first just to generate DPI headers - compile( - nc_flags2 => ["+ncdpiheader+$Self->{obj_dir}/dpi-exp.h", - "+ncdpiimpheader+$Self->{obj_dir}/dpi-imp.h"] - ); -} - -compile( - v_flags2 => ["t/$Self->{name}.cpp"], - # --no-decoration so .out file doesn't comment on source lines - verilator_flags2 => ["-Wall -Wno-DECLFILENAME --no-decoration"], - # NC: Gdd the obj_dir to the C include path - nc_flags2 => ["+ncscargs+-I$Self->{obj_dir}"], - # ModelSim: Generate DPI header, add obj_dir to the C include path - ms_flags2 => ["-dpiheader $Self->{obj_dir}/dpi.h", - "-ccflags -I$Self->{obj_dir}"], - ); - -if ($Self->{vlt_all}) { - files_identical("$Self->{obj_dir}/$Self->{vm_prefix}__Dpi.h", - "t/$Self->{name}__Dpi.out"); -} - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_arg_inout_type.py b/test_regress/t/t_dpi_arg_inout_type.py new file mode 100755 index 000000000..50423db37 --- /dev/null +++ b/test_regress/t/t_dpi_arg_inout_type.py @@ -0,0 +1,36 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if test.nc: + # For NC, compile twice, first just to generate DPI headers + test.compile(nc_flags2=[ + "+ncdpiheader+" + test.obj_dir + "/dpi-exp.h", "+ncdpiimpheader+" + test.obj_dir + + "/dpi-imp.h" + ]) + +test.compile( + v_flags2=["t/" + test.name + ".cpp"], + # --no-decoration so .out file doesn't comment on source lines + verilator_flags2=["-Wall -Wno-DECLFILENAME --no-decoration"], + # NC: Gdd the obj_dir to the C include path + nc_flags2=["+ncscargs+-I" + test.obj_dir], + # ModelSim: Generate DPI header, add obj_dir to the C include path + ms_flags2=["-dpiheader " + test.obj_dir + "/dpi.h", "-ccflags -I" + test.obj_dir]) + +if test.vlt_all: + test.files_identical(test.obj_dir + "/" + test.vm_prefix + "__Dpi.h", + "t/" + test.name + "__Dpi.out") + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dpi_arg_inout_unpack.pl b/test_regress/t/t_dpi_arg_inout_unpack.pl deleted file mode 100755 index 9c22e3e54..000000000 --- a/test_regress/t/t_dpi_arg_inout_unpack.pl +++ /dev/null @@ -1,41 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if ($Self->{nc}) { - # For NC, compile twice, first just to generate DPI headers - compile( - nc_flags2 => ["+ncdpiheader+$Self->{obj_dir}/dpi-exp.h", - "+ncdpiimpheader+$Self->{obj_dir}/dpi-imp.h"] - ); -} - -compile( - v_flags2 => ["t/$Self->{name}.cpp"], - # --no-decoration so .out file doesn't comment on source lines - verilator_flags2 => ["-Wall -Wno-DECLFILENAME --no-decoration"], - # NC: Gdd the obj_dir to the C include path - nc_flags2 => ["+ncscargs+-I$Self->{obj_dir}"], - # ModelSim: Generate DPI header, add obj_dir to the C include path - ms_flags2 => ["-dpiheader $Self->{obj_dir}/dpi.h", - "-ccflags -I$Self->{obj_dir}"], - ); - -if ($Self->{vlt_all}) { - files_identical("$Self->{obj_dir}/$Self->{vm_prefix}__Dpi.h", - "t/$Self->{name}__Dpi.out"); -} - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_arg_inout_unpack.py b/test_regress/t/t_dpi_arg_inout_unpack.py new file mode 100755 index 000000000..866c0c9db --- /dev/null +++ b/test_regress/t/t_dpi_arg_inout_unpack.py @@ -0,0 +1,36 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if test.nc: + # For NC, compile twice, first just to generate DPI headers + test.compile(nc_flags2=[ + "+ncdpiheader+" + test.obj_dir + "/dpi-exp.h", "+ncdpiimpheader+" + test.obj_dir + + "/dpi-imp.h" + ]) + +test.compile( + v_flags2=["t/" + test.name + ".cpp"], + # --no-decoration so .out file doesn't comment on source lines + verilator_flags2=["-Wall -Wno-DECLFILENAME --no-decoration"], + # NC: Gdd the obj_dir to the C include path + nc_flags2=["+ncscargs+-I" + test.obj_dir], + # ModelSim: Generate DPI header, add obj_dir to the C include path + ms_flags2=["-dpiheader " + test.obj_dir + "/dpi.h", "-ccflags -I" + test.obj_dir]) + +if test.vlt_all: + test.files_identical(test.obj_dir + "/" + test.vm_prefix + "__Dpi.h", + "t/" + test.name + "__Dpi.out") + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_arg_input_type.pl b/test_regress/t/t_dpi_arg_input_type.pl deleted file mode 100755 index c945d3a46..000000000 --- a/test_regress/t/t_dpi_arg_input_type.pl +++ /dev/null @@ -1,42 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if ($Self->{nc}) { - # For NC, compile twice, first just to generate DPI headers - compile( - nc_flags2 => ["+ncdpiheader+$Self->{obj_dir}/dpi-exp.h", - "+ncdpiimpheader+$Self->{obj_dir}/dpi-imp.h"] - ); -} - -compile( - v_flags2 => ["t/$Self->{name}.cpp"], - # --no-decoration so .out file doesn't comment on source lines - verilator_flags2 => ["-Wall -Wno-DECLFILENAME --no-decoration"], - # NC: Gdd the obj_dir to the C include path - nc_flags2 => ["+ncscargs+-I$Self->{obj_dir}"], - # ModelSim: Generate DPI header, add obj_dir to the C include path - ms_flags2 => ["-dpiheader $Self->{obj_dir}/dpi.h", - "-ccflags -I$Self->{obj_dir}"], - ); - -if ($Self->{vlt_all}) { - files_identical("$Self->{obj_dir}/$Self->{vm_prefix}__Dpi.h", - "t/$Self->{name}__Dpi.out"); -} - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_arg_input_type.py b/test_regress/t/t_dpi_arg_input_type.py new file mode 100755 index 000000000..50423db37 --- /dev/null +++ b/test_regress/t/t_dpi_arg_input_type.py @@ -0,0 +1,36 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if test.nc: + # For NC, compile twice, first just to generate DPI headers + test.compile(nc_flags2=[ + "+ncdpiheader+" + test.obj_dir + "/dpi-exp.h", "+ncdpiimpheader+" + test.obj_dir + + "/dpi-imp.h" + ]) + +test.compile( + v_flags2=["t/" + test.name + ".cpp"], + # --no-decoration so .out file doesn't comment on source lines + verilator_flags2=["-Wall -Wno-DECLFILENAME --no-decoration"], + # NC: Gdd the obj_dir to the C include path + nc_flags2=["+ncscargs+-I" + test.obj_dir], + # ModelSim: Generate DPI header, add obj_dir to the C include path + ms_flags2=["-dpiheader " + test.obj_dir + "/dpi.h", "-ccflags -I" + test.obj_dir]) + +if test.vlt_all: + test.files_identical(test.obj_dir + "/" + test.vm_prefix + "__Dpi.h", + "t/" + test.name + "__Dpi.out") + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dpi_arg_input_unpack.pl b/test_regress/t/t_dpi_arg_input_unpack.pl deleted file mode 100755 index 9c22e3e54..000000000 --- a/test_regress/t/t_dpi_arg_input_unpack.pl +++ /dev/null @@ -1,41 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if ($Self->{nc}) { - # For NC, compile twice, first just to generate DPI headers - compile( - nc_flags2 => ["+ncdpiheader+$Self->{obj_dir}/dpi-exp.h", - "+ncdpiimpheader+$Self->{obj_dir}/dpi-imp.h"] - ); -} - -compile( - v_flags2 => ["t/$Self->{name}.cpp"], - # --no-decoration so .out file doesn't comment on source lines - verilator_flags2 => ["-Wall -Wno-DECLFILENAME --no-decoration"], - # NC: Gdd the obj_dir to the C include path - nc_flags2 => ["+ncscargs+-I$Self->{obj_dir}"], - # ModelSim: Generate DPI header, add obj_dir to the C include path - ms_flags2 => ["-dpiheader $Self->{obj_dir}/dpi.h", - "-ccflags -I$Self->{obj_dir}"], - ); - -if ($Self->{vlt_all}) { - files_identical("$Self->{obj_dir}/$Self->{vm_prefix}__Dpi.h", - "t/$Self->{name}__Dpi.out"); -} - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_arg_input_unpack.py b/test_regress/t/t_dpi_arg_input_unpack.py new file mode 100755 index 000000000..866c0c9db --- /dev/null +++ b/test_regress/t/t_dpi_arg_input_unpack.py @@ -0,0 +1,36 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if test.nc: + # For NC, compile twice, first just to generate DPI headers + test.compile(nc_flags2=[ + "+ncdpiheader+" + test.obj_dir + "/dpi-exp.h", "+ncdpiimpheader+" + test.obj_dir + + "/dpi-imp.h" + ]) + +test.compile( + v_flags2=["t/" + test.name + ".cpp"], + # --no-decoration so .out file doesn't comment on source lines + verilator_flags2=["-Wall -Wno-DECLFILENAME --no-decoration"], + # NC: Gdd the obj_dir to the C include path + nc_flags2=["+ncscargs+-I" + test.obj_dir], + # ModelSim: Generate DPI header, add obj_dir to the C include path + ms_flags2=["-dpiheader " + test.obj_dir + "/dpi.h", "-ccflags -I" + test.obj_dir]) + +if test.vlt_all: + test.files_identical(test.obj_dir + "/" + test.vm_prefix + "__Dpi.h", + "t/" + test.name + "__Dpi.out") + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_arg_output_type.pl b/test_regress/t/t_dpi_arg_output_type.pl deleted file mode 100755 index c945d3a46..000000000 --- a/test_regress/t/t_dpi_arg_output_type.pl +++ /dev/null @@ -1,42 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if ($Self->{nc}) { - # For NC, compile twice, first just to generate DPI headers - compile( - nc_flags2 => ["+ncdpiheader+$Self->{obj_dir}/dpi-exp.h", - "+ncdpiimpheader+$Self->{obj_dir}/dpi-imp.h"] - ); -} - -compile( - v_flags2 => ["t/$Self->{name}.cpp"], - # --no-decoration so .out file doesn't comment on source lines - verilator_flags2 => ["-Wall -Wno-DECLFILENAME --no-decoration"], - # NC: Gdd the obj_dir to the C include path - nc_flags2 => ["+ncscargs+-I$Self->{obj_dir}"], - # ModelSim: Generate DPI header, add obj_dir to the C include path - ms_flags2 => ["-dpiheader $Self->{obj_dir}/dpi.h", - "-ccflags -I$Self->{obj_dir}"], - ); - -if ($Self->{vlt_all}) { - files_identical("$Self->{obj_dir}/$Self->{vm_prefix}__Dpi.h", - "t/$Self->{name}__Dpi.out"); -} - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_arg_output_type.py b/test_regress/t/t_dpi_arg_output_type.py new file mode 100755 index 000000000..50423db37 --- /dev/null +++ b/test_regress/t/t_dpi_arg_output_type.py @@ -0,0 +1,36 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if test.nc: + # For NC, compile twice, first just to generate DPI headers + test.compile(nc_flags2=[ + "+ncdpiheader+" + test.obj_dir + "/dpi-exp.h", "+ncdpiimpheader+" + test.obj_dir + + "/dpi-imp.h" + ]) + +test.compile( + v_flags2=["t/" + test.name + ".cpp"], + # --no-decoration so .out file doesn't comment on source lines + verilator_flags2=["-Wall -Wno-DECLFILENAME --no-decoration"], + # NC: Gdd the obj_dir to the C include path + nc_flags2=["+ncscargs+-I" + test.obj_dir], + # ModelSim: Generate DPI header, add obj_dir to the C include path + ms_flags2=["-dpiheader " + test.obj_dir + "/dpi.h", "-ccflags -I" + test.obj_dir]) + +if test.vlt_all: + test.files_identical(test.obj_dir + "/" + test.vm_prefix + "__Dpi.h", + "t/" + test.name + "__Dpi.out") + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dpi_arg_output_unpack.pl b/test_regress/t/t_dpi_arg_output_unpack.pl deleted file mode 100755 index 9c22e3e54..000000000 --- a/test_regress/t/t_dpi_arg_output_unpack.pl +++ /dev/null @@ -1,41 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if ($Self->{nc}) { - # For NC, compile twice, first just to generate DPI headers - compile( - nc_flags2 => ["+ncdpiheader+$Self->{obj_dir}/dpi-exp.h", - "+ncdpiimpheader+$Self->{obj_dir}/dpi-imp.h"] - ); -} - -compile( - v_flags2 => ["t/$Self->{name}.cpp"], - # --no-decoration so .out file doesn't comment on source lines - verilator_flags2 => ["-Wall -Wno-DECLFILENAME --no-decoration"], - # NC: Gdd the obj_dir to the C include path - nc_flags2 => ["+ncscargs+-I$Self->{obj_dir}"], - # ModelSim: Generate DPI header, add obj_dir to the C include path - ms_flags2 => ["-dpiheader $Self->{obj_dir}/dpi.h", - "-ccflags -I$Self->{obj_dir}"], - ); - -if ($Self->{vlt_all}) { - files_identical("$Self->{obj_dir}/$Self->{vm_prefix}__Dpi.h", - "t/$Self->{name}__Dpi.out"); -} - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_arg_output_unpack.py b/test_regress/t/t_dpi_arg_output_unpack.py new file mode 100755 index 000000000..866c0c9db --- /dev/null +++ b/test_regress/t/t_dpi_arg_output_unpack.py @@ -0,0 +1,36 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if test.nc: + # For NC, compile twice, first just to generate DPI headers + test.compile(nc_flags2=[ + "+ncdpiheader+" + test.obj_dir + "/dpi-exp.h", "+ncdpiimpheader+" + test.obj_dir + + "/dpi-imp.h" + ]) + +test.compile( + v_flags2=["t/" + test.name + ".cpp"], + # --no-decoration so .out file doesn't comment on source lines + verilator_flags2=["-Wall -Wno-DECLFILENAME --no-decoration"], + # NC: Gdd the obj_dir to the C include path + nc_flags2=["+ncscargs+-I" + test.obj_dir], + # ModelSim: Generate DPI header, add obj_dir to the C include path + ms_flags2=["-dpiheader " + test.obj_dir + "/dpi.h", "-ccflags -I" + test.obj_dir]) + +if test.vlt_all: + test.files_identical(test.obj_dir + "/" + test.vm_prefix + "__Dpi.h", + "t/" + test.name + "__Dpi.out") + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_argtype_bad.pl b/test_regress/t/t_dpi_argtype_bad.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_dpi_argtype_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_argtype_bad.py b/test_regress/t/t_dpi_argtype_bad.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_dpi_argtype_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dpi_context.pl b/test_regress/t/t_dpi_context.pl deleted file mode 100755 index 4b9f63f9b..000000000 --- a/test_regress/t/t_dpi_context.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["t/t_dpi_context_c.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_context.py b/test_regress/t/t_dpi_context.py new file mode 100755 index 000000000..8f4de8825 --- /dev/null +++ b/test_regress/t/t_dpi_context.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["t/t_dpi_context_c.cpp"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_context_noopt.pl b/test_regress/t/t_dpi_context_noopt.pl deleted file mode 100755 index 62032fac5..000000000 --- a/test_regress/t/t_dpi_context_noopt.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_dpi_context.v"); - -compile( - v_flags2 => ["t/t_dpi_context_c.cpp"], - verilator_flags2 => [$Self->{vlt_all} ? "-O0" : ""], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_context_noopt.py b/test_regress/t/t_dpi_context_noopt.py new file mode 100755 index 000000000..c9ef10cd5 --- /dev/null +++ b/test_regress/t/t_dpi_context_noopt.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_dpi_context.v" + +test.compile(v_flags2=["t/t_dpi_context_c.cpp"], + verilator_flags2=[("-O0" if test.vlt_all else "")]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_display.pl b/test_regress/t/t_dpi_display.pl deleted file mode 100755 index ac1e79060..000000000 --- a/test_regress/t/t_dpi_display.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["t/t_dpi_display_c.cpp"], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_display.py b/test_regress/t/t_dpi_display.py new file mode 100755 index 000000000..54a8c8ece --- /dev/null +++ b/test_regress/t/t_dpi_display.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["t/t_dpi_display_c.cpp"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dpi_dup_bad.pl b/test_regress/t/t_dpi_dup_bad.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_dpi_dup_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_dup_bad.py b/test_regress/t/t_dpi_dup_bad.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_dpi_dup_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dpi_export.pl b/test_regress/t/t_dpi_export.pl deleted file mode 100755 index bd6ec0b05..000000000 --- a/test_regress/t/t_dpi_export.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# irun -sv top.v t_dpi_export.v -cpost t_dpi_export_c.c -end - -scenarios(simulator => 1); - -compile( - # Amazingly VCS, NC and Verilator all just accept the C file here! - v_flags2 => ["t/t_dpi_export_c.cpp"], - verilator_flags2 => ["-Wall -Wno-DECLFILENAME -no-l2name"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_export.py b/test_regress/t/t_dpi_export.py new file mode 100755 index 000000000..481162f17 --- /dev/null +++ b/test_regress/t/t_dpi_export.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +# irun -sv top.v t_dpi_export.v -cpost t_dpi_export_c.c -end + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["t/t_dpi_export_c.cpp"], + verilator_flags2=["-Wall -Wno-DECLFILENAME -no-l2name"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_export_bad.pl b/test_regress/t/t_dpi_export_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_dpi_export_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_export_bad.py b/test_regress/t/t_dpi_export_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_dpi_export_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dpi_export_context2_bad.pl b/test_regress/t/t_dpi_export_context2_bad.pl deleted file mode 100755 index 93b856ef1..000000000 --- a/test_regress/t/t_dpi_export_context2_bad.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["--exe $Self->{t_dir}/t_dpi_export_context2_bad.cpp"], - make_main => 0, - ); - -execute( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_export_context2_bad.py b/test_regress/t/t_dpi_export_context2_bad.py new file mode 100755 index 000000000..b84ad228c --- /dev/null +++ b/test_regress/t/t_dpi_export_context2_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["--exe", test.pli_filename], make_main=False) + +test.execute(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dpi_export_context_bad.pl b/test_regress/t/t_dpi_export_context_bad.pl deleted file mode 100755 index 3bf347339..000000000 --- a/test_regress/t/t_dpi_export_context_bad.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["--exe $Self->{t_dir}/t_dpi_export_context_bad.cpp"], - make_main => 0, - ); - -execute( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_export_context_bad.py b/test_regress/t/t_dpi_export_context_bad.py new file mode 100755 index 000000000..b84ad228c --- /dev/null +++ b/test_regress/t/t_dpi_export_context_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["--exe", test.pli_filename], make_main=False) + +test.execute(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dpi_export_noopt.pl b/test_regress/t/t_dpi_export_noopt.pl deleted file mode 100755 index feda360cc..000000000 --- a/test_regress/t/t_dpi_export_noopt.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# irun -sv top.v t_dpi_export.v -cpost t_dpi_export_c.c -end - -scenarios(simulator => 1); - -top_filename("t/t_dpi_export.v"); - -compile( - # Amazingly VCS, NC and Verilator all just accept the C file here! - v_flags2 => ["t/t_dpi_export_c.cpp"], - verilator_flags2 => ["-Wall -Wno-DECLFILENAME -no-l2name", - $Self->{vlt_all} ? "-O0" : ""], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_export_noopt.py b/test_regress/t/t_dpi_export_noopt.py new file mode 100755 index 000000000..d6f865acf --- /dev/null +++ b/test_regress/t/t_dpi_export_noopt.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +# irun -sv top.v t_dpi_export.v -cpost t_dpi_export_c.c -end + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_dpi_export.v" + +test.compile( + v_flags2=["t/t_dpi_export_c.cpp"], + verilator_flags2=["-Wall -Wno-DECLFILENAME -no-l2name", ("-O0" if test.vlt_all else "")]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_export_scope_bad.pl b/test_regress/t/t_dpi_export_scope_bad.pl deleted file mode 100755 index 5b97a7901..000000000 --- a/test_regress/t/t_dpi_export_scope_bad.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"], - make_main => 0, - ); - -execute( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_export_scope_bad.py b/test_regress/t/t_dpi_export_scope_bad.py new file mode 100755 index 000000000..b84ad228c --- /dev/null +++ b/test_regress/t/t_dpi_export_scope_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["--exe", test.pli_filename], make_main=False) + +test.execute(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dpi_if_cond.pl b/test_regress/t/t_dpi_if_cond.pl deleted file mode 100755 index 44234b5d0..000000000 --- a/test_regress/t/t_dpi_if_cond.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["t/t_dpi_if_cond_c.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_if_cond.py b/test_regress/t/t_dpi_if_cond.py new file mode 100755 index 000000000..7323376c7 --- /dev/null +++ b/test_regress/t/t_dpi_if_cond.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["t/t_dpi_if_cond_c.cpp"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_imp_gen.pl b/test_regress/t/t_dpi_imp_gen.pl deleted file mode 100755 index b6aa1dca1..000000000 --- a/test_regress/t/t_dpi_imp_gen.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2011 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["t/t_dpi_imp_gen_c.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_imp_gen.py b/test_regress/t/t_dpi_imp_gen.py new file mode 100755 index 000000000..54580144a --- /dev/null +++ b/test_regress/t/t_dpi_imp_gen.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["t/t_dpi_imp_gen_c.cpp"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_import.pl b/test_regress/t/t_dpi_import.pl deleted file mode 100755 index da8e5d1bb..000000000 --- a/test_regress/t/t_dpi_import.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - # Amazingly VCS, NC and Verilator all just accept the C file here! - v_flags2 => ["t/t_dpi_import_c.cpp"], - verilator_flags2 => ["-Wall -Wno-DECLFILENAME"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_import.py b/test_regress/t/t_dpi_import.py new file mode 100755 index 000000000..c1a90041a --- /dev/null +++ b/test_regress/t/t_dpi_import.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["t/t_dpi_import_c.cpp"], verilator_flags2=["-Wall -Wno-DECLFILENAME"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_import_hdr_only.pl b/test_regress/t/t_dpi_import_hdr_only.pl deleted file mode 100755 index b497878f2..000000000 --- a/test_regress/t/t_dpi_import_hdr_only.pl +++ /dev/null @@ -1,48 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Todd Strader. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -use File::Temp; -use File::Compare; - -scenarios(simulator => 1); - -top_filename("t/t_dpi_import.v"); - -my $tmp_dir = File::Temp->newdir(); - -compile( - # Override default flags also - verilator_flags => ["-Wall -Wno-DECLFILENAME -Mdir " . $tmp_dir . " --dpi-hdr-only"], - verilator_make_gmake => 0, - ); - -my @files = glob($tmp_dir . "/*"); - -error("Did not produce DPI header") if scalar(@files) == 0; -error("Too many files created:" . join(', ', @files)) if scalar(@files) > 1; - -my $tmp_header = $files[0]; -print("============" . $tmp_header . "\n"); -error("Unexpected file $tmp_header") unless $tmp_header =~ /__Dpi\.h$/; - -compile( - verilator_flags2 => ["-Wall -Wno-DECLFILENAME"], - verilator_make_gmake => 0, - ); - -@files = glob($Self->obj_dir . "/*__Dpi.h"); -my $header = $files[0]; - -if (compare($tmp_header, $header) != 0) { - error("DPI header files are not the same"); -} - -ok(1); -1; diff --git a/test_regress/t/t_dpi_import_hdr_only.py b/test_regress/t/t_dpi_import_hdr_only.py new file mode 100755 index 000000000..edb00f4b9 --- /dev/null +++ b/test_regress/t/t_dpi_import_hdr_only.py @@ -0,0 +1,45 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import filecmp + +test.scenarios('simulator') +test.top_filename = "t/t_dpi_import.v" + +tmp_dir = test.obj_dir + "/dpi-hdr" +test.mkdir_ok(tmp_dir) + +test.compile( + # Override default flags also + verilator_flags=["-Wall -Wno-DECLFILENAME -Mdir " + tmp_dir + " --dpi-hdr-only"], + verilator_make_gmake=False) + +files = glob.glob(tmp_dir + "/*") + +if len(files) < 1: + test.error("Did not produce DPI header") +if len(files) > 1: + test.error("Too many files created:" + ', '.join(files)) + +tmp_header = files[0] +print("============" + tmp_header) + +if not re.search(r'__Dpi\.h$', tmp_header): + test.error("Unexpected file " + tmp_header) + +test.compile(verilator_flags2=["-Wall -Wno-DECLFILENAME"], verilator_make_gmake=False) + +files = glob.glob(test.obj_dir + "/*__Dpi.h") +header = files[0] + +if not filecmp.cmp(tmp_header, header): + test.error("DPI header files are not the same") + +test.passes() diff --git a/test_regress/t/t_dpi_import_mix_bad.pl b/test_regress/t/t_dpi_import_mix_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_dpi_import_mix_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_import_mix_bad.py b/test_regress/t/t_dpi_import_mix_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_dpi_import_mix_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dpi_lib.pl b/test_regress/t/t_dpi_lib.pl deleted file mode 100755 index f519458d5..000000000 --- a/test_regress/t/t_dpi_lib.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["t/t_dpi_lib_c.cpp"], - verilator_flags2 => ["-Wall -Wno-DECLFILENAME"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_lib.py b/test_regress/t/t_dpi_lib.py new file mode 100755 index 000000000..f193c7954 --- /dev/null +++ b/test_regress/t/t_dpi_lib.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["t/t_dpi_lib_c.cpp"], verilator_flags2=["-Wall -Wno-DECLFILENAME"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_name_bad.pl b/test_regress/t/t_dpi_name_bad.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_dpi_name_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_name_bad.py b/test_regress/t/t_dpi_name_bad.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_dpi_name_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dpi_open.pl b/test_regress/t/t_dpi_open.pl deleted file mode 100755 index c85c25b09..000000000 --- a/test_regress/t/t_dpi_open.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["t/t_dpi_open_c.cpp"], - verilator_flags2 => ["-Wall -Wno-DECLFILENAME -unroll-count 1"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_open.py b/test_regress/t/t_dpi_open.py new file mode 100755 index 000000000..159176896 --- /dev/null +++ b/test_regress/t/t_dpi_open.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["t/t_dpi_open_c.cpp"], + verilator_flags2=["-Wall -Wno-DECLFILENAME -unroll-count 1"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_open_elem.pl b/test_regress/t/t_dpi_open_elem.pl deleted file mode 100755 index c92315f39..000000000 --- a/test_regress/t/t_dpi_open_elem.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["t/t_dpi_open_elem_c.cpp"], - verilator_flags2 => ["-Wall -Wno-DECLFILENAME -unroll-count 1"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_open_elem.py b/test_regress/t/t_dpi_open_elem.py new file mode 100755 index 000000000..447d00f22 --- /dev/null +++ b/test_regress/t/t_dpi_open_elem.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["t/t_dpi_open_elem_c.cpp"], + verilator_flags2=["-Wall -Wno-DECLFILENAME -unroll-count 1"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_open_oob_bad.pl b/test_regress/t/t_dpi_open_oob_bad.pl deleted file mode 100755 index 8f02d74a8..000000000 --- a/test_regress/t/t_dpi_open_oob_bad.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - v_flags2 => ["t/t_dpi_open_oob_bad_c.cpp"], - verilator_flags2 => ["-Wall -Wno-DECLFILENAME -unroll-count 1"], - ); - -execute( - fails => 0, # DPI warnings are not errors - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_open_oob_bad.py b/test_regress/t/t_dpi_open_oob_bad.py new file mode 100755 index 000000000..a2a8336aa --- /dev/null +++ b/test_regress/t/t_dpi_open_oob_bad.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(v_flags2=["t/t_dpi_open_oob_bad_c.cpp"], + verilator_flags2=["-Wall -Wno-DECLFILENAME -unroll-count 1"]) + +test.execute( + fails=False, # DPI warnings are not errors + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dpi_open_query.pl b/test_regress/t/t_dpi_open_query.pl deleted file mode 100755 index 7e29388a6..000000000 --- a/test_regress/t/t_dpi_open_query.pl +++ /dev/null @@ -1,34 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if ($Self->{nc}) { - # For NC, compile twice, first just to generate DPI headers - compile( - nc_flags2 => ["+ncdpiimpheader+$Self->{obj_dir}/dpi-imp.h"] - ); -} - -compile( - v_flags2 => ["t/t_dpi_open_query.cpp"], - verilator_flags2 => ["-Wall -Wno-DECLFILENAME"], - # NC: Gdd the obj_dir to the C include path - nc_flags2 => ["+ncscargs+-I$Self->{obj_dir}"], - # ModelSim: Generate DPI header, add obj_dir to the C include path - ms_flags2 => ["-dpiheader $Self->{obj_dir}/dpi.h", - "-ccflags -I$Self->{obj_dir}"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_open_query.py b/test_regress/t/t_dpi_open_query.py new file mode 100755 index 000000000..347bb962e --- /dev/null +++ b/test_regress/t/t_dpi_open_query.py @@ -0,0 +1,28 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if test.nc: + # For NC, compile twice, first just to generate DPI headers + test.compile(nc_flags2=["+ncdpiimpheader+" + test.obj_dir + "/dpi-imp.h"]) + +test.compile( + v_flags2=["t/t_dpi_open_query.cpp"], + verilator_flags2=["-Wall -Wno-DECLFILENAME"], + # NC: Gdd the obj_dir to the C include path + nc_flags2=["+ncscargs+-I" + test.obj_dir], + # ModelSim: Generate DPI header, add obj_dir to the C include path + ms_flags2=["-dpiheader " + test.obj_dir + "/dpi.h", "-ccflags -I" + test.obj_dir]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_open_vecval.pl b/test_regress/t/t_dpi_open_vecval.pl deleted file mode 100755 index fb1e95906..000000000 --- a/test_regress/t/t_dpi_open_vecval.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["t/t_dpi_open_vecval_c.cpp"], - verilator_flags2 => ["-Wall -Wno-DECLFILENAME -unroll-count 1"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_open_vecval.py b/test_regress/t/t_dpi_open_vecval.py new file mode 100755 index 000000000..e2ea46c98 --- /dev/null +++ b/test_regress/t/t_dpi_open_vecval.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["t/t_dpi_open_vecval_c.cpp"], + verilator_flags2=["-Wall -Wno-DECLFILENAME -unroll-count 1"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_openfirst.pl b/test_regress/t/t_dpi_openfirst.pl deleted file mode 100755 index 180ffe35c..000000000 --- a/test_regress/t/t_dpi_openfirst.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["t/t_dpi_openfirst_c.cpp"], - verilator_flags2 => ["-Wall -Wno-DECLFILENAME"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_openfirst.py b/test_regress/t/t_dpi_openfirst.py new file mode 100755 index 000000000..13eebeba0 --- /dev/null +++ b/test_regress/t/t_dpi_openfirst.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["t/t_dpi_openfirst_c.cpp"], verilator_flags2=["-Wall -Wno-DECLFILENAME"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_qw.pl b/test_regress/t/t_dpi_qw.pl deleted file mode 100755 index a1ae2da50..000000000 --- a/test_regress/t/t_dpi_qw.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2011 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["t/t_dpi_qw_c.cpp"], - verilator_flags2 => ["-Wall -Wno-DECLFILENAME -Wno-UNOPTFLAT -no-l2name"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_qw.py b/test_regress/t/t_dpi_qw.py new file mode 100755 index 000000000..6e3f18c06 --- /dev/null +++ b/test_regress/t/t_dpi_qw.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["t/t_dpi_qw_c.cpp"], + verilator_flags2=["-Wall -Wno-DECLFILENAME -Wno-UNOPTFLAT -no-l2name"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_result_type.pl b/test_regress/t/t_dpi_result_type.pl deleted file mode 100755 index c945d3a46..000000000 --- a/test_regress/t/t_dpi_result_type.pl +++ /dev/null @@ -1,42 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if ($Self->{nc}) { - # For NC, compile twice, first just to generate DPI headers - compile( - nc_flags2 => ["+ncdpiheader+$Self->{obj_dir}/dpi-exp.h", - "+ncdpiimpheader+$Self->{obj_dir}/dpi-imp.h"] - ); -} - -compile( - v_flags2 => ["t/$Self->{name}.cpp"], - # --no-decoration so .out file doesn't comment on source lines - verilator_flags2 => ["-Wall -Wno-DECLFILENAME --no-decoration"], - # NC: Gdd the obj_dir to the C include path - nc_flags2 => ["+ncscargs+-I$Self->{obj_dir}"], - # ModelSim: Generate DPI header, add obj_dir to the C include path - ms_flags2 => ["-dpiheader $Self->{obj_dir}/dpi.h", - "-ccflags -I$Self->{obj_dir}"], - ); - -if ($Self->{vlt_all}) { - files_identical("$Self->{obj_dir}/$Self->{vm_prefix}__Dpi.h", - "t/$Self->{name}__Dpi.out"); -} - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_result_type.py b/test_regress/t/t_dpi_result_type.py new file mode 100755 index 000000000..50423db37 --- /dev/null +++ b/test_regress/t/t_dpi_result_type.py @@ -0,0 +1,36 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if test.nc: + # For NC, compile twice, first just to generate DPI headers + test.compile(nc_flags2=[ + "+ncdpiheader+" + test.obj_dir + "/dpi-exp.h", "+ncdpiimpheader+" + test.obj_dir + + "/dpi-imp.h" + ]) + +test.compile( + v_flags2=["t/" + test.name + ".cpp"], + # --no-decoration so .out file doesn't comment on source lines + verilator_flags2=["-Wall -Wno-DECLFILENAME --no-decoration"], + # NC: Gdd the obj_dir to the C include path + nc_flags2=["+ncscargs+-I" + test.obj_dir], + # ModelSim: Generate DPI header, add obj_dir to the C include path + ms_flags2=["-dpiheader " + test.obj_dir + "/dpi.h", "-ccflags -I" + test.obj_dir]) + +if test.vlt_all: + test.files_identical(test.obj_dir + "/" + test.vm_prefix + "__Dpi.h", + "t/" + test.name + "__Dpi.out") + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dpi_result_type_bad.pl b/test_regress/t/t_dpi_result_type_bad.pl deleted file mode 100755 index 4d9f82122..000000000 --- a/test_regress/t/t_dpi_result_type_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - verilator_flags2 => ["-Wall --error-limit 0"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_result_type_bad.py b/test_regress/t/t_dpi_result_type_bad.py new file mode 100755 index 000000000..bedc7eb77 --- /dev/null +++ b/test_regress/t/t_dpi_result_type_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, + expect_filename=test.golden_filename, + verilator_flags2=["-Wall --error-limit 0"]) + +test.passes() diff --git a/test_regress/t/t_dpi_shortcircuit.pl b/test_regress/t/t_dpi_shortcircuit.pl deleted file mode 100755 index 5c07e0f1c..000000000 --- a/test_regress/t/t_dpi_shortcircuit.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - v_flags2 => ["t/t_dpi_shortcircuit_c.cpp"], - verilator_flags2 => ["-Wno-DECLFILENAME"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_shortcircuit.py b/test_regress/t/t_dpi_shortcircuit.py new file mode 100755 index 000000000..349844c9a --- /dev/null +++ b/test_regress/t/t_dpi_shortcircuit.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(v_flags2=["t/t_dpi_shortcircuit_c.cpp"], verilator_flags2=["-Wno-DECLFILENAME"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_shortcircuit2.pl b/test_regress/t/t_dpi_shortcircuit2.pl deleted file mode 100755 index 3f291a06e..000000000 --- a/test_regress/t/t_dpi_shortcircuit2.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - # Amazingly VCS, NC and Verilator all just accept the C file here! - v_flags2 => ["t/t_dpi_shortcircuit_c.cpp"], - verilator_flags2 => ["-Wno-DECLFILENAME"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_shortcircuit2.py b/test_regress/t/t_dpi_shortcircuit2.py new file mode 100755 index 000000000..4dffb1ad7 --- /dev/null +++ b/test_regress/t/t_dpi_shortcircuit2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["t/t_dpi_shortcircuit_c.cpp"], verilator_flags2=["-Wno-DECLFILENAME"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_string.pl b/test_regress/t/t_dpi_string.pl deleted file mode 100755 index 17a59ab64..000000000 --- a/test_regress/t/t_dpi_string.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["t/t_dpi_string_c.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_string.py b/test_regress/t/t_dpi_string.py new file mode 100755 index 000000000..b45da9e3c --- /dev/null +++ b/test_regress/t/t_dpi_string.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["t/t_dpi_string_c.cpp"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_sys.pl b/test_regress/t/t_dpi_sys.pl deleted file mode 100755 index 567ebffee..000000000 --- a/test_regress/t/t_dpi_sys.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["t/t_dpi_sys_c.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_sys.py b/test_regress/t/t_dpi_sys.py new file mode 100755 index 000000000..292a39802 --- /dev/null +++ b/test_regress/t/t_dpi_sys.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["t/t_dpi_sys_c.cpp"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_threads.pl b/test_regress/t/t_dpi_threads.pl deleted file mode 100755 index 9ac5db9bb..000000000 --- a/test_regress/t/t_dpi_threads.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2018 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vltmt => 1); - -compile( - v_flags2 => ["t/t_dpi_threads_c.cpp --no-threads-coarsen"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_threads.py b/test_regress/t/t_dpi_threads.py new file mode 100755 index 000000000..f13ae5199 --- /dev/null +++ b/test_regress/t/t_dpi_threads.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vltmt') + +test.compile(v_flags2=["t/t_dpi_threads_c.cpp --no-threads-coarsen"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_threads.v b/test_regress/t/t_dpi_threads.v index 2a80f029a..b8637e62c 100644 --- a/test_regress/t/t_dpi_threads.v +++ b/test_regress/t/t_dpi_threads.v @@ -40,12 +40,12 @@ module t (clk); // Alternatively, the test may be run with "--threads-dpi all" in which case // it should confirm that the calls do run concurrently and do detect a // collision (they should, if the test is set up right.) This is - // t_dpi_threads_collide.pl. + // t_dpi_threads_collide.py. // // Q) Is it a risk that the partitioner will merge or serialize these always // blocks, just by luck, even if the DPI-call serialization code fails? // - // A) Yes, that's why t_dpi_threads_collide.pl also passes + // A) Yes, that's why t_dpi_threads_collide.py also passes // --no-threads-do-coaren to disable MTask coarsening. This ensures that // the MTask graph at the end of FixDataHazards (where we resolve DPI // hazards) is basically the final MTasks graph, and that data hazards diff --git a/test_regress/t/t_dpi_threads_collide.pl b/test_regress/t/t_dpi_threads_collide.pl deleted file mode 100755 index dff046d94..000000000 --- a/test_regress/t/t_dpi_threads_collide.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2018 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -$Self->skip_if_too_few_cores(); - -scenarios(vltmt => 1); - -top_filename("t/t_dpi_threads.v"); - -compile( - v_flags2 => ["t/t_dpi_threads_c.cpp --threads-dpi all --no-threads-coarsen"], - ); - -# Similar to t_dpi_threads, which confirms that Verilator can prevent a -# race between DPI import calls, this test confirms that the race exists -# and that the DPI C code can detect it under --threads-dpi all -# mode. -# -execute( - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_threads_collide.py b/test_regress/t/t_dpi_threads_collide.py new file mode 100755 index 000000000..fe226e43a --- /dev/null +++ b/test_regress/t/t_dpi_threads_collide.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vltmt') +test.top_filename = "t/t_dpi_threads.v" + +test.skip_if_too_few_cores() + +test.compile(v_flags2=["t/t_dpi_threads_c.cpp --threads-dpi all --no-threads-coarsen"]) + +# Similar to t_dpi_threads, which confirms that Verilator can prevent a +# race between DPI import calls, this test confirms that the race exists +# and that the DPI C code can detect it under --threads-dpi all +# mode. +# +test.execute(fails=True) + +test.passes() diff --git a/test_regress/t/t_dpi_type_bad.pl b/test_regress/t/t_dpi_type_bad.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_dpi_type_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_type_bad.py b/test_regress/t/t_dpi_type_bad.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_dpi_type_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dpi_unpack_bad.pl b/test_regress/t/t_dpi_unpack_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_dpi_unpack_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_unpack_bad.py b/test_regress/t/t_dpi_unpack_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_dpi_unpack_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dpi_vams.pl b/test_regress/t/t_dpi_vams.pl deleted file mode 100755 index faffdbdec..000000000 --- a/test_regress/t/t_dpi_vams.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe", "$Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_vams.py b/test_regress/t/t_dpi_vams.py new file mode 100755 index 000000000..f37ad07c8 --- /dev/null +++ b/test_regress/t/t_dpi_vams.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_var.pl b/test_regress/t/t_dpi_var.pl deleted file mode 100755 index fa02ebd9d..000000000 --- a/test_regress/t/t_dpi_var.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--no-json-edit-nums", "-DATTRIBUTES --exe --no-l2name $Self->{t_dir}/t_dpi_var.cpp"], - ); - -if ($Self->{vlt_all}) { - file_grep("$out_filename", qr/{"type":"VAR","name":"formatted",.*"loc":"e,56:[^"]*",.*"origName":"formatted",.*"direction":"INPUT",.*"dtypeName":"string",.*"attrSFormat":true/); - file_grep("$out_filename", qr/{"type":"VAR","name":"t.sub.in",.*"loc":"e,77:[^"]*",.*"origName":"in",.*"dtypeName":"int",.*"isSigUserRdPublic":true/); - file_grep("$out_filename", qr/{"type":"VAR","name":"t.sub.fr_a",.*"loc":"e,78:[^"]*",.*"origName":"fr_a",.*"dtypeName":"int",.*"isSigUserRdPublic":true,.*"isSigUserRWPublic":true/); - file_grep("$out_filename", qr/{"type":"VAR","name":"t.sub.fr_b",.*"loc":"e,79:[^"]*",.*"origName":"fr_b",.*"dtypeName":"int",.*"isSigUserRdPublic":true,.*"isSigUserRWPublic":true/); -} - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_var.py b/test_regress/t/t_dpi_var.py new file mode 100755 index 000000000..87e0c90a1 --- /dev/null +++ b/test_regress/t/t_dpi_var.py @@ -0,0 +1,41 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile( + make_top_shell=False, + make_main=False, + verilator_flags2=["--no-json-edit-nums", "-DATTRIBUTES --exe --no-l2name", test.pli_filename]) + +if test.vlt_all: + test.file_grep( + out_filename, + r'{"type":"VAR","name":"formatted",.*"loc":"e,56:[^"]*",.*"origName":"formatted",.*"direction":"INPUT",.*"dtypeName":"string",.*"attrSFormat":true' + ) + test.file_grep( + out_filename, + r'{"type":"VAR","name":"t.sub.in",.*"loc":"e,77:[^"]*",.*"origName":"in",.*"dtypeName":"int",.*"isSigUserRdPublic":true' + ) + test.file_grep( + out_filename, + r'{"type":"VAR","name":"t.sub.fr_a",.*"loc":"e,78:[^"]*",.*"origName":"fr_a",.*"dtypeName":"int",.*"isSigUserRdPublic":true,.*"isSigUserRWPublic":true' + ) + test.file_grep( + out_filename, + r'{"type":"VAR","name":"t.sub.fr_b",.*"loc":"e,79:[^"]*",.*"origName":"fr_b",.*"dtypeName":"int",.*"isSigUserRdPublic":true,.*"isSigUserRWPublic":true' + ) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_var_vlt.pl b/test_regress/t/t_dpi_var_vlt.pl deleted file mode 100755 index e338e3b04..000000000 --- a/test_regress/t/t_dpi_var_vlt.pl +++ /dev/null @@ -1,33 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_dpi_var.v"); -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--no-json-edit-nums", "--exe --no-l2name $Self->{t_dir}/t_dpi_var.vlt $Self->{t_dir}/t_dpi_var.cpp"], - ); - -if ($Self->{vlt_all}) { - file_grep("$out_filename", qr/{"type":"VAR","name":"formatted","addr":"[^"]*","loc":"f,58:[^"]*",.*"origName":"formatted",.*"direction":"INPUT",.*"dtypeName":"string",.*"attrSFormat":true/); - file_grep("$out_filename", qr/{"type":"VAR","name":"t.sub.in","addr":"[^"]*","loc":"f,81:[^"]*",.*"origName":"in",.*"dtypeName":"int",.*"isSigUserRdPublic":true/); - file_grep("$out_filename", qr/{"type":"VAR","name":"t.sub.fr_a","addr":"[^"]*","loc":"f,82:[^"]*",.*"origName":"fr_a",.*"dtypeName":"int",.*"isSigUserRdPublic":true,.*"isSigUserRWPublic":true/); - file_grep("$out_filename", qr/{"type":"VAR","name":"t.sub.fr_b","addr":"[^"]*","loc":"f,83:[^"]*",.*"origName":"fr_b",.*"dtypeName":"int",.*"isSigUserRdPublic":true,.*"isSigUserRWPublic":true/); -} - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_dpi_var_vlt.py b/test_regress/t/t_dpi_var_vlt.py new file mode 100755 index 000000000..b625c8c09 --- /dev/null +++ b/test_regress/t/t_dpi_var_vlt.py @@ -0,0 +1,44 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_dpi_var.v" + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=[ + "--no-json-edit-nums", "--exe --no-l2name", test.t_dir + "/t_dpi_var.vlt", + test.t_dir + "/t_dpi_var.cpp" + ]) + +if test.vlt_all: + test.file_grep( + out_filename, + r'{"type":"VAR","name":"formatted","addr":"[^"]*","loc":"f,58:[^"]*",.*"origName":"formatted",.*"direction":"INPUT",.*"dtypeName":"string",.*"attrSFormat":true' + ) + test.file_grep( + out_filename, + r'{"type":"VAR","name":"t.sub.in","addr":"[^"]*","loc":"f,81:[^"]*",.*"origName":"in",.*"dtypeName":"int",.*"isSigUserRdPublic":true' + ) + test.file_grep( + out_filename, + r'{"type":"VAR","name":"t.sub.fr_a","addr":"[^"]*","loc":"f,82:[^"]*",.*"origName":"fr_a",.*"dtypeName":"int",.*"isSigUserRdPublic":true,.*"isSigUserRWPublic":true' + ) + test.file_grep( + out_filename, + r'{"type":"VAR","name":"t.sub.fr_b","addr":"[^"]*","loc":"f,83:[^"]*",.*"origName":"fr_b",.*"dtypeName":"int",.*"isSigUserRdPublic":true,.*"isSigUserRWPublic":true' + ) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_driver_random.pl b/test_regress/t/t_driver_random.pl deleted file mode 100755 index 482afba94..000000000 --- a/test_regress/t/t_driver_random.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -use IO::File; -use Time::HiRes; - -scenarios(dist => 1); - -if (!$ENV{VERILATOR_TEST_RANDOM_FAILURE}) { - print("Test is for harness checking only, setenv VERILATOR_TEST_RANDOM_FAILURE=1\n"); - ok(1); -} else { - # Randomly fail to test driver.pl - my ($ign, $t) = Time::HiRes::gettimeofday(); - if ($t % 2) { - error("random failure " . $t); - } - else { - ok(1); - } -} -1; diff --git a/test_regress/t/t_driver_random.py b/test_regress/t/t_driver_random.py new file mode 100755 index 000000000..83ab65bdd --- /dev/null +++ b/test_regress/t/t_driver_random.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import time + +test.scenarios('dist') + +if 'VERILATOR_TEST_RANDOM_FAILURE' not in os.environ: + print("Test is for harness checking only, setenv VERILATOR_TEST_RANDOM_FAILURE=1") + test.passes() +else: + # Randomly fail to test driver.py + t = time.time() + if t % 2: + test.error("random failure " + str(t)) + + test.passes() diff --git a/test_regress/t/t_dump_dfg.pl b/test_regress/t/t_dump_dfg.pl deleted file mode 100755 index 2164a894c..000000000 --- a/test_regress/t/t_dump_dfg.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Geza Lore. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -# For code coverage of graph dumping, so does not matter much what the input is -top_filename("t/t_bench_mux4k.v"); - -compile( - verilator_flags2 => ["--dump-dfg", "--dumpi-dfg 9"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_dump_dfg.py b/test_regress/t/t_dump_dfg.py new file mode 100755 index 000000000..6c72c0fc0 --- /dev/null +++ b/test_regress/t/t_dump_dfg.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +# For code coverage of graph dumping, so does not matter much what the input is +test.top_filename = "t/t_bench_mux4k.v" + +test.compile(verilator_flags2=["--dump-dfg", "--dumpi-dfg 9"]) + +test.passes() diff --git a/test_regress/t/t_dump_json.pl b/test_regress/t/t_dump_json.pl deleted file mode 100755 index 435b25067..000000000 --- a/test_regress/t/t_dump_json.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_dump.v"); - -lint( - v_flags => ["--dump-tree-json --no-json-edit-nums"], - ); - -files_identical("$Self->{obj_dir}/Vt_dump_json_001_cells.tree.json", $Self->{golden_filename}, 'logfile'); - -ok(1); - -1; diff --git a/test_regress/t/t_dump_json.py b/test_regress/t/t_dump_json.py new file mode 100755 index 000000000..d0cc13c96 --- /dev/null +++ b/test_regress/t/t_dump_json.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_dump.v" + +test.lint(v_flags=["--dump-tree-json --no-json-edit-nums"]) + +test.files_identical(test.obj_dir + "/Vt_dump_json_001_cells.tree.json", test.golden_filename, + 'logfile') + +test.passes() diff --git a/test_regress/t/t_dump_tree_dot.pl b/test_regress/t/t_dump_tree_dot.pl deleted file mode 100755 index 8caebed51..000000000 --- a/test_regress/t/t_dump_tree_dot.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_EXAMPLE.v"); - -lint( - v_flags => ["--lint-only --dump-tree-dot"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_dump_tree_dot.py b/test_regress/t/t_dump_tree_dot.py new file mode 100755 index 000000000..70a3a8d47 --- /dev/null +++ b/test_regress/t/t_dump_tree_dot.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_EXAMPLE.v" + +test.lint(v_flags=["--lint-only --dump-tree-dot"]) + +test.passes() diff --git a/test_regress/t/t_dynarray.pl b/test_regress/t/t_dynarray.pl deleted file mode 100755 index 56363dab6..000000000 --- a/test_regress/t/t_dynarray.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_dynarray.py b/test_regress/t/t_dynarray.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_dynarray.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dynarray_bad.pl b/test_regress/t/t_dynarray_bad.pl deleted file mode 100755 index 27159da5b..000000000 --- a/test_regress/t/t_dynarray_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dynarray_bad.py b/test_regress/t/t_dynarray_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_dynarray_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dynarray_bits.pl b/test_regress/t/t_dynarray_bits.pl deleted file mode 100755 index 27159da5b..000000000 --- a/test_regress/t/t_dynarray_bits.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_dynarray_bits.py b/test_regress/t/t_dynarray_bits.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_dynarray_bits.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_dynarray_concat.pl b/test_regress/t/t_dynarray_concat.pl deleted file mode 100755 index 3708008f8..000000000 --- a/test_regress/t/t_dynarray_concat.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_dynarray_concat.py b/test_regress/t/t_dynarray_concat.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_dynarray_concat.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dynarray_init.pl b/test_regress/t/t_dynarray_init.pl deleted file mode 100755 index 56363dab6..000000000 --- a/test_regress/t/t_dynarray_init.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_dynarray_init.py b/test_regress/t/t_dynarray_init.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_dynarray_init.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dynarray_method.pl b/test_regress/t/t_dynarray_method.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_dynarray_method.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_dynarray_method.py b/test_regress/t/t_dynarray_method.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_dynarray_method.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dynarray_multid.pl b/test_regress/t/t_dynarray_multid.pl deleted file mode 100755 index 56363dab6..000000000 --- a/test_regress/t/t_dynarray_multid.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_dynarray_multid.py b/test_regress/t/t_dynarray_multid.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_dynarray_multid.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dynarray_param.pl b/test_regress/t/t_dynarray_param.pl deleted file mode 100755 index 6e1338f8e..000000000 --- a/test_regress/t/t_dynarray_param.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_dynarray_param.py b/test_regress/t/t_dynarray_param.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_dynarray_param.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dynarray_unpacked.pl b/test_regress/t/t_dynarray_unpacked.pl deleted file mode 100755 index 56363dab6..000000000 --- a/test_regress/t/t_dynarray_unpacked.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_dynarray_unpacked.py b/test_regress/t/t_dynarray_unpacked.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_dynarray_unpacked.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_embed1.pl b/test_regress/t/t_embed1.pl deleted file mode 100755 index d9e2a538d..000000000 --- a/test_regress/t/t_embed1.pl +++ /dev/null @@ -1,54 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -use File::Spec; - -scenarios(simulator => 1); - -my $self = $Self; -my $child_dir = "$Self->{obj_dir}_child"; -mkdir $child_dir; - -# Compile the child -{ - my @cmdargs = $Self->compile_vlt_cmd - (vm_prefix => "$Self->{vm_prefix}_child", - top_filename => "$Self->{name}_child.v", - verilator_flags => ["-cc", "-Mdir", "${child_dir}", "--debug-check"], - # Can't use multi threading (like hier blocks), but needs to be thread safe - threads => 1, - ); - - run(logfile => "${child_dir}/vlt_compile.log", - cmd => \@cmdargs); - - run(logfile => "${child_dir}/vlt_gcc.log", - cmd => ["cd ${child_dir} && ", - $ENV{MAKE}, "-f" . getcwd() . "/Makefile_obj", - "CPPFLAGS_DRIVER=-D" . uc($self->{name}), - ($opt_verbose ? "CPPFLAGS_DRIVER2=-DTEST_VERBOSE=1" : ""), - "VM_PREFIX=$self->{vm_prefix}_child", - "V$self->{name}_child__ALL.a", # bypass default rule, make archive - ($param{make_flags}||""), - ]); -} - -# Compile the parent (might be with other than verilator) -compile( - v_flags2 => [File::Spec->rel2abs("${child_dir}/V$self->{name}_child__ALL.a"), - # TODO would be nice to have this in embedded archive - "t/t_embed1_c.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_embed1.py b/test_regress/t/t_embed1.py new file mode 100755 index 000000000..ff5997985 --- /dev/null +++ b/test_regress/t/t_embed1.py @@ -0,0 +1,47 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +child_dir = test.obj_dir + "_child" +test.mkdir_ok(child_dir) + +# Compile the child +while True: + cmdargs = test.compile_vlt_cmd( + vm_prefix=test.vm_prefix + "_child", + top_filename=test.name + "_child.v", + verilator_flags=["-cc", "-Mdir", child_dir, "--debug-check"], + # Can't use multi threading (like hier blocks), but needs to be thread safe + threads=1) # yapf:disable + + test.run(logfile=child_dir + "/vlt_compile.log", cmd=cmdargs) + + test.run( + logfile=child_dir + "/vlt_gcc.log", + cmd=[os.environ["MAKE"], "-C", child_dir, + "-f" + os.getcwd() + "/Makefile_obj", + "CPPFLAGS_DRIVER=-D"+test.name.upper(), + ("CPPFLAGS_DRIVER2=-DTEST_VERBOSE=1" if test.verbose else ""), + "VM_PREFIX=" + test.vm_prefix + "_child", + "V" + test.name + "_child__ALL.a" # bypass default rule, make archive + ]) # yapf:disable + + break + +# Compile the parent (might be with other than verilator) +test.compile(v_flags2=[os.path.abspath(child_dir + "/V" + test.name + "_child__ALL.a"), + # TODO would be nice to have this in embedded archive + "t/t_embed1_c.cpp"]) # yapf:disable + +test.execute() + +test.passes() diff --git a/test_regress/t/t_emit_accessors.pl b/test_regress/t/t_emit_accessors.pl deleted file mode 100755 index 533483c87..000000000 --- a/test_regress/t/t_emit_accessors.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - make_main => 0, - verilator_flags2 => [ - "--emit-accessors", - "--exe", - "$Self->{t_dir}/$Self->{name}.cpp" - ], -); - -ok(1); -1; diff --git a/test_regress/t/t_emit_accessors.py b/test_regress/t/t_emit_accessors.py new file mode 100755 index 000000000..a85bb33eb --- /dev/null +++ b/test_regress/t/t_emit_accessors.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(make_main=False, verilator_flags2=["--emit-accessors", "--exe", test.pli_filename]) + +test.passes() diff --git a/test_regress/t/t_emit_constw.pl b/test_regress/t/t_emit_constw.pl deleted file mode 100755 index 77826cbdb..000000000 --- a/test_regress/t/t_emit_constw.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--fno-expand'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_emit_constw.py b/test_regress/t/t_emit_constw.py new file mode 100755 index 000000000..32620aed3 --- /dev/null +++ b/test_regress/t/t_emit_constw.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--fno-expand']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_emit_memb_limit.pl b/test_regress/t/t_emit_memb_limit.pl deleted file mode 100755 index 513d9c0af..000000000 --- a/test_regress/t/t_emit_memb_limit.pl +++ /dev/null @@ -1,60 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -use IO::File; - -# Very slow on vltmt, and doesn't test much of value there, so disabled -scenarios(vlt => 1); - -sub gen { - my $filename = shift; - my $n = shift; - - my $fh = IO::File->new(">$filename"); - $fh->print("// Generated by t_emit_memb_limit.pl\n"); - $fh->print("module t (i, clk, o);\n"); - $fh->print(" input clk;\n"); - $fh->print(" input i;\n"); - $fh->print(" output logic o;\n"); - for (my $i = 0; $i < ($n + 1); ++$i) { - $fh->print(" logic r$i;\n"); - } - $fh->print(" always @ (posedge clk) begin\n"); - $fh->print(" r0 <= i;\n"); - for (my $i = 1; $i < $n; ++$i) { - $fh->print(" r" . ($i+1) . " <= r$i;\n"); - } - $fh->print(" o <= r$n;\n"); - $fh->print(' $write("*-* All Finished *-*\n");', "\n"); - $fh->print(' $finish;', "\n"); - $fh->print(" end\n"); - $fh->print("endmodule\n"); -} - -top_filename("$Self->{obj_dir}/t_emit_memb_limit.v"); - -# Current limit is 50, so want to test at least 50*50 cases -gen($Self->{top_filename}, 6000); - -compile( - verilator_flags2=>["-x-assign fast --x-initial fast", - "-Wno-UNOPTTHREADS", - # The slow V3Partition asserts are just too slow - # in this test. They're disabled just for performance - # reasons: - "--no-debug-partition"], - ); - -execute( - ); - -file_grep("$Self->{obj_dir}/$Self->{vm_prefix}___024root.h", qr/struct \{/); - -ok(1); -1; diff --git a/test_regress/t/t_emit_memb_limit.py b/test_regress/t/t_emit_memb_limit.py new file mode 100755 index 000000000..a6d6ef4d1 --- /dev/null +++ b/test_regress/t/t_emit_memb_limit.py @@ -0,0 +1,53 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +# Very slow on vltmt, and doesn't test much of value there, so disabled +test.scenarios('vlt') +test.top_filename = test.obj_dir + "/t_emit_memb_limit.v" + + +def gen(filename, n): + with open(filename, 'w', encoding="utf8") as fh: + fh.write("// Generated by t_emit_memb_limit.py\n") + fh.write("module t (i, clk, o);\n") + fh.write(" input clk;\n") + fh.write(" input i;\n") + fh.write(" output logic o;\n") + for i in range(0, n + 1): + fh.write(" logic r" + str(i) + ";\n") + fh.write(" always @ (posedge clk) begin\n") + fh.write(" r0 <= i;\n") + for i in range(1, n): + fh.write(" r" + str(i + 1) + " <= r" + str(i) + ";\n") + fh.write(" o <= r" + str(n) + ";\n") + fh.write(' $write("*-* All Finished *-*\\n");' + "\n") + fh.write(' $finish;' + "\n") + fh.write(" end\n") + fh.write("endmodule\n") + + +# Current limit is 50, so want to test at least 50*50 cases +gen(test.top_filename, 6000) + +test.compile(verilator_flags2=[ + "-x-assign fast --x-initial fast", + "-Wno-UNOPTTHREADS", + # The slow V3Partition asserts are just too slow + # in this test. They're disabled just for performance + # reasons: + "--no-debug-partition" +]) + +test.execute() + +test.file_grep(test.obj_dir + "/" + test.vm_prefix + "___024root.h", r'struct \{') + +test.passes() diff --git a/test_regress/t/t_enum.pl b/test_regress/t/t_enum.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_enum.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum.py b/test_regress/t/t_enum.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_enum.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_enum_bad_cell.pl b/test_regress/t/t_enum_bad_cell.pl deleted file mode 100755 index f1eef1686..000000000 --- a/test_regress/t/t_enum_bad_cell.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only -Wwarn-VARHIDDEN"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_bad_cell.py b/test_regress/t/t_enum_bad_cell.py new file mode 100755 index 000000000..2076da382 --- /dev/null +++ b/test_regress/t/t_enum_bad_cell.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only -Wwarn-VARHIDDEN"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_enum_bad_circdecl.pl b/test_regress/t/t_enum_bad_circdecl.pl deleted file mode 100755 index f1eef1686..000000000 --- a/test_regress/t/t_enum_bad_circdecl.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only -Wwarn-VARHIDDEN"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_bad_circdecl.py b/test_regress/t/t_enum_bad_circdecl.py new file mode 100755 index 000000000..2076da382 --- /dev/null +++ b/test_regress/t/t_enum_bad_circdecl.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only -Wwarn-VARHIDDEN"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_enum_bad_dup.pl b/test_regress/t/t_enum_bad_dup.pl deleted file mode 100755 index f1eef1686..000000000 --- a/test_regress/t/t_enum_bad_dup.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only -Wwarn-VARHIDDEN"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_bad_dup.py b/test_regress/t/t_enum_bad_dup.py new file mode 100755 index 000000000..2076da382 --- /dev/null +++ b/test_regress/t/t_enum_bad_dup.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only -Wwarn-VARHIDDEN"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_enum_bad_hide.pl b/test_regress/t/t_enum_bad_hide.pl deleted file mode 100755 index f1eef1686..000000000 --- a/test_regress/t/t_enum_bad_hide.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only -Wwarn-VARHIDDEN"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_bad_hide.py b/test_regress/t/t_enum_bad_hide.py new file mode 100755 index 000000000..2076da382 --- /dev/null +++ b/test_regress/t/t_enum_bad_hide.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only -Wwarn-VARHIDDEN"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_enum_bad_value.pl b/test_regress/t/t_enum_bad_value.pl deleted file mode 100755 index 0a723255a..000000000 --- a/test_regress/t/t_enum_bad_value.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--Wno-fatal"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_bad_value.py b/test_regress/t/t_enum_bad_value.py new file mode 100755 index 000000000..176cdf75d --- /dev/null +++ b/test_regress/t/t_enum_bad_value.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--Wno-fatal"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_enum_bad_wrap.pl b/test_regress/t/t_enum_bad_wrap.pl deleted file mode 100755 index f1eef1686..000000000 --- a/test_regress/t/t_enum_bad_wrap.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only -Wwarn-VARHIDDEN"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_bad_wrap.py b/test_regress/t/t_enum_bad_wrap.py new file mode 100755 index 000000000..2076da382 --- /dev/null +++ b/test_regress/t/t_enum_bad_wrap.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only -Wwarn-VARHIDDEN"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_enum_const_methods.pl b/test_regress/t/t_enum_const_methods.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_enum_const_methods.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_const_methods.py b/test_regress/t/t_enum_const_methods.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_enum_const_methods.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_enum_enumvalue_struct_bad.pl b/test_regress/t/t_enum_enumvalue_struct_bad.pl deleted file mode 100755 index 58225a99e..000000000 --- a/test_regress/t/t_enum_enumvalue_struct_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - expect_filename => $Self->{golden_filename}, - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_enumvalue_struct_bad.py b/test_regress/t/t_enum_enumvalue_struct_bad.py new file mode 100755 index 000000000..069c1f01e --- /dev/null +++ b/test_regress/t/t_enum_enumvalue_struct_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(expect_filename=test.golden_filename, fails=True) + +test.passes() diff --git a/test_regress/t/t_enum_func.pl b/test_regress/t/t_enum_func.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_enum_func.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_func.py b/test_regress/t/t_enum_func.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_enum_func.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_enum_huge_methods.pl b/test_regress/t/t_enum_huge_methods.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_enum_huge_methods.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_huge_methods.py b/test_regress/t/t_enum_huge_methods.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_enum_huge_methods.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_enum_huge_methods_bad.pl b/test_regress/t/t_enum_huge_methods_bad.pl deleted file mode 100755 index b5861b2ab..000000000 --- a/test_regress/t/t_enum_huge_methods_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_huge_methods_bad.py b/test_regress/t/t_enum_huge_methods_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_enum_huge_methods_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_enum_int.pl b/test_regress/t/t_enum_int.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_enum_int.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_int.py b/test_regress/t/t_enum_int.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_enum_int.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_enum_large_methods.pl b/test_regress/t/t_enum_large_methods.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_enum_large_methods.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_large_methods.py b/test_regress/t/t_enum_large_methods.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_enum_large_methods.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_enum_name2.pl b/test_regress/t/t_enum_name2.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_enum_name2.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_name2.py b/test_regress/t/t_enum_name2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_enum_name2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_enum_name3.pl b/test_regress/t/t_enum_name3.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_enum_name3.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_name3.py b/test_regress/t/t_enum_name3.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_enum_name3.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_enum_overlap_bad.pl b/test_regress/t/t_enum_overlap_bad.pl deleted file mode 100755 index a82cf66cb..000000000 --- a/test_regress/t/t_enum_overlap_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_overlap_bad.py b/test_regress/t/t_enum_overlap_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_enum_overlap_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_enum_param_class.pl b/test_regress/t/t_enum_param_class.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_enum_param_class.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_param_class.py b/test_regress/t/t_enum_param_class.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_enum_param_class.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_enum_public.pl b/test_regress/t/t_enum_public.pl deleted file mode 100755 index cb8cef498..000000000 --- a/test_regress/t/t_enum_public.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if ($Self->{vlt_all}) { - compile( - verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"], - make_top_shell => 0, - make_main => 0, - ); -} else { - compile( - ); -} - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_public.py b/test_regress/t/t_enum_public.py new file mode 100755 index 000000000..0916bd913 --- /dev/null +++ b/test_regress/t/t_enum_public.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if test.vlt_all: + test.compile(verilator_flags2=["--exe", test.pli_filename], + make_top_shell=False, + make_main=False) +else: + test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_enum_recurse_bad.pl b/test_regress/t/t_enum_recurse_bad.pl deleted file mode 100755 index 53e145105..000000000 --- a/test_regress/t/t_enum_recurse_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_recurse_bad.py b/test_regress/t/t_enum_recurse_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_enum_recurse_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_enum_recurse_bad2.pl b/test_regress/t/t_enum_recurse_bad2.pl deleted file mode 100755 index 53e145105..000000000 --- a/test_regress/t/t_enum_recurse_bad2.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_recurse_bad2.py b/test_regress/t/t_enum_recurse_bad2.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_enum_recurse_bad2.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_enum_size.pl b/test_regress/t/t_enum_size.pl deleted file mode 100755 index 56363dab6..000000000 --- a/test_regress/t/t_enum_size.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_size.py b/test_regress/t/t_enum_size.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_enum_size.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_enum_type_bad.pl b/test_regress/t/t_enum_type_bad.pl deleted file mode 100755 index a083f46f5..000000000 --- a/test_regress/t/t_enum_type_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_type_bad.py b/test_regress/t/t_enum_type_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_enum_type_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_enum_type_methods.pl b/test_regress/t/t_enum_type_methods.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_enum_type_methods.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_type_methods.py b/test_regress/t/t_enum_type_methods.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_enum_type_methods.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_enum_type_methods_bad.pl b/test_regress/t/t_enum_type_methods_bad.pl deleted file mode 100755 index 3c938d615..000000000 --- a/test_regress/t/t_enum_type_methods_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename} - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_type_methods_bad.py b/test_regress/t/t_enum_type_methods_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_enum_type_methods_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_enum_type_nomethod_bad.pl b/test_regress/t/t_enum_type_nomethod_bad.pl deleted file mode 100755 index 3c938d615..000000000 --- a/test_regress/t/t_enum_type_nomethod_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename} - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_type_nomethod_bad.py b/test_regress/t/t_enum_type_nomethod_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_enum_type_nomethod_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_enum_type_pins.pl b/test_regress/t/t_enum_type_pins.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_enum_type_pins.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_type_pins.py b/test_regress/t/t_enum_type_pins.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_enum_type_pins.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_enum_value_assign.pl b/test_regress/t/t_enum_value_assign.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_enum_value_assign.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_value_assign.py b/test_regress/t/t_enum_value_assign.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_enum_value_assign.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_enum_x_bad.pl b/test_regress/t/t_enum_x_bad.pl deleted file mode 100755 index a82cf66cb..000000000 --- a/test_regress/t/t_enum_x_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_enum_x_bad.py b/test_regress/t/t_enum_x_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_enum_x_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_enumeration.pl b/test_regress/t/t_enumeration.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_enumeration.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_enumeration.py b/test_regress/t/t_enumeration.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_enumeration.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_event.pl b/test_regress/t/t_event.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_event.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_event.py b/test_regress/t/t_event.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_event.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_event_control.pl b/test_regress/t/t_event_control.pl deleted file mode 100755 index 1047a4907..000000000 --- a/test_regress/t/t_event_control.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--no-timing'], - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_event_control.py b/test_regress/t/t_event_control.py new file mode 100755 index 000000000..330e93cb7 --- /dev/null +++ b/test_regress/t/t_event_control.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--no-timing'], + fails=test.vlt_all, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_event_control_assign.pl b/test_regress/t/t_event_control_assign.pl deleted file mode 100755 index 60aba0d46..000000000 --- a/test_regress/t/t_event_control_assign.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - make_main => 0, - # Multithreading would cause a warning on event assignments - threads => 1, - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_event_control_assign.py b/test_regress/t/t_event_control_assign.py new file mode 100755 index 000000000..9516162d0 --- /dev/null +++ b/test_regress/t/t_event_control_assign.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + verilator_flags2=["--exe --main --timing"], + make_main=False, + # Multithreading would cause a warning on event assignments + threads=1) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_event_control_expr.pl b/test_regress/t/t_event_control_expr.pl deleted file mode 100755 index bbc19ca7e..000000000 --- a/test_regress/t/t_event_control_expr.pl +++ /dev/null @@ -1,32 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - # do not test classes for multithreaded, as V3InstrCount doesn't handle MemberSel - verilator_flags2 => $Self->{vltmt} ? ['-DNO_CLASS'] : [], - ); - -execute( - ); - -for my $file (glob_all("$Self->{obj_dir}/$Self->{vm_prefix}*.cpp")) { - # Check that these simple expressions are not stored in temp variables - file_grep_not($file, qr/__Vtrigcurr__expression_.* = vlSelf->clk;/); - file_grep_not($file, qr/__Vtrigcurr__expression_.* = vlSelf->t__DOT__q.at\(0U\);/); - file_grep_not($file, qr/__Vtrigcurr__expression_.* = .*vlSelf->t__DOT____Vcellinp__u_array__t/); - file_grep_not($file, qr/__Vtrigcurr__expression_.* = .*vlSymsp->TOP__t__DOT__u_class.__PVT__obj/); - # The line below should only be generated if concats/replicates aren't converted to separate senitems - file_grep_not($file, qr/__Vtrigcurr__expression_.* = .*vlSelf->t__DOT__a/); -} - -ok(1); -1; diff --git a/test_regress/t/t_event_control_expr.py b/test_regress/t/t_event_control_expr.py new file mode 100755 index 000000000..ad96efae9 --- /dev/null +++ b/test_regress/t/t_event_control_expr.py @@ -0,0 +1,31 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + # do not test classes for multithreaded, as V3InstrCount doesn't handle MemberSel + verilator_flags2=(['-DNO_CLASS'] if test.vltmt else [])) + +test.execute() + +for filename in test.glob_some(test.obj_dir + "/" + test.vm_prefix + "*.cpp"): + # Check that these simple expressions are not stored in temp variables + test.file_grep_not(filename, r'__Vtrigcurr__expression_.* = vlSelf->clk;') + test.file_grep_not(filename, r'__Vtrigcurr__expression_.* = vlSelf->t__DOT__q.at\(0U\);') + test.file_grep_not(filename, + r'__Vtrigcurr__expression_.* = .*vlSelf->t__DOT____Vcellinp__u_array__t') + test.file_grep_not(filename, + r'__Vtrigcurr__expression_.* = .*vlSymsp->TOP__t__DOT__u_class.__PVT__obj') + # The line below should only be generated if concats/replicates aren't converted to separate senitems + test.file_grep_not(filename, r'__Vtrigcurr__expression_.* = .*vlSelf->t__DOT__a') + +test.passes() diff --git a/test_regress/t/t_event_control_expr_unsup.pl b/test_regress/t/t_event_control_expr_unsup.pl deleted file mode 100755 index 2f43f3687..000000000 --- a/test_regress/t/t_event_control_expr_unsup.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); # no vltmt, as AstMemberSel is unhandled in V3InstrCount - -top_filename("t_event_control_expr.v"); - -lint( - verilator_flags2 => ['-DUNSUP'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_event_control_expr_unsup.py b/test_regress/t/t_event_control_expr_unsup.py new file mode 100755 index 000000000..dbee9633e --- /dev/null +++ b/test_regress/t/t_event_control_expr_unsup.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') # no vltmt, as AstMemberSel is unhandled in V3InstrCount +test.top_filename = "t_event_control_expr.v" + +test.lint(verilator_flags2=['-DUNSUP'], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_event_control_pass.pl b/test_regress/t/t_event_control_pass.pl deleted file mode 100755 index 713bae4b5..000000000 --- a/test_regress/t/t_event_control_pass.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - threads => 1, - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_event_control_pass.py b/test_regress/t/t_event_control_pass.py new file mode 100755 index 000000000..483af3382 --- /dev/null +++ b/test_regress/t/t_event_control_pass.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"], threads=1) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_event_control_prev_name_collision.pl b/test_regress/t/t_event_control_prev_name_collision.pl deleted file mode 100755 index b56b0023f..000000000 --- a/test_regress/t/t_event_control_prev_name_collision.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["-fno-inline"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_event_control_prev_name_collision.py b/test_regress/t/t_event_control_prev_name_collision.py new file mode 100755 index 000000000..54de0aad4 --- /dev/null +++ b/test_regress/t/t_event_control_prev_name_collision.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_event_control_scope_var.pl b/test_regress/t/t_event_control_scope_var.pl deleted file mode 100755 index bccd16adf..000000000 --- a/test_regress/t/t_event_control_scope_var.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['-fno-inline', '-Wno-WIDTHTRUNC'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_event_control_scope_var.py b/test_regress/t/t_event_control_scope_var.py new file mode 100755 index 000000000..e1fb39066 --- /dev/null +++ b/test_regress/t/t_event_control_scope_var.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['-fno-inline', '-Wno-WIDTHTRUNC']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_event_control_star.pl b/test_regress/t/t_event_control_star.pl deleted file mode 100755 index 68471ddd3..000000000 --- a/test_regress/t/t_event_control_star.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--timing"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_event_control_star.py b/test_regress/t/t_event_control_star.py new file mode 100755 index 000000000..c8abf435a --- /dev/null +++ b/test_regress/t/t_event_control_star.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--timing"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_event_control_timing.pl b/test_regress/t/t_event_control_timing.pl deleted file mode 100755 index fbca1f660..000000000 --- a/test_regress/t/t_event_control_timing.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_event_control.v"); - -compile( - verilator_flags2 => ["--timing"], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_event_control_timing.py b/test_regress/t/t_event_control_timing.py new file mode 100755 index 000000000..dc5a3dbd2 --- /dev/null +++ b/test_regress/t/t_event_control_timing.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_event_control.v" + +test.compile(verilator_flags2=["--timing"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_event_copy.pl b/test_regress/t/t_event_copy.pl deleted file mode 100755 index cf0d3583f..000000000 --- a/test_regress/t/t_event_copy.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - threads => 1, - ); - -execute( - ) if !$Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_event_copy.py b/test_regress/t/t_event_copy.py new file mode 100755 index 000000000..a61e23c88 --- /dev/null +++ b/test_regress/t/t_event_copy.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(fails=test.vlt_all, expect_filename=test.golden_filename, threads=1) + +if not test.vlt_all: + test.execute() + +test.passes() diff --git a/test_regress/t/t_event_method_bad.pl b/test_regress/t/t_event_method_bad.pl deleted file mode 100755 index a82cf66cb..000000000 --- a/test_regress/t/t_event_method_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_event_method_bad.py b/test_regress/t/t_event_method_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_event_method_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_exit.pl b/test_regress/t/t_exit.pl deleted file mode 100755 index 56363dab6..000000000 --- a/test_regress/t/t_exit.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_exit.py b/test_regress/t/t_exit.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_exit.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_expect.pl b/test_regress/t/t_expect.pl deleted file mode 100755 index 7da2a2cb5..000000000 --- a/test_regress/t/t_expect.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - expect_filename => $Self->{golden_filename}, - verilator_flags2 => ['--assert --timing'], - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_expect.py b/test_regress/t/t_expect.py new file mode 100755 index 000000000..f0ed5d34b --- /dev/null +++ b/test_regress/t/t_expect.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert --timing'], fails=True) + +test.passes() diff --git a/test_regress/t/t_export_packed_struct.pl b/test_regress/t/t_export_packed_struct.pl deleted file mode 100755 index 5be036cb1..000000000 --- a/test_regress/t/t_export_packed_struct.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp -Wno-SYMRSVDWORD"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_export_packed_struct.py b/test_regress/t/t_export_packed_struct.py new file mode 100755 index 000000000..a08f8ed86 --- /dev/null +++ b/test_regress/t/t_export_packed_struct.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--exe", test.pli_filename, "-Wno-SYMRSVDWORD"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_export_packed_struct2.pl b/test_regress/t/t_export_packed_struct2.pl deleted file mode 100755 index dfebdabee..000000000 --- a/test_regress/t/t_export_packed_struct2.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_export_packed_struct2.py b/test_regress/t/t_export_packed_struct2.py new file mode 100755 index 000000000..9d1dcec8d --- /dev/null +++ b/test_regress/t/t_export_packed_struct2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_expr_incr_unsup.pl b/test_regress/t/t_expr_incr_unsup.pl deleted file mode 100755 index 35d749208..000000000 --- a/test_regress/t/t_expr_incr_unsup.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_expr_incr_unsup.py b/test_regress/t/t_expr_incr_unsup.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_expr_incr_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_extend.pl b/test_regress/t/t_extend.pl deleted file mode 100755 index 72847408e..000000000 --- a/test_regress/t/t_extend.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_extend.py b/test_regress/t/t_extend.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_extend.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_extend_class.pl b/test_regress/t/t_extend_class.pl deleted file mode 100755 index 97a44fa8f..000000000 --- a/test_regress/t/t_extend_class.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_flags => "CPPFLAGS_ADD=-I$Self->{t_dir}", - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_extend_class.py b/test_regress/t/t_extend_class.py new file mode 100755 index 000000000..6795aaac5 --- /dev/null +++ b/test_regress/t/t_extend_class.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_flags=["CPPFLAGS_ADD=-I" + test.t_dir]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_extract_static_const.pl b/test_regress/t/t_extract_static_const.pl deleted file mode 100755 index e871384b7..000000000 --- a/test_regress/t/t_extract_static_const.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, Prelim extracted value to ConstPool\s+(\d+)/, - 8); - file_grep($Self->{stats}, qr/ConstPool, Constants emitted\s+(\d+)/, - 1); -} - -ok(1); -1; diff --git a/test_regress/t/t_extract_static_const.py b/test_regress/t/t_extract_static_const.py new file mode 100755 index 000000000..c48009a42 --- /dev/null +++ b/test_regress/t/t_extract_static_const.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(verilator_flags2=["--stats"]) + +test.execute(expect_filename=test.golden_filename) + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, Prelim extracted value to ConstPool\s+(\d+)', 8) + test.file_grep(test.stats, r'ConstPool, Constants emitted\s+(\d+)', 1) + +test.passes() diff --git a/test_regress/t/t_extract_static_const_multimodule.pl b/test_regress/t/t_extract_static_const_multimodule.pl deleted file mode 100755 index e871384b7..000000000 --- a/test_regress/t/t_extract_static_const_multimodule.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, Prelim extracted value to ConstPool\s+(\d+)/, - 8); - file_grep($Self->{stats}, qr/ConstPool, Constants emitted\s+(\d+)/, - 1); -} - -ok(1); -1; diff --git a/test_regress/t/t_extract_static_const_multimodule.py b/test_regress/t/t_extract_static_const_multimodule.py new file mode 100755 index 000000000..c48009a42 --- /dev/null +++ b/test_regress/t/t_extract_static_const_multimodule.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(verilator_flags2=["--stats"]) + +test.execute(expect_filename=test.golden_filename) + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, Prelim extracted value to ConstPool\s+(\d+)', 8) + test.file_grep(test.stats, r'ConstPool, Constants emitted\s+(\d+)', 1) + +test.passes() diff --git a/test_regress/t/t_extract_static_const_no_merge.pl b/test_regress/t/t_extract_static_const_no_merge.pl deleted file mode 100755 index 19e77ecd7..000000000 --- a/test_regress/t/t_extract_static_const_no_merge.pl +++ /dev/null @@ -1,32 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_extract_static_const.v"); -golden_filename("t/t_extract_static_const.out"); - -compile( - verilator_flags2 => ["--stats", "--fno-merge-const-pool"], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, Prelim extracted value to ConstPool\s+(\d+)/, - 8); - file_grep($Self->{stats}, qr/ConstPool, Constants emitted\s+(\d+)/, - 2); -} - -ok(1); -1; diff --git a/test_regress/t/t_extract_static_const_no_merge.py b/test_regress/t/t_extract_static_const_no_merge.py new file mode 100755 index 000000000..8c3835a5d --- /dev/null +++ b/test_regress/t/t_extract_static_const_no_merge.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_extract_static_const.v" +test.golden_filename = "t/t_extract_static_const.out" + +test.compile(verilator_flags2=["--stats", "--fno-merge-const-pool"]) + +test.execute(expect_filename=test.golden_filename) + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, Prelim extracted value to ConstPool\s+(\d+)', 8) + test.file_grep(test.stats, r'ConstPool, Constants emitted\s+(\d+)', 2) + +test.passes() diff --git a/test_regress/t/t_f_bad.pl b/test_regress/t/t_f_bad.pl deleted file mode 100755 index bebe33c0c..000000000 --- a/test_regress/t/t_f_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only -f file_will_not_exist.vc"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_f_bad.py b/test_regress/t/t_f_bad.py new file mode 100755 index 000000000..9d256232c --- /dev/null +++ b/test_regress/t/t_f_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only -f file_will_not_exist.vc"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fallback_bad.pl b/test_regress/t/t_fallback_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_fallback_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_fallback_bad.py b/test_regress/t/t_fallback_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_fallback_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_final.pl b/test_regress/t/t_final.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_final.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_final.py b/test_regress/t/t_final.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_final.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_bboxsys.pl b/test_regress/t/t_flag_bboxsys.pl deleted file mode 100755 index e57ede6b7..000000000 --- a/test_regress/t/t_flag_bboxsys.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["--bbox-sys"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_bboxsys.py b/test_regress/t/t_flag_bboxsys.py new file mode 100755 index 000000000..9cdbf53a8 --- /dev/null +++ b/test_regress/t/t_flag_bboxsys.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--bbox-sys"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_binary.pl b/test_regress/t/t_flag_binary.pl deleted file mode 100755 index 1bb0e0252..000000000 --- a/test_regress/t/t_flag_binary.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_flag_main.v"); - -compile( - verilator_flags => [# Custom as don't want -cc - "-Mdir $Self->{obj_dir}", - "--debug-check", ], - verilator_flags2 => ['--binary'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_binary.py b/test_regress/t/t_flag_binary.py new file mode 100755 index 000000000..3aca74af7 --- /dev/null +++ b/test_regress/t/t_flag_binary.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_flag_main.v" + +test.compile( + verilator_flags=[ # Custom as don't want -cc + "-Mdir", test.obj_dir, "--debug-check" + ], + verilator_flags2=['--binary']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_binary_parallel.pl b/test_regress/t/t_flag_binary_parallel.pl deleted file mode 100755 index e324095cc..000000000 --- a/test_regress/t/t_flag_binary_parallel.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_flag_main.v"); - -compile( - verilator_flags => [# Custom as don't want -cc - "-Mdir $Self->{obj_dir}", - "--debug-check", ], - verilator_flags2 => ['--binary', '--output-split 1'], - make_main => 0, - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_binary_parallel.py b/test_regress/t/t_flag_binary_parallel.py new file mode 100755 index 000000000..3d881a0f1 --- /dev/null +++ b/test_regress/t/t_flag_binary_parallel.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_flag_main.v" + +test.compile( + verilator_flags=[ # Custom as don't want -cc + "-Mdir", test.obj_dir, "--debug-check" + ], + verilator_flags2=['--binary', '--output-split 1'], + make_main=False) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_build.pl b/test_regress/t/t_flag_build.pl deleted file mode 100755 index c08828ef9..000000000 --- a/test_regress/t/t_flag_build.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); -top_filename("t/t_flag_make_cmake.v"); - -compile( # Don't call cmake nor gmake from driver.pl - verilator_flags2 => ['--exe --cc --build -j 2', - '../' . $Self->{main_filename}, - '-MAKEFLAGS -p --trace'], - ); - -execute( - ); - -# If '-MAKEFLAGS --trace' is not properly processed, -# the log will not contain 'CMAKE_BUILD_TYPE:STRING=Debug'. -file_grep($Self->{obj_dir} . '/vlt_compile.log', /^Vt_flag_build_make.mk:\d+: update target \'(\w+)\' due to:/, 'Vt_flag_build'); - -ok(1); -1; diff --git a/test_regress/t/t_flag_build.py b/test_regress/t/t_flag_build.py new file mode 100755 index 000000000..e7603f123 --- /dev/null +++ b/test_regress/t/t_flag_build.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_flag_make_cmake.v" + +test.compile( # Don't call cmake nor gmake from driver.py + verilator_flags2=[ + '--exe --cc --build -j 2', '../' + test.main_filename, '-MAKEFLAGS -p --trace' + ]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_build_bad.pl b/test_regress/t/t_flag_build_bad.pl deleted file mode 100755 index a1ce4734f..000000000 --- a/test_regress/t/t_flag_build_bad.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["--build --make gmake"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -compile( - verilator_flags2 => ["--build --make cmake"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_build_bad.py b/test_regress/t/t_flag_build_bad.py new file mode 100755 index 000000000..6161025f1 --- /dev/null +++ b/test_regress/t/t_flag_build_bad.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--build --make gmake"], + fails=True, + expect_filename=test.golden_filename) + +test.compile(verilator_flags2=["--build --make cmake"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_build_bad2.pl b/test_regress/t/t_flag_build_bad2.pl deleted file mode 100755 index b61a1b234..000000000 --- a/test_regress/t/t_flag_build_bad2.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); -top_filename("t/t_flag_make_cmake.v"); - -compile( - # Need --no-print-directory so golden file doesn't compare directory names - verilator_flags2 => ["--build --MAKEFLAGS --no-print-directory" - ." --MAKEFLAGS illegal-flag-to-fail-make"], - fails => 1, - # Recursive make breaks the golden compare - #expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_build_bad2.py b/test_regress/t/t_flag_build_bad2.py new file mode 100755 index 000000000..c25924cf5 --- /dev/null +++ b/test_regress/t/t_flag_build_bad2.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_flag_make_cmake.v" + +test.compile( + # Need --no-print-directory so golden file doesn't compare directory names + verilator_flags2=[ + "--build --MAKEFLAGS --no-print-directory", " --MAKEFLAGS illegal-flag-to-fail-make" + ], + # Recursive make breaks the golden compare + #expect_filename = test.golden_filename + fails=True) + +test.passes() diff --git a/test_regress/t/t_flag_build_dep_bin.pl b/test_regress/t/t_flag_build_dep_bin.pl deleted file mode 100755 index 95eda3687..000000000 --- a/test_regress/t/t_flag_build_dep_bin.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - v_flags2 => ['--build-dep-bin', 'path_to_exe'], - ); - -file_grep("$Self->{obj_dir}/$Self->{vm_prefix}__ver.d", qr/path_to_exe/); - -ok(1); -1; diff --git a/test_regress/t/t_flag_build_dep_bin.py b/test_regress/t/t_flag_build_dep_bin.py new file mode 100755 index 000000000..fc4874e71 --- /dev/null +++ b/test_regress/t/t_flag_build_dep_bin.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(v_flags2=['--build-dep-bin', 'path_to_exe']) + +test.file_grep(test.obj_dir + "/" + test.vm_prefix + "__ver.d", r'path_to_exe') + +test.passes() diff --git a/test_regress/t/t_flag_build_jobs_and_j.pl b/test_regress/t/t_flag_build_jobs_and_j.pl deleted file mode 100755 index acab97246..000000000 --- a/test_regress/t/t_flag_build_jobs_and_j.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd.. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); -top_filename("t/t_flag_make_cmake.v"); - -compile( - verilator_flags2 => ['--exe --cc --build -j 10 --build-jobs 2 --stats', - '../' . $Self->{main_filename}], - ); - -execute( - ); - -file_grep($Self->{stats}, qr/Build jobs: 2/); - -ok(1); -1; diff --git a/test_regress/t/t_flag_build_jobs_and_j.py b/test_regress/t/t_flag_build_jobs_and_j.py new file mode 100755 index 000000000..bdc9b5ee9 --- /dev/null +++ b/test_regress/t/t_flag_build_jobs_and_j.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_flag_make_cmake.v" + +test.compile(verilator_flags2=[ + '--exe --cc --build -j 10 --build-jobs 2 --stats', '../' + test.main_filename +]) + +test.execute() + +test.file_grep(test.stats, r'Build jobs: 2') + +test.passes() diff --git a/test_regress/t/t_flag_build_jobs_bad.pl b/test_regress/t/t_flag_build_jobs_bad.pl deleted file mode 100755 index 8432e74c6..000000000 --- a/test_regress/t/t_flag_build_jobs_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_flag_werror.v"); - -lint( - fails => 1, - verilator_flags => [qw(--build-jobs -1 --build)], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_build_jobs_bad.py b/test_regress/t/t_flag_build_jobs_bad.py new file mode 100755 index 000000000..d944bef02 --- /dev/null +++ b/test_regress/t/t_flag_build_jobs_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_flag_werror.v" + +test.lint(fails=True, + verilator_flags=["--build-jobs -1 --build"], + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_comp_limit_parens.pl b/test_regress/t/t_flag_comp_limit_parens.pl deleted file mode 100755 index c387b0eba..000000000 --- a/test_regress/t/t_flag_comp_limit_parens.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["--comp-limit-parens 2"], - ); - -execute( - ); - -my @files = glob_all("$Self->{obj_dir}/$Self->{vm_prefix}___024root__DepSet*__Slow.cpp"); -file_grep_any(\@files, qr/Vdeeptemp/); - -ok(1); -1; diff --git a/test_regress/t/t_flag_comp_limit_parens.py b/test_regress/t/t_flag_comp_limit_parens.py new file mode 100755 index 000000000..fd7df3778 --- /dev/null +++ b/test_regress/t/t_flag_comp_limit_parens.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--comp-limit-parens 2"]) + +test.execute() + +files = test.glob_some(test.obj_dir + "/" + test.vm_prefix + "___024root__DepSet*__Slow.cpp") +test.file_grep_any(files, r'Vdeeptemp') + +test.passes() diff --git a/test_regress/t/t_flag_compiler_bad.pl b/test_regress/t/t_flag_compiler_bad.pl deleted file mode 100755 index 0bf39f727..000000000 --- a/test_regress/t/t_flag_compiler_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--compiler bad_one"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_compiler_bad.py b/test_regress/t/t_flag_compiler_bad.py new file mode 100755 index 000000000..bd99f7973 --- /dev/null +++ b/test_regress/t/t_flag_compiler_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--compiler bad_one"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_compiler_clang.pl b/test_regress/t/t_flag_compiler_clang.pl deleted file mode 100755 index ebd354fb0..000000000 --- a/test_regress/t/t_flag_compiler_clang.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_flag_compiler.v"); - -compile( - verilator_flags2 => ["--compiler clang"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_compiler_clang.py b/test_regress/t/t_flag_compiler_clang.py new file mode 100755 index 000000000..b3f8bb752 --- /dev/null +++ b/test_regress/t/t_flag_compiler_clang.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_flag_compiler.v" + +test.compile(verilator_flags2=["--compiler clang"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_compiler_gcc.pl b/test_regress/t/t_flag_compiler_gcc.pl deleted file mode 100755 index 5dbf948ff..000000000 --- a/test_regress/t/t_flag_compiler_gcc.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_flag_compiler.v"); - -compile( - verilator_flags2 => ["--compiler gcc"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_compiler_gcc.py b/test_regress/t/t_flag_compiler_gcc.py new file mode 100755 index 000000000..e868fd2f5 --- /dev/null +++ b/test_regress/t/t_flag_compiler_gcc.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_flag_compiler.v" + +test.compile(verilator_flags2=["--compiler gcc"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_compiler_msvc.pl b/test_regress/t/t_flag_compiler_msvc.pl deleted file mode 100755 index fcacbc555..000000000 --- a/test_regress/t/t_flag_compiler_msvc.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_flag_compiler.v"); - -compile( - verilator_flags2 => ["--compiler msvc"], # Bug requires msvc - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_compiler_msvc.py b/test_regress/t/t_flag_compiler_msvc.py new file mode 100755 index 000000000..33ce62dd2 --- /dev/null +++ b/test_regress/t/t_flag_compiler_msvc.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_flag_compiler.v" + +test.compile( + # Bug requires msvc + verilator_flags2=["--compiler msvc"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_context_bad.pl b/test_regress/t/t_flag_context_bad.pl deleted file mode 100755 index 054b31aac..000000000 --- a/test_regress/t/t_flag_context_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["-Wall -Wno-DECLFILENAME -Wno-context"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_context_bad.py b/test_regress/t/t_flag_context_bad.py new file mode 100755 index 000000000..b5c4b0655 --- /dev/null +++ b/test_regress/t/t_flag_context_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["-Wall -Wno-DECLFILENAME -Wno-context"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_csplit.pl b/test_regress/t/t_flag_csplit.pl deleted file mode 100755 index 88dea1af9..000000000 --- a/test_regress/t/t_flag_csplit.pl +++ /dev/null @@ -1,128 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -while (1) { - # This rule requires GNU make > 4.1 (or so, known broken in 3.81) - #%__Slow.o: %__Slow.cpp - # $(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_SLOW) -c -o $@ $< - if (make_version() < 4.1) { - skip("Test requires GNU Make version >= 4.1"); - last; - } - - compile( - v_flags2 => ["--trace --output-split 1 --output-split-cfuncs 1 --exe ../$Self->{main_filename}"], - verilator_make_gmake => 0, - ); - - # We don't use the standard test_regress rules, as want to test the rules - # properly build - run(logfile => "$Self->{obj_dir}/vlt_gcc.log", - tee => $self->{verbose}, - cmd=>[$ENV{MAKE}, - "-C " . $Self->{obj_dir}, - "-f $Self->{vm_prefix}.mk", - "-j 4", - "VM_PREFIX=$Self->{vm_prefix}", - "TEST_OBJ_DIR=$Self->{obj_dir}", - "CPPFLAGS_DRIVER=-D".uc($Self->{name}), - ($opt_verbose ? "CPPFLAGS_DRIVER2=-DTEST_VERBOSE=1" : ""), - "OPT_FAST=-O2", - "OPT_SLOW=-O0", - "OPT_GLOBAL=-Os", - ($param{make_flags}||""), - ]); - - execute( - ); - - # Splitting should set VM_PARALLEL_BUILDS to 1 by default - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}_classes.mk", qr/VM_PARALLEL_BUILDS\s*=\s*1/); - check_splits(); - check_no_all_file(); - check_gcc_flags("$Self->{obj_dir}/vlt_gcc.log"); - - ok(1); - last; -} -1; - -sub check_splits { - my $got1; - my $gotSyms1; - foreach my $file (glob("$Self->{obj_dir}/*.cpp")) { - if ($file =~ /Syms__1/) { - $gotSyms1 = 1; - } elsif ($file =~ /__1/) { - $got1 = 1; - } - check_cpp($file); - } - $got1 or error("No __1 split file found"); - $gotSyms1 or error("No Syms__1 split file found"); -} - -sub check_no_all_file { - foreach my $file (glob("$Self->{obj_dir}/*.cpp")) { - if ($file =~ qr/__ALL.cpp/) { - error("__ALL.cpp file found: $file"); - } - } -} - -sub check_cpp { - my $filename = shift; - my $size = -s $filename; - printf " File %6d %s\n", $size, $filename if $Self->{verbose}; - my $fh = IO::File->new("<$filename") or error("$! $filenme"); - my @funcs; - while (defined(my $line = $fh->getline)) { - if ($line =~ /^(void|IData)\s+(.*::.*){/) { - my $func = $2; - $func =~ s/\(.*$//; - print "\tFunc $func\n" if $Self->{verbose}; - if ($func !~ /::_eval_initial_loop$/ - && $func !~ /::__Vconfigure$/ - && $func !~ /::trace$/ - && $func !~ /::traceInit$/ - && $func !~ /::traceFull$/ - && $func !~ /::final$/ - && $func !~ /::prepareClone$/ - && $func !~ /::atClone$/ - ) { - push @funcs, $func; - } - } - } - if ($#funcs > 0) { - error("Split had multiple functions in $filename\n\t" . join("\n\t", @funcs)); - } -} - -sub check_gcc_flags { - my $filename = shift; - my $fh = IO::File->new("<$filename") or error("$! $filenme"); - while (defined(my $line = $fh->getline)) { - chomp $line; - print ":log: $line\n" if $Self->{verbose}; - if ($line =~ /$Self->{vm_prefix}\S*\.cpp/) { - my $filetype = ($line =~ /Slow|Syms/) ? "slow" : "fast"; - my $opt = ($line !~ /-O2/) ? "slow" : "fast"; - print "$filetype, $opt, $line\n" if $Self->{verbose}; - if ($filetype ne $opt) { - error("${filetype} file compiled as if was ${opt}: $line"); - } - } elsif ($line =~ /\.cpp/ and $line !~ /-Os/) { - error("library file not compiled with OPT_GLOBAL: $line"); - } - } -} diff --git a/test_regress/t/t_flag_csplit.py b/test_regress/t/t_flag_csplit.py new file mode 100755 index 000000000..d05df9e3c --- /dev/null +++ b/test_regress/t/t_flag_csplit.py @@ -0,0 +1,115 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + + +def check_splits(): + got1 = False + gotSyms1 = False + for filename in test.glob_some(test.obj_dir + "/*.cpp"): + if re.search(r'Syms__1', filename): + gotSyms1 = True + elif re.search(r'__1', filename): + got1 = True + if not got1: + test.error("No __1 split file found") + if not gotSyms1: + test.error("No Syms__1 split file found") + + +def check_no_all_file(): + for filename in test.glob_some(test.obj_dir + "/*.cpp"): + if re.search(r'__ALL.cpp', filename): + test.error("__ALL.cpp file found: " + filename) + + +def check_cpp(filename): + size = os.path.getsize(filename) + if test.verbose: + print(" File %6d %s\n" % (size, filename)) + funcs = [] + with open(filename, 'r', encoding="utf8") as fh: + for line in fh: + m = re.search(r'^(void|IData)\s+(.*::.*){', line) + if not m: + continue + func = m.group(2) + func = re.sub(r'\(.*$', '', func) + if test.verbose: + print("\tFunc " + func) + if (re.search(r'(::_eval_initial_loop$', func) or re.search(r'::__Vconfigure$', func) + or re.search(r'::trace$', func) or re.search(r'::traceInit$', func) + or re.search(r'::traceFull$', func) or re.search(r'::final$', func) + or re.search(r'::prepareClone$', func) or re.search(r'::atClone$', func)): + continue + funcs.append(func) + + if len(funcs) > 0: + test.error("Split had multiple functions in $filename\n\t" + "\n\t".join(funcs)) + + +def check_gcc_flags(filename): + with open(filename, 'r', encoding="utf8") as fh: + for line in fh: + line = line.rstrip() + if test.verbose: + print(":log: " + line) + if re.search(r'' + test.vm_prefix + r'\S*\.cpp', line): + filetype = "slow" if re.search(r'(Slow|Syms)', line) else "fast" + opt = "fast" if re.search(r'-O2', line) else "slow" + if test.verbose: + print(filetype + ", " + opt + ", " + line) + if filetype != opt: + test.error(filetype + " file compiled as if was " + opt + ": " + line) + elif re.search(r'.cpp', line) and not re.search(r'-Os', line): + test.error("library file not compiled with OPT_GLOBAL: " + line) + + +# This rule requires GNU make > 4.1 (or so, known broken in 3.81) +#%__Slow.o: %__Slow.cpp +# $(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_SLOW) -c -o $@ $< +if not test.make_version or float(test.make_version) < 4.1: + test.skip("Test requires GNU Make version >= 4.1") + +test.compile(v_flags2=["--trace", + "--output-split 1", + "--output-split-cfuncs 1", + "--exe", + "../" + test.main_filename], + verilator_make_gmake=False) # yapf:disable + +# We don't use the standard test_regress rules, as want to test the rules +# properly build +test.run(logfile=test.obj_dir + "/vlt_gcc.log", + tee=test.verbose, + cmd=[os.environ["MAKE"], + "-C " + test.obj_dir, + "-f "+test.vm_prefix+".mk", + "-j 4", + "VM_PREFIX="+test.vm_prefix, + "TEST_OBJ_DIR="+test.obj_dir, + "CPPFLAGS_DRIVER=-D"+test.name.upper(), + ("CPPFLAGS_DRIVER2=-DTEST_VERBOSE=1" if test.verbose else ""), + "OPT_FAST=-O2", + "OPT_SLOW=-O0", + "OPT_GLOBAL=-Os", + ]) # yapf:disable + +test.execute() + +# Splitting should set VM_PARALLEL_BUILDS to 1 by default +test.file_grep(test.obj_dir + "/" + test.vm_prefix + "_classes.mk", r'VM_PARALLEL_BUILDS\s*=\s*1') +check_splits() +check_no_all_file() +check_gcc_flags(test.obj_dir + "/vlt_gcc.log") + +test.passes() diff --git a/test_regress/t/t_flag_csplit_eval.pl b/test_regress/t/t_flag_csplit_eval.pl deleted file mode 100755 index 3b44c3193..000000000 --- a/test_regress/t/t_flag_csplit_eval.pl +++ /dev/null @@ -1,35 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -sub check_evals { - my $got = 0; - foreach my $file (glob("$Self->{obj_dir}/*.cpp")) { - my $fh = IO::File->new("<$file"); - local $/; undef $/; - my $wholefile = <$fh>; - - if ($wholefile =~ /__eval_nba__[0-9]+\(.*\)\s*{/) { - ++$got; - } - } - $got >= 2 or error("Too few _eval functions found: $got"); -} - -scenarios(vlt => 1); - -compile( - v_flags2 => ["--output-split 1 --output-split-cfuncs 20"], - verilator_make_gmake => 0, # Slow to compile, so skip it - ); - -check_evals(); - -ok(1); -1; diff --git a/test_regress/t/t_flag_csplit_eval.py b/test_regress/t/t_flag_csplit_eval.py new file mode 100755 index 000000000..55d94dcc2 --- /dev/null +++ b/test_regress/t/t_flag_csplit_eval.py @@ -0,0 +1,31 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + + +def check_evals(): + got = 0 + for filename in test.glob_some(test.obj_dir + "/*.cpp"): + wholefile = test.file_contents(filename) + if re.search(r'__eval_nba__[0-9]+\(.*\)\s*{', wholefile): + got += 1 + + if got < 3: + test.error("Too few _eval functions found: " + str(got)) + + +test.compile(v_flags2=["--output-split 1 --output-split-cfuncs 20"], + verilator_make_gmake=False) # Slow to compile, so skip it) + +check_evals() + +test.passes() diff --git a/test_regress/t/t_flag_csplit_off.pl b/test_regress/t/t_flag_csplit_off.pl deleted file mode 100755 index 50666dc0f..000000000 --- a/test_regress/t/t_flag_csplit_off.pl +++ /dev/null @@ -1,88 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_flag_csplit.v"); - -while (1) { - # This rule requires GNU make > 4.1 (or so, known broken in 3.81) - #%__Slow.o: %__Slow.cpp - # $(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_SLOW) -c -o $@ $< - if (make_version() < 4.1) { - skip("Test requires GNU Make version >= 4.1"); - last; - } - - compile( - v_flags2 => ["--trace --output-split 0 --exe ../$Self->{main_filename}"], - verilator_make_gmake => 0, - ); - - # We don't use the standard test_regress rules, as want to test the rules - # properly build - run(logfile => "$Self->{obj_dir}/vlt_gcc.log", - tee => $self->{verbose}, - cmd=>[$ENV{MAKE}, - "-C " . $Self->{obj_dir}, - "-f $Self->{vm_prefix}.mk", - "-j 4", - "VM_PREFIX=$Self->{vm_prefix}", - "TEST_OBJ_DIR=$Self->{obj_dir}", - "CPPFLAGS_DRIVER=-D".uc($Self->{name}), - ($opt_verbose ? "CPPFLAGS_DRIVER2=-DTEST_VERBOSE=1" : ""), - "OPT_FAST=-O2", - "OPT_SLOW=-O0", - ($param{make_flags}||""), - ]); - - execute( - ); - - # Never spliting, so should set VM_PARALLEL_BUILDS to 0 by default - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}_classes.mk", qr/VM_PARALLEL_BUILDS\s*=\s*0/); - check_no_splits(); - check_all_file(); - check_gcc_flags("$Self->{obj_dir}/vlt_gcc.log"); - - ok(1); - last; -} -1; - -sub check_no_splits { - foreach my $file (glob("$Self->{obj_dir}/*.cpp")) { - $file =~ s/__024root//; - if ($file =~ qr/__[1-9]/) { - error("Split file found: $file"); - } - } -} - -sub check_all_file { - foreach my $file (glob("$Self->{obj_dir}/*.cpp")) { - if ($file =~ qr/__ALL.cpp/) { - return; - } - } - error("__ALL.cpp file not found"); -} - -sub check_gcc_flags { - my $filename = shift; - my $fh = IO::File->new("<$filename") or error("$! $filenme"); - while (defined(my $line = $fh->getline)) { - chomp $line; - print ":log: $line\n" if $Self->{verbose}; - if ($line =~ /\.cpp/ && $line =~ qr/-O0/) { - error("File built as slow (should be in __ALL.cpp) : $line"); - } - } -} diff --git a/test_regress/t/t_flag_csplit_off.py b/test_regress/t/t_flag_csplit_off.py new file mode 100755 index 000000000..bdad4a618 --- /dev/null +++ b/test_regress/t/t_flag_csplit_off.py @@ -0,0 +1,68 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_flag_csplit.v" + + +def check_no_splits(): + for filename in test.glob_some(test.obj_dir + "/*.cpp"): + filename = re.sub(r'__024root', '', filename) + if re.search(r'__[1-9]', filename): + test.error("Split file found: " + filename) + + +def check_all_file(): + for filename in test.glob_some(test.obj_dir + "/*.cpp"): + if re.search(r'__ALL.cpp', filename): + return + + +def check_gcc_flags(filename): + with open(filename, 'r', encoding="utf8") as fh: + for line in fh: + line = line.rstrip() + if test.verbose: + print(":log: " + line) + if re.search(r'\.cpp', line) and re.search('-O0', line): + test.error("File built as slow (should be in __ALL.cpp) : " + line) + + +# This rule requires GNU make > 4.1 (or so, known broken in 3.81) +#%__Slow.o: %__Slow.cpp +# $(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_SLOW) -c -o $@ $< +if not test.make_version or float(test.make_version) < 4.1: + test.skip("Test requires GNU Make version >= 4.1") + +test.compile(v_flags2=["--trace --output-split 0 --exe ../" + test.main_filename], + verilator_make_gmake=False) + +# We don't use the standard test_regress rules, as want to test the rules +# properly build +test.run(logfile=test.obj_dir + "/vlt_gcc.log", + tee=test.verbose, + cmd=[ + os.environ["MAKE"], "-C " + test.obj_dir, "-f " + test.vm_prefix + ".mk", "-j 4", + "VM_PREFIX=" + test.vm_prefix, "TEST_OBJ_DIR=" + test.obj_dir, + "CPPFLAGS_DRIVER=-D" + test.name.upper(), + ("CPPFLAGS_DRIVER2=-DTEST_VERBOSE=1" if test.verbose else ""), "OPT_FAST=-O2", + "OPT_SLOW=-O0" + ]) + +test.execute() + +# Never spliting, so should set VM_PARALLEL_BUILDS to 0 by default +test.file_grep(test.obj_dir + "/" + test.vm_prefix + "_classes.mk", r'VM_PARALLEL_BUILDS\s*=\s*0') +check_no_splits() +check_all_file() +check_gcc_flags(test.obj_dir + "/vlt_gcc.log") + +test.passes() diff --git a/test_regress/t/t_flag_debug_noleak.pl b/test_regress/t/t_flag_debug_noleak.pl deleted file mode 100755 index aad25c780..000000000 --- a/test_regress/t/t_flag_debug_noleak.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - v_flags2 => ["--debug --no-debug-leak"], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_debug_noleak.py b/test_regress/t/t_flag_debug_noleak.py new file mode 100755 index 000000000..effa05d68 --- /dev/null +++ b/test_regress/t/t_flag_debug_noleak.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(v_flags2=["--debug --no-debug-leak"], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.passes() diff --git a/test_regress/t/t_flag_debugi9.pl b/test_regress/t/t_flag_debugi9.pl deleted file mode 100755 index 6db7a5c95..000000000 --- a/test_regress/t/t_flag_debugi9.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - v_flags2 => ["--debug --debugi 9"], - tee => 0, - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_debugi9.py b/test_regress/t/t_flag_debugi9.py new file mode 100755 index 000000000..c0da0071a --- /dev/null +++ b/test_regress/t/t_flag_debugi9.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(v_flags2=["--debug --debugi 9"], + tee=False, + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.passes() diff --git a/test_regress/t/t_flag_decoration.pl b/test_regress/t/t_flag_decoration.pl deleted file mode 100755 index 82d6aeddc..000000000 --- a/test_regress/t/t_flag_decoration.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_flag_decoration.v"); - -compile( - verilator_flags2 => ["--decoration"], - ); - -file_grep_not("$Self->{obj_dir}/V$Self->{name}.h", qr!\n// CONSTRUCTORS!); -file_grep("$Self->{obj_dir}/V$Self->{name}.h", qr!\n // CONSTRUCTORS!); -file_grep_not("$Self->{obj_dir}/V$Self->{name}.h", qr!/\*t/t_flag_decoration!); - -ok(1); -1; diff --git a/test_regress/t/t_flag_decoration.py b/test_regress/t/t_flag_decoration.py new file mode 100755 index 000000000..55807f346 --- /dev/null +++ b/test_regress/t/t_flag_decoration.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_flag_decoration.v" + +test.compile(verilator_flags2=["--decoration"]) + +test.file_grep_not(test.obj_dir + "/V" + test.name + ".h", r'\n// CONSTRUCTORS') +test.file_grep(test.obj_dir + "/V" + test.name + ".h", r'\n // CONSTRUCTORS') +test.file_grep_not(test.obj_dir + "/V" + test.name + ".h", r'/\*t/t_flag_decoration') + +test.passes() diff --git a/test_regress/t/t_flag_decoration_no.pl b/test_regress/t/t_flag_decoration_no.pl deleted file mode 100755 index 9f2f6a84b..000000000 --- a/test_regress/t/t_flag_decoration_no.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_flag_decoration.v"); - -compile( - verilator_flags2 => ["--no-decoration"], - ); - -file_grep("$Self->{obj_dir}/V$Self->{name}.h", qr!\n// CONSTRUCTORS!); -file_grep_not("$Self->{obj_dir}/V$Self->{name}.h", qr!\n // CONSTRUCTORS!); -file_grep_not("$Self->{obj_dir}/V$Self->{name}.h", qr!/\*t/t_flag_decoration!); - -ok(1); -1; diff --git a/test_regress/t/t_flag_decoration_no.py b/test_regress/t/t_flag_decoration_no.py new file mode 100755 index 000000000..af6c9f21b --- /dev/null +++ b/test_regress/t/t_flag_decoration_no.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_flag_decoration.v" + +test.compile(verilator_flags2=["--no-decoration"]) + +test.file_grep(test.obj_dir + "/V" + test.name + ".h", r'\n// CONSTRUCTORS') +test.file_grep_not(test.obj_dir + "/V" + test.name + ".h", r'\n // CONSTRUCTORS') +test.file_grep_not(test.obj_dir + "/V" + test.name + ".h", r'/\*t/t_flag_decoration') + +test.passes() diff --git a/test_regress/t/t_flag_decorations_bad.pl b/test_regress/t/t_flag_decorations_bad.pl deleted file mode 100755 index 238b5dfc0..000000000 --- a/test_regress/t/t_flag_decorations_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_flag_decoration.v"); - -lint( - verilator_flags2 => ["-decorations BAD"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_decorations_bad.py b/test_regress/t/t_flag_decorations_bad.py new file mode 100755 index 000000000..081a6cc01 --- /dev/null +++ b/test_regress/t/t_flag_decorations_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_flag_decoration.v" + +test.lint(verilator_flags2=["-decorations BAD"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_decorations_node.pl b/test_regress/t/t_flag_decorations_node.pl deleted file mode 100755 index e611e91ba..000000000 --- a/test_regress/t/t_flag_decorations_node.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_flag_decoration.v"); - -compile( - verilator_flags2 => ["--decorations node"], - ); - -file_grep_not("$Self->{obj_dir}/V$Self->{name}.h", qr!\n// CONSTRUCTORS!); -file_grep("$Self->{obj_dir}/V$Self->{name}.h", qr!\n // CONSTRUCTORS!); -file_grep("$Self->{obj_dir}/V$Self->{name}.h", qr!/\*t/t_flag_decoration!); - -ok(1); -1; diff --git a/test_regress/t/t_flag_decorations_node.py b/test_regress/t/t_flag_decorations_node.py new file mode 100755 index 000000000..a3f6e7efe --- /dev/null +++ b/test_regress/t/t_flag_decorations_node.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_flag_decoration.v" + +test.compile(verilator_flags2=["--decorations node"]) + +test.file_grep_not(test.obj_dir + "/V" + test.name + ".h", "\n// CONSTRUCTORS") +test.file_grep(test.obj_dir + "/V" + test.name + ".h", "\n // CONSTRUCTORS") +test.file_grep(test.obj_dir + "/V" + test.name + ".h", r'/\*t/t_flag_decoration') + +test.passes() diff --git a/test_regress/t/t_flag_define.pl b/test_regress/t/t_flag_define.pl deleted file mode 100755 index 9bba33ed4..000000000 --- a/test_regress/t/t_flag_define.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - v_flags2 => ["-f t/t_flag_define.vc -DCMD_DEF -DCMD_UNDEF -UCMD_UNDEF +define+CMD_DEF2"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_define.py b/test_regress/t/t_flag_define.py new file mode 100755 index 000000000..68eca8398 --- /dev/null +++ b/test_regress/t/t_flag_define.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(v_flags2=["-f t/t_flag_define.vc -DCMD_DEF -DCMD_UNDEF -UCMD_UNDEF +define+CMD_DEF2"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_deprecated_bad.pl b/test_regress/t/t_flag_deprecated_bad.pl deleted file mode 100755 index ba2b1d388..000000000 --- a/test_regress/t/t_flag_deprecated_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--trace-fst-thread --order-clock-delay"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_deprecated_bad.py b/test_regress/t/t_flag_deprecated_bad.py new file mode 100755 index 000000000..8cdf75fef --- /dev/null +++ b/test_regress/t/t_flag_deprecated_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--trace-fst-thread --order-clock-delay"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_errorlimit_bad.pl b/test_regress/t/t_flag_errorlimit_bad.pl deleted file mode 100755 index 6f645f2c0..000000000 --- a/test_regress/t/t_flag_errorlimit_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["-Wall -Wno-DECLFILENAME --error-limit 2"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_errorlimit_bad.py b/test_regress/t/t_flag_errorlimit_bad.py new file mode 100755 index 000000000..41ee4fce1 --- /dev/null +++ b/test_regress/t/t_flag_errorlimit_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["-Wall -Wno-DECLFILENAME --error-limit 2"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_expand_limit.pl b/test_regress/t/t_flag_expand_limit.pl deleted file mode 100755 index 4616430cb..000000000 --- a/test_regress/t/t_flag_expand_limit.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ['--expand-limit 1 --stats -fno-dfg'], - ); - -file_grep($Self->{stats}, qr/Optimizations, expand limited\s+(\d+)/, 3); - -ok(1); -1; diff --git a/test_regress/t/t_flag_expand_limit.py b/test_regress/t/t_flag_expand_limit.py new file mode 100755 index 000000000..c5e6b9338 --- /dev/null +++ b/test_regress/t/t_flag_expand_limit.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['--expand-limit 1 --stats -fno-dfg']) + +test.file_grep(test.stats, r'Optimizations, expand limited\s+(\d+)', 3) + +test.passes() diff --git a/test_regress/t/t_flag_f.pl b/test_regress/t/t_flag_f.pl deleted file mode 100755 index 124b2970f..000000000 --- a/test_regress/t/t_flag_f.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - v_flags2 => ["-f t/t_flag_f.vc"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_f.py b/test_regress/t/t_flag_f.py new file mode 100755 index 000000000..340eb7020 --- /dev/null +++ b/test_regress/t/t_flag_f.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(v_flags2=["-f t/t_flag_f.vc"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_f_bad_cmt.pl b/test_regress/t/t_flag_f_bad_cmt.pl deleted file mode 100755 index 24d8b0de5..000000000 --- a/test_regress/t/t_flag_f_bad_cmt.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - v_flags2 => ["-f t/t_flag_f_bad_cmt.vc"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_f_bad_cmt.py b/test_regress/t/t_flag_f_bad_cmt.py new file mode 100755 index 000000000..19aee7a96 --- /dev/null +++ b/test_regress/t/t_flag_f_bad_cmt.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(v_flags2=["-f t/t_flag_f_bad_cmt.vc"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_fi.pl b/test_regress/t/t_flag_fi.pl deleted file mode 100755 index 3e26a0793..000000000 --- a/test_regress/t/t_flag_fi.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ["-FI $Self->{t_dir}/t_flag_fi_h.h", - "--exe $Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_fi.py b/test_regress/t/t_flag_fi.py new file mode 100755 index 000000000..8bc5976ef --- /dev/null +++ b/test_regress/t/t_flag_fi.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(make_top_shell=False, + make_main=False, + v_flags2=["-FI", test.t_dir + "/t_flag_fi_h.h", "--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_future.pl b/test_regress/t/t_flag_future.pl deleted file mode 100755 index 5216b1dfd..000000000 --- a/test_regress/t/t_flag_future.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => [qw(--lint-only --future0 thefuture --future1 thefuturei --thefuture -thefuture +thefuture --thefuturei 1 -Wfuture-FUTURE1 -Wfuture-FUTURE2)], - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_future.py b/test_regress/t/t_flag_future.py new file mode 100755 index 000000000..68aa7e65a --- /dev/null +++ b/test_regress/t/t_flag_future.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=[ + "--lint-only --future0 thefuture --future1 thefuturei --thefuture -thefuture +thefuture --thefuturei 1 -Wfuture-FUTURE1 -Wfuture-FUTURE2" +]) + +test.passes() diff --git a/test_regress/t/t_flag_future_bad.pl b/test_regress/t/t_flag_future_bad.pl deleted file mode 100755 index 60a812ac4..000000000 --- a/test_regress/t/t_flag_future_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_flag_future.v"); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_flag_future_bad.py b/test_regress/t/t_flag_future_bad.py new file mode 100755 index 000000000..761b8b708 --- /dev/null +++ b/test_regress/t/t_flag_future_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_flag_future.v" + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_generate_key.pl b/test_regress/t/t_flag_generate_key.pl deleted file mode 100755 index 3458cfd36..000000000 --- a/test_regress/t/t_flag_generate_key.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - v_flags2 => ["--generate-key"], - expect => qr/VL-KEY/, - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_generate_key.py b/test_regress/t/t_flag_generate_key.py new file mode 100755 index 000000000..1f95c3a57 --- /dev/null +++ b/test_regress/t/t_flag_generate_key.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(v_flags2=["--generate-key"], + expect=r'VL-KEY', + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.passes() diff --git a/test_regress/t/t_flag_getenv.pl b/test_regress/t/t_flag_getenv.pl deleted file mode 100755 index 0c000760d..000000000 --- a/test_regress/t/t_flag_getenv.pl +++ /dev/null @@ -1,32 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -setenv('FOOBARTEST', "gotit"); - -run( - cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator --getenv FOOBARTEST"], - expect => 'gotit -', - logfile => "$Self->{obj_dir}/simx.log", - verilator_run => 1, - ); - -foreach my $var (qw(MAKE PERL PYTHON3 SYSTEMC SYSTEMC_ARCH SYSTEMC_LIBDIR VERILATOR_ROOT)) { - run( - cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator --getenv ${var}"], - logfile => "$Self->{obj_dir}/simx.log", - verilator_run => 1, - ); -} - -ok(1); -1; diff --git a/test_regress/t/t_flag_getenv.py b/test_regress/t/t_flag_getenv.py new file mode 100755 index 000000000..491390b59 --- /dev/null +++ b/test_regress/t/t_flag_getenv.py @@ -0,0 +1,28 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.setenv('FOOBARTEST', "gotit") + +test.run(cmd=[os.environ["VERILATOR_ROOT"] + "/bin/verilator --getenv FOOBARTEST"], + expect=r'gotit', + logfile=test.obj_dir + "/simx.log", + verilator_run=True) + +for var in [ + 'MAKE', 'PERL', 'PYTHON3', 'SYSTEMC', 'SYSTEMC_ARCH', 'SYSTEMC_LIBDIR', 'VERILATOR_ROOT' +]: + test.run(cmd=[os.environ["VERILATOR_ROOT"] + "/bin/verilator", "--getenv", var], + logfile=test.obj_dir + "/simx.log", + verilator_run=True) + +test.passes() diff --git a/test_regress/t/t_flag_help.pl b/test_regress/t/t_flag_help.pl deleted file mode 100755 index e7d501820..000000000 --- a/test_regress/t/t_flag_help.pl +++ /dev/null @@ -1,45 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -use File::Basename; - -scenarios(dist => 1); - -# See also t_flag_version.pl - -sub check { - my $interpreter = shift; - my $prog = shift; - - my $logfile = "$Self->{obj_dir}/t_help__" . basename($prog) . ".log"; - - run(fails => 0, - cmd => [$interpreter, $prog, "--help"], - logfile => $logfile, - tee => 0, - verilator_run => 1, - ); - - file_grep($logfile, qr/(DISTRIBUTION|usage:)/); -} - -check("perl", "$ENV{VERILATOR_ROOT}/bin/verilator"); -check("perl", "$ENV{VERILATOR_ROOT}/bin/verilator_coverage"); - -check("python3", "$ENV{VERILATOR_ROOT}/bin/verilator_ccache_report"); -check("python3", "$ENV{VERILATOR_ROOT}/bin/verilator_gantt"); -check("python3", "$ENV{VERILATOR_ROOT}/bin/verilator_profcfunc"); - -if (-x "$ENV{VERILATOR_ROOT}/bin/verilator_difftree") { - check("python3", "$ENV{VERILATOR_ROOT}/bin/verilator_difftree"); -} - -ok(1); -1; diff --git a/test_regress/t/t_flag_help.py b/test_regress/t/t_flag_help.py new file mode 100755 index 000000000..d9ec36e3c --- /dev/null +++ b/test_regress/t/t_flag_help.py @@ -0,0 +1,39 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +# See also t_flag_version.py + + +def check(interpreter, prog): + logfile = test.obj_dir + "/t_help__" + os.path.basename(prog) + ".log" + + test.run(fails=False, + cmd=[interpreter, prog, "--help"], + logfile=logfile, + tee=False, + verilator_run=True) + + test.file_grep(logfile, r'(DISTRIBUTION|usage:)') + + +check("perl", os.environ["VERILATOR_ROOT"] + "/bin/verilator") +check("perl", os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage") + +check("python3", os.environ["VERILATOR_ROOT"] + "/bin/verilator_ccache_report") +check("python3", os.environ["VERILATOR_ROOT"] + "/bin/verilator_gantt") +check("python3", os.environ["VERILATOR_ROOT"] + "/bin/verilator_profcfunc") + +if os.path.exists(os.environ["VERILATOR_ROOT"] + "/bin/verilator_difftree"): + check("python3", os.environ["VERILATOR_ROOT"] + "/bin/verilator_difftree") + +test.passes() diff --git a/test_regress/t/t_flag_help_valgrind.pl b/test_regress/t/t_flag_help_valgrind.pl deleted file mode 100755 index 47fa4e396..000000000 --- a/test_regress/t/t_flag_help_valgrind.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -run(fails => 0, - cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator", "--help", "--valgrind"], - tee => 0, - verilator_run => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_help_valgrind.py b/test_regress/t/t_flag_help_valgrind.py new file mode 100755 index 000000000..3969109d8 --- /dev/null +++ b/test_regress/t/t_flag_help_valgrind.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +test.run(fails=False, + cmd=[os.environ["VERILATOR_ROOT"] + "/bin/verilator", "--help", "--valgrind"], + tee=False, + verilator_run=True) + +test.passes() diff --git a/test_regress/t/t_flag_hier0_bad.pl b/test_regress/t/t_flag_hier0_bad.pl deleted file mode 100755 index fb589c623..000000000 --- a/test_regress/t/t_flag_hier0_bad.pl +++ /dev/null @@ -1,38 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); -top_filename("t/t_hier_block.v"); - -lint( - fails => 1, - verilator_flags2 => ['--hierarchical-block', - 'modName,mangledName,param0,"paramValue0",param0,"paramValue1",param1,2,param3', - '--hierarchical-block', - 'modName', - '--hierarchical-block', - 'mod0,mod1,\'"str\\\'', # end with backslash - '--hierarchical-block', - 'mod2,mod3,\'"str\\a\'', # unexpected 'a' after backslash - '--hierarchical-block', - 'mod4,mod5,\'"str"abc\',', # not end with " - '--hierarchical-block', - 'mod6,mod7,\'"str"\',', # end with , - '--hierarchical-block', - 'mod8,mod9,\'s"tr"\',', # unexpected " - '--hierarchical-block', - 'modA,modB,param,', # end with , - ], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_flag_hier0_bad.py b/test_regress/t/t_flag_hier0_bad.py new file mode 100755 index 000000000..9d9e638b4 --- /dev/null +++ b/test_regress/t/t_flag_hier0_bad.py @@ -0,0 +1,30 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_hier_block.v" + +test.lint( + fails=True, + verilator_flags2=[ + '--hierarchical-block', + 'modName,mangledName,param0,"paramValue0",param0,"paramValue1",param1,2,param3', + '--hierarchical-block', 'modName', + '--hierarchical-block', 'mod0,mod1,\'"str\\\'', # end with backslash + '--hierarchical-block', 'mod2,mod3,\'"str\\a\'', # unexpected 'a' after backslash + '--hierarchical-block', 'mod4,mod5,\'"str"abc\',', # not end with " + '--hierarchical-block', 'mod6,mod7,\'"str"\',', # end with , + '--hierarchical-block', 'mod8,mod9,\'s"tr"\',', # unexpected " + '--hierarchical-block', 'modA,modB,param,', # end with , + ], + expect_filename=test.golden_filename) # yapf:disable + +test.passes() diff --git a/test_regress/t/t_flag_hier1_bad.pl b/test_regress/t/t_flag_hier1_bad.pl deleted file mode 100755 index 8a3475533..000000000 --- a/test_regress/t/t_flag_hier1_bad.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); -top_filename("t/t_hier_block.v"); - -lint( - fails => 1, - verilator_flags2 => ['--hierarchical', - '--hierarchical-child 1', - 'modName', - ], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_flag_hier1_bad.py b/test_regress/t/t_flag_hier1_bad.py new file mode 100755 index 000000000..6c7b401a8 --- /dev/null +++ b/test_regress/t/t_flag_hier1_bad.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_hier_block.v" + +test.lint(fails=True, + verilator_flags2=[ + '--hierarchical', + '--hierarchical-child 1', + 'modName', + ], + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_i_empty.pl b/test_regress/t/t_flag_i_empty.pl deleted file mode 100755 index 8cee660a7..000000000 --- a/test_regress/t/t_flag_i_empty.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["-Wno-MODDUP -I t_flag_i_empty.v t_flag_i_empty.v"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_i_empty.py b/test_regress/t/t_flag_i_empty.py new file mode 100755 index 000000000..885a35916 --- /dev/null +++ b/test_regress/t/t_flag_i_empty.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["-Wno-MODDUP -I t_flag_i_empty.v t_flag_i_empty.v"]) + +test.passes() diff --git a/test_regress/t/t_flag_instr_count_dpi_bad.pl b/test_regress/t/t_flag_instr_count_dpi_bad.pl deleted file mode 100755 index ebc71f887..000000000 --- a/test_regress/t/t_flag_instr_count_dpi_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--instr-count-dpi -1"], - fails => 1, - expect => "%Error: --instr-count-dpi must be non-negative: -1" - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_instr_count_dpi_bad.py b/test_regress/t/t_flag_instr_count_dpi_bad.py new file mode 100755 index 000000000..12381c7b3 --- /dev/null +++ b/test_regress/t/t_flag_instr_count_dpi_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--instr-count-dpi -1"], + fails=True, + expect="%Error: --instr-count-dpi must be non-negative: -1") + +test.passes() diff --git a/test_regress/t/t_flag_invalid2_bad.pl b/test_regress/t/t_flag_invalid2_bad.pl deleted file mode 100755 index 7aae03f4b..000000000 --- a/test_regress/t/t_flag_invalid2_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - verilator_flags2 => ['+invalid-plus'], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_flag_invalid2_bad.py b/test_regress/t/t_flag_invalid2_bad.py new file mode 100755 index 000000000..a91c4f34f --- /dev/null +++ b/test_regress/t/t_flag_invalid2_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, verilator_flags2=['+invalid-plus'], expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_invalid_bad.pl b/test_regress/t/t_flag_invalid_bad.pl deleted file mode 100755 index ac8693b64..000000000 --- a/test_regress/t/t_flag_invalid_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - verilator_flags2 => ['--invalid-dash'], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_flag_invalid_bad.py b/test_regress/t/t_flag_invalid_bad.py new file mode 100755 index 000000000..139abb1ab --- /dev/null +++ b/test_regress/t/t_flag_invalid_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, verilator_flags2=['--invalid-dash'], expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_language.pl b/test_regress/t/t_flag_language.pl deleted file mode 100755 index e219288ea..000000000 --- a/test_regress/t/t_flag_language.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ['--language 1364-2001'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_language.py b/test_regress/t/t_flag_language.py new file mode 100755 index 000000000..8ce75c418 --- /dev/null +++ b/test_regress/t/t_flag_language.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['--language 1364-2001']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_language_bad.pl b/test_regress/t/t_flag_language_bad.pl deleted file mode 100755 index bfd78a9ab..000000000 --- a/test_regress/t/t_flag_language_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ['--language 1-2-3-4'], - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_language_bad.py b/test_regress/t/t_flag_language_bad.py new file mode 100755 index 000000000..fb255200c --- /dev/null +++ b/test_regress/t/t_flag_language_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=['--language 1-2-3-4'], fails=True) + +test.passes() diff --git a/test_regress/t/t_flag_ldflags.pl b/test_regress/t/t_flag_ldflags.pl deleted file mode 100755 index b1005c2c2..000000000 --- a/test_regress/t/t_flag_ldflags.pl +++ /dev/null @@ -1,49 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -run(cmd => ["cd $Self->{obj_dir}" - . " && $ENV{CXX} -c ../../t/t_flag_ldflags_a.cpp" - . " && ar -cr t_flag_ldflags_a.a t_flag_ldflags_a.o" - . " && ranlib t_flag_ldflags_a.a "], - check_finished => 0); -run(cmd => ["cd $Self->{obj_dir}" - . " && $ENV{CXX} -fPIC -c ../../t/t_flag_ldflags_so.cpp" - . " && $ENV{CXX} -shared -o t_flag_ldflags_so.so -lc t_flag_ldflags_so.o"], - check_finished => 0); - -compile( - # Pass multiple -D's so we check quoting works properly - v_flags2 => ["-CFLAGS '-DCFLAGS_FROM_CMDLINE -DCFLAGS2_FROM_CMDLINE' ", - "t/t_flag_ldflags_c.cpp", - "t_flag_ldflags_a.a", - "t_flag_ldflags_so.so",], - ); - - -# On OS X, LD_LIBRARY_PATH is ignored, so set rpath of the exe to find the .so -if ($^O eq "darwin") { - run(cmd => ["cd $Self->{obj_dir}" - . " && install_name_tool -add_rpath \@executable_path/." - . " $Self->{vm_prefix}"], - check_finished => 0); - run(cmd => ["cd $Self->{obj_dir}" - . " && install_name_tool -change t_flag_ldflags_so.so" - . " \@rpath/t_flag_ldflags_so.so $Self->{vm_prefix}"], - check_finished => 0); -} - -execute( - run_env => "LD_LIBRARY_PATH=$Self->{obj_dir}:$ENV{LD_LIBRARY_PATH}", - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_ldflags.py b/test_regress/t/t_flag_ldflags.py new file mode 100755 index 000000000..661f2b1af --- /dev/null +++ b/test_regress/t/t_flag_ldflags.py @@ -0,0 +1,58 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import sys + +test.scenarios('vlt') + +CXX = os.environ["CXX"] + +test.run( + cmd=[ + "cd " + test.obj_dir # + + " && " + CXX + " -c ../../t/t_flag_ldflags_a.cpp" # + + " && ar -cr t_flag_ldflags_a.a t_flag_ldflags_a.o" # + + " && ranlib t_flag_ldflags_a.a " + ], + check_finished=False) + +test.run( + cmd=[ + "cd " + test.obj_dir # + + " && " + CXX + " -fPIC -c ../../t/t_flag_ldflags_so.cpp" # + + " && " + CXX + " -shared -o t_flag_ldflags_so.so -lc t_flag_ldflags_so.o" + ], + check_finished=False) + +test.compile( + # Pass multiple -D's so we check quoting works properly + v_flags2=[ + "-CFLAGS '-DCFLAGS_FROM_CMDLINE -DCFLAGS2_FROM_CMDLINE' ", "t/t_flag_ldflags_c.cpp", + "t_flag_ldflags_a.a", "t_flag_ldflags_so.so" + ]) + +# On OS X, LD_LIBRARY_PATH is ignored, so set rpath of the exe to find the .so +if sys.platform == "darwin": + test.run(cmd=[ + "cd " + test.obj_dir + " && install_name_tool -add_rpath @executable_path/.", + test.vm_prefix + ], + check_finished=False) + + test.run(cmd=[ + "cd " + test.obj_dir + " && install_name_tool -change t_flag_ldflags_so.so" + + " @rpath/t_flag_ldflags_so.so", test.vm_prefix + ], + check_finished=False) + +test.execute(run_env="LD_LIBRARY_PATH=" + test.obj_dir + ":" + + test.getenv_def("LD_LIBRARY_PATH", "")) + +test.passes() diff --git a/test_regress/t/t_flag_lib.pl b/test_regress/t/t_flag_lib.pl deleted file mode 100755 index 594d31d55..000000000 --- a/test_regress/t/t_flag_lib.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - v_flags2 => ['-v', 't/t_flag_libinc.v'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_lib.py b/test_regress/t/t_flag_lib.py new file mode 100755 index 000000000..59e45bab9 --- /dev/null +++ b/test_regress/t/t_flag_lib.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(v_flags2=['-v', 't/t_flag_libinc.v']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_lib_dpi.pl b/test_regress/t/t_flag_lib_dpi.pl deleted file mode 100755 index e853caaa3..000000000 --- a/test_regress/t/t_flag_lib_dpi.pl +++ /dev/null @@ -1,35 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -run(logfile => "$Self->{obj_dir}/vlt_compile.log", - cmd => ["perl", - "$ENV{VERILATOR_ROOT}/bin/verilator", - "-cc", - "--build", - '--no-timing', - "-Mdir", - "$Self->{obj_dir}", - "t/t_flag_lib_dpi.v", - "$Self->{t_dir}/t_flag_lib_dpi.cpp", - "$Self->{t_dir}/t_flag_lib_dpi_main.cpp"], - verilator_run => 1, - ); - -run(logfile => "$Self->{obj_dir}/cxx_compile.log", - cmd => ["cd $Self->{obj_dir}" - . " && cp $Self->{t_dir}/t_flag_lib_dpi.mk t_flag_lib_dpi.mk" - . " && $ENV{MAKE} -f t_flag_lib_dpi.mk t_flag_lib_dpi_test" - . " && ./t_flag_lib_dpi_test"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_lib_dpi.py b/test_regress/t/t_flag_lib_dpi.py new file mode 100755 index 000000000..225f73eb6 --- /dev/null +++ b/test_regress/t/t_flag_lib_dpi.py @@ -0,0 +1,31 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.run(logfile=test.obj_dir + "/vlt_compile.log", + cmd=[ + "perl", os.environ["VERILATOR_ROOT"] + "/bin/verilator", "-cc", "--build", + '--no-timing', "-Mdir", test.obj_dir, "t/t_flag_lib_dpi.v", + test.t_dir + "/t_flag_lib_dpi.cpp", test.t_dir + "/t_flag_lib_dpi_main.cpp" + ], + verilator_run=True) + +test.run( + logfile=test.obj_dir + "/cxx_compile.log", + cmd=[ + "cd " + test.obj_dir # + + " && cp " + test.t_dir + "/t_flag_lib_dpi.mk t_flag_lib_dpi.mk" # + + " && " + os.environ["MAKE"] + " -f t_flag_lib_dpi.mk t_flag_lib_dpi_test" # + + " && ./t_flag_lib_dpi_test" + ]) + +test.passes() diff --git a/test_regress/t/t_flag_main.pl b/test_regress/t/t_flag_main.pl deleted file mode 100755 index 0bade1a41..000000000 --- a/test_regress/t/t_flag_main.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags => [# Custom as don't want -cc - "-Mdir $Self->{obj_dir}", - "--debug-check", ], - verilator_flags2 => ['--exe --build --main'], - # Check that code --main produces uses only most modern API features - make_flags => 'CPPFLAGS_ADD=-DVL_NO_LEGACY', - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_main.py b/test_regress/t/t_flag_main.py new file mode 100755 index 000000000..52df09333 --- /dev/null +++ b/test_regress/t/t_flag_main.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + verilator_flags=[ # Custom as don't want -cc + "-Mdir " + test.obj_dir, "--debug-check" + ], + verilator_flags2=['--exe --build --main'], + # Check that code --main produces uses only most modern API features + make_flags=['CPPFLAGS_ADD=-DVL_NO_LEGACY']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_main_sc_bad.pl b/test_regress/t/t_flag_main_sc_bad.pl deleted file mode 100755 index 75c182412..000000000 --- a/test_regress/t/t_flag_main_sc_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ['--exe --build --main --sc'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_main_sc_bad.py b/test_regress/t/t_flag_main_sc_bad.py new file mode 100755 index 000000000..08d370745 --- /dev/null +++ b/test_regress/t/t_flag_main_sc_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=['--exe --build --main --sc'], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_main_top_name.pl b/test_regress/t/t_flag_main_top_name.pl deleted file mode 100755 index 362cb1003..000000000 --- a/test_regress/t/t_flag_main_top_name.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Don Williamson and Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_flag_main_top_name.v"); - -compile( - verilator_flags => ["-Mdir $Self->{obj_dir}", "--exe", "--build", "--main"], - verilator_flags2 => ["--top-module top", "--main-top-name ALTOP"], - make_main => 0, - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_main_top_name.py b/test_regress/t/t_flag_main_top_name.py new file mode 100755 index 000000000..40d6b3d44 --- /dev/null +++ b/test_regress/t/t_flag_main_top_name.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_flag_main_top_name.v" + +test.compile(verilator_flags=["-Mdir " + test.obj_dir, "--exe", "--build", "--main"], + verilator_flags2=["--top-module top", "--main-top-name ALTOP"], + make_main=False) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_main_top_name_empty.pl b/test_regress/t/t_flag_main_top_name_empty.pl deleted file mode 100755 index 8ded10be3..000000000 --- a/test_regress/t/t_flag_main_top_name_empty.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Don Williamson and Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_flag_main_top_name.v"); - -compile( - verilator_flags => ["-Mdir $Self->{obj_dir}", "--exe", "--build", "--main"], - verilator_flags2 => ["--top-module top", "--main-top-name -", "-DMAIN_TOP_NAME_EMPTY"], - make_main => 0, - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_main_top_name_empty.py b/test_regress/t/t_flag_main_top_name_empty.py new file mode 100755 index 000000000..872d0f076 --- /dev/null +++ b/test_regress/t/t_flag_main_top_name_empty.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_flag_main_top_name.v" + +test.compile(verilator_flags=["-Mdir " + test.obj_dir, "--exe", "--build", "--main"], + verilator_flags2=["--top-module top", "--main-top-name -", "-DMAIN_TOP_NAME_EMPTY"], + make_main=False) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_make_bad.pl b/test_regress/t/t_flag_make_bad.pl deleted file mode 100755 index 1c6f23aec..000000000 --- a/test_regress/t/t_flag_make_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--make bad_one"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_make_bad.py b/test_regress/t/t_flag_make_bad.py new file mode 100755 index 000000000..39e7f80eb --- /dev/null +++ b/test_regress/t/t_flag_make_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--make bad_one"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_make_cmake.pl b/test_regress/t/t_flag_make_cmake.pl deleted file mode 100755 index e8a004057..000000000 --- a/test_regress/t/t_flag_make_cmake.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_make_gmake => 0, - verilator_make_cmake => 1, - ); - -if (!$Self->have_cmake) { - skip("cmake is not installed"); -} else { - my $cmakecache = $Self->{obj_dir} . "/CMakeCache.txt"; - if (! -e $cmakecache) { - error("$cmakecache does not exist.") - } - - execute( - ); -} -ok(1); -1; diff --git a/test_regress/t/t_flag_make_cmake.py b/test_regress/t/t_flag_make_cmake.py new file mode 100755 index 000000000..1802450e1 --- /dev/null +++ b/test_regress/t/t_flag_make_cmake.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_make_gmake=False, verilator_make_cmake=True) + +if not test.have_cmake: + test.skip("cmake is not installed") + +cmakecache = test.obj_dir + "/CMakeCache.txt" +if not os.path.exists(cmakecache): + test.error(cmakecache + " does not exist") + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_make_cmake_sc.pl b/test_regress/t/t_flag_make_cmake_sc.pl deleted file mode 100755 index f6efd265e..000000000 --- a/test_regress/t/t_flag_make_cmake_sc.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# This test tests CMake support for SystemC - -scenarios(simulator => 1); - -compile( - verilator_make_gmake => 0, - verilator_make_cmake => 1, - verilator_flags2 => ["-sc"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_make_cmake_sc.py b/test_regress/t/t_flag_make_cmake_sc.py new file mode 100755 index 000000000..b32ca9667 --- /dev/null +++ b/test_regress/t/t_flag_make_cmake_sc.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +# This test tests CMake support for SystemC + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_make_gmake=False, verilator_make_cmake=True, verilator_flags2=["-sc"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_make_gmake.pl b/test_regress/t/t_flag_make_gmake.pl deleted file mode 100755 index b25888d6e..000000000 --- a/test_regress/t/t_flag_make_gmake.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_flag_make_cmake.v"); - -compile( - verilator_flags2 => ['--make gmake'], - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_make_gmake.py b/test_regress/t/t_flag_make_gmake.py new file mode 100755 index 000000000..aa50772d8 --- /dev/null +++ b/test_regress/t/t_flag_make_gmake.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_flag_make_cmake.v" + +test.compile(verilator_flags2=['--make gmake']) + +test.passes() diff --git a/test_regress/t/t_flag_mmd.pl b/test_regress/t/t_flag_mmd.pl deleted file mode 100755 index be72328d3..000000000 --- a/test_regress/t/t_flag_mmd.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["-MMD -MP"], - ); - -file_grep("$Self->{obj_dir}/Vt_flag_mmd__ver.d", qr!t/t_flag_mmd.v!); - -ok(1); -1; diff --git a/test_regress/t/t_flag_mmd.py b/test_regress/t/t_flag_mmd.py new file mode 100755 index 000000000..4709521ae --- /dev/null +++ b/test_regress/t/t_flag_mmd.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["-MMD -MP"]) + +test.file_grep(test.obj_dir + "/Vt_flag_mmd__ver.d", r't/t_flag_mmd.v') + +test.passes() diff --git a/test_regress/t/t_flag_names.pl b/test_regress/t/t_flag_names.pl deleted file mode 100755 index 8471c8910..000000000 --- a/test_regress/t/t_flag_names.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["--mod-prefix modPrefix --top-module t --l2-name l2Name"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_names.py b/test_regress/t/t_flag_names.py new file mode 100755 index 000000000..f4807c1bc --- /dev/null +++ b/test_regress/t/t_flag_names.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--mod-prefix modPrefix --top-module t --l2-name l2Name"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_no_unlimited_stack.pl b/test_regress/t/t_flag_no_unlimited_stack.pl deleted file mode 100755 index ef1a415a2..000000000 --- a/test_regress/t/t_flag_no_unlimited_stack.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -# Just check whether the flag is recognized. -lint( - verilator_flags2 => ["--no-unlimited-stack"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_no_unlimited_stack.py b/test_regress/t/t_flag_no_unlimited_stack.py new file mode 100755 index 000000000..d414c3381 --- /dev/null +++ b/test_regress/t/t_flag_no_unlimited_stack.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +# Just check whether the flag is recognized. +test.lint(verilator_flags2=["--no-unlimited-stack"]) + +test.passes() diff --git a/test_regress/t/t_flag_nofile_bad.pl b/test_regress/t/t_flag_nofile_bad.pl deleted file mode 100755 index 88e6198ba..000000000 --- a/test_regress/t/t_flag_nofile_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -run(cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator --lint-only"], - fails => 1, - logfile => "$Self->{obj_dir}/sim.log", - expect_filename => $Self->{golden_filename}, - verilator_run => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_nofile_bad.py b/test_regress/t/t_flag_nofile_bad.py new file mode 100755 index 000000000..15e3547bb --- /dev/null +++ b/test_regress/t/t_flag_nofile_bad.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.run(cmd=[os.environ["VERILATOR_ROOT"] + "/bin/verilator --lint-only"], + fails=True, + logfile=test.obj_dir + "/sim.log", + expect_filename=test.golden_filename, + verilator_run=True) + +test.passes() diff --git a/test_regress/t/t_flag_nomod_bad.pl b/test_regress/t/t_flag_nomod_bad.pl deleted file mode 100755 index b5861b2ab..000000000 --- a/test_regress/t/t_flag_nomod_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_nomod_bad.py b/test_regress/t/t_flag_nomod_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_flag_nomod_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_noop_bad.pl b/test_regress/t/t_flag_noop_bad.pl deleted file mode 100755 index 7f1db4900..000000000 --- a/test_regress/t/t_flag_noop_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -run(cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator", - "t_flag_noop_bad.v"], - fails => 1, - logfile => "$Self->{obj_dir}/sim.log", - expect_filename => $Self->{golden_filename}, - verilator_run => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_noop_bad.py b/test_regress/t/t_flag_noop_bad.py new file mode 100755 index 000000000..8ac06d1a7 --- /dev/null +++ b/test_regress/t/t_flag_noop_bad.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.run(cmd=[os.environ["VERILATOR_ROOT"] + "/bin/verilator", "t_flag_noop_bad.v"], + fails=True, + logfile=test.obj_dir + "/sim.log", + expect_filename=test.golden_filename, + verilator_run=True) + +test.passes() diff --git a/test_regress/t/t_flag_only_bad.pl b/test_regress/t/t_flag_only_bad.pl deleted file mode 100755 index aa2276bc0..000000000 --- a/test_regress/t/t_flag_only_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); -top_filename("t/t_flag_main.v"); - -lint( - verilator_flags2 => ["--binary -E --dpi-hdr-only --lint-only --xml-only --json-only -Wall"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_only_bad.py b/test_regress/t/t_flag_only_bad.py new file mode 100755 index 000000000..be2835493 --- /dev/null +++ b/test_regress/t/t_flag_only_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_flag_main.v" + +test.lint(verilator_flags2=["--binary -E --dpi-hdr-only --lint-only --xml-only --json-only -Wall"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_only_bad2.pl b/test_regress/t/t_flag_only_bad2.pl deleted file mode 100755 index 0d33fbf71..000000000 --- a/test_regress/t/t_flag_only_bad2.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); -top_filename("t/t_flag_main.v"); - -lint( - verilator_flags2 => ["--build -E -Wno-fatal --dpi-hdr-only --lint-only --xml-only --json-only"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_only_bad2.py b/test_regress/t/t_flag_only_bad2.py new file mode 100755 index 000000000..10fa26356 --- /dev/null +++ b/test_regress/t/t_flag_only_bad2.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_flag_main.v" + +test.lint( + verilator_flags2=["--build -E -Wno-fatal --dpi-hdr-only --lint-only --xml-only --json-only"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_only_bad3.pl b/test_regress/t/t_flag_only_bad3.pl deleted file mode 100755 index d01fc2b88..000000000 --- a/test_regress/t/t_flag_only_bad3.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); -top_filename("t/t_flag_main.v"); - -lint( - verilator_flags2 => ["-Wall --lint-only -Wno-fatal --dpi-hdr-only --xml-only --json-only"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_only_bad3.py b/test_regress/t/t_flag_only_bad3.py new file mode 100755 index 000000000..7bd76ebe4 --- /dev/null +++ b/test_regress/t/t_flag_only_bad3.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_flag_main.v" + +test.lint(verilator_flags2=["-Wall --lint-only -Wno-fatal --dpi-hdr-only --xml-only --json-only"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_parameter.pl b/test_regress/t/t_flag_parameter.pl deleted file mode 100755 index 59845ac54..000000000 --- a/test_regress/t/t_flag_parameter.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - # It is not possible to put them into the options file - v_flags2 => ['-f t/t_flag_parameter.vc'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_parameter.py b/test_regress/t/t_flag_parameter.py new file mode 100755 index 000000000..a0976af1a --- /dev/null +++ b/test_regress/t/t_flag_parameter.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile( + # It is not possible to put them into the options file + v_flags2=['-f t/t_flag_parameter.vc']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_parameter_bad.pl b/test_regress/t/t_flag_parameter_bad.pl deleted file mode 100755 index ec91b7170..000000000 --- a/test_regress/t/t_flag_parameter_bad.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_flag_parameter.v"); - -lint( - fails => 1, - # It is not possible to put them into the options file - v_flags2 => ['-GPARAM_THAT_DOES_NON_EXIST=1'], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_parameter_bad.py b/test_regress/t/t_flag_parameter_bad.py new file mode 100755 index 000000000..79a16fac7 --- /dev/null +++ b/test_regress/t/t_flag_parameter_bad.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_flag_parameter.v" + +test.lint( + fails=True, + # It is not possible to put them into the options file + v_flags2=['-GPARAM_THAT_DOES_NON_EXIST=1'], + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_parameter_hier.pl b/test_regress/t/t_flag_parameter_hier.pl deleted file mode 100755 index 422014f84..000000000 --- a/test_regress/t/t_flag_parameter_hier.pl +++ /dev/null @@ -1,32 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - # For Verilator, all PARAMs at all levels are overridden - # Error if parameter not found - #verilator_flags2 => ['-GPARAM=10 -Gtop.t.x.HIER=20'], # HIER would error - verilator_flags2 => ['-GPARAM=10'], - # For NC, always implies a hierarchy, only HIER will be set - # Warns if sets nothing - nc_flags2 => ['+defparam+PARAM=10 +defparam+top.t.x.HIER=20'], - # For VCS, all PARAMs at all levels are overridden. Hierarchy not allowed. - # Informational on all overrides - vcs_flags2 => ['-pvalue+PARAM=10 -px.HIER=20'], - # For icarus -P without hierarchy does nothing, only can ref into top - iv_flags2 => ['-PPARAM=10', '-Ptop.HIER=30', '-Ptop.t.x.HIER=20'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_parameter_hier.py b/test_regress/t/t_flag_parameter_hier.py new file mode 100755 index 000000000..b795ba12c --- /dev/null +++ b/test_regress/t/t_flag_parameter_hier.py @@ -0,0 +1,30 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + # For Verilator, all PARAMs at all levels are overridden + # Error if parameter not found + #verilator_flags2 = ['-GPARAM=10 -Gtop.t.x.HIER=20'], # HIER would error + verilator_flags2=['-GPARAM=10'], + # For NC, always implies a hierarchy, only HIER will be set + # Warns if sets nothing + nc_flags2=['+defparam+PARAM=10 +defparam+top.t.x.HIER=20'], + # For VCS, all PARAMs at all levels are overridden. Hierarchy not allowed. + # Informational on all overrides + vcs_flags2=['-pvalue+PARAM=10 -px.HIER=20'], + # For icarus -P without hierarchy does nothing, only can ref into top + iv_flags2=['-PPARAM=10', '-Ptop.HIER=30', '-Ptop.t.x.HIER=20']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_parameter_pkg.pl b/test_regress/t/t_flag_parameter_pkg.pl deleted file mode 100755 index da120a1e8..000000000 --- a/test_regress/t/t_flag_parameter_pkg.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['-GPARAM_A=1'], - ms_flags2 => ['-GPARAM_A=1'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_parameter_pkg.py b/test_regress/t/t_flag_parameter_pkg.py new file mode 100755 index 000000000..84bc7ac5a --- /dev/null +++ b/test_regress/t/t_flag_parameter_pkg.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['-GPARAM_A=1'], ms_flags2=['-GPARAM_A=1']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_prefix.pl b/test_regress/t/t_flag_prefix.pl deleted file mode 100755 index 66abadf80..000000000 --- a/test_regress/t/t_flag_prefix.pl +++ /dev/null @@ -1,47 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Geza Lore. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["--prefix t_flag_prefix", # should be overridden - "--prefix Vprefix", - "--exe", "--main", "--stats", "--build"], - verilator_make_cmake => 0, - verilator_make_gmake => 0, - ); - -execute( - executable => "$Self->{obj_dir}/Vprefix", - ); - -sub check_files { - foreach my $path (glob("$Self->{obj_dir}/*")) { - my $filename = substr $path, ((length $Self->{obj_dir}) + 1); - next if ($filename =~ /^.*\.log$/); - if ($filename =~ /t_flag_prefix/) { - error("bad filename $filename"); - next; - } - next if ($filename =~ /^(.*\.(o|a)|Vprefix)$/); - my $fh = IO::File->new("<$path") or error("$! $filenme"); - while (defined(my $line = $fh->getline)) { - $line =~ s/--prefix V?t_flag_prefix//g; - $line =~ s/obj_vlt\/t_flag_prefix//g; - $line =~ s/t\/t_flag_prefix\.v//g; - error("bad line in $filename: $line") if $line =~ /t_flag_prefix/; - } - } -} - -check_files(); - -ok(1); -1; diff --git a/test_regress/t/t_flag_prefix.py b/test_regress/t/t_flag_prefix.py new file mode 100755 index 000000000..3e0ee470a --- /dev/null +++ b/test_regress/t/t_flag_prefix.py @@ -0,0 +1,50 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile( + verilator_flags2=[ + "--prefix t_flag_prefix", # should be overridden + "--prefix Vprefix", + "--exe", + "--main", + "--stats", + "--build" + ], + verilator_make_cmake=False, + verilator_make_gmake=False) + +test.execute(executable=test.obj_dir + "/Vprefix") + + +def check_files(): + for path in test.glob_some(test.obj_dir + "/*"): + filename = path[(len(test.obj_dir) + 1):] + if re.search(r'\.log$', filename): + continue + if re.search(r't_flag_prefix', filename): + test.error("bad filename '" + filename + "'") + continue + if re.search(r'^(.*\.(o|a)|Vprefix)$', filename): + continue + with open(path, 'r', encoding="utf8") as fh: + for line in fh: + line = re.sub(r'--prefix V?t_flag_prefix', '', line) + line = re.sub(r'obj_vlt\/t_flag_prefix', '', line) + line = re.sub(r't\/t_flag_prefix\.v', '', line) + if re.search(r't_flag_prefix', line): + test.error(filename + ": bad line: " + line) + + +check_files() + +test.passes() diff --git a/test_regress/t/t_flag_quiet_exit.pl b/test_regress/t/t_flag_quiet_exit.pl deleted file mode 100755 index cb3d6bedd..000000000 --- a/test_regress/t/t_flag_quiet_exit.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Todd Strader. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_file_does_not_exist.v"); - -# Tests for the error message and then the absence of the -# "Command Failed" line -compile( - v_flags2 => ["--quiet-exit"], - fails => 1, - ); - -file_grep_not("$Self->{obj_dir}/vlt_compile.log", qr/Exiting due to/); -file_grep_not("$Self->{obj_dir}/vlt_compile.log", qr/Command Failed/); - -ok(1); -1; diff --git a/test_regress/t/t_flag_quiet_exit.py b/test_regress/t/t_flag_quiet_exit.py new file mode 100755 index 000000000..ffe942afc --- /dev/null +++ b/test_regress/t/t_flag_quiet_exit.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_file_does_not_exist.v" + +# Tests for the error message and then the absence of the +# "Command Failed" line +test.compile(v_flags2=["--quiet-exit"], fails=True) + +test.file_grep_not(test.obj_dir + "/vlt_compile.log", r'Exiting due to') +test.file_grep_not(test.obj_dir + "/vlt_compile.log", r'Command Failed') + +test.passes() diff --git a/test_regress/t/t_flag_quiet_stats.pl b/test_regress/t/t_flag_quiet_stats.pl deleted file mode 100755 index 81590297b..000000000 --- a/test_regress/t/t_flag_quiet_stats.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ['--quiet-stats'], - verilator_make_gcc => 0, - logfile => $Self->{run_log_filename}, - ); - -file_grep_not($Self->{obj_dir}.'/vlt_compile.log', qr/V e r i l a t/); - -ok(1); -1; diff --git a/test_regress/t/t_flag_quiet_stats.py b/test_regress/t/t_flag_quiet_stats.py new file mode 100755 index 000000000..a229ed30f --- /dev/null +++ b/test_regress/t/t_flag_quiet_stats.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['--quiet-stats'], + verilator_make_gcc=False, + logfile=test.run_log_filename) + +test.file_grep_not(test.obj_dir + '/vlt_compile.log', r'V e r i l a t') + +test.passes() diff --git a/test_regress/t/t_flag_quiet_stats2.pl b/test_regress/t/t_flag_quiet_stats2.pl deleted file mode 100755 index 1f62cf14a..000000000 --- a/test_regress/t/t_flag_quiet_stats2.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_flag_quiet_stats.v"); - -compile( - verilator_flags2 => ['--quiet'], - verilator_make_gcc => 0, - logfile => $Self->{run_log_filename}, - ); - -file_grep_not($Self->{obj_dir}.'/vlt_compile.log', qr/V e r i l a t/); - -ok(1); -1; diff --git a/test_regress/t/t_flag_quiet_stats2.py b/test_regress/t/t_flag_quiet_stats2.py new file mode 100755 index 000000000..1b3b95356 --- /dev/null +++ b/test_regress/t/t_flag_quiet_stats2.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_flag_quiet_stats.v" + +test.compile(verilator_flags2=['--quiet'], verilator_make_gcc=False, logfile=test.run_log_filename) + +test.file_grep_not(test.obj_dir + '/vlt_compile.log', r'V e r i l a t') + +test.passes() diff --git a/test_regress/t/t_flag_quiet_stats3.pl b/test_regress/t/t_flag_quiet_stats3.pl deleted file mode 100755 index 514e31bf5..000000000 --- a/test_regress/t/t_flag_quiet_stats3.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_flag_quiet_stats.v"); - -compile( - verilator_flags2 => ['--quiet --no-quiet-stats'], - verilator_make_gcc => 0, - logfile => $Self->{run_log_filename}, - ); - -file_grep($Self->{obj_dir}.'/vlt_compile.log', qr/V e r i l a t/); - -ok(1); -1; diff --git a/test_regress/t/t_flag_quiet_stats3.py b/test_regress/t/t_flag_quiet_stats3.py new file mode 100755 index 000000000..43bdfb9fb --- /dev/null +++ b/test_regress/t/t_flag_quiet_stats3.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_flag_quiet_stats.v" + +test.compile(verilator_flags2=['--quiet --no-quiet-stats'], + verilator_make_gcc=False, + logfile=test.run_log_filename) + +test.file_grep(test.obj_dir + '/vlt_compile.log', r'V e r i l a t') + +test.passes() diff --git a/test_regress/t/t_flag_relinc.pl b/test_regress/t/t_flag_relinc.pl deleted file mode 100755 index 38fc1bf91..000000000 --- a/test_regress/t/t_flag_relinc.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - v_flags2 => ["--relative-includes", - "--lint-only $Self->{t_dir}/t_flag_relinc_dir/chip/t_flag_relinc_sub.v"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_relinc.py b/test_regress/t/t_flag_relinc.py new file mode 100755 index 000000000..af6f9fa75 --- /dev/null +++ b/test_regress/t/t_flag_relinc.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(v_flags2=[ + "--relative-includes", "--lint-only", test.t_dir + + "/t_flag_relinc_dir/chip/t_flag_relinc_sub.v" +]) + +test.passes() diff --git a/test_regress/t/t_flag_runtime_debug.pl b/test_regress/t/t_flag_runtime_debug.pl deleted file mode 100755 index 4b3380d68..000000000 --- a/test_regress/t/t_flag_runtime_debug.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_flag_main.v"); - -compile( - verilator_flags2 => ['--binary --runtime-debug'], - ); - -execute( - aslr_off => 1, # Some GCC versions hit an address-sanitizer bug otherwise - ); - -file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.mk", qr/VL_DEBUG=1/); - -ok(1); -1; diff --git a/test_regress/t/t_flag_runtime_debug.py b/test_regress/t/t_flag_runtime_debug.py new file mode 100755 index 000000000..aabbbc531 --- /dev/null +++ b/test_regress/t/t_flag_runtime_debug.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_flag_main.v" + +test.compile(verilator_flags2=['--binary --runtime-debug']) + +test.execute( + # Some GCC versions hit an address-sanitizer bug otherwise + aslr_off=True) + +test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".mk", r'VL_DEBUG=1') + +test.passes() diff --git a/test_regress/t/t_flag_skipidentical.pl b/test_regress/t/t_flag_skipidentical.pl deleted file mode 100755 index 731515d06..000000000 --- a/test_regress/t/t_flag_skipidentical.pl +++ /dev/null @@ -1,36 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -{ - compile(); - - print "NOTE: use --debugi, as --debug in driver turns off skip-identical\n"; - - my $outfile = "$Self->{obj_dir}/V" . $Self->{name} . ".cpp"; - my @oldstats = stat($outfile); - print "Old mtime=", $oldstats[9], "\n"; - $oldstats[9] or error("No output file found: $outfile\n"); - - sleep(2); # Or else it might take < 1 second to compile and see no diff. - - setenv('VERILATOR_DEBUG_SKIP_IDENTICAL', 1); - compile(); - - my @newstats = stat($outfile); - print "New mtime=", $newstats[9], "\n"; - - ($oldstats[9] == $newstats[9]) - or error("--skip-identical was ignored -- recompiled\n"); -} - -ok(1); -1; diff --git a/test_regress/t/t_flag_skipidentical.py b/test_regress/t/t_flag_skipidentical.py new file mode 100755 index 000000000..5b20bd00b --- /dev/null +++ b/test_regress/t/t_flag_skipidentical.py @@ -0,0 +1,36 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import time + +test.scenarios('vlt') + +test.compile() + +print("NOTE: use --debugi, as --debug in driver turns off skip-identical") + +outfile = test.obj_dir + "/V" + test.name + ".cpp" +oldstats = os.path.getmtime(outfile) +if not oldstats: + test.error("No output file found: " + outfile) +print("Old mtime=", oldstats) + +time.sleep(2) # Or else it might take < 1 second to compile and see no diff. + +test.setenv('VERILATOR_DEBUG_SKIP_IDENTICAL', "1") +test.compile() + +newstats = os.path.getmtime(outfile) +print("New mtime=", newstats) + +if oldstats != newstats: + test.error("--skip-identical was ignored -- recompiled") + +test.passes() diff --git a/test_regress/t/t_flag_stats.pl b/test_regress/t/t_flag_stats.pl deleted file mode 100755 index 1f18c20b1..000000000 --- a/test_regress/t/t_flag_stats.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - verilator_flags2 => ["--stats --stats-vars"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_stats.py b/test_regress/t/t_flag_stats.py new file mode 100755 index 000000000..e3ec064b6 --- /dev/null +++ b/test_regress/t/t_flag_stats.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(verilator_flags2=["--stats --stats-vars"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_structs_packed.pl b/test_regress/t/t_flag_structs_packed.pl deleted file mode 100755 index d9178ac25..000000000 --- a/test_regress/t/t_flag_structs_packed.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -compile( - verilator_flags2 => ['--structs-packed'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_structs_packed.py b/test_regress/t/t_flag_structs_packed.py new file mode 100755 index 000000000..77a354d22 --- /dev/null +++ b/test_regress/t/t_flag_structs_packed.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.compile(verilator_flags2=['--structs-packed']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_structs_packed_bad.pl b/test_regress/t/t_flag_structs_packed_bad.pl deleted file mode 100755 index 2ac9f69e8..000000000 --- a/test_regress/t/t_flag_structs_packed_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -top_filename("t/t_flag_structs_packed.v"); - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_structs_packed_bad.py b/test_regress/t/t_flag_structs_packed_bad.py new file mode 100755 index 000000000..002271397 --- /dev/null +++ b/test_regress/t/t_flag_structs_packed_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_flag_structs_packed.v" + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_suggest.pl b/test_regress/t/t_flag_suggest.pl deleted file mode 100755 index 1022af5ff..000000000 --- a/test_regress/t/t_flag_suggest.pl +++ /dev/null @@ -1,51 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my @opts; -# Typo -push @opts, "-ccc"; -# Typo of an option that starts with "--" -push @opts, "--ccc"; -# Typo of an option that starts with "-no-" -push @opts, "-no-asserT"; -# Typo of an option that starts with "-no" -push @opts, "-noasserT"; -# Typo of an option that allows "-no" -push @opts, "-asserT"; -# Typo of an option that starts with '+' -push @opts, "+definE+A=B"; -# Typo that takes arg -push @opts, "-CFLAGs -ggdb"; -# Typo of an undocumented option -push @opts, "-debug-aborT"; -# Typo of "-Wno" for partial match -push @opts, "-Won-SPLITVAR"; -# Typo after -Wno- for partial match -push @opts, "-Wno-SPLITVER"; -# Typo of -language -push @opts, "-language 1364-1997"; - -my $cmd = ""; - -foreach my $var (@opts) { - $cmd = $cmd . $ENV{VERILATOR_ROOT} . "/bin/verilator ${var}; "; -} - -run(cmd => [$cmd], - verilator_run => 1, - logfile => "$Self->{obj_dir}/sim.log", - fails => 1, - expect_filename => $Self->{golden_filename}, -); - -ok(1); -1; diff --git a/test_regress/t/t_flag_suggest.py b/test_regress/t/t_flag_suggest.py new file mode 100755 index 000000000..baf7f8394 --- /dev/null +++ b/test_regress/t/t_flag_suggest.py @@ -0,0 +1,48 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +opts = [] +# Typo +opts += ["-ccc"] +# Typo of an option that starts with "--" +opts += ["--ccc"] +# Typo of an option that starts with "-no-" +opts += ["-no-asserT"] +# Typo of an option that starts with "-no" +opts += ["-noasserT"] +# Typo of an option that allows "-no" +opts += ["-asserT"] +# Typo of an option that starts with '+' +opts += ["+definE+A=B"] +# Typo that takes arg +opts += ["-CFLAGs -ggdb"] +# Typo of an undocumented option +opts += ["-debug-aborT"] +# Typo of "-Wno" for partial match +opts += ["-Won-SPLITVAR"] +# Typo after -Wno- for partial match +opts += ["-Wno-SPLITVER"] +# Typo of -language +opts += ["-language 1364-1997"] + +cmd = "" +for var in opts: + cmd += os.environ["VERILATOR_ROOT"] + "/bin/verilator " + var + "; " + +test.run(cmd=[cmd], + verilator_run=True, + logfile=test.obj_dir + "/sim.log", + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_supported.pl b/test_regress/t/t_flag_supported.pl deleted file mode 100755 index ae36a6645..000000000 --- a/test_regress/t/t_flag_supported.pl +++ /dev/null @@ -1,42 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -if ($Self->have_coroutines) { - run( - cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator --get-supported COROUTINES"], - expect => '1 -', - logfile => "$Self->{obj_dir}/vlt_coroutines.log", - verilator_run => 1, - ); -} - -if ($Self->have_sc) { - run( - cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator --get-supported SYSTEMC"], - expect => '1 -', - logfile => "$Self->{obj_dir}/vlt_systemc.log", - verilator_run => 1, - ); -} - -run( - cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator --get-supported DOES_NOT_EXIST"], - expect => '', - logfile => "$Self->{obj_dir}/vlt_does_not_exist.log", - verilator_run => 1, - ); - - -ok(1); -1; diff --git a/test_regress/t/t_flag_supported.py b/test_regress/t/t_flag_supported.py new file mode 100755 index 000000000..90f3ca8a9 --- /dev/null +++ b/test_regress/t/t_flag_supported.py @@ -0,0 +1,33 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +if test.have_coroutines: + test.run(cmd=[os.environ["VERILATOR_ROOT"] + "/bin/verilator --get-supported COROUTINES"], + expect="""1 +""", + logfile=test.obj_dir + "/vlt_coroutines.log", + verilator_run=True) + +if test.have_sc: + test.run(cmd=[os.environ["VERILATOR_ROOT"] + "/bin/verilator --get-supported SYSTEMC"], + expect="""1 +""", + logfile=test.obj_dir + "/vlt_systemc.log", + verilator_run=True) + +test.run(cmd=[os.environ["VERILATOR_ROOT"] + "/bin/verilator --get-supported DOES_NOT_EXIST"], + expect='', + logfile=test.obj_dir + "/vlt_does_not_exist.log", + verilator_run=True) + +test.passes() diff --git a/test_regress/t/t_flag_threads_dpi_bad.pl b/test_regress/t/t_flag_threads_dpi_bad.pl deleted file mode 100755 index 46cf0221c..000000000 --- a/test_regress/t/t_flag_threads_dpi_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--threads-dpi bad_one"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_threads_dpi_bad.py b/test_regress/t/t_flag_threads_dpi_bad.py new file mode 100755 index 000000000..e37bc99e3 --- /dev/null +++ b/test_regress/t/t_flag_threads_dpi_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--threads-dpi bad_one"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_timescale.pl b/test_regress/t/t_flag_timescale.pl deleted file mode 100755 index 01f4fe003..000000000 --- a/test_regress/t/t_flag_timescale.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["-timescale 1ms/1us"], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_flag_timescale.py b/test_regress/t/t_flag_timescale.py new file mode 100755 index 000000000..0aee7a5b7 --- /dev/null +++ b/test_regress/t/t_flag_timescale.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["-timescale 1ms/1us"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_timescale_override.pl b/test_regress/t/t_flag_timescale_override.pl deleted file mode 100755 index a63f0bb83..000000000 --- a/test_regress/t/t_flag_timescale_override.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["-timescale-override 1ms/1us"], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_flag_timescale_override.py b/test_regress/t/t_flag_timescale_override.py new file mode 100755 index 000000000..f3c33e6b1 --- /dev/null +++ b/test_regress/t/t_flag_timescale_override.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["-timescale-override 1ms/1us"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_timescale_override2.pl b/test_regress/t/t_flag_timescale_override2.pl deleted file mode 100755 index bc4f9ca6d..000000000 --- a/test_regress/t/t_flag_timescale_override2.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_flag_timescale_override.v"); - -compile( - verilator_flags2 => ["-timescale-override /1us"], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_flag_timescale_override2.py b/test_regress/t/t_flag_timescale_override2.py new file mode 100755 index 000000000..1403c4c24 --- /dev/null +++ b/test_regress/t/t_flag_timescale_override2.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_flag_timescale_override.v" + +test.compile(verilator_flags2=["-timescale-override /1us"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_topmodule.pl b/test_regress/t/t_flag_topmodule.pl deleted file mode 100755 index de44b0532..000000000 --- a/test_regress/t/t_flag_topmodule.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - v_flags2 => ["--top-module b "], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_topmodule.py b/test_regress/t/t_flag_topmodule.py new file mode 100755 index 000000000..3d54ce7d9 --- /dev/null +++ b/test_regress/t/t_flag_topmodule.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(v_flags2=["--top-module b "]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_topmodule_bad.pl b/test_regress/t/t_flag_topmodule_bad.pl deleted file mode 100755 index 856e31ae4..000000000 --- a/test_regress/t/t_flag_topmodule_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_flag_topmodule.v"); - -lint( - fails => 1, - nc => 0, # Need to get it not to give the prompt - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_topmodule_bad.py b/test_regress/t/t_flag_topmodule_bad.py new file mode 100755 index 000000000..55e58e547 --- /dev/null +++ b/test_regress/t/t_flag_topmodule_bad.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_flag_topmodule.v" + +test.lint( + fails=True, + nc=False, # Need to get it not to give the prompt + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_topmodule_bad2.pl b/test_regress/t/t_flag_topmodule_bad2.pl deleted file mode 100755 index c3f6245ff..000000000 --- a/test_regress/t/t_flag_topmodule_bad2.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_flag_topmodule.v"); - -lint( - fails => 1, - v_flags2 => ["--top-module notfound"], - nc => 0, # Need to get it not to give the prompt - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_topmodule_bad2.py b/test_regress/t/t_flag_topmodule_bad2.py new file mode 100755 index 000000000..e78d43f39 --- /dev/null +++ b/test_regress/t/t_flag_topmodule_bad2.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_flag_topmodule.v" + +test.lint( + fails=True, + v_flags2=["--top-module notfound"], + nc=False, # Need to get it not to give the prompt + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_topmodule_inline.pl b/test_regress/t/t_flag_topmodule_inline.pl deleted file mode 100755 index 9ee65bc8a..000000000 --- a/test_regress/t/t_flag_topmodule_inline.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - # This also tests --top as opposed to --top-module - v_flags2 => ["--top b"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_topmodule_inline.py b/test_regress/t/t_flag_topmodule_inline.py new file mode 100755 index 000000000..5738ae537 --- /dev/null +++ b/test_regress/t/t_flag_topmodule_inline.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile( + # This also tests --top as opposed to --top-module + v_flags2=["--top b"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_values_bad.pl b/test_regress/t/t_flag_values_bad.pl deleted file mode 100755 index a5f3d7743..000000000 --- a/test_regress/t/t_flag_values_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--output-split-cfuncs -1", - "--output-split-ctrace -1", - "--reloop-limit -1",], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_values_bad.py b/test_regress/t/t_flag_values_bad.py new file mode 100755 index 000000000..ab8c8bb79 --- /dev/null +++ b/test_regress/t/t_flag_values_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint( + verilator_flags2=["--output-split-cfuncs -1", "--output-split-ctrace -1", "--reloop-limit -1"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_values_deprecated.pl b/test_regress/t/t_flag_values_deprecated.pl deleted file mode 100755 index a4d6ad3c2..000000000 --- a/test_regress/t/t_flag_values_deprecated.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["-Werror-DEPRECATED", "--no-threads"], - fails => 1, - threads => 0, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_values_deprecated.py b/test_regress/t/t_flag_values_deprecated.py new file mode 100755 index 000000000..8db5f897f --- /dev/null +++ b/test_regress/t/t_flag_values_deprecated.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["-Werror-DEPRECATED", "--no-threads"], + fails=True, + threads=0, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_verilate.pl b/test_regress/t/t_flag_verilate.pl deleted file mode 100755 index 958a32da6..000000000 --- a/test_regress/t/t_flag_verilate.pl +++ /dev/null @@ -1,60 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); -top_filename("t/t_flag_make_cmake.v"); - -# We expect below that Vt_flag_verilate.mk and others are not in the build -# tree already when doing --no-verilate, so we must remove them when -# re-running the test. -clean_objs(); - -compile( # Don't call cmake nor gmake from driver.pl. Nothing should be done here. - verilator_make_cmake => 0, - verilator_make_gmake => 0, - verilator_flags2 => ['--exe --cc --no-verilate', - '../' . $Self->{main_filename}] - ); - -# --no-verilate should skip Verilation -if ( -e $Self->{obj_dir} . '/Vt_flag_verilate.mk' ) { - $Self->error('Vt_flag_verilate.mk is unexpectedly created'); -} - -# --verilate this time -compile( # Don't call cmake nor gmake from driver.pl. Just verilate here. - verilator_make_cmake => 0, - verilator_make_gmake => 0, - verilator_flags2 => ['--exe --cc --verilate', - '../' . $Self->{main_filename}] - ); - -# must be verilated this time -if ( ! -e $Self->{obj_dir} . '/Vt_flag_verilate.mk' ) { - $Self->error('Vt_flag_verilate.mk does not exist'); -} - -# Just build, no Verilation. .tree must not be saved even with --dump-tree option. -compile( # Don't call cmake nor gmake from driver.pl. Just build here - verilator_flags2 => ['--exe --cc --build --no-verilate', - '../' . $Self->{main_filename}, - '--debugi 1 --dump-tree --dump-tree-addrids'], - ); - -# The previous run must not verilated, only build is expected. -if (-e $Self->{obj_dir} . '/Vt_flag_verilate_990_final.tree') { - $Self->error('Unexpectedly verilated.'); -} - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_verilate.py b/test_regress/t/t_flag_verilate.py new file mode 100755 index 000000000..38928e3db --- /dev/null +++ b/test_regress/t/t_flag_verilate.py @@ -0,0 +1,52 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_flag_make_cmake.v" + +# We expect below that Vt_flag_verilate.mk and others are not in the build +# tree already when doing --no-verilate, so we must remove them when +# re-running the test. +test.clean_objs() + +test.compile( # Don't call cmake nor gmake from driver.py. Nothing should be done here. + verilator_make_cmake=False, + verilator_make_gmake=False, + verilator_flags2=['--exe --cc --no-verilate', '../' + test.main_filename]) + +# --no-verilate should skip Verilation +if os.path.exists(test.obj_dir + '/Vt_flag_verilate.mk'): + test.error('Vt_flag_verilate.mk is unexpectedly created') + +# --verilate this time +test.compile( # Don't call cmake nor gmake from driver.py. Just verilate here. + verilator_make_cmake=False, + verilator_make_gmake=False, + verilator_flags2=['--exe --cc --verilate', '../' + test.main_filename]) + +# must be verilated this time +if not os.path.exists(test.obj_dir + '/Vt_flag_verilate.mk'): + test.error('Vt_flag_verilate.mk does not exist') + +# Just build, no Verilation. .tree must not be saved even with --dump-tree option. +test.compile( # Don't call cmake nor gmake from driver.py. Just build here + verilator_flags2=[ + '--exe --cc --build --no-verilate', '../' + test.main_filename, + '--debugi 1 --dump-tree --dump-tree-addrids' + ]) + +# The previous run must not verilated, only build is expected. +if os.path.exists(test.obj_dir + '/Vt_flag_verilate_990_final.tree'): + test.error('Unexpectedly verilated.') + +test.execute() + +test.passes() diff --git a/test_regress/t/t_flag_verilate_threads_bad.pl b/test_regress/t/t_flag_verilate_threads_bad.pl deleted file mode 100755 index 8743294da..000000000 --- a/test_regress/t/t_flag_verilate_threads_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_flag_werror.v"); - -lint( - fails => 1, - verilator_flags => [qw(--verilate-jobs -1)], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_verilate_threads_bad.py b/test_regress/t/t_flag_verilate_threads_bad.py new file mode 100755 index 000000000..26f50c37b --- /dev/null +++ b/test_regress/t/t_flag_verilate_threads_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_flag_werror.v" + +test.lint(fails=True, verilator_flags=["--verilate-jobs -1"], expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_version.pl b/test_regress/t/t_flag_version.pl deleted file mode 100755 index 5e7c46a06..000000000 --- a/test_regress/t/t_flag_version.pl +++ /dev/null @@ -1,49 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(dist => 1); - -foreach my $prog ( - # See also t_flag_help.pl - "$ENV{VERILATOR_ROOT}/bin/verilator", - "$ENV{VERILATOR_ROOT}/bin/verilator_coverage", - #"$ENV{VERILATOR_ROOT}/bin/verilator_difftree", - #"$ENV{VERILATOR_ROOT}/bin/verilator_gantt", - #"$ENV{VERILATOR_ROOT}/bin/verilator_profcfunc", - ) { - run(fails => 0, - cmd => ["perl", $prog, - "--version"], - tee => $self->{verbose}, - logfile => "$Self->{obj_dir}/t_help.log", - expect => qr/^Verilator/, - verilator_run => 1, - ); - - run(fails => 0, - cmd => ["perl", $prog, - "-V"], - tee => $self->{verbose}, - logfile => "$Self->{obj_dir}/t_help.log", - expect => qr/^Verilator/, - verilator_run => 1, - ); - - run(fails => 0, - cmd => ["perl", $prog, - "-V"], - logfile => "$Self->{obj_dir}/t_help.log", - expect => qr/^Verilator/, - verilator_run => 1, - ); -} - -ok(1); -1; diff --git a/test_regress/t/t_flag_version.py b/test_regress/t/t_flag_version.py new file mode 100755 index 000000000..478f3a049 --- /dev/null +++ b/test_regress/t/t_flag_version.py @@ -0,0 +1,42 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +for prog in [ + # See also t_flag_help.py + os.environ["VERILATOR_ROOT"] + "/bin/verilator", + os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", + #os.environ["VERILATOR_ROOT"] + "/bin/verilator_difftree", + #os.environ["VERILATOR_ROOT"] + "/bin/verilator_gantt", + #os.environ["VERILATOR_ROOT"] + "/bin/verilator_profcfunc", +]: + test.run(fails=False, + cmd=["perl", prog, "--version"], + tee=test.verbose, + logfile=test.obj_dir + "/t_help.log", + expect=r'^Verilator', + verilator_run=True) + + test.run(fails=False, + cmd=["perl", prog, "-V"], + tee=test.verbose, + logfile=test.obj_dir + "/t_help.log", + expect=r'^Verilator', + verilator_run=True) + + test.run(fails=False, + cmd=["perl", prog, "-V"], + logfile=test.obj_dir + "/t_help.log", + expect=r'^Verilator', + verilator_run=True) + +test.passes() diff --git a/test_regress/t/t_flag_werror_bad1.pl b/test_regress/t/t_flag_werror_bad1.pl deleted file mode 100755 index c9a9614cc..000000000 --- a/test_regress/t/t_flag_werror_bad1.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_flag_werror.v"); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_werror_bad1.py b/test_regress/t/t_flag_werror_bad1.py new file mode 100755 index 000000000..61de16fab --- /dev/null +++ b/test_regress/t/t_flag_werror_bad1.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_flag_werror.v" + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_werror_bad2.pl b/test_regress/t/t_flag_werror_bad2.pl deleted file mode 100755 index e3044056a..000000000 --- a/test_regress/t/t_flag_werror_bad2.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_flag_werror.v"); - -lint( - fails => 1, - verilator_flags => [qw(-cc -Werror-WIDTH)], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_werror_bad2.py b/test_regress/t/t_flag_werror_bad2.py new file mode 100755 index 000000000..c960be889 --- /dev/null +++ b/test_regress/t/t_flag_werror_bad2.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_flag_werror.v" + +test.lint(fails=True, verilator_flags=["-cc -Werror-WIDTH"], expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_werror_bad3.pl b/test_regress/t/t_flag_werror_bad3.pl deleted file mode 100755 index d031c654f..000000000 --- a/test_regress/t/t_flag_werror_bad3.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_flag_werror.v"); - -lint( - fails => 1, - verilator_flags => [qw(-cc -Werror-NOSUCHERRORASTHIS)], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_werror_bad3.py b/test_regress/t/t_flag_werror_bad3.py new file mode 100755 index 000000000..7d2cd8587 --- /dev/null +++ b/test_regress/t/t_flag_werror_bad3.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_flag_werror.v" + +test.lint(fails=True, + verilator_flags=["-cc -Werror-NOSUCHERRORASTHIS"], + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_wfatal.pl b/test_regress/t/t_flag_wfatal.pl deleted file mode 100755 index 1fee4b430..000000000 --- a/test_regress/t/t_flag_wfatal.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_flag_wfatal.v"); - -lint( - verilator_flags2 => ["--lint-only -Wno-fatal"], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_wfatal.py b/test_regress/t/t_flag_wfatal.py new file mode 100755 index 000000000..a23be6d7a --- /dev/null +++ b/test_regress/t/t_flag_wfatal.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_flag_wfatal.v" + +test.lint(verilator_flags2=["--lint-only -Wno-fatal"], expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_woff.pl b/test_regress/t/t_flag_woff.pl deleted file mode 100755 index 17c128753..000000000 --- a/test_regress/t/t_flag_woff.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only -Wno-WIDTH"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_woff.py b/test_regress/t/t_flag_woff.py new file mode 100755 index 000000000..b31c5f049 --- /dev/null +++ b/test_regress/t/t_flag_woff.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only -Wno-WIDTH"]) + +test.passes() diff --git a/test_regress/t/t_flag_woff_bad.pl b/test_regress/t/t_flag_woff_bad.pl deleted file mode 100755 index d1c151c64..000000000 --- a/test_regress/t/t_flag_woff_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only -Wno-NOSUCHERRORASTHIS"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_woff_bad.py b/test_regress/t/t_flag_woff_bad.py new file mode 100755 index 000000000..10a2221a7 --- /dev/null +++ b/test_regress/t/t_flag_woff_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only -Wno-NOSUCHERRORASTHIS"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_wpedantic_bad.pl b/test_regress/t/t_flag_wpedantic_bad.pl deleted file mode 100755 index 9de6b85ee..000000000 --- a/test_regress/t/t_flag_wpedantic_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["-Wpedantic"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_wpedantic_bad.py b/test_regress/t/t_flag_wpedantic_bad.py new file mode 100755 index 000000000..4cc015636 --- /dev/null +++ b/test_regress/t/t_flag_wpedantic_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["-Wpedantic"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_wwarn_bad.pl b/test_regress/t/t_flag_wwarn_bad.pl deleted file mode 100755 index 541ce84cf..000000000 --- a/test_regress/t/t_flag_wwarn_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_flag_werror.v"); - -lint( - fails => 1, - verilator_flags => [qw(-cc -Wwarn-NOSUCHERRORASTHIS)], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_wwarn_bad.py b/test_regress/t/t_flag_wwarn_bad.py new file mode 100755 index 000000000..ec10e44d4 --- /dev/null +++ b/test_regress/t/t_flag_wwarn_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_flag_werror.v" + +test.lint(fails=True, + verilator_flags=["-cc -Wwarn-NOSUCHERRORASTHIS"], + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_x_assign_bad.pl b/test_regress/t/t_flag_x_assign_bad.pl deleted file mode 100755 index af3b0a78c..000000000 --- a/test_regress/t/t_flag_x_assign_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--x-assign bad_one"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_x_assign_bad.py b/test_regress/t/t_flag_x_assign_bad.py new file mode 100755 index 000000000..a800d4eb2 --- /dev/null +++ b/test_regress/t/t_flag_x_assign_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--x-assign bad_one"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_x_initial_bad.pl b/test_regress/t/t_flag_x_initial_bad.pl deleted file mode 100755 index 88423465e..000000000 --- a/test_regress/t/t_flag_x_initial_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--x-initial bad_one"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_flag_x_initial_bad.py b/test_regress/t/t_flag_x_initial_bad.py new file mode 100755 index 000000000..98cc57a39 --- /dev/null +++ b/test_regress/t/t_flag_x_initial_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--x-initial bad_one"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_xinitial_0.pl b/test_regress/t/t_flag_xinitial_0.pl deleted file mode 100755 index d706c2de6..000000000 --- a/test_regress/t/t_flag_xinitial_0.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - verilator_flags2 => ["--x-initial 0"], - ); - -execute( - ); - -file_grep_not("$Self->{obj_dir}/$Self->{vm_prefix}___024root__Slow.cpp", qr/VL_RAND_RESET/); - -ok(1); -1; diff --git a/test_regress/t/t_flag_xinitial_0.py b/test_regress/t/t_flag_xinitial_0.py new file mode 100755 index 000000000..a5c7efa68 --- /dev/null +++ b/test_regress/t/t_flag_xinitial_0.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(verilator_flags2=["--x-initial 0"]) + +test.execute() + +test.file_grep_not(test.obj_dir + "/" + test.vm_prefix + "___024root__Slow.cpp", r'VL_RAND_RESET') + +test.passes() diff --git a/test_regress/t/t_flag_xinitial_unique.pl b/test_regress/t/t_flag_xinitial_unique.pl deleted file mode 100755 index 0e3f165fb..000000000 --- a/test_regress/t/t_flag_xinitial_unique.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - verilator_flags2 => ["--x-initial unique"], - ); - -execute( - ); - -my @files = glob_all("$Self->{obj_dir}/$Self->{vm_prefix}___024root__DepSet_*__Slow.cpp"); -file_grep_any(\@files, qr/VL_RAND_RESET/); - -ok(1); -1; diff --git a/test_regress/t/t_flag_xinitial_unique.py b/test_regress/t/t_flag_xinitial_unique.py new file mode 100755 index 000000000..64ac07036 --- /dev/null +++ b/test_regress/t/t_flag_xinitial_unique.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(verilator_flags2=["--x-initial unique"]) + +test.execute() + +files = glob.glob(test.obj_dir + "/" + test.vm_prefix + "___024root__DepSet_*__Slow.cpp") +test.file_grep_any(files, r'VL_RAND_RESET') + +test.passes() diff --git a/test_regress/t/t_for_assign.pl b/test_regress/t/t_for_assign.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_for_assign.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_for_assign.py b/test_regress/t/t_for_assign.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_for_assign.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_for_break.pl b/test_regress/t/t_for_break.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_for_break.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_for_break.py b/test_regress/t/t_for_break.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_for_break.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_for_comma.pl b/test_regress/t/t_for_comma.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_for_comma.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_for_comma.py b/test_regress/t/t_for_comma.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_for_comma.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_for_count.pl b/test_regress/t/t_for_count.pl deleted file mode 100755 index fdc76316a..000000000 --- a/test_regress/t/t_for_count.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_for_count.py b/test_regress/t/t_for_count.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_for_count.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_for_disable_dot.pl b/test_regress/t/t_for_disable_dot.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_for_disable_dot.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_for_disable_dot.py b/test_regress/t/t_for_disable_dot.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_for_disable_dot.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_for_funcbound.pl b/test_regress/t/t_for_funcbound.pl deleted file mode 100755 index f0df46de2..000000000 --- a/test_regress/t/t_for_funcbound.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - expect => -'[10] hello -[20] world -', - ); - -ok(1); -1; diff --git a/test_regress/t/t_for_funcbound.py b/test_regress/t/t_for_funcbound.py new file mode 100755 index 000000000..5291ebae6 --- /dev/null +++ b/test_regress/t/t_for_funcbound.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect="""[10] hello +[20] world +""") + +test.passes() diff --git a/test_regress/t/t_for_init_bug.pl b/test_regress/t/t_for_init_bug.pl deleted file mode 100755 index 300cb0b09..000000000 --- a/test_regress/t/t_for_init_bug.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -#execute() - -ok(1); -1; diff --git a/test_regress/t/t_for_init_bug.py b/test_regress/t/t_for_init_bug.py new file mode 100755 index 000000000..3aafd524c --- /dev/null +++ b/test_regress/t/t_for_init_bug.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +#test.execute() + +test.passes() diff --git a/test_regress/t/t_for_local.pl b/test_regress/t/t_for_local.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_for_local.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_for_local.py b/test_regress/t/t_for_local.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_for_local.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_for_loop.pl b/test_regress/t/t_for_loop.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_for_loop.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_for_loop.py b/test_regress/t/t_for_loop.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_for_loop.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_force.pl b/test_regress/t/t_force.pl deleted file mode 100755 index 6e1338f8e..000000000 --- a/test_regress/t/t_force.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_force.py b/test_regress/t/t_force.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_force.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_force_bad_rw.pl b/test_regress/t/t_force_bad_rw.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_force_bad_rw.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_force_bad_rw.py b/test_regress/t/t_force_bad_rw.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_force_bad_rw.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_force_mid.pl b/test_regress/t/t_force_mid.pl deleted file mode 100755 index baf68a8e1..000000000 --- a/test_regress/t/t_force_mid.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/t_force_mid.cpp"] - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_force_mid.py b/test_regress/t/t_force_mid.py new file mode 100755 index 000000000..f37ad07c8 --- /dev/null +++ b/test_regress/t/t_force_mid.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_force_multi.pl b/test_regress/t/t_force_multi.pl deleted file mode 100755 index 6e1338f8e..000000000 --- a/test_regress/t/t_force_multi.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_force_multi.py b/test_regress/t/t_force_multi.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_force_multi.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_force_port_alias.pl b/test_regress/t/t_force_port_alias.pl deleted file mode 100755 index 2633a14a7..000000000 --- a/test_regress/t/t_force_port_alias.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_force_port_alias.py b/test_regress/t/t_force_port_alias.py new file mode 100755 index 000000000..cacc314ab --- /dev/null +++ b/test_regress/t/t_force_port_alias.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_force_release_net.pl b/test_regress/t/t_force_release_net.pl deleted file mode 100755 index db100371d..000000000 --- a/test_regress/t/t_force_release_net.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile(); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_force_release_net.py b/test_regress/t/t_force_release_net.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_force_release_net.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_force_release_net_reverse.pl b/test_regress/t/t_force_release_net_reverse.pl deleted file mode 100755 index 2ecabfed9..000000000 --- a/test_regress/t/t_force_release_net_reverse.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_force_release_net.v"); - -compile( - verilator_flags2 => ['+define+REVERSE'] - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_force_release_net_reverse.py b/test_regress/t/t_force_release_net_reverse.py new file mode 100755 index 000000000..eee5aeb88 --- /dev/null +++ b/test_regress/t/t_force_release_net_reverse.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_force_release_net.v" + +test.compile(verilator_flags2=['+define+REVERSE']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_force_release_net_trace.pl b/test_regress/t/t_force_release_net_trace.pl deleted file mode 100755 index b325bca65..000000000 --- a/test_regress/t/t_force_release_net_trace.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_force_release_net.v"); - -compile( - verilator_flags2 => ['--trace'] - ); - -execute( - ); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_force_release_net_trace.py b/test_regress/t/t_force_release_net_trace.py new file mode 100755 index 000000000..721b7b0e4 --- /dev/null +++ b/test_regress/t/t_force_release_net_trace.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_force_release_net.v" + +test.compile(verilator_flags2=['--trace']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_force_release_var.pl b/test_regress/t/t_force_release_var.pl deleted file mode 100755 index db100371d..000000000 --- a/test_regress/t/t_force_release_var.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile(); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_force_release_var.py b/test_regress/t/t_force_release_var.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_force_release_var.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_force_release_var_reverse.pl b/test_regress/t/t_force_release_var_reverse.pl deleted file mode 100755 index 85bbc7b95..000000000 --- a/test_regress/t/t_force_release_var_reverse.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_force_release_var.v"); - -compile( - verilator_flags2 => ['+define+REVERSE'] - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_force_release_var_reverse.py b/test_regress/t/t_force_release_var_reverse.py new file mode 100755 index 000000000..624ccbc3b --- /dev/null +++ b/test_regress/t/t_force_release_var_reverse.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_force_release_var.v" + +test.compile(verilator_flags2=['+define+REVERSE']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_force_release_var_trace.pl b/test_regress/t/t_force_release_var_trace.pl deleted file mode 100755 index 50f5a6fdc..000000000 --- a/test_regress/t/t_force_release_var_trace.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_force_release_var.v"); - -compile( - verilator_flags2 => ['--trace'] - ); - -execute( - ); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_force_release_var_trace.py b/test_regress/t/t_force_release_var_trace.py new file mode 100755 index 000000000..d8f366168 --- /dev/null +++ b/test_regress/t/t_force_release_var_trace.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_force_release_var.v" + +test.compile(verilator_flags2=['--trace']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_force_subnet.pl b/test_regress/t/t_force_subnet.pl deleted file mode 100755 index 6e1338f8e..000000000 --- a/test_regress/t/t_force_subnet.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_force_subnet.py b/test_regress/t/t_force_subnet.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_force_subnet.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_force_subvar.pl b/test_regress/t/t_force_subvar.pl deleted file mode 100755 index 6e1338f8e..000000000 --- a/test_regress/t/t_force_subvar.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_force_subvar.py b/test_regress/t/t_force_subvar.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_force_subvar.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_force_tri.pl b/test_regress/t/t_force_tri.pl deleted file mode 100755 index c213189c1..000000000 --- a/test_regress/t/t_force_tri.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_force_tri.py b/test_regress/t/t_force_tri.py new file mode 100755 index 000000000..6038b562c --- /dev/null +++ b/test_regress/t/t_force_tri.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_forceable_net_cmt.pl b/test_regress/t/t_forceable_net_cmt.pl deleted file mode 100755 index 98246139e..000000000 --- a/test_regress/t/t_forceable_net_cmt.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_forceable_net.v"); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => [ - '-DCMT=1', - '--exe', - "$Self->{t_dir}/t_forceable_net.cpp" - ], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_forceable_net_cmt.py b/test_regress/t/t_forceable_net_cmt.py new file mode 100755 index 000000000..041bb0c49 --- /dev/null +++ b/test_regress/t/t_forceable_net_cmt.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.pli_filename = "t/t_forceable_net.cpp" +test.top_filename = "t/t_forceable_net.v" + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=['-DCMT=1', '--exe', test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_forceable_net_cmt_trace.pl b/test_regress/t/t_forceable_net_cmt_trace.pl deleted file mode 100755 index 0d031d7c8..000000000 --- a/test_regress/t/t_forceable_net_cmt_trace.pl +++ /dev/null @@ -1,33 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_forceable_net.v"); -golden_filename("t/t_forceable_net_trace.vcd"); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => [ - '-DCMT=1', - '--exe', - '--trace', - "$Self->{t_dir}/t_forceable_net.cpp" - ], - ); - -execute( - ); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_forceable_net_cmt_trace.py b/test_regress/t/t_forceable_net_cmt_trace.py new file mode 100755 index 000000000..bed940206 --- /dev/null +++ b/test_regress/t/t_forceable_net_cmt_trace.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.pli_filename = "t/t_forceable_net.cpp" +test.top_filename = "t/t_forceable_net.v" +test.golden_filename = "t/t_forceable_net_trace.vcd" + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=['-DCMT=1', '--exe', '--trace', test.pli_filename]) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_forceable_net_vlt.pl b/test_regress/t/t_forceable_net_vlt.pl deleted file mode 100755 index 0c6094b3b..000000000 --- a/test_regress/t/t_forceable_net_vlt.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_forceable_net.v"); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => [ - '--exe', - "$Self->{t_dir}/t_forceable_net.cpp", - "$Self->{t_dir}/t_forceable_net.vlt" - ], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_forceable_net_vlt.py b/test_regress/t/t_forceable_net_vlt.py new file mode 100755 index 000000000..5d9d78291 --- /dev/null +++ b/test_regress/t/t_forceable_net_vlt.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.pli_filename = "t/t_forceable_net.cpp" +test.top_filename = "t/t_forceable_net.v" + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=['--exe', test.pli_filename, test.t_dir + "/t_forceable_net.vlt"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_forceable_net_vlt_trace.pl b/test_regress/t/t_forceable_net_vlt_trace.pl deleted file mode 100755 index 3afb852b3..000000000 --- a/test_regress/t/t_forceable_net_vlt_trace.pl +++ /dev/null @@ -1,33 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_forceable_net.v"); -golden_filename("t/t_forceable_net_trace.vcd"); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => [ - '--exe', - '--trace', - "$Self->{t_dir}/t_forceable_net.cpp", - "$Self->{t_dir}/t_forceable_net.vlt" - ], - ); - -execute( - ); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_forceable_net_vlt_trace.py b/test_regress/t/t_forceable_net_vlt_trace.py new file mode 100755 index 000000000..59b55a74e --- /dev/null +++ b/test_regress/t/t_forceable_net_vlt_trace.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.pli_filename = "t/t_forceable_net.cpp" +test.top_filename = "t/t_forceable_net.v" +test.golden_filename = "t/t_forceable_net_trace.vcd" + +test.compile( + make_top_shell=False, + make_main=False, + verilator_flags2=['--exe', '--trace', test.pli_filename, test.t_dir + "/t_forceable_net.vlt"]) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_forceable_var_cmt.pl b/test_regress/t/t_forceable_var_cmt.pl deleted file mode 100755 index 198ea6dc3..000000000 --- a/test_regress/t/t_forceable_var_cmt.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_forceable_var.v"); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => [ - '-DCMT=1', - '--exe', - "$Self->{t_dir}/t_forceable_var.cpp" - ], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_forceable_var_cmt.py b/test_regress/t/t_forceable_var_cmt.py new file mode 100755 index 000000000..c79bd38ef --- /dev/null +++ b/test_regress/t/t_forceable_var_cmt.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.pli_filename = "t/t_forceable_var.cpp" +test.top_filename = "t/t_forceable_var.v" + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=['-DCMT=1', '--exe', test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_forceable_var_cmt_trace.pl b/test_regress/t/t_forceable_var_cmt_trace.pl deleted file mode 100755 index 1215def9a..000000000 --- a/test_regress/t/t_forceable_var_cmt_trace.pl +++ /dev/null @@ -1,33 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_forceable_var.v"); -golden_filename("t/t_forceable_var_trace.vcd"); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => [ - '-DCMT=1', - '--exe', - '--trace', - "$Self->{t_dir}/t_forceable_var.cpp" - ], - ); - -execute( - ); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_forceable_var_cmt_trace.py b/test_regress/t/t_forceable_var_cmt_trace.py new file mode 100755 index 000000000..a59d2e6c5 --- /dev/null +++ b/test_regress/t/t_forceable_var_cmt_trace.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.pli_filename = "t/t_forceable_var.cpp" +test.top_filename = "t/t_forceable_var.v" +test.golden_filename = "t/t_forceable_var_trace.vcd" + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=['-DCMT=1', '--exe', '--trace', test.pli_filename]) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_forceable_var_vlt.pl b/test_regress/t/t_forceable_var_vlt.pl deleted file mode 100755 index 99e3611c0..000000000 --- a/test_regress/t/t_forceable_var_vlt.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_forceable_var.v"); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => [ - '--exe', - "$Self->{t_dir}/t_forceable_var.cpp", - "$Self->{t_dir}/t_forceable_var.vlt" - ], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_forceable_var_vlt.py b/test_regress/t/t_forceable_var_vlt.py new file mode 100755 index 000000000..83033dff9 --- /dev/null +++ b/test_regress/t/t_forceable_var_vlt.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.pli_filename = "t/t_forceable_var.cpp" +test.top_filename = "t/t_forceable_var.v" + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=['--exe', test.pli_filename, test.t_dir + "/t_forceable_var.vlt"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_forceable_var_vlt_trace.pl b/test_regress/t/t_forceable_var_vlt_trace.pl deleted file mode 100755 index c690ce385..000000000 --- a/test_regress/t/t_forceable_var_vlt_trace.pl +++ /dev/null @@ -1,33 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_forceable_var.v"); -golden_filename("t/t_forceable_var_trace.vcd"); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => [ - '--exe', - '--trace', - "$Self->{t_dir}/t_forceable_var.cpp", - "$Self->{t_dir}/t_forceable_var.vlt" - ], - ); - -execute( - ); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_forceable_var_vlt_trace.py b/test_regress/t/t_forceable_var_vlt_trace.py new file mode 100755 index 000000000..fad62ca60 --- /dev/null +++ b/test_regress/t/t_forceable_var_vlt_trace.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.pli_filename = "t/t_forceable_var.cpp" +test.top_filename = "t/t_forceable_var.v" +test.golden_filename = "t/t_forceable_var_trace.vcd" + +test.compile( + make_top_shell=False, + make_main=False, + verilator_flags2=['--exe', '--trace', test.pli_filename, test.t_dir + "/t_forceable_var.vlt"]) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_foreach.pl b/test_regress/t/t_foreach.pl deleted file mode 100755 index da62ca6a9..000000000 --- a/test_regress/t/t_foreach.pl +++ /dev/null @@ -1,34 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--assert'] - ); - -execute( - ); - -# We expect all loops should be unrolled by verilator, -# none of the loop variables should exist in the output: -for my $file (glob_all("$Self->{obj_dir}/$Self->{vm_prefix}*.cpp")) { - file_grep_not($file, qr/index_/); -} - -# Further, we expect that all logic within the loop should -# have been evaluated inside the compiler. So there should be -# no references to 'sum' in the .cpp. -for my $file (glob_all("$Self->{obj_dir}/$Self->{vm_prefix}*.cpp")) { - file_grep_not($file, qr/[^a-zA-Z]sum[^a-zA-Z]/); -} - -ok(1); -1; diff --git a/test_regress/t/t_foreach.py b/test_regress/t/t_foreach.py new file mode 100755 index 000000000..7a4bc150c --- /dev/null +++ b/test_regress/t/t_foreach.py @@ -0,0 +1,29 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--assert']) + +test.execute() + +# We expect all loops should be unrolled by verilator, +# none of the loop variables should exist in the output: +for filename in test.glob_some(test.obj_dir + "/" + test.vm_prefix + "*.cpp"): + test.file_grep_not(filename, r'index_') + +# Further, we expect that all logic within the loop should +# have been evaluated inside the compiler. So there should be +# no references to 'sum' in the .cpp. +for filename in test.glob_some(test.obj_dir + "/" + test.vm_prefix + "*.cpp"): + test.file_grep_not(filename, r'[^a-zA-Z]sum[^a-zA-Z]') + +test.passes() diff --git a/test_regress/t/t_foreach.v b/test_regress/t/t_foreach.v index b700d5bb6..22035e4cd 100644 --- a/test_regress/t/t_foreach.v +++ b/test_regress/t/t_foreach.v @@ -37,7 +37,7 @@ module t (/*AUTOARG*/); initial begin sum = 0; // We use 'index_' as the prefix for all loop vars, - // this allows t_foreach.pl to confirm that all loops + // this allows t_foreach.py to confirm that all loops // have been unrolled and flattened away and no loop vars // remain in the generated .cpp foreach (depth1_array[index_a]) begin diff --git a/test_regress/t/t_foreach_bad.pl b/test_regress/t/t_foreach_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_foreach_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_foreach_bad.py b/test_regress/t/t_foreach_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_foreach_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_foreach_blkname.pl b/test_regress/t/t_foreach_blkname.pl deleted file mode 100755 index 13587bf85..000000000 --- a/test_regress/t/t_foreach_blkname.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - ); - -ok(1); -1; diff --git a/test_regress/t/t_foreach_blkname.py b/test_regress/t/t_foreach_blkname.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_foreach_blkname.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_foreach_class.pl b/test_regress/t/t_foreach_class.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_foreach_class.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_foreach_class.py b/test_regress/t/t_foreach_class.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_foreach_class.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_foreach_const.pl b/test_regress/t/t_foreach_const.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_foreach_const.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_foreach_const.py b/test_regress/t/t_foreach_const.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_foreach_const.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_foreach_const.v b/test_regress/t/t_foreach_const.v index 999ca69e1..08e95917c 100644 --- a/test_regress/t/t_foreach_const.v +++ b/test_regress/t/t_foreach_const.v @@ -34,7 +34,7 @@ module t (/*AUTOARG*/); function [63:0] test1; test1 = 0; // We use 'index_' as the prefix for all loop vars, - // this allows t_foreach.pl to confirm that all loops + // this allows t_foreach.py to confirm that all loops // have been unrolled and flattened away and no loop vars // remain in the generated .cpp foreach (depth1_array[index_a]) begin diff --git a/test_regress/t/t_foreach_iface.pl b/test_regress/t/t_foreach_iface.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_foreach_iface.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_foreach_iface.py b/test_regress/t/t_foreach_iface.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_foreach_iface.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_foreach_nindex_bad.pl b/test_regress/t/t_foreach_nindex_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_foreach_nindex_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_foreach_nindex_bad.py b/test_regress/t/t_foreach_nindex_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_foreach_nindex_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_foreach_type_bad.pl b/test_regress/t/t_foreach_type_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_foreach_type_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_foreach_type_bad.py b/test_regress/t/t_foreach_type_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_foreach_type_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fork.pl b/test_regress/t/t_fork.pl deleted file mode 100755 index 9459580d1..000000000 --- a/test_regress/t/t_fork.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ['--no-timing'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_fork.py b/test_regress/t/t_fork.py new file mode 100755 index 000000000..bb6e45319 --- /dev/null +++ b/test_regress/t/t_fork.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=['--no-timing'], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fork_bbox.pl b/test_regress/t/t_fork_bbox.pl deleted file mode 100755 index 72f18add1..000000000 --- a/test_regress/t/t_fork_bbox.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ['--lint-only --no-timing --bbox-unsup'], - ); - -ok(1); -1; diff --git a/test_regress/t/t_fork_bbox.py b/test_regress/t/t_fork_bbox.py new file mode 100755 index 000000000..7a642a939 --- /dev/null +++ b/test_regress/t/t_fork_bbox.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=['--lint-only --no-timing --bbox-unsup']) + +test.passes() diff --git a/test_regress/t/t_fork_block_item_declaration.pl b/test_regress/t/t_fork_block_item_declaration.pl deleted file mode 100755 index 21a2189cc..000000000 --- a/test_regress/t/t_fork_block_item_declaration.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_fork_block_item_declaration.py b/test_regress/t/t_fork_block_item_declaration.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_fork_block_item_declaration.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fork_dynscope.pl b/test_regress/t/t_fork_dynscope.pl deleted file mode 100755 index 21a2189cc..000000000 --- a/test_regress/t/t_fork_dynscope.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_fork_dynscope.py b/test_regress/t/t_fork_dynscope.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_fork_dynscope.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fork_dynscope_out.pl b/test_regress/t/t_fork_dynscope_out.pl deleted file mode 100755 index f2487da19..000000000 --- a/test_regress/t/t_fork_dynscope_out.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--binary -Wno-INITIALDLY"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_fork_dynscope_out.py b/test_regress/t/t_fork_dynscope_out.py new file mode 100755 index 000000000..e555ab909 --- /dev/null +++ b/test_regress/t/t_fork_dynscope_out.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary -Wno-INITIALDLY"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fork_dynscope_unsup.pl b/test_regress/t/t_fork_dynscope_unsup.pl deleted file mode 100755 index 4bc2cbf36..000000000 --- a/test_regress/t/t_fork_dynscope_unsup.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint( - verilator_flags2 => ["--timing"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_fork_dynscope_unsup.py b/test_regress/t/t_fork_dynscope_unsup.py new file mode 100755 index 000000000..27ba50a31 --- /dev/null +++ b/test_regress/t/t_fork_dynscope_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(verilator_flags2=["--timing"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fork_func2_bad.pl b/test_regress/t/t_fork_func2_bad.pl deleted file mode 100755 index 89ffd046b..000000000 --- a/test_regress/t/t_fork_func2_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ['--lint-only'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_fork_func2_bad.py b/test_regress/t/t_fork_func2_bad.py new file mode 100755 index 000000000..d6dde1012 --- /dev/null +++ b/test_regress/t/t_fork_func2_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=['--lint-only'], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fork_func_bad.pl b/test_regress/t/t_fork_func_bad.pl deleted file mode 100755 index 89ffd046b..000000000 --- a/test_regress/t/t_fork_func_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ['--lint-only'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_fork_func_bad.py b/test_regress/t/t_fork_func_bad.py new file mode 100755 index 000000000..d6dde1012 --- /dev/null +++ b/test_regress/t/t_fork_func_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=['--lint-only'], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fork_initial.pl b/test_regress/t/t_fork_initial.pl deleted file mode 100755 index e4ae8115a..000000000 --- a/test_regress/t/t_fork_initial.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - # issue #4471 - remove this - verilator_make_gmake => 0, - ); - -# issue #4471 - add this -#execute( -# ); - -ok(1); -1; diff --git a/test_regress/t/t_fork_initial.py b/test_regress/t/t_fork_initial.py new file mode 100755 index 000000000..8dbd20354 --- /dev/null +++ b/test_regress/t/t_fork_initial.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + verilator_flags2=["--exe --main --timing"], + # issue #4471 - remove this + verilator_make_gmake=False) + +# issue #4471 - add this +#test.execute() + +test.passes() diff --git a/test_regress/t/t_fork_join_none_any_nested.pl b/test_regress/t/t_fork_join_none_any_nested.pl deleted file mode 100755 index a8264f47b..000000000 --- a/test_regress/t/t_fork_join_none_any_nested.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--binary --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_fork_join_none_any_nested.py b/test_regress/t/t_fork_join_none_any_nested.py new file mode 100755 index 000000000..7bd93561b --- /dev/null +++ b/test_regress/t/t_fork_join_none_any_nested.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fork_join_none_class_cap.pl b/test_regress/t/t_fork_join_none_class_cap.pl deleted file mode 100755 index 21a2189cc..000000000 --- a/test_regress/t/t_fork_join_none_class_cap.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_fork_join_none_class_cap.py b/test_regress/t/t_fork_join_none_class_cap.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_fork_join_none_class_cap.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fork_join_none_virtual.pl b/test_regress/t/t_fork_join_none_virtual.pl deleted file mode 100755 index 21a2189cc..000000000 --- a/test_regress/t/t_fork_join_none_virtual.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_fork_join_none_virtual.py b/test_regress/t/t_fork_join_none_virtual.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_fork_join_none_virtual.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fork_jumpblock.pl b/test_regress/t/t_fork_jumpblock.pl deleted file mode 100755 index f8708065f..000000000 --- a/test_regress/t/t_fork_jumpblock.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_fork_jumpblock.py b/test_regress/t/t_fork_jumpblock.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_fork_jumpblock.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fork_label.pl b/test_regress/t/t_fork_label.pl deleted file mode 100755 index dc3cfd898..000000000 --- a/test_regress/t/t_fork_label.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--binary --no-timing'], - ); - -execute(); - -ok(1); -1; diff --git a/test_regress/t/t_fork_label.py b/test_regress/t/t_fork_label.py new file mode 100755 index 000000000..46560bc9c --- /dev/null +++ b/test_regress/t/t_fork_label.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--binary --no-timing']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fork_label_timing.pl b/test_regress/t/t_fork_label_timing.pl deleted file mode 100755 index 51cbb28f4..000000000 --- a/test_regress/t/t_fork_label_timing.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_fork_label.v"); - -compile( - verilator_flags2 => ["--exe --main --timing"], - make_main => 0, - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_fork_label_timing.py b/test_regress/t/t_fork_label_timing.py new file mode 100755 index 000000000..21739800c --- /dev/null +++ b/test_regress/t/t_fork_label_timing.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_fork_label.v" + +test.compile(verilator_flags2=["--exe --main --timing"], make_main=False) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fork_none_var.pl b/test_regress/t/t_fork_none_var.pl deleted file mode 100755 index 21a2189cc..000000000 --- a/test_regress/t/t_fork_none_var.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_fork_none_var.py b/test_regress/t/t_fork_none_var.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_fork_none_var.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fork_output_arg.pl b/test_regress/t/t_fork_output_arg.pl deleted file mode 100755 index 21a2189cc..000000000 --- a/test_regress/t/t_fork_output_arg.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_fork_output_arg.py b/test_regress/t/t_fork_output_arg.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_fork_output_arg.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fork_port.pl b/test_regress/t/t_fork_port.pl deleted file mode 100755 index df4c1c59e..000000000 --- a/test_regress/t/t_fork_port.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_fork_port.py b/test_regress/t/t_fork_port.py new file mode 100755 index 000000000..664ad3bec --- /dev/null +++ b/test_regress/t/t_fork_port.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fork_timing.pl b/test_regress/t/t_fork_timing.pl deleted file mode 100755 index 92bbd0c2f..000000000 --- a/test_regress/t/t_fork_timing.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_fork.v"); - -compile( - verilator_flags2 => ["--binary --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_fork_timing.py b/test_regress/t/t_fork_timing.py new file mode 100755 index 000000000..b8512ba82 --- /dev/null +++ b/test_regress/t/t_fork_timing.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_fork.v" + +test.compile(verilator_flags2=["--binary --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_format_wide_decimal.pl b/test_regress/t/t_format_wide_decimal.pl deleted file mode 100755 index 0b32cc99c..000000000 --- a/test_regress/t/t_format_wide_decimal.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["-Wall"] - ); - - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_format_wide_decimal.py b/test_regress/t/t_format_wide_decimal.py new file mode 100755 index 000000000..957f7bb4c --- /dev/null +++ b/test_regress/t/t_format_wide_decimal.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["-Wall"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_func.pl b/test_regress/t/t_func.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_func.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func.py b/test_regress/t/t_func.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_arg_complex.pl b/test_regress/t/t_func_arg_complex.pl deleted file mode 100755 index dc84f82b3..000000000 --- a/test_regress/t/t_func_arg_complex.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - v_flags2 => ["-Wno-PKGNODECL -Wno-UNPACKED -Wno-IMPLICITSTATIC -Wno-CONSTRAINTIGN -Wno-MISINDENT", - "--error-limit 200"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_arg_complex.py b/test_regress/t/t_func_arg_complex.py new file mode 100755 index 000000000..b9135448f --- /dev/null +++ b/test_regress/t/t_func_arg_complex.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(v_flags2=[ + "-Wno-PKGNODECL -Wno-UNPACKED -Wno-IMPLICITSTATIC -Wno-CONSTRAINTIGN -Wno-MISINDENT", + "--error-limit 200" +]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_bad.pl b/test_regress/t/t_func_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_func_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_bad.py b/test_regress/t/t_func_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_func_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_func_bad_width.pl b/test_regress/t/t_func_bad_width.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_func_bad_width.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_bad_width.py b/test_regress/t/t_func_bad_width.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_func_bad_width.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_func_begin2.pl b/test_regress/t/t_func_begin2.pl deleted file mode 100755 index 0f2fb4862..000000000 --- a/test_regress/t/t_func_begin2.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only --inline-mult 1"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_begin2.py b/test_regress/t/t_func_begin2.py new file mode 100755 index 000000000..713453910 --- /dev/null +++ b/test_regress/t/t_func_begin2.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only --inline-mult 1"]) + +test.passes() diff --git a/test_regress/t/t_func_call_order.pl b/test_regress/t/t_func_call_order.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_func_call_order.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_call_order.py b/test_regress/t/t_func_call_order.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_call_order.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_check.pl b/test_regress/t/t_func_check.pl deleted file mode 100755 index 037482f42..000000000 --- a/test_regress/t/t_func_check.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -$Self->{verilated_randReset} = 1; - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_check.py b/test_regress/t/t_func_check.py new file mode 100755 index 000000000..629441927 --- /dev/null +++ b/test_regress/t/t_func_check.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.verilated_randReset = 1 + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_complex.pl b/test_regress/t/t_func_complex.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_func_complex.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_complex.py b/test_regress/t/t_func_complex.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_complex.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_complex_noinl.pl b/test_regress/t/t_func_complex_noinl.pl deleted file mode 100755 index 31b688d7c..000000000 --- a/test_regress/t/t_func_complex_noinl.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -top_filename("t/t_func_complex.v"); - -scenarios(simulator => 1); - -compile( - v_flags2 => ["+define+TEST_NOINLINE"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_complex_noinl.py b/test_regress/t/t_func_complex_noinl.py new file mode 100755 index 000000000..b5ec76840 --- /dev/null +++ b/test_regress/t/t_func_complex_noinl.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +test.top_filename = "t/t_func_complex.v" + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["+define+TEST_NOINLINE"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_cond.pl b/test_regress/t/t_func_cond.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_func_cond.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_cond.py b/test_regress/t/t_func_cond.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_cond.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_const.pl b/test_regress/t/t_func_const.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_func_const.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_const.py b/test_regress/t/t_func_const.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_const.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_const2_bad.pl b/test_regress/t/t_func_const2_bad.pl deleted file mode 100755 index 0fd907991..000000000 --- a/test_regress/t/t_func_const2_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2017 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_const2_bad.py b/test_regress/t/t_func_const2_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_func_const2_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_func_const3_bad.pl b/test_regress/t/t_func_const3_bad.pl deleted file mode 100755 index 5ece32e17..000000000 --- a/test_regress/t/t_func_const3_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2017 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_const3_bad.py b/test_regress/t/t_func_const3_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_func_const3_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_func_const_bad.pl b/test_regress/t/t_func_const_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_func_const_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_const_bad.py b/test_regress/t/t_func_const_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_func_const_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_func_const_packed_array_bad.pl b/test_regress/t/t_func_const_packed_array_bad.pl deleted file mode 100755 index 0fd907991..000000000 --- a/test_regress/t/t_func_const_packed_array_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2017 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_const_packed_array_bad.py b/test_regress/t/t_func_const_packed_array_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_func_const_packed_array_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_func_const_packed_struct_bad.pl b/test_regress/t/t_func_const_packed_struct_bad.pl deleted file mode 100755 index 0fd907991..000000000 --- a/test_regress/t/t_func_const_packed_struct_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2017 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_const_packed_struct_bad.py b/test_regress/t/t_func_const_packed_struct_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_func_const_packed_struct_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_func_const_packed_struct_bad2.pl b/test_regress/t/t_func_const_packed_struct_bad2.pl deleted file mode 100755 index 0fd907991..000000000 --- a/test_regress/t/t_func_const_packed_struct_bad2.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2017 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_const_packed_struct_bad2.py b/test_regress/t/t_func_const_packed_struct_bad2.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_func_const_packed_struct_bad2.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_func_const_struct_bad.pl b/test_regress/t/t_func_const_struct_bad.pl deleted file mode 100755 index 0fd907991..000000000 --- a/test_regress/t/t_func_const_struct_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2017 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_const_struct_bad.py b/test_regress/t/t_func_const_struct_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_func_const_struct_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_func_crc.pl b/test_regress/t/t_func_crc.pl deleted file mode 100755 index 80d0232b8..000000000 --- a/test_regress/t/t_func_crc.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--compiler msvc", "--stats"], # We have deep expressions we want to test - ); - -execute( - ); - -if ($Self->{vlt}) { - file_grep($Self->{stats}, qr/Optimizations, Const bit op reduction\s+(\d+)/, 3888); -} - -ok(1); -1; diff --git a/test_regress/t/t_func_crc.py b/test_regress/t/t_func_crc.py new file mode 100755 index 000000000..0304e7ed5 --- /dev/null +++ b/test_regress/t/t_func_crc.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + # We have deep expressions we want to test + verilator_flags2=["--compiler msvc", "--stats"]) + +test.execute() + +if test.vlt: + test.file_grep(test.stats, r'Optimizations, Const bit op reduction\s+(\d+)', 3888) + +test.passes() diff --git a/test_regress/t/t_func_default_warn.pl b/test_regress/t/t_func_default_warn.pl deleted file mode 100755 index 25afbc4ee..000000000 --- a/test_regress/t/t_func_default_warn.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["-Wno-WIDTH"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_default_warn.py b/test_regress/t/t_func_default_warn.py new file mode 100755 index 000000000..78d425f95 --- /dev/null +++ b/test_regress/t/t_func_default_warn.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["-Wno-WIDTH"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_defaults.pl b/test_regress/t/t_func_defaults.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_func_defaults.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_defaults.py b/test_regress/t/t_func_defaults.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_defaults.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_dotted_inl0.pl b/test_regress/t/t_func_dotted_inl0.pl deleted file mode 100755 index 03dbd07ca..000000000 --- a/test_regress/t/t_func_dotted_inl0.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_func_dotted.v"); -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - v_flags2 => ['--no-json-edit-nums', '+define+ATTRIBUTES', '+define+NOUSE_INLINE',], - ); - -if ($Self->{vlt_all}) { - file_grep("$out_filename", qr/{"type":"MODULE","name":"ma",.*"loc":"e,84:[^"]*","origName":"ma",.*,"modPublic":true/); - file_grep("$out_filename", qr/{"type":"MODULE","name":"mb",.*"loc":"e,99:[^"]*","origName":"mb",.*"modPublic":true/); - file_grep("$out_filename", qr/{"type":"MODULE","name":"mc","addr":"[^"]*","loc":"e,127:[^"]*","origName":"mc",.*"modPublic":true/); - file_grep("$out_filename", qr/{"type":"MODULE","name":"mc__PB1","addr":"[^"]*","loc":"e,127:[^"]*","origName":"mc",.*"modPublic":true/); -} - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_dotted_inl0.py b/test_regress/t/t_func_dotted_inl0.py new file mode 100755 index 000000000..ac6c72de4 --- /dev/null +++ b/test_regress/t/t_func_dotted_inl0.py @@ -0,0 +1,37 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_func_dotted.v" + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(v_flags2=['--no-json-edit-nums', '+define+ATTRIBUTES', '+define+NOUSE_INLINE']) + +if test.vlt_all: + test.file_grep( + out_filename, + r'{"type":"MODULE","name":"ma",.*"loc":"e,84:[^"]*","origName":"ma",.*,"modPublic":true') + test.file_grep( + out_filename, + r'{"type":"MODULE","name":"mb",.*"loc":"e,99:[^"]*","origName":"mb",.*"modPublic":true') + test.file_grep( + out_filename, + r'{"type":"MODULE","name":"mc","addr":"[^"]*","loc":"e,127:[^"]*","origName":"mc",.*"modPublic":true' + ) + test.file_grep( + out_filename, + r'{"type":"MODULE","name":"mc__PB1","addr":"[^"]*","loc":"e,127:[^"]*","origName":"mc",.*"modPublic":true' + ) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_dotted_inl0_vlt.pl b/test_regress/t/t_func_dotted_inl0_vlt.pl deleted file mode 100755 index 28b0fc06a..000000000 --- a/test_regress/t/t_func_dotted_inl0_vlt.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_func_dotted.v"); -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - v_flags2 => ["--no-json-edit-nums", "$Self->{t_dir}/t_func_dotted_inl0.vlt"], - ); - -if ($Self->{vlt_all}) { - file_grep("$out_filename", qr/{"type":"MODULE","name":"ma",.*"loc":"f,84:[^"]*",.*"origName":"ma",.*"modPublic":true/); - file_grep("$out_filename", qr/{"type":"MODULE","name":"mb",.*"loc":"f,99:[^"]*",.*"origName":"mb",.*"modPublic":true/); - file_grep("$out_filename", qr/{"type":"MODULE","name":"mc",.*"loc":"f,127:[^"]*",.*"origName":"mc",.*"modPublic":true/); - file_grep("$out_filename", qr/{"type":"MODULE","name":"mc__PB1",.*"loc":"f,127:[^"]*",.*"origName":"mc",.*"modPublic":true/); -} - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_dotted_inl0_vlt.py b/test_regress/t/t_func_dotted_inl0_vlt.py new file mode 100755 index 000000000..dd12a7af4 --- /dev/null +++ b/test_regress/t/t_func_dotted_inl0_vlt.py @@ -0,0 +1,36 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_func_dotted.v" + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(v_flags2=["--no-json-edit-nums", test.t_dir + "/t_func_dotted_inl0.vlt"]) + +if test.vlt_all: + test.file_grep( + out_filename, + r'{"type":"MODULE","name":"ma",.*"loc":"f,84:[^"]*",.*"origName":"ma",.*"modPublic":true') + test.file_grep( + out_filename, + r'{"type":"MODULE","name":"mb",.*"loc":"f,99:[^"]*",.*"origName":"mb",.*"modPublic":true') + test.file_grep( + out_filename, + r'{"type":"MODULE","name":"mc",.*"loc":"f,127:[^"]*",.*"origName":"mc",.*"modPublic":true') + test.file_grep( + out_filename, + r'{"type":"MODULE","name":"mc__PB1",.*"loc":"f,127:[^"]*",.*"origName":"mc",.*"modPublic":true' + ) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_dotted_inl1.pl b/test_regress/t/t_func_dotted_inl1.pl deleted file mode 100755 index 2f9bc0a1c..000000000 --- a/test_regress/t/t_func_dotted_inl1.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_func_dotted.v"); -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - v_flags2 => ["--no-json-edit-nums", '+define+ATTRIBUTES', '+define+USE_INLINE',], - ); - -if ($Self->{vlt_all}) { - file_grep_not("$out_filename", qr/"ma0"/); - file_grep_not("$out_filename", qr/"mb0"/); - file_grep_not("$out_filename", qr/"mc0"/); -} - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_dotted_inl1.py b/test_regress/t/t_func_dotted_inl1.py new file mode 100755 index 000000000..a60a34cb4 --- /dev/null +++ b/test_regress/t/t_func_dotted_inl1.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_func_dotted.v" + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(v_flags2=["--no-json-edit-nums", '+define+ATTRIBUTES', '+define+USE_INLINE']) + +if test.vlt_all: + test.file_grep_not(out_filename, r'"ma0"') + test.file_grep_not(out_filename, r'"mb0"') + test.file_grep_not(out_filename, r'"mc0"') + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_dotted_inl1_vlt.pl b/test_regress/t/t_func_dotted_inl1_vlt.pl deleted file mode 100755 index 25e67c1c4..000000000 --- a/test_regress/t/t_func_dotted_inl1_vlt.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_func_dotted.v"); -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - v_flags2 => ["--no-json-edit-nums", "t/t_func_dotted_inl1.vlt",], - ); - -if ($Self->{vlt_all}) { - file_grep_not("$out_filename", qr/"ma0"/); - file_grep_not("$out_filename", qr/"mb0"/); - file_grep_not("$out_filename", qr/"mc0"/); -} - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_dotted_inl1_vlt.py b/test_regress/t/t_func_dotted_inl1_vlt.py new file mode 100755 index 000000000..bd48a7f96 --- /dev/null +++ b/test_regress/t/t_func_dotted_inl1_vlt.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_func_dotted.v" + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(v_flags2=["--no-json-edit-nums", "t/t_func_dotted_inl1.vlt"]) + +if test.vlt_all: + test.file_grep_not(out_filename, r'"ma0"') + test.file_grep_not(out_filename, r'"mb0"') + test.file_grep_not(out_filename, r'"mc0"') + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_dotted_inl2.pl b/test_regress/t/t_func_dotted_inl2.pl deleted file mode 100755 index e9f234086..000000000 --- a/test_regress/t/t_func_dotted_inl2.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_func_dotted.v"); -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - v_flags2 => ["--no-json-edit-nums", '+define+ATTRIBUTES', '+define+USE_INLINE_MID',], - ); - -if ($Self->{vlt_all}) { - my $modp = (file_grep("$out_filename", qr/{"type":"MODULE","name":"mb","addr":"([^"]*)","loc":"e,99:[^"]*",.*"origName":"mb"/))[0]; - file_grep("$out_filename", qr/{"type":"CELL","name":"t.ma0.mb0","addr":"[^"]*","loc":"e,87:[^"]*",.*"origName":"mb0",.*"modp":"([^"]*)"/, $modp); -} - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_dotted_inl2.py b/test_regress/t/t_func_dotted_inl2.py new file mode 100755 index 000000000..1ab47172d --- /dev/null +++ b/test_regress/t/t_func_dotted_inl2.py @@ -0,0 +1,31 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_func_dotted.v" + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(v_flags2=["--no-json-edit-nums", '+define+ATTRIBUTES', '+define+USE_INLINE_MID']) + +if test.vlt_all: + modps = test.file_grep( + out_filename, + r'{"type":"MODULE","name":"mb","addr":"([^"]*)","loc":"e,99:[^"]*",.*"origName":"mb"') + modp = modps[0][0] + test.file_grep( + out_filename, + r'{"type":"CELL","name":"t.ma0.mb0","addr":"[^"]*","loc":"e,87:[^"]*",.*"origName":"mb0",.*"modp":"([^"]*)"', + modp) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_dotted_inl2_vlt.pl b/test_regress/t/t_func_dotted_inl2_vlt.pl deleted file mode 100755 index 4b8c800b9..000000000 --- a/test_regress/t/t_func_dotted_inl2_vlt.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_func_dotted.v"); -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - v_flags2 => ["--no-json-edit-nums", "t/t_func_dotted_inl2.vlt",], - ); - -if ($Self->{vlt_all}) { - my $modp = (file_grep("$out_filename", qr/{"type":"MODULE","name":"mb","addr":"([^"]*)","loc":"f,99:[^"]*",.*"origName":"mb"/))[0]; - file_grep("$out_filename", qr/{"type":"CELL","name":"t.ma0.mb0","addr":"[^"]*","loc":"f,87:[^"]*",.*"origName":"mb0",.*"modp":"([^"]*)"/, $modp); -} - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_dotted_inl2_vlt.py b/test_regress/t/t_func_dotted_inl2_vlt.py new file mode 100755 index 000000000..76860999e --- /dev/null +++ b/test_regress/t/t_func_dotted_inl2_vlt.py @@ -0,0 +1,30 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_func_dotted.v" +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(v_flags2=["--no-json-edit-nums", "t/t_func_dotted_inl2.vlt"]) + +if test.vlt_all: + modps = test.file_grep( + out_filename, + r'{"type":"MODULE","name":"mb","addr":"([^"]*)","loc":"f,99:[^"]*",.*"origName":"mb"') + modp = modps[0][0] + test.file_grep( + out_filename, + r'{"type":"CELL","name":"t.ma0.mb0","addr":"[^"]*","loc":"f,87:[^"]*",.*"origName":"mb0",.*"modp":"([^"]*)"', + modp) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_endian.pl b/test_regress/t/t_func_endian.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_func_endian.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_endian.py b/test_regress/t/t_func_endian.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_endian.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_first.pl b/test_regress/t/t_func_first.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_func_first.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_first.py b/test_regress/t/t_func_first.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_first.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_flip.pl b/test_regress/t/t_func_flip.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_func_flip.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_flip.py b/test_regress/t/t_func_flip.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_flip.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_gen.pl b/test_regress/t/t_func_gen.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_func_gen.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_gen.py b/test_regress/t/t_func_gen.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_gen.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_graphcirc.pl b/test_regress/t/t_func_graphcirc.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_func_graphcirc.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_graphcirc.py b/test_regress/t/t_func_graphcirc.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_graphcirc.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_grey.pl b/test_regress/t/t_func_grey.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_func_grey.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_grey.py b/test_regress/t/t_func_grey.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_grey.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_impure_bad.pl b/test_regress/t/t_func_impure_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_func_impure_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_impure_bad.py b/test_regress/t/t_func_impure_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_func_impure_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_func_inconly.pl b/test_regress/t/t_func_inconly.pl deleted file mode 100755 index 56363dab6..000000000 --- a/test_regress/t/t_func_inconly.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_inconly.py b/test_regress/t/t_func_inconly.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_inconly.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_inout_bit_sel.pl b/test_regress/t/t_func_inout_bit_sel.pl deleted file mode 100755 index 3a732a7dc..000000000 --- a/test_regress/t/t_func_inout_bit_sel.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_inout_bit_sel.py b/test_regress/t/t_func_inout_bit_sel.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_inout_bit_sel.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_io_order.pl b/test_regress/t/t_func_io_order.pl deleted file mode 100755 index 3708008f8..000000000 --- a/test_regress/t/t_func_io_order.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_io_order.py b/test_regress/t/t_func_io_order.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_io_order.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_lib.pl b/test_regress/t/t_func_lib.pl deleted file mode 100755 index db4cb34df..000000000 --- a/test_regress/t/t_func_lib.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ['-v', 't/t_func_lib_sub.v'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_lib.py b/test_regress/t/t_func_lib.py new file mode 100755 index 000000000..1b870040f --- /dev/null +++ b/test_regress/t/t_func_lib.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=['-v', 't/t_func_lib_sub.v']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_lib_sub.pl b/test_regress/t/t_func_lib_sub.pl deleted file mode 100755 index 8651e4fd4..000000000 --- a/test_regress/t/t_func_lib_sub.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - verilator_flags2 => ['--no-timing'], - ); -# No execute -ok(1); -1; diff --git a/test_regress/t/t_func_lib_sub.py b/test_regress/t/t_func_lib_sub.py new file mode 100755 index 000000000..de97f6118 --- /dev/null +++ b/test_regress/t/t_func_lib_sub.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(verilator_flags2=['--no-timing']) + +#test.execute() + +test.passes() diff --git a/test_regress/t/t_func_lib_sub_timing.pl b/test_regress/t/t_func_lib_sub_timing.pl deleted file mode 100755 index 6101d0fa0..000000000 --- a/test_regress/t/t_func_lib_sub_timing.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); # UNOPTTHREADS in vltmt - -top_filename("t/t_func_lib_sub.v"); - -compile( - verilator_flags2 => ["--binary --timing"], - ); - -# No execute -ok(1); -1; diff --git a/test_regress/t/t_func_lib_sub_timing.py b/test_regress/t/t_func_lib_sub_timing.py new file mode 100755 index 000000000..b882e9cc6 --- /dev/null +++ b/test_regress/t/t_func_lib_sub_timing.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') # UNOPTTHREADS in vltmt +test.top_filename = "t/t_func_lib_sub.v" + +test.compile(verilator_flags2=["--binary --timing"]) + +#test.execute() + +test.passes() diff --git a/test_regress/t/t_func_link.pl b/test_regress/t/t_func_link.pl deleted file mode 100755 index 8b320a422..000000000 --- a/test_regress/t/t_func_link.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_link.py b/test_regress/t/t_func_link.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_link.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_many_return.pl b/test_regress/t/t_func_many_return.pl deleted file mode 100755 index 8a98a199a..000000000 --- a/test_regress/t/t_func_many_return.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--comp-limit-blocks 100"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_many_return.py b/test_regress/t/t_func_many_return.py new file mode 100755 index 000000000..5b582e767 --- /dev/null +++ b/test_regress/t/t_func_many_return.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--comp-limit-blocks 100"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_mlog2.pl b/test_regress/t/t_func_mlog2.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_func_mlog2.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_mlog2.py b/test_regress/t/t_func_mlog2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_mlog2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_modify_input.pl b/test_regress/t/t_func_modify_input.pl deleted file mode 100755 index 32bdf873d..000000000 --- a/test_regress/t/t_func_modify_input.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile(); - -ok(1); -1; diff --git a/test_regress/t/t_func_modify_input.py b/test_regress/t/t_func_modify_input.py new file mode 100755 index 000000000..0b27c3dc0 --- /dev/null +++ b/test_regress/t/t_func_modify_input.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_func_named.pl b/test_regress/t/t_func_named.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_func_named.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_named.py b/test_regress/t/t_func_named.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_named.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_no_lifetime_bad.pl b/test_regress/t/t_func_no_lifetime_bad.pl deleted file mode 100755 index 7d0a36d0d..000000000 --- a/test_regress/t/t_func_no_lifetime_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -execute( - ) if !$Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_func_no_lifetime_bad.py b/test_regress/t/t_func_no_lifetime_bad.py new file mode 100755 index 000000000..966dc53da --- /dev/null +++ b/test_regress/t/t_func_no_lifetime_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) + +if not test.vlt_all: + test.execute() + +test.passes() diff --git a/test_regress/t/t_func_no_parentheses_bad.pl b/test_regress/t/t_func_no_parentheses_bad.pl deleted file mode 100755 index 7d0a36d0d..000000000 --- a/test_regress/t/t_func_no_parentheses_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -execute( - ) if !$Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_func_no_parentheses_bad.py b/test_regress/t/t_func_no_parentheses_bad.py new file mode 100755 index 000000000..966dc53da --- /dev/null +++ b/test_regress/t/t_func_no_parentheses_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) + +if not test.vlt_all: + test.execute() + +test.passes() diff --git a/test_regress/t/t_func_noinl.pl b/test_regress/t/t_func_noinl.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_func_noinl.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_noinl.py b/test_regress/t/t_func_noinl.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_noinl.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_numones.pl b/test_regress/t/t_func_numones.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_func_numones.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_numones.py b/test_regress/t/t_func_numones.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_numones.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_outfirst.pl b/test_regress/t/t_func_outfirst.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_func_outfirst.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_outfirst.py b/test_regress/t/t_func_outfirst.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_outfirst.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_outp.pl b/test_regress/t/t_func_outp.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_func_outp.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_outp.py b/test_regress/t/t_func_outp.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_outp.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_paramed.pl b/test_regress/t/t_func_paramed.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_func_paramed.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_paramed.py b/test_regress/t/t_func_paramed.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_paramed.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_plog.pl b/test_regress/t/t_func_plog.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_func_plog.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_plog.py b/test_regress/t/t_func_plog.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_plog.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_public.pl b/test_regress/t/t_func_public.pl deleted file mode 100755 index 9b67696bb..000000000 --- a/test_regress/t/t_func_public.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['+define+VERILATOR_PUBLIC_TASKS'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_public.py b/test_regress/t/t_func_public.py new file mode 100755 index 000000000..8c9c746dc --- /dev/null +++ b/test_regress/t/t_func_public.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['+define+VERILATOR_PUBLIC_TASKS']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_public_trace.pl b/test_regress/t/t_func_public_trace.pl deleted file mode 100755 index 10e02184d..000000000 --- a/test_regress/t/t_func_public_trace.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_func_public.v"); - -compile( - verilator_flags2 => ["--trace"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_public_trace.py b/test_regress/t/t_func_public_trace.py new file mode 100755 index 000000000..296e9f1cf --- /dev/null +++ b/test_regress/t/t_func_public_trace.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_func_public.v" + +test.compile(verilator_flags2=["--trace"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_rand.pl b/test_regress/t/t_func_rand.pl deleted file mode 100755 index 46b75d671..000000000 --- a/test_regress/t/t_func_rand.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp", "--no-timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_rand.py b/test_regress/t/t_func_rand.py new file mode 100755 index 000000000..7b94250d8 --- /dev/null +++ b/test_regress/t/t_func_rand.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--exe", test.pli_filename, "--no-timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_range.pl b/test_regress/t/t_func_range.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_func_range.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_range.py b/test_regress/t/t_func_range.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_range.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_real_abs.pl b/test_regress/t/t_func_real_abs.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_func_real_abs.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_real_abs.py b/test_regress/t/t_func_real_abs.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_real_abs.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_real_exprstmt.pl b/test_regress/t/t_func_real_exprstmt.pl deleted file mode 100755 index 496700b88..000000000 --- a/test_regress/t/t_func_real_exprstmt.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -if ($Self->{vlt_all}) { - # Check no EXPRSTMTs in final output - should get optimized away - file_grep_not($Self->{stats}, qr/Node count, EXPRSTMT/); -} - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_real_exprstmt.py b/test_regress/t/t_func_real_exprstmt.py new file mode 100755 index 000000000..f8d9a4ad0 --- /dev/null +++ b/test_regress/t/t_func_real_exprstmt.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats"]) + +if test.vlt_all: + # Check no EXPRSTMTs in final output - should get optimized away + test.file_grep_not(test.stats, r'Node count, EXPRSTMT') + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_real_param.pl b/test_regress/t/t_func_real_param.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_func_real_param.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_real_param.py b/test_regress/t/t_func_real_param.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_real_param.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_recurse.pl b/test_regress/t/t_func_recurse.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_func_recurse.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_recurse.py b/test_regress/t/t_func_recurse.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_recurse.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_recurse2.pl b/test_regress/t/t_func_recurse2.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_func_recurse2.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_recurse2.py b/test_regress/t/t_func_recurse2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_recurse2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_recurse_param.pl b/test_regress/t/t_func_recurse_param.pl deleted file mode 100755 index 391ec23fd..000000000 --- a/test_regress/t/t_func_recurse_param.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -execute( - ) if !$Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_func_recurse_param.py b/test_regress/t/t_func_recurse_param.py new file mode 100755 index 000000000..966dc53da --- /dev/null +++ b/test_regress/t/t_func_recurse_param.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) + +if not test.vlt_all: + test.execute() + +test.passes() diff --git a/test_regress/t/t_func_recurse_param_bad.pl b/test_regress/t/t_func_recurse_param_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_func_recurse_param_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_recurse_param_bad.py b/test_regress/t/t_func_recurse_param_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_func_recurse_param_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_func_redef.pl b/test_regress/t/t_func_redef.pl deleted file mode 100755 index 552bd97db..000000000 --- a/test_regress/t/t_func_redef.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_redef.py b/test_regress/t/t_func_redef.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_func_redef.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_func_ref.pl b/test_regress/t/t_func_ref.pl deleted file mode 100755 index 3708008f8..000000000 --- a/test_regress/t/t_func_ref.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_ref.py b/test_regress/t/t_func_ref.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_ref.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_ref_arg.pl b/test_regress/t/t_func_ref_arg.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_func_ref_arg.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_ref_arg.py b/test_regress/t/t_func_ref_arg.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_ref_arg.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_ref_bad.pl b/test_regress/t/t_func_ref_bad.pl deleted file mode 100755 index 23eda8f99..000000000 --- a/test_regress/t/t_func_ref_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_ref_bad.py b/test_regress/t/t_func_ref_bad.py new file mode 100755 index 000000000..07fc79e8e --- /dev/null +++ b/test_regress/t/t_func_ref_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_func_refio_bad.pl b/test_regress/t/t_func_refio_bad.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_func_refio_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_refio_bad.py b/test_regress/t/t_func_refio_bad.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_func_refio_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_func_regfirst.pl b/test_regress/t/t_func_regfirst.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_func_regfirst.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_regfirst.py b/test_regress/t/t_func_regfirst.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_regfirst.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_return.pl b/test_regress/t/t_func_return.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_func_return.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_return.py b/test_regress/t/t_func_return.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_return.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_return_bad.pl b/test_regress/t/t_func_return_bad.pl deleted file mode 100755 index 0c0e3ac70..000000000 --- a/test_regress/t/t_func_return_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2011 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_return_bad.py b/test_regress/t/t_func_return_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_func_return_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_func_sel.pl b/test_regress/t/t_func_sel.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_func_sel.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_sel.py b/test_regress/t/t_func_sel.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_sel.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_sum.pl b/test_regress/t/t_func_sum.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_func_sum.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_sum.py b/test_regress/t/t_func_sum.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_sum.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_task_bad.pl b/test_regress/t/t_func_task_bad.pl deleted file mode 100755 index 0c0e3ac70..000000000 --- a/test_regress/t/t_func_task_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2011 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_task_bad.py b/test_regress/t/t_func_task_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_func_task_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_func_tie_bad.pl b/test_regress/t/t_func_tie_bad.pl deleted file mode 100755 index 0c0e3ac70..000000000 --- a/test_regress/t/t_func_tie_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2011 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_tie_bad.py b/test_regress/t/t_func_tie_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_func_tie_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_func_twocall.pl b/test_regress/t/t_func_twocall.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_func_twocall.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_twocall.py b/test_regress/t/t_func_twocall.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_twocall.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_twocall_noexpand.pl b/test_regress/t/t_func_twocall_noexpand.pl deleted file mode 100755 index f85427094..000000000 --- a/test_regress/t/t_func_twocall_noexpand.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_func_twocall.v"); - -compile( - verilator_flags2 => ['-fno-expand'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_twocall_noexpand.py b/test_regress/t/t_func_twocall_noexpand.py new file mode 100755 index 000000000..995ad7526 --- /dev/null +++ b/test_regress/t/t_func_twocall_noexpand.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_func_twocall.v" + +test.compile(verilator_flags2=['-fno-expand']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_types.pl b/test_regress/t/t_func_types.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_func_types.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_types.py b/test_regress/t/t_func_types.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_types.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_under.pl b/test_regress/t/t_func_under.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_func_under.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_under.py b/test_regress/t/t_func_under.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_under.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_under2.pl b/test_regress/t/t_func_under2.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_func_under2.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_under2.py b/test_regress/t/t_func_under2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_under2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_uninit.pl b/test_regress/t/t_func_uninit.pl deleted file mode 100755 index 6e1338f8e..000000000 --- a/test_regress/t/t_func_uninit.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_uninit.py b/test_regress/t/t_func_uninit.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_uninit.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_unit.pl b/test_regress/t/t_func_unit.pl deleted file mode 100755 index 56363dab6..000000000 --- a/test_regress/t/t_func_unit.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_unit.py b/test_regress/t/t_func_unit.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_unit.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_v.pl b/test_regress/t/t_func_v.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_func_v.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_v.py b/test_regress/t/t_func_v.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_v.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_v_noinl.pl b/test_regress/t/t_func_v_noinl.pl deleted file mode 100755 index 1145d18cd..000000000 --- a/test_regress/t/t_func_v_noinl.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_func_v.v"); - -compile( - v_flags2 => ['+define+T_FUNC_V_NOINL',], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_v_noinl.py b/test_regress/t/t_func_v_noinl.py new file mode 100755 index 000000000..eb69b64b8 --- /dev/null +++ b/test_regress/t/t_func_v_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_func_v.v" + +test.compile(v_flags2=['+define+T_FUNC_V_NOINL']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_void.pl b/test_regress/t/t_func_void.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_func_void.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_void.py b/test_regress/t/t_func_void.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_void.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_void_bad.pl b/test_regress/t/t_func_void_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_func_void_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_void_bad.py b/test_regress/t/t_func_void_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_func_void_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_func_while.pl b/test_regress/t/t_func_while.pl deleted file mode 100755 index 886645acd..000000000 --- a/test_regress/t/t_func_while.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--trace"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_while.py b/test_regress/t/t_func_while.py new file mode 100755 index 000000000..320934d1d --- /dev/null +++ b/test_regress/t/t_func_while.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--trace"]) + +test.passes() diff --git a/test_regress/t/t_func_wide.pl b/test_regress/t/t_func_wide.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_func_wide.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_wide.py b/test_regress/t/t_func_wide.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_func_wide.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_wide_out.pl b/test_regress/t/t_func_wide_out.pl deleted file mode 100755 index 2e87a8a5c..000000000 --- a/test_regress/t/t_func_wide_out.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["-Wno-WIDTHTRUNC"], - v_flags2 => ["+define+T_FUNC_WIDE_OUT t/t_func_wide_out_c.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_wide_out.py b/test_regress/t/t_func_wide_out.py new file mode 100755 index 000000000..a4ec64568 --- /dev/null +++ b/test_regress/t/t_func_wide_out.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["-Wno-WIDTHTRUNC"], + v_flags2=["+define+T_FUNC_WIDE_OUT t/t_func_wide_out_c.cpp"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_wide_out_bad.pl b/test_regress/t/t_func_wide_out_bad.pl deleted file mode 100755 index 15b164f6a..000000000 --- a/test_regress/t/t_func_wide_out_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_func_wide_out.v"); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_wide_out_bad.py b/test_regress/t/t_func_wide_out_bad.py new file mode 100755 index 000000000..f2623d634 --- /dev/null +++ b/test_regress/t/t_func_wide_out_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_func_wide_out.v" + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_func_wide_out_noinl.pl b/test_regress/t/t_func_wide_out_noinl.pl deleted file mode 100755 index eee2581fa..000000000 --- a/test_regress/t/t_func_wide_out_noinl.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t_func_wide_out.v"); - -compile( - verilator_flags2 => ["-Wno-WIDTHTRUNC"], - v_flags2 => ["+define+T_FUNC_WIDE_OUT_NOINL +define+TEST_NOINLINE t/t_func_wide_out_c.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_func_wide_out_noinl.py b/test_regress/t/t_func_wide_out_noinl.py new file mode 100755 index 000000000..a27b30540 --- /dev/null +++ b/test_regress/t/t_func_wide_out_noinl.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t_func_wide_out.v" + +test.compile( + verilator_flags2=["-Wno-WIDTHTRUNC"], + v_flags2=["+define+T_FUNC_WIDE_OUT_NOINL +define+TEST_NOINLINE t/t_func_wide_out_c.cpp"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fuzz_always_bad.pl b/test_regress/t/t_fuzz_always_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_fuzz_always_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_fuzz_always_bad.py b/test_regress/t/t_fuzz_always_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_fuzz_always_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fuzz_eof_bad.pl b/test_regress/t/t_fuzz_eof_bad.pl deleted file mode 100755 index 3be843059..000000000 --- a/test_regress/t/t_fuzz_eof_bad.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_fuzz_eof_bad.py b/test_regress/t/t_fuzz_eof_bad.py new file mode 100755 index 000000000..d14db8ce3 --- /dev/null +++ b/test_regress/t/t_fuzz_eof_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True) + +test.passes() diff --git a/test_regress/t/t_fuzz_eqne_bad.pl b/test_regress/t/t_fuzz_eqne_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_fuzz_eqne_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_fuzz_eqne_bad.py b/test_regress/t/t_fuzz_eqne_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_fuzz_eqne_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fuzz_genintf_bad.pl b/test_regress/t/t_fuzz_genintf_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_fuzz_genintf_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_fuzz_genintf_bad.py b/test_regress/t/t_fuzz_genintf_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_fuzz_genintf_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fuzz_negwidth_bad.pl b/test_regress/t/t_fuzz_negwidth_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_fuzz_negwidth_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_fuzz_negwidth_bad.py b/test_regress/t/t_fuzz_negwidth_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_fuzz_negwidth_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fuzz_triand_bad.pl b/test_regress/t/t_fuzz_triand_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_fuzz_triand_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_fuzz_triand_bad.py b/test_regress/t/t_fuzz_triand_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_fuzz_triand_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_gantt.pl b/test_regress/t/t_gantt.pl deleted file mode 100755 index d9cc88ff7..000000000 --- a/test_regress/t/t_gantt.pl +++ /dev/null @@ -1,59 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# Test for bin/verilator_gantt, - -scenarios(vlt_all => 1); - -# It doesn't really matter what test -# we use, so long as it runs several cycles, -# enough for the profiling to happen: -top_filename("t/t_gen_alw.v"); - -compile( - v_flags2 => ["--prof-exec"], - # Checks below care about thread count, so use 2 (minimum reasonable) - threads => $Self->{vltmt} ? 2 : 1 - ); - -execute( - all_run_flags => ["+verilator+prof+exec+start+2", - " +verilator+prof+exec+window+2", - " +verilator+prof+exec+file+$Self->{obj_dir}/profile_exec.dat", - " +verilator+prof+vlt+file+$Self->{obj_dir}/profile.vlt", - ], - ); - -# For now, verilator_gantt still reads from STDIN -# (probably it should take a file, gantt.dat like verilator_profcfunc) -# The profiling data still goes direct to the runtime's STDOUT -# (maybe that should go to a separate file - gantt.dat?) -run(cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator_gantt", - "$Self->{obj_dir}/profile_exec.dat", - "--vcd $Self->{obj_dir}/profile_exec.vcd", - "| tee $Self->{obj_dir}/gantt.log"], - ); - -if ($Self->{vltmt}) { - file_grep("$Self->{obj_dir}/gantt.log", qr/Total threads += 2/); - file_grep("$Self->{obj_dir}/gantt.log", qr/Total mtasks += 7/); - # Predicted thread utilization should be less than 100% - file_grep_not("$Self->{obj_dir}/gantt.log", qr/Thread utilization =\s*\d\d\d+\.\d+%/); -} else { - file_grep("$Self->{obj_dir}/gantt.log", qr/Total threads += 1/); - file_grep("$Self->{obj_dir}/gantt.log", qr/Total mtasks += 0/); -} -file_grep("$Self->{obj_dir}/gantt.log", qr/\|\s+2\s+\|\s+2\.0+\s+\|\s+eval/); - -# Diff to itself, just to check parsing -vcd_identical("$Self->{obj_dir}/profile_exec.vcd", "$Self->{obj_dir}/profile_exec.vcd"); - -ok(1); -1; diff --git a/test_regress/t/t_gantt.py b/test_regress/t/t_gantt.py new file mode 100755 index 000000000..2217faff4 --- /dev/null +++ b/test_regress/t/t_gantt.py @@ -0,0 +1,52 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +# Test for bin/verilator_gantt, + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_gen_alw.v" # Any, as long as runs a few cycles + +test.compile( + v_flags2=["--prof-exec"], + # Checks below care about thread count, so use 2 (minimum reasonable) + threads=(2 if test.vltmt else 1)) + +test.execute(all_run_flags=[ + "+verilator+prof+exec+start+2", + " +verilator+prof+exec+window+2", + " +verilator+prof+exec+file+" + test.obj_dir + "/profile_exec.dat", + " +verilator+prof+vlt+file+" + test.obj_dir + "/profile.vlt"]) # yapf:disable + +# For now, verilator_gantt still reads from STDIN +# (probably it should take a file, gantt.dat like verilator_profcfunc) +# The profiling data still goes direct to the runtime's STDOUT +# (maybe that should go to a separate file - gantt.dat?) +test.run(cmd=[ + os.environ["VERILATOR_ROOT"] + "/bin/verilator_gantt", test.obj_dir + + "/profile_exec.dat", "--vcd " + test.obj_dir + "/profile_exec.vcd", "| tee " + test.obj_dir + + "/gantt.log" +]) + +if test.vltmt: + test.file_grep(test.obj_dir + "/gantt.log", r'Total threads += 2') + test.file_grep(test.obj_dir + "/gantt.log", r'Total mtasks += 7') + # Predicted thread utilization should be less than 100% + test.file_grep_not(test.obj_dir + "/gantt.log", r'Thread utilization =\s*\d\d\d+\.\d+%') +else: + test.file_grep(test.obj_dir + "/gantt.log", r'Total threads += 1') + test.file_grep(test.obj_dir + "/gantt.log", r'Total mtasks += 0') + +test.file_grep(test.obj_dir + "/gantt.log", r'\|\s+2\s+\|\s+2\.0+\s+\|\s+eval') + +# Diff to itself, just to check parsing +test.vcd_identical(test.obj_dir + "/profile_exec.vcd", test.obj_dir + "/profile_exec.vcd") + +test.passes() diff --git a/test_regress/t/t_gantt_io.pl b/test_regress/t/t_gantt_io.pl deleted file mode 100755 index d3ba7df5c..000000000 --- a/test_regress/t/t_gantt_io.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(dist => 1); - -run(cmd => ["cd $Self->{obj_dir} && $ENV{VERILATOR_ROOT}/bin/verilator_gantt" - . " $Self->{t_dir}/$Self->{name}.dat > gantt.log"], - check_finished => 0); - -files_identical("$Self->{obj_dir}/gantt.log", $Self->{golden_filename}); - -vcd_identical("$Self->{obj_dir}/profile_exec.vcd", "$Self->{t_dir}/$Self->{name}.vcd.out"); - -ok(1); -1; diff --git a/test_regress/t/t_gantt_io.py b/test_regress/t/t_gantt_io.py new file mode 100755 index 000000000..03f00fd52 --- /dev/null +++ b/test_regress/t/t_gantt_io.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +test.run(cmd=[ + "cd " + test.obj_dir + " && " + os.environ["VERILATOR_ROOT"] + "/bin/verilator_gantt" + " " + + test.t_dir + "/" + test.name + ".dat > gantt.log" +], + check_finished=False) + +test.files_identical(test.obj_dir + "/gantt.log", test.golden_filename) +test.vcd_identical(test.obj_dir + "/profile_exec.vcd", test.t_dir + "/" + test.name + ".vcd.out") + +test.passes() diff --git a/test_regress/t/t_gantt_io_arm.pl b/test_regress/t/t_gantt_io_arm.pl deleted file mode 100755 index 7eac146d9..000000000 --- a/test_regress/t/t_gantt_io_arm.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(dist => 1); - -run(cmd => ["cd $Self->{obj_dir} && $ENV{VERILATOR_ROOT}/bin/verilator_gantt" - . " $Self->{t_dir}/$Self->{name}.dat > gantt.log"], - check_finished => 0); - -files_identical("$Self->{obj_dir}/gantt.log", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_gantt_io_arm.py b/test_regress/t/t_gantt_io_arm.py new file mode 100755 index 000000000..99cb09f47 --- /dev/null +++ b/test_regress/t/t_gantt_io_arm.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +test.run(cmd=[ + "cd " + test.obj_dir + " && " + os.environ["VERILATOR_ROOT"] + "/bin/verilator_gantt" + " " + + test.t_dir + "/" + test.name + ".dat > gantt.log" +], + check_finished=False) + +test.files_identical(test.obj_dir + "/gantt.log", test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_gantt_io_noproc.pl b/test_regress/t/t_gantt_io_noproc.pl deleted file mode 100755 index f3011e1ff..000000000 --- a/test_regress/t/t_gantt_io_noproc.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(dist => 1); - -run(cmd => ["cd $Self->{obj_dir} && $ENV{VERILATOR_ROOT}/bin/verilator_gantt" - . " --no-vcd $Self->{t_dir}/$Self->{name}.dat > gantt.log"], - check_finished => 0); - -files_identical("$Self->{obj_dir}/gantt.log", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_gantt_io_noproc.py b/test_regress/t/t_gantt_io_noproc.py new file mode 100755 index 000000000..d5270ebae --- /dev/null +++ b/test_regress/t/t_gantt_io_noproc.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +test.run(cmd=[ + "cd " + test.obj_dir + " && " + os.environ["VERILATOR_ROOT"] + "/bin/verilator_gantt" + + " --no-vcd", test.t_dir + "/" + test.name + ".dat > gantt.log" +], + check_finished=False) + +test.files_identical(test.obj_dir + "/gantt.log", test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_gantt_two.cpp b/test_regress/t/t_gantt_two.cpp index 50a30b88b..484fd4072 100644 --- a/test_regress/t/t_gantt_two.cpp +++ b/test_regress/t/t_gantt_two.cpp @@ -16,7 +16,7 @@ int main(int argc, char** argv) { srand48(5); const std::unique_ptr contextp{new VerilatedContext}; - // VL_USE_THREADS define is set in t_gantt_two.pl + // VL_USE_THREADS define is set in t_gantt_two.py contextp->threads(TEST_USE_THREADS); contextp->debug(0); contextp->commandArgs(argc, argv); diff --git a/test_regress/t/t_gantt_two.pl b/test_regress/t/t_gantt_two.pl deleted file mode 100755 index 2aa8a4670..000000000 --- a/test_regress/t/t_gantt_two.pl +++ /dev/null @@ -1,62 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# Test for bin/verilator_gantt, - -scenarios(vlt_all => 1); - -# It doesn't really matter what test -# we use, so long as it runs several cycles, -# enough for the profiling to happen: -top_filename("t/t_gen_alw.v"); - -my $threads_num = $Self->{vltmt} ? 2 : 1; - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ["--prof-exec --exe $Self->{t_dir}/$Self->{name}.cpp"], - # Checks below care about thread count, so use 2 (minimum reasonable) - threads => $threads_num, - make_flags => "CPPFLAGS_ADD=\"-DVL_NO_LEGACY -DTEST_USE_THREADS=$threads_num\"", - ); - -execute( - all_run_flags => ["+verilator+prof+exec+start+4", - " +verilator+prof+exec+window+4", - " +verilator+prof+exec+file+$Self->{obj_dir}/profile_exec.dat", - " +verilator+prof+vlt+file+$Self->{obj_dir}/profile.vlt", - ], - ); - -# For now, verilator_gantt still reads from STDIN -# (probably it should take a file, gantt.dat like verilator_profcfunc) -# The profiling data still goes direct to the runtime's STDOUT -# (maybe that should go to a separate file - gantt.dat?) -run(cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator_gantt", - "$Self->{obj_dir}/profile_exec.dat", - "--vcd $Self->{obj_dir}/profile_exec.vcd", - "| tee $Self->{obj_dir}/gantt.log"], - ); - -if ($Self->{vltmt}) { - file_grep("$Self->{obj_dir}/gantt.log", qr/Total threads += 2/); - file_grep("$Self->{obj_dir}/gantt.log", qr/Total mtasks += 7/); -} else { - file_grep("$Self->{obj_dir}/gantt.log", qr/Total threads += 1/); - file_grep("$Self->{obj_dir}/gantt.log", qr/Total mtasks += 0/); -} -file_grep("$Self->{obj_dir}/gantt.log", qr/\|\s+4\s+\|\s+4\.0+\s+\|\s+eval/); - -# Diff to itself, just to check parsing -vcd_identical("$Self->{obj_dir}/profile_exec.vcd", "$Self->{obj_dir}/profile_exec.vcd"); - -ok(1); -1; diff --git a/test_regress/t/t_gantt_two.py b/test_regress/t/t_gantt_two.py new file mode 100755 index 000000000..e9a61e566 --- /dev/null +++ b/test_regress/t/t_gantt_two.py @@ -0,0 +1,55 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +# Test for bin/verilator_gantt, + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_gen_alw.v" # Any, as long as runs a few cycles + +threads_num = (2 if test.vltmt else 1) + +test.compile( + make_top_shell=False, + make_main=False, + v_flags2=["--prof-exec --exe", test.pli_filename], + # Checks below care about thread count, so use 2 (minimum reasonable) + threads=threads_num, + make_flags=["CPPFLAGS_ADD=\"-DVL_NO_LEGACY -DTEST_USE_THREADS=" + str(threads_num) + "\""]) + +test.execute(all_run_flags=[ + "+verilator+prof+exec+start+4", + " +verilator+prof+exec+window+4", + " +verilator+prof+exec+file+" + test.obj_dir + "/profile_exec.dat", + " +verilator+prof+vlt+file+" + test.obj_dir + "/profile.vlt"]) # yapf:disable + +# For now, verilator_gantt still reads from STDIN +# (probably it should take a file, gantt.dat like verilator_profcfunc) +# The profiling data still goes direct to the runtime's STDOUT +# (maybe that should go to a separate file - gantt.dat?) +test.run(cmd=[ + os.environ["VERILATOR_ROOT"] + "/bin/verilator_gantt", + test.obj_dir + "/profile_exec.dat", + "--vcd " + test.obj_dir + "/profile_exec.vcd", + "| tee " + test.obj_dir + "/gantt.log"]) # yapf:disable + +if test.vltmt: + test.file_grep(test.obj_dir + "/gantt.log", r'Total threads += 2') + test.file_grep(test.obj_dir + "/gantt.log", r'Total mtasks += 7') +else: + test.file_grep(test.obj_dir + "/gantt.log", r'Total threads += 1') + test.file_grep(test.obj_dir + "/gantt.log", r'Total mtasks += 0') + +test.file_grep(test.obj_dir + "/gantt.log", r'\|\s+4\s+\|\s+4\.0+\s+\|\s+eval') + +# Diff to itself, just to check parsing +test.vcd_identical(test.obj_dir + "/profile_exec.vcd", test.obj_dir + "/profile_exec.vcd") + +test.passes() diff --git a/test_regress/t/t_gate_array.pl b/test_regress/t/t_gate_array.pl deleted file mode 100755 index fdc76316a..000000000 --- a/test_regress/t/t_gate_array.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_gate_array.py b/test_regress/t/t_gate_array.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_gate_array.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gate_basic.pl b/test_regress/t/t_gate_basic.pl deleted file mode 100755 index 6e263990d..000000000 --- a/test_regress/t/t_gate_basic.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--no-timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_gate_basic.py b/test_regress/t/t_gate_basic.py new file mode 100755 index 000000000..e5667d0d0 --- /dev/null +++ b/test_regress/t/t_gate_basic.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--no-timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gate_basic_timing.pl b/test_regress/t/t_gate_basic_timing.pl deleted file mode 100755 index 96d8dc59c..000000000 --- a/test_regress/t/t_gate_basic_timing.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -$Self->{main_time_multiplier} = 10e-7 / 10e-9; - -top_filename("t/t_gate_basic.v"); - -compile( - timing_loop => 1, - verilator_flags2 => ["--timing --timescale 10ns/1ns -Wno-RISEFALLDLY"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_gate_basic_timing.py b/test_regress/t/t_gate_basic_timing.py new file mode 100755 index 000000000..cfcba0b42 --- /dev/null +++ b/test_regress/t/t_gate_basic_timing.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_gate_basic.v" +test.main_time_multiplier = 10e-7 / 10e-9 + +test.compile(timing_loop=True, verilator_flags2=["--timing --timescale 10ns/1ns -Wno-RISEFALLDLY"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gate_chained.pl b/test_regress/t/t_gate_chained.pl deleted file mode 100755 index d218e3a12..000000000 --- a/test_regress/t/t_gate_chained.pl +++ /dev/null @@ -1,59 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -use IO::File; - -scenarios(simulator => 1); - -sub gen { - my $filename = shift; - - my $fh = IO::File->new(">$filename"); - $fh->print("// Generated by t_gate_chained.pl\n"); - $fh->print("module t (clk,i,sel,o);\n"); - $fh->print(" input clk;\n"); - $fh->print(" input [63:0] i;\n"); - $fh->print(" input [15:0] sel;\n"); - $fh->print(" output [63:0] o;\n"); - $fh->print("\n"); - my $prev = "i"; - my $n = 9000; - for (my $i = 1; $i < $n; ++$i) { - $fh->printf(" wire [63:0] ass%04x = (sel == 16'h%04x) ? 64'h0 : $prev;\n", $i, $i); - $prev = sprintf("ass%04x", $i); - } - - $fh->print("\n"); - $fh->print(" wire [63:0] o = $prev;\n"); - - $fh->print("\n"); - $fh->print(" always @ (posedge clk) begin\n"); - $fh->print(' $write("*-* All Finished *-*\n");', "\n"); - $fh->print(' $finish;', "\n"); - $fh->print(" end\n"); - $fh->print("endmodule\n"); -} - -top_filename("$Self->{obj_dir}/t_gate_chained.v"); - -gen($Self->{top_filename}); - -compile( - verilator_flags2 => ["--stats --x-assign fast --x-initial fast", - "-Wno-UNOPTTHREADS -fno-dfg"], - ); - -execute( - ); - -# Must be <<9000 above to prove this worked -file_grep($Self->{stats}, qr/Optimizations, Gate sigs deleted\s+(\d+)/, 8575); - -ok(1); -1; diff --git a/test_regress/t/t_gate_chained.py b/test_regress/t/t_gate_chained.py new file mode 100755 index 000000000..37a8dd6d4 --- /dev/null +++ b/test_regress/t/t_gate_chained.py @@ -0,0 +1,53 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = test.obj_dir + "/t_gate_chained.v" + + +def gen(filename): + with open(filename, 'w', encoding="utf8") as fh: + fh.write("// Generated by t_gate_chained.py\n") + fh.write("module t (clk,i,sel,o);\n") + fh.write(" input clk;\n") + fh.write(" input [63:0] i;\n") + fh.write(" input [15:0] sel;\n") + fh.write(" output [63:0] o;\n") + fh.write("\n") + prev = "i" + n = 9000 + for i in range(1, n): + fh.write( + (" wire [63:0] ass%04x = (sel == 16'h%04x) ? 64'h0 : " + prev + ";\n") % (i, i)) + prev = "ass%04x" % i + + fh.write("\n") + fh.write(" wire [63:0] o = " + prev + ";\n") + + fh.write("\n") + fh.write(" always @ (posedge clk) begin\n") + fh.write(' $write("*-* All Finished *-*\\n");' + "\n") + fh.write(' $finish;' + "\n") + fh.write(" end\n") + fh.write("endmodule\n") + + +gen(test.top_filename) + +test.compile( + verilator_flags2=["--stats --x-assign fast --x-initial fast", "-Wno-UNOPTTHREADS -fno-dfg"]) + +test.execute() + +# Must be <<9000 above to prove this worked +test.file_grep(test.stats, r'Optimizations, Gate sigs deleted\s+(\d+)', 8575) + +test.passes() diff --git a/test_regress/t/t_gate_delay_unsup.pl b/test_regress/t/t_gate_delay_unsup.pl deleted file mode 100755 index ecb0ab324..000000000 --- a/test_regress/t/t_gate_delay_unsup.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -top_filename("t/t_gate_basic.v"); - -lint( - verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME -Wno-UNUSED --timing"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gate_delay_unsup.py b/test_regress/t/t_gate_delay_unsup.py new file mode 100755 index 000000000..3e0229f9a --- /dev/null +++ b/test_regress/t/t_gate_delay_unsup.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_gate_basic.v" + +test.lint(verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME -Wno-UNUSED --timing"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_gate_delref.pl b/test_regress/t/t_gate_delref.pl deleted file mode 100755 index 2eb6a63bc..000000000 --- a/test_regress/t/t_gate_delref.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_gate_delref.py b/test_regress/t/t_gate_delref.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_gate_delref.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_gate_elim.pl b/test_regress/t/t_gate_elim.pl deleted file mode 100755 index fdc76316a..000000000 --- a/test_regress/t/t_gate_elim.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_gate_elim.py b/test_regress/t/t_gate_elim.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_gate_elim.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gate_fdup.pl b/test_regress/t/t_gate_fdup.pl deleted file mode 100755 index d2f13f637..000000000 --- a/test_regress/t/t_gate_fdup.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -lint( - verilator_flags2 => ["--language 1364-2005"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_gate_fdup.py b/test_regress/t/t_gate_fdup.py new file mode 100755 index 000000000..648df1761 --- /dev/null +++ b/test_regress/t/t_gate_fdup.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.lint(verilator_flags2=["--language 1364-2005"]) + +test.passes() diff --git a/test_regress/t/t_gate_implicit.pl b/test_regress/t/t_gate_implicit.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_gate_implicit.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_gate_implicit.py b/test_regress/t/t_gate_implicit.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_gate_implicit.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gate_loop.pl b/test_regress/t/t_gate_loop.pl deleted file mode 100755 index 1d9caab1c..000000000 --- a/test_regress/t/t_gate_loop.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Geza Lore. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["-Wno-UNOPTFLAT"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_gate_loop.py b/test_regress/t/t_gate_loop.py new file mode 100755 index 000000000..8e15ef2eb --- /dev/null +++ b/test_regress/t/t_gate_loop.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["-Wno-UNOPTFLAT"]) + +test.passes() diff --git a/test_regress/t/t_gate_lvalue_const.pl b/test_regress/t/t_gate_lvalue_const.pl deleted file mode 100755 index 56363dab6..000000000 --- a/test_regress/t/t_gate_lvalue_const.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_gate_lvalue_const.py b/test_regress/t/t_gate_lvalue_const.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_gate_lvalue_const.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gate_opt.pl b/test_regress/t/t_gate_opt.pl deleted file mode 100755 index 9a4371ebf..000000000 --- a/test_regress/t/t_gate_opt.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile(); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_gate_opt.py b/test_regress/t/t_gate_opt.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_gate_opt.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gate_ormux.pl b/test_regress/t/t_gate_ormux.pl deleted file mode 100755 index 4cef31d51..000000000 --- a/test_regress/t/t_gate_ormux.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -$Self->{cycles} = ($Self->{benchmark} ? 100_000_000 : 100); -$Self->{sim_time} = $Self->{cycles} * 10 + 1000; - -compile( - v_flags2 => ["+define+SIM_CYCLES=$Self->{cycles}",], - verilator_flags2 => ["-Wno-UNOPTTHREADS", "--stats", "-fno-dfg"], - ); - -if ($Self->{vlt}) { - file_grep($Self->{stats}, qr/Optimizations, Const bit op reduction\s+(\d+)/, 1058); -} - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_gate_ormux.py b/test_regress/t/t_gate_ormux.py new file mode 100755 index 000000000..3fb514208 --- /dev/null +++ b/test_regress/t/t_gate_ormux.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.cycles = (100000000 if test.benchmark else 100) +test.sim_time = test.cycles * 10 + 1000 + +test.compile(v_flags2=["+define+SIM_CYCLES=" + str(test.cycles)], + verilator_flags2=["-Wno-UNOPTTHREADS", "--stats", "-fno-dfg"]) + +if test.vlt: + test.file_grep(test.stats, r'Optimizations, Const bit op reduction\s+(\d+)', 1058) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gate_primitives_implicit_net.pl b/test_regress/t/t_gate_primitives_implicit_net.pl deleted file mode 100755 index 7af9753a1..000000000 --- a/test_regress/t/t_gate_primitives_implicit_net.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["-Wno-fatal --no-skip-identical"], - expect_filename => $Self->{golden_filename}, - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_gate_primitives_implicit_net.py b/test_regress/t/t_gate_primitives_implicit_net.py new file mode 100755 index 000000000..30e8dbdb0 --- /dev/null +++ b/test_regress/t/t_gate_primitives_implicit_net.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["-Wno-fatal --no-skip-identical"], + expect_filename=test.golden_filename) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gate_strength.pl b/test_regress/t/t_gate_strength.pl deleted file mode 100755 index dd8b670e0..000000000 --- a/test_regress/t/t_gate_strength.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['-bbox-unsup'], - ); - -ok(1); -1; diff --git a/test_regress/t/t_gate_strength.py b/test_regress/t/t_gate_strength.py new file mode 100755 index 000000000..e838b9b8f --- /dev/null +++ b/test_regress/t/t_gate_strength.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['-bbox-unsup']) + +test.passes() diff --git a/test_regress/t/t_gate_tree.pl b/test_regress/t/t_gate_tree.pl deleted file mode 100755 index a6ec6889c..000000000 --- a/test_regress/t/t_gate_tree.pl +++ /dev/null @@ -1,129 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -use IO::File; -#use Data::Dumper; -use strict; -use vars qw($Self); - -scenarios(simulator => 1); - -my $width = 64 * ($ENV{VERILATOR_TEST_WIDTH} || 4); -my $vars = 64; - -$Self->{cycles} = ($Self->{benchmark} ? 1_000_000 : 100); -$Self->{sim_time} = $Self->{cycles} * 10 + 1000; - -sub gen { - my $filename = shift; - - my $fh = IO::File->new(">$filename"); - $fh->print("// Generated by t_gate_tree.pl\n"); - $fh->print("module t (clk);\n"); - $fh->print(" input clk;\n"); - $fh->print("\n"); - $fh->print(" integer cyc=0;\n"); - $fh->print(" reg reset;\n"); - $fh->print("\n"); - - my %tree; - my $fanin = 8; - my $stages = int(log($vars) / log($fanin) + 0.99999) + 1; - my $result = 0; - for (my $n = 0; $n < $vars; $n++) { - $result += ($n || 1); - $tree{0}{$n}{$n} = 1; - my $nl = $n; - for (my $stage=1; $stage < $stages; $stage++) { - my $lastn = $nl; - $nl = int($nl / $fanin); - $tree{$stage}{$nl}{$lastn} = 1; - } - } - #print Dumper(\%tree); - - $fh->print("\n"); - my $workingset = 0; - foreach my $stage (sort { $a <=> $b} keys %tree) { - foreach my $n (sort { $a <=> $b} keys %{$tree{$stage}}) { - $fh->print( " reg [" . ($width - 1) . ":0] v${stage}_${n};\n"); - $workingset += int($width/8 + 7); - } - } - - $fh->print("\n"); - $fh->print(" always @ (posedge clk) begin\n"); - $fh->print(" cyc <= cyc + 1;\n"); - $fh->print("`ifdef TEST_VERBOSE\n"); - $fh->print(" \$write(\"[%0t] rst=%0x v0_0=%0x v1_0=%0x result=%0x\\n\"" - .", \$time, reset, v0_0, v1_0, v" . ($stages - 1) . "_0);\n"); - $fh->print("`endif\n"); - $fh->print(" if (cyc==0) begin\n"); - $fh->print(" reset <= 1;\n"); - $fh->print(" end\n"); - $fh->print(" else if (cyc==10) begin\n"); - $fh->print(" reset <= 0;\n"); - $fh->print(" end\n"); - $fh->print("`ifndef SIM_CYCLES\n"); - $fh->print(" `define SIM_CYCLES 99\n"); - $fh->print("`endif\n"); - $fh->print(" else if (cyc==`SIM_CYCLES) begin\n"); - $fh->print(" if (v" . ($stages - 1) . "_0 != ${width}'d${result}) \$stop;\n"); - $fh->print(" \$write(\"VARS=${vars} WIDTH=${width}" - ." WORKINGSET=" . (int($workingset / 1024)) . "KB\\n\");\n"); - $fh->print(' $write("*-* All Finished *-*\n");', "\n"); - $fh->print(' $finish;', "\n"); - $fh->print(" end\n"); - $fh->print(" end\n"); - - $fh->print("\n"); - for (my $n=0; $n<$vars; $n++) { - $fh->print(" always @ (posedge clk)" - . " v0_${n} <= reset ? ${width}'d" . (${n} || 1) . " : v0_" - . ((int($n / $fanin) * $fanin) + (($n + 1) % $fanin)) . ";\n"); - } - - foreach my $stage (sort {$a<=>$b} keys %tree) { - next if $stage == 0; - $fh->print("\n"); - foreach my $n (sort {$a<=>$b} keys %{$tree{$stage}}) { - $fh->print(" always @ (posedge clk)" - . " v${stage}_${n} <="); - my $op = ""; - foreach my $ni (sort {$a<=>$b} keys %{$tree{$stage}{$n}}) { - $fh->print($op . " v" . (${stage} - 1) . "_${ni}"); - $op = " +"; - } - $fh->print(";\n"); - } - } - - $fh->print("endmodule\n"); -} - -top_filename("$Self->{obj_dir}/t_gate_tree.v"); - -gen($Self->{top_filename}); - -compile( - v_flags2 => ["+define+SIM_CYCLES=$Self->{cycles}",], - verilator_flags2=>["--stats --x-assign fast --x-initial fast", - "-Wno-UNOPTTHREADS"], - ); - -execute( - all_run_flags => ["+verilator+prof+exec+start+100", - " +verilator+prof+exec+window+2", - " +verilator+prof+exec+file+$Self->{obj_dir}/profile_exec.dat", - " +verilator+prof+vlt+file+$Self->{obj_dir}/profile.vlt", - ], - ); - -ok(1); -1; diff --git a/test_regress/t/t_gate_tree.py b/test_regress/t/t_gate_tree.py new file mode 100755 index 000000000..49fa92260 --- /dev/null +++ b/test_regress/t/t_gate_tree.py @@ -0,0 +1,121 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import collections +import math + +test.scenarios('simulator') +test.top_filename = test.obj_dir + "/t_gate_tree.v" +test.cycles = (1000000 if test.benchmark else 100) +test.sim_time = test.cycles * 10 + 1000 + +width = 64 * int(test.getenv_def("VERILATOR_TEST_WIDTH", "4")) +nvars = 64 + + +def gen(filename): + with open(filename, 'w', encoding="utf8") as fh: + fh.write("// Generated by t_gate_tree.py\n") + fh.write("module t (clk);\n") + fh.write(" input clk;\n") + fh.write("\n") + fh.write(" integer cyc=0;\n") + fh.write(" reg reset;\n") + fh.write("\n") + + tree = collections.defaultdict(dict) + fanin = 8 + stages = int(math.log(nvars) / math.log(fanin) + 0.99999) + 1 + result = 0 + for n in range(0, nvars): + result += max(n, 1) + if 0 not in tree: + tree[0] = {} + if n not in tree[0]: + tree[0][n] = {} + tree[0][n][n] = True + nl = n + for stage in range(1, stages): + lastn = nl + nl = int(nl / fanin) + if stage not in tree: + tree[stage] = {} + if nl not in tree[stage]: + tree[stage][nl] = {} + tree[stage][nl][lastn] = True + + # pprint(tree) + + fh.write("\n") + workingset = 0 + for stage in sorted(tree.keys()): + for n in sorted(tree[stage].keys()): + fh.write(" reg [" + str(width - 1) + ":0] v" + str(stage) + "_" + str(n) + ";\n") + workingset += int(width / 8 + 7) + + fh.write("\n") + fh.write(" always @ (posedge clk) begin\n") + fh.write(" cyc <= cyc + 1;\n") + fh.write("`ifdef TEST_VERBOSE\n") + fh.write(" $write(\"[%0t] rst=%0x v0_0=%0x v1_0=%0x result=%0x\\n\"" + ", $time, reset, v0_0, v1_0, v" + str(stages - 1) + "_0);\n") + fh.write("`endif\n") + fh.write(" if (cyc==0) begin\n") + fh.write(" reset <= 1;\n") + fh.write(" end\n") + fh.write(" else if (cyc==10) begin\n") + fh.write(" reset <= 0;\n") + fh.write(" end\n") + fh.write("`ifndef SIM_CYCLES\n") + fh.write(" `define SIM_CYCLES 99\n") + fh.write("`endif\n") + fh.write(" else if (cyc==`SIM_CYCLES) begin\n") + fh.write(" if (v" + str(stages - 1) + "_0 != " + str(width) + "'d" + str(result) + + ") $stop;\n") + fh.write(" $write(\"VARS=" + str(nvars) + " WIDTH=" + str(width) + " WORKINGSET=" + + str(int(workingset / 1024)) + "KB\\n\");\n") + fh.write(' $write("*-* All Finished *-*\\n");' + "\n") + fh.write(' $finish;' + "\n") + fh.write(" end\n") + fh.write(" end\n") + + fh.write("\n") + for n in range(0, nvars): + fh.write(" always @ (posedge clk)" + " v0_" + str(n) + " <= reset ? " + str(width) + + "'d" + str(max(n, 1)) + " : v0_" + str((int(n / fanin) * fanin) + + ((n + 1) % fanin)) + ";\n") + + for stage in sorted(tree.keys()): + if stage == 0: + continue + fh.write("\n") + for n in sorted(tree[stage].keys()): + fh.write(" always @ (posedge clk) v" + str(stage) + "_" + str(n) + " <=") + op = "" + for ni in sorted(tree[stage][n].keys()): + fh.write(op + " v" + str(stage - 1) + "_" + str(ni)) + op = " +" + fh.write(";\n") + + fh.write("endmodule\n") + + +gen(test.top_filename) + +test.compile(v_flags2=["+define+SIM_CYCLES=" + str(test.cycles)], + verilator_flags2=["--stats --x-assign fast --x-initial fast", "-Wno-UNOPTTHREADS"]) + +test.execute(all_run_flags=[ + "+verilator+prof+exec+start+100", + " +verilator+prof+exec+window+2", + " +verilator+prof+exec+file+" + test.obj_dir + "/profile_exec.dat", + " +verilator+prof+vlt+file+" + test.obj_dir + "/profile.vlt"]) # yapf:disable + +test.passes() diff --git a/test_regress/t/t_gate_unsup.pl b/test_regress/t/t_gate_unsup.pl deleted file mode 100755 index f32089412..000000000 --- a/test_regress/t/t_gate_unsup.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - # Unsupported: UDP Tables - verilator_flags2 => ["--lint-only --bbox-unsup"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_gate_unsup.py b/test_regress/t/t_gate_unsup.py new file mode 100755 index 000000000..fcdfcc6f4 --- /dev/null +++ b/test_regress/t/t_gate_unsup.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint( + # Unsupported: UDP Tables + verilator_flags2=["--lint-only --bbox-unsup"]) + +test.passes() diff --git a/test_regress/t/t_gated_clk_1.pl b/test_regress/t/t_gated_clk_1.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_gated_clk_1.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_gated_clk_1.py b/test_regress/t/t_gated_clk_1.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_gated_clk_1.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gen_alw.pl b/test_regress/t/t_gen_alw.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_gen_alw.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_alw.py b/test_regress/t/t_gen_alw.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_gen_alw.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gen_assign.pl b/test_regress/t/t_gen_assign.pl deleted file mode 100755 index 7c611fc4c..000000000 --- a/test_regress/t/t_gen_assign.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_assign.py b/test_regress/t/t_gen_assign.py new file mode 100755 index 000000000..3527cdb06 --- /dev/null +++ b/test_regress/t/t_gen_assign.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_gen_cond_bitrange.pl b/test_regress/t/t_gen_cond_bitrange.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_gen_cond_bitrange.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_cond_bitrange.py b/test_regress/t/t_gen_cond_bitrange.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_gen_cond_bitrange.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gen_cond_bitrange_bad.pl b/test_regress/t/t_gen_cond_bitrange_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_gen_cond_bitrange_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_cond_bitrange_bad.py b/test_regress/t/t_gen_cond_bitrange_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_gen_cond_bitrange_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_gen_cond_const.pl b/test_regress/t/t_gen_cond_const.pl deleted file mode 100755 index 328005d82..000000000 --- a/test_regress/t/t_gen_cond_const.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--language 1364-2001"] - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_cond_const.py b/test_regress/t/t_gen_cond_const.py new file mode 100755 index 000000000..4aa451103 --- /dev/null +++ b/test_regress/t/t_gen_cond_const.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--language 1364-2001"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gen_defparam.pl b/test_regress/t/t_gen_defparam.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_gen_defparam.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_defparam.py b/test_regress/t/t_gen_defparam.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_gen_defparam.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gen_defparam_multi.pl b/test_regress/t/t_gen_defparam_multi.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_gen_defparam_multi.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_defparam_multi.py b/test_regress/t/t_gen_defparam_multi.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_gen_defparam_multi.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_gen_defparam_nfound_bad.pl b/test_regress/t/t_gen_defparam_nfound_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_gen_defparam_nfound_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_defparam_nfound_bad.py b/test_regress/t/t_gen_defparam_nfound_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_gen_defparam_nfound_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_gen_div0.pl b/test_regress/t/t_gen_div0.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_gen_div0.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_div0.py b/test_regress/t/t_gen_div0.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_gen_div0.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gen_for.pl b/test_regress/t/t_gen_for.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_gen_for.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_for.py b/test_regress/t/t_gen_for.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_gen_for.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gen_for0.pl b/test_regress/t/t_gen_for0.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_gen_for0.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_for0.py b/test_regress/t/t_gen_for0.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_gen_for0.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gen_for1.pl b/test_regress/t/t_gen_for1.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_gen_for1.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_for1.py b/test_regress/t/t_gen_for1.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_gen_for1.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gen_for_interface.pl b/test_regress/t/t_gen_for_interface.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_gen_for_interface.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_for_interface.py b/test_regress/t/t_gen_for_interface.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_gen_for_interface.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gen_for_overlap.pl b/test_regress/t/t_gen_for_overlap.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_gen_for_overlap.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_for_overlap.py b/test_regress/t/t_gen_for_overlap.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_gen_for_overlap.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gen_for_shuffle.pl b/test_regress/t/t_gen_for_shuffle.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_gen_for_shuffle.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_for_shuffle.py b/test_regress/t/t_gen_for_shuffle.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_gen_for_shuffle.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gen_forif.pl b/test_regress/t/t_gen_forif.pl deleted file mode 100755 index a377b9bbc..000000000 --- a/test_regress/t/t_gen_forif.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - nc_flags2 => ['+access+r'], - verilator_flags2 => ["--no-timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_forif.py b/test_regress/t/t_gen_forif.py new file mode 100755 index 000000000..c8913bea4 --- /dev/null +++ b/test_regress/t/t_gen_forif.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(nc_flags2=['+access+r'], verilator_flags2=["--no-timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gen_genblk.pl b/test_regress/t/t_gen_genblk.pl deleted file mode 100755 index e86489964..000000000 --- a/test_regress/t/t_gen_genblk.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -$Self->{sim_time} = 11000; - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_genblk.py b/test_regress/t/t_gen_genblk.py new file mode 100755 index 000000000..b89e72146 --- /dev/null +++ b/test_regress/t/t_gen_genblk.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.sim_time = 11000 + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_gen_genblk_noinl.pl b/test_regress/t/t_gen_genblk_noinl.pl deleted file mode 100755 index ef537cd4d..000000000 --- a/test_regress/t/t_gen_genblk_noinl.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -top_filename("t_gen_genblk.v"); -golden_filename("t/t_gen_genblk.out"); - -scenarios(simulator => 1); - -$Self->{sim_time} = 11000; - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_genblk_noinl.py b/test_regress/t/t_gen_genblk_noinl.py new file mode 100755 index 000000000..0b6136eb6 --- /dev/null +++ b/test_regress/t/t_gen_genblk_noinl.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t_gen_genblk.v" +test.golden_filename = "t/t_gen_genblk.out" +test.sim_time = 11000 + +test.compile(v_flags2=["-fno-inline"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_gen_if.pl b/test_regress/t/t_gen_if.pl deleted file mode 100755 index 1f3b9a577..000000000 --- a/test_regress/t/t_gen_if.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_if.py b/test_regress/t/t_gen_if.py new file mode 100755 index 000000000..3527cdb06 --- /dev/null +++ b/test_regress/t/t_gen_if.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_gen_ifelse.pl b/test_regress/t/t_gen_ifelse.pl deleted file mode 100755 index 6e1338f8e..000000000 --- a/test_regress/t/t_gen_ifelse.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_ifelse.py b/test_regress/t/t_gen_ifelse.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_gen_ifelse.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gen_inc.pl b/test_regress/t/t_gen_inc.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_gen_inc.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_inc.py b/test_regress/t/t_gen_inc.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_gen_inc.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gen_index.pl b/test_regress/t/t_gen_index.pl deleted file mode 100755 index 6d131b585..000000000 --- a/test_regress/t/t_gen_index.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -# Compile time only test -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_index.py b/test_regress/t/t_gen_index.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_gen_index.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_gen_intdot.pl b/test_regress/t/t_gen_intdot.pl deleted file mode 100755 index 4fcbd9558..000000000 --- a/test_regress/t/t_gen_intdot.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--no-timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_intdot.py b/test_regress/t/t_gen_intdot.py new file mode 100755 index 000000000..e5667d0d0 --- /dev/null +++ b/test_regress/t/t_gen_intdot.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--no-timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gen_intdot2.pl b/test_regress/t/t_gen_intdot2.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_gen_intdot2.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_intdot2.py b/test_regress/t/t_gen_intdot2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_gen_intdot2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gen_local.pl b/test_regress/t/t_gen_local.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_gen_local.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_local.py b/test_regress/t/t_gen_local.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_gen_local.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gen_lsb.pl b/test_regress/t/t_gen_lsb.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_gen_lsb.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_lsb.py b/test_regress/t/t_gen_lsb.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_gen_lsb.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gen_mislevel.pl b/test_regress/t/t_gen_mislevel.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_gen_mislevel.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_mislevel.py b/test_regress/t/t_gen_mislevel.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_gen_mislevel.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gen_missing.pl b/test_regress/t/t_gen_missing.pl deleted file mode 100755 index 58978643b..000000000 --- a/test_regress/t/t_gen_missing.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ['+define+T_GEN_MISSING'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_missing.py b/test_regress/t/t_gen_missing.py new file mode 100755 index 000000000..1421dc553 --- /dev/null +++ b/test_regress/t/t_gen_missing.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=['+define+T_GEN_MISSING']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gen_missing_bad.pl b/test_regress/t/t_gen_missing_bad.pl deleted file mode 100755 index 7cd5ea1e5..000000000 --- a/test_regress/t/t_gen_missing_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_gen_missing.v"); - -lint( - v_flags2 => ['+define+T_GEN_MISSING_BAD'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_missing_bad.py b/test_regress/t/t_gen_missing_bad.py new file mode 100755 index 000000000..8be012ec5 --- /dev/null +++ b/test_regress/t/t_gen_missing_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_gen_missing.v" + +test.lint(v_flags2=['+define+T_GEN_MISSING_BAD'], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_gen_missing_bad2.pl b/test_regress/t/t_gen_missing_bad2.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_gen_missing_bad2.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_missing_bad2.py b/test_regress/t/t_gen_missing_bad2.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_gen_missing_bad2.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_gen_nonconst_bad.pl b/test_regress/t/t_gen_nonconst_bad.pl deleted file mode 100755 index d9066a317..000000000 --- a/test_regress/t/t_gen_nonconst_bad.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - v_flags => [], # To avoid -I - v_flags2 => [], # To avoid -I - verilator_flags => ["--lint-only"], # To avoid -I - verilator_flags2 => [], # To avoid -I - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_nonconst_bad.py b/test_regress/t/t_gen_nonconst_bad.py new file mode 100755 index 000000000..a3ece0800 --- /dev/null +++ b/test_regress/t/t_gen_nonconst_bad.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint( + v_flags=[], # To avoid -I + v_flags2=[], # To avoid -I + verilator_flags=["--lint-only"], # To avoid -I + verilator_flags2=[], # To avoid -I + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_gen_self_return.pl b/test_regress/t/t_gen_self_return.pl deleted file mode 100755 index 56363dab6..000000000 --- a/test_regress/t/t_gen_self_return.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_self_return.py b/test_regress/t/t_gen_self_return.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_gen_self_return.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_gen_upscope.pl b/test_regress/t/t_gen_upscope.pl deleted file mode 100755 index 56cc415df..000000000 --- a/test_regress/t/t_gen_upscope.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_upscope.py b/test_regress/t/t_gen_upscope.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_gen_upscope.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_gen_var_bad.pl b/test_regress/t/t_gen_var_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_gen_var_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_gen_var_bad.py b/test_regress/t/t_gen_var_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_gen_var_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_generate_fatal_bad.pl b/test_regress/t/t_generate_fatal_bad.pl deleted file mode 100755 index 27159da5b..000000000 --- a/test_regress/t/t_generate_fatal_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_generate_fatal_bad.py b/test_regress/t/t_generate_fatal_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_generate_fatal_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_genfor_hier.pl b/test_regress/t/t_genfor_hier.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_genfor_hier.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_genfor_hier.py b/test_regress/t/t_genfor_hier.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_genfor_hier.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_genfor_init_o0.pl b/test_regress/t/t_genfor_init_o0.pl deleted file mode 100755 index 60b075c18..000000000 --- a/test_regress/t/t_genfor_init_o0.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ['-O0'], - make_main => 0, - verilator_make_gmake => 0, - ); - -ok(1); -1; diff --git a/test_regress/t/t_genfor_init_o0.py b/test_regress/t/t_genfor_init_o0.py new file mode 100755 index 000000000..3eb087ae6 --- /dev/null +++ b/test_regress/t/t_genfor_init_o0.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['-O0'], make_main=False, verilator_make_gmake=False) + +test.passes() diff --git a/test_regress/t/t_genfor_signed.pl b/test_regress/t/t_genfor_signed.pl deleted file mode 100755 index ba6e69d67..000000000 --- a/test_regress/t/t_genfor_signed.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_genfor_signed.py b/test_regress/t/t_genfor_signed.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_genfor_signed.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_genvar_for_bad.pl b/test_regress/t/t_genvar_for_bad.pl deleted file mode 100755 index 27159da5b..000000000 --- a/test_regress/t/t_genvar_for_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_genvar_for_bad.py b/test_regress/t/t_genvar_for_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_genvar_for_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_genvar_misuse_bad.pl b/test_regress/t/t_genvar_misuse_bad.pl deleted file mode 100755 index 05585a90b..000000000 --- a/test_regress/t/t_genvar_misuse_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - # Should fail, but bug408, Verilator unsupported - fails => !$Self->{vlt}, - # expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_genvar_misuse_bad.py b/test_regress/t/t_genvar_misuse_bad.py new file mode 100755 index 000000000..b7b9dee6a --- /dev/null +++ b/test_regress/t/t_genvar_misuse_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint( + # Should fail, but bug408, Verilator unsupported + # expect_filename = test.golden_filename + fails=not test.vlt) + +test.passes() diff --git a/test_regress/t/t_hier_block.pl b/test_regress/t/t_hier_block.pl deleted file mode 100755 index a0a39a46c..000000000 --- a/test_regress/t/t_hier_block.pl +++ /dev/null @@ -1,41 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. -clean_objs(); - -scenarios(vlt_all => 1); - -# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. -# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. -# So use 6 threads here though it's not optimal in performance, but ok. - -compile( - v_flags2 => ['t/t_hier_block.cpp'], - verilator_flags2 => ['--stats', - '--hierarchical', - '--Wno-TIMESCALEMOD', - '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"' - ], - threads => $Self->{vltmt} ? 6 : 1 - ); - -execute( - ); - -file_grep($Self->{obj_dir} . "/Vsub0/sub0.sv", qr/^\s+\/\/\s+timeprecision\s+(\d+)ps;/m, 1); -file_grep($Self->{obj_dir} . "/Vsub0/sub0.sv", /^module\s+(\S+)\s+/, "sub0"); -file_grep($Self->{obj_dir} . "/Vsub1/sub1.sv", /^module\s+(\S+)\s+/, "sub1"); -file_grep($Self->{obj_dir} . "/Vsub2/sub2.sv", /^module\s+(\S+)\s+/, "sub2"); -file_grep($Self->{stats}, qr/HierBlock,\s+Hierarchical blocks\s+(\d+)/, 14); -file_grep($Self->{run_log_filename}, qr/MACRO:(\S+) is defined/, "cplusplus"); - -ok(1); -1; diff --git a/test_regress/t/t_hier_block.py b/test_regress/t/t_hier_block.py new file mode 100755 index 000000000..c2cac597b --- /dev/null +++ b/test_regress/t/t_hier_block.py @@ -0,0 +1,37 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +# stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. +test.clean_objs() + +# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. +# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. +# So use 6 threads here though it's not optimal in performance, but ok. + +test.compile(v_flags2=['t/t_hier_block.cpp'], + verilator_flags2=[ + '--stats', '--hierarchical', '--Wno-TIMESCALEMOD', '--CFLAGS', + '"-pipe -DCPP_MACRO=cplusplus"' + ], + threads=(6 if test.vltmt else 1)) + +test.execute() + +test.file_grep(test.obj_dir + "/Vsub0/sub0.sv", r'^\s+\/\/\s+timeprecision\s+(\d+)ps;', 1) +test.file_grep(test.obj_dir + "/Vsub0/sub0.sv", r'^module\s+(\S+)\s+', "sub0") +test.file_grep(test.obj_dir + "/Vsub1/sub1.sv", r'^module\s+(\S+)\s+', "sub1") +test.file_grep(test.obj_dir + "/Vsub2/sub2.sv", r'^module\s+(\S+)\s+', "sub2") +test.file_grep(test.stats, r'HierBlock,\s+Hierarchical blocks\s+(\d+)', 14) +test.file_grep(test.run_log_filename, r'MACRO:(\S+) is defined', "cplusplus") + +test.passes() diff --git a/test_regress/t/t_hier_block0_bad.pl b/test_regress/t/t_hier_block0_bad.pl deleted file mode 100755 index 39bf8dbac..000000000 --- a/test_regress/t/t_hier_block0_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - verilator_flags2 => ['--hierarchical'], - expect_filename => $Self->{golden_filename}, -); - -ok(1); -1; diff --git a/test_regress/t/t_hier_block0_bad.py b/test_regress/t/t_hier_block0_bad.py new file mode 100755 index 000000000..c80415ffe --- /dev/null +++ b/test_regress/t/t_hier_block0_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, verilator_flags2=['--hierarchical'], expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_hier_block1_bad.pl b/test_regress/t/t_hier_block1_bad.pl deleted file mode 100755 index 39bf8dbac..000000000 --- a/test_regress/t/t_hier_block1_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - verilator_flags2 => ['--hierarchical'], - expect_filename => $Self->{golden_filename}, -); - -ok(1); -1; diff --git a/test_regress/t/t_hier_block1_bad.py b/test_regress/t/t_hier_block1_bad.py new file mode 100755 index 000000000..c80415ffe --- /dev/null +++ b/test_regress/t/t_hier_block1_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, verilator_flags2=['--hierarchical'], expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_hier_block_cmake.pl b/test_regress/t/t_hier_block_cmake.pl deleted file mode 100755 index 9034257fd..000000000 --- a/test_regress/t/t_hier_block_cmake.pl +++ /dev/null @@ -1,44 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# If a test fails, broken .cmake may disturb the next run -clean_objs(); - -scenarios(simulator => 1); -top_filename("t/t_hier_block.v"); - -my $threads = ($Self->{vltmt} ? '-DTEST_THREADS=6' : '-DTEST_THREADS=1'); - -if (!$Self->have_cmake) { - $Self->skip("Test requires CMake; ignore error since not available or version too old\n"); -} else { - run(logfile => "$Self->{obj_dir}/cmake.log", - cmd => ['cd "' . $Self->{obj_dir} . '" && cmake ' . $Self->{t_dir} . '/t_hier_block_cmake', - "-DCMAKE_PREFIX_PATH=$ENV{VERILATOR_ROOT}", - $threads - ]); - - run(logfile => "$Self->{obj_dir}/build.log", - cmd => ['cd "' . $Self->{obj_dir} . '" && cmake --build', '.', '--', "CXX_FLAGS=$threads"] - ); - - run(logfile => "$Self->{obj_dir}/run.log", - cmd => ['cd "' . $Self->{obj_dir} . '" && ./t_hier_block_cmake', '.'] - ); - my $target_dir = $Self->{obj_dir} . '/CMakeFiles/t_hier_block_cmake.dir/Vt_hier_block.dir/'; - file_grep($target_dir . 'Vsub0/sub0.sv', /^module\s+(\S+)\s+/, "sub0"); - file_grep($target_dir . 'Vsub1/sub1.sv', /^module\s+(\S+)\s+/, "sub1"); - file_grep($target_dir . 'Vsub2/sub2.sv', /^module\s+(\S+)\s+/, "sub2"); - file_grep($target_dir . 'Vt_hier_block__stats.txt', qr/HierBlock,\s+Hierarchical blocks\s+(\d+)/, 14); - file_grep($Self->{obj_dir} . '/run.log', qr/MACRO:(\S+) is defined/, "cplusplus"); -} - -ok(1); -1; diff --git a/test_regress/t/t_hier_block_cmake.py b/test_regress/t/t_hier_block_cmake.py new file mode 100755 index 000000000..dcc940045 --- /dev/null +++ b/test_regress/t/t_hier_block_cmake.py @@ -0,0 +1,44 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +# If a test fails, broken .cmake may disturb the next run +test.clean_objs() + +test.scenarios('simulator') +test.top_filename = "t/t_hier_block.v" + +threads = ('-DTEST_THREADS=6' if test.vltmt else '-DTEST_THREADS=1') + +if not test.have_cmake: + test.skip("Test requires CMake; ignore error since not available or version too old") + +test.run(logfile=test.obj_dir + "/cmake.log", + cmd=[ + 'cd "' + test.obj_dir + '" && cmake ' + test.t_dir + '/t_hier_block_cmake', + "-DCMAKE_PREFIX_PATH=" + os.environ["VERILATOR_ROOT"], threads + ]) + +test.run( + logfile=test.obj_dir + "/build.log", + cmd=['cd "' + test.obj_dir + '" && cmake --build', '.', '--', "CXX_FLAGS=" + str(threads)]) + +test.run(logfile=test.obj_dir + "/run.log", + cmd=['cd "' + test.obj_dir + '" && ./t_hier_block_cmake', '.']) + +target_dir = test.obj_dir + '/CMakeFiles/t_hier_block_cmake.dir/Vt_hier_block.dir/' +test.file_grep(target_dir + 'Vsub0/sub0.sv', r'^module\s+(\S+)\s+', "sub0") +test.file_grep(target_dir + 'Vsub1/sub1.sv', r'^module\s+(\S+)\s+', "sub1") +test.file_grep(target_dir + 'Vsub2/sub2.sv', r'^module\s+(\S+)\s+', "sub2") +test.file_grep(target_dir + 'Vt_hier_block__stats.txt', + r'HierBlock,\s+Hierarchical blocks\s+(\d+)', 14) +test.file_grep(test.obj_dir + '/run.log', r'MACRO:(\S+) is defined', "cplusplus") + +test.passes() diff --git a/test_regress/t/t_hier_block_cmake/main.cpp b/test_regress/t/t_hier_block_cmake/main.cpp index beebaabff..731237b88 100644 --- a/test_regress/t/t_hier_block_cmake/main.cpp +++ b/test_regress/t/t_hier_block_cmake/main.cpp @@ -14,7 +14,7 @@ int main(int argc, char *argv[]) { const std::unique_ptr contextp{new VerilatedContext}; - // TEST_THREADS is set in t_hier_block_cmake.pl + // TEST_THREADS is set in t_hier_block_cmake.py contextp->threads(TEST_THREADS); contextp->commandArgs(argc, argv); std::unique_ptr top{new Vt_hier_block{contextp.get(), "top"}}; diff --git a/test_regress/t/t_hier_block_libmod.pl b/test_regress/t/t_hier_block_libmod.pl deleted file mode 100755 index 2d44eb30c..000000000 --- a/test_regress/t/t_hier_block_libmod.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - verilator_flags2 => ['--hierarchical', - '-y', $Self->{t_dir} . '/t_flag_relinc_dir/chip', - '+incdir+'. $Self->{t_dir} . '/t_flag_relinc_dir/include'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_hier_block_libmod.py b/test_regress/t/t_hier_block_libmod.py new file mode 100755 index 000000000..7b78daf9c --- /dev/null +++ b/test_regress/t/t_hier_block_libmod.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(verilator_flags2=[ + '--hierarchical', '-y', test.t_dir + '/t_flag_relinc_dir/chip', '+incdir+' + test.t_dir + + '/t_flag_relinc_dir/include' +]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_hier_block_nohier.pl b/test_regress/t/t_hier_block_nohier.pl deleted file mode 100755 index 06814d334..000000000 --- a/test_regress/t/t_hier_block_nohier.pl +++ /dev/null @@ -1,38 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# This test makes sure that the internal check of t_hier_block.v is correct. -# --hierarchical option is not set intentionally. - -# stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. -clean_objs(); - -scenarios(vlt_all => 1); -top_filename("t/t_hier_block.v"); - -# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. -# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. -# So use 6 threads here though it's not optimal in performance, but ok. -compile( - v_flags2 => ['t/t_hier_block.cpp'], - verilator_flags2 => ['--stats', - '+define+USE_VLT', 't/t_hier_block_vlt.vlt', - '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"'], - threads => $Self->{vltmt} ? 6 : 1 - ); - -execute( - ); - -file_grep_not($Self->{stats}, qr/HierBlock,\s+Hierarchical blocks\s+(\d+)/); -file_grep($Self->{run_log_filename}, qr/MACRO:(\S+) is defined/, "cplusplus"); - -ok(1); -1; diff --git a/test_regress/t/t_hier_block_nohier.py b/test_regress/t/t_hier_block_nohier.py new file mode 100755 index 000000000..514491950 --- /dev/null +++ b/test_regress/t/t_hier_block_nohier.py @@ -0,0 +1,36 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +# This test makes sure that the internal check of t_hier_block.v is correct. +# --hierarchical option is not set intentionally. + +import vltest_bootstrap + +# stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. +test.clean_objs() + +test.scenarios('vlt_all') +test.top_filename = "t/t_hier_block.v" + +# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. +# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. +# So use 6 threads here though it's not optimal in performance, but ok. +test.compile(v_flags2=['t/t_hier_block.cpp'], + verilator_flags2=[ + '--stats', '+define+USE_VLT', 't/t_hier_block_vlt.vlt', '--CFLAGS', + '"-pipe -DCPP_MACRO=cplusplus"' + ], + threads=(6 if test.vltmt else 1)) + +test.execute() + +test.file_grep_not(test.stats, r'HierBlock,\s+Hierarchical blocks\s+(\d+)') +test.file_grep(test.run_log_filename, r'MACRO:(\S+) is defined', "cplusplus") + +test.passes() diff --git a/test_regress/t/t_hier_block_prot_lib.pl b/test_regress/t/t_hier_block_prot_lib.pl deleted file mode 100755 index 675ac65f5..000000000 --- a/test_regress/t/t_hier_block_prot_lib.pl +++ /dev/null @@ -1,65 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -top_filename("t/t_hier_block.v"); - -scenarios(vlt_all => 1, xsim => 1); - -my $secret_prefix = "secret"; -my $secret_dir = "$Self->{obj_dir}/$secret_prefix"; -mkdir $secret_dir; - -while (1) { - # Always compile the secret file with Verilator no matter what simulator - # we are testing with - run(logfile => "$secret_dir/vlt_compile.log", - cmd => ["perl", - "$ENV{VERILATOR_ROOT}/bin/verilator", - "-cc", - "--hierarchical", - "-Mdir", - $secret_dir, - "--protect-lib", - $secret_prefix, - "--protect-key", - "PROTECT_KEY", - "t/t_hier_block.v", - "-DAS_PROT_LIB", - '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"', - $Self->{vltmt} ? ' --threads 1' : '', - "--build"], - verilator_run => 1, - ); - last if $Self->{errors}; - - compile( - v_flags2 => ['t/t_hier_block.cpp'], - verilator_flags2 => ["$secret_dir/secret.sv", - "-DPROTLIB_TOP", - "--top-module t", - "-LDFLAGS", - "'$secret_prefix/libsecret.a'"], - ); - - execute( - ); - - - ok(1); - last; -} - -file_grep($secret_dir . "/Vsub0/sub0.sv", /^module\s+(\S+)\s+/, "sub0"); -file_grep($secret_dir . "/Vsub1/sub1.sv", /^module\s+(\S+)\s+/, "sub1"); -file_grep($secret_dir . "/Vsub2/sub2.sv", /^module\s+(\S+)\s+/, "sub2"); -file_grep($Self->{run_log_filename}, qr/MACRO:(\S+) is defined/, "cplusplus"); - -ok(1); -1; diff --git a/test_regress/t/t_hier_block_prot_lib.py b/test_regress/t/t_hier_block_prot_lib.py new file mode 100755 index 000000000..d8f4103ee --- /dev/null +++ b/test_regress/t/t_hier_block_prot_lib.py @@ -0,0 +1,45 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all', 'xsim') +test.top_filename = "t/t_hier_block.v" + +secret_prefix = "secret" +secret_dir = test.obj_dir + "/" + secret_prefix +test.mkdir_ok(secret_dir) + +# Always compile the secret file with Verilator no matter what simulator +# we are testing with +test.run(logfile=secret_dir + "/vlt_compile.log", + cmd=[ + "perl", os.environ["VERILATOR_ROOT"] + "/bin/verilator", "-cc", "--hierarchical", + "-Mdir", secret_dir, "--protect-lib", secret_prefix, "--protect-key", "PROTECT_KEY", + "t/t_hier_block.v", "-DAS_PROT_LIB", '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"', + (' --threads 1' if test.vltmt else ''), "--build" + ], + verilator_run=True) + +test.compile(v_flags2=['t/t_hier_block.cpp'], + verilator_flags2=[ + secret_dir + "/secret.sv", "-DPROTLIB_TOP", "--top-module t", "-LDFLAGS", + "'" + secret_prefix + "/libsecret.a'" + ]) + +test.execute() + +test.passes() + +test.file_grep(secret_dir + "/Vsub0/sub0.sv", r'^module\s+(\S+)\s+', "sub0") +test.file_grep(secret_dir + "/Vsub1/sub1.sv", r'^module\s+(\S+)\s+', "sub1") +test.file_grep(secret_dir + "/Vsub2/sub2.sv", r'^module\s+(\S+)\s+', "sub2") +test.file_grep(test.run_log_filename, r'MACRO:(\S+) is defined', "cplusplus") + +test.passes() diff --git a/test_regress/t/t_hier_block_prot_lib_shared.pl b/test_regress/t/t_hier_block_prot_lib_shared.pl deleted file mode 100755 index 516904426..000000000 --- a/test_regress/t/t_hier_block_prot_lib_shared.pl +++ /dev/null @@ -1,67 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -top_filename("t/t_hier_block.v"); - -scenarios(vlt_all => 1, xsim => 1); - -my $secret_prefix = "secret"; -my $secret_dir = "$Self->{obj_dir}/$secret_prefix"; -mkdir $secret_dir; -my $abs_secret_dir = File::Spec->rel2abs($secret_dir); - -while (1) { - # Always compile the secret file with Verilator no matter what simulator - # we are testing with - run(logfile => "$secret_dir/vlt_compile.log", - cmd => ["perl", - "$ENV{VERILATOR_ROOT}/bin/verilator", - "-cc", - "--hierarchical", - "-Mdir", - $secret_dir, - "--protect-lib", - $secret_prefix, - "--protect-key", - "PROTECT_KEY", - "t/t_hier_block.v", - "-DAS_PROT_LIB", - '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"', - $Self->{vltmt} ? ' --threads 1' : '', - "--build"], - verilator_run => 1, - ); - last if $Self->{errors}; - - compile( - v_flags2 => ['t/t_hier_block.cpp'], - verilator_flags2 => ["$secret_dir/secret.sv", - "-DPROTLIB_TOP", - "--top-module t", - "-LDFLAGS", - "'-Wl,-rpath,$abs_secret_dir -L$abs_secret_dir -l$secret_prefix'"], - ); - - execute( - run_env => "DYLD_FALLBACK_LIBRARY_PATH=$abs_secret_dir" - ); - - - ok(1); - last; -} - -file_grep($secret_dir . "/Vsub0/sub0.sv", /^module\s+(\S+)\s+/, "sub0"); -file_grep($secret_dir . "/Vsub1/sub1.sv", /^module\s+(\S+)\s+/, "sub1"); -file_grep($secret_dir . "/Vsub2/sub2.sv", /^module\s+(\S+)\s+/, "sub2"); -file_grep($Self->{run_log_filename}, qr/MACRO:(\S+) is defined/, "cplusplus"); - -ok(1); -1; diff --git a/test_regress/t/t_hier_block_prot_lib_shared.py b/test_regress/t/t_hier_block_prot_lib_shared.py new file mode 100755 index 000000000..1f073834c --- /dev/null +++ b/test_regress/t/t_hier_block_prot_lib_shared.py @@ -0,0 +1,45 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all', 'xsim') +test.top_filename = "t/t_hier_block.v" + +secret_prefix = "secret" +secret_dir = test.obj_dir + "/" + secret_prefix +test.mkdir_ok(secret_dir) +abs_secret_dir = os.path.abspath(secret_dir) + +# Always compile the secret file with Verilator no matter what simulator +# we are testing with +test.run(logfile=secret_dir + "/vlt_compile.log", + cmd=[ + "perl", os.environ["VERILATOR_ROOT"] + "/bin/verilator", "-cc", "--hierarchical", + "-Mdir", secret_dir, "--protect-lib", secret_prefix, "--protect-key", "PROTECT_KEY", + "t/t_hier_block.v", "-DAS_PROT_LIB", '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"', + (' --threads 1' if test.vltmt else ''), "--build" + ], + verilator_run=True) + +test.compile( + v_flags2=['t/t_hier_block.cpp'], + verilator_flags2=[ + secret_dir + "/secret.sv", "-DPROTLIB_TOP", "--top-module t", "-LDFLAGS", + "'-Wl,-rpath," + abs_secret_dir + " -L" + abs_secret_dir + " -l" + secret_prefix + "'" + ]) + +test.execute(run_env="DYLD_FALLBACK_LIBRARY_PATH=" + abs_secret_dir) + +test.file_grep(secret_dir + "/Vsub0/sub0.sv", r'^module\s+(\S+)\s+', "sub0") +test.file_grep(secret_dir + "/Vsub1/sub1.sv", r'^module\s+(\S+)\s+', "sub1") +test.file_grep(secret_dir + "/Vsub2/sub2.sv", r'^module\s+(\S+)\s+', "sub2") +test.file_grep(test.run_log_filename, r'MACRO:(\S+) is defined', "cplusplus") + +test.passes() diff --git a/test_regress/t/t_hier_block_sc.pl b/test_regress/t/t_hier_block_sc.pl deleted file mode 100755 index b0023b4b7..000000000 --- a/test_regress/t/t_hier_block_sc.pl +++ /dev/null @@ -1,41 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. -clean_objs(); - -top_filename("t/t_hier_block.v"); - -# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. -# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. -# So use 6 threads here though it's not optimal in performance, but ok. -scenarios(vlt_all => 1); - -compile( - v_flags2 => ['t/t_hier_block.cpp'], - verilator_flags2 => ['--sc', - '--stats', - '--hierarchical', - '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"' - ], - threads => $Self->{vltmt} ? 6 : 1 - ); - -execute( - ); - -file_grep($Self->{obj_dir} . "/Vsub0/sub0.sv", /^module\s+(\S+)\s+/, "sub0"); -file_grep($Self->{obj_dir} . "/Vsub1/sub1.sv", /^module\s+(\S+)\s+/, "sub1"); -file_grep($Self->{obj_dir} . "/Vsub2/sub2.sv", /^module\s+(\S+)\s+/, "sub2"); -file_grep($Self->{stats}, qr/HierBlock,\s+Hierarchical blocks\s+(\d+)/, 14); -file_grep($Self->{run_log_filename}, qr/MACRO:(\S+) is defined/, "cplusplus"); - -ok(1); -1; diff --git a/test_regress/t/t_hier_block_sc.py b/test_regress/t/t_hier_block_sc.py new file mode 100755 index 000000000..ee03f4602 --- /dev/null +++ b/test_regress/t/t_hier_block_sc.py @@ -0,0 +1,36 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_hier_block.v" + +# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. +# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. +# So use 6 threads here though it's not optimal in performance, but ok. + +# stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. +test.clean_objs() + +test.compile(v_flags2=['t/t_hier_block.cpp'], + verilator_flags2=[ + '--sc', '--stats', '--hierarchical', '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"' + ], + threads=(6 if test.vltmt else 1)) + +test.execute() + +test.file_grep(test.obj_dir + "/Vsub0/sub0.sv", r'^module\s+(\S+)\s+', "sub0") +test.file_grep(test.obj_dir + "/Vsub1/sub1.sv", r'^module\s+(\S+)\s+', "sub1") +test.file_grep(test.obj_dir + "/Vsub2/sub2.sv", r'^module\s+(\S+)\s+', "sub2") +test.file_grep(test.stats, r'HierBlock,\s+Hierarchical blocks\s+(\d+)', 14) +test.file_grep(test.run_log_filename, r'MACRO:(\S+) is defined', "cplusplus") + +test.passes() diff --git a/test_regress/t/t_hier_block_sc_trace_fst.pl b/test_regress/t/t_hier_block_sc_trace_fst.pl deleted file mode 100755 index 4234811c7..000000000 --- a/test_regress/t/t_hier_block_sc_trace_fst.pl +++ /dev/null @@ -1,44 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. -clean_objs(); - -top_filename("t/t_hier_block.v"); - -# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. -# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. -# So use 6 threads here though it's not optimal in performance, but ok. -scenarios(vlt_all => 1); - -compile( - v_flags2 => ['t/t_hier_block.cpp'], - verilator_flags2 => ['--sc', - '--stats', - '--hierarchical', - '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"', - "--CFLAGS", '"-O0 -ggdb"', - "--trace-fst" - ], - threads => $Self->{vltmt} ? 6 : 1 - ); - -execute( - ); - -file_grep($Self->{obj_dir} . "/Vsub0/sub0.sv", /^module\s+(\S+)\s+/, "sub0"); -file_grep($Self->{obj_dir} . "/Vsub1/sub1.sv", /^module\s+(\S+)\s+/, "sub1"); -file_grep($Self->{obj_dir} . "/Vsub2/sub2.sv", /^module\s+(\S+)\s+/, "sub2"); -file_grep($Self->{stats}, qr/HierBlock,\s+Hierarchical blocks\s+(\d+)/, 14); -file_grep($Self->{run_log_filename}, qr/MACRO:(\S+) is defined/, "cplusplus"); - -fst_identical($Self->trace_filename, $Self->{golden_filename}); -ok(1); -1; diff --git a/test_regress/t/t_hier_block_sc_trace_fst.py b/test_regress/t/t_hier_block_sc_trace_fst.py new file mode 100755 index 000000000..5dbe51557 --- /dev/null +++ b/test_regress/t/t_hier_block_sc_trace_fst.py @@ -0,0 +1,39 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_hier_block.v" + +# stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. +test.clean_objs() + +# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. +# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. +# So use 6 threads here though it's not optimal in performance, but ok. + +test.compile(v_flags2=['t/t_hier_block.cpp'], + verilator_flags2=[ + '--sc', '--stats', '--hierarchical', '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"', + "--CFLAGS", '"-O0 -ggdb"', "--trace-fst" + ], + threads=(6 if test.vltmt else 1)) + +test.execute() + +test.file_grep(test.obj_dir + "/Vsub0/sub0.sv", r'^module\s+(\S+)\s+', "sub0") +test.file_grep(test.obj_dir + "/Vsub1/sub1.sv", r'^module\s+(\S+)\s+', "sub1") +test.file_grep(test.obj_dir + "/Vsub2/sub2.sv", r'^module\s+(\S+)\s+', "sub2") +test.file_grep(test.stats, r'HierBlock,\s+Hierarchical blocks\s+(\d+)', 14) +test.file_grep(test.run_log_filename, r'MACRO:(\S+) is defined', "cplusplus") + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_hier_block_sc_trace_vcd.pl b/test_regress/t/t_hier_block_sc_trace_vcd.pl deleted file mode 100755 index ccd49a671..000000000 --- a/test_regress/t/t_hier_block_sc_trace_vcd.pl +++ /dev/null @@ -1,44 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. -clean_objs(); - -top_filename("t/t_hier_block.v"); - -# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. -# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. -# So use 6 threads here though it's not optimal in performance, but ok. -scenarios(vlt_all => 1); - -compile( - v_flags2 => ['t/t_hier_block.cpp'], - verilator_flags2 => ['--sc', - '--stats', - '--hierarchical', - '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"', - "--CFLAGS", '"-O0 -ggdb"', - "--trace" - ], - threads => $Self->{vltmt} ? 6 : 1 - ); - -execute( - ); - -file_grep($Self->{obj_dir} . "/Vsub0/sub0.sv", /^module\s+(\S+)\s+/, "sub0"); -file_grep($Self->{obj_dir} . "/Vsub1/sub1.sv", /^module\s+(\S+)\s+/, "sub1"); -file_grep($Self->{obj_dir} . "/Vsub2/sub2.sv", /^module\s+(\S+)\s+/, "sub2"); -file_grep($Self->{stats}, qr/HierBlock,\s+Hierarchical blocks\s+(\d+)/, 14); -file_grep($Self->{run_log_filename}, qr/MACRO:(\S+) is defined/, "cplusplus"); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); -ok(1); -1; diff --git a/test_regress/t/t_hier_block_sc_trace_vcd.py b/test_regress/t/t_hier_block_sc_trace_vcd.py new file mode 100755 index 000000000..a2b2d0353 --- /dev/null +++ b/test_regress/t/t_hier_block_sc_trace_vcd.py @@ -0,0 +1,39 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_hier_block.v" + +# stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. +test.clean_objs() + +# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. +# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. +# So use 6 threads here though it's not optimal in performance, but ok. + +test.compile(v_flags2=['t/t_hier_block.cpp'], + verilator_flags2=[ + '--sc', '--stats', '--hierarchical', '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"', + "--CFLAGS", '"-O0 -ggdb"', "--trace" + ], + threads=(6 if test.vltmt else 1)) + +test.execute() + +test.file_grep(test.obj_dir + "/Vsub0/sub0.sv", r'^module\s+(\S+)\s+', "sub0") +test.file_grep(test.obj_dir + "/Vsub1/sub1.sv", r'^module\s+(\S+)\s+', "sub1") +test.file_grep(test.obj_dir + "/Vsub2/sub2.sv", r'^module\s+(\S+)\s+', "sub2") +test.file_grep(test.stats, r'HierBlock,\s+Hierarchical blocks\s+(\d+)', 14) +test.file_grep(test.run_log_filename, r'MACRO:(\S+) is defined', "cplusplus") + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_hier_block_signed_logic.pl b/test_regress/t/t_hier_block_signed_logic.pl deleted file mode 100755 index 230264176..000000000 --- a/test_regress/t/t_hier_block_signed_logic.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--stats', '--hierarchical'] - ); - -execute( - ); - -file_grep($Self->{obj_dir} . "/Vsub/sub.sv", /^module\s+(\S+)\s+/, "sub"); -file_grep($Self->{stats}, qr/HierBlock,\s+Hierarchical blocks\s+(\d+)/, 1); - -ok(1); diff --git a/test_regress/t/t_hier_block_signed_logic.py b/test_regress/t/t_hier_block_signed_logic.py new file mode 100755 index 000000000..7bba1f55e --- /dev/null +++ b/test_regress/t/t_hier_block_signed_logic.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--stats', '--hierarchical']) + +test.execute() + +test.file_grep(test.obj_dir + "/Vsub/sub.sv", r'^module\s+(\S+)\s+', "sub") +test.file_grep(test.stats, r'HierBlock,\s+Hierarchical blocks\s+(\d+)', 1) + +test.passes() diff --git a/test_regress/t/t_hier_block_struct.pl b/test_regress/t/t_hier_block_struct.pl deleted file mode 100755 index 5f2aa7a21..000000000 --- a/test_regress/t/t_hier_block_struct.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--hierarchical'] - ); - -execute( - ); - -file_grep($Self->{obj_dir} . "/VTest/Test.sv", /^module\s+(\S+)\s+/, "Test"); - -ok(1); -1; diff --git a/test_regress/t/t_hier_block_struct.py b/test_regress/t/t_hier_block_struct.py new file mode 100755 index 000000000..1f3ee62cc --- /dev/null +++ b/test_regress/t/t_hier_block_struct.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--hierarchical']) + +test.execute() + +test.file_grep(test.obj_dir + "/VTest/Test.sv", r'^module\s+(\S+)\s+', "Test") + +test.passes() diff --git a/test_regress/t/t_hier_block_trace_fst.pl b/test_regress/t/t_hier_block_trace_fst.pl deleted file mode 100755 index fd78605e4..000000000 --- a/test_regress/t/t_hier_block_trace_fst.pl +++ /dev/null @@ -1,35 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_hier_block.v"); - -# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. -# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. -# So use 6 threads here though it's not optimal in performance, but ok. - -compile( - v_flags2 => ['t/t_hier_block.cpp'], - verilator_flags2 => ['--hierarchical', - '--Wno-TIMESCALEMOD', - '--trace-fst', - '--no-trace-underscore', # To avoid handle mismatches - ], - threads => $Self->{vltmt} ? 6 : 1 - ); - -execute( - ); - -fst_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_hier_block_trace_fst.py b/test_regress/t/t_hier_block_trace_fst.py new file mode 100755 index 000000000..f6b26d0f5 --- /dev/null +++ b/test_regress/t/t_hier_block_trace_fst.py @@ -0,0 +1,33 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_hier_block.v" + +# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. +# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. +# So use 6 threads here though it's not optimal in performance, but ok. + +test.compile( + v_flags2=['t/t_hier_block.cpp'], + verilator_flags2=[ + '--hierarchical', + '--Wno-TIMESCALEMOD', + '--trace-fst', + '--no-trace-underscore', # To avoid handle mismatches + ], + threads=(6 if test.vltmt else 1)) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_hier_block_trace_vcd.pl b/test_regress/t/t_hier_block_trace_vcd.pl deleted file mode 100755 index 398c1056e..000000000 --- a/test_regress/t/t_hier_block_trace_vcd.pl +++ /dev/null @@ -1,35 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_hier_block.v"); - -# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. -# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. -# So use 6 threads here though it's not optimal in performance, but ok. - -compile( - v_flags2 => ['t/t_hier_block.cpp'], - verilator_flags2 => ['--hierarchical', - '--Wno-TIMESCALEMOD', - '--trace', - '--no-trace-underscore', # To avoid handle mismatches - ], - threads => $Self->{vltmt} ? 6 : 1 - ); - -execute( - ); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_hier_block_trace_vcd.py b/test_regress/t/t_hier_block_trace_vcd.py new file mode 100755 index 000000000..8952878f4 --- /dev/null +++ b/test_regress/t/t_hier_block_trace_vcd.py @@ -0,0 +1,33 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_hier_block.v" + +# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. +# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. +# So use 6 threads here though it's not optimal in performance, but ok. + +test.compile( + v_flags2=['t/t_hier_block.cpp'], + verilator_flags2=[ + '--hierarchical', + '--Wno-TIMESCALEMOD', + '--trace', + '--no-trace-underscore', # To avoid handle mismatches + ], + threads=(6 if test.vltmt else 1)) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_hier_block_type_param.pl b/test_regress/t/t_hier_block_type_param.pl deleted file mode 100755 index 76f03b765..000000000 --- a/test_regress/t/t_hier_block_type_param.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--hierarchical'] - ); - -execute( - ); - -file_grep($Self->{obj_dir} . "/VTest_1/Test_1.sv", /^module\s+(\S+)\s+/, "Test"); - -ok(1); -1; diff --git a/test_regress/t/t_hier_block_type_param.py b/test_regress/t/t_hier_block_type_param.py new file mode 100755 index 000000000..96ef0646c --- /dev/null +++ b/test_regress/t/t_hier_block_type_param.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--hierarchical']) + +test.execute() + +test.file_grep(test.obj_dir + "/VTest_1/Test_1.sv", r'^module\s+(\S+)\s+', "Test_1") + +test.passes() diff --git a/test_regress/t/t_hier_block_type_param_multiple.pl b/test_regress/t/t_hier_block_type_param_multiple.pl deleted file mode 100755 index f920b98d3..000000000 --- a/test_regress/t/t_hier_block_type_param_multiple.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--hierarchical'] - ); - -execute( - ); -ok(1); -1; diff --git a/test_regress/t/t_hier_block_type_param_multiple.py b/test_regress/t/t_hier_block_type_param_multiple.py new file mode 100755 index 000000000..a5474d2ec --- /dev/null +++ b/test_regress/t/t_hier_block_type_param_multiple.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--hierarchical']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_hier_block_type_param_multiple_instances.pl b/test_regress/t/t_hier_block_type_param_multiple_instances.pl deleted file mode 100755 index f920b98d3..000000000 --- a/test_regress/t/t_hier_block_type_param_multiple_instances.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--hierarchical'] - ); - -execute( - ); -ok(1); -1; diff --git a/test_regress/t/t_hier_block_type_param_multiple_instances.py b/test_regress/t/t_hier_block_type_param_multiple_instances.py new file mode 100755 index 000000000..a5474d2ec --- /dev/null +++ b/test_regress/t/t_hier_block_type_param_multiple_instances.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--hierarchical']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_hier_block_type_param_nested.pl b/test_regress/t/t_hier_block_type_param_nested.pl deleted file mode 100755 index 4d5a65138..000000000 --- a/test_regress/t/t_hier_block_type_param_nested.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--hierarchical'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_hier_block_type_param_nested.py b/test_regress/t/t_hier_block_type_param_nested.py new file mode 100755 index 000000000..a5474d2ec --- /dev/null +++ b/test_regress/t/t_hier_block_type_param_nested.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--hierarchical']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_hier_block_type_param_notfound_bad.pl b/test_regress/t/t_hier_block_type_param_notfound_bad.pl deleted file mode 100755 index 253e975ef..000000000 --- a/test_regress/t/t_hier_block_type_param_notfound_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); -top_filename("t/t_hier_block_type_param.v"); - -compile ( - verilator_flags2 => ["--hierarchical-params-file", "/does-not-exist"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_hier_block_type_param_notfound_bad.py b/test_regress/t/t_hier_block_type_param_notfound_bad.py new file mode 100755 index 000000000..7eae3e24a --- /dev/null +++ b/test_regress/t/t_hier_block_type_param_notfound_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_hier_block_type_param.v" + +test.compile(verilator_flags2=["--hierarchical-params-file", "/does-not-exist"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_hier_block_typedef_param.pl b/test_regress/t/t_hier_block_typedef_param.pl deleted file mode 100755 index 57e24f3ad..000000000 --- a/test_regress/t/t_hier_block_typedef_param.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); -top_filename("t/t_typedef_param.v"); - -compile( - verilator_flags2 => ["--hierarchical"] - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_hier_block_typedef_param.py b/test_regress/t/t_hier_block_typedef_param.py new file mode 100755 index 000000000..43ec2591b --- /dev/null +++ b/test_regress/t/t_hier_block_typedef_param.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_typedef_param.v" + +test.compile(verilator_flags2=["--hierarchical"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_hier_block_vlt.pl b/test_regress/t/t_hier_block_vlt.pl deleted file mode 100755 index 12e21bc38..000000000 --- a/test_regress/t/t_hier_block_vlt.pl +++ /dev/null @@ -1,41 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. -clean_objs(); - -scenarios(vlt_all => 1); -top_filename("t/t_hier_block.v"); - -# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. -# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. -# So use 6 threads here though it's not optimal in performance, but ok. -compile( - v_flags2 => ['t/t_hier_block.cpp'], - verilator_flags2 => ['--stats', - '--hierarchical', - '+define+SHOW_TIMESCALE', - '+define+USE_VLT', 't/t_hier_block_vlt.vlt', - '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"'], - threads => $Self->{vltmt} ? 6 : 1 - ); - -execute( - ); - -file_grep($Self->{obj_dir} . "/Vsub0/sub0.sv", qr/^\s+timeprecision\s+(\d+)ps;/mi, 1); -file_grep($Self->{obj_dir} . "/Vsub0/sub0.sv", /^module\s+(\S+)\s+/, "sub0"); -file_grep($Self->{obj_dir} . "/Vsub1/sub1.sv", /^module\s+(\S+)\s+/, "sub1"); -file_grep($Self->{obj_dir} . "/Vsub2/sub2.sv", /^module\s+(\S+)\s+/, "sub2"); -file_grep($Self->{stats}, qr/HierBlock,\s+Hierarchical blocks\s+(\d+)/, 14); -file_grep($Self->{run_log_filename}, qr/MACRO:(\S+) is defined/, "cplusplus"); - -ok(1); -1; diff --git a/test_regress/t/t_hier_block_vlt.py b/test_regress/t/t_hier_block_vlt.py new file mode 100755 index 000000000..0d1643704 --- /dev/null +++ b/test_regress/t/t_hier_block_vlt.py @@ -0,0 +1,37 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_hier_block.v" + +# stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. +test.clean_objs() + +# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. +# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. +# So use 6 threads here though it's not optimal in performance, but ok. +test.compile(v_flags2=['t/t_hier_block.cpp'], + verilator_flags2=[ + '--stats', '--hierarchical', '+define+SHOW_TIMESCALE', '+define+USE_VLT', + 't/t_hier_block_vlt.vlt', '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"' + ], + threads=(6 if test.vltmt else 1)) + +test.execute() + +test.file_grep(test.obj_dir + "/Vsub0/sub0.sv", r'^\s+timeprecision\s+(\d+)ps;', 1) +test.file_grep(test.obj_dir + "/Vsub0/sub0.sv", r'^module\s+(\S+)\s+', "sub0") +test.file_grep(test.obj_dir + "/Vsub1/sub1.sv", r'^module\s+(\S+)\s+', "sub1") +test.file_grep(test.obj_dir + "/Vsub2/sub2.sv", r'^module\s+(\S+)\s+', "sub2") +test.file_grep(test.stats, r'HierBlock,\s+Hierarchical blocks\s+(\d+)', 14) +test.file_grep(test.run_log_filename, r'MACRO:(\S+) is defined', "cplusplus") + +test.passes() diff --git a/test_regress/t/t_hier_bynum.pl b/test_regress/t/t_hier_bynum.pl deleted file mode 100755 index 4e314adef..000000000 --- a/test_regress/t/t_hier_bynum.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - v_flags2 => ['t/t_hier_block.cpp'], - verilator_flags2 => ['--hierarchical'], - verilator_make_gmake => 0, - ); - -ok(1); -1; diff --git a/test_regress/t/t_hier_bynum.py b/test_regress/t/t_hier_bynum.py new file mode 100755 index 000000000..c2db19e11 --- /dev/null +++ b/test_regress/t/t_hier_bynum.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(v_flags2=['t/t_hier_block.cpp'], + verilator_flags2=['--hierarchical'], + verilator_make_gmake=False) + +test.passes() diff --git a/test_regress/t/t_hier_task.pl b/test_regress/t/t_hier_task.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_hier_task.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_hier_task.py b/test_regress/t/t_hier_task.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_hier_task.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_hier_trace.pl b/test_regress/t/t_hier_trace.pl deleted file mode 100755 index 0e3d2f384..000000000 --- a/test_regress/t/t_hier_trace.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--trace', '-j 4', 't/t_hier_trace_sub/t_hier_trace.vlt', '--top-module t', '--hierarchical', '-F t/t_hier_trace_sub/top.F'], - ); - -execute( - all_run_flags => ['-j 4'], - ); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_hier_trace.py b/test_regress/t/t_hier_trace.py new file mode 100755 index 000000000..4da2102bc --- /dev/null +++ b/test_regress/t/t_hier_trace.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=[ + '--trace', '-j 4', 't/t_hier_trace_sub/t_hier_trace.vlt', '--top-module t', '--hierarchical', + '-F t/t_hier_trace_sub/top.F' +]) + +test.execute(all_run_flags=['-j 4']) + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_hier_trace_noinl.pl b/test_regress/t/t_hier_trace_noinl.pl deleted file mode 100755 index d23ee56be..000000000 --- a/test_regress/t/t_hier_trace_noinl.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_hier_trace.v"); - -compile( - verilator_flags2 => ['--trace', '-j 4', 't/t_hier_trace_sub/t_hier_trace.vlt', '--top-module t', '--hierarchical', '--fno-inline', '-F t/t_hier_trace_sub/top.F'], - ); - -execute( - all_run_flags => ['-j 4'], - ); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_hier_trace_noinl.py b/test_regress/t/t_hier_trace_noinl.py new file mode 100755 index 000000000..890644b91 --- /dev/null +++ b/test_regress/t/t_hier_trace_noinl.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_hier_trace.v" + +test.compile(verilator_flags2=[ + '--trace', '-j 4', 't/t_hier_trace_sub/t_hier_trace.vlt', '--top-module t', '--hierarchical', + '--fno-inline', '-F t/t_hier_trace_sub/top.F' +]) + +test.execute(all_run_flags=['-j 4']) + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_hierarchy_identifier.pl b/test_regress/t/t_hierarchy_identifier.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_hierarchy_identifier.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_hierarchy_identifier.py b/test_regress/t/t_hierarchy_identifier.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_hierarchy_identifier.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_hierarchy_identifier_bad.pl b/test_regress/t/t_hierarchy_identifier_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_hierarchy_identifier_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_hierarchy_identifier_bad.py b/test_regress/t/t_hierarchy_identifier_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_hierarchy_identifier_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_hierarchy_unnamed.pl b/test_regress/t/t_hierarchy_unnamed.pl deleted file mode 100755 index 13c6e2b71..000000000 --- a/test_regress/t/t_hierarchy_unnamed.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_hierarchy_unnamed.py b/test_regress/t/t_hierarchy_unnamed.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_hierarchy_unnamed.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_if_deep.pl b/test_regress/t/t_if_deep.pl deleted file mode 100755 index 1185a445f..000000000 --- a/test_regress/t/t_if_deep.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--compiler msvc"], # We have deep expressions we want to test - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_if_deep.py b/test_regress/t/t_if_deep.py new file mode 100755 index 000000000..539f320b1 --- /dev/null +++ b/test_regress/t/t_if_deep.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + # We have deep expressions we want to test) + verilator_flags2=["--compiler msvc"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_if_same_bad.pl b/test_regress/t/t_if_same_bad.pl deleted file mode 100755 index fa67e585c..000000000 --- a/test_regress/t/t_if_same_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 0, # bug3806 - this test should fail but does not - # expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_if_same_bad.py b/test_regress/t/t_if_same_bad.py new file mode 100755 index 000000000..f206d9126 --- /dev/null +++ b/test_regress/t/t_if_same_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint( + # expect_filename = test.golden_filename + fails=False) # bug3806 - this test should fail but does not + +test.passes() diff --git a/test_regress/t/t_if_swap.pl b/test_regress/t/t_if_swap.pl deleted file mode 100755 index da2e37bda..000000000 --- a/test_regress/t/t_if_swap.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_if_swap.py b/test_regress/t/t_if_swap.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_if_swap.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_iff.pl b/test_regress/t/t_iff.pl deleted file mode 100755 index 56363dab6..000000000 --- a/test_regress/t/t_iff.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_iff.py b/test_regress/t/t_iff.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_iff.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_implements.pl b/test_regress/t/t_implements.pl deleted file mode 100755 index da2e37bda..000000000 --- a/test_regress/t/t_implements.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_implements.py b/test_regress/t/t_implements.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_implements.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_implements_collision.pl b/test_regress/t/t_implements_collision.pl deleted file mode 100755 index e22e7f5d9..000000000 --- a/test_regress/t/t_implements_collision.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_implements_collision.py b/test_regress/t/t_implements_collision.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_implements_collision.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_implements_collision_bad.pl b/test_regress/t/t_implements_collision_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_implements_collision_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_implements_collision_bad.py b/test_regress/t/t_implements_collision_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_implements_collision_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_implements_contents_bad.pl b/test_regress/t/t_implements_contents_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_implements_contents_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_implements_contents_bad.py b/test_regress/t/t_implements_contents_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_implements_contents_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_implements_missing_bad.pl b/test_regress/t/t_implements_missing_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_implements_missing_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_implements_missing_bad.py b/test_regress/t/t_implements_missing_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_implements_missing_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_implements_nested_bad.pl b/test_regress/t/t_implements_nested_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_implements_nested_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_implements_nested_bad.py b/test_regress/t/t_implements_nested_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_implements_nested_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_implements_new_bad.pl b/test_regress/t/t_implements_new_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_implements_new_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_implements_new_bad.py b/test_regress/t/t_implements_new_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_implements_new_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_implements_noinherit_bad.pl b/test_regress/t/t_implements_noinherit_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_implements_noinherit_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_implements_noinherit_bad.py b/test_regress/t/t_implements_noinherit_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_implements_noinherit_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_implements_noninterface_bad.pl b/test_regress/t/t_implements_noninterface_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_implements_noninterface_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_implements_noninterface_bad.py b/test_regress/t/t_implements_noninterface_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_implements_noninterface_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_implements_notfound_bad.pl b/test_regress/t/t_implements_notfound_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_implements_notfound_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_implements_notfound_bad.py b/test_regress/t/t_implements_notfound_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_implements_notfound_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_implements_typed.pl b/test_regress/t/t_implements_typed.pl deleted file mode 100755 index da2e37bda..000000000 --- a/test_regress/t/t_implements_typed.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_implements_typed.py b/test_regress/t/t_implements_typed.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_implements_typed.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_impure_cond_empty_if.pl b/test_regress/t/t_impure_cond_empty_if.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_impure_cond_empty_if.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_impure_cond_empty_if.py b/test_regress/t/t_impure_cond_empty_if.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_impure_cond_empty_if.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inc_relink.pl b/test_regress/t/t_inc_relink.pl deleted file mode 100755 index 92b300018..000000000 --- a/test_regress/t/t_inc_relink.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["-Wno-WIDTHTRUNC"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_inc_relink.py b/test_regress/t/t_inc_relink.py new file mode 100755 index 000000000..754bdeefc --- /dev/null +++ b/test_regress/t/t_inc_relink.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["-Wno-WIDTHTRUNC"]) + +test.passes() diff --git a/test_regress/t/t_incorrect_multi_driven.pl b/test_regress/t/t_incorrect_multi_driven.pl deleted file mode 100755 index 0fc71f8e9..000000000 --- a/test_regress/t/t_incorrect_multi_driven.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } - -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -top_filename("t/t_incorrect_multi_driven.v"); - -lint( - fails => 0 - ); - -ok(1); -1; diff --git a/test_regress/t/t_incorrect_multi_driven.py b/test_regress/t/t_incorrect_multi_driven.py new file mode 100755 index 000000000..f51428711 --- /dev/null +++ b/test_regress/t/t_incorrect_multi_driven.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 + +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_incorrect_multi_driven.v" + +test.lint(fails=False) + +test.passes() diff --git a/test_regress/t/t_incr_void.pl b/test_regress/t/t_incr_void.pl deleted file mode 100755 index 9af7c145a..000000000 --- a/test_regress/t/t_incr_void.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--fno-split -x-assign 0"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_incr_void.py b/test_regress/t/t_incr_void.py new file mode 100755 index 000000000..487255781 --- /dev/null +++ b/test_regress/t/t_incr_void.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--fno-split -x-assign 0"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_increment_bad.pl b/test_regress/t/t_increment_bad.pl deleted file mode 100755 index 23eda8f99..000000000 --- a/test_regress/t/t_increment_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_increment_bad.py b/test_regress/t/t_increment_bad.py new file mode 100755 index 000000000..07fc79e8e --- /dev/null +++ b/test_regress/t/t_increment_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_infinite_recursion.pl b/test_regress/t/t_infinite_recursion.pl deleted file mode 100755 index ad3863480..000000000 --- a/test_regress/t/t_infinite_recursion.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--no-unlimited-stack"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_infinite_recursion.py b/test_regress/t/t_infinite_recursion.py new file mode 100755 index 000000000..d789a829e --- /dev/null +++ b/test_regress/t/t_infinite_recursion.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(verilator_flags2=["--no-unlimited-stack"]) + +test.passes() diff --git a/test_regress/t/t_init_concat.pl b/test_regress/t/t_init_concat.pl deleted file mode 100755 index fdc76316a..000000000 --- a/test_regress/t/t_init_concat.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_init_concat.py b/test_regress/t/t_init_concat.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_init_concat.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_initarray_nonarray.pl b/test_regress/t/t_initarray_nonarray.pl deleted file mode 100755 index 552bd97db..000000000 --- a/test_regress/t/t_initarray_nonarray.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_initarray_nonarray.py b/test_regress/t/t_initarray_nonarray.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_initarray_nonarray.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_initial.pl b/test_regress/t/t_initial.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_initial.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_initial.py b/test_regress/t/t_initial.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_initial.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_initial_assign_sformatf.pl b/test_regress/t/t_initial_assign_sformatf.pl deleted file mode 100755 index b46d46042..000000000 --- a/test_regress/t/t_initial_assign_sformatf.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_initial_assign_sformatf.py b/test_regress/t/t_initial_assign_sformatf.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_initial_assign_sformatf.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_initial_assign_sformatf_debug.pl b/test_regress/t/t_initial_assign_sformatf_debug.pl deleted file mode 100755 index 281cd4b10..000000000 --- a/test_regress/t/t_initial_assign_sformatf_debug.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_initial_assign_sformatf.v"); - -compile( - verilator_flags2 => ['--debug'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_initial_assign_sformatf_debug.py b/test_regress/t/t_initial_assign_sformatf_debug.py new file mode 100755 index 000000000..4679bcd8c --- /dev/null +++ b/test_regress/t/t_initial_assign_sformatf_debug.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_initial_assign_sformatf.v" + +test.compile(verilator_flags2=['--debug']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_initial_dlyass.pl b/test_regress/t/t_initial_dlyass.pl deleted file mode 100755 index 6c38c7d5a..000000000 --- a/test_regress/t/t_initial_dlyass.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['-Wno-INITIALDLY'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_initial_dlyass.py b/test_regress/t/t_initial_dlyass.py new file mode 100755 index 000000000..49c67d3a1 --- /dev/null +++ b/test_regress/t/t_initial_dlyass.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['-Wno-INITIALDLY']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_initial_dlyass_bad.pl b/test_regress/t/t_initial_dlyass_bad.pl deleted file mode 100755 index e9702830c..000000000 --- a/test_regress/t/t_initial_dlyass_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -top_filename("t/t_initial_dlyass.v"); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_initial_dlyass_bad.py b/test_regress/t/t_initial_dlyass_bad.py new file mode 100755 index 000000000..883aebe62 --- /dev/null +++ b/test_regress/t/t_initial_dlyass_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_initial_dlyass.v" + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_initial_edge.pl b/test_regress/t/t_initial_edge.pl deleted file mode 100755 index c96761446..000000000 --- a/test_regress/t/t_initial_edge.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--x-initial-edge"] - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_initial_edge.py b/test_regress/t/t_initial_edge.py new file mode 100755 index 000000000..989bc8776 --- /dev/null +++ b/test_regress/t/t_initial_edge.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--x-initial-edge"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_initial_edge_bad.pl b/test_regress/t/t_initial_edge_bad.pl deleted file mode 100755 index 8d882c587..000000000 --- a/test_regress/t/t_initial_edge_bad.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# This works with other vlt_alls, we we don't run it for them. It should -# fail with Verilator if --x-initial-edge is not specified. - -scenarios(vlt_all => 1); - -top_filename("t/t_initial_edge.v"); - -compile( - ); - -execute( - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_initial_edge_bad.py b/test_regress/t/t_initial_edge_bad.py new file mode 100755 index 000000000..2182cc77c --- /dev/null +++ b/test_regress/t/t_initial_edge_bad.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +# This works with other vlt_alls, we we don't run it for them. It should +# fail with Verilator if --x-initial-edge is not specified. + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_initial_edge.v" + +test.compile() + +test.execute(fails=True) + +test.passes() diff --git a/test_regress/t/t_initialstatic_circ.pl b/test_regress/t/t_initialstatic_circ.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_initialstatic_circ.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_initialstatic_circ.py b/test_regress/t/t_initialstatic_circ.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_initialstatic_circ.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inside.pl b/test_regress/t/t_inside.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_inside.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_inside.py b/test_regress/t/t_inside.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_inside.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inside2.pl b/test_regress/t/t_inside2.pl deleted file mode 100755 index 552bd97db..000000000 --- a/test_regress/t/t_inside2.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_inside2.py b/test_regress/t/t_inside2.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_inside2.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_inside_assoc_unsup.pl b/test_regress/t/t_inside_assoc_unsup.pl deleted file mode 100755 index 27159da5b..000000000 --- a/test_regress/t/t_inside_assoc_unsup.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inside_assoc_unsup.py b/test_regress/t/t_inside_assoc_unsup.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_inside_assoc_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_inside_dyn.pl b/test_regress/t/t_inside_dyn.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_inside_dyn.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_inside_dyn.py b/test_regress/t/t_inside_dyn.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_inside_dyn.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inside_nonint.pl b/test_regress/t/t_inside_nonint.pl deleted file mode 100755 index e22e7f5d9..000000000 --- a/test_regress/t/t_inside_nonint.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_inside_nonint.py b/test_regress/t/t_inside_nonint.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_inside_nonint.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inside_unpacked.pl b/test_regress/t/t_inside_unpacked.pl deleted file mode 100755 index 56363dab6..000000000 --- a/test_regress/t/t_inside_unpacked.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_inside_unpacked.py b/test_regress/t/t_inside_unpacked.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_inside_unpacked.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inside_unpacked_param.pl b/test_regress/t/t_inside_unpacked_param.pl deleted file mode 100755 index 525842afe..000000000 --- a/test_regress/t/t_inside_unpacked_param.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -execute( - ) if !$Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_inside_unpacked_param.py b/test_regress/t/t_inside_unpacked_param.py new file mode 100755 index 000000000..966dc53da --- /dev/null +++ b/test_regress/t/t_inside_unpacked_param.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) + +if not test.vlt_all: + test.execute() + +test.passes() diff --git a/test_regress/t/t_inside_wild.pl b/test_regress/t/t_inside_wild.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_inside_wild.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_inside_wild.py b/test_regress/t/t_inside_wild.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_inside_wild.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_2star_bad.pl b/test_regress/t/t_inst_2star_bad.pl deleted file mode 100755 index 35d749208..000000000 --- a/test_regress/t/t_inst_2star_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_2star_bad.py b/test_regress/t/t_inst_2star_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_inst_2star_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_inst_array_bad.pl b/test_regress/t/t_inst_array_bad.pl deleted file mode 100755 index 35d749208..000000000 --- a/test_regress/t/t_inst_array_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_array_bad.py b/test_regress/t/t_inst_array_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_inst_array_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_inst_array_connect.pl b/test_regress/t/t_inst_array_connect.pl deleted file mode 100755 index 56363dab6..000000000 --- a/test_regress/t/t_inst_array_connect.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_array_connect.py b/test_regress/t/t_inst_array_connect.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_inst_array_connect.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_array_inl0.pl b/test_regress/t/t_inst_array_inl0.pl deleted file mode 100755 index f64f9c533..000000000 --- a/test_regress/t/t_inst_array_inl0.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_inst_array.v"); - -compile( - v_flags2 => ['+define+NOUSE_INLINE',], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_array_inl0.py b/test_regress/t/t_inst_array_inl0.py new file mode 100755 index 000000000..38c939c11 --- /dev/null +++ b/test_regress/t/t_inst_array_inl0.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_inst_array.v" + +test.compile(v_flags2=['+define+NOUSE_INLINE']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_array_inl1.pl b/test_regress/t/t_inst_array_inl1.pl deleted file mode 100755 index a14f6269f..000000000 --- a/test_regress/t/t_inst_array_inl1.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_inst_array.v"); - -compile( - v_flags2 => ['+define+USE_INLINE',], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_array_inl1.py b/test_regress/t/t_inst_array_inl1.py new file mode 100755 index 000000000..588df37a9 --- /dev/null +++ b/test_regress/t/t_inst_array_inl1.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_inst_array.v" + +test.compile(v_flags2=['+define+USE_INLINE']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_array_partial.pl b/test_regress/t/t_inst_array_partial.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_inst_array_partial.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_array_partial.py b/test_regress/t/t_inst_array_partial.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_inst_array_partial.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_array_struct.pl b/test_regress/t/t_inst_array_struct.pl deleted file mode 100755 index e22e7f5d9..000000000 --- a/test_regress/t/t_inst_array_struct.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_array_struct.py b/test_regress/t/t_inst_array_struct.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_inst_array_struct.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_ccall.pl b/test_regress/t/t_inst_ccall.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_inst_ccall.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_ccall.py b/test_regress/t/t_inst_ccall.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_inst_ccall.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_comma_inl0.pl b/test_regress/t/t_inst_comma_inl0.pl deleted file mode 100755 index 2c3670a37..000000000 --- a/test_regress/t/t_inst_comma_inl0.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_inst_comma.v"); - -compile( - v_flags2 => ['+define+NOUSE_INLINE',], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_comma_inl0.py b/test_regress/t/t_inst_comma_inl0.py new file mode 100755 index 000000000..03cf930d4 --- /dev/null +++ b/test_regress/t/t_inst_comma_inl0.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_inst_comma.v" + +test.compile(v_flags2=['+define+NOUSE_INLINE']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_comma_inl1.pl b/test_regress/t/t_inst_comma_inl1.pl deleted file mode 100755 index 7ca8470da..000000000 --- a/test_regress/t/t_inst_comma_inl1.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_inst_comma.v"); - -compile( - v_flags2 => ['+define+USE_INLINE',], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_comma_inl1.py b/test_regress/t/t_inst_comma_inl1.py new file mode 100755 index 000000000..02a41e5a1 --- /dev/null +++ b/test_regress/t/t_inst_comma_inl1.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_inst_comma.v" + +test.compile(v_flags2=['+define+USE_INLINE']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_darray.pl b/test_regress/t/t_inst_darray.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_inst_darray.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_darray.py b/test_regress/t/t_inst_darray.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_inst_darray.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_dearray_slice.pl b/test_regress/t/t_inst_dearray_slice.pl deleted file mode 100755 index 56363dab6..000000000 --- a/test_regress/t/t_inst_dearray_slice.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_dearray_slice.py b/test_regress/t/t_inst_dearray_slice.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_inst_dearray_slice.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_dff.pl b/test_regress/t/t_inst_dff.pl deleted file mode 100755 index fdc76316a..000000000 --- a/test_regress/t/t_inst_dff.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_dff.py b/test_regress/t/t_inst_dff.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_inst_dff.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_dtree_inla.pl b/test_regress/t/t_inst_dtree_inla.pl deleted file mode 100755 index bdc806318..000000000 --- a/test_regress/t/t_inst_dtree_inla.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_inst_dtree.v"); - -compile( - v_flags2 => ['+define+INLINE_A'], - verilator_flags2 => ['-trace'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_dtree_inla.py b/test_regress/t/t_inst_dtree_inla.py new file mode 100755 index 000000000..0c74e5b29 --- /dev/null +++ b/test_regress/t/t_inst_dtree_inla.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_inst_dtree.v" + +test.compile(v_flags2=['+define+INLINE_A'], verilator_flags2=['-trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_dtree_inlab.pl b/test_regress/t/t_inst_dtree_inlab.pl deleted file mode 100755 index bed4e69ba..000000000 --- a/test_regress/t/t_inst_dtree_inlab.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_inst_dtree.v"); - -compile( - v_flags2 => ['+define+INLINE_A +define+INLINE_B'], - verilator_flags2 => ['-trace'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_dtree_inlab.py b/test_regress/t/t_inst_dtree_inlab.py new file mode 100755 index 000000000..2e47b5491 --- /dev/null +++ b/test_regress/t/t_inst_dtree_inlab.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_inst_dtree.v" + +test.compile(v_flags2=['+define+INLINE_A +define+INLINE_B'], verilator_flags2=['-trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_dtree_inlac.pl b/test_regress/t/t_inst_dtree_inlac.pl deleted file mode 100755 index f0f4a2fa0..000000000 --- a/test_regress/t/t_inst_dtree_inlac.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_inst_dtree.v"); - -compile( - v_flags2 => ['+define+INLINE_A +define+INLINE_C'], - verilator_flags2 => ['-trace'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_dtree_inlac.py b/test_regress/t/t_inst_dtree_inlac.py new file mode 100755 index 000000000..af4e087f5 --- /dev/null +++ b/test_regress/t/t_inst_dtree_inlac.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_inst_dtree.v" + +test.compile(v_flags2=['+define+INLINE_A +define+INLINE_C'], verilator_flags2=['-trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_dtree_inlad.pl b/test_regress/t/t_inst_dtree_inlad.pl deleted file mode 100755 index 1b9bddfcf..000000000 --- a/test_regress/t/t_inst_dtree_inlad.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_inst_dtree.v"); - -compile( - v_flags2 => ['+define+INLINE_A +define+INLINE_D'], - verilator_flags2 => ['-trace'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_dtree_inlad.py b/test_regress/t/t_inst_dtree_inlad.py new file mode 100755 index 000000000..f8d8a945a --- /dev/null +++ b/test_regress/t/t_inst_dtree_inlad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_inst_dtree.v" + +test.compile(v_flags2=['+define+INLINE_A +define+INLINE_D'], verilator_flags2=['-trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_dtree_inlb.pl b/test_regress/t/t_inst_dtree_inlb.pl deleted file mode 100755 index c58d89c72..000000000 --- a/test_regress/t/t_inst_dtree_inlb.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_inst_dtree.v"); - -compile( - v_flags2 => ['+define+INLINE_B'], - verilator_flags2 => ['-trace'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_dtree_inlb.py b/test_regress/t/t_inst_dtree_inlb.py new file mode 100755 index 000000000..ff392eb7a --- /dev/null +++ b/test_regress/t/t_inst_dtree_inlb.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_inst_dtree.v" + +test.compile(v_flags2=['+define+INLINE_B'], verilator_flags2=['-trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_dtree_inlbc.pl b/test_regress/t/t_inst_dtree_inlbc.pl deleted file mode 100755 index 6c439476d..000000000 --- a/test_regress/t/t_inst_dtree_inlbc.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_inst_dtree.v"); - -compile( - v_flags2 => ['+define+INLINE_B +define+INLINE_C'], - verilator_flags2 => ['-trace'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_dtree_inlbc.py b/test_regress/t/t_inst_dtree_inlbc.py new file mode 100755 index 000000000..2bf440d42 --- /dev/null +++ b/test_regress/t/t_inst_dtree_inlbc.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_inst_dtree.v" + +test.compile(v_flags2=['+define+INLINE_B +define+INLINE_C'], verilator_flags2=['-trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_dtree_inlbd.pl b/test_regress/t/t_inst_dtree_inlbd.pl deleted file mode 100755 index 3297d13a8..000000000 --- a/test_regress/t/t_inst_dtree_inlbd.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_inst_dtree.v"); - -compile( - v_flags2 => ['+define+INLINE_B +define+INLINE_D'], - verilator_flags2 => ['-trace'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_dtree_inlbd.py b/test_regress/t/t_inst_dtree_inlbd.py new file mode 100755 index 000000000..9b9abcd5c --- /dev/null +++ b/test_regress/t/t_inst_dtree_inlbd.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_inst_dtree.v" + +test.compile(v_flags2=['+define+INLINE_B +define+INLINE_D'], verilator_flags2=['-trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_dtree_inlc.pl b/test_regress/t/t_inst_dtree_inlc.pl deleted file mode 100755 index 877d7be35..000000000 --- a/test_regress/t/t_inst_dtree_inlc.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_inst_dtree.v"); - -compile( - v_flags2 => ['+define+INLINE_C'], - verilator_flags2 => ['-trace'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_dtree_inlc.py b/test_regress/t/t_inst_dtree_inlc.py new file mode 100755 index 000000000..3310eff69 --- /dev/null +++ b/test_regress/t/t_inst_dtree_inlc.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_inst_dtree.v" + +test.compile(v_flags2=['+define+INLINE_C'], verilator_flags2=['-trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_dtree_inlcd.pl b/test_regress/t/t_inst_dtree_inlcd.pl deleted file mode 100755 index 8cff7481c..000000000 --- a/test_regress/t/t_inst_dtree_inlcd.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_inst_dtree.v"); - -compile( - v_flags2 => ['+define+INLINE_C +define+INLINE_D'], - verilator_flags2 => ['-trace'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_dtree_inlcd.py b/test_regress/t/t_inst_dtree_inlcd.py new file mode 100755 index 000000000..2ba7663b0 --- /dev/null +++ b/test_regress/t/t_inst_dtree_inlcd.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_inst_dtree.v" + +test.compile(v_flags2=['+define+INLINE_C +define+INLINE_D'], verilator_flags2=['-trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_dtree_inld.pl b/test_regress/t/t_inst_dtree_inld.pl deleted file mode 100755 index 69e876fc2..000000000 --- a/test_regress/t/t_inst_dtree_inld.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_inst_dtree.v"); - -compile( - v_flags2 => ['+define+INLINE_D'], - verilator_flags2 => ['-trace'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_dtree_inld.py b/test_regress/t/t_inst_dtree_inld.py new file mode 100755 index 000000000..304292305 --- /dev/null +++ b/test_regress/t/t_inst_dtree_inld.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_inst_dtree.v" + +test.compile(v_flags2=['+define+INLINE_D'], verilator_flags2=['-trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_first.pl b/test_regress/t/t_inst_first.pl deleted file mode 100755 index cbc744927..000000000 --- a/test_regress/t/t_inst_first.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => [$Self->wno_unopthreads_for_few_cores()] - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_first.py b/test_regress/t/t_inst_first.py new file mode 100755 index 000000000..a06492309 --- /dev/null +++ b/test_regress/t/t_inst_first.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=[test.wno_unopthreads_for_few_cores]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_implicit.pl b/test_regress/t/t_inst_implicit.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_inst_implicit.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_implicit.py b/test_regress/t/t_inst_implicit.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_inst_implicit.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_long.pl b/test_regress/t/t_inst_long.pl deleted file mode 100755 index 425516114..000000000 --- a/test_regress/t/t_inst_long.pl +++ /dev/null @@ -1,58 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -use IO::File; -use strict; -use vars qw($Self); - -scenarios(vlt => 1); - -my $length = 200; -my $long = "long_" x (($length + 4) / 5); - -sub gen_top { - my $filename = shift; - - my $fh = IO::File->new(">$filename") - or $Self->error("Can't write $filename"); - $fh->print("// Generated by t_inst_long.pl\n"); - $fh->print("module t;\n"); - $fh->print("\n"); - $fh->print(" ${long} inst ();\n"); - $fh->print("\n"); - $fh->print("endmodule\n"); - $fh->close; -} - -sub gen_sub { - my $filename = shift; - - my $fh = IO::File->new(">$filename") - or $Self->error("Can't write $filename"); - $fh->print("// Generated by t_inst_long.pl\n"); - $fh->print("module ${long};\n"); - $fh->print("\n"); - $fh->print(" initial begin\n"); - $fh->print(" \$write(\"*-* All Finished *-*\\n\");\n"); - $fh->print(" \$finish;\n"); - $fh->print(" end\n"); - $fh->print("endmodule\n"); - $fh->close; -} - -top_filename("$Self->{obj_dir}/t_inst_long.v", $long); - -gen_top($Self->{top_filename}); -gen_sub("$Self->{obj_dir}/${long}.v"); - -compile(); - -ok(1); -1; diff --git a/test_regress/t/t_inst_long.py b/test_regress/t/t_inst_long.py new file mode 100755 index 000000000..a34888c88 --- /dev/null +++ b/test_regress/t/t_inst_long.py @@ -0,0 +1,46 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = os.path.join(test.obj_dir, "t_inst_long.v") + +length = 200 +longname = "long_" * int((length + 4) / 5) + + +def gen_top(filename): + with open(filename, 'w', encoding="utf8") as fh: + fh.write("// Generated by t_inst_long.py\n") + fh.write("module t;\n") + fh.write("\n") + fh.write(" " + longname + " inst ();\n") + fh.write("\n") + fh.write("endmodule\n") + + +def gen_sub(filename): + with open(filename, 'w', encoding="utf8") as fh: + fh.write("// Generated by t_inst_long.py\n") + fh.write("module " + longname + ";\n") + fh.write("\n") + fh.write(" initial begin\n") + fh.write(" $write(\"*-* All Finished *-*\\n\");\n") + fh.write(" $finish;\n") + fh.write(" end\n") + fh.write("endmodule\n") + + +gen_top(test.top_filename) +gen_sub(os.path.join(test.obj_dir, longname + ".v")) + +test.compile() + +test.passes() diff --git a/test_regress/t/t_inst_long_bad.pl b/test_regress/t/t_inst_long_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_inst_long_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_long_bad.py b/test_regress/t/t_inst_long_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_inst_long_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_inst_misarray2_bad.pl b/test_regress/t/t_inst_misarray2_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_inst_misarray2_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_misarray2_bad.py b/test_regress/t/t_inst_misarray2_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_inst_misarray2_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_inst_misarray_bad.pl b/test_regress/t/t_inst_misarray_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_inst_misarray_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_misarray_bad.py b/test_regress/t/t_inst_misarray_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_inst_misarray_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_inst_mism.pl b/test_regress/t/t_inst_mism.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_inst_mism.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_mism.py b/test_regress/t/t_inst_mism.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_inst_mism.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_missing.pl b/test_regress/t/t_inst_missing.pl deleted file mode 100755 index 47e83b415..000000000 --- a/test_regress/t/t_inst_missing.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only --Wall -Wno-DECLFILENAME"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_missing.py b/test_regress/t/t_inst_missing.py new file mode 100755 index 000000000..eed023f4a --- /dev/null +++ b/test_regress/t/t_inst_missing.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only --Wall -Wno-DECLFILENAME"]) + +test.passes() diff --git a/test_regress/t/t_inst_missing_bad.pl b/test_regress/t/t_inst_missing_bad.pl deleted file mode 100755 index ebce1e9f0..000000000 --- a/test_regress/t/t_inst_missing_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only --Wall -Wno-DECLFILENAME"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_missing_bad.py b/test_regress/t/t_inst_missing_bad.py new file mode 100755 index 000000000..af59f8be9 --- /dev/null +++ b/test_regress/t/t_inst_missing_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only --Wall -Wno-DECLFILENAME"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_inst_missing_dot_bad.pl b/test_regress/t/t_inst_missing_dot_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_inst_missing_dot_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_missing_dot_bad.py b/test_regress/t/t_inst_missing_dot_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_inst_missing_dot_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_inst_mnpipe.pl b/test_regress/t/t_inst_mnpipe.pl deleted file mode 100755 index 72847408e..000000000 --- a/test_regress/t/t_inst_mnpipe.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_mnpipe.py b/test_regress/t/t_inst_mnpipe.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_inst_mnpipe.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_name_long.pl b/test_regress/t/t_inst_name_long.pl deleted file mode 100755 index b65c35c81..000000000 --- a/test_regress/t/t_inst_name_long.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile(); - -ok(1); -1; diff --git a/test_regress/t/t_inst_name_long.py b/test_regress/t/t_inst_name_long.py new file mode 100755 index 000000000..0b27c3dc0 --- /dev/null +++ b/test_regress/t/t_inst_name_long.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_inst_noname_bad.pl b/test_regress/t/t_inst_noname_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_inst_noname_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_noname_bad.py b/test_regress/t/t_inst_noname_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_inst_noname_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_inst_notunsized.pl b/test_regress/t/t_inst_notunsized.pl deleted file mode 100755 index e61f1e09d..000000000 --- a/test_regress/t/t_inst_notunsized.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["-Wno-IMPLICIT"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_notunsized.py b/test_regress/t/t_inst_notunsized.py new file mode 100755 index 000000000..46c86aaf4 --- /dev/null +++ b/test_regress/t/t_inst_notunsized.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["-Wno-IMPLICIT"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_overwide.pl b/test_regress/t/t_inst_overwide.pl deleted file mode 100755 index 741f0f044..000000000 --- a/test_regress/t/t_inst_overwide.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => [qw(-sc -Wno-WIDTH)], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -#No execute() - -ok(1); -1; diff --git a/test_regress/t/t_inst_overwide.py b/test_regress/t/t_inst_overwide.py new file mode 100755 index 000000000..9acf5a62b --- /dev/null +++ b/test_regress/t/t_inst_overwide.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["-sc -Wno-WIDTH"], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +#test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_overwide_bad.pl b/test_regress/t/t_inst_overwide_bad.pl deleted file mode 100755 index 9bb70c819..000000000 --- a/test_regress/t/t_inst_overwide_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -top_filename("t/t_inst_overwide.v"); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_overwide_bad.py b/test_regress/t/t_inst_overwide_bad.py new file mode 100755 index 000000000..3133e885c --- /dev/null +++ b/test_regress/t/t_inst_overwide_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_inst_overwide.v" + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_inst_param_comma_bad.pl b/test_regress/t/t_inst_param_comma_bad.pl deleted file mode 100755 index 376c2d2ee..000000000 --- a/test_regress/t/t_inst_param_comma_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_param_comma_bad.py b/test_regress/t/t_inst_param_comma_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_inst_param_comma_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_inst_param_override_bad.pl b/test_regress/t/t_inst_param_override_bad.pl deleted file mode 100755 index 376c2d2ee..000000000 --- a/test_regress/t/t_inst_param_override_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_param_override_bad.py b/test_regress/t/t_inst_param_override_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_inst_param_override_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_inst_pin_place_bad.pl b/test_regress/t/t_inst_pin_place_bad.pl deleted file mode 100755 index 376c2d2ee..000000000 --- a/test_regress/t/t_inst_pin_place_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_pin_place_bad.py b/test_regress/t/t_inst_pin_place_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_inst_pin_place_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_inst_pin_realnreal.pl b/test_regress/t/t_inst_pin_realnreal.pl deleted file mode 100755 index 525842afe..000000000 --- a/test_regress/t/t_inst_pin_realnreal.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -execute( - ) if !$Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_inst_pin_realnreal.py b/test_regress/t/t_inst_pin_realnreal.py new file mode 100755 index 000000000..966dc53da --- /dev/null +++ b/test_regress/t/t_inst_pin_realnreal.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) + +if not test.vlt_all: + test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_port_array.pl b/test_regress/t/t_inst_port_array.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_inst_port_array.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_port_array.py b/test_regress/t/t_inst_port_array.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_inst_port_array.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_prepost.pl b/test_regress/t/t_inst_prepost.pl deleted file mode 100755 index 552bd97db..000000000 --- a/test_regress/t/t_inst_prepost.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_prepost.py b/test_regress/t/t_inst_prepost.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_inst_prepost.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_inst_recurse2_bad.pl b/test_regress/t/t_inst_recurse2_bad.pl deleted file mode 100755 index 53e145105..000000000 --- a/test_regress/t/t_inst_recurse2_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_recurse2_bad.py b/test_regress/t/t_inst_recurse2_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_inst_recurse2_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_inst_recurse_bad.pl b/test_regress/t/t_inst_recurse_bad.pl deleted file mode 100755 index 53e145105..000000000 --- a/test_regress/t/t_inst_recurse_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_recurse_bad.py b/test_regress/t/t_inst_recurse_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_inst_recurse_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_inst_signed.pl b/test_regress/t/t_inst_signed.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_inst_signed.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_signed.py b/test_regress/t/t_inst_signed.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_inst_signed.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_signed1.pl b/test_regress/t/t_inst_signed1.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_inst_signed1.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_signed1.py b/test_regress/t/t_inst_signed1.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_inst_signed1.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_slice.pl b/test_regress/t/t_inst_slice.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_inst_slice.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_slice.py b/test_regress/t/t_inst_slice.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_inst_slice.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_slice_noinl.pl b/test_regress/t/t_inst_slice_noinl.pl deleted file mode 100755 index 5069b1490..000000000 --- a/test_regress/t/t_inst_slice_noinl.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_inst_slice.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_slice_noinl.py b/test_regress/t/t_inst_slice_noinl.py new file mode 100755 index 000000000..bd7bcdff5 --- /dev/null +++ b/test_regress/t/t_inst_slice_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_inst_slice.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_slice_part_select.pl b/test_regress/t/t_inst_slice_part_select.pl deleted file mode 100755 index 56363dab6..000000000 --- a/test_regress/t/t_inst_slice_part_select.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_slice_part_select.py b/test_regress/t/t_inst_slice_part_select.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_inst_slice_part_select.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_sv.pl b/test_regress/t/t_inst_sv.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_inst_sv.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_sv.py b/test_regress/t/t_inst_sv.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_inst_sv.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_tree_inl0_pub0.pl b/test_regress/t/t_inst_tree_inl0_pub0.pl deleted file mode 100755 index a1e85db23..000000000 --- a/test_regress/t/t_inst_tree_inl0_pub0.pl +++ /dev/null @@ -1,36 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_inst_tree.v"); -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - v_flags2 => ["--no-json-edit-nums", "$Self->{t_dir}/$Self->{name}.vlt"], -); - -if ($Self->{vlt_all}) { - file_grep("$out_filename", qr/{"type":"MODULE","name":"l1",.*"loc":"f,56:[^"]*",.*"origName":"l1"/); - file_grep("$out_filename", qr/{"type":"MODULE","name":"l2",.*"loc":"f,62:[^"]*",.*"origName":"l2"/); - file_grep("$out_filename", qr/{"type":"MODULE","name":"l3",.*"loc":"f,69:[^"]*",.*"origName":"l3"/); - file_grep("$out_filename", qr/{"type":"MODULE","name":"l4",.*"loc":"f,76:[^"]*",.*"origName":"l4"/); - file_grep("$out_filename", qr/{"type":"MODULE","name":"l5__P1",.*"loc":"f,83:[^"]*",.*"origName":"l5"/); - file_grep("$out_filename", qr/{"type":"MODULE","name":"l5__P2",.*"loc":"f,83:[^"]*",.*"origName":"l5"/); -} - -execute( - expect => -'\] (%m|.*t\.ps): Clocked -', - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_tree_inl0_pub0.py b/test_regress/t/t_inst_tree_inl0_pub0.py new file mode 100755 index 000000000..e433c3e88 --- /dev/null +++ b/test_regress/t/t_inst_tree_inl0_pub0.py @@ -0,0 +1,35 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_inst_tree.v" + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(v_flags2=["--no-json-edit-nums", test.t_dir + "/" + test.name + ".vlt"]) + +if test.vlt_all: + test.file_grep(out_filename, + r'{"type":"MODULE","name":"l1",.*"loc":"f,56:[^"]*",.*"origName":"l1"') + test.file_grep(out_filename, + r'{"type":"MODULE","name":"l2",.*"loc":"f,62:[^"]*",.*"origName":"l2"') + test.file_grep(out_filename, + r'{"type":"MODULE","name":"l3",.*"loc":"f,69:[^"]*",.*"origName":"l3"') + test.file_grep(out_filename, + r'{"type":"MODULE","name":"l4",.*"loc":"f,76:[^"]*",.*"origName":"l4"') + test.file_grep(out_filename, + r'{"type":"MODULE","name":"l5__P1",.*"loc":"f,83:[^"]*",.*"origName":"l5"') + test.file_grep(out_filename, + r'{"type":"MODULE","name":"l5__P2",.*"loc":"f,83:[^"]*",.*"origName":"l5"') + +test.execute(expect=r"\] (%m|.*t\.ps): Clocked", ) + +test.passes() diff --git a/test_regress/t/t_inst_tree_inl0_pub1.pl b/test_regress/t/t_inst_tree_inl0_pub1.pl deleted file mode 100755 index 897de0083..000000000 --- a/test_regress/t/t_inst_tree_inl0_pub1.pl +++ /dev/null @@ -1,64 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_inst_tree.v"); - -my $default_vltmt_threads = $Self->get_default_vltmt_threads(); -compile( - verilator_flags2 => ['--stats', "$Self->{t_dir}/$Self->{name}.vlt"], - # Force 3 threads even if we have fewer cores - threads => $Self->{vltmt} ? $default_vltmt_threads : 1 - ); - -sub checkRelativeRefs { - my ($mod, $expect_relative) = @_; - my $found_relative = 0; - - foreach my $file (glob_all("$Self->{obj_dir}/V$Self->{name}_${mod}*.cpp")) { - my $text = file_contents($file); - - if ($text =~ m/this->/ || $text =~ m/vlSelf->/) { - $found_relative = 1; - } - - if ($found_relative != $expect_relative) { - error("$file " - . ($found_relative ? "has" : "does not have") - . " relative variable references."); - } - } -} - -if ($Self->{vlt_all}) { - # We expect to combine sequent functions across multiple instances of - # l2, l3, l4, l5. If this number drops, please confirm this has not broken. - file_grep($Self->{stats}, qr/Optimizations, Combined CFuncs\s+(\d+)/, - ($Self->{vltmt} ? 85 : 67)); - - # Everything should use relative references - checkRelativeRefs("t", 1); - checkRelativeRefs("l1", 1); - checkRelativeRefs("l2", 1); - checkRelativeRefs("l3", 1); - checkRelativeRefs("l4", 1); - checkRelativeRefs("l5__P1", 1); - checkRelativeRefs("l5__P2", 1); -} - -execute( - expect => -'\] (%m|.*t\.ps): Clocked -', - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_tree_inl0_pub1.py b/test_regress/t/t_inst_tree_inl0_pub1.py new file mode 100755 index 000000000..57ac152d9 --- /dev/null +++ b/test_regress/t/t_inst_tree_inl0_pub1.py @@ -0,0 +1,58 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_inst_tree.v" + +default_vltmt_threads = test.get_default_vltmt_threads +test.compile( + verilator_flags2=['--stats', test.t_dir + "/" + test.name + ".vlt"], + # Force 3 threads even if we have fewer cores + threads=(default_vltmt_threads if test.vltmt else 1)) + + +def check_relative_refs(mod, expect_relative): + found_relative = False + for filename in test.glob_some(test.obj_dir + "/V" + test.name + "_" + mod + "*.cpp"): + if test.verbose: + print("FILE " + filename) + text = test.file_contents(filename) + + if re.search(r'this->', text) or re.search(r'vlSelf->', text): + if test.verbose: + print(" REL " + filename) + found_relative = True + + if found_relative != expect_relative: + test.error(filename + " " + + ("has 'relative'" if found_relative else "has 'non-relative'") + + " variable references but expected " + + ("'relative'" if expect_relative else "'non-relative'")) + + +if test.vlt_all: + # We expect to combine sequent functions across multiple instances of + # l2, l3, l4, l5. If this number drops, please confirm this has not broken. + test.file_grep(test.stats, r'Optimizations, Combined CFuncs\s+(\d+)', + (85 if test.vltmt else 67)) + + # Everything should use relative references + check_relative_refs("t", True) + check_relative_refs("l1", True) + check_relative_refs("l2", True) + check_relative_refs("l3", True) + check_relative_refs("l4", True) + check_relative_refs("l5__P1", True) + check_relative_refs("l5__P2", True) + +test.execute(expect=r"\] (%m|.*t\.ps): Clocked") + +test.passes() diff --git a/test_regress/t/t_inst_tree_inl1_pub0.pl b/test_regress/t/t_inst_tree_inl1_pub0.pl deleted file mode 100755 index f9f77d3d5..000000000 --- a/test_regress/t/t_inst_tree_inl1_pub0.pl +++ /dev/null @@ -1,33 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_inst_tree.v"); -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - v_flags2 => ["--no-json-edit-nums", "-fno-dfg-post-inline", "$Self->{t_dir}/t_inst_tree_inl1_pub0.vlt"], - ); - -if ($Self->{vlt_all}) { - file_grep("$out_filename", qr/{"type":"VAR","name":"t.u.u0.u0.z1",.*"loc":"f,70:[^"]*",.*"origName":"z1",.*"dtypeName":"logic"/); - file_grep("$out_filename", qr/{"type":"VAR","name":"t.u.u0.u1.z1",.*"loc":"f,70:[^"]*",.*"origName":"z1",.*"dtypeName":"logic"/); - file_grep("$out_filename", qr/{"type":"VAR","name":"t.u.u1.u0.z0",.*"loc":"f,70:[^"]*",.*"origName":"z0",.*"dtypeName":"logic"/); -} - -execute( - expect => -'\] (%m|.*t\.ps): Clocked -', - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_tree_inl1_pub0.py b/test_regress/t/t_inst_tree_inl1_pub0.py new file mode 100755 index 000000000..9ecece33d --- /dev/null +++ b/test_regress/t/t_inst_tree_inl1_pub0.py @@ -0,0 +1,37 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_inst_tree.v" + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(v_flags2=[ + "--no-json-edit-nums", "-fno-dfg-post-inline", test.t_dir + "/t_inst_tree_inl1_pub0.vlt" +]) + +if test.vlt_all: + test.file_grep( + out_filename, + r'{"type":"VAR","name":"t.u.u0.u0.z1",.*"loc":"f,70:[^"]*",.*"origName":"z1",.*"dtypeName":"logic"' + ) + test.file_grep( + out_filename, + r'{"type":"VAR","name":"t.u.u0.u1.z1",.*"loc":"f,70:[^"]*",.*"origName":"z1",.*"dtypeName":"logic"' + ) + test.file_grep( + out_filename, + r'{"type":"VAR","name":"t.u.u1.u0.z0",.*"loc":"f,70:[^"]*",.*"origName":"z0",.*"dtypeName":"logic"' + ) + +test.execute(expect=r"\] (%m|.*t\.ps): Clocked\n") + +test.passes() diff --git a/test_regress/t/t_inst_tree_inl1_pub1.pl b/test_regress/t/t_inst_tree_inl1_pub1.pl deleted file mode 100755 index 13a7afd51..000000000 --- a/test_regress/t/t_inst_tree_inl1_pub1.pl +++ /dev/null @@ -1,34 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_inst_tree.v"); -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - v_flags2 => ["--no-json-edit-nums", "-fno-dfg-post-inline", "t/$Self->{name}.vlt", - $Self->wno_unopthreads_for_few_cores()] - ); - -if ($Self->{vlt_all}) { - file_grep("$out_filename", qr/{"type":"VAR","name":"u.u0.u0.z0",.*"loc":"f,70:[^"]*",.*"origName":"z0",.*"isSigPublic":true,.*"dtypeName":"logic",.*"isSigUserRdPublic":true.*"isSigUserRWPublic":true/); - file_grep("$out_filename", qr/{"type":"VAR","name":"u.u0.u0.u0.u0.z1",.*"loc":"f,85:[^"]*",.*"origName":"z1",.*"isSigPublic":true,.*"dtypeName":"logic",.*"isSigUserRdPublic":true,.*"isSigUserRWPublic":true/); - file_grep("$out_filename", qr/{"type":"VAR","name":"u.u0.u1.u0.u0.z",.*"loc":"f,83:[^"]*",.*"origName":"z",.*,"isSigPublic":true,.*dtypeName":"logic",.*"isSigUserRdPublic":true,.*"isSigUserRWPublic":true/); -} - -execute( - expect => -'\] (%m|.*t\.ps): Clocked -', - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_tree_inl1_pub1.py b/test_regress/t/t_inst_tree_inl1_pub1.py new file mode 100755 index 000000000..f26506db1 --- /dev/null +++ b/test_regress/t/t_inst_tree_inl1_pub1.py @@ -0,0 +1,38 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_inst_tree.v" + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(v_flags2=[ + "--no-json-edit-nums", "-fno-dfg-post-inline", "t/" + test.name + + ".vlt", test.wno_unopthreads_for_few_cores +]) + +if test.vlt_all: + test.file_grep( + out_filename, + r'{"type":"VAR","name":"u.u0.u0.z0",.*"loc":"f,70:[^"]*",.*"origName":"z0",.*"isSigPublic":true,.*"dtypeName":"logic",.*"isSigUserRdPublic":true.*"isSigUserRWPublic":true' + ) + test.file_grep( + out_filename, + r'{"type":"VAR","name":"u.u0.u0.u0.u0.z1",.*"loc":"f,85:[^"]*",.*"origName":"z1",.*"isSigPublic":true,.*"dtypeName":"logic",.*"isSigUserRdPublic":true,.*"isSigUserRWPublic":true' + ) + test.file_grep( + out_filename, + r'{"type":"VAR","name":"u.u0.u1.u0.u0.z",.*"loc":"f,83:[^"]*",.*"origName":"z",.*,"isSigPublic":true,.*dtypeName":"logic",.*"isSigUserRdPublic":true,.*"isSigUserRWPublic":true' + ) + +test.execute(expect=r"\] (%m|.*t\.ps): Clocked") + +test.passes() diff --git a/test_regress/t/t_inst_v2k.pl b/test_regress/t/t_inst_v2k.pl deleted file mode 100755 index f596436e6..000000000 --- a/test_regress/t/t_inst_v2k.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ['+libext+.vi+.extranoneed'], - nc => 0, # Error: Multiple +libext flags found - vcs => 0, - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_v2k.py b/test_regress/t/t_inst_v2k.py new file mode 100755 index 000000000..a791c097a --- /dev/null +++ b/test_regress/t/t_inst_v2k.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + v_flags2=['+libext+.vi+.extranoneed'], + nc=False, # Error: Multiple +libext flags found + vcs=False) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_wideconst.pl b/test_regress/t/t_inst_wideconst.pl deleted file mode 100755 index c712a5630..000000000 --- a/test_regress/t/t_inst_wideconst.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['-public'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_inst_wideconst.py b/test_regress/t/t_inst_wideconst.py new file mode 100755 index 000000000..54297fbe0 --- /dev/null +++ b/test_regress/t/t_inst_wideconst.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['-public']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interconnect.pl b/test_regress/t/t_interconnect.pl deleted file mode 100755 index 7cb28e364..000000000 --- a/test_regress/t/t_interconnect.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--binary --timing"], - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interconnect.py b/test_regress/t/t_interconnect.py new file mode 100755 index 000000000..186787928 --- /dev/null +++ b/test_regress/t/t_interconnect.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary --timing"], + fails=test.vlt_all, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interconnect_bad.pl b/test_regress/t/t_interconnect_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_interconnect_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interconnect_bad.py b/test_regress/t/t_interconnect_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_interconnect_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface.pl b/test_regress/t/t_interface.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_interface.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface.py b/test_regress/t/t_interface.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface1.pl b/test_regress/t/t_interface1.pl deleted file mode 100755 index 72847408e..000000000 --- a/test_regress/t/t_interface1.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface1.py b/test_regress/t/t_interface1.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface1.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface1_modport.pl b/test_regress/t/t_interface1_modport.pl deleted file mode 100755 index 72847408e..000000000 --- a/test_regress/t/t_interface1_modport.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface1_modport.py b/test_regress/t/t_interface1_modport.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface1_modport.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface1_modport_nansi.pl b/test_regress/t/t_interface1_modport_nansi.pl deleted file mode 100755 index 03ba543ba..000000000 --- a/test_regress/t/t_interface1_modport_nansi.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface1_modport.v"); - -compile( - v_flags2 => ['+define+NANSI'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface1_modport_nansi.py b/test_regress/t/t_interface1_modport_nansi.py new file mode 100755 index 000000000..83abc3d48 --- /dev/null +++ b/test_regress/t/t_interface1_modport_nansi.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface1_modport.v" + +test.compile(v_flags2=['+define+NANSI']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface1_modport_noinl.pl b/test_regress/t/t_interface1_modport_noinl.pl deleted file mode 100755 index a6329eb4c..000000000 --- a/test_regress/t/t_interface1_modport_noinl.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface1_modport.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface1_modport_noinl.py b/test_regress/t/t_interface1_modport_noinl.py new file mode 100755 index 000000000..39ec887e7 --- /dev/null +++ b/test_regress/t/t_interface1_modport_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface1_modport.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface1_modport_trace.pl b/test_regress/t/t_interface1_modport_trace.pl deleted file mode 100755 index 04206508e..000000000 --- a/test_regress/t/t_interface1_modport_trace.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface1_modport.v"); - -compile( - verilator_flags2 => ['--trace'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface1_modport_trace.py b/test_regress/t/t_interface1_modport_trace.py new file mode 100755 index 000000000..c16b2aa0e --- /dev/null +++ b/test_regress/t/t_interface1_modport_trace.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface1_modport.v" + +test.compile(verilator_flags2=['--trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface1_noinl.pl b/test_regress/t/t_interface1_noinl.pl deleted file mode 100755 index c964ba457..000000000 --- a/test_regress/t/t_interface1_noinl.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface1.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface1_noinl.py b/test_regress/t/t_interface1_noinl.py new file mode 100755 index 000000000..f38117e8e --- /dev/null +++ b/test_regress/t/t_interface1_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface1.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface2.pl b/test_regress/t/t_interface2.pl deleted file mode 100755 index 80cb5d427..000000000 --- a/test_regress/t/t_interface2.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--top-module t"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface2.py b/test_regress/t/t_interface2.py new file mode 100755 index 000000000..fd9bd7244 --- /dev/null +++ b/test_regress/t/t_interface2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--top-module t"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface2_noinl.pl b/test_regress/t/t_interface2_noinl.pl deleted file mode 100755 index 024a98250..000000000 --- a/test_regress/t/t_interface2_noinl.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface2.v"); - -compile( - verilator_flags2 => ["--top-module t -fno-inline"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface2_noinl.py b/test_regress/t/t_interface2_noinl.py new file mode 100755 index 000000000..b231b4c73 --- /dev/null +++ b/test_regress/t/t_interface2_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface2.v" + +test.compile(verilator_flags2=["--top-module t -fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_ar2a.pl b/test_regress/t/t_interface_ar2a.pl deleted file mode 100755 index 552bd97db..000000000 --- a/test_regress/t/t_interface_ar2a.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_ar2a.py b/test_regress/t/t_interface_ar2a.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_interface_ar2a.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_interface_ar2b.pl b/test_regress/t/t_interface_ar2b.pl deleted file mode 100755 index 552bd97db..000000000 --- a/test_regress/t/t_interface_ar2b.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_ar2b.py b/test_regress/t/t_interface_ar2b.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_interface_ar2b.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_interface_ar3.pl b/test_regress/t/t_interface_ar3.pl deleted file mode 100755 index 68aa73dfd..000000000 --- a/test_regress/t/t_interface_ar3.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - fails => $Self->{vlt_all}, # Verilator unsupported, bug546 - expect_filename => $Self->{golden_filename}, - ); - -execute( - ) if !$Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_interface_ar3.py b/test_regress/t/t_interface_ar3.py new file mode 100755 index 000000000..b0a6b1891 --- /dev/null +++ b/test_regress/t/t_interface_ar3.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + fails=test.vlt_all, # Verilator unsupported, bug546 + expect_filename=test.golden_filename) + +if not test.vlt_all: + test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_array.pl b/test_regress/t/t_interface_array.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_interface_array.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_array.py b/test_regress/t/t_interface_array.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_array.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_array2.pl b/test_regress/t/t_interface_array2.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_interface_array2.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_array2.py b/test_regress/t/t_interface_array2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_array2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_array2_coverage.pl b/test_regress/t/t_interface_array2_coverage.pl deleted file mode 100755 index c7fceb174..000000000 --- a/test_regress/t/t_interface_array2_coverage.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_array2.v"); - -compile( - v_flags2 => ["--coverage"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_array2_coverage.py b/test_regress/t/t_interface_array2_coverage.py new file mode 100755 index 000000000..4b8df9ff0 --- /dev/null +++ b/test_regress/t/t_interface_array2_coverage.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_array2.v" + +test.compile(v_flags2=["--coverage"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_array2_noinl.pl b/test_regress/t/t_interface_array2_noinl.pl deleted file mode 100755 index 419d74cf1..000000000 --- a/test_regress/t/t_interface_array2_noinl.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_array2.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_array2_noinl.py b/test_regress/t/t_interface_array2_noinl.py new file mode 100755 index 000000000..2c6d02725 --- /dev/null +++ b/test_regress/t/t_interface_array2_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_array2.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_array_bad.pl b/test_regress/t/t_interface_array_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_interface_array_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_array_bad.py b/test_regress/t/t_interface_array_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_interface_array_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_array_modport.pl b/test_regress/t/t_interface_array_modport.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_interface_array_modport.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_array_modport.py b/test_regress/t/t_interface_array_modport.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_array_modport.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_array_nocolon.pl b/test_regress/t/t_interface_array_nocolon.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_interface_array_nocolon.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_array_nocolon.py b/test_regress/t/t_interface_array_nocolon.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_array_nocolon.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_array_nocolon_bad.pl b/test_regress/t/t_interface_array_nocolon_bad.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_interface_array_nocolon_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_array_nocolon_bad.py b/test_regress/t/t_interface_array_nocolon_bad.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_interface_array_nocolon_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_array_noinl.pl b/test_regress/t/t_interface_array_noinl.pl deleted file mode 100755 index 91d88d421..000000000 --- a/test_regress/t/t_interface_array_noinl.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_array.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_array_noinl.py b/test_regress/t/t_interface_array_noinl.py new file mode 100755 index 000000000..e4b1e7a2d --- /dev/null +++ b/test_regress/t/t_interface_array_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_array.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_arraymux.pl b/test_regress/t/t_interface_arraymux.pl deleted file mode 100755 index 13c6e2b71..000000000 --- a/test_regress/t/t_interface_arraymux.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_interface_arraymux.py b/test_regress/t/t_interface_arraymux.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_interface_arraymux.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_interface_asvar_bad.pl b/test_regress/t/t_interface_asvar_bad.pl deleted file mode 100755 index df9afd1d4..000000000 --- a/test_regress/t/t_interface_asvar_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_asvar_bad.py b/test_regress/t/t_interface_asvar_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_interface_asvar_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_bind_public.pl b/test_regress/t/t_interface_bind_public.pl deleted file mode 100755 index c712a5630..000000000 --- a/test_regress/t/t_interface_bind_public.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['-public'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_bind_public.py b/test_regress/t/t_interface_bind_public.py new file mode 100755 index 000000000..54297fbe0 --- /dev/null +++ b/test_regress/t/t_interface_bind_public.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['-public']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_down.pl b/test_regress/t/t_interface_down.pl deleted file mode 100755 index 72847408e..000000000 --- a/test_regress/t/t_interface_down.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_down.py b/test_regress/t/t_interface_down.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_down.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_down_inla.pl b/test_regress/t/t_interface_down_inla.pl deleted file mode 100755 index 03f594950..000000000 --- a/test_regress/t/t_interface_down_inla.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_down.v"); - -compile( - v_flags2 => ['+define+INLINE_A'], - verilator_flags2 => ['-trace'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_down_inla.py b/test_regress/t/t_interface_down_inla.py new file mode 100755 index 000000000..1782f7d1b --- /dev/null +++ b/test_regress/t/t_interface_down_inla.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_down.v" + +test.compile(v_flags2=['+define+INLINE_A'], verilator_flags2=['-trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_down_inlab.pl b/test_regress/t/t_interface_down_inlab.pl deleted file mode 100755 index ba9431a34..000000000 --- a/test_regress/t/t_interface_down_inlab.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_down.v"); - -compile( - v_flags2 => ['+define+INLINE_A +define+INLINE_B'], - verilator_flags2 => ['-trace'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_down_inlab.py b/test_regress/t/t_interface_down_inlab.py new file mode 100755 index 000000000..d65a7085d --- /dev/null +++ b/test_regress/t/t_interface_down_inlab.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_down.v" + +test.compile(v_flags2=['+define+INLINE_A +define+INLINE_B'], verilator_flags2=['-trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_down_inlac.pl b/test_regress/t/t_interface_down_inlac.pl deleted file mode 100755 index 6ebedf7c8..000000000 --- a/test_regress/t/t_interface_down_inlac.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_down.v"); - -compile( - v_flags2 => ['+define+INLINE_A +define+INLINE_C'], - verilator_flags2 => ['-trace'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_down_inlac.py b/test_regress/t/t_interface_down_inlac.py new file mode 100755 index 000000000..6cc094f25 --- /dev/null +++ b/test_regress/t/t_interface_down_inlac.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_down.v" + +test.compile(v_flags2=['+define+INLINE_A +define+INLINE_C'], verilator_flags2=['-trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_down_inlad.pl b/test_regress/t/t_interface_down_inlad.pl deleted file mode 100755 index 2c3a13272..000000000 --- a/test_regress/t/t_interface_down_inlad.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_down.v"); - -compile( - v_flags2 => ['+define+INLINE_A +define+INLINE_D'], - verilator_flags2 => ['-trace'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_down_inlad.py b/test_regress/t/t_interface_down_inlad.py new file mode 100755 index 000000000..d7d413259 --- /dev/null +++ b/test_regress/t/t_interface_down_inlad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_down.v" + +test.compile(v_flags2=['+define+INLINE_A +define+INLINE_D'], verilator_flags2=['-trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_down_inlb.pl b/test_regress/t/t_interface_down_inlb.pl deleted file mode 100755 index 965309ad5..000000000 --- a/test_regress/t/t_interface_down_inlb.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_down.v"); - -compile( - v_flags2 => ['+define+INLINE_B'], - verilator_flags2 => ['-trace'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_down_inlb.py b/test_regress/t/t_interface_down_inlb.py new file mode 100755 index 000000000..daf398a11 --- /dev/null +++ b/test_regress/t/t_interface_down_inlb.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_down.v" + +test.compile(v_flags2=['+define+INLINE_B'], verilator_flags2=['-trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_down_inlbc.pl b/test_regress/t/t_interface_down_inlbc.pl deleted file mode 100755 index 86c09c1b5..000000000 --- a/test_regress/t/t_interface_down_inlbc.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_down.v"); - -compile( - v_flags2 => ['+define+INLINE_B +define+INLINE_C'], - verilator_flags2 => ['-trace'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_down_inlbc.py b/test_regress/t/t_interface_down_inlbc.py new file mode 100755 index 000000000..5a4620498 --- /dev/null +++ b/test_regress/t/t_interface_down_inlbc.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_down.v" + +test.compile(v_flags2=['+define+INLINE_B +define+INLINE_C'], verilator_flags2=['-trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_down_inlbd.pl b/test_regress/t/t_interface_down_inlbd.pl deleted file mode 100755 index 4dfc5f577..000000000 --- a/test_regress/t/t_interface_down_inlbd.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_down.v"); - -compile( - v_flags2 => ['+define+INLINE_B +define+INLINE_D'], - verilator_flags2 => ['-trace'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_down_inlbd.py b/test_regress/t/t_interface_down_inlbd.py new file mode 100755 index 000000000..7b3bdf8c9 --- /dev/null +++ b/test_regress/t/t_interface_down_inlbd.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_down.v" + +test.compile(v_flags2=['+define+INLINE_B +define+INLINE_D'], verilator_flags2=['-trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_down_inlc.pl b/test_regress/t/t_interface_down_inlc.pl deleted file mode 100755 index 6444e4c8f..000000000 --- a/test_regress/t/t_interface_down_inlc.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_down.v"); - -compile( - v_flags2 => ['+define+INLINE_C'], - verilator_flags2 => ['-trace'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_down_inlc.py b/test_regress/t/t_interface_down_inlc.py new file mode 100755 index 000000000..f0d83ee04 --- /dev/null +++ b/test_regress/t/t_interface_down_inlc.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_down.v" + +test.compile(v_flags2=['+define+INLINE_C'], verilator_flags2=['-trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_down_inlcd.pl b/test_regress/t/t_interface_down_inlcd.pl deleted file mode 100755 index eeaa56492..000000000 --- a/test_regress/t/t_interface_down_inlcd.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_down.v"); - -compile( - v_flags2 => ['+define+INLINE_C +define+INLINE_D'], - verilator_flags2 => ['-trace'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_down_inlcd.py b/test_regress/t/t_interface_down_inlcd.py new file mode 100755 index 000000000..bc2c3a4ff --- /dev/null +++ b/test_regress/t/t_interface_down_inlcd.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_down.v" + +test.compile(v_flags2=['+define+INLINE_C +define+INLINE_D'], verilator_flags2=['-trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_down_inld.pl b/test_regress/t/t_interface_down_inld.pl deleted file mode 100755 index 3325e696f..000000000 --- a/test_regress/t/t_interface_down_inld.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_down.v"); - -compile( - v_flags2 => ['+define+INLINE_D'], - verilator_flags2 => ['-trace'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_down_inld.py b/test_regress/t/t_interface_down_inld.py new file mode 100755 index 000000000..aa706ba17 --- /dev/null +++ b/test_regress/t/t_interface_down_inld.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_down.v" + +test.compile(v_flags2=['+define+INLINE_D'], verilator_flags2=['-trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_down_noinl.pl b/test_regress/t/t_interface_down_noinl.pl deleted file mode 100755 index 45f0a9979..000000000 --- a/test_regress/t/t_interface_down_noinl.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_down.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_down_noinl.py b/test_regress/t/t_interface_down_noinl.py new file mode 100755 index 000000000..d1aa7ab2b --- /dev/null +++ b/test_regress/t/t_interface_down_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_down.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_dups.pl b/test_regress/t/t_interface_dups.pl deleted file mode 100755 index 72847408e..000000000 --- a/test_regress/t/t_interface_dups.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_dups.py b/test_regress/t/t_interface_dups.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_dups.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen.pl b/test_regress/t/t_interface_gen.pl deleted file mode 100755 index 72847408e..000000000 --- a/test_regress/t/t_interface_gen.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen.py b/test_regress/t/t_interface_gen.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_gen.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen10.pl b/test_regress/t/t_interface_gen10.pl deleted file mode 100755 index 72847408e..000000000 --- a/test_regress/t/t_interface_gen10.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen10.py b/test_regress/t/t_interface_gen10.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_gen10.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen10_noinl.pl b/test_regress/t/t_interface_gen10_noinl.pl deleted file mode 100755 index 9903a36d2..000000000 --- a/test_regress/t/t_interface_gen10_noinl.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_gen10.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen10_noinl.py b/test_regress/t/t_interface_gen10_noinl.py new file mode 100755 index 000000000..b75c3971f --- /dev/null +++ b/test_regress/t/t_interface_gen10_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_gen10.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen11.pl b/test_regress/t/t_interface_gen11.pl deleted file mode 100755 index 72847408e..000000000 --- a/test_regress/t/t_interface_gen11.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen11.py b/test_regress/t/t_interface_gen11.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_gen11.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen11_noinl.pl b/test_regress/t/t_interface_gen11_noinl.pl deleted file mode 100755 index b658b2a71..000000000 --- a/test_regress/t/t_interface_gen11_noinl.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_gen11.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen11_noinl.py b/test_regress/t/t_interface_gen11_noinl.py new file mode 100755 index 000000000..0c8f41ceb --- /dev/null +++ b/test_regress/t/t_interface_gen11_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_gen11.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen12.pl b/test_regress/t/t_interface_gen12.pl deleted file mode 100755 index 72847408e..000000000 --- a/test_regress/t/t_interface_gen12.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen12.py b/test_regress/t/t_interface_gen12.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_gen12.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen12_noinl.pl b/test_regress/t/t_interface_gen12_noinl.pl deleted file mode 100755 index 02df4b96a..000000000 --- a/test_regress/t/t_interface_gen12_noinl.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_gen12.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen12_noinl.py b/test_regress/t/t_interface_gen12_noinl.py new file mode 100755 index 000000000..343c709d0 --- /dev/null +++ b/test_regress/t/t_interface_gen12_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_gen12.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen13.pl b/test_regress/t/t_interface_gen13.pl deleted file mode 100755 index 72847408e..000000000 --- a/test_regress/t/t_interface_gen13.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen13.py b/test_regress/t/t_interface_gen13.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_gen13.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen2.pl b/test_regress/t/t_interface_gen2.pl deleted file mode 100755 index 72847408e..000000000 --- a/test_regress/t/t_interface_gen2.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen2.py b/test_regress/t/t_interface_gen2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_gen2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen2_collision.pl b/test_regress/t/t_interface_gen2_collision.pl deleted file mode 100755 index efb121334..000000000 --- a/test_regress/t/t_interface_gen2_collision.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_gen2.v"); - -compile( - verilator_flags2 => ["--debug-collision"] - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen2_collision.py b/test_regress/t/t_interface_gen2_collision.py new file mode 100755 index 000000000..132e5efc8 --- /dev/null +++ b/test_regress/t/t_interface_gen2_collision.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_gen2.v" + +test.compile(verilator_flags2=["--debug-collision"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen2_noinl.pl b/test_regress/t/t_interface_gen2_noinl.pl deleted file mode 100755 index 41e1c4369..000000000 --- a/test_regress/t/t_interface_gen2_noinl.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_gen2.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen2_noinl.py b/test_regress/t/t_interface_gen2_noinl.py new file mode 100755 index 000000000..a58e9c947 --- /dev/null +++ b/test_regress/t/t_interface_gen2_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_gen2.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen3.pl b/test_regress/t/t_interface_gen3.pl deleted file mode 100755 index 72847408e..000000000 --- a/test_regress/t/t_interface_gen3.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen3.py b/test_regress/t/t_interface_gen3.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_gen3.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen3_collision.pl b/test_regress/t/t_interface_gen3_collision.pl deleted file mode 100755 index 12f4d9131..000000000 --- a/test_regress/t/t_interface_gen3_collision.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_gen3.v"); - -compile( - verilator_flags2 => ["--debug-collision"] - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen3_collision.py b/test_regress/t/t_interface_gen3_collision.py new file mode 100755 index 000000000..90c0230e2 --- /dev/null +++ b/test_regress/t/t_interface_gen3_collision.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_gen3.v" + +test.compile(verilator_flags2=["--debug-collision"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen3_noinl.pl b/test_regress/t/t_interface_gen3_noinl.pl deleted file mode 100755 index c4eb798da..000000000 --- a/test_regress/t/t_interface_gen3_noinl.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_gen3.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen3_noinl.py b/test_regress/t/t_interface_gen3_noinl.py new file mode 100755 index 000000000..a3c907564 --- /dev/null +++ b/test_regress/t/t_interface_gen3_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_gen3.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen4.pl b/test_regress/t/t_interface_gen4.pl deleted file mode 100755 index 72847408e..000000000 --- a/test_regress/t/t_interface_gen4.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen4.py b/test_regress/t/t_interface_gen4.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_gen4.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen4_noinl.pl b/test_regress/t/t_interface_gen4_noinl.pl deleted file mode 100755 index bfa4308dc..000000000 --- a/test_regress/t/t_interface_gen4_noinl.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_gen4.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen4_noinl.py b/test_regress/t/t_interface_gen4_noinl.py new file mode 100755 index 000000000..4309bc821 --- /dev/null +++ b/test_regress/t/t_interface_gen4_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_gen4.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen5.pl b/test_regress/t/t_interface_gen5.pl deleted file mode 100755 index 72847408e..000000000 --- a/test_regress/t/t_interface_gen5.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen5.py b/test_regress/t/t_interface_gen5.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_gen5.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen5_noinl.pl b/test_regress/t/t_interface_gen5_noinl.pl deleted file mode 100755 index 6befb7a2a..000000000 --- a/test_regress/t/t_interface_gen5_noinl.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_gen5.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen5_noinl.py b/test_regress/t/t_interface_gen5_noinl.py new file mode 100755 index 000000000..6408c8ce9 --- /dev/null +++ b/test_regress/t/t_interface_gen5_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_gen5.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen6.pl b/test_regress/t/t_interface_gen6.pl deleted file mode 100755 index 72847408e..000000000 --- a/test_regress/t/t_interface_gen6.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen6.py b/test_regress/t/t_interface_gen6.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_gen6.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen6_noinl.pl b/test_regress/t/t_interface_gen6_noinl.pl deleted file mode 100755 index 2e0ed1387..000000000 --- a/test_regress/t/t_interface_gen6_noinl.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_gen6.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen6_noinl.py b/test_regress/t/t_interface_gen6_noinl.py new file mode 100755 index 000000000..1130f060e --- /dev/null +++ b/test_regress/t/t_interface_gen6_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_gen6.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen7.pl b/test_regress/t/t_interface_gen7.pl deleted file mode 100755 index 72847408e..000000000 --- a/test_regress/t/t_interface_gen7.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen7.py b/test_regress/t/t_interface_gen7.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_gen7.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen7_noinl.pl b/test_regress/t/t_interface_gen7_noinl.pl deleted file mode 100755 index 50e396e38..000000000 --- a/test_regress/t/t_interface_gen7_noinl.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_gen7.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen7_noinl.py b/test_regress/t/t_interface_gen7_noinl.py new file mode 100755 index 000000000..5f3047e6d --- /dev/null +++ b/test_regress/t/t_interface_gen7_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_gen7.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen8.pl b/test_regress/t/t_interface_gen8.pl deleted file mode 100755 index 72847408e..000000000 --- a/test_regress/t/t_interface_gen8.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen8.py b/test_regress/t/t_interface_gen8.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_gen8.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen8_noinl.pl b/test_regress/t/t_interface_gen8_noinl.pl deleted file mode 100755 index ab4c7cef6..000000000 --- a/test_regress/t/t_interface_gen8_noinl.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_gen8.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen8_noinl.py b/test_regress/t/t_interface_gen8_noinl.py new file mode 100755 index 000000000..a436079e9 --- /dev/null +++ b/test_regress/t/t_interface_gen8_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_gen8.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen9.pl b/test_regress/t/t_interface_gen9.pl deleted file mode 100755 index 72847408e..000000000 --- a/test_regress/t/t_interface_gen9.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen9.py b/test_regress/t/t_interface_gen9.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_gen9.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen9_noinl.pl b/test_regress/t/t_interface_gen9_noinl.pl deleted file mode 100755 index 06b89e11f..000000000 --- a/test_regress/t/t_interface_gen9_noinl.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_gen9.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen9_noinl.py b/test_regress/t/t_interface_gen9_noinl.py new file mode 100755 index 000000000..a4c47ac50 --- /dev/null +++ b/test_regress/t/t_interface_gen9_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_gen9.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_gen_noinl.pl b/test_regress/t/t_interface_gen_noinl.pl deleted file mode 100755 index 123c9af68..000000000 --- a/test_regress/t/t_interface_gen_noinl.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_gen.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_gen_noinl.py b/test_regress/t/t_interface_gen_noinl.py new file mode 100755 index 000000000..510c52a8b --- /dev/null +++ b/test_regress/t/t_interface_gen_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_gen.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_import_param.pl b/test_regress/t/t_interface_import_param.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_interface_import_param.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_import_param.py b/test_regress/t/t_interface_import_param.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_import_param.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_inl.pl b/test_regress/t/t_interface_inl.pl deleted file mode 100755 index 784f6dad0..000000000 --- a/test_regress/t/t_interface_inl.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface.v"); - -compile( - # Avoid inlining so we find bugs in the non-inliner connection code - verilator_flags2 => ["-fno-inline"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_inl.py b/test_regress/t/t_interface_inl.py new file mode 100755 index 000000000..e5a851161 --- /dev/null +++ b/test_regress/t/t_interface_inl.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface.v" + +test.compile( + # Avoid inlining so we find bugs in the non-inliner connection code + verilator_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_localparam.pl b/test_regress/t/t_interface_localparam.pl deleted file mode 100755 index 7a32ecaa3..000000000 --- a/test_regress/t/t_interface_localparam.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( -); - -ok(1); -1; diff --git a/test_regress/t/t_interface_localparam.py b/test_regress/t/t_interface_localparam.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_localparam.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_mismodport_bad.pl b/test_regress/t/t_interface_mismodport_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_interface_mismodport_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_mismodport_bad.py b/test_regress/t/t_interface_mismodport_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_interface_mismodport_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_missing_bad.pl b/test_regress/t/t_interface_missing_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_interface_missing_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_missing_bad.py b/test_regress/t/t_interface_missing_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_interface_missing_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_modport.pl b/test_regress/t/t_interface_modport.pl deleted file mode 100755 index 72847408e..000000000 --- a/test_regress/t/t_interface_modport.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_modport.py b/test_regress/t/t_interface_modport.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_modport.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_modport_bad.pl b/test_regress/t/t_interface_modport_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_interface_modport_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_modport_bad.py b/test_regress/t/t_interface_modport_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_interface_modport_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_modport_coverage.pl b/test_regress/t/t_interface_modport_coverage.pl deleted file mode 100755 index 5adadac25..000000000 --- a/test_regress/t/t_interface_modport_coverage.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_modport.v"); - -compile( - verilator_flags2 => ["-fno-inline --coverage"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_modport_coverage.py b/test_regress/t/t_interface_modport_coverage.py new file mode 100755 index 000000000..76d179c19 --- /dev/null +++ b/test_regress/t/t_interface_modport_coverage.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_modport.v" + +test.compile(verilator_flags2=["-fno-inline --coverage"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_modport_dir_bad.pl b/test_regress/t/t_interface_modport_dir_bad.pl deleted file mode 100755 index 27159da5b..000000000 --- a/test_regress/t/t_interface_modport_dir_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_modport_dir_bad.py b/test_regress/t/t_interface_modport_dir_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_interface_modport_dir_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_modport_export.pl b/test_regress/t/t_interface_modport_export.pl deleted file mode 100755 index 391ec23fd..000000000 --- a/test_regress/t/t_interface_modport_export.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -execute( - ) if !$Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_interface_modport_export.py b/test_regress/t/t_interface_modport_export.py new file mode 100755 index 000000000..966dc53da --- /dev/null +++ b/test_regress/t/t_interface_modport_export.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) + +if not test.vlt_all: + test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_modport_import.pl b/test_regress/t/t_interface_modport_import.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_interface_modport_import.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_modport_import.py b/test_regress/t/t_interface_modport_import.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_modport_import.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_modport_import_export_list.pl b/test_regress/t/t_interface_modport_import_export_list.pl deleted file mode 100755 index c74d44be5..000000000 --- a/test_regress/t/t_interface_modport_import_export_list.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile(); - -ok(1); -1; diff --git a/test_regress/t/t_interface_modport_import_export_list.py b/test_regress/t/t_interface_modport_import_export_list.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_interface_modport_import_export_list.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_interface_modport_import_noinl.pl b/test_regress/t/t_interface_modport_import_noinl.pl deleted file mode 100755 index 5a273d9d1..000000000 --- a/test_regress/t/t_interface_modport_import_noinl.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_modport_import.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_modport_import_noinl.py b/test_regress/t/t_interface_modport_import_noinl.py new file mode 100755 index 000000000..799af8f28 --- /dev/null +++ b/test_regress/t/t_interface_modport_import_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_modport_import.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_modport_inl.pl b/test_regress/t/t_interface_modport_inl.pl deleted file mode 100755 index e1a9879c0..000000000 --- a/test_regress/t/t_interface_modport_inl.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_modport.v"); - -compile( - # Avoid inlining so we find bugs in the non-inliner connection code - verilator_flags2 => ["-fno-inline"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_modport_inl.py b/test_regress/t/t_interface_modport_inl.py new file mode 100755 index 000000000..06444df8c --- /dev/null +++ b/test_regress/t/t_interface_modport_inl.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_modport.v" + +test.compile( + # Avoid inlining so we find bugs in the non-inliner connection code + verilator_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_modport_noinl.pl b/test_regress/t/t_interface_modport_noinl.pl deleted file mode 100755 index 8ec176f9d..000000000 --- a/test_regress/t/t_interface_modport_noinl.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_modport.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_modport_noinl.py b/test_regress/t/t_interface_modport_noinl.py new file mode 100755 index 000000000..cd95c2a08 --- /dev/null +++ b/test_regress/t/t_interface_modport_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_modport.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_modportlist.pl b/test_regress/t/t_interface_modportlist.pl deleted file mode 100755 index 78cb97ce0..000000000 --- a/test_regress/t/t_interface_modportlist.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_modportlist.py b/test_regress/t/t_interface_modportlist.py new file mode 100755 index 000000000..69ecdb152 --- /dev/null +++ b/test_regress/t/t_interface_modportlist.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_make_gmake=False, make_top_shell=False, make_main=False) + +test.passes() diff --git a/test_regress/t/t_interface_mp_func.pl b/test_regress/t/t_interface_mp_func.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_interface_mp_func.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_mp_func.py b/test_regress/t/t_interface_mp_func.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_mp_func.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_mp_func_noinl.pl b/test_regress/t/t_interface_mp_func_noinl.pl deleted file mode 100755 index 41d3da2f8..000000000 --- a/test_regress/t/t_interface_mp_func_noinl.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_mp_func.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_mp_func_noinl.py b/test_regress/t/t_interface_mp_func_noinl.py new file mode 100755 index 000000000..eaddfaae9 --- /dev/null +++ b/test_regress/t/t_interface_mp_func_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_mp_func.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_nansi.pl b/test_regress/t/t_interface_nansi.pl deleted file mode 100755 index 72847408e..000000000 --- a/test_regress/t/t_interface_nansi.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_nansi.py b/test_regress/t/t_interface_nansi.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_nansi.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_nest.pl b/test_regress/t/t_interface_nest.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_interface_nest.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_nest.py b/test_regress/t/t_interface_nest.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_nest.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_nest_noinl.pl b/test_regress/t/t_interface_nest_noinl.pl deleted file mode 100755 index a66cd3f7f..000000000 --- a/test_regress/t/t_interface_nest_noinl.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_nest.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_nest_noinl.py b/test_regress/t/t_interface_nest_noinl.py new file mode 100755 index 000000000..bd3c559ac --- /dev/null +++ b/test_regress/t/t_interface_nest_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_nest.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_noinl.pl b/test_regress/t/t_interface_noinl.pl deleted file mode 100755 index dd355212e..000000000 --- a/test_regress/t/t_interface_noinl.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_noinl.py b/test_regress/t/t_interface_noinl.py new file mode 100755 index 000000000..626af0d7c --- /dev/null +++ b/test_regress/t/t_interface_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_param1.pl b/test_regress/t/t_interface_param1.pl deleted file mode 100755 index 13c6e2b71..000000000 --- a/test_regress/t/t_interface_param1.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_interface_param1.py b/test_regress/t/t_interface_param1.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_interface_param1.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_interface_param2.pl b/test_regress/t/t_interface_param2.pl deleted file mode 100755 index eaa885ca5..000000000 --- a/test_regress/t/t_interface_param2.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - # Verilator unsupported, bug1104 - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -execute( - ) if !$Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_interface_param2.py b/test_regress/t/t_interface_param2.py new file mode 100755 index 000000000..fb4c87343 --- /dev/null +++ b/test_regress/t/t_interface_param2.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + # Verilator unsupported, bug1104 + fails=test.vlt_all, + expect_filename=test.golden_filename) + +if not test.vlt_all: + test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_param_acc_bits.pl b/test_regress/t/t_interface_param_acc_bits.pl deleted file mode 100755 index 1c9cd303c..000000000 --- a/test_regress/t/t_interface_param_acc_bits.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - fails => $Self->{vlt_all}, # Unsupported bug1523 - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_param_acc_bits.py b/test_regress/t/t_interface_param_acc_bits.py new file mode 100755 index 000000000..ac60e9122 --- /dev/null +++ b/test_regress/t/t_interface_param_acc_bits.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + fails=test.vlt_all, # Unsupported bug1523 + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_param_another_bad.pl b/test_regress/t/t_interface_param_another_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_interface_param_another_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_param_another_bad.py b/test_regress/t/t_interface_param_another_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_interface_param_another_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_param_genblk.pl b/test_regress/t/t_interface_param_genblk.pl deleted file mode 100755 index d1ed9a923..000000000 --- a/test_regress/t/t_interface_param_genblk.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_param_genblk.py b/test_regress/t/t_interface_param_genblk.py new file mode 100755 index 000000000..ccec64024 --- /dev/null +++ b/test_regress/t/t_interface_param_genblk.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_param_loop_bad.pl b/test_regress/t/t_interface_param_loop_bad.pl deleted file mode 100755 index 485e44130..000000000 --- a/test_regress/t/t_interface_param_loop_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - # Should fail, Verilator unsupported, bug1626"); - fails => !$Self->{vlt}, - # expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_param_loop_bad.py b/test_regress/t/t_interface_param_loop_bad.py new file mode 100755 index 000000000..564f2a1d8 --- /dev/null +++ b/test_regress/t/t_interface_param_loop_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint( + # Should fail, Verilator unsupported, bug1626 + # expect_filename = test.golden_filename, + fails=not test.vlt) + +test.passes() diff --git a/test_regress/t/t_interface_parameter_access.pl b/test_regress/t/t_interface_parameter_access.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_interface_parameter_access.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_parameter_access.py b/test_regress/t/t_interface_parameter_access.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_parameter_access.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_paren_missing_bad.pl b/test_regress/t/t_interface_paren_missing_bad.pl deleted file mode 100755 index b564041ff..000000000 --- a/test_regress/t/t_interface_paren_missing_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_paren_missing_bad.py b/test_regress/t/t_interface_paren_missing_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_interface_paren_missing_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_parent_scope_bad.pl b/test_regress/t/t_interface_parent_scope_bad.pl deleted file mode 100755 index 2d88dbd1b..000000000 --- a/test_regress/t/t_interface_parent_scope_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - # Should fail, Verilator unsupported, bug1623 - fails => !$Self->{vlt}, - # expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_parent_scope_bad.py b/test_regress/t/t_interface_parent_scope_bad.py new file mode 100755 index 000000000..96a59e345 --- /dev/null +++ b/test_regress/t/t_interface_parent_scope_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint( + # Should fail, Verilator unsupported, bug1623 + # expect_filename = test.golden_filename, + fails=not test.vlt) + +test.passes() diff --git a/test_regress/t/t_interface_ref_trace.pl b/test_regress/t/t_interface_ref_trace.pl deleted file mode 100755 index 14131c931..000000000 --- a/test_regress/t/t_interface_ref_trace.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--trace-structs --trace'], - ); - -execute( - ); - -vcd_identical($Self->trace_filename, - $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_interface_ref_trace.py b/test_regress/t/t_interface_ref_trace.py new file mode 100755 index 000000000..b62c5c728 --- /dev/null +++ b/test_regress/t/t_interface_ref_trace.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--trace-structs --trace']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_ref_trace_fst.pl b/test_regress/t/t_interface_ref_trace_fst.pl deleted file mode 100755 index 56501e7ac..000000000 --- a/test_regress/t/t_interface_ref_trace_fst.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_ref_trace.v"); - -compile( - verilator_flags2 => ['--trace-structs --trace-fst'], - ); - -execute( - ); - -fst_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_interface_ref_trace_fst.py b/test_regress/t/t_interface_ref_trace_fst.py new file mode 100755 index 000000000..fef2fad52 --- /dev/null +++ b/test_regress/t/t_interface_ref_trace_fst.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_ref_trace.v" + +test.compile(verilator_flags2=['--trace-structs --trace-fst']) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_ref_trace_fst_sc.pl b/test_regress/t/t_interface_ref_trace_fst_sc.pl deleted file mode 100755 index 767aedbe7..000000000 --- a/test_regress/t/t_interface_ref_trace_fst_sc.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); -if (!$Self->have_sc) { - skip("No SystemC installed"); -} -else { - top_filename("t/t_interface_ref_trace.v"); - - compile( - verilator_flags2 => ['--trace-structs --trace-fst --sc'], - ); - - execute( - ); - - fst_identical($Self->trace_filename, $Self->{golden_filename}); -} -ok(1); -1; diff --git a/test_regress/t/t_interface_ref_trace_fst_sc.py b/test_regress/t/t_interface_ref_trace_fst_sc.py new file mode 100755 index 000000000..a45926d74 --- /dev/null +++ b/test_regress/t/t_interface_ref_trace_fst_sc.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_ref_trace.v" + +if not test.have_sc: + test.skip("No SystemC installed") + +test.compile(verilator_flags2=['--trace-structs --trace-fst --sc']) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) +test.passes() diff --git a/test_regress/t/t_interface_ref_trace_inla.pl b/test_regress/t/t_interface_ref_trace_inla.pl deleted file mode 100755 index 964d24fe2..000000000 --- a/test_regress/t/t_interface_ref_trace_inla.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_ref_trace.v"); -golden_filename("t/t_interface_ref_trace.out"); - -compile( - v_flags2 => ['+define+NO_INLINE_A'], - verilator_flags2 => ['--trace-structs --trace'], - ); - -execute( - ); - -vcd_identical($Self->trace_filename, - $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_interface_ref_trace_inla.py b/test_regress/t/t_interface_ref_trace_inla.py new file mode 100755 index 000000000..cef0f6ce1 --- /dev/null +++ b/test_regress/t/t_interface_ref_trace_inla.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_ref_trace.v" +test.golden_filename = "t/t_interface_ref_trace.out" + +test.compile(v_flags2=['+define+NO_INLINE_A'], verilator_flags2=['--trace-structs --trace']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_ref_trace_inlab.pl b/test_regress/t/t_interface_ref_trace_inlab.pl deleted file mode 100755 index 4f245978b..000000000 --- a/test_regress/t/t_interface_ref_trace_inlab.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_ref_trace.v"); -golden_filename("t/t_interface_ref_trace.out"); - -compile( - v_flags2 => ['+define+NO_INLINE_A +define+NO_INLINE_B'], - verilator_flags2 => ['--trace-structs --trace'], - ); - -execute( - ); - -vcd_identical($Self->trace_filename, - $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_interface_ref_trace_inlab.py b/test_regress/t/t_interface_ref_trace_inlab.py new file mode 100755 index 000000000..b0eece321 --- /dev/null +++ b/test_regress/t/t_interface_ref_trace_inlab.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_ref_trace.v" +test.golden_filename = "t/t_interface_ref_trace.out" + +test.compile(v_flags2=['+define+NO_INLINE_A +define+NO_INLINE_B'], + verilator_flags2=['--trace-structs --trace']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_ref_trace_inlb.pl b/test_regress/t/t_interface_ref_trace_inlb.pl deleted file mode 100755 index 786677341..000000000 --- a/test_regress/t/t_interface_ref_trace_inlb.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_ref_trace.v"); -golden_filename("t/t_interface_ref_trace.out"); - -compile( - v_flags2 => ['+define+NO_INLINE_B'], - verilator_flags2 => ['--trace-structs --trace'], - ); - -execute( - ); - -vcd_identical($Self->trace_filename, - $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_interface_ref_trace_inlb.py b/test_regress/t/t_interface_ref_trace_inlb.py new file mode 100755 index 000000000..946cc2ece --- /dev/null +++ b/test_regress/t/t_interface_ref_trace_inlb.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_ref_trace.v" +test.golden_filename = "t/t_interface_ref_trace.out" + +test.compile(v_flags2=['+define+NO_INLINE_B'], verilator_flags2=['--trace-structs --trace']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_ref_trace_noinl.pl b/test_regress/t/t_interface_ref_trace_noinl.pl deleted file mode 100755 index 28a340991..000000000 --- a/test_regress/t/t_interface_ref_trace_noinl.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_ref_trace.v"); -# Should be the same as the inlined version, but might have declarations -# in a different order. Sadly vcddiff can't check equivalence -# golden_filename("t/t_interface_ref_trace.out"); - -compile( - verilator_flags2 => ['-fno-inline --trace-structs --trace'], - ); - -execute( - ); - -vcd_identical($Self->trace_filename, - $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_interface_ref_trace_noinl.py b/test_regress/t/t_interface_ref_trace_noinl.py new file mode 100755 index 000000000..aff9b32b8 --- /dev/null +++ b/test_regress/t/t_interface_ref_trace_noinl.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_ref_trace.v" +# Should be the same as the inlined version, but might have declarations +# in a different order. Sadly vcddiff can't check equivalence +# test.golden_filename = "t/t_interface_ref_trace.out" + +test.compile(verilator_flags2=['-fno-inline --trace-structs --trace']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_ref_trace_noinl_notrace.pl b/test_regress/t/t_interface_ref_trace_noinl_notrace.pl deleted file mode 100755 index a4d5344e6..000000000 --- a/test_regress/t/t_interface_ref_trace_noinl_notrace.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_ref_trace.v"); - -compile( - verilator_flags2 => ['-fno-inline'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_ref_trace_noinl_notrace.py b/test_regress/t/t_interface_ref_trace_noinl_notrace.py new file mode 100755 index 000000000..d646cb61b --- /dev/null +++ b/test_regress/t/t_interface_ref_trace_noinl_notrace.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_ref_trace.v" + +test.compile(verilator_flags2=['-fno-inline']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_size_bad.pl b/test_regress/t/t_interface_size_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_interface_size_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_size_bad.py b/test_regress/t/t_interface_size_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_interface_size_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_star.pl b/test_regress/t/t_interface_star.pl deleted file mode 100755 index 72847408e..000000000 --- a/test_regress/t/t_interface_star.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_star.py b/test_regress/t/t_interface_star.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_star.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_top_bad.pl b/test_regress/t/t_interface_top_bad.pl deleted file mode 100755 index 8eda3a219..000000000 --- a/test_regress/t/t_interface_top_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_top_bad.py b/test_regress/t/t_interface_top_bad.py new file mode 100755 index 000000000..3def97587 --- /dev/null +++ b/test_regress/t/t_interface_top_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_twod.pl b/test_regress/t/t_interface_twod.pl deleted file mode 100755 index 72847408e..000000000 --- a/test_regress/t/t_interface_twod.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_twod.py b/test_regress/t/t_interface_twod.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_twod.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_twod_noinl.pl b/test_regress/t/t_interface_twod_noinl.pl deleted file mode 100755 index 45e33ac64..000000000 --- a/test_regress/t/t_interface_twod_noinl.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_twod.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_twod_noinl.py b/test_regress/t/t_interface_twod_noinl.py new file mode 100755 index 000000000..2c5b11cf0 --- /dev/null +++ b/test_regress/t/t_interface_twod_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_twod.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_typedef.pl b/test_regress/t/t_interface_typedef.pl deleted file mode 100755 index c887ad9a5..000000000 --- a/test_regress/t/t_interface_typedef.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -execute( - ) if !$Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_interface_typedef.py b/test_regress/t/t_interface_typedef.py new file mode 100755 index 000000000..966dc53da --- /dev/null +++ b/test_regress/t/t_interface_typedef.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) + +if not test.vlt_all: + test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_typo_bad.pl b/test_regress/t/t_interface_typo_bad.pl deleted file mode 100755 index e30ce1ac9..000000000 --- a/test_regress/t/t_interface_typo_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2005 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - # Used to be %Error: t/t_order_wireloop.v:\d+: Wire inputs its own output, creating circular logic .wire x=x. - # However we no longer gate optimize this - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_typo_bad.py b/test_regress/t/t_interface_typo_bad.py new file mode 100755 index 000000000..9047bac40 --- /dev/null +++ b/test_regress/t/t_interface_typo_bad.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint( + fails=True, + # Used to be %Error: t/t_order_wireloop.v:\d+: Wire inputs its own output, creating circular logic .wire x=x. + # However we no longer gate optimize this + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_virtual.pl b/test_regress/t/t_interface_virtual.pl deleted file mode 100755 index ba0cd2b16..000000000 --- a/test_regress/t/t_interface_virtual.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_virtual.py b/test_regress/t/t_interface_virtual.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_interface_virtual.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_virtual_bad.pl b/test_regress/t/t_interface_virtual_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_interface_virtual_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_virtual_bad.py b/test_regress/t/t_interface_virtual_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_interface_virtual_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_virtual_controlflow.pl b/test_regress/t/t_interface_virtual_controlflow.pl deleted file mode 100755 index e701df6cd..000000000 --- a/test_regress/t/t_interface_virtual_controlflow.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["-fno-reorder"], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_virtual_controlflow.py b/test_regress/t/t_interface_virtual_controlflow.py new file mode 100755 index 000000000..7aedd7b28 --- /dev/null +++ b/test_regress/t/t_interface_virtual_controlflow.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["-fno-reorder"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_virtual_inl.pl b/test_regress/t/t_interface_virtual_inl.pl deleted file mode 100755 index 522fa99e4..000000000 --- a/test_regress/t/t_interface_virtual_inl.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_interface_virtual.v"); -golden_filename("t/t_interface_virtual.out"); - -compile( - # Avoid inlining so we find bugs in the non-inliner connection code - verilator_flags2 => ["-fno-inline"], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_virtual_inl.py b/test_regress/t/t_interface_virtual_inl.py new file mode 100755 index 000000000..0276a9140 --- /dev/null +++ b/test_regress/t/t_interface_virtual_inl.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_virtual.v" +test.golden_filename = "t/t_interface_virtual.out" + +test.compile( + # Avoid inlining so we find bugs in the non-inliner connection code + verilator_flags2=["-fno-inline"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_virtual_opt.pl b/test_regress/t/t_interface_virtual_opt.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_interface_virtual_opt.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_virtual_opt.py b/test_regress/t/t_interface_virtual_opt.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_virtual_opt.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_virtual_param.pl b/test_regress/t/t_interface_virtual_param.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_interface_virtual_param.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_virtual_param.py b/test_regress/t/t_interface_virtual_param.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_virtual_param.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_virtual_sched_act.pl b/test_regress/t/t_interface_virtual_sched_act.pl deleted file mode 100755 index ba0cd2b16..000000000 --- a/test_regress/t/t_interface_virtual_sched_act.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_virtual_sched_act.py b/test_regress/t/t_interface_virtual_sched_act.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_interface_virtual_sched_act.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_virtual_sched_ico.pl b/test_regress/t/t_interface_virtual_sched_ico.pl deleted file mode 100755 index dc9558d90..000000000 --- a/test_regress/t/t_interface_virtual_sched_ico.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_main => 0, - v_flags2 => ["--exe", "$Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_virtual_sched_ico.py b/test_regress/t/t_interface_virtual_sched_ico.py new file mode 100755 index 000000000..5f13c2aee --- /dev/null +++ b/test_regress/t/t_interface_virtual_sched_ico.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_main=False, v_flags2=["--exe", test.pli_filename]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_virtual_sched_nba.pl b/test_regress/t/t_interface_virtual_sched_nba.pl deleted file mode 100755 index ba0cd2b16..000000000 --- a/test_regress/t/t_interface_virtual_sched_nba.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_virtual_sched_nba.py b/test_regress/t/t_interface_virtual_sched_nba.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_interface_virtual_sched_nba.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_virtual_timing.pl b/test_regress/t/t_interface_virtual_timing.pl deleted file mode 100755 index 984c25432..000000000 --- a/test_regress/t/t_interface_virtual_timing.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_virtual_timing.py b/test_regress/t/t_interface_virtual_timing.py new file mode 100755 index 000000000..bded720e2 --- /dev/null +++ b/test_regress/t/t_interface_virtual_timing.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_virtual_unsup.pl b/test_regress/t/t_interface_virtual_unsup.pl deleted file mode 100755 index 7d0a36d0d..000000000 --- a/test_regress/t/t_interface_virtual_unsup.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -execute( - ) if !$Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_interface_virtual_unsup.py b/test_regress/t/t_interface_virtual_unsup.py new file mode 100755 index 000000000..966dc53da --- /dev/null +++ b/test_regress/t/t_interface_virtual_unsup.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) + +if not test.vlt_all: + test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_virtual_unused_bad.pl b/test_regress/t/t_interface_virtual_unused_bad.pl deleted file mode 100755 index 7be596e0f..000000000 --- a/test_regress/t/t_interface_virtual_unused_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_virtual_unused_bad.py b/test_regress/t/t_interface_virtual_unused_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_interface_virtual_unused_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_wrong_bad.pl b/test_regress/t/t_interface_wrong_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_interface_wrong_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_interface_wrong_bad.py b/test_regress/t/t_interface_wrong_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_interface_wrong_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_json_only_begin_hier.pl b/test_regress/t/t_json_only_begin_hier.pl deleted file mode 100755 index d6d231360..000000000 --- a/test_regress/t/t_json_only_begin_hier.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - verilator_flags2 => ['--no-std', '--json-only', '--no-json-edit-nums'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -files_identical("$out_filename", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_json_only_begin_hier.py b/test_regress/t/t_json_only_begin_hier.py new file mode 100755 index 000000000..5fa0ddc00 --- /dev/null +++ b/test_regress/t/t_json_only_begin_hier.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(verilator_flags2=['--no-std', '--json-only', '--no-json-edit-nums'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.files_identical(out_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_json_only_debugcheck.pl b/test_regress/t/t_json_only_debugcheck.pl deleted file mode 100755 index 9eb18a787..000000000 --- a/test_regress/t/t_json_only_debugcheck.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -top_filename("t/t_enum_type_methods.v"); - -compile( - verilator_flags2 => ['--no-std', '--debug-check', '--no-json-edit-nums', '--flatten'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -files_identical("$out_filename", $Self->{golden_filename}, 'logfile'); - - -ok(1); -1; diff --git a/test_regress/t/t_json_only_debugcheck.py b/test_regress/t/t_json_only_debugcheck.py new file mode 100755 index 000000000..810a93a19 --- /dev/null +++ b/test_regress/t/t_json_only_debugcheck.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_enum_type_methods.v" + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(verilator_flags2=['--no-std', '--debug-check', '--no-json-edit-nums', '--flatten'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.files_identical(out_filename, test.golden_filename, 'logfile') + +test.passes() diff --git a/test_regress/t/t_json_only_first.pl b/test_regress/t/t_json_only_first.pl deleted file mode 100755 index d6d231360..000000000 --- a/test_regress/t/t_json_only_first.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - verilator_flags2 => ['--no-std', '--json-only', '--no-json-edit-nums'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -files_identical("$out_filename", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_json_only_first.py b/test_regress/t/t_json_only_first.py new file mode 100755 index 000000000..5fa0ddc00 --- /dev/null +++ b/test_regress/t/t_json_only_first.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(verilator_flags2=['--no-std', '--json-only', '--no-json-edit-nums'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.files_identical(out_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_json_only_flat.pl b/test_regress/t/t_json_only_flat.pl deleted file mode 100755 index 339b4b5a3..000000000 --- a/test_regress/t/t_json_only_flat.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -top_filename("t/t_json_only_first.v"); - -compile( - verilator_flags2 => ['--no-std', '--json-only', '--no-json-edit-nums', '--flatten'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -files_identical("$out_filename", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_json_only_flat.py b/test_regress/t/t_json_only_flat.py new file mode 100755 index 000000000..0c8fa3240 --- /dev/null +++ b/test_regress/t/t_json_only_flat.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_json_only_first.v" + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(verilator_flags2=['--no-std', '--json-only', '--no-json-edit-nums', '--flatten'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.files_identical(out_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_json_only_flat_no_inline_mod.pl b/test_regress/t/t_json_only_flat_no_inline_mod.pl deleted file mode 100755 index 4ae513fb6..000000000 --- a/test_regress/t/t_json_only_flat_no_inline_mod.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - verilator_flags2 => ['--no-std', '--json-only', '--no-json-edit-nums', '--flatten'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -files_identical("$out_filename", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_json_only_flat_no_inline_mod.py b/test_regress/t/t_json_only_flat_no_inline_mod.py new file mode 100755 index 000000000..9903be780 --- /dev/null +++ b/test_regress/t/t_json_only_flat_no_inline_mod.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(verilator_flags2=['--no-std', '--json-only', '--no-json-edit-nums', '--flatten'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.files_identical(out_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_json_only_flat_pub_mod.pl b/test_regress/t/t_json_only_flat_pub_mod.pl deleted file mode 100755 index 4ae513fb6..000000000 --- a/test_regress/t/t_json_only_flat_pub_mod.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - verilator_flags2 => ['--no-std', '--json-only', '--no-json-edit-nums', '--flatten'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -files_identical("$out_filename", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_json_only_flat_pub_mod.py b/test_regress/t/t_json_only_flat_pub_mod.py new file mode 100755 index 000000000..9903be780 --- /dev/null +++ b/test_regress/t/t_json_only_flat_pub_mod.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(verilator_flags2=['--no-std', '--json-only', '--no-json-edit-nums', '--flatten'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.files_identical(out_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_json_only_flat_vlvbound.pl b/test_regress/t/t_json_only_flat_vlvbound.pl deleted file mode 100755 index 4ae513fb6..000000000 --- a/test_regress/t/t_json_only_flat_vlvbound.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - verilator_flags2 => ['--no-std', '--json-only', '--no-json-edit-nums', '--flatten'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -files_identical("$out_filename", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_json_only_flat_vlvbound.py b/test_regress/t/t_json_only_flat_vlvbound.py new file mode 100755 index 000000000..9903be780 --- /dev/null +++ b/test_regress/t/t_json_only_flat_vlvbound.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(verilator_flags2=['--no-std', '--json-only', '--no-json-edit-nums', '--flatten'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.files_identical(out_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_json_only_output.pl b/test_regress/t/t_json_only_output.pl deleted file mode 100755 index 81baf48b0..000000000 --- a/test_regress/t/t_json_only_output.pl +++ /dev/null @@ -1,33 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/renamed-$Self->{name}.tree.json"; -my $meta_filename = "$Self->{obj_dir}/renamed-$Self->{name}.tree.meta.json"; - -compile( - verilator_flags2 => ["--no-std", "--json-only", "--json-only-output", "$out_filename", "--json-only-meta-output", "$meta_filename", '--no-json-edit-nums'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -files_identical("$out_filename", $Self->{golden_filename}); - -foreach my $file (glob("$Self->{obj_dir}/*")) { - next if $file =~ /\.log/; # Made by driver.pl, not Verilator - next if $file =~ /\.status/; # Made by driver.pl, not Verilator - next if $file =~ /renamed-/; # Requested output - error("%Error: Created $file, but --json-only shouldn't create files"); -} - -ok(1); -1; diff --git a/test_regress/t/t_json_only_output.py b/test_regress/t/t_json_only_output.py new file mode 100755 index 000000000..8f6c3b581 --- /dev/null +++ b/test_regress/t/t_json_only_output.py @@ -0,0 +1,34 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +out_filename = test.obj_dir + "/renamed-" + test.name + ".tree.json" +meta_filename = test.obj_dir + "/renamed-" + test.name + ".tree.meta.json" + +test.compile(verilator_flags2=[ + "--no-std", "--json-only", "--json-only-output", out_filename, "--json-only-meta-output", + meta_filename, '--no-json-edit-nums' +], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.files_identical(out_filename, test.golden_filename) + +for filename in glob.glob(test.obj_dir + "/*"): + if (re.search(r'\.log', filename) # Made by driver.py, not Verilator sources + or re.search(r'\.status', filename) # Made by driver.py, not Verilator sources + or re.search(r'renamed-', filename)): # Requested output + continue + test.error("%Error: Created '" + filename + "', but --json-only shouldn't create files") + +test.passes() diff --git a/test_regress/t/t_json_only_tag.pl b/test_regress/t/t_json_only_tag.pl deleted file mode 100755 index d6d231360..000000000 --- a/test_regress/t/t_json_only_tag.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - verilator_flags2 => ['--no-std', '--json-only', '--no-json-edit-nums'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -files_identical("$out_filename", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_json_only_tag.py b/test_regress/t/t_json_only_tag.py new file mode 100755 index 000000000..5fa0ddc00 --- /dev/null +++ b/test_regress/t/t_json_only_tag.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(verilator_flags2=['--no-std', '--json-only', '--no-json-edit-nums'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.files_identical(out_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_jumps_do_while.pl b/test_regress/t/t_jumps_do_while.pl deleted file mode 100755 index f96aad9b7..000000000 --- a/test_regress/t/t_jumps_do_while.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--assert'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_jumps_do_while.py b/test_regress/t/t_jumps_do_while.py new file mode 100755 index 000000000..2c4ffdce2 --- /dev/null +++ b/test_regress/t/t_jumps_do_while.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--assert']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_jumps_uninit_destructor_call.pl b/test_regress/t/t_jumps_uninit_destructor_call.pl deleted file mode 100755 index 21a2189cc..000000000 --- a/test_regress/t/t_jumps_uninit_destructor_call.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_jumps_uninit_destructor_call.py b/test_regress/t/t_jumps_uninit_destructor_call.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_jumps_uninit_destructor_call.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_langext_1.pl b/test_regress/t/t_langext_1.pl deleted file mode 100755 index 98a9e0a4a..000000000 --- a/test_regress/t/t_langext_1.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -# This is a compile only test. -compile( - v_flags2 => ["+verilog2001ext+v"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_langext_1.py b/test_regress/t/t_langext_1.py new file mode 100755 index 000000000..e87ec43cc --- /dev/null +++ b/test_regress/t/t_langext_1.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +# This is a compile only test. +test.compile(v_flags2=["+verilog2001ext+v"]) + +test.passes() diff --git a/test_regress/t/t_langext_1_bad.pl b/test_regress/t/t_langext_1_bad.pl deleted file mode 100755 index 9929990a7..000000000 --- a/test_regress/t/t_langext_1_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -top_filename("t/t_langext_1.v"); - -# This is a lint only test. -lint( - v_flags2 => ["+verilog1995ext+v"], - fails => 1 - ); - -ok(1); -1; diff --git a/test_regress/t/t_langext_1_bad.py b/test_regress/t/t_langext_1_bad.py new file mode 100755 index 000000000..f09919252 --- /dev/null +++ b/test_regress/t/t_langext_1_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_langext_1.v" + +# This is a lint only test. +test.lint(v_flags2=["+verilog1995ext+v"], fails=True) + +test.passes() diff --git a/test_regress/t/t_langext_2.pl b/test_regress/t/t_langext_2.pl deleted file mode 100755 index 9cade2ddb..000000000 --- a/test_regress/t/t_langext_2.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -# This is a compile only test. -compile( - v_flags2 => ["+systemverilogext+v"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_langext_2.py b/test_regress/t/t_langext_2.py new file mode 100755 index 000000000..76841dd5e --- /dev/null +++ b/test_regress/t/t_langext_2.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +# This is a compile only test. +test.compile(v_flags2=["+systemverilogext+v"]) + +test.passes() diff --git a/test_regress/t/t_langext_2012ext.pl b/test_regress/t/t_langext_2012ext.pl deleted file mode 100755 index cbf040cde..000000000 --- a/test_regress/t/t_langext_2012ext.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_langext_2.v"); - -# This is a compile only test. -compile( - v_flags2 => ["+1800-2012ext+v"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_langext_2012ext.py b/test_regress/t/t_langext_2012ext.py new file mode 100755 index 000000000..bdc9b832b --- /dev/null +++ b/test_regress/t/t_langext_2012ext.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_langext_2.v" + +# This is a compile only test. +test.compile(v_flags2=["+1800-2012ext+v"]) + +test.passes() diff --git a/test_regress/t/t_langext_2017ext.pl b/test_regress/t/t_langext_2017ext.pl deleted file mode 100755 index 7aa0a8c5f..000000000 --- a/test_regress/t/t_langext_2017ext.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_langext_2.v"); - -# This is a compile only test. -compile( - v_flags2 => ["+1800-2017ext+v"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_langext_2017ext.py b/test_regress/t/t_langext_2017ext.py new file mode 100755 index 000000000..0c7fffebf --- /dev/null +++ b/test_regress/t/t_langext_2017ext.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_langext_2.v" + +# This is a compile only test. +test.compile(v_flags2=["+1800-2017ext+v"]) + +test.passes() diff --git a/test_regress/t/t_langext_2023ext.pl b/test_regress/t/t_langext_2023ext.pl deleted file mode 100755 index 6badad6e3..000000000 --- a/test_regress/t/t_langext_2023ext.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_langext_2.v"); - -# This is a compile only test. -compile( - v_flags2 => ["+1800-2023ext+v"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_langext_2023ext.py b/test_regress/t/t_langext_2023ext.py new file mode 100755 index 000000000..2fb9f6909 --- /dev/null +++ b/test_regress/t/t_langext_2023ext.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_langext_2.v" + +# This is a compile only test. +test.compile(v_flags2=["+1800-2023ext+v"]) + +test.passes() diff --git a/test_regress/t/t_langext_2_bad.pl b/test_regress/t/t_langext_2_bad.pl deleted file mode 100755 index 4e8700380..000000000 --- a/test_regress/t/t_langext_2_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -top_filename("t/t_langext_2.v"); - -# This is a lint only test. -lint( - v_flags2 => ["+1364-1995ext+v"], - fails => 1 - ); - -ok(1); -1; diff --git a/test_regress/t/t_langext_2_bad.py b/test_regress/t/t_langext_2_bad.py new file mode 100755 index 000000000..2c8cce718 --- /dev/null +++ b/test_regress/t/t_langext_2_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_langext_2.v" + +# This is a lint only test. +test.lint(v_flags2=["+1364-1995ext+v"], fails=True) + +test.passes() diff --git a/test_regress/t/t_langext_3.pl b/test_regress/t/t_langext_3.pl deleted file mode 100755 index 6286db1d6..000000000 --- a/test_regress/t/t_langext_3.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -# This is a compile only test. -compile( - v_flags2 => ["+1364-2005ext+v"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_langext_3.py b/test_regress/t/t_langext_3.py new file mode 100755 index 000000000..d2e142d8b --- /dev/null +++ b/test_regress/t/t_langext_3.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +# This is a compile only test. +test.compile(v_flags2=["+1364-2005ext+v"]) + +test.passes() diff --git a/test_regress/t/t_langext_3_bad.pl b/test_regress/t/t_langext_3_bad.pl deleted file mode 100755 index f6e5e2b52..000000000 --- a/test_regress/t/t_langext_3_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -top_filename("t/t_langext_3.v"); - -# This is a lint only test. -lint( - v_flags2 => ["+1364-2001ext+v"], - fails => 1 - ); - -ok(1); -1; diff --git a/test_regress/t/t_langext_3_bad.py b/test_regress/t/t_langext_3_bad.py new file mode 100755 index 000000000..b0cb8ed8e --- /dev/null +++ b/test_regress/t/t_langext_3_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_langext_3.v" + +# This is a lint only test. +test.lint(v_flags2=["+1364-2001ext+v"], fails=True) + +test.passes() diff --git a/test_regress/t/t_langext_4.pl b/test_regress/t/t_langext_4.pl deleted file mode 100755 index dc5b8030c..000000000 --- a/test_regress/t/t_langext_4.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_langext_2.v"); - -# This is a compile only test. -compile( - v_flags2 => ["+1800-2009ext+v"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_langext_4.py b/test_regress/t/t_langext_4.py new file mode 100755 index 000000000..829a07706 --- /dev/null +++ b/test_regress/t/t_langext_4.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_langext_2.v" + +# This is a compile only test. +test.compile(v_flags2=["+1800-2009ext+v"]) + +test.passes() diff --git a/test_regress/t/t_langext_4_bad.pl b/test_regress/t/t_langext_4_bad.pl deleted file mode 100755 index ed58832e3..000000000 --- a/test_regress/t/t_langext_4_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -top_filename("t/t_langext_2.v"); - -# This is a lint only test. -lint( - v_flags2 => ["+1800-2005ext+v"], - fails => 1 - ); - -ok(1); -1; diff --git a/test_regress/t/t_langext_4_bad.py b/test_regress/t/t_langext_4_bad.py new file mode 100755 index 000000000..fa9e4431d --- /dev/null +++ b/test_regress/t/t_langext_4_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_langext_2.v" + +# This is a lint only test. +test.lint(v_flags2=["+1800-2005ext+v"], fails=True) + +test.passes() diff --git a/test_regress/t/t_langext_order.pl b/test_regress/t/t_langext_order.pl deleted file mode 100755 index 6286db1d6..000000000 --- a/test_regress/t/t_langext_order.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -# This is a compile only test. -compile( - v_flags2 => ["+1364-2005ext+v"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_langext_order.py b/test_regress/t/t_langext_order.py new file mode 100755 index 000000000..d2e142d8b --- /dev/null +++ b/test_regress/t/t_langext_order.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +# This is a compile only test. +test.compile(v_flags2=["+1364-2005ext+v"]) + +test.passes() diff --git a/test_regress/t/t_leak.pl b/test_regress/t/t_leak.pl deleted file mode 100755 index a0ba4ff73..000000000 --- a/test_regress/t/t_leak.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -if ($Self->{vltmt} && exists $ENV{TRAVIS_DIST} && - $ENV{TRAVIS_DIST} eq "trusty") -{ - skip("Multithreaded test does not work under CI w/ Ubuntu Trusty"); -} - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"], - make_flags => 'CPPFLAGS_ADD=-DVL_NO_LEGACY', - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_leak.py b/test_regress/t/t_leak.py new file mode 100755 index 000000000..a743e049c --- /dev/null +++ b/test_regress/t/t_leak.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +if test.vltmt and test.getenv_def('TRAVIS_DIST', "None") == "trusty": + test.skip("Multithreaded test does not work under CI w/ Ubuntu Trusty") + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--exe", test.pli_filename], + make_flags=['CPPFLAGS_ADD=-DVL_NO_LEGACY']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_let.pl b/test_regress/t/t_let.pl deleted file mode 100755 index 86fa92ccb..000000000 --- a/test_regress/t/t_let.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_let.py b/test_regress/t/t_let.py new file mode 100755 index 000000000..fc5a55e3f --- /dev/null +++ b/test_regress/t/t_let.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_let_arg_bad.pl b/test_regress/t/t_let_arg_bad.pl deleted file mode 100755 index d85145f99..000000000 --- a/test_regress/t/t_let_arg_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - expect_filename => $Self->{golden_filename}, - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_let_arg_bad.py b/test_regress/t/t_let_arg_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_let_arg_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_let_recurse_bad.pl b/test_regress/t/t_let_recurse_bad.pl deleted file mode 100755 index d85145f99..000000000 --- a/test_regress/t/t_let_recurse_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - expect_filename => $Self->{golden_filename}, - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_let_recurse_bad.py b/test_regress/t/t_let_recurse_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_let_recurse_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_let_unsup.pl b/test_regress/t/t_let_unsup.pl deleted file mode 100755 index d85145f99..000000000 --- a/test_regress/t/t_let_unsup.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - expect_filename => $Self->{golden_filename}, - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_let_unsup.py b/test_regress/t/t_let_unsup.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_let_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lib.pl b/test_regress/t/t_lib.pl deleted file mode 100755 index fbe7a6b2d..000000000 --- a/test_regress/t/t_lib.pl +++ /dev/null @@ -1,68 +0,0 @@ -#!/usr/bin/env perl -# Makes the test run with tracing enabled by default, can be overridden -# with --notrace -unshift(@ARGV, "--trace"); -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Todd Strader. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1, xsim => 1); - -top_filename("t/t_lib_prot.v"); - -$Self->{sim_time} = $Self->{benchmark} * 100 if $Self->{benchmark}; - -my $secret_prefix = "secret"; -my $secret_dir = "$Self->{obj_dir}/$secret_prefix"; -mkdir $secret_dir; - -while (1) { - # Always compile the secret file with Verilator no matter what simulator - # we are testing with - run(logfile => "$secret_dir/vlt_compile.log", - cmd => ["perl", - "$ENV{VERILATOR_ROOT}/bin/verilator", - '--no-timing', - "--prefix", - "Vt_lib_prot_secret", - "-cc", - "-Mdir", - $secret_dir, - "--lib-create", - $secret_prefix, - "t/t_lib_prot_secret.v"], - verilator_run => 1, - ); - last if $Self->{errors}; - - run(logfile => "$secret_dir/secret_gcc.log", - cmd=>[$ENV{MAKE}, - "-C", - $secret_dir, - "-f", - "Vt_lib_prot_secret.mk"]); - last if $Self->{errors}; - - compile( - verilator_flags2 => ["$secret_dir/secret.sv", - '--no-timing', - "-LDFLAGS", - "$secret_prefix/libsecret.a"], - xsim_flags2 => ["$secret_dir/secret.sv"], - ); - - execute( - xsim_run_flags2 => ["--sv_lib", - "$secret_dir/libsecret", - "--dpi_absolute"], - ); - - ok(1); - last; -} -1; diff --git a/test_regress/t/t_lib.py b/test_regress/t/t_lib.py new file mode 100755 index 000000000..ddd055e11 --- /dev/null +++ b/test_regress/t/t_lib.py @@ -0,0 +1,49 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt', 'xsim') +test.top_filename = "t/t_lib_prot.v" +if test.benchmark: + test.sim_time = test.benchmark * 100 + +trace_opt = "" if re.search(r'--no-trace', ' '.join(test.driver_verilator_flags)) else "-trace" + +secret_prefix = "secret" +secret_dir = test.obj_dir + "/" + secret_prefix +test.mkdir_ok(secret_dir) + +while True: + # Always compile the secret file with Verilator no matter what simulator + # we are testing with + test.run(logfile=secret_dir + "/vlt_compile.log", + cmd=["perl", os.environ["VERILATOR_ROOT"] + "/bin/verilator", + '--no-timing', + trace_opt, + "--prefix", "Vt_lib_prot_secret", + "-cc", + "-Mdir", secret_dir, + "--lib-create", secret_prefix, + "t/t_lib_prot_secret.v"], + verilator_run=True) # yapf:disable + + test.run(logfile=secret_dir + "/secret_gcc.log", + cmd=[os.environ["MAKE"], "-C", secret_dir, "-f", "Vt_lib_prot_secret.mk"]) + + test.compile(verilator_flags2=['--no-timing', + trace_opt, + "-LDFLAGS", secret_prefix + "/libsecret.a", + secret_dir + "/secret.sv"], + xsim_flags2=[secret_dir + "/secret.sv"]) # yapf:disable + + test.execute(xsim_run_flags2=["--sv_lib", secret_dir + "/libsecret", "--dpi_absolute"]) + + test.passes() + break diff --git a/test_regress/t/t_lib_nolib.pl b/test_regress/t/t_lib_nolib.pl deleted file mode 100755 index 55c4d8892..000000000 --- a/test_regress/t/t_lib_nolib.pl +++ /dev/null @@ -1,36 +0,0 @@ -#!/usr/bin/env perl -# Makes the test run with tracing enabled by default, can be overridden -# with --notrace -unshift(@ARGV, "--trace"); -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Todd Strader. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1, xsim => 1); - -$Self->{sim_time} = $Self->{benchmark} * 100 if $Self->{benchmark}; -top_filename("t/t_lib_prot.v"); - -# Tests the same code as t_lib_prot.pl but without --protect-lib -compile( - verilator_flags2 => ["t/t_lib_prot_secret.v", '--no-timing'], - xsim_flags2 => ["t/t_lib_prot_secret.v"], - ); - -execute( - ); - -if ($Self->{vlt} && $Self->{trace}) { - # We can see the ports of the secret module - file_grep($Self->trace_filename, qr/accum_in/); - # and we can see what's inside (because we didn't use --protect-lib) - file_grep($Self->trace_filename, qr/secret_/); -} - -ok(1); -1; diff --git a/test_regress/t/t_lib_nolib.py b/test_regress/t/t_lib_nolib.py new file mode 100755 index 000000000..3c4e861ab --- /dev/null +++ b/test_regress/t/t_lib_nolib.py @@ -0,0 +1,32 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all', 'xsim') +test.top_filename = "t/t_lib_prot.v" + +if test.benchmark: + test.sim_time = test.benchmark * 100 + +trace_opt = ("" if re.search(r'--no-trace', ' '.join(test.driver_verilator_flags)) else "-trace") + +# Tests the same code as t_lib_prot.py but without --protect-lib +test.compile(verilator_flags2=['--no-timing', trace_opt, "t/t_lib_prot_secret.v"], + xsim_flags2=["t/t_lib_prot_secret.v"]) + +test.execute() + +if test.vlt and test.trace: + # We can see the ports of the secret module + test.file_grep(test.trace_filename, r'accum_in') + # and we can see what's inside (because we didn't use --protect-lib) + test.file_grep(test.trace_filename, r'secret_') + +test.passes() diff --git a/test_regress/t/t_lib_prot.pl b/test_regress/t/t_lib_prot.pl deleted file mode 100755 index b058ca0b7..000000000 --- a/test_regress/t/t_lib_prot.pl +++ /dev/null @@ -1,75 +0,0 @@ -#!/usr/bin/env perl -# Makes the test run with tracing enabled by default, can be overridden -# with --notrace -unshift(@ARGV, "--trace"); -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Todd Strader. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1, xsim => 1); - -$Self->{sim_time} = $Self->{benchmark} * 100 if $Self->{benchmark}; - -my $secret_prefix = "secret"; -my $secret_dir = "$Self->{obj_dir}/$secret_prefix"; -mkdir $secret_dir; - -while (1) { - # Always compile the secret file with Verilator no matter what simulator - # we are testing with - run(logfile => "$secret_dir/vlt_compile.log", - cmd => ["perl", - "$ENV{VERILATOR_ROOT}/bin/verilator", - '--no-timing', - "--prefix", - "Vt_lib_prot_secret", - "-cc", - "-Mdir", - $secret_dir, - "--protect-lib", - $secret_prefix, - "--protect-key", - "secret-key", - "t/t_lib_prot_secret.v"], - verilator_run => 1, - ); - last if $Self->{errors}; - - run(logfile => "$secret_dir/secret_gcc.log", - cmd=>[$ENV{MAKE}, - "-C", - $secret_dir, - "-f", - "Vt_lib_prot_secret.mk"]); - last if $Self->{errors}; - - compile( - verilator_flags2 => ["$secret_dir/secret.sv", - '--no-timing', - "-LDFLAGS", - "$secret_prefix/libsecret.a"], - xsim_flags2 => ["$secret_dir/secret.sv"], - ); - - execute( - xsim_run_flags2 => ["--sv_lib", - "$secret_dir/libsecret", - "--dpi_absolute"], - ); - - if ($Self->{vlt} && $Self->{trace}) { - # We can see the ports of the secret module - file_grep($Self->trace_filename, qr/accum_in/); - # but we can't see what's inside - file_grep_not($Self->trace_filename, qr/secret_/); - } - - ok(1); - last; -} -1; diff --git a/test_regress/t/t_lib_prot.py b/test_regress/t/t_lib_prot.py new file mode 100755 index 000000000..fdec419c3 --- /dev/null +++ b/test_regress/t/t_lib_prot.py @@ -0,0 +1,53 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt', 'xsim') + +if test.benchmark: + test.sim_time = test.benchmark * 100 + +secret_prefix = "secret" +secret_dir = test.obj_dir + "/" + secret_prefix +test.mkdir_ok(secret_dir) +trace_opt = "" + +# Always compile the secret file with Verilator no matter what simulator +# we are testing with +test.run(logfile=secret_dir + "/vlt_compile.log", + cmd=["perl", os.environ["VERILATOR_ROOT"] + "/bin/verilator", + '--no-timing', + trace_opt, + "--prefix", "Vt_lib_prot_secret", + "-cc", + "-Mdir", secret_dir, + "--protect-lib", secret_prefix, + "--protect-key", "secret-key", + "t/t_lib_prot_secret.v"], + verilator_run=True) # yapf:disable + +test.run(logfile=secret_dir + "/secret_gcc.log", + cmd=[os.environ["MAKE"], "-C", secret_dir, "-f", "Vt_lib_prot_secret.mk"]) + +test.compile(verilator_flags2=['--no-timing', + trace_opt, + "-LDFLAGS", secret_prefix + "/libsecret.a", + secret_dir + "/secret.sv"], + xsim_flags2=[secret_dir + "/secret.sv"]) # yapf:disable + +test.execute(xsim_run_flags2=["--sv_lib", secret_dir + "/libsecret", "--dpi_absolute"]) + +if test.vlt and test.trace: + # We can see the ports of the secret module + test.file_grep(test.trace_filename, r'accum_in') + # but we can't see what's inside + test.file_grep_not(test.trace_filename, r'secret_') + +test.passes() diff --git a/test_regress/t/t_lib_prot_clk_gated.pl b/test_regress/t/t_lib_prot_clk_gated.pl deleted file mode 100755 index 32a03d28f..000000000 --- a/test_regress/t/t_lib_prot_clk_gated.pl +++ /dev/null @@ -1,78 +0,0 @@ -#!/usr/bin/env perl -# Makes the test run with tracing enabled by default, can be overridden -# with --notrace -unshift(@ARGV, "--trace"); -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Todd Strader. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1, xsim => 1); - -$Self->{sim_time} = $Self->{benchmark} * 100 if $Self->{benchmark}; - -top_filename("t/t_lib_prot.v"); -my $secret_prefix = "secret"; -my $secret_dir = "$Self->{obj_dir}/$secret_prefix"; -mkdir $secret_dir; - -while (1) { - # Always compile the secret file with Verilator no matter what simulator - # we are testing with - run(logfile => "$secret_dir/vlt_compile.log", - cmd => ["perl", - "$ENV{VERILATOR_ROOT}/bin/verilator", - '--no-timing', - "--prefix", - "Vt_lib_prot_secret", - "-cc", - "-Mdir", - $secret_dir, - "-GGATED_CLK=1", - "--protect-lib", - $secret_prefix, - "--protect-key", - "secret-key", - "t/t_lib_prot_secret.v"], - verilator_run => 1, - ); - last if $Self->{errors}; - - run(logfile => "$secret_dir/secret_gcc.log", - cmd=>[$ENV{MAKE}, - "-C", - $secret_dir, - "-f", - "Vt_lib_prot_secret.mk"]); - last if $Self->{errors}; - - compile( - verilator_flags2 => ["$secret_dir/secret.sv", - '--no-timing', - "-GGATED_CLK=1", - "-LDFLAGS", - "$secret_prefix/libsecret.a"], - xsim_flags2 => ["$secret_dir/secret.sv"], - ); - - execute( - xsim_run_flags2 => ["--sv_lib", - "$secret_dir/libsecret", - "--dpi_absolute"], - ); - - if ($Self->{vlt} && $Self->{trace}) { - # We can see the ports of the secret module - file_grep($Self->trace_filename, qr/accum_in/); - # but we can't see what's inside - file_grep_not($Self->trace_filename, qr/secret_/); - } - - ok(1); - last; -} -1; diff --git a/test_regress/t/t_lib_prot_clk_gated.py b/test_regress/t/t_lib_prot_clk_gated.py new file mode 100755 index 000000000..c7e7c897f --- /dev/null +++ b/test_regress/t/t_lib_prot_clk_gated.py @@ -0,0 +1,58 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt', 'xsim') +test.top_filename = "t/t_lib_prot.v" + +if test.benchmark: + test.sim_time = test.benchmark * 100 + +trace_opt = "" + +secret_prefix = "secret" +secret_dir = test.obj_dir + "/" + secret_prefix +test.mkdir_ok(secret_dir) + +# Always compile the secret file with Verilator no matter what simulator +# we are testing with +test.run( + logfile=secret_dir + "/vlt_compile.log", + cmd=["perl", os.environ["VERILATOR_ROOT"] + "/bin/verilator", + '--no-timing', + trace_opt, + "--prefix", "Vt_lib_prot_secret", + "-cc", + "-Mdir", secret_dir, + "-GGATED_CLK=1", + "--protect-lib", secret_prefix, + "--protect-key", "secret-key", + "t/t_lib_prot_secret.v"], + verilator_run=True) # yapf:disable + +test.run(logfile=secret_dir + "/secret_gcc.log", + cmd=[os.environ["MAKE"], "-C", secret_dir, "-f", "Vt_lib_prot_secret.mk"]) + +test.compile(verilator_flags2=['--no-timing', + trace_opt, + "-GGATED_CLK=1", + "-LDFLAGS", secret_prefix + "/libsecret.a", + secret_dir + "/secret.sv"], + xsim_flags2=[secret_dir + "/secret.sv"]) # yapf:disable + +test.execute(xsim_run_flags2=["--sv_lib", secret_dir + "/libsecret", "--dpi_absolute"]) + +if test.vlt and test.trace: + # We can see the ports of the secret module + test.file_grep(test.trace_filename, r'accum_in') + # but we can't see what's inside + test.file_grep_not(test.trace_filename, r'secret_') + +test.passes() diff --git a/test_regress/t/t_lib_prot_comb.pl b/test_regress/t/t_lib_prot_comb.pl deleted file mode 100755 index 09ac0144d..000000000 --- a/test_regress/t/t_lib_prot_comb.pl +++ /dev/null @@ -1,67 +0,0 @@ -#!/usr/bin/env perl -# Makes the test run with tracing enabled by default, can be overridden -# with --notrace -unshift(@ARGV, "--trace"); -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Todd Strader. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1, xsim => 1); - -$Self->{sim_time} = $Self->{benchmark} * 100 if $Self->{benchmark}; - -my $secret_prefix = "secret"; -my $secret_dir = "$Self->{obj_dir}/$secret_prefix"; -mkdir $secret_dir; - -while (1) { - # Always compile the secret file with Verilator no matter what simulator - # we are testing with - run(logfile => "$secret_dir/vlt_compile.log", - cmd => ["perl", - "$ENV{VERILATOR_ROOT}/bin/verilator", - "--prefix", - "Vt_lib_prot_secret", - "-cc", - "-Mdir", - $secret_dir, - "--protect-lib", - $secret_prefix, - "--protect-key", - "secret-key", - "t/t_lib_prot_comb.v"], - verilator_run => 1, - ); - last if $Self->{errors}; - - run(logfile => "$secret_dir/secret_gcc.log", - cmd=>[$ENV{MAKE}, - "-C", - $secret_dir, - "-f", - "Vt_lib_prot_secret.mk"]); - last if $Self->{errors}; - - compile( - verilator_flags2 => ["$secret_dir/secret.sv", - "+define+PROCESS_TOP", - "-LDFLAGS", - "$secret_prefix/libsecret.a"], - xsim_flags2 => ["$secret_dir/secret.sv"], - ); - - execute( - xsim_run_flags2 => ["--sv_lib", - "$secret_dir/libsecret", - "--dpi_absolute"], - ); - - ok(1); - last; -} -1; diff --git a/test_regress/t/t_lib_prot_comb.py b/test_regress/t/t_lib_prot_comb.py new file mode 100755 index 000000000..4a314fcbd --- /dev/null +++ b/test_regress/t/t_lib_prot_comb.py @@ -0,0 +1,49 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all', 'xsim') + +if test.benchmark: + test.sim_time = test.benchmark * 100 + +trace_opt = "" + +secret_prefix = "secret" +secret_dir = test.obj_dir + "/" + secret_prefix +test.mkdir_ok(secret_dir) + +# Always compile the secret file with Verilator no matter what simulator +# we are testing with +test.run( + logfile=secret_dir + "/vlt_compile.log", + cmd=["perl", os.environ["VERILATOR_ROOT"] + "/bin/verilator", + "-cc", + trace_opt, + "--prefix", "Vt_lib_prot_secret", + "-Mdir", secret_dir, + "--protect-lib", secret_prefix, + "--protect-key", "secret-key", + "t/t_lib_prot_comb.v"], + verilator_run=True) # yapf:disable + +test.run(logfile=secret_dir + "/secret_gcc.log", + cmd=[os.environ["MAKE"], "-C", secret_dir, "-f", "Vt_lib_prot_secret.mk"]) + +test.compile( + verilator_flags2=[ + secret_dir + "/secret.sv", + "+define+PROCESS_TOP", + "-LDFLAGS",secret_prefix + "/libsecret.a"], + xsim_flags2=[secret_dir + "/secret.sv"]) # yapf:disable + +test.execute(xsim_run_flags2=["--sv_lib", secret_dir + "/libsecret", "--dpi_absolute"]) + +test.passes() diff --git a/test_regress/t/t_lib_prot_delay_bad.pl b/test_regress/t/t_lib_prot_delay_bad.pl deleted file mode 100755 index 802270587..000000000 --- a/test_regress/t/t_lib_prot_delay_bad.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Todd Strader. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile ( - verilator_flags2 => ["--protect-lib", - "secret", - "--protect-key", - "secret-key", - "--timing", - ], - verilator_make_gcc => 0, - make_main => 0, - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lib_prot_delay_bad.py b/test_regress/t/t_lib_prot_delay_bad.py new file mode 100755 index 000000000..edbc0bdc5 --- /dev/null +++ b/test_regress/t/t_lib_prot_delay_bad.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=[ + "--protect-lib", + "secret", + "--protect-key", + "secret-key", + "--timing", +], + verilator_make_gcc=False, + make_main=False, + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lib_prot_exe_bad.pl b/test_regress/t/t_lib_prot_exe_bad.pl deleted file mode 100755 index 9700f4120..000000000 --- a/test_regress/t/t_lib_prot_exe_bad.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile ( - verilator_flags2 => ["--protect-lib", - "secret", - "--protect-key", - "secret-key", - ], - verilator_make_gcc => 0, - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lib_prot_exe_bad.py b/test_regress/t/t_lib_prot_exe_bad.py new file mode 100755 index 000000000..236b2a27a --- /dev/null +++ b/test_regress/t/t_lib_prot_exe_bad.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=[ + "--protect-lib", + "secret", + "--protect-key", + "secret-key", +], + verilator_make_gcc=False, + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lib_prot_inout_bad.pl b/test_regress/t/t_lib_prot_inout_bad.pl deleted file mode 100755 index 375b280ce..000000000 --- a/test_regress/t/t_lib_prot_inout_bad.pl +++ /dev/null @@ -1,32 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Todd Strader. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile ( - verilator_flags2 => ["--protect-lib", - "secret", - "--protect-key", - "secret-key" - ], - verilator_make_gcc => 0, - make_main => 0, - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -#run(cmd=>["make", -# "-C", -# "$Self->{obj_dir}", -# "-f", -# "V$Self->{name}.mk"]); - -ok(1); -1; diff --git a/test_regress/t/t_lib_prot_inout_bad.py b/test_regress/t/t_lib_prot_inout_bad.py new file mode 100755 index 000000000..4ca020c38 --- /dev/null +++ b/test_regress/t/t_lib_prot_inout_bad.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--protect-lib", "secret", "--protect-key", "secret-key"], + verilator_make_gcc=False, + make_main=False, + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lib_prot_secret.pl b/test_regress/t/t_lib_prot_secret.pl deleted file mode 100755 index 18efa9ff7..000000000 --- a/test_regress/t/t_lib_prot_secret.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Todd Strader. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile ( - verilator_flags2 => ["--protect-lib", - "secret", - "--protect-key", - "SECRET_FAKE_KEY"], - verilator_make_gcc => 0, - verilator_make_gmake => 0, - make_main => 0, - make_top_shell => 0, - ); - -run(cmd=>[$ENV{MAKE}, - "-C", - "$Self->{obj_dir}", - "-f", - "V$Self->{name}.mk"]); - -ok(1); -1; diff --git a/test_regress/t/t_lib_prot_secret.py b/test_regress/t/t_lib_prot_secret.py new file mode 100755 index 000000000..d0e834c5a --- /dev/null +++ b/test_regress/t/t_lib_prot_secret.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--protect-lib", "secret", "--protect-key", "SECRET_FAKE_KEY"], + verilator_make_gcc=False, + verilator_make_gmake=False, + make_main=False, + make_top_shell=False) + +test.run(cmd=[os.environ["MAKE"], "-C", test.obj_dir, "-f", "V" + test.name + ".mk"]) + +test.passes() diff --git a/test_regress/t/t_lib_prot_shared.pl b/test_regress/t/t_lib_prot_shared.pl deleted file mode 100755 index da37b466b..000000000 --- a/test_regress/t/t_lib_prot_shared.pl +++ /dev/null @@ -1,81 +0,0 @@ -#!/usr/bin/env perl -# Makes the test run with tracing enabled by default, can be overridden -# with --notrace -unshift(@ARGV, "--trace"); -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Todd Strader. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1, xsim => 1); -top_filename("t/t_lib_prot.v"); - -$Self->{sim_time} = $Self->{benchmark} * 100 if $Self->{benchmark}; - -my $secret_prefix = "secret"; -my $secret_dir = "$Self->{obj_dir}/$secret_prefix"; -my $abs_secret_dir = File::Spec->rel2abs($secret_dir); -mkdir $secret_dir; - -while (1) { - # Always compile the secret file with Verilator no matter what simulator - # we are testing with - run(logfile => "$secret_dir/vlt_compile.log", - cmd => ["perl", - "$ENV{VERILATOR_ROOT}/bin/verilator", - ($Self->{vltmt} ? ' --threads 6' : ''), - '--no-timing', - "--prefix", - "Vt_lib_prot_secret", - "-cc", - "-Mdir", - $secret_dir, - "--protect-lib", - $secret_prefix, - "--protect-key", - "secret-key", - "t/t_lib_prot_secret.v"], - verilator_run => 1, - ); - last if $Self->{errors}; - - run(logfile => "$secret_dir/secret_gcc.log", - cmd=>[$ENV{MAKE}, - "-C", - $secret_dir, - "-f", - "Vt_lib_prot_secret.mk"]); - last if $Self->{errors}; - - compile( - verilator_flags2 => ["$secret_dir/secret.sv", - '--no-timing', - "-LDFLAGS", - "'-Wl,-rpath,$abs_secret_dir -L$abs_secret_dir -l$secret_prefix'"], - xsim_flags2 => ["$secret_dir/secret.sv"], - threads => 1, - context_threads => $Self->{vltmt} ? 6 : 1 - ); - - execute( - run_env => "DYLD_FALLBACK_LIBRARY_PATH=$abs_secret_dir", - xsim_run_flags2 => ["--sv_lib", - "$secret_dir/libsecret", - "--dpi_absolute"], - ); - - if ($Self->{vlt} && $Self->{trace}) { - # We can see the ports of the secret module - file_grep($Self->trace_filename, qr/accum_in/); - # but we can't see what's inside - file_grep_not($Self->trace_filename, qr/secret_/); - } - - ok(1); - last; -} -1; diff --git a/test_regress/t/t_lib_prot_shared.py b/test_regress/t/t_lib_prot_shared.py new file mode 100755 index 000000000..17f750203 --- /dev/null +++ b/test_regress/t/t_lib_prot_shared.py @@ -0,0 +1,58 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all', 'xsim') +test.top_filename = "t/t_lib_prot.v" + +if test.benchmark: + test.sim_time = test.benchmark * 100 + +trace_opt = "" if re.search(r'--no-trace', ' '.join(test.driver_verilator_flags)) else "-trace" + +secret_prefix = "secret" +secret_dir = test.obj_dir + "/" + secret_prefix +abs_secret_dir = os.path.abspath(secret_dir) +test.mkdir_ok(secret_dir) + +# Always compile the secret file with Verilator no matter what simulator +# we are testing with +test.run(logfile=secret_dir + "/vlt_compile.log", + cmd=["perl", os.environ["VERILATOR_ROOT"] + "/bin/verilator", + (' --threads 6' if test.vltmt else ''), + '--no-timing', + "--prefix", "Vt_lib_prot_secret", + "-cc", + "-Mdir", secret_dir, + "--protect-lib", secret_prefix, + "--protect-key", "secret-key", + "t/t_lib_prot_secret.v"], + verilator_run=True) # yapf:disable + +test.run(logfile=secret_dir + "/secret_gcc.log", + cmd=[os.environ["MAKE"], "-C", secret_dir, "-f", "Vt_lib_prot_secret.mk"]) + +test.compile(verilator_flags2=['--no-timing', + "-LDFLAGS", "'-Wl,-rpath," + abs_secret_dir + " -L" + abs_secret_dir + " -l" + secret_prefix + "'", + secret_dir + "/secret.sv"], + xsim_flags2=[secret_dir + "/secret.sv"], + threads=1, + context_threads=(6 if test.vltmt else 1)) # yapf:disable + +test.execute(run_env="DYLD_FALLBACK_LIBRARY_PATH=" + abs_secret_dir, + xsim_run_flags2=["--sv_lib", secret_dir + "/libsecret", "--dpi_absolute"]) + +if test.vlt and test.trace: + # We can see the ports of the secret module + test.file_grep(test.trace_filename, r'accum_in') + # but we can't see what's inside + test.file_grep_not(test.trace_filename, r'secret_') + +test.passes() diff --git a/test_regress/t/t_lint_always_comb_bad.pl b/test_regress/t/t_lint_always_comb_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_lint_always_comb_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_always_comb_bad.py b/test_regress/t/t_lint_always_comb_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_lint_always_comb_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_always_comb_iface.pl b/test_regress/t/t_lint_always_comb_iface.pl deleted file mode 100755 index 7918d5f13..000000000 --- a/test_regress/t/t_lint_always_comb_iface.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_lint_always_comb_iface.py b/test_regress/t/t_lint_always_comb_iface.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_lint_always_comb_iface.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_lint_always_comb_multidriven_bad.pl b/test_regress/t/t_lint_always_comb_multidriven_bad.pl deleted file mode 100755 index 4786ecc50..000000000 --- a/test_regress/t/t_lint_always_comb_multidriven_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ['--lint-only'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_always_comb_multidriven_bad.py b/test_regress/t/t_lint_always_comb_multidriven_bad.py new file mode 100755 index 000000000..d6dde1012 --- /dev/null +++ b/test_regress/t/t_lint_always_comb_multidriven_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=['--lint-only'], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_always_comb_multidriven_compile_public_flat_bad.pl b/test_regress/t/t_lint_always_comb_multidriven_compile_public_flat_bad.pl deleted file mode 100755 index 48576365b..000000000 --- a/test_regress/t/t_lint_always_comb_multidriven_compile_public_flat_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_lint_always_comb_multidriven_bad.v"); - -lint( - verilator_flags2 => ['--public-flat-rw --lint-only'], - fails => 1, - expect_filename => "t/t_lint_always_comb_multidriven_bad.out", - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_always_comb_multidriven_compile_public_flat_bad.py b/test_regress/t/t_lint_always_comb_multidriven_compile_public_flat_bad.py new file mode 100755 index 000000000..58bab8994 --- /dev/null +++ b/test_regress/t/t_lint_always_comb_multidriven_compile_public_flat_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_lint_always_comb_multidriven_bad.v" + +test.lint(verilator_flags2=['--public-flat-rw --lint-only'], + fails=True, + expect_filename="t/t_lint_always_comb_multidriven_bad.out") + +test.passes() diff --git a/test_regress/t/t_lint_blksync_bad.pl b/test_regress/t/t_lint_blksync_bad.pl deleted file mode 100755 index 57bd2d964..000000000 --- a/test_regress/t/t_lint_blksync_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only -Wwarn-BLKSEQ -Wwarn-COMBDLY"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_blksync_bad.py b/test_regress/t/t_lint_blksync_bad.py new file mode 100755 index 000000000..f27c3eae1 --- /dev/null +++ b/test_regress/t/t_lint_blksync_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only -Wwarn-BLKSEQ -Wwarn-COMBDLY"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_blksync_loop.pl b/test_regress/t/t_lint_blksync_loop.pl deleted file mode 100755 index 8a474235a..000000000 --- a/test_regress/t/t_lint_blksync_loop.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only -Wwarn-BLKSEQ -Wwarn-COMBDLY"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_blksync_loop.py b/test_regress/t/t_lint_blksync_loop.py new file mode 100755 index 000000000..e822338c0 --- /dev/null +++ b/test_regress/t/t_lint_blksync_loop.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only -Wwarn-BLKSEQ -Wwarn-COMBDLY"]) + +test.passes() diff --git a/test_regress/t/t_lint_block_redecl_bad.pl b/test_regress/t/t_lint_block_redecl_bad.pl deleted file mode 100755 index b5861b2ab..000000000 --- a/test_regress/t/t_lint_block_redecl_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_block_redecl_bad.py b/test_regress/t/t_lint_block_redecl_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_lint_block_redecl_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_bsspace_bad.pl b/test_regress/t/t_lint_bsspace_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_lint_bsspace_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_bsspace_bad.py b/test_regress/t/t_lint_bsspace_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_lint_bsspace_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_caseincomplete_bad.pl b/test_regress/t/t_lint_caseincomplete_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_lint_caseincomplete_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_caseincomplete_bad.py b/test_regress/t/t_lint_caseincomplete_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_lint_caseincomplete_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_cmpconst_bad.pl b/test_regress/t/t_lint_cmpconst_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_lint_cmpconst_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_cmpconst_bad.py b/test_regress/t/t_lint_cmpconst_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_lint_cmpconst_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_colonplus_bad.pl b/test_regress/t/t_lint_colonplus_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_lint_colonplus_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_colonplus_bad.py b/test_regress/t/t_lint_colonplus_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_lint_colonplus_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_comb_bad.pl b/test_regress/t/t_lint_comb_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_lint_comb_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_comb_bad.py b/test_regress/t/t_lint_comb_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_lint_comb_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_comb_use.pl b/test_regress/t/t_lint_comb_use.pl deleted file mode 100755 index 9c58f64a3..000000000 --- a/test_regress/t/t_lint_comb_use.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only --bbox-sys"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_comb_use.py b/test_regress/t/t_lint_comb_use.py new file mode 100755 index 000000000..b39e4b760 --- /dev/null +++ b/test_regress/t/t_lint_comb_use.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only --bbox-sys"]) + +test.passes() diff --git a/test_regress/t/t_lint_const_func_dpi_bad.pl b/test_regress/t/t_lint_const_func_dpi_bad.pl deleted file mode 100755 index b5861b2ab..000000000 --- a/test_regress/t/t_lint_const_func_dpi_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_const_func_dpi_bad.py b/test_regress/t/t_lint_const_func_dpi_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_lint_const_func_dpi_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_const_func_gen_bad.pl b/test_regress/t/t_lint_const_func_gen_bad.pl deleted file mode 100755 index b5861b2ab..000000000 --- a/test_regress/t/t_lint_const_func_gen_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_const_func_gen_bad.py b/test_regress/t/t_lint_const_func_gen_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_lint_const_func_gen_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_contassreg_bad.pl b/test_regress/t/t_lint_contassreg_bad.pl deleted file mode 100755 index 46010fd1c..000000000 --- a/test_regress/t/t_lint_contassreg_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ['--language 1364-2001'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_contassreg_bad.py b/test_regress/t/t_lint_contassreg_bad.py new file mode 100755 index 000000000..129a49d56 --- /dev/null +++ b/test_regress/t/t_lint_contassreg_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=['--language 1364-2001'], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_declfilename.pl b/test_regress/t/t_lint_declfilename.pl deleted file mode 100755 index 1366501ca..000000000 --- a/test_regress/t/t_lint_declfilename.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_lint_declfilename.py b/test_regress/t/t_lint_declfilename.py new file mode 100755 index 000000000..f81c3d68d --- /dev/null +++ b/test_regress/t/t_lint_declfilename.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_lint_declfilename_bad.pl b/test_regress/t/t_lint_declfilename_bad.pl deleted file mode 100755 index a884e811f..000000000 --- a/test_regress/t/t_lint_declfilename_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_lint_declfilename.v"); - -lint( - verilator_flags2 => ["--lint-only -Wall"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_declfilename_bad.py b/test_regress/t/t_lint_declfilename_bad.py new file mode 100755 index 000000000..8877eb52f --- /dev/null +++ b/test_regress/t/t_lint_declfilename_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_lint_declfilename.v" + +test.lint(verilator_flags2=["--lint-only -Wall"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_declfilename_bbox.pl b/test_regress/t/t_lint_declfilename_bbox.pl deleted file mode 100755 index f73da325a..000000000 --- a/test_regress/t/t_lint_declfilename_bbox.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only -Wall"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_declfilename_bbox.py b/test_regress/t/t_lint_declfilename_bbox.py new file mode 100755 index 000000000..f31da0fcd --- /dev/null +++ b/test_regress/t/t_lint_declfilename_bbox.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only -Wall"]) + +test.passes() diff --git a/test_regress/t/t_lint_defparam.pl b/test_regress/t/t_lint_defparam.pl deleted file mode 100755 index 1366501ca..000000000 --- a/test_regress/t/t_lint_defparam.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_lint_defparam.py b/test_regress/t/t_lint_defparam.py new file mode 100755 index 000000000..f81c3d68d --- /dev/null +++ b/test_regress/t/t_lint_defparam.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_lint_defparam_bad.pl b/test_regress/t/t_lint_defparam_bad.pl deleted file mode 100755 index 9b7fa451e..000000000 --- a/test_regress/t/t_lint_defparam_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_lint_defparam.v"); - -lint( - verilator_flags2 => ["--lint-only -Wwarn-style -Wno-DECLFILENAME"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_defparam_bad.py b/test_regress/t/t_lint_defparam_bad.py new file mode 100755 index 000000000..a707e9afc --- /dev/null +++ b/test_regress/t/t_lint_defparam_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_lint_defparam.v" + +test.lint(verilator_flags2=["--lint-only -Wwarn-style -Wno-DECLFILENAME"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_didnotconverge_bad.pl b/test_regress/t/t_lint_didnotconverge_bad.pl deleted file mode 100755 index 7e7872f63..000000000 --- a/test_regress/t/t_lint_didnotconverge_bad.pl +++ /dev/null @@ -1,39 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $root = ".."; - -if (!-r "$root/.git") { - skip("Not in a git repository"); -} else { - compile( - verilator_flags2 => ["--prof-cfuncs"], - ); - - execute( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - - extract( - in => $Self->{top_filename}, - out => "../docs/gen/ex_DIDNOTCONVERGE_faulty.rst", - lines => "16-17"); - - extract( - in => $Self->{golden_filename}, - out => "../docs/gen/ex_DIDNOTCONVERGE_msg.rst", - lines => "1-2"); -} - -ok(1); -1; diff --git a/test_regress/t/t_lint_didnotconverge_bad.py b/test_regress/t/t_lint_didnotconverge_bad.py new file mode 100755 index 000000000..40e40f26e --- /dev/null +++ b/test_regress/t/t_lint_didnotconverge_bad.py @@ -0,0 +1,31 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +root = ".." + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +test.compile(verilator_flags2=["--prof-cfuncs"]) + +test.execute(fails=True, expect_filename=test.golden_filename) + +test.extract(in_filename=test.top_filename, + out_filename="../docs/gen/ex_DIDNOTCONVERGE_faulty.rst", + lines="16-17") + +test.extract(in_filename=test.golden_filename, + out_filename="../docs/gen/ex_DIDNOTCONVERGE_msg.rst", + lines="1-2") + +test.passes() diff --git a/test_regress/t/t_lint_didnotconverge_nodbg_bad.pl b/test_regress/t/t_lint_didnotconverge_nodbg_bad.pl deleted file mode 100755 index b0de186ba..000000000 --- a/test_regress/t/t_lint_didnotconverge_nodbg_bad.pl +++ /dev/null @@ -1,36 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $root = ".."; - -if (!-r "$root/.git") { - skip("Not in a git repository"); -} else { - top_filename("t/t_lint_didnotconverge_bad.v"); - - compile( - make_flags => 'CPPFLAGS_ADD=-UVL_DEBUG', - ); - - execute( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - - extract( - in => $Self->{golden_filename}, - out => "../docs/gen/ex_DIDNOTCONVERGE_nodbg_msg.rst", - lines => "1"); -} - -ok(1); -1; diff --git a/test_regress/t/t_lint_didnotconverge_nodbg_bad.py b/test_regress/t/t_lint_didnotconverge_nodbg_bad.py new file mode 100755 index 000000000..1d53c8c93 --- /dev/null +++ b/test_regress/t/t_lint_didnotconverge_nodbg_bad.py @@ -0,0 +1,28 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_lint_didnotconverge_bad.v" + +root = ".." + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +test.compile(make_flags=['CPPFLAGS_ADD=-UVL_DEBUG']) + +test.execute(fails=True, expect_filename=test.golden_filename) + +test.extract(in_filename=test.golden_filename, + out_filename="../docs/gen/ex_DIDNOTCONVERGE_nodbg_msg.rst", + lines="1") + +test.passes() diff --git a/test_regress/t/t_lint_edge_real_bad.pl b/test_regress/t/t_lint_edge_real_bad.pl deleted file mode 100755 index 07964a1b5..000000000 --- a/test_regress/t/t_lint_edge_real_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_edge_real_bad.py b/test_regress/t/t_lint_edge_real_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_lint_edge_real_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_eofline.pl b/test_regress/t/t_lint_eofline.pl deleted file mode 100755 index 709ff432e..000000000 --- a/test_regress/t/t_lint_eofline.pl +++ /dev/null @@ -1,34 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -use IO::File; -use strict; -use vars qw($Self); - -scenarios(vlt => 1); - -sub gen { - my $filename = shift; - - my $fh = IO::File->new(">$filename"); - # Empty file should not EOFLINE warn -} - -top_filename("$Self->{obj_dir}/t_lint_eofline_bad.v"); - -gen($Self->{top_filename}); - -lint( - verilator_flags2 => ["-E -Wall -Wno-DECLFILENAME"], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_eofline.py b/test_regress/t/t_lint_eofline.py new file mode 100755 index 000000000..0c46692ef --- /dev/null +++ b/test_regress/t/t_lint_eofline.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = test.obj_dir + "/t_lint_eofline_bad.v" + + +def gen(filename): + with open(filename, 'w', encoding="utf8") as fh: # pylint: disable=unused-variable + pass + # Empty file should not EOFLINE warn + + +gen(test.top_filename) + +test.lint(verilator_flags2=["-E -Wall -Wno-DECLFILENAME"], expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_eofline_bad.pl b/test_regress/t/t_lint_eofline_bad.pl deleted file mode 100755 index 1528e4cef..000000000 --- a/test_regress/t/t_lint_eofline_bad.pl +++ /dev/null @@ -1,38 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -use IO::File; -use strict; -use vars qw($Self); - -scenarios(vlt => 1); - -sub gen { - my $filename = shift; - - my $fh = IO::File->new(">$filename"); - $fh->print("// Generated by t_lint_eofline_bad.pl\n"); - $fh->print("module t;\n"); - $fh->print("// No newline below:\n"); - $fh->print("endmodule"); # Intentionally no newline -} - -top_filename("$Self->{obj_dir}/t_lint_eofline_bad.v"); - -gen($Self->{top_filename}); - -lint( - verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_eofline_bad.py b/test_regress/t/t_lint_eofline_bad.py new file mode 100755 index 000000000..c39e86fc6 --- /dev/null +++ b/test_regress/t/t_lint_eofline_bad.py @@ -0,0 +1,31 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = test.obj_dir + "/t_lint_eofline_bad.v" + + +def gen(filename): + with open(filename, 'w', encoding="utf8") as fh: + fh.write("// Generated by t_lint_eofline_bad.py\n") + fh.write("module t;\n") + fh.write("// No newline below:\n") + fh.write("endmodule") + # Intentionally no newline + + +gen(test.top_filename) + +test.lint(verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_eofline_vlt.pl b/test_regress/t/t_lint_eofline_vlt.pl deleted file mode 100755 index 9bea83d86..000000000 --- a/test_regress/t/t_lint_eofline_vlt.pl +++ /dev/null @@ -1,36 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -use IO::File; -use strict; -use vars qw($Self); - -scenarios(vlt => 1); - -sub gen { - my $filename = shift; - - my $fh = IO::File->new(">$filename"); - $fh->print("// Generated by t_lint_eofline_bad.pl\n"); - $fh->print("module t;\n"); - $fh->print("// No newline below:\n"); - $fh->print("endmodule"); # Intentionally no newline -} - -top_filename("$Self->{obj_dir}/t_lint_eofline_bad.v"); - -gen($Self->{top_filename}); - -lint( - verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME t/t_lint_eofline_vlt.vlt"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_eofline_vlt.py b/test_regress/t/t_lint_eofline_vlt.py new file mode 100755 index 000000000..43944fe94 --- /dev/null +++ b/test_regress/t/t_lint_eofline_vlt.py @@ -0,0 +1,29 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = test.obj_dir + "/t_lint_eofline_bad.v" + + +def gen(filename): + with open(filename, 'w', encoding="utf8") as fh: + fh.write("// Generated by t_lint_eofline_bad.py\n") + fh.write("module t;\n") + fh.write("// No newline below:\n") + fh.write("endmodule") + # Intentionally no newline + + +gen(test.top_filename) + +test.lint(verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME t/t_lint_eofline_vlt.vlt"]) + +test.passes() diff --git a/test_regress/t/t_lint_ftask_output_assign_bad.pl b/test_regress/t/t_lint_ftask_output_assign_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_lint_ftask_output_assign_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_ftask_output_assign_bad.py b/test_regress/t/t_lint_ftask_output_assign_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_lint_ftask_output_assign_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_genunnamed_bad.pl b/test_regress/t/t_lint_genunnamed_bad.pl deleted file mode 100755 index 4ad25735e..000000000 --- a/test_regress/t/t_lint_genunnamed_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME"], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_genunnamed_bad.py b/test_regress/t/t_lint_genunnamed_bad.py new file mode 100755 index 000000000..f05a78df6 --- /dev/null +++ b/test_regress/t/t_lint_genunnamed_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, + verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME"], + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_historical.pl b/test_regress/t/t_lint_historical.pl deleted file mode 100755 index a6e8d4033..000000000 --- a/test_regress/t/t_lint_historical.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_historical.py b/test_regress/t/t_lint_historical.py new file mode 100755 index 000000000..9ab47796d --- /dev/null +++ b/test_regress/t/t_lint_historical.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only"]) + +test.passes() diff --git a/test_regress/t/t_lint_iface_array_topmodule1.pl b/test_regress/t/t_lint_iface_array_topmodule1.pl deleted file mode 100755 index 7918d5f13..000000000 --- a/test_regress/t/t_lint_iface_array_topmodule1.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_lint_iface_array_topmodule1.py b/test_regress/t/t_lint_iface_array_topmodule1.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_lint_iface_array_topmodule1.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_lint_iface_array_topmodule2.pl b/test_regress/t/t_lint_iface_array_topmodule2.pl deleted file mode 100755 index 7918d5f13..000000000 --- a/test_regress/t/t_lint_iface_array_topmodule2.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_lint_iface_array_topmodule2.py b/test_regress/t/t_lint_iface_array_topmodule2.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_lint_iface_array_topmodule2.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_lint_iface_array_topmodule3.pl b/test_regress/t/t_lint_iface_array_topmodule3.pl deleted file mode 100755 index 7918d5f13..000000000 --- a/test_regress/t/t_lint_iface_array_topmodule3.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_lint_iface_array_topmodule3.py b/test_regress/t/t_lint_iface_array_topmodule3.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_lint_iface_array_topmodule3.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_lint_iface_array_topmodule_bad.pl b/test_regress/t/t_lint_iface_array_topmodule_bad.pl deleted file mode 100755 index a82cf66cb..000000000 --- a/test_regress/t/t_lint_iface_array_topmodule_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_iface_array_topmodule_bad.py b/test_regress/t/t_lint_iface_array_topmodule_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_lint_iface_array_topmodule_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_iface_topmodule1.pl b/test_regress/t/t_lint_iface_topmodule1.pl deleted file mode 100755 index 7918d5f13..000000000 --- a/test_regress/t/t_lint_iface_topmodule1.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_lint_iface_topmodule1.py b/test_regress/t/t_lint_iface_topmodule1.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_lint_iface_topmodule1.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_lint_iface_topmodule2.pl b/test_regress/t/t_lint_iface_topmodule2.pl deleted file mode 100755 index 7918d5f13..000000000 --- a/test_regress/t/t_lint_iface_topmodule2.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_lint_iface_topmodule2.py b/test_regress/t/t_lint_iface_topmodule2.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_lint_iface_topmodule2.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_lint_iface_topmodule3.pl b/test_regress/t/t_lint_iface_topmodule3.pl deleted file mode 100755 index 7918d5f13..000000000 --- a/test_regress/t/t_lint_iface_topmodule3.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_lint_iface_topmodule3.py b/test_regress/t/t_lint_iface_topmodule3.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_lint_iface_topmodule3.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_lint_iface_topmodule_bad.pl b/test_regress/t/t_lint_iface_topmodule_bad.pl deleted file mode 100755 index a82cf66cb..000000000 --- a/test_regress/t/t_lint_iface_topmodule_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_iface_topmodule_bad.py b/test_regress/t/t_lint_iface_topmodule_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_lint_iface_topmodule_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_ifdepth_bad.pl b/test_regress/t/t_lint_ifdepth_bad.pl deleted file mode 100755 index 76be13063..000000000 --- a/test_regress/t/t_lint_ifdepth_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME --if-depth 10"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_ifdepth_bad.py b/test_regress/t/t_lint_ifdepth_bad.py new file mode 100755 index 000000000..2d9f441cf --- /dev/null +++ b/test_regress/t/t_lint_ifdepth_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME --if-depth 10"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_implicit.pl b/test_regress/t/t_lint_implicit.pl deleted file mode 100755 index f666ab867..000000000 --- a/test_regress/t/t_lint_implicit.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["-Wno-IMPLICIT"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_implicit.py b/test_regress/t/t_lint_implicit.py new file mode 100755 index 000000000..837cc7107 --- /dev/null +++ b/test_regress/t/t_lint_implicit.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["-Wno-IMPLICIT"]) + +test.passes() diff --git a/test_regress/t/t_lint_implicit_bad.pl b/test_regress/t/t_lint_implicit_bad.pl deleted file mode 100755 index abf5d91f2..000000000 --- a/test_regress/t/t_lint_implicit_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_lint_implicit.v"); - -lint( - verilator_flags2 => ["--lint-only -Wwarn-IMPLICIT"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_implicit_bad.py b/test_regress/t/t_lint_implicit_bad.py new file mode 100755 index 000000000..3713dce09 --- /dev/null +++ b/test_regress/t/t_lint_implicit_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_lint_implicit.v" + +test.lint(verilator_flags2=["--lint-only -Wwarn-IMPLICIT"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_implicit_def_bad.pl b/test_regress/t/t_lint_implicit_def_bad.pl deleted file mode 100755 index 7539b1bd9..000000000 --- a/test_regress/t/t_lint_implicit_def_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_implicit_def_bad.py b/test_regress/t/t_lint_implicit_def_bad.py new file mode 100755 index 000000000..c0608225e --- /dev/null +++ b/test_regress/t/t_lint_implicit_def_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_implicit_port.pl b/test_regress/t/t_lint_implicit_port.pl deleted file mode 100755 index f666ab867..000000000 --- a/test_regress/t/t_lint_implicit_port.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["-Wno-IMPLICIT"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_implicit_port.py b/test_regress/t/t_lint_implicit_port.py new file mode 100755 index 000000000..837cc7107 --- /dev/null +++ b/test_regress/t/t_lint_implicit_port.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["-Wno-IMPLICIT"]) + +test.passes() diff --git a/test_regress/t/t_lint_import_name2_bad.pl b/test_regress/t/t_lint_import_name2_bad.pl deleted file mode 100755 index 7539b1bd9..000000000 --- a/test_regress/t/t_lint_import_name2_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_import_name2_bad.py b/test_regress/t/t_lint_import_name2_bad.py new file mode 100755 index 000000000..c0608225e --- /dev/null +++ b/test_regress/t/t_lint_import_name2_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_import_name_bad.pl b/test_regress/t/t_lint_import_name_bad.pl deleted file mode 100755 index 7539b1bd9..000000000 --- a/test_regress/t/t_lint_import_name_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_import_name_bad.py b/test_regress/t/t_lint_import_name_bad.py new file mode 100755 index 000000000..c0608225e --- /dev/null +++ b/test_regress/t/t_lint_import_name_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_importstar_bad.pl b/test_regress/t/t_lint_importstar_bad.pl deleted file mode 100755 index 7539b1bd9..000000000 --- a/test_regress/t/t_lint_importstar_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_importstar_bad.py b/test_regress/t/t_lint_importstar_bad.py new file mode 100755 index 000000000..c0608225e --- /dev/null +++ b/test_regress/t/t_lint_importstar_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_in_inc_bad.pl b/test_regress/t/t_lint_in_inc_bad.pl deleted file mode 100755 index 0661a705e..000000000 --- a/test_regress/t/t_lint_in_inc_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - v_flags2 => ["-Wall -Wno-DECLFILENAME --if-depth 10"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_in_inc_bad.py b/test_regress/t/t_lint_in_inc_bad.py new file mode 100755 index 000000000..6307c426b --- /dev/null +++ b/test_regress/t/t_lint_in_inc_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(v_flags2=["-Wall -Wno-DECLFILENAME --if-depth 10"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_incabspath.pl b/test_regress/t/t_lint_incabspath.pl deleted file mode 100755 index 1366501ca..000000000 --- a/test_regress/t/t_lint_incabspath.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_lint_incabspath.py b/test_regress/t/t_lint_incabspath.py new file mode 100755 index 000000000..f81c3d68d --- /dev/null +++ b/test_regress/t/t_lint_incabspath.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_lint_incabspath_bad.pl b/test_regress/t/t_lint_incabspath_bad.pl deleted file mode 100755 index 80a2b601f..000000000 --- a/test_regress/t/t_lint_incabspath_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_lint_incabspath.v"); - -lint( - verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_incabspath_bad.py b/test_regress/t/t_lint_incabspath_bad.py new file mode 100755 index 000000000..a825eadf4 --- /dev/null +++ b/test_regress/t/t_lint_incabspath_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_lint_incabspath.v" + +test.lint(verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_infinite.pl b/test_regress/t/t_lint_infinite.pl deleted file mode 100755 index dee19d2aa..000000000 --- a/test_regress/t/t_lint_infinite.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_infinite.py b/test_regress/t/t_lint_infinite.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_lint_infinite.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_lint_infinite_bad.pl b/test_regress/t/t_lint_infinite_bad.pl deleted file mode 100755 index 07964a1b5..000000000 --- a/test_regress/t/t_lint_infinite_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_infinite_bad.py b/test_regress/t/t_lint_infinite_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_lint_infinite_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_inherit.pl b/test_regress/t/t_lint_inherit.pl deleted file mode 100755 index 552bd97db..000000000 --- a/test_regress/t/t_lint_inherit.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_inherit.py b/test_regress/t/t_lint_inherit.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_lint_inherit.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_lint_input_eq_good.pl b/test_regress/t/t_lint_input_eq_good.pl deleted file mode 100755 index 8b318d39c..000000000 --- a/test_regress/t/t_lint_input_eq_good.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_lint_input_eq_good.py b/test_regress/t/t_lint_input_eq_good.py new file mode 100755 index 000000000..f81c3d68d --- /dev/null +++ b/test_regress/t/t_lint_input_eq_good.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_lint_latch_1.pl b/test_regress/t/t_lint_latch_1.pl deleted file mode 100755 index 629a44bbb..000000000 --- a/test_regress/t/t_lint_latch_1.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_latch_1.py b/test_regress/t/t_lint_latch_1.py new file mode 100755 index 000000000..f81c3d68d --- /dev/null +++ b/test_regress/t/t_lint_latch_1.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_lint_latch_2.pl b/test_regress/t/t_lint_latch_2.pl deleted file mode 100755 index 629a44bbb..000000000 --- a/test_regress/t/t_lint_latch_2.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_latch_2.py b/test_regress/t/t_lint_latch_2.py new file mode 100755 index 000000000..f81c3d68d --- /dev/null +++ b/test_regress/t/t_lint_latch_2.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_lint_latch_3.pl b/test_regress/t/t_lint_latch_3.pl deleted file mode 100755 index 629a44bbb..000000000 --- a/test_regress/t/t_lint_latch_3.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_latch_3.py b/test_regress/t/t_lint_latch_3.py new file mode 100755 index 000000000..f81c3d68d --- /dev/null +++ b/test_regress/t/t_lint_latch_3.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_lint_latch_4.pl b/test_regress/t/t_lint_latch_4.pl deleted file mode 100755 index 629a44bbb..000000000 --- a/test_regress/t/t_lint_latch_4.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_latch_4.py b/test_regress/t/t_lint_latch_4.py new file mode 100755 index 000000000..f81c3d68d --- /dev/null +++ b/test_regress/t/t_lint_latch_4.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_lint_latch_5.pl b/test_regress/t/t_lint_latch_5.pl deleted file mode 100755 index 629a44bbb..000000000 --- a/test_regress/t/t_lint_latch_5.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_latch_5.py b/test_regress/t/t_lint_latch_5.py new file mode 100755 index 000000000..f81c3d68d --- /dev/null +++ b/test_regress/t/t_lint_latch_5.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_lint_latch_6.pl b/test_regress/t/t_lint_latch_6.pl deleted file mode 100755 index 629a44bbb..000000000 --- a/test_regress/t/t_lint_latch_6.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_latch_6.py b/test_regress/t/t_lint_latch_6.py new file mode 100755 index 000000000..f81c3d68d --- /dev/null +++ b/test_regress/t/t_lint_latch_6.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_lint_latch_7.pl b/test_regress/t/t_lint_latch_7.pl deleted file mode 100755 index 629a44bbb..000000000 --- a/test_regress/t/t_lint_latch_7.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_latch_7.py b/test_regress/t/t_lint_latch_7.py new file mode 100755 index 000000000..f81c3d68d --- /dev/null +++ b/test_regress/t/t_lint_latch_7.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_lint_latch_bad.pl b/test_regress/t/t_lint_latch_bad.pl deleted file mode 100755 index 6755217bb..000000000 --- a/test_regress/t/t_lint_latch_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only -Wwarn-style -Wno-DECLFILENAME"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_latch_bad.py b/test_regress/t/t_lint_latch_bad.py new file mode 100755 index 000000000..8441aff14 --- /dev/null +++ b/test_regress/t/t_lint_latch_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only -Wwarn-style -Wno-DECLFILENAME"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_latch_bad_2.pl b/test_regress/t/t_lint_latch_bad_2.pl deleted file mode 100755 index 70301e9b6..000000000 --- a/test_regress/t/t_lint_latch_bad_2.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_latch_bad_2.py b/test_regress/t/t_lint_latch_bad_2.py new file mode 100755 index 000000000..dece38f4e --- /dev/null +++ b/test_regress/t/t_lint_latch_bad_2.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_latch_bad_3.pl b/test_regress/t/t_lint_latch_bad_3.pl deleted file mode 100755 index 70301e9b6..000000000 --- a/test_regress/t/t_lint_latch_bad_3.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_latch_bad_3.py b/test_regress/t/t_lint_latch_bad_3.py new file mode 100755 index 000000000..dece38f4e --- /dev/null +++ b/test_regress/t/t_lint_latch_bad_3.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_literal_bad.pl b/test_regress/t/t_lint_literal_bad.pl deleted file mode 100755 index 5ece32e17..000000000 --- a/test_regress/t/t_lint_literal_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2017 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_literal_bad.py b/test_regress/t/t_lint_literal_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_lint_literal_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_misindent_bad.pl b/test_regress/t/t_lint_misindent_bad.pl deleted file mode 100755 index 4ad25735e..000000000 --- a/test_regress/t/t_lint_misindent_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME"], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_misindent_bad.py b/test_regress/t/t_lint_misindent_bad.py new file mode 100755 index 000000000..f05a78df6 --- /dev/null +++ b/test_regress/t/t_lint_misindent_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, + verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME"], + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_mod_paren_bad.pl b/test_regress/t/t_lint_mod_paren_bad.pl deleted file mode 100755 index 0b0675898..000000000 --- a/test_regress/t/t_lint_mod_paren_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only -Wno-DECLFILENAME"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_mod_paren_bad.py b/test_regress/t/t_lint_mod_paren_bad.py new file mode 100755 index 000000000..3ce9351b2 --- /dev/null +++ b/test_regress/t/t_lint_mod_paren_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only -Wno-DECLFILENAME"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_modport_dir_bad.pl b/test_regress/t/t_lint_modport_dir_bad.pl deleted file mode 100755 index abf587bd3..000000000 --- a/test_regress/t/t_lint_modport_dir_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only -Wno-DECLFILENAME"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_modport_dir_bad.py b/test_regress/t/t_lint_modport_dir_bad.py new file mode 100755 index 000000000..53e81eb85 --- /dev/null +++ b/test_regress/t/t_lint_modport_dir_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only -Wno-DECLFILENAME"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_multidriven_bad.pl b/test_regress/t/t_lint_multidriven_bad.pl deleted file mode 100755 index 2ec245f15..000000000 --- a/test_regress/t/t_lint_multidriven_bad.pl +++ /dev/null @@ -1,35 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -my $root = ".."; - -if (!-r "$root/.git") { - skip("Not in a git repository"); -} else { - lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - - extract( - in => $Self->{top_filename}, - out => "../docs/gen/ex_MULTIDRIVEN_faulty.rst", - lines => "31-36"); - - extract( - in => $Self->{golden_filename}, - out => "../docs/gen/ex_MULTIDRIVEN_msg.rst", - lines => "10,11,14"); -} - -ok(1); -1; diff --git a/test_regress/t/t_lint_multidriven_bad.py b/test_regress/t/t_lint_multidriven_bad.py new file mode 100755 index 000000000..ed3410fdd --- /dev/null +++ b/test_regress/t/t_lint_multidriven_bad.py @@ -0,0 +1,29 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +root = ".." + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.extract(in_filename=test.top_filename, + out_filename="../docs/gen/ex_MULTIDRIVEN_faulty.rst", + lines="31-36") + +test.extract(in_filename=test.golden_filename, + out_filename="../docs/gen/ex_MULTIDRIVEN_msg.rst", + lines="10,11,14") + +test.passes() diff --git a/test_regress/t/t_lint_nolatch_bad.pl b/test_regress/t/t_lint_nolatch_bad.pl deleted file mode 100755 index a8b75812f..000000000 --- a/test_regress/t/t_lint_nolatch_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename} - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_nolatch_bad.py b/test_regress/t/t_lint_nolatch_bad.py new file mode 100755 index 000000000..dece38f4e --- /dev/null +++ b/test_regress/t/t_lint_nolatch_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_nullport_bad.pl b/test_regress/t/t_lint_nullport_bad.pl deleted file mode 100755 index 4f29861db..000000000 --- a/test_regress/t/t_lint_nullport_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_nullport_bad.py b/test_regress/t/t_lint_nullport_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_lint_nullport_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_numwidth.pl b/test_regress/t/t_lint_numwidth.pl deleted file mode 100755 index 9fe706c85..000000000 --- a/test_regress/t/t_lint_numwidth.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--max-num-width 131072"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_numwidth.py b/test_regress/t/t_lint_numwidth.py new file mode 100755 index 000000000..9f7577b1b --- /dev/null +++ b/test_regress/t/t_lint_numwidth.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--max-num-width 131072"]) + +test.passes() diff --git a/test_regress/t/t_lint_once_bad.pl b/test_regress/t/t_lint_once_bad.pl deleted file mode 100755 index 4937974bc..000000000 --- a/test_regress/t/t_lint_once_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only -Wwarn-UNUSED"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_once_bad.py b/test_regress/t/t_lint_once_bad.py new file mode 100755 index 000000000..9690ccd5f --- /dev/null +++ b/test_regress/t/t_lint_once_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only -Wwarn-UNUSED"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_only.pl b/test_regress/t/t_lint_only.pl deleted file mode 100755 index d1e2ac8bc..000000000 --- a/test_regress/t/t_lint_only.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint(); - -foreach my $file (glob("$Self->{obj_dir}/*")) { - next if $file =~ /\.log/; # Made by driver.pl, not Verilator sources - next if $file =~ /\.status/; # Made by driver.pl, not Verilator sources - next if $file =~ /\.gcda/; # Made by gcov, not Verilator sources - error("%Error: Created $file, but --lint-only shouldn't create files"); -} - -ok(1); -1; diff --git a/test_regress/t/t_lint_only.py b/test_regress/t/t_lint_only.py new file mode 100755 index 000000000..6bd600182 --- /dev/null +++ b/test_regress/t/t_lint_only.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint() + +for filename in glob.glob(test.obj_dir + "/*"): + if (re.search(r'\.log', filename) # Made by driver.py, not Verilator sources + or re.search(r'\.status', filename) # Made by driver.py, not Verilator sources + or re.search(r'\.gcda', filename)): # Made by gcov, not Verilator sources + continue + test.error("%Error: Created '" + filename + "', but --lint-only shouldn't create files") + +test.passes() diff --git a/test_regress/t/t_lint_pindup_bad.pl b/test_regress/t/t_lint_pindup_bad.pl deleted file mode 100755 index a82cf66cb..000000000 --- a/test_regress/t/t_lint_pindup_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_pindup_bad.py b/test_regress/t/t_lint_pindup_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_lint_pindup_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_pinmissing_bad.pl b/test_regress/t/t_lint_pinmissing_bad.pl deleted file mode 100755 index b48fa0bc9..000000000 --- a/test_regress/t/t_lint_pinmissing_bad.pl +++ /dev/null @@ -1,35 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -my $root = ".."; - -if (!-r "$root/.git") { - skip("Not in a git repository"); -} else { - lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - - extract( - in => $Self->{top_filename}, - out => "../docs/gen/ex_PINMISSING_faulty.rst", - lines => "7-12"); - - extract( - in => $Self->{golden_filename}, - out => "../docs/gen/ex_PINMISSING_msg.rst", - lines => "1-1"); -} - -ok(1); -1; diff --git a/test_regress/t/t_lint_pinmissing_bad.py b/test_regress/t/t_lint_pinmissing_bad.py new file mode 100755 index 000000000..3f80106f9 --- /dev/null +++ b/test_regress/t/t_lint_pinmissing_bad.py @@ -0,0 +1,29 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +root = ".." + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.extract(in_filename=test.top_filename, + out_filename="../docs/gen/ex_PINMISSING_faulty.rst", + lines="7-12") + +test.extract(in_filename=test.golden_filename, + out_filename="../docs/gen/ex_PINMISSING_msg.rst", + lines="1-1") + +test.passes() diff --git a/test_regress/t/t_lint_pinnotfound.pl b/test_regress/t/t_lint_pinnotfound.pl deleted file mode 100755 index aca1cb3c1..000000000 --- a/test_regress/t/t_lint_pinnotfound.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_pinnotfound.py b/test_regress/t/t_lint_pinnotfound.py new file mode 100755 index 000000000..f81c3d68d --- /dev/null +++ b/test_regress/t/t_lint_pinnotfound.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_lint_pinnotfound_bad.pl b/test_regress/t/t_lint_pinnotfound_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_lint_pinnotfound_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_pinnotfound_bad.py b/test_regress/t/t_lint_pinnotfound_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_lint_pinnotfound_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_pkg_colon_bad.pl b/test_regress/t/t_lint_pkg_colon_bad.pl deleted file mode 100755 index a82cf66cb..000000000 --- a/test_regress/t/t_lint_pkg_colon_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_pkg_colon_bad.py b/test_regress/t/t_lint_pkg_colon_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_lint_pkg_colon_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_pkgnodecl_bad.pl b/test_regress/t/t_lint_pkgnodecl_bad.pl deleted file mode 100755 index 7a81df912..000000000 --- a/test_regress/t/t_lint_pkgnodecl_bad.pl +++ /dev/null @@ -1,35 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -my $root = ".."; - -if (!-r "$root/.git") { - skip("Not in a git repository"); -} else { - lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - - extract( - in => $Self->{top_filename}, - out => "../docs/gen/ex_PKGNODECL_faulty.rst", - lines => "7-12"); - - extract( - in => $Self->{golden_filename}, - out => "../docs/gen/ex_PKGNODECL_msg.rst", - lines => "1"); -} - -ok(1); -1; diff --git a/test_regress/t/t_lint_pkgnodecl_bad.py b/test_regress/t/t_lint_pkgnodecl_bad.py new file mode 100755 index 000000000..21d9be319 --- /dev/null +++ b/test_regress/t/t_lint_pkgnodecl_bad.py @@ -0,0 +1,29 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +root = ".." + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.extract(in_filename=test.top_filename, + out_filename="../docs/gen/ex_PKGNODECL_faulty.rst", + lines="7-12") + +test.extract(in_filename=test.golden_filename, + out_filename="../docs/gen/ex_PKGNODECL_msg.rst", + lines="1") + +test.passes() diff --git a/test_regress/t/t_lint_pragma_protected.pl b/test_regress/t/t_lint_pragma_protected.pl deleted file mode 100755 index 26a2c09ae..000000000 --- a/test_regress/t/t_lint_pragma_protected.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - - -lint( - verilator_flags2 => ['--lint-only -Wno-PROTECTED'], - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_pragma_protected.py b/test_regress/t/t_lint_pragma_protected.py new file mode 100755 index 000000000..e0fa30056 --- /dev/null +++ b/test_regress/t/t_lint_pragma_protected.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=['--lint-only -Wno-PROTECTED']) + +test.passes() diff --git a/test_regress/t/t_lint_pragma_protected_bad.pl b/test_regress/t/t_lint_pragma_protected_bad.pl deleted file mode 100755 index ad84f1b54..000000000 --- a/test_regress/t/t_lint_pragma_protected_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - verilator_flags2 => ['--lint-only -Wpedantic'], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_pragma_protected_bad.py b/test_regress/t/t_lint_pragma_protected_bad.py new file mode 100755 index 000000000..dde27733d --- /dev/null +++ b/test_regress/t/t_lint_pragma_protected_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, + verilator_flags2=['--lint-only -Wpedantic'], + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_realcvt_bad.pl b/test_regress/t/t_lint_realcvt_bad.pl deleted file mode 100755 index 49de1747e..000000000 --- a/test_regress/t/t_lint_realcvt_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only -Wwarn-REALCVT"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_realcvt_bad.py b/test_regress/t/t_lint_realcvt_bad.py new file mode 100755 index 000000000..acbdae169 --- /dev/null +++ b/test_regress/t/t_lint_realcvt_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only -Wwarn-REALCVT"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_removed_unused_loop_bad.pl b/test_regress/t/t_lint_removed_unused_loop_bad.pl deleted file mode 100755 index d4d0ecb72..000000000 --- a/test_regress/t/t_lint_removed_unused_loop_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - verilator_flags2 => ["--top-module t", "-Wall"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_removed_unused_loop_bad.py b/test_regress/t/t_lint_removed_unused_loop_bad.py new file mode 100755 index 000000000..61e258882 --- /dev/null +++ b/test_regress/t/t_lint_removed_unused_loop_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, + expect_filename=test.golden_filename, + verilator_flags2=["--top-module t", "-Wall"]) + +test.passes() diff --git a/test_regress/t/t_lint_repeat_bad.pl b/test_regress/t/t_lint_repeat_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_lint_repeat_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_repeat_bad.py b/test_regress/t/t_lint_repeat_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_lint_repeat_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_restore_bad.pl b/test_regress/t/t_lint_restore_bad.pl deleted file mode 100755 index 07964a1b5..000000000 --- a/test_regress/t/t_lint_restore_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_restore_bad.py b/test_regress/t/t_lint_restore_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_lint_restore_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_restore_prag_bad.pl b/test_regress/t/t_lint_restore_prag_bad.pl deleted file mode 100755 index 07964a1b5..000000000 --- a/test_regress/t/t_lint_restore_prag_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_restore_prag_bad.py b/test_regress/t/t_lint_restore_prag_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_lint_restore_prag_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_rsvd_bad.pl b/test_regress/t/t_lint_rsvd_bad.pl deleted file mode 100755 index 49de1747e..000000000 --- a/test_regress/t/t_lint_rsvd_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only -Wwarn-REALCVT"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_rsvd_bad.py b/test_regress/t/t_lint_rsvd_bad.py new file mode 100755 index 000000000..acbdae169 --- /dev/null +++ b/test_regress/t/t_lint_rsvd_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only -Wwarn-REALCVT"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_setout_bad.pl b/test_regress/t/t_lint_setout_bad.pl deleted file mode 100755 index a82cf66cb..000000000 --- a/test_regress/t/t_lint_setout_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_setout_bad.py b/test_regress/t/t_lint_setout_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_lint_setout_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_setout_bad_noinl.pl b/test_regress/t/t_lint_setout_bad_noinl.pl deleted file mode 100755 index cbbf96bb4..000000000 --- a/test_regress/t/t_lint_setout_bad_noinl.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -top_filename("t/t_lint_setout_bad.v"); - -lint( - verilator_flags2 => ["--lint-only -fno-inline"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_setout_bad_noinl.py b/test_regress/t/t_lint_setout_bad_noinl.py new file mode 100755 index 000000000..c10fcd5f7 --- /dev/null +++ b/test_regress/t/t_lint_setout_bad_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_lint_setout_bad.v" + +test.lint(verilator_flags2=["--lint-only -fno-inline"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_sideeffect_bad.pl b/test_regress/t/t_lint_sideeffect_bad.pl deleted file mode 100755 index a82cf66cb..000000000 --- a/test_regress/t/t_lint_sideeffect_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_sideeffect_bad.py b/test_regress/t/t_lint_sideeffect_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_lint_sideeffect_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_stmtdly_bad.pl b/test_regress/t/t_lint_stmtdly_bad.pl deleted file mode 100755 index e9c855466..000000000 --- a/test_regress/t/t_lint_stmtdly_bad.pl +++ /dev/null @@ -1,36 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $root = ".."; - -if (!-r "$root/.git") { - skip("Not in a git repository"); -} else { - lint( - verilator_flags2 => ["--no-timing"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - - extract( - in => $Self->{top_filename}, - out => "../docs/gen/ex_STMTDLY_faulty.rst", - lines => "10"); - - extract( - in => $Self->{golden_filename}, - out => "../docs/gen/ex_STMTDLY_msg.rst", - lines => "1"); -} - -ok(1); -1; diff --git a/test_regress/t/t_lint_stmtdly_bad.py b/test_regress/t/t_lint_stmtdly_bad.py new file mode 100755 index 000000000..cf06e63a2 --- /dev/null +++ b/test_regress/t/t_lint_stmtdly_bad.py @@ -0,0 +1,29 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +root = ".." + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +test.lint(verilator_flags2=["--no-timing"], fails=True, expect_filename=test.golden_filename) + +test.extract(in_filename=test.top_filename, + out_filename="../docs/gen/ex_STMTDLY_faulty.rst", + lines="10") + +test.extract(in_filename=test.golden_filename, + out_filename="../docs/gen/ex_STMTDLY_msg.rst", + lines="1") + +test.passes() diff --git a/test_regress/t/t_lint_subout_bad.pl b/test_regress/t/t_lint_subout_bad.pl deleted file mode 100755 index 88f90f1d4..000000000 --- a/test_regress/t/t_lint_subout_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - # No --lint-only as got compile error - verilator_flags2 => ["--trace"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_subout_bad.py b/test_regress/t/t_lint_subout_bad.py new file mode 100755 index 000000000..2ea3b149a --- /dev/null +++ b/test_regress/t/t_lint_subout_bad.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile( + # No --lint-only as got compile error + verilator_flags2=["--trace"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_syncasyncnet_bad.pl b/test_regress/t/t_lint_syncasyncnet_bad.pl deleted file mode 100755 index a40f3dab1..000000000 --- a/test_regress/t/t_lint_syncasyncnet_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME --if-depth 10"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_syncasyncnet_bad.py b/test_regress/t/t_lint_syncasyncnet_bad.py new file mode 100755 index 000000000..44eef5de9 --- /dev/null +++ b/test_regress/t/t_lint_syncasyncnet_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME --if-depth 10"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_top_bad.pl b/test_regress/t/t_lint_top_bad.pl deleted file mode 100755 index b1d44e6a9..000000000 --- a/test_regress/t/t_lint_top_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ['-O0 --trace-fst'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_top_bad.py b/test_regress/t/t_lint_top_bad.py new file mode 100755 index 000000000..161c81983 --- /dev/null +++ b/test_regress/t/t_lint_top_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['-O0 --trace-fst'], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_unsigned_bad.pl b/test_regress/t/t_lint_unsigned_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_lint_unsigned_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_unsigned_bad.py b/test_regress/t/t_lint_unsigned_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_lint_unsigned_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_unsized_bad.pl b/test_regress/t/t_lint_unsized_bad.pl deleted file mode 100755 index a82cf66cb..000000000 --- a/test_regress/t/t_lint_unsized_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_unsized_bad.py b/test_regress/t/t_lint_unsized_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_lint_unsized_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_unsup_deassign.pl b/test_regress/t/t_lint_unsup_deassign.pl deleted file mode 100755 index d4a6fe9d8..000000000 --- a/test_regress/t/t_lint_unsup_deassign.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only --bbox-unsup"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_unsup_deassign.py b/test_regress/t/t_lint_unsup_deassign.py new file mode 100755 index 000000000..ef40a09c4 --- /dev/null +++ b/test_regress/t/t_lint_unsup_deassign.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only --bbox-unsup"]) + +test.passes() diff --git a/test_regress/t/t_lint_unsup_mixed.pl b/test_regress/t/t_lint_unsup_mixed.pl deleted file mode 100755 index d4a6fe9d8..000000000 --- a/test_regress/t/t_lint_unsup_mixed.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only --bbox-unsup"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_unsup_mixed.py b/test_regress/t/t_lint_unsup_mixed.py new file mode 100755 index 000000000..ef40a09c4 --- /dev/null +++ b/test_regress/t/t_lint_unsup_mixed.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only --bbox-unsup"]) + +test.passes() diff --git a/test_regress/t/t_lint_unused.pl b/test_regress/t/t_lint_unused.pl deleted file mode 100755 index ab8a6023e..000000000 --- a/test_regress/t/t_lint_unused.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only --bbox-sys --bbox-unsup -Wall -Wno-DECLFILENAME"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_unused.py b/test_regress/t/t_lint_unused.py new file mode 100755 index 000000000..3993e1fec --- /dev/null +++ b/test_regress/t/t_lint_unused.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only --bbox-sys --bbox-unsup -Wall -Wno-DECLFILENAME"]) + +test.passes() diff --git a/test_regress/t/t_lint_unused_bad.pl b/test_regress/t/t_lint_unused_bad.pl deleted file mode 100755 index feee5f9e4..000000000 --- a/test_regress/t/t_lint_unused_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only --bbox-sys --bbox-unsup -Wall -Wno-DECLFILENAME", - "--unused-regexp 'cmdln*'"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_unused_bad.py b/test_regress/t/t_lint_unused_bad.py new file mode 100755 index 000000000..4108fcca7 --- /dev/null +++ b/test_regress/t/t_lint_unused_bad.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=[ + "--lint-only --bbox-sys --bbox-unsup -Wall -Wno-DECLFILENAME", "--unused-regexp 'cmdln*'" +], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_unused_iface.pl b/test_regress/t/t_lint_unused_iface.pl deleted file mode 100755 index 3679f5264..000000000 --- a/test_regress/t/t_lint_unused_iface.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_unused_iface.py b/test_regress/t/t_lint_unused_iface.py new file mode 100755 index 000000000..8bb4f3a66 --- /dev/null +++ b/test_regress/t/t_lint_unused_iface.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME"]) + +test.passes() diff --git a/test_regress/t/t_lint_unused_iface_bad.pl b/test_regress/t/t_lint_unused_iface_bad.pl deleted file mode 100755 index 1c2a82989..000000000 --- a/test_regress/t/t_lint_unused_iface_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_unused_iface_bad.py b/test_regress/t/t_lint_unused_iface_bad.py new file mode 100755 index 000000000..c6b6f1747 --- /dev/null +++ b/test_regress/t/t_lint_unused_iface_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_unused_tri.pl b/test_regress/t/t_lint_unused_tri.pl deleted file mode 100755 index 3679f5264..000000000 --- a/test_regress/t/t_lint_unused_tri.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_unused_tri.py b/test_regress/t/t_lint_unused_tri.py new file mode 100755 index 000000000..8bb4f3a66 --- /dev/null +++ b/test_regress/t/t_lint_unused_tri.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME"]) + +test.passes() diff --git a/test_regress/t/t_lint_vcmarker_bad.pl b/test_regress/t/t_lint_vcmarker_bad.pl deleted file mode 100755 index 07964a1b5..000000000 --- a/test_regress/t/t_lint_vcmarker_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_vcmarker_bad.py b/test_regress/t/t_lint_vcmarker_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_lint_vcmarker_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_wait_bad.pl b/test_regress/t/t_lint_wait_bad.pl deleted file mode 100755 index b92ab79f3..000000000 --- a/test_regress/t/t_lint_wait_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_timing_wait1.v"); - -lint( - verilator_flags2 => ["--timing"], - expect_filename => $Self->{golden_filename}, - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_wait_bad.py b/test_regress/t/t_lint_wait_bad.py new file mode 100755 index 000000000..a449d4a24 --- /dev/null +++ b/test_regress/t/t_lint_wait_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_timing_wait1.v" + +test.lint(verilator_flags2=["--timing"], expect_filename=test.golden_filename, fails=True) + +test.passes() diff --git a/test_regress/t/t_lint_warn_incfile2_bad.pl b/test_regress/t/t_lint_warn_incfile2_bad.pl deleted file mode 100755 index b3cdb56a9..000000000 --- a/test_regress/t/t_lint_warn_incfile2_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - # See also t/t_lint_warn_incfile1_bad - # See also t/t_vlt_warn_file_bad - verilator_flags2 => ["--no-std"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_warn_incfile2_bad.py b/test_regress/t/t_lint_warn_incfile2_bad.py new file mode 100755 index 000000000..1add606d3 --- /dev/null +++ b/test_regress/t/t_lint_warn_incfile2_bad.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint( + # See also t/t_lint_warn_incfile1_bad + # See also t/t_vlt_warn_file_bad + verilator_flags2=["--no-std"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_warn_line_bad.pl b/test_regress/t/t_lint_warn_line_bad.pl deleted file mode 100755 index b3cdb56a9..000000000 --- a/test_regress/t/t_lint_warn_line_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - # See also t/t_lint_warn_incfile1_bad - # See also t/t_vlt_warn_file_bad - verilator_flags2 => ["--no-std"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_warn_line_bad.py b/test_regress/t/t_lint_warn_line_bad.py new file mode 100755 index 000000000..1add606d3 --- /dev/null +++ b/test_regress/t/t_lint_warn_line_bad.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint( + # See also t/t_lint_warn_incfile1_bad + # See also t/t_vlt_warn_file_bad + verilator_flags2=["--no-std"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_width.pl b/test_regress/t/t_lint_width.pl deleted file mode 100755 index cc34dc85f..000000000 --- a/test_regress/t/t_lint_width.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_lint_width.py b/test_regress/t/t_lint_width.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_lint_width.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_lint_width_arraydecl.pl b/test_regress/t/t_lint_width_arraydecl.pl deleted file mode 100755 index 629a44bbb..000000000 --- a/test_regress/t/t_lint_width_arraydecl.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_width_arraydecl.py b/test_regress/t/t_lint_width_arraydecl.py new file mode 100755 index 000000000..f81c3d68d --- /dev/null +++ b/test_regress/t/t_lint_width_arraydecl.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_lint_width_bad.pl b/test_regress/t/t_lint_width_bad.pl deleted file mode 100755 index 07964a1b5..000000000 --- a/test_regress/t/t_lint_width_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_width_bad.py b/test_regress/t/t_lint_width_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_lint_width_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_width_genfor.pl b/test_regress/t/t_lint_width_genfor.pl deleted file mode 100755 index d4dec648c..000000000 --- a/test_regress/t/t_lint_width_genfor.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -$Self->{vlt_all}; - -scenarios(linter => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_lint_width_genfor.py b/test_regress/t/t_lint_width_genfor.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_lint_width_genfor.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_lint_width_genfor_bad.pl b/test_regress/t/t_lint_width_genfor_bad.pl deleted file mode 100755 index 35d749208..000000000 --- a/test_regress/t/t_lint_width_genfor_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_width_genfor_bad.py b/test_regress/t/t_lint_width_genfor_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_lint_width_genfor_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_width_shift_bad.pl b/test_regress/t/t_lint_width_shift_bad.pl deleted file mode 100755 index 07964a1b5..000000000 --- a/test_regress/t/t_lint_width_shift_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_lint_width_shift_bad.py b/test_regress/t/t_lint_width_shift_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_lint_width_shift_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_widthexpand_docs_bad.pl b/test_regress/t/t_lint_widthexpand_docs_bad.pl deleted file mode 100755 index 5dc62a3fc..000000000 --- a/test_regress/t/t_lint_widthexpand_docs_bad.pl +++ /dev/null @@ -1,42 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -my $root = ".."; - -if (!-r "$root/.git") { - skip("Not in a git repository"); -} else { - lint( - verilator_flags2 => ["--lint-only"], - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - - extract( - in => $Self->{top_filename}, - out => "../docs/gen/ex_WIDTHEXPAND_1_faulty.rst", - lines => "8-10"); - - extract( - in => $Self->{golden_filename}, - out => "../docs/gen/ex_WIDTHEXPAND_1_msg.rst", - lineno_adjust => -7, - regexp => qr/Warning-WIDTH/); - - extract( - in => $Self->{top_filename}, - out => "../docs/gen/ex_WIDTHEXPAND_1_fixed.rst", - lines => "18"); -} - -ok(1); -1; diff --git a/test_regress/t/t_lint_widthexpand_docs_bad.py b/test_regress/t/t_lint_widthexpand_docs_bad.py new file mode 100755 index 000000000..2b57b2bd5 --- /dev/null +++ b/test_regress/t/t_lint_widthexpand_docs_bad.py @@ -0,0 +1,36 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +root = ".." + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +test.lint(verilator_flags2=["--lint-only"], + fails=test.vlt_all, + expect_filename=test.golden_filename) + +test.extract(in_filename=test.top_filename, + out_filename="../docs/gen/ex_WIDTHEXPAND_1_faulty.rst", + lines="8-10") + +test.extract(in_filename=test.golden_filename, + out_filename="../docs/gen/ex_WIDTHEXPAND_1_msg.rst", + lineno_adjust=-7, + regexp=r'Warning-WIDTH') + +test.extract(in_filename=test.top_filename, + out_filename="../docs/gen/ex_WIDTHEXPAND_1_fixed.rst", + lines="18") + +test.passes() diff --git a/test_regress/t/t_mailbox.pl b/test_regress/t/t_mailbox.pl deleted file mode 100755 index 860c9a749..000000000 --- a/test_regress/t/t_mailbox.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing -Wall"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_mailbox.py b/test_regress/t/t_mailbox.py new file mode 100755 index 000000000..e84a7d7e7 --- /dev/null +++ b/test_regress/t/t_mailbox.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing -Wall"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mailbox_bad.pl b/test_regress/t/t_mailbox_bad.pl deleted file mode 100755 index a083f46f5..000000000 --- a/test_regress/t/t_mailbox_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mailbox_bad.py b/test_regress/t/t_mailbox_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_mailbox_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_mailbox_class.pl b/test_regress/t/t_mailbox_class.pl deleted file mode 100755 index 91589388d..000000000 --- a/test_regress/t/t_mailbox_class.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--binary --timing"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_mailbox_class.py b/test_regress/t/t_mailbox_class.py new file mode 100755 index 000000000..bbbcfc078 --- /dev/null +++ b/test_regress/t/t_mailbox_class.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary --timing"]) + +test.passes() diff --git a/test_regress/t/t_mailbox_concurrent.pl b/test_regress/t/t_mailbox_concurrent.pl deleted file mode 100755 index 27000793f..000000000 --- a/test_regress/t/t_mailbox_concurrent.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Liam Braun and Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--binary --timing"] - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mailbox_concurrent.py b/test_regress/t/t_mailbox_concurrent.py new file mode 100755 index 000000000..a74b0c7ec --- /dev/null +++ b/test_regress/t/t_mailbox_concurrent.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary --timing"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_mailbox_notiming.pl b/test_regress/t/t_mailbox_notiming.pl deleted file mode 100755 index 4454ec759..000000000 --- a/test_regress/t/t_mailbox_notiming.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --no-timing -Wall"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_mailbox_notiming.py b/test_regress/t/t_mailbox_notiming.py new file mode 100755 index 000000000..e504226e4 --- /dev/null +++ b/test_regress/t/t_mailbox_notiming.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --no-timing -Wall"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mailbox_std.pl b/test_regress/t/t_mailbox_std.pl deleted file mode 100755 index 50a28e807..000000000 --- a/test_regress/t/t_mailbox_std.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_mailbox.v"); - -compile( - verilator_flags2 => ["--exe --main --timing -Wall --Wpedantic -DMAILBOX_T=std::mailbox"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_mailbox_std.py b/test_regress/t/t_mailbox_std.py new file mode 100755 index 000000000..10f8af694 --- /dev/null +++ b/test_regress/t/t_mailbox_std.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_mailbox.v" + +test.compile(verilator_flags2=["--exe --main --timing -Wall --Wpedantic -DMAILBOX_T=std::mailbox"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mailbox_unbounded.pl b/test_regress/t/t_mailbox_unbounded.pl deleted file mode 100755 index 860c9a749..000000000 --- a/test_regress/t/t_mailbox_unbounded.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing -Wall"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_mailbox_unbounded.py b/test_regress/t/t_mailbox_unbounded.py new file mode 100755 index 000000000..e84a7d7e7 --- /dev/null +++ b/test_regress/t/t_mailbox_unbounded.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing -Wall"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_arith.pl b/test_regress/t/t_math_arith.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_math_arith.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_arith.py b/test_regress/t/t_math_arith.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_arith.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_clog2.pl b/test_regress/t/t_math_clog2.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_math_clog2.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_clog2.py b/test_regress/t/t_math_clog2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_clog2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_cmp.pl b/test_regress/t/t_math_cmp.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_math_cmp.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_cmp.py b/test_regress/t/t_math_cmp.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_cmp.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_concat.pl b/test_regress/t/t_math_concat.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_math_concat.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_concat.py b/test_regress/t/t_math_concat.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_concat.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_concat0.pl b/test_regress/t/t_math_concat0.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_math_concat0.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_concat0.py b/test_regress/t/t_math_concat0.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_concat0.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_concat64.pl b/test_regress/t/t_math_concat64.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_math_concat64.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_concat64.py b/test_regress/t/t_math_concat64.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_concat64.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_cond_clean.pl b/test_regress/t/t_math_cond_clean.pl deleted file mode 100755 index 56363dab6..000000000 --- a/test_regress/t/t_math_cond_clean.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_cond_clean.py b/test_regress/t/t_math_cond_clean.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_cond_clean.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_cond_huge.pl b/test_regress/t/t_math_cond_huge.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_math_cond_huge.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_cond_huge.py b/test_regress/t/t_math_cond_huge.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_cond_huge.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_cond_huge_noexpand.pl b/test_regress/t/t_math_cond_huge_noexpand.pl deleted file mode 100755 index f20b41edd..000000000 --- a/test_regress/t/t_math_cond_huge_noexpand.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_math_cond_huge.v"); - -compile( - verilator_flags2 => ['-fno-expand'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_cond_huge_noexpand.py b/test_regress/t/t_math_cond_huge_noexpand.py new file mode 100755 index 000000000..fe079527b --- /dev/null +++ b/test_regress/t/t_math_cond_huge_noexpand.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_math_cond_huge.v" + +test.compile(verilator_flags2=['-fno-expand']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_const.pl b/test_regress/t/t_math_const.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_math_const.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_const.py b/test_regress/t/t_math_const.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_const.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_countbits.pl b/test_regress/t/t_math_countbits.pl deleted file mode 100755 index 56363dab6..000000000 --- a/test_regress/t/t_math_countbits.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_countbits.py b/test_regress/t/t_math_countbits.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_countbits.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_countbits_bad.pl b/test_regress/t/t_math_countbits_bad.pl deleted file mode 100755 index 487e3aadf..000000000 --- a/test_regress/t/t_math_countbits_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename} - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_countbits_bad.py b/test_regress/t/t_math_countbits_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_math_countbits_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_math_div.pl b/test_regress/t/t_math_div.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_math_div.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_div.py b/test_regress/t/t_math_div.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_div.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_div0.pl b/test_regress/t/t_math_div0.pl deleted file mode 100755 index 20346f7b4..000000000 --- a/test_regress/t/t_math_div0.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--x-assign 0'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_div0.py b/test_regress/t/t_math_div0.py new file mode 100755 index 000000000..1c1006dc8 --- /dev/null +++ b/test_regress/t/t_math_div0.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--x-assign 0']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_div_noexpand.pl b/test_regress/t/t_math_div_noexpand.pl deleted file mode 100755 index afa562767..000000000 --- a/test_regress/t/t_math_div_noexpand.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_math_div.v"); - -compile( - verilator_flags2 => ['-fno-expand'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_div_noexpand.py b/test_regress/t/t_math_div_noexpand.py new file mode 100755 index 000000000..59a7dbcac --- /dev/null +++ b/test_regress/t/t_math_div_noexpand.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_math_div.v" + +test.compile(verilator_flags2=['-fno-expand']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_divw.pl b/test_regress/t/t_math_divw.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_math_divw.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_divw.py b/test_regress/t/t_math_divw.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_divw.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_eq.pl b/test_regress/t/t_math_eq.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_math_eq.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_eq.py b/test_regress/t/t_math_eq.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_eq.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_eq_bad.pl b/test_regress/t/t_math_eq_bad.pl deleted file mode 100755 index bce2416ed..000000000 --- a/test_regress/t/t_math_eq_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - expect_filename => $Self->{golden_filename}, - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_eq_bad.py b/test_regress/t/t_math_eq_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_math_eq_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_math_eq_noexpand.pl b/test_regress/t/t_math_eq_noexpand.pl deleted file mode 100755 index abe1aa896..000000000 --- a/test_regress/t/t_math_eq_noexpand.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_math_eq.v"); - -compile( - verilator_flags2 => ['-fno-expand'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_eq_noexpand.py b/test_regress/t/t_math_eq_noexpand.py new file mode 100755 index 000000000..9ee292fb7 --- /dev/null +++ b/test_regress/t/t_math_eq_noexpand.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_math_eq.v" + +test.compile(verilator_flags2=['-fno-expand']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_equal.pl b/test_regress/t/t_math_equal.pl deleted file mode 100755 index fdc76316a..000000000 --- a/test_regress/t/t_math_equal.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_equal.py b/test_regress/t/t_math_equal.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_equal.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_imm.pl b/test_regress/t/t_math_imm.pl deleted file mode 100755 index 1185a445f..000000000 --- a/test_regress/t/t_math_imm.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--compiler msvc"], # We have deep expressions we want to test - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_imm.py b/test_regress/t/t_math_imm.py new file mode 100755 index 000000000..539f320b1 --- /dev/null +++ b/test_regress/t/t_math_imm.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + # We have deep expressions we want to test) + verilator_flags2=["--compiler msvc"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_imm2.pl b/test_regress/t/t_math_imm2.pl deleted file mode 100755 index aa34a2efa..000000000 --- a/test_regress/t/t_math_imm2.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_imm2.py b/test_regress/t/t_math_imm2.py new file mode 100755 index 000000000..273ccc85c --- /dev/null +++ b/test_regress/t/t_math_imm2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_insert_bound.pl b/test_regress/t/t_math_insert_bound.pl deleted file mode 100755 index 3708008f8..000000000 --- a/test_regress/t/t_math_insert_bound.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_insert_bound.py b/test_regress/t/t_math_insert_bound.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_insert_bound.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_mul.pl b/test_regress/t/t_math_mul.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_math_mul.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_mul.py b/test_regress/t/t_math_mul.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_mul.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_pick.pl b/test_regress/t/t_math_pick.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_math_pick.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_pick.py b/test_regress/t/t_math_pick.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_pick.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_pow.pl b/test_regress/t/t_math_pow.pl deleted file mode 100755 index e309166a2..000000000 --- a/test_regress/t/t_math_pow.pl +++ /dev/null @@ -1,44 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['-fno-gate'], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -# Check for coverage on all POW functions -system("cat $Self->{obj_dir}/$Self->{vm_prefix}_*.cpp > $Self->{obj_dir}/all.cpp"); - -file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POW_III/); -file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POW_IIQ/); -file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POW_IIW/); -file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POW_QQI/); -file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POW_QQQ/); -file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POW_QQW/); -file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POW_WWI/); -file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POW_WWQ/); -file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POW_WWW/); -file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POWSS_III/); -file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POWSS_IIQ/); -file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POWSS_IIW/); -file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POWSS_QQI/); -file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POWSS_QQQ/); -file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POWSS_QQW/); -file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POWSS_WWI/); -file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POWSS_WWQ/); -file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POWSS_WWW/); - -ok(1); -1; diff --git a/test_regress/t/t_math_pow.py b/test_regress/t/t_math_pow.py new file mode 100755 index 000000000..774a16957 --- /dev/null +++ b/test_regress/t/t_math_pow.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['-fno-gate']) + +test.execute(expect_filename=test.golden_filename) + +# Check for coverage on all POW functions +os.system("cat " + test.obj_dir + "/" + test.vm_prefix + "_*.cpp > " + test.obj_dir + "/all.cpp") + +test.file_grep(test.obj_dir + "/all.cpp", r'VL_POW_III') +test.file_grep(test.obj_dir + "/all.cpp", r'VL_POW_IIQ') +test.file_grep(test.obj_dir + "/all.cpp", r'VL_POW_IIW') +test.file_grep(test.obj_dir + "/all.cpp", r'VL_POW_QQI') +test.file_grep(test.obj_dir + "/all.cpp", r'VL_POW_QQQ') +test.file_grep(test.obj_dir + "/all.cpp", r'VL_POW_QQW') +test.file_grep(test.obj_dir + "/all.cpp", r'VL_POW_WWI') +test.file_grep(test.obj_dir + "/all.cpp", r'VL_POW_WWQ') +test.file_grep(test.obj_dir + "/all.cpp", r'VL_POW_WWW') +test.file_grep(test.obj_dir + "/all.cpp", r'VL_POWSS_III') +test.file_grep(test.obj_dir + "/all.cpp", r'VL_POWSS_IIQ') +test.file_grep(test.obj_dir + "/all.cpp", r'VL_POWSS_IIW') +test.file_grep(test.obj_dir + "/all.cpp", r'VL_POWSS_QQI') +test.file_grep(test.obj_dir + "/all.cpp", r'VL_POWSS_QQQ') +test.file_grep(test.obj_dir + "/all.cpp", r'VL_POWSS_QQW') +test.file_grep(test.obj_dir + "/all.cpp", r'VL_POWSS_WWI') +test.file_grep(test.obj_dir + "/all.cpp", r'VL_POWSS_WWQ') +test.file_grep(test.obj_dir + "/all.cpp", r'VL_POWSS_WWW') + +test.passes() diff --git a/test_regress/t/t_math_pow2.pl b/test_regress/t/t_math_pow2.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_math_pow2.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_pow2.py b/test_regress/t/t_math_pow2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_pow2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_pow3.pl b/test_regress/t/t_math_pow3.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_math_pow3.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_pow3.py b/test_regress/t/t_math_pow3.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_pow3.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_pow4.pl b/test_regress/t/t_math_pow4.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_math_pow4.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_pow4.py b/test_regress/t/t_math_pow4.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_pow4.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_pow5.pl b/test_regress/t/t_math_pow5.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_math_pow5.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_pow5.py b/test_regress/t/t_math_pow5.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_pow5.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_pow6.pl b/test_regress/t/t_math_pow6.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_math_pow6.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_pow6.py b/test_regress/t/t_math_pow6.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_pow6.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_pow7.pl b/test_regress/t/t_math_pow7.pl deleted file mode 100755 index 57487fac7..000000000 --- a/test_regress/t/t_math_pow7.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => [ - "--exe", - "$Self->{t_dir}/$Self->{name}.cpp" - ], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_pow7.py b/test_regress/t/t_math_pow7.py new file mode 100755 index 000000000..f37ad07c8 --- /dev/null +++ b/test_regress/t/t_math_pow7.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_precedence.pl b/test_regress/t/t_math_precedence.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_math_precedence.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_precedence.py b/test_regress/t/t_math_precedence.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_precedence.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_real.pl b/test_regress/t/t_math_real.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_math_real.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_real.py b/test_regress/t/t_math_real.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_real.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_real_public.pl b/test_regress/t/t_math_real_public.pl deleted file mode 100755 index 5238e8c79..000000000 --- a/test_regress/t/t_math_real_public.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--cc --public'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_real_public.py b/test_regress/t/t_math_real_public.py new file mode 100755 index 000000000..d219f422e --- /dev/null +++ b/test_regress/t/t_math_real_public.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--cc --public']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_real_random.pl b/test_regress/t/t_math_real_random.pl deleted file mode 100755 index 56363dab6..000000000 --- a/test_regress/t/t_math_real_random.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_real_random.py b/test_regress/t/t_math_real_random.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_real_random.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_real_round.pl b/test_regress/t/t_math_real_round.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_math_real_round.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_real_round.py b/test_regress/t/t_math_real_round.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_real_round.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_red.pl b/test_regress/t/t_math_red.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_math_red.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_red.py b/test_regress/t/t_math_red.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_red.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_red_noexpand.pl b/test_regress/t/t_math_red_noexpand.pl deleted file mode 100755 index 0dc056bd3..000000000 --- a/test_regress/t/t_math_red_noexpand.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_math_red.v"); - -compile( - verilator_flags2 => ['-fno-expand'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_red_noexpand.py b/test_regress/t/t_math_red_noexpand.py new file mode 100755 index 000000000..eb44fb046 --- /dev/null +++ b/test_regress/t/t_math_red_noexpand.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_math_red.v" + +test.compile(verilator_flags2=['-fno-expand']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_repl.pl b/test_regress/t/t_math_repl.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_math_repl.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_repl.py b/test_regress/t/t_math_repl.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_repl.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_repl2_bad.pl b/test_regress/t/t_math_repl2_bad.pl deleted file mode 100755 index 9c9fb65a0..000000000 --- a/test_regress/t/t_math_repl2_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_repl2_bad.py b/test_regress/t/t_math_repl2_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_math_repl2_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_math_repl_bad.pl b/test_regress/t/t_math_repl_bad.pl deleted file mode 100755 index 9c9fb65a0..000000000 --- a/test_regress/t/t_math_repl_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_repl_bad.py b/test_regress/t/t_math_repl_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_math_repl_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_math_reverse.pl b/test_regress/t/t_math_reverse.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_math_reverse.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_reverse.py b/test_regress/t/t_math_reverse.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_reverse.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_shift.pl b/test_regress/t/t_math_shift.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_math_shift.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_shift.py b/test_regress/t/t_math_shift.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_shift.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_shift_extend.pl b/test_regress/t/t_math_shift_extend.pl deleted file mode 100755 index 763e64f5b..000000000 --- a/test_regress/t/t_math_shift_extend.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute(); - -ok(1); -1; diff --git a/test_regress/t/t_math_shift_extend.py b/test_regress/t/t_math_shift_extend.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_shift_extend.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_shift_huge.pl b/test_regress/t/t_math_shift_huge.pl deleted file mode 100755 index 8c2ca139b..000000000 --- a/test_regress/t/t_math_shift_huge.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_shift_huge.py b/test_regress/t/t_math_shift_huge.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_math_shift_huge.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_math_shift_noexpand.pl b/test_regress/t/t_math_shift_noexpand.pl deleted file mode 100755 index 4eaf34c59..000000000 --- a/test_regress/t/t_math_shift_noexpand.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_math_shift.v"); - -compile( - verilator_flags2 => ['-fno-expand'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_shift_noexpand.py b/test_regress/t/t_math_shift_noexpand.py new file mode 100755 index 000000000..72d3f29af --- /dev/null +++ b/test_regress/t/t_math_shift_noexpand.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_math_shift.v" + +test.compile(verilator_flags2=['-fno-expand']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_shift_rep.pl b/test_regress/t/t_math_shift_rep.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_math_shift_rep.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_shift_rep.py b/test_regress/t/t_math_shift_rep.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_shift_rep.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_shift_sel.pl b/test_regress/t/t_math_shift_sel.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_math_shift_sel.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_shift_sel.py b/test_regress/t/t_math_shift_sel.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_shift_sel.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_shift_side.pl b/test_regress/t/t_math_shift_side.pl deleted file mode 100755 index e22e7f5d9..000000000 --- a/test_regress/t/t_math_shift_side.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_shift_side.py b/test_regress/t/t_math_shift_side.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_shift_side.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_shiftrs.pl b/test_regress/t/t_math_shiftrs.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_math_shiftrs.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_shiftrs.py b/test_regress/t/t_math_shiftrs.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_shiftrs.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_shortreal.pl b/test_regress/t/t_math_shortreal.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_math_shortreal.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_shortreal.py b/test_regress/t/t_math_shortreal.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_shortreal.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_shortreal_unsup_bad.pl b/test_regress/t/t_math_shortreal_unsup_bad.pl deleted file mode 100755 index 9c9fb65a0..000000000 --- a/test_regress/t/t_math_shortreal_unsup_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_shortreal_unsup_bad.py b/test_regress/t/t_math_shortreal_unsup_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_math_shortreal_unsup_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_math_sign_extend.pl b/test_regress/t/t_math_sign_extend.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_math_sign_extend.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_sign_extend.py b/test_regress/t/t_math_sign_extend.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_sign_extend.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_signed.pl b/test_regress/t/t_math_signed.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_math_signed.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_signed.py b/test_regress/t/t_math_signed.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_signed.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_signed2.pl b/test_regress/t/t_math_signed2.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_math_signed2.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_signed2.py b/test_regress/t/t_math_signed2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_signed2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_signed3.pl b/test_regress/t/t_math_signed3.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_math_signed3.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_signed3.py b/test_regress/t/t_math_signed3.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_signed3.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_signed4.pl b/test_regress/t/t_math_signed4.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_math_signed4.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_signed4.py b/test_regress/t/t_math_signed4.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_signed4.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_signed5.pl b/test_regress/t/t_math_signed5.pl deleted file mode 100755 index cfd2608b3..000000000 --- a/test_regress/t/t_math_signed5.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--binary --no-timing'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_signed5.py b/test_regress/t/t_math_signed5.py new file mode 100755 index 000000000..46560bc9c --- /dev/null +++ b/test_regress/t/t_math_signed5.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--binary --no-timing']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_signed5_timing.pl b/test_regress/t/t_math_signed5_timing.pl deleted file mode 100755 index 23b9de752..000000000 --- a/test_regress/t/t_math_signed5_timing.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_math_signed5.v"); - -compile( - verilator_flags2 => ['--binary --timing'], - timing_loop => 1, - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_signed5_timing.py b/test_regress/t/t_math_signed5_timing.py new file mode 100755 index 000000000..dd77ccb19 --- /dev/null +++ b/test_regress/t/t_math_signed5_timing.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_math_signed5.v" + +test.compile(verilator_flags2=['--binary --timing'], timing_loop=True) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_signed6.pl b/test_regress/t/t_math_signed6.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_math_signed6.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_signed6.py b/test_regress/t/t_math_signed6.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_signed6.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_signed7.pl b/test_regress/t/t_math_signed7.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_math_signed7.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_signed7.py b/test_regress/t/t_math_signed7.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_signed7.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_signed_calc.pl b/test_regress/t/t_math_signed_calc.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_math_signed_calc.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_signed_calc.py b/test_regress/t/t_math_signed_calc.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_signed_calc.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_signed_noexpand.pl b/test_regress/t/t_math_signed_noexpand.pl deleted file mode 100755 index cae6f528b..000000000 --- a/test_regress/t/t_math_signed_noexpand.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_math_signed.v"); - -compile( - verilator_flags2 => ['-fno-expand'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_signed_noexpand.py b/test_regress/t/t_math_signed_noexpand.py new file mode 100755 index 000000000..52c2b4c7a --- /dev/null +++ b/test_regress/t/t_math_signed_noexpand.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_math_signed.v" + +test.compile(verilator_flags2=['-fno-expand']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_signed_wire.pl b/test_regress/t/t_math_signed_wire.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_math_signed_wire.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_signed_wire.py b/test_regress/t/t_math_signed_wire.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_signed_wire.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_strwidth.pl b/test_regress/t/t_math_strwidth.pl deleted file mode 100755 index f5ab16fe8..000000000 --- a/test_regress/t/t_math_strwidth.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => [], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_strwidth.py b/test_regress/t/t_math_strwidth.py new file mode 100755 index 000000000..272dabc9b --- /dev/null +++ b/test_regress/t/t_math_strwidth.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=[]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_svl.pl b/test_regress/t/t_math_svl.pl deleted file mode 100755 index 1defe5d68..000000000 --- a/test_regress/t/t_math_svl.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2005 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - # Make sure we get the finish statement called - expect => -'\*-\* All Finished \*-\* -Goodbye world, at cycle \d+.*', - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_svl.py b/test_regress/t/t_math_svl.py new file mode 100755 index 000000000..492920838 --- /dev/null +++ b/test_regress/t/t_math_svl.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute( + # Make sure we get the finish statement called + expect=r"""\*-\* All Finished \*-\* +Goodbye world, at cycle \d+.*""") + +test.passes() diff --git a/test_regress/t/t_math_svl2.pl b/test_regress/t/t_math_svl2.pl deleted file mode 100755 index 264987108..000000000 --- a/test_regress/t/t_math_svl2.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2006 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_svl2.py b/test_regress/t/t_math_svl2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_svl2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_swap.pl b/test_regress/t/t_math_swap.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_math_swap.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_swap.py b/test_regress/t/t_math_swap.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_swap.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_tri.pl b/test_regress/t/t_math_tri.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_math_tri.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_tri.py b/test_regress/t/t_math_tri.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_tri.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_trig.pl b/test_regress/t/t_math_trig.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_math_trig.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_trig.py b/test_regress/t/t_math_trig.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_trig.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_vgen.pl b/test_regress/t/t_math_vgen.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_math_vgen.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_vgen.py b/test_regress/t/t_math_vgen.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_vgen.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_vliw.pl b/test_regress/t/t_math_vliw.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_math_vliw.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_vliw.py b/test_regress/t/t_math_vliw.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_vliw.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_vliw_noexpand.pl b/test_regress/t/t_math_vliw_noexpand.pl deleted file mode 100755 index 943a82414..000000000 --- a/test_regress/t/t_math_vliw_noexpand.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_math_vliw.v"); - -compile( - verilator_flags2 => ['-fno-expand'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_vliw_noexpand.py b/test_regress/t/t_math_vliw_noexpand.py new file mode 100755 index 000000000..ca6a4fa58 --- /dev/null +++ b/test_regress/t/t_math_vliw_noexpand.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_math_vliw.v" + +test.compile(verilator_flags2=['-fno-expand']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_wide_bad.pl b/test_regress/t/t_math_wide_bad.pl deleted file mode 100755 index 9c9fb65a0..000000000 --- a/test_regress/t/t_math_wide_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_wide_bad.py b/test_regress/t/t_math_wide_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_math_wide_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_math_wide_inc.pl b/test_regress/t/t_math_wide_inc.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_math_wide_inc.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_wide_inc.py b/test_regress/t/t_math_wide_inc.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_wide_inc.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_width.pl b/test_regress/t/t_math_width.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_math_width.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_width.py b/test_regress/t/t_math_width.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_width.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_yosys.pl b/test_regress/t/t_math_yosys.pl deleted file mode 100755 index 56363dab6..000000000 --- a/test_regress/t/t_math_yosys.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_math_yosys.py b/test_regress/t/t_math_yosys.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_math_yosys.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mem.pl b/test_regress/t/t_mem.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_mem.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem.py b/test_regress/t/t_mem.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_mem.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mem_banks.pl b/test_regress/t/t_mem_banks.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_mem_banks.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_banks.py b/test_regress/t/t_mem_banks.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_mem_banks.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mem_bound_bad.pl b/test_regress/t/t_mem_bound_bad.pl deleted file mode 100755 index d86162476..000000000 --- a/test_regress/t/t_mem_bound_bad.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => !$Self->{vlt_all}, # Should fail, but doesn't - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_bound_bad.py b/test_regress/t/t_mem_bound_bad.py new file mode 100755 index 000000000..c038d3707 --- /dev/null +++ b/test_regress/t/t_mem_bound_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint( + # Should fail, but doesn't) + fails=not test.vlt_all) + +test.passes() diff --git a/test_regress/t/t_mem_cond.pl b/test_regress/t/t_mem_cond.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_mem_cond.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_cond.py b/test_regress/t/t_mem_cond.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_mem_cond.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mem_fifo.pl b/test_regress/t/t_mem_fifo.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_mem_fifo.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_fifo.py b/test_regress/t/t_mem_fifo.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_mem_fifo.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mem_file.pl b/test_regress/t/t_mem_file.pl deleted file mode 100755 index cbc744927..000000000 --- a/test_regress/t/t_mem_file.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => [$Self->wno_unopthreads_for_few_cores()] - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_file.py b/test_regress/t/t_mem_file.py new file mode 100755 index 000000000..a06492309 --- /dev/null +++ b/test_regress/t/t_mem_file.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=[test.wno_unopthreads_for_few_cores]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mem_first.pl b/test_regress/t/t_mem_first.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_mem_first.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_first.py b/test_regress/t/t_mem_first.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_mem_first.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mem_func.pl b/test_regress/t/t_mem_func.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_mem_func.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_func.py b/test_regress/t/t_mem_func.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_mem_func.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mem_iforder.pl b/test_regress/t/t_mem_iforder.pl deleted file mode 100755 index 72847408e..000000000 --- a/test_regress/t/t_mem_iforder.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_iforder.py b/test_regress/t/t_mem_iforder.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_mem_iforder.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mem_multi_io.pl b/test_regress/t/t_mem_multi_io.pl deleted file mode 100755 index 41f33cc75..000000000 --- a/test_regress/t/t_mem_multi_io.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - # Disable inlining, this test is trivial without it - verilator_flags2 => ["-fno-inline --trace"], - verilator_flags3 => [], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_multi_io.py b/test_regress/t/t_mem_multi_io.py new file mode 100755 index 000000000..7b164ec7b --- /dev/null +++ b/test_regress/t/t_mem_multi_io.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + # Disable inlining, this test is trivial without it + verilator_flags2=["-fno-inline --trace"], + verilator_flags3=[]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mem_multi_io2_cc.pl b/test_regress/t/t_mem_multi_io2_cc.pl deleted file mode 100755 index 0ee829638..000000000 --- a/test_regress/t/t_mem_multi_io2_cc.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_mem_multi_io2.v"); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/t_mem_multi_io2.cpp -fno-inline"], - verilator_flags3 => [], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_multi_io2_cc.py b/test_regress/t/t_mem_multi_io2_cc.py new file mode 100755 index 000000000..de38bbd98 --- /dev/null +++ b/test_regress/t/t_mem_multi_io2_cc.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_mem_multi_io2.cpp" +test.top_filename = "t/t_mem_multi_io2.v" + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--exe", test.pli_filename, "-fno-inline"], + verilator_flags3=[]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mem_multi_io2_sc.pl b/test_regress/t/t_mem_multi_io2_sc.pl deleted file mode 100755 index 140980a20..000000000 --- a/test_regress/t/t_mem_multi_io2_sc.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_mem_multi_io2.v"); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/t_mem_multi_io2.cpp --sc -fno-inline"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_multi_io2_sc.py b/test_regress/t/t_mem_multi_io2_sc.py new file mode 100755 index 000000000..25fa435f5 --- /dev/null +++ b/test_regress/t/t_mem_multi_io2_sc.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_mem_multi_io2.cpp" +test.top_filename = "t/t_mem_multi_io2.v" + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--exe", test.pli_filename, "--sc -fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mem_multi_io3_cc.pl b/test_regress/t/t_mem_multi_io3_cc.pl deleted file mode 100755 index b6090a775..000000000 --- a/test_regress/t/t_mem_multi_io3_cc.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_mem_multi_io3.v"); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/t_mem_multi_io3.cpp -fno-inline"], - verilator_flags3 => [], - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_multi_io3_cc.py b/test_regress/t/t_mem_multi_io3_cc.py new file mode 100755 index 000000000..4cd1b4166 --- /dev/null +++ b/test_regress/t/t_mem_multi_io3_cc.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_mem_multi_io3.cpp" +test.top_filename = "t/t_mem_multi_io3.v" + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--exe", test.pli_filename, "-fno-inline"], + verilator_flags3=[]) + +test.passes() diff --git a/test_regress/t/t_mem_multi_io3_sc.pl b/test_regress/t/t_mem_multi_io3_sc.pl deleted file mode 100755 index f37d9dedd..000000000 --- a/test_regress/t/t_mem_multi_io3_sc.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_mem_multi_io3.v"); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/t_mem_multi_io3.cpp --sc -fno-inline"], - verilator_flags3 => [], - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_multi_io3_sc.py b/test_regress/t/t_mem_multi_io3_sc.py new file mode 100755 index 000000000..49c0e89c1 --- /dev/null +++ b/test_regress/t/t_mem_multi_io3_sc.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_mem_multi_io3.cpp" +test.top_filename = "t/t_mem_multi_io3.v" + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--exe", test.pli_filename, "--sc -fno-inline"], + verilator_flags3=[]) + +test.passes() diff --git a/test_regress/t/t_mem_multi_ref_bad.pl b/test_regress/t/t_mem_multi_ref_bad.pl deleted file mode 100755 index 7121b42e4..000000000 --- a/test_regress/t/t_mem_multi_ref_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - nc => 0, # Need to get it not to give the prompt - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_multi_ref_bad.py b/test_regress/t/t_mem_multi_ref_bad.py new file mode 100755 index 000000000..6e8952fd0 --- /dev/null +++ b/test_regress/t/t_mem_multi_ref_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint( + fails=test.vlt_all, + nc=False, # Need to get it not to give the prompt + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_mem_multidim.pl b/test_regress/t/t_mem_multidim.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_mem_multidim.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_multidim.py b/test_regress/t/t_mem_multidim.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_mem_multidim.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mem_multidim_Ox.pl b/test_regress/t/t_mem_multidim_Ox.pl deleted file mode 100755 index 3024f76cb..000000000 --- a/test_regress/t/t_mem_multidim_Ox.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_mem_multidim.v"); - -compile( - verilator_flags2 => ['--fno-expand'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_multidim_Ox.py b/test_regress/t/t_mem_multidim_Ox.py new file mode 100755 index 000000000..7b2c5a036 --- /dev/null +++ b/test_regress/t/t_mem_multidim_Ox.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_mem_multidim.v" + +test.compile(verilator_flags2=['--fno-expand']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mem_multidim_trace.pl b/test_regress/t/t_mem_multidim_trace.pl deleted file mode 100755 index 63be984b1..000000000 --- a/test_regress/t/t_mem_multidim_trace.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_mem_multidim.v"); - -compile( - verilator_flags2 => ['--cc --trace'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_multidim_trace.py b/test_regress/t/t_mem_multidim_trace.py new file mode 100755 index 000000000..8ac322e79 --- /dev/null +++ b/test_regress/t/t_mem_multidim_trace.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_mem_multidim.v" + +test.compile(verilator_flags2=['--cc --trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mem_multiwire.pl b/test_regress/t/t_mem_multiwire.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_mem_multiwire.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_multiwire.py b/test_regress/t/t_mem_multiwire.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_mem_multiwire.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mem_packed.pl b/test_regress/t/t_mem_packed.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_mem_packed.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_packed.py b/test_regress/t/t_mem_packed.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_mem_packed.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mem_packed_assign.pl b/test_regress/t/t_mem_packed_assign.pl deleted file mode 100755 index c144b5022..000000000 --- a/test_regress/t/t_mem_packed_assign.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_packed_assign.py b/test_regress/t/t_mem_packed_assign.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_mem_packed_assign.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mem_packed_bad.pl b/test_regress/t/t_mem_packed_bad.pl deleted file mode 100755 index 9c9fb65a0..000000000 --- a/test_regress/t/t_mem_packed_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_packed_bad.py b/test_regress/t/t_mem_packed_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_mem_packed_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_mem_packed_noexpand.pl b/test_regress/t/t_mem_packed_noexpand.pl deleted file mode 100755 index 86590761b..000000000 --- a/test_regress/t/t_mem_packed_noexpand.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_mem_packed.v"); - -compile( - verilator_flags2 => ['-fno-expand'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_packed_noexpand.py b/test_regress/t/t_mem_packed_noexpand.py new file mode 100755 index 000000000..0dcc3d32a --- /dev/null +++ b/test_regress/t/t_mem_packed_noexpand.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_mem_packed.v" + +test.compile(verilator_flags2=['-fno-expand']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mem_shift.pl b/test_regress/t/t_mem_shift.pl deleted file mode 100755 index b6026e614..000000000 --- a/test_regress/t/t_mem_shift.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, Delayed shared-sets\s+(\d+)/, 14); -} - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_shift.py b/test_regress/t/t_mem_shift.py new file mode 100755 index 000000000..ba44906f5 --- /dev/null +++ b/test_regress/t/t_mem_shift.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats"]) + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, Delayed shared-sets\s+(\d+)', 14) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mem_slice.pl b/test_regress/t/t_mem_slice.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_mem_slice.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_slice.py b/test_regress/t/t_mem_slice.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_mem_slice.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mem_slice_bad.pl b/test_regress/t/t_mem_slice_bad.pl deleted file mode 100755 index 9c9fb65a0..000000000 --- a/test_regress/t/t_mem_slice_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_slice_bad.py b/test_regress/t/t_mem_slice_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_mem_slice_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_mem_slice_conc_bad.pl b/test_regress/t/t_mem_slice_conc_bad.pl deleted file mode 100755 index 3be843059..000000000 --- a/test_regress/t/t_mem_slice_conc_bad.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_slice_conc_bad.py b/test_regress/t/t_mem_slice_conc_bad.py new file mode 100755 index 000000000..d14db8ce3 --- /dev/null +++ b/test_regress/t/t_mem_slice_conc_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True) + +test.passes() diff --git a/test_regress/t/t_mem_slice_dtype_bad.pl b/test_regress/t/t_mem_slice_dtype_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_mem_slice_dtype_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_slice_dtype_bad.py b/test_regress/t/t_mem_slice_dtype_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_mem_slice_dtype_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_mem_slot.pl b/test_regress/t/t_mem_slot.pl deleted file mode 100755 index 756442b6e..000000000 --- a/test_regress/t/t_mem_slot.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp --no-timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_slot.py b/test_regress/t/t_mem_slot.py new file mode 100755 index 000000000..7b94250d8 --- /dev/null +++ b/test_regress/t/t_mem_slot.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--exe", test.pli_filename, "--no-timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mem_twoedge.pl b/test_regress/t/t_mem_twoedge.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_mem_twoedge.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_mem_twoedge.py b/test_regress/t/t_mem_twoedge.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_mem_twoedge.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_merge_cond.pl b/test_regress/t/t_merge_cond.pl deleted file mode 100755 index 9af7b64ee..000000000 --- a/test_regress/t/t_merge_cond.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - verilator_flags2 => ["-unroll-count 64", "--stats"], - ); - -execute( - ); - -if ($Self->{vlt}) { - # Note, with vltmt this might be split differently, so only checking vlt - file_grep($Self->{stats}, qr/Optimizations, MergeCond merges\s+(\d+)/, - 9); - file_grep($Self->{stats}, qr/Optimizations, MergeCond merged items\s+(\d+)/, - 580); - file_grep($Self->{stats}, qr/Optimizations, MergeCond longest merge\s+(\d+)/, - 128); -} - -ok(1); -1; diff --git a/test_regress/t/t_merge_cond.py b/test_regress/t/t_merge_cond.py new file mode 100755 index 000000000..34bb401c0 --- /dev/null +++ b/test_regress/t/t_merge_cond.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(verilator_flags2=["-unroll-count 64", "--stats"]) + +test.execute() + +if test.vlt: + # Note, with vltmt this might be split differently, so only checking vlt + test.file_grep(test.stats, r'Optimizations, MergeCond merges\s+(\d+)', 9) + test.file_grep(test.stats, r'Optimizations, MergeCond merged items\s+(\d+)', 580) + test.file_grep(test.stats, r'Optimizations, MergeCond longest merge\s+(\d+)', 128) + +test.passes() diff --git a/test_regress/t/t_merge_cond_blowup.pl b/test_regress/t/t_merge_cond_blowup.pl deleted file mode 100755 index bda5fd2d7..000000000 --- a/test_regress/t/t_merge_cond_blowup.pl +++ /dev/null @@ -1,33 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Geza Lore. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -# TODO: This takes excessively long on vltmt, this should be fixed - -compile( - verilator_flags2 => ["--unroll-count 1000000000", "--output-split 0", "--stats"], - ); - -execute( - ); - -if ($Self->{vlt}) { - # Note, with vltmt this might be split differently, so only checking vlt - file_grep($Self->{stats}, qr/Optimizations, MergeCond merges\s+(\d+)/, - 500); # V3MergeCond.cpp MAX_DISTANCE - file_grep($Self->{stats}, qr/Optimizations, MergeCond merged items\s+(\d+)/, - 1000); # V3MergeCond.cpp MAX_DISTANCE *2 - file_grep($Self->{stats}, qr/Optimizations, MergeCond longest merge\s+(\d+)/, - 2); -} - -ok(1); -1; diff --git a/test_regress/t/t_merge_cond_blowup.py b/test_regress/t/t_merge_cond_blowup.py new file mode 100755 index 000000000..9602f04f6 --- /dev/null +++ b/test_regress/t/t_merge_cond_blowup.py @@ -0,0 +1,28 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +# TODO: This takes excessively long on vltmt, this should be fixed + +test.compile(verilator_flags2=["--unroll-count 1000000000", "--output-split 0", "--stats"]) + +test.execute() + +if test.vlt: + # Note, with vltmt this might be split differently, so only checking vlt + test.file_grep(test.stats, r'Optimizations, MergeCond merges\s+(\d+)', 500) + # V3MergeCond.cpp MAX_DISTANCE + test.file_grep(test.stats, r'Optimizations, MergeCond merged items\s+(\d+)', 1000) + # V3MergeCond.cpp MAX_DISTANCE *2 + test.file_grep(test.stats, r'Optimizations, MergeCond longest merge\s+(\d+)', 2) + +test.passes() diff --git a/test_regress/t/t_merge_cond_bug_3409.pl b/test_regress/t/t_merge_cond_bug_3409.pl deleted file mode 100755 index 6a407de6a..000000000 --- a/test_regress/t/t_merge_cond_bug_3409.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2=> ["--stats"] - ); - -execute(); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, MergeCond merges\s+(\d+)/, - 0); - file_grep($Self->{stats}, qr/Optimizations, MergeCond merged items\s+(\d+)/, - 0); - file_grep($Self->{stats}, qr/Optimizations, MergeCond longest merge\s+(\d+)/, - 0); -} - -ok(1); -1; diff --git a/test_regress/t/t_merge_cond_bug_3409.py b/test_regress/t/t_merge_cond_bug_3409.py new file mode 100755 index 000000000..e5bc05874 --- /dev/null +++ b/test_regress/t/t_merge_cond_bug_3409.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats"]) + +test.execute() + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, MergeCond merges\s+(\d+)', 0) + test.file_grep(test.stats, r'Optimizations, MergeCond merged items\s+(\d+)', 0) + test.file_grep(test.stats, r'Optimizations, MergeCond longest merge\s+(\d+)', 0) + +test.passes() diff --git a/test_regress/t/t_merge_cond_no_extend.pl b/test_regress/t/t_merge_cond_no_extend.pl deleted file mode 100755 index 41393c3bd..000000000 --- a/test_regress/t/t_merge_cond_no_extend.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Geza Lore. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -file_grep($Self->{stats}, qr/Optimizations, MergeCond merges\s+(\d+)/, 0); - -ok(1); -1; diff --git a/test_regress/t/t_merge_cond_no_extend.py b/test_regress/t/t_merge_cond_no_extend.py new file mode 100755 index 000000000..d85958438 --- /dev/null +++ b/test_regress/t/t_merge_cond_no_extend.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(verilator_flags2=["--stats"]) + +test.file_grep(test.stats, r'Optimizations, MergeCond merges\s+(\d+)', 0) + +test.passes() diff --git a/test_regress/t/t_merge_cond_no_motion.pl b/test_regress/t/t_merge_cond_no_motion.pl deleted file mode 100755 index f2a9b4f23..000000000 --- a/test_regress/t/t_merge_cond_no_motion.pl +++ /dev/null @@ -1,33 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Geza Lore. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_merge_cond.v"); - -compile( - verilator_flags2 => ["-unroll-count 64", "--stats", "-fno-merge-cond-motion"], - ); - -execute( - ); - -if ($Self->{vlt}) { - # Note, with vltmt this might be split differently, so only checking vlt - file_grep($Self->{stats}, qr/Optimizations, MergeCond merges\s+(\d+)/, - 10); - file_grep($Self->{stats}, qr/Optimizations, MergeCond merged items\s+(\d+)/, - 580); - file_grep($Self->{stats}, qr/Optimizations, MergeCond longest merge\s+(\d+)/, - 64); -} - -ok(1); -1; diff --git a/test_regress/t/t_merge_cond_no_motion.py b/test_regress/t/t_merge_cond_no_motion.py new file mode 100755 index 000000000..241c21a12 --- /dev/null +++ b/test_regress/t/t_merge_cond_no_motion.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_merge_cond.v" + +test.compile(verilator_flags2=["-unroll-count 64", "--stats", "-fno-merge-cond-motion"]) + +test.execute() + +if test.vlt: + # Note, with vltmt this might be split differently, so only checking vlt + test.file_grep(test.stats, r'Optimizations, MergeCond merges\s+(\d+)', 10) + test.file_grep(test.stats, r'Optimizations, MergeCond merged items\s+(\d+)', 580) + test.file_grep(test.stats, r'Optimizations, MergeCond longest merge\s+(\d+)', 64) + +test.passes() diff --git a/test_regress/t/t_metacmt_onoff.pl b/test_regress/t/t_metacmt_onoff.pl deleted file mode 100755 index 674687687..000000000 --- a/test_regress/t/t_metacmt_onoff.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_metacmt_onoff.py b/test_regress/t/t_metacmt_onoff.py new file mode 100755 index 000000000..6585af685 --- /dev/null +++ b/test_regress/t/t_metacmt_onoff.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_mod_dollar$.pl b/test_regress/t/t_mod_dollar$.pl deleted file mode 100755 index e4855df5c..000000000 --- a/test_regress/t/t_mod_dollar$.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -# This doesn't use the general compile rule as we want to make sure we form -# prefix properly using post-escaped identifiers -run(cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator", - "--cc", - "--Mdir " . $Self->{obj_dir} . "/t_mod_dollar", - "--exe --build --main", - 't/t_mod_dollar$.v', - ], - verilator_run => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mod_dollar$.py b/test_regress/t/t_mod_dollar$.py new file mode 100755 index 000000000..926c9b4d4 --- /dev/null +++ b/test_regress/t/t_mod_dollar$.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +# This doesn't use the general compile rule as we want to make sure we form +# prefix properly using post-escaped identifiers +test.run(cmd=[ + os.environ["VERILATOR_ROOT"] + "/bin/verilator", + "--cc", + "--Mdir " + test.obj_dir + "/t_mod_dollar", + "--exe --build --main", + 't/t_mod_dollar$.v', +], + verilator_run=True) + +test.passes() diff --git a/test_regress/t/t_mod_dup_bad.pl b/test_regress/t/t_mod_dup_bad.pl deleted file mode 100755 index b5861b2ab..000000000 --- a/test_regress/t/t_mod_dup_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mod_dup_bad.py b/test_regress/t/t_mod_dup_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_mod_dup_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_mod_dup_ign.pl b/test_regress/t/t_mod_dup_ign.pl deleted file mode 100755 index 8b318d39c..000000000 --- a/test_regress/t/t_mod_dup_ign.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_mod_dup_ign.py b/test_regress/t/t_mod_dup_ign.py new file mode 100755 index 000000000..f81c3d68d --- /dev/null +++ b/test_regress/t/t_mod_dup_ign.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_mod_interface_array0.pl b/test_regress/t/t_mod_interface_array0.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_mod_interface_array0.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_mod_interface_array0.py b/test_regress/t/t_mod_interface_array0.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_mod_interface_array0.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mod_interface_array0_noinl.pl b/test_regress/t/t_mod_interface_array0_noinl.pl deleted file mode 100755 index b9959c339..000000000 --- a/test_regress/t/t_mod_interface_array0_noinl.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_mod_interface_array0.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_mod_interface_array0_noinl.py b/test_regress/t/t_mod_interface_array0_noinl.py new file mode 100755 index 000000000..d82128883 --- /dev/null +++ b/test_regress/t/t_mod_interface_array0_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_mod_interface_array0.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mod_interface_array1.pl b/test_regress/t/t_mod_interface_array1.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_mod_interface_array1.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_mod_interface_array1.py b/test_regress/t/t_mod_interface_array1.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_mod_interface_array1.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mod_interface_array1_noinl.pl b/test_regress/t/t_mod_interface_array1_noinl.pl deleted file mode 100755 index fe75255be..000000000 --- a/test_regress/t/t_mod_interface_array1_noinl.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_mod_interface_array1.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_mod_interface_array1_noinl.py b/test_regress/t/t_mod_interface_array1_noinl.py new file mode 100755 index 000000000..6d7fc4468 --- /dev/null +++ b/test_regress/t/t_mod_interface_array1_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_mod_interface_array1.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mod_interface_array2.pl b/test_regress/t/t_mod_interface_array2.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_mod_interface_array2.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_mod_interface_array2.py b/test_regress/t/t_mod_interface_array2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_mod_interface_array2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mod_interface_array2_noinl.pl b/test_regress/t/t_mod_interface_array2_noinl.pl deleted file mode 100755 index 571dc1bc5..000000000 --- a/test_regress/t/t_mod_interface_array2_noinl.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_mod_interface_array2.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_mod_interface_array2_noinl.py b/test_regress/t/t_mod_interface_array2_noinl.py new file mode 100755 index 000000000..c0f6c74f7 --- /dev/null +++ b/test_regress/t/t_mod_interface_array2_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_mod_interface_array2.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mod_interface_array3.pl b/test_regress/t/t_mod_interface_array3.pl deleted file mode 100755 index a29ead0ed..000000000 --- a/test_regress/t/t_mod_interface_array3.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_mod_interface_array3.py b/test_regress/t/t_mod_interface_array3.py new file mode 100755 index 000000000..efe8cc01c --- /dev/null +++ b/test_regress/t/t_mod_interface_array3.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_mod_interface_array4.pl b/test_regress/t/t_mod_interface_array4.pl deleted file mode 100755 index 6e1338f8e..000000000 --- a/test_regress/t/t_mod_interface_array4.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_mod_interface_array4.py b/test_regress/t/t_mod_interface_array4.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_mod_interface_array4.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mod_interface_array4_noinl.pl b/test_regress/t/t_mod_interface_array4_noinl.pl deleted file mode 100755 index 84aa23a68..000000000 --- a/test_regress/t/t_mod_interface_array4_noinl.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_mod_interface_array4.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_mod_interface_array4_noinl.py b/test_regress/t/t_mod_interface_array4_noinl.py new file mode 100755 index 000000000..5c330f73d --- /dev/null +++ b/test_regress/t/t_mod_interface_array4_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_mod_interface_array4.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mod_interface_array5.pl b/test_regress/t/t_mod_interface_array5.pl deleted file mode 100755 index 6e1338f8e..000000000 --- a/test_regress/t/t_mod_interface_array5.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_mod_interface_array5.py b/test_regress/t/t_mod_interface_array5.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_mod_interface_array5.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mod_interface_array6.pl b/test_regress/t/t_mod_interface_array6.pl deleted file mode 100755 index 6e1338f8e..000000000 --- a/test_regress/t/t_mod_interface_array6.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_mod_interface_array6.py b/test_regress/t/t_mod_interface_array6.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_mod_interface_array6.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mod_interface_array6_noinl.pl b/test_regress/t/t_mod_interface_array6_noinl.pl deleted file mode 100755 index 6cbca0855..000000000 --- a/test_regress/t/t_mod_interface_array6_noinl.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_mod_interface_array6.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_mod_interface_array6_noinl.py b/test_regress/t/t_mod_interface_array6_noinl.py new file mode 100755 index 000000000..1740bd164 --- /dev/null +++ b/test_regress/t/t_mod_interface_array6_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_mod_interface_array6.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mod_longname.pl b/test_regress/t/t_mod_longname.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_mod_longname.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_mod_longname.py b/test_regress/t/t_mod_longname.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_mod_longname.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mod_nomod.pl b/test_regress/t/t_mod_nomod.pl deleted file mode 100755 index e26d2aa31..000000000 --- a/test_regress/t/t_mod_nomod.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_mod_nomod.py b/test_regress/t/t_mod_nomod.py new file mode 100755 index 000000000..3527cdb06 --- /dev/null +++ b/test_regress/t/t_mod_nomod.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_mod_recurse.pl b/test_regress/t/t_mod_recurse.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_mod_recurse.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_mod_recurse.py b/test_regress/t/t_mod_recurse.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_mod_recurse.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mod_recurse1.pl b/test_regress/t/t_mod_recurse1.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_mod_recurse1.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_mod_recurse1.py b/test_regress/t/t_mod_recurse1.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_mod_recurse1.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mod_topmodule.pl b/test_regress/t/t_mod_topmodule.pl deleted file mode 100755 index e69c2db66..000000000 --- a/test_regress/t/t_mod_topmodule.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--top-module top"] - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_mod_topmodule.py b/test_regress/t/t_mod_topmodule.py new file mode 100755 index 000000000..2ea7dd9e0 --- /dev/null +++ b/test_regress/t/t_mod_topmodule.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--top-module top"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mod_topmodule_nest.pl b/test_regress/t/t_mod_topmodule_nest.pl deleted file mode 100755 index e69c2db66..000000000 --- a/test_regress/t/t_mod_topmodule_nest.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--top-module top"] - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_mod_topmodule_nest.py b/test_regress/t/t_mod_topmodule_nest.py new file mode 100755 index 000000000..2ea7dd9e0 --- /dev/null +++ b/test_regress/t/t_mod_topmodule_nest.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--top-module top"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mod_uselib.pl b/test_regress/t/t_mod_uselib.pl deleted file mode 100755 index 8fbc2f576..000000000 --- a/test_regress/t/t_mod_uselib.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_mod_uselib.py b/test_regress/t/t_mod_uselib.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_mod_uselib.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_module_class_static_method.pl b/test_regress/t/t_module_class_static_method.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_module_class_static_method.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_module_class_static_method.py b/test_regress/t/t_module_class_static_method.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_module_class_static_method.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_module_input_default_value.pl b/test_regress/t/t_module_input_default_value.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_module_input_default_value.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_module_input_default_value.py b/test_regress/t/t_module_input_default_value.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_module_input_default_value.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_module_input_default_value_1_bad.pl b/test_regress/t/t_module_input_default_value_1_bad.pl deleted file mode 100755 index b9057722c..000000000 --- a/test_regress/t/t_module_input_default_value_1_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_module_input_default_value_1_bad.py b/test_regress/t/t_module_input_default_value_1_bad.py new file mode 100755 index 000000000..3def97587 --- /dev/null +++ b/test_regress/t/t_module_input_default_value_1_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_module_input_default_value_2_bad.pl b/test_regress/t/t_module_input_default_value_2_bad.pl deleted file mode 100755 index b9057722c..000000000 --- a/test_regress/t/t_module_input_default_value_2_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_module_input_default_value_2_bad.py b/test_regress/t/t_module_input_default_value_2_bad.py new file mode 100755 index 000000000..3def97587 --- /dev/null +++ b/test_regress/t/t_module_input_default_value_2_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_module_input_default_value_3_bad.pl b/test_regress/t/t_module_input_default_value_3_bad.pl deleted file mode 100755 index b9057722c..000000000 --- a/test_regress/t/t_module_input_default_value_3_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_module_input_default_value_3_bad.py b/test_regress/t/t_module_input_default_value_3_bad.py new file mode 100755 index 000000000..3def97587 --- /dev/null +++ b/test_regress/t/t_module_input_default_value_3_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_module_input_default_value_noinl.pl b/test_regress/t/t_module_input_default_value_noinl.pl deleted file mode 100755 index d09dba4d9..000000000 --- a/test_regress/t/t_module_input_default_value_noinl.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_module_input_default_value.v"); - -compile( - v_flags2 => ["-fno-inline"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_module_input_default_value_noinl.py b/test_regress/t/t_module_input_default_value_noinl.py new file mode 100755 index 000000000..7858944b8 --- /dev/null +++ b/test_regress/t/t_module_input_default_value_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_module_input_default_value.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_multiline_waivers.pl b/test_regress/t/t_multiline_waivers.pl deleted file mode 100755 index 6cfad5889..000000000 --- a/test_regress/t/t_multiline_waivers.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/$Self->{name}_waiver_gen.vlt"; -my $waiver_filename = "$Self->{obj_dir}/$Self->{name}_waiver.vlt"; - -compile( - v_flags2 => ['--waiver-output', $out_filename], - fails => 1, - ); - -file_sed($out_filename, $waiver_filename, - sub { s/\/\/ lint_off/lint_off/g; }); - -compile( - v_flags2 => [$waiver_filename], - ); - -ok(1); -1; diff --git a/test_regress/t/t_multiline_waivers.py b/test_regress/t/t_multiline_waivers.py new file mode 100755 index 000000000..3f3414f68 --- /dev/null +++ b/test_regress/t/t_multiline_waivers.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +out_filename = test.obj_dir + "/" + test.name + "_waiver_gen.vlt" +waiver_filename = test.obj_dir + "/" + test.name + "_waiver.vlt" + +test.compile(v_flags2=['--waiver-output', out_filename], fails=True) + +test.file_sed(out_filename, waiver_filename, + lambda line: re.sub(r'\/\/ lint_off', 'lint_off', line)) + +test.compile(v_flags2=[waiver_filename]) + +test.passes() diff --git a/test_regress/t/t_multitop1.pl b/test_regress/t/t_multitop1.pl deleted file mode 100755 index e70f69cd0..000000000 --- a/test_regress/t/t_multitop1.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - ); - -execute( - check_finished => 0, - ); - -# Order of lines is unspecified, so don't use a golden file -file_grep($Self->{run_log_filename}, qr!In 'top.t'!); -file_grep($Self->{run_log_filename}, qr!In 'top.t.s'!); -file_grep_not($Self->{run_log_filename}, qr!in_subfile!); - -ok(1); -1; diff --git a/test_regress/t/t_multitop1.py b/test_regress/t/t_multitop1.py new file mode 100755 index 000000000..86e5ab5e5 --- /dev/null +++ b/test_regress/t/t_multitop1.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile() + +test.execute(check_finished=False) + +# Order of lines is unspecified, so don't use a golden file +test.file_grep(test.run_log_filename, r"In 'top.t'") +test.file_grep(test.run_log_filename, r"In 'top.t.s'") +test.file_grep_not(test.run_log_filename, r"in_subfile") + +test.passes() diff --git a/test_regress/t/t_multitop_sig.pl b/test_regress/t/t_multitop_sig.pl deleted file mode 100755 index 208271dd7..000000000 --- a/test_regress/t/t_multitop_sig.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["-Wno-MULTITOP --exe $Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - ); - -file_grep($Self->{run_log_filename}, qr!In 'a'!); -file_grep($Self->{run_log_filename}, qr!In 'a.sub'!); -file_grep($Self->{run_log_filename}, qr!In 'b'!); -file_grep($Self->{run_log_filename}, qr!In 'b.sub'!); -file_grep($Self->{run_log_filename}, qr!In 'c'!); -file_grep($Self->{run_log_filename}, qr!In 'c.sub'!); - -ok(1); -1; diff --git a/test_regress/t/t_multitop_sig.py b/test_regress/t/t_multitop_sig.py new file mode 100755 index 000000000..b70faf4bc --- /dev/null +++ b/test_regress/t/t_multitop_sig.py @@ -0,0 +1,27 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["-Wno-MULTITOP --exe", test.pli_filename]) + +test.execute() + +test.file_grep(test.run_log_filename, r"In 'a'") +test.file_grep(test.run_log_filename, r"In 'a.sub'") +test.file_grep(test.run_log_filename, r"In 'b'") +test.file_grep(test.run_log_filename, r"In 'b.sub'") +test.file_grep(test.run_log_filename, r"In 'c'") +test.file_grep(test.run_log_filename, r"In 'c.sub'") + +test.passes() diff --git a/test_regress/t/t_multitop_sig_bad.pl b/test_regress/t/t_multitop_sig_bad.pl deleted file mode 100755 index f3b7679b6..000000000 --- a/test_regress/t/t_multitop_sig_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -top_filename("t/t_multitop_sig.v"); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_multitop_sig_bad.py b/test_regress/t/t_multitop_sig_bad.py new file mode 100755 index 000000000..b76511c6c --- /dev/null +++ b/test_regress/t/t_multitop_sig_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_multitop_sig.v" + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_name_collision.pl b/test_regress/t/t_name_collision.pl deleted file mode 100755 index feca268d4..000000000 --- a/test_regress/t/t_name_collision.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--coverage'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_name_collision.py b/test_regress/t/t_name_collision.py new file mode 100755 index 000000000..fdaf03625 --- /dev/null +++ b/test_regress/t/t_name_collision.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--coverage']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_nba_commit_queue.pl b/test_regress/t/t_nba_commit_queue.pl deleted file mode 100755 index 04eaa131e..000000000 --- a/test_regress/t/t_nba_commit_queue.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - verilator_flags2 => ["-unroll-count 1", "--stats"], - ); - -execute( - ); - -file_grep($Self->{stats}, qr/Dynamic NBA, variables needing commit queue without partial updates\s+(\d+)/, - 6); -file_grep($Self->{stats}, qr/Dynamic NBA, variables needing commit queue with partial updates\s+(\d+)/, - 3); - -ok(1); -1; diff --git a/test_regress/t/t_nba_commit_queue.py b/test_regress/t/t_nba_commit_queue.py new file mode 100755 index 000000000..154e017d3 --- /dev/null +++ b/test_regress/t/t_nba_commit_queue.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(verilator_flags2=["-unroll-count 1", "--stats"]) + +test.execute() + +test.file_grep(test.stats, + r'Dynamic NBA, variables needing commit queue without partial updates\s+(\d+)', 6) +test.file_grep(test.stats, + r'Dynamic NBA, variables needing commit queue with partial updates\s+(\d+)', 3) + +test.passes() diff --git a/test_regress/t/t_negated_property.pl b/test_regress/t/t_negated_property.pl deleted file mode 100755 index f96aad9b7..000000000 --- a/test_regress/t/t_negated_property.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--assert'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_negated_property.py b/test_regress/t/t_negated_property.py new file mode 100755 index 000000000..2c4ffdce2 --- /dev/null +++ b/test_regress/t/t_negated_property.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--assert']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_net_delay.pl b/test_regress/t/t_net_delay.pl deleted file mode 100755 index 09ee1bbae..000000000 --- a/test_regress/t/t_net_delay.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint( - verilator_flags2 => ['-Wall -Wno-DECLFILENAME --no-timing'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_net_delay.py b/test_regress/t/t_net_delay.py new file mode 100755 index 000000000..2424f0de5 --- /dev/null +++ b/test_regress/t/t_net_delay.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(verilator_flags2=['-Wall -Wno-DECLFILENAME --no-timing'], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_net_delay_timing.pl b/test_regress/t/t_net_delay_timing.pl deleted file mode 100755 index 658376a53..000000000 --- a/test_regress/t/t_net_delay_timing.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_net_delay.v"); - -compile( - timing_loop => 1, - verilator_flags2 => ["--timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_net_delay_timing.py b/test_regress/t/t_net_delay_timing.py new file mode 100755 index 000000000..bc41b20a9 --- /dev/null +++ b/test_regress/t/t_net_delay_timing.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_net_delay.v" + +test.compile(timing_loop=True, verilator_flags2=["--timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_net_delay_timing_sc.pl b/test_regress/t/t_net_delay_timing_sc.pl deleted file mode 100755 index 1e02c8790..000000000 --- a/test_regress/t/t_net_delay_timing_sc.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -$Self->{main_time_multiplier} = 2; - -top_filename("t/t_net_delay.v"); - -compile( - verilator_flags2 => ["--sc --exe --timing --timescale 10ps/1ps"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_net_delay_timing_sc.py b/test_regress/t/t_net_delay_timing_sc.py new file mode 100755 index 000000000..9e15c738f --- /dev/null +++ b/test_regress/t/t_net_delay_timing_sc.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_net_delay.v" +test.main_time_multiplier = 2 + +test.compile(verilator_flags2=["--sc --exe --timing --timescale 10ps/1ps"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_nettype.pl b/test_regress/t/t_nettype.pl deleted file mode 100755 index 376c2d2ee..000000000 --- a/test_regress/t/t_nettype.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_nettype.py b/test_regress/t/t_nettype.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_nettype.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_no_sel_assign_merge_in_cpp.pl b/test_regress/t/t_no_sel_assign_merge_in_cpp.pl deleted file mode 100755 index 72441b2f8..000000000 --- a/test_regress/t/t_no_sel_assign_merge_in_cpp.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_no_sel_assign_merge_in_cpp.py b/test_regress/t/t_no_sel_assign_merge_in_cpp.py new file mode 100755 index 000000000..f81c3d68d --- /dev/null +++ b/test_regress/t/t_no_sel_assign_merge_in_cpp.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_no_std_bad.pl b/test_regress/t/t_no_std_bad.pl deleted file mode 100755 index b7236cf3c..000000000 --- a/test_regress/t/t_no_std_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint(fails => 1, - verilator_flags2 => ["--no-std", "--exe --main --timing -Wall"], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_no_std_bad.py b/test_regress/t/t_no_std_bad.py new file mode 100755 index 000000000..1f7e09325 --- /dev/null +++ b/test_regress/t/t_no_std_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(fails=True, + verilator_flags2=["--no-std", "--exe --main --timing -Wall"], + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_no_trace_top.pl b/test_regress/t/t_no_trace_top.pl deleted file mode 100755 index 5eecece00..000000000 --- a/test_regress/t/t_no_trace_top.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2013 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t_trace_cat.v"); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ["--trace --no-trace-top --exe $Self->{t_dir}/t_no_trace_top.cpp"], - ); - -execute( - ); - -vcd_identical("$Self->{obj_dir}/simno_trace_top.vcd", - $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_no_trace_top.py b/test_regress/t/t_no_trace_top.py new file mode 100755 index 000000000..06f1eac14 --- /dev/null +++ b/test_regress/t/t_no_trace_top.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t_trace_cat.v" + +test.compile(make_top_shell=False, + make_main=False, + v_flags2=["--trace --no-trace-top --exe", test.pli_filename]) + +test.execute() + +test.vcd_identical(test.obj_dir + "/simno_trace_top.vcd", test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_no_typedef_bad.pl b/test_regress/t/t_no_typedef_bad.pl deleted file mode 100755 index a9a904f17..000000000 --- a/test_regress/t/t_no_typedef_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--json-only"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_no_typedef_bad.py b/test_regress/t/t_no_typedef_bad.py new file mode 100755 index 000000000..33cb398b7 --- /dev/null +++ b/test_regress/t/t_no_typedef_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--json-only"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_notiming.pl b/test_regress/t/t_notiming.pl deleted file mode 100755 index bf475c910..000000000 --- a/test_regress/t/t_notiming.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint( - verilator_flags2 => ["--no-timing"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_notiming.py b/test_regress/t/t_notiming.py new file mode 100755 index 000000000..6f71603b5 --- /dev/null +++ b/test_regress/t/t_notiming.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(verilator_flags2=["--no-timing"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_notiming_off.pl b/test_regress/t/t_notiming_off.pl deleted file mode 100755 index 955b160b1..000000000 --- a/test_regress/t/t_notiming_off.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_timing_off.v"); - -lint( - verilator_flags2 => ["--no-timing"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_notiming_off.py b/test_regress/t/t_notiming_off.py new file mode 100755 index 000000000..a1cb5082f --- /dev/null +++ b/test_regress/t/t_notiming_off.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_timing_off.v" + +test.lint(verilator_flags2=["--no-timing"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_number_bad.pl b/test_regress/t/t_number_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_number_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_number_bad.py b/test_regress/t/t_number_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_number_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_number_v_bad.pl b/test_regress/t/t_number_v_bad.pl deleted file mode 100755 index 24b1e474d..000000000 --- a/test_regress/t/t_number_v_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Ethan Sifferman and Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--language 1364-2005"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_number_v_bad.py b/test_regress/t/t_number_v_bad.py new file mode 100755 index 000000000..93c8b0951 --- /dev/null +++ b/test_regress/t/t_number_v_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--language 1364-2005"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_opt_dead.pl b/test_regress/t/t_opt_dead.pl deleted file mode 100755 index cf4dd74fb..000000000 --- a/test_regress/t/t_opt_dead.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -# bug2227, Verilator unsupported, class dead -# This is what we really want: -# file_grep_not("$Self->{obj_dir}/V$Self->{name}__Syms.h", qr/dead/); -file_grep("$Self->{obj_dir}/V$Self->{name}__Syms.h", qr/dead/); - -ok(1); -1; diff --git a/test_regress/t/t_opt_dead.py b/test_regress/t/t_opt_dead.py new file mode 100755 index 000000000..10b9c67ff --- /dev/null +++ b/test_regress/t/t_opt_dead.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +# bug2227, Verilator unsupported, class dead +# This is what we really want: +# test.file_grep_not(test.obj_dir + "/V"+test.name+"__Syms.h", r'dead') +test.file_grep(test.obj_dir + "/V" + test.name + "__Syms.h", r'dead') + +test.passes() diff --git a/test_regress/t/t_opt_dead_noassigns.pl b/test_regress/t/t_opt_dead_noassigns.pl deleted file mode 100755 index 62206e42e..000000000 --- a/test_regress/t/t_opt_dead_noassigns.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--fno-dead-assigns'], - ); - -execute( - ); - -my @files = glob_all("$Self->{obj_dir}/$Self->{vm_prefix}_*.cpp"); -file_grep_any(\@files, qr/keptdead/); - -ok(1); -1; diff --git a/test_regress/t/t_opt_dead_noassigns.py b/test_regress/t/t_opt_dead_noassigns.py new file mode 100755 index 000000000..c191088d1 --- /dev/null +++ b/test_regress/t/t_opt_dead_noassigns.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--fno-dead-assigns']) + +test.execute() + +files = test.glob_some(test.obj_dir + "/" + test.vm_prefix + "_*.cpp") +test.file_grep_any(files, r'keptdead') + +test.passes() diff --git a/test_regress/t/t_opt_dead_nocells.pl b/test_regress/t/t_opt_dead_nocells.pl deleted file mode 100755 index 60b8f1f2c..000000000 --- a/test_regress/t/t_opt_dead_nocells.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ['--fno-inline', '--fno-dead-cells'], - ); - -my @files = glob_all("$Self->{obj_dir}/$Self->{vm_prefix}_*.h"); -file_grep_any(\@files, qr/keptdead/); - -ok(1); -1; diff --git a/test_regress/t/t_opt_dead_nocells.py b/test_regress/t/t_opt_dead_nocells.py new file mode 100755 index 000000000..3637842f4 --- /dev/null +++ b/test_regress/t/t_opt_dead_nocells.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['--fno-inline', '--fno-dead-cells']) + +files = test.glob_some(test.obj_dir + "/" + test.vm_prefix + "_*.h") +test.file_grep_any(files, r'keptdead') + +test.passes() diff --git a/test_regress/t/t_opt_localize_deep.pl b/test_regress/t/t_opt_localize_deep.pl deleted file mode 100755 index 1185a445f..000000000 --- a/test_regress/t/t_opt_localize_deep.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--compiler msvc"], # We have deep expressions we want to test - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_opt_localize_deep.py b/test_regress/t/t_opt_localize_deep.py new file mode 100755 index 000000000..539f320b1 --- /dev/null +++ b/test_regress/t/t_opt_localize_deep.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + # We have deep expressions we want to test) + verilator_flags2=["--compiler msvc"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_opt_localize_max_size.pl b/test_regress/t/t_opt_localize_max_size.pl deleted file mode 100755 index 08c91af72..000000000 --- a/test_regress/t/t_opt_localize_max_size.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -execute( - ); - -# Value must differ from that in t_opt_localize_max_size.pl -file_grep($Self->{stats}, qr/Optimizations, Vars localized\s+(\d+)/, 5); - -ok(1); -1; diff --git a/test_regress/t/t_opt_localize_max_size.py b/test_regress/t/t_opt_localize_max_size.py new file mode 100755 index 000000000..0e8655407 --- /dev/null +++ b/test_regress/t/t_opt_localize_max_size.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--stats"]) + +test.execute() + +# Value must differ from that in t_opt_localize_max_size.py +test.file_grep(test.stats, r'Optimizations, Vars localized\s+(\d+)', 5) + +test.passes() diff --git a/test_regress/t/t_opt_localize_max_size_1.pl b/test_regress/t/t_opt_localize_max_size_1.pl deleted file mode 100755 index ca334ac3f..000000000 --- a/test_regress/t/t_opt_localize_max_size_1.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_opt_localize_max_size.v"); - -compile( - verilator_flags2 => ["--stats --localize-max-size 1"], - ); - -execute( - ); - -# Value must differ from that in t_opt_localize_max_size.pl -file_grep($Self->{stats}, qr/Optimizations, Vars localized\s+(\d+)/, 4); - -ok(1); -1; diff --git a/test_regress/t/t_opt_localize_max_size_1.py b/test_regress/t/t_opt_localize_max_size_1.py new file mode 100755 index 000000000..72657566d --- /dev/null +++ b/test_regress/t/t_opt_localize_max_size_1.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_opt_localize_max_size.v" + +test.compile(verilator_flags2=["--stats --localize-max-size 1"]) + +test.execute() + +# Value must differ from that in t_opt_localize_max_size.py +test.file_grep(test.stats, r'Optimizations, Vars localized\s+(\d+)', 4) + +test.passes() diff --git a/test_regress/t/t_opt_table_display.pl b/test_regress/t/t_opt_table_display.pl deleted file mode 100755 index 3e1680a43..000000000 --- a/test_regress/t/t_opt_table_display.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_opt_table_display.py b/test_regress/t/t_opt_table_display.py new file mode 100755 index 000000000..e8fd08599 --- /dev/null +++ b/test_regress/t/t_opt_table_display.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_opt_table_enum.pl b/test_regress/t/t_opt_table_enum.pl deleted file mode 100755 index 6a3f89ba3..000000000 --- a/test_regress/t/t_opt_table_enum.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, Tables created\s+(\d+)/, 1); - file_grep($Self->{stats}, qr/ConstPool, Tables emitted\s+(\d+)/, 1); -} - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_opt_table_enum.py b/test_regress/t/t_opt_table_enum.py new file mode 100755 index 000000000..912dd4cf8 --- /dev/null +++ b/test_regress/t/t_opt_table_enum.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats"]) + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, Tables created\s+(\d+)', 1) + test.file_grep(test.stats, r'ConstPool, Tables emitted\s+(\d+)', 1) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_opt_table_packed_array.pl b/test_regress/t/t_opt_table_packed_array.pl deleted file mode 100755 index 6a3f89ba3..000000000 --- a/test_regress/t/t_opt_table_packed_array.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, Tables created\s+(\d+)/, 1); - file_grep($Self->{stats}, qr/ConstPool, Tables emitted\s+(\d+)/, 1); -} - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_opt_table_packed_array.py b/test_regress/t/t_opt_table_packed_array.py new file mode 100755 index 000000000..912dd4cf8 --- /dev/null +++ b/test_regress/t/t_opt_table_packed_array.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats"]) + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, Tables created\s+(\d+)', 1) + test.file_grep(test.stats, r'ConstPool, Tables emitted\s+(\d+)', 1) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_opt_table_real.pl b/test_regress/t/t_opt_table_real.pl deleted file mode 100755 index a022e91de..000000000 --- a/test_regress/t/t_opt_table_real.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, Tables created\s+(\d+)/, 1); - file_grep($Self->{stats}, qr/ConstPool, Tables emitted\s+(\d+)/, 1); -} - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_opt_table_real.py b/test_regress/t/t_opt_table_real.py new file mode 100755 index 000000000..912dd4cf8 --- /dev/null +++ b/test_regress/t/t_opt_table_real.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats"]) + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, Tables created\s+(\d+)', 1) + test.file_grep(test.stats, r'ConstPool, Tables emitted\s+(\d+)', 1) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_opt_table_same.pl b/test_regress/t/t_opt_table_same.pl deleted file mode 100755 index bda76de82..000000000 --- a/test_regress/t/t_opt_table_same.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, Tables created\s+(\d+)/, 2); - file_grep($Self->{stats}, qr/ConstPool, Tables emitted\s+(\d+)/, 1); -} - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_opt_table_same.py b/test_regress/t/t_opt_table_same.py new file mode 100755 index 000000000..622bd1b1b --- /dev/null +++ b/test_regress/t/t_opt_table_same.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats"]) + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, Tables created\s+(\d+)', 2) + test.file_grep(test.stats, r'ConstPool, Tables emitted\s+(\d+)', 1) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_opt_table_signed.pl b/test_regress/t/t_opt_table_signed.pl deleted file mode 100755 index 6a3f89ba3..000000000 --- a/test_regress/t/t_opt_table_signed.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, Tables created\s+(\d+)/, 1); - file_grep($Self->{stats}, qr/ConstPool, Tables emitted\s+(\d+)/, 1); -} - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_opt_table_signed.py b/test_regress/t/t_opt_table_signed.py new file mode 100755 index 000000000..912dd4cf8 --- /dev/null +++ b/test_regress/t/t_opt_table_signed.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats"]) + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, Tables created\s+(\d+)', 1) + test.file_grep(test.stats, r'ConstPool, Tables emitted\s+(\d+)', 1) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_opt_table_sparse.pl b/test_regress/t/t_opt_table_sparse.pl deleted file mode 100755 index 5f7ab5ac6..000000000 --- a/test_regress/t/t_opt_table_sparse.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, Tables created\s+(\d+)/, 1); - file_grep($Self->{stats}, qr/ConstPool, Tables emitted\s+(\d+)/, 2); -} - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_opt_table_sparse.py b/test_regress/t/t_opt_table_sparse.py new file mode 100755 index 000000000..9d5ac0261 --- /dev/null +++ b/test_regress/t/t_opt_table_sparse.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats"]) + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, Tables created\s+(\d+)', 1) + test.file_grep(test.stats, r'ConstPool, Tables emitted\s+(\d+)', 2) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_opt_table_sparse_output_split.pl b/test_regress/t/t_opt_table_sparse_output_split.pl deleted file mode 100755 index 48ee9c21b..000000000 --- a/test_regress/t/t_opt_table_sparse_output_split.pl +++ /dev/null @@ -1,46 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_opt_table_sparse.v"); -golden_filename("t/t_opt_table_sparse.out"); - -compile( - verilator_flags2 => ["--stats", "--output-split 1"], - ); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, Tables created\s+(\d+)/, 1); - file_grep($Self->{stats}, qr/ConstPool, Tables emitted\s+(\d+)/, 2); -} - -# Splitting should set VM_PARALLEL_BUILDS to 1 by default -file_grep("$Self->{obj_dir}/$Self->{vm_prefix}_classes.mk", qr/VM_PARALLEL_BUILDS\s*=\s*1/); - -check_splits(2); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; - -sub check_splits { - my $expected = shift; - my $n; - foreach my $file (glob("$Self->{obj_dir}/*.cpp")) { - if ($file =~ /__ConstPool_/) { - $n += 1; - } - } - $n == $expected or error("__ConstPool*.cpp not split: $n"); -} diff --git a/test_regress/t/t_opt_table_sparse_output_split.py b/test_regress/t/t_opt_table_sparse_output_split.py new file mode 100755 index 000000000..bc87cb9fc --- /dev/null +++ b/test_regress/t/t_opt_table_sparse_output_split.py @@ -0,0 +1,39 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_opt_table_sparse.v" +test.golden_filename = "t/t_opt_table_sparse.out" + + +def check_splits(expected): + n = 0 + for filename in test.glob_some(test.obj_dir + "/*.cpp"): + if re.search(r'__ConstPool_', filename): + n += 1 + if n != expected: + test.error("__ConstPool*.cpp not split: " + str(n)) + + +test.compile(verilator_flags2=["--stats", "--output-split 1"]) + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, Tables created\s+(\d+)', 1) + test.file_grep(test.stats, r'ConstPool, Tables emitted\s+(\d+)', 2) + +# Splitting should set VM_PARALLEL_BUILDS to 1 by default +test.file_grep(test.obj_dir + "/" + test.vm_prefix + "_classes.mk", r'VM_PARALLEL_BUILDS\s*=\s*1') + +check_splits(2) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_opt_table_string.pl b/test_regress/t/t_opt_table_string.pl deleted file mode 100755 index 6a3f89ba3..000000000 --- a/test_regress/t/t_opt_table_string.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, Tables created\s+(\d+)/, 1); - file_grep($Self->{stats}, qr/ConstPool, Tables emitted\s+(\d+)/, 1); -} - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_opt_table_string.py b/test_regress/t/t_opt_table_string.py new file mode 100755 index 000000000..912dd4cf8 --- /dev/null +++ b/test_regress/t/t_opt_table_string.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats"]) + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, Tables created\s+(\d+)', 1) + test.file_grep(test.stats, r'ConstPool, Tables emitted\s+(\d+)', 1) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_opt_table_struct.pl b/test_regress/t/t_opt_table_struct.pl deleted file mode 100755 index 6a3f89ba3..000000000 --- a/test_regress/t/t_opt_table_struct.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, Tables created\s+(\d+)/, 1); - file_grep($Self->{stats}, qr/ConstPool, Tables emitted\s+(\d+)/, 1); -} - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_opt_table_struct.py b/test_regress/t/t_opt_table_struct.py new file mode 100755 index 000000000..912dd4cf8 --- /dev/null +++ b/test_regress/t/t_opt_table_struct.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats"]) + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, Tables created\s+(\d+)', 1) + test.file_grep(test.stats, r'ConstPool, Tables emitted\s+(\d+)', 1) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_optm_if_array.pl b/test_regress/t/t_optm_if_array.pl deleted file mode 100755 index c5e92b8a9..000000000 --- a/test_regress/t/t_optm_if_array.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -for my $file (glob_all("$Self->{obj_dir}/$Self->{vm_prefix}___024root*.cpp")) { - file_grep_not($file, qr/rstn_r/); -} - -ok(1); -1; diff --git a/test_regress/t/t_optm_if_array.py b/test_regress/t/t_optm_if_array.py new file mode 100755 index 000000000..0739b468a --- /dev/null +++ b/test_regress/t/t_optm_if_array.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +for filename in test.glob_some(test.obj_dir + "/" + test.vm_prefix + "___024root*.cpp"): + test.file_grep_not(filename, r'rstn_r') + +test.passes() diff --git a/test_regress/t/t_optm_if_array.v b/test_regress/t/t_optm_if_array.v index 4ec2472cc..2004c58eb 100644 --- a/test_regress/t/t_optm_if_array.v +++ b/test_regress/t/t_optm_if_array.v @@ -21,7 +21,7 @@ module t (/*AUTOARG*/ reg [31:0] dinit [0:1]; wire [31:0] dinitout = dinit[0] | dinit[1]; - reg rstn_r; // .pl file checks that this signal gets optimized away + reg rstn_r; // .py file checks that this signal gets optimized away always @(posedge clk) begin rstn_r <= rstn; end diff --git a/test_regress/t/t_optm_redor.pl b/test_regress/t/t_optm_redor.pl deleted file mode 100755 index c5e92b8a9..000000000 --- a/test_regress/t/t_optm_redor.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -for my $file (glob_all("$Self->{obj_dir}/$Self->{vm_prefix}___024root*.cpp")) { - file_grep_not($file, qr/rstn_r/); -} - -ok(1); -1; diff --git a/test_regress/t/t_optm_redor.py b/test_regress/t/t_optm_redor.py new file mode 100755 index 000000000..0739b468a --- /dev/null +++ b/test_regress/t/t_optm_redor.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +for filename in test.glob_some(test.obj_dir + "/" + test.vm_prefix + "___024root*.cpp"): + test.file_grep_not(filename, r'rstn_r') + +test.passes() diff --git a/test_regress/t/t_order.pl b/test_regress/t/t_order.pl deleted file mode 100755 index 81ae162b3..000000000 --- a/test_regress/t/t_order.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -$Self->{main_time_multiplier} = 1e-8 / 1e-9; - -compile( - verilator_flags2 => ["--timescale 10ns/1ns --no-timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_order.py b/test_regress/t/t_order.py new file mode 100755 index 000000000..77acf6161 --- /dev/null +++ b/test_regress/t/t_order.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.main_time_multiplier = 1e-8 / 1e-9 + +test.compile(verilator_flags2=["--timescale 10ns/1ns --no-timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_order_2d.pl b/test_regress/t/t_order_2d.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_order_2d.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_order_2d.py b/test_regress/t/t_order_2d.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_order_2d.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_order_blkandnblk_bad.pl b/test_regress/t/t_order_blkandnblk_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_order_blkandnblk_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_order_blkandnblk_bad.py b/test_regress/t/t_order_blkandnblk_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_order_blkandnblk_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_order_blkloopinit_bad.pl b/test_regress/t/t_order_blkloopinit_bad.pl deleted file mode 100755 index e3fd94eb8..000000000 --- a/test_regress/t/t_order_blkloopinit_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--timing"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_order_blkloopinit_bad.py b/test_regress/t/t_order_blkloopinit_bad.py new file mode 100755 index 000000000..ae6f7e918 --- /dev/null +++ b/test_regress/t/t_order_blkloopinit_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--timing"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_order_clkinst.pl b/test_regress/t/t_order_clkinst.pl deleted file mode 100755 index d9e27e016..000000000 --- a/test_regress/t/t_order_clkinst.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -# On Verilator, we expect this to pass. -# -# TBD: Will event-based simulators match Verilator's behavior -# closely enough to pass the same test? -# If not -- probably we should switch this to be vlt-only. - -compile(verilator_flags2 => ["--trace"]); - -execute(); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_order_clkinst.py b/test_regress/t/t_order_clkinst.py new file mode 100755 index 000000000..7b88a42a2 --- /dev/null +++ b/test_regress/t/t_order_clkinst.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +# On Verilator, we expect this to pass. +# +# TBD: Will event-based simulators match Verilator's behavior +# closely enough to pass the same test? +# If not -- probably we should switch this to be vlt-only. + +test.compile(verilator_flags2=["--trace"]) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_order_comboclkloop.pl b/test_regress/t/t_order_comboclkloop.pl deleted file mode 100755 index 72847408e..000000000 --- a/test_regress/t/t_order_comboclkloop.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_order_comboclkloop.py b/test_regress/t/t_order_comboclkloop.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_order_comboclkloop.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_order_comboloop.pl b/test_regress/t/t_order_comboloop.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_order_comboloop.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_order_comboloop.py b/test_regress/t/t_order_comboloop.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_order_comboloop.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_order_doubleloop.pl b/test_regress/t/t_order_doubleloop.pl deleted file mode 100755 index 72847408e..000000000 --- a/test_regress/t/t_order_doubleloop.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_order_doubleloop.py b/test_regress/t/t_order_doubleloop.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_order_doubleloop.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_order_dpi_export_1.pl b/test_regress/t/t_order_dpi_export_1.pl deleted file mode 100755 index bea108c13..000000000 --- a/test_regress/t/t_order_dpi_export_1.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe", "$Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_order_dpi_export_1.py b/test_regress/t/t_order_dpi_export_1.py new file mode 100755 index 000000000..273ccc85c --- /dev/null +++ b/test_regress/t/t_order_dpi_export_1.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_order_dpi_export_2.pl b/test_regress/t/t_order_dpi_export_2.pl deleted file mode 100755 index bea108c13..000000000 --- a/test_regress/t/t_order_dpi_export_2.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe", "$Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_order_dpi_export_2.py b/test_regress/t/t_order_dpi_export_2.py new file mode 100755 index 000000000..273ccc85c --- /dev/null +++ b/test_regress/t/t_order_dpi_export_2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_order_dpi_export_3.pl b/test_regress/t/t_order_dpi_export_3.pl deleted file mode 100755 index bea108c13..000000000 --- a/test_regress/t/t_order_dpi_export_3.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe", "$Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_order_dpi_export_3.py b/test_regress/t/t_order_dpi_export_3.py new file mode 100755 index 000000000..273ccc85c --- /dev/null +++ b/test_regress/t/t_order_dpi_export_3.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_order_dpi_export_4.pl b/test_regress/t/t_order_dpi_export_4.pl deleted file mode 100755 index bea108c13..000000000 --- a/test_regress/t/t_order_dpi_export_4.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe", "$Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_order_dpi_export_4.py b/test_regress/t/t_order_dpi_export_4.py new file mode 100755 index 000000000..273ccc85c --- /dev/null +++ b/test_regress/t/t_order_dpi_export_4.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_order_dpi_export_5.pl b/test_regress/t/t_order_dpi_export_5.pl deleted file mode 100755 index bea108c13..000000000 --- a/test_regress/t/t_order_dpi_export_5.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe", "$Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_order_dpi_export_5.py b/test_regress/t/t_order_dpi_export_5.py new file mode 100755 index 000000000..273ccc85c --- /dev/null +++ b/test_regress/t/t_order_dpi_export_5.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_order_dpi_export_6.pl b/test_regress/t/t_order_dpi_export_6.pl deleted file mode 100755 index bea108c13..000000000 --- a/test_regress/t/t_order_dpi_export_6.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe", "$Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_order_dpi_export_6.py b/test_regress/t/t_order_dpi_export_6.py new file mode 100755 index 000000000..273ccc85c --- /dev/null +++ b/test_regress/t/t_order_dpi_export_6.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_order_dpi_export_7.pl b/test_regress/t/t_order_dpi_export_7.pl deleted file mode 100755 index bea108c13..000000000 --- a/test_regress/t/t_order_dpi_export_7.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe", "$Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_order_dpi_export_7.py b/test_regress/t/t_order_dpi_export_7.py new file mode 100755 index 000000000..273ccc85c --- /dev/null +++ b/test_regress/t/t_order_dpi_export_7.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_order_dpi_export_8.pl b/test_regress/t/t_order_dpi_export_8.pl deleted file mode 100755 index abdad8e8b..000000000 --- a/test_regress/t/t_order_dpi_export_8.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - verilator_flags2 => ["--exe", "$Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_order_dpi_export_8.py b/test_regress/t/t_order_dpi_export_8.py new file mode 100755 index 000000000..38f29b4e6 --- /dev/null +++ b/test_regress/t/t_order_dpi_export_8.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_order_first.pl b/test_regress/t/t_order_first.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_order_first.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_order_first.py b/test_regress/t/t_order_first.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_order_first.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_order_loop_bad.pl b/test_regress/t/t_order_loop_bad.pl deleted file mode 100755 index 90117b64b..000000000 --- a/test_regress/t/t_order_loop_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile(); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_order_loop_bad.py b/test_regress/t/t_order_loop_bad.py new file mode 100755 index 000000000..fc5a55e3f --- /dev/null +++ b/test_regress/t/t_order_loop_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_order_multialways.pl b/test_regress/t/t_order_multialways.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_order_multialways.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_order_multialways.py b/test_regress/t/t_order_multialways.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_order_multialways.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_order_multidriven.pl b/test_regress/t/t_order_multidriven.pl deleted file mode 100755 index 83e70cad5..000000000 --- a/test_regress/t/t_order_multidriven.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2013 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ["--trace --exe $Self->{t_dir}/t_order_multidriven.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_order_multidriven.py b/test_regress/t/t_order_multidriven.py new file mode 100755 index 000000000..ec6142999 --- /dev/null +++ b/test_regress/t/t_order_multidriven.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_top_shell=False, make_main=False, v_flags2=["--trace --exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_order_quad.pl b/test_regress/t/t_order_quad.pl deleted file mode 100755 index faffdbdec..000000000 --- a/test_regress/t/t_order_quad.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe", "$Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_order_quad.py b/test_regress/t/t_order_quad.py new file mode 100755 index 000000000..f37ad07c8 --- /dev/null +++ b/test_regress/t/t_order_quad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_order_timing.pl b/test_regress/t/t_order_timing.pl deleted file mode 100755 index aaf9a4692..000000000 --- a/test_regress/t/t_order_timing.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -$Self->{main_time_multiplier} = 1e-8 / 1e-9; - -top_filename("t/t_order.v"); - -compile( - timing_loop => 1, - verilator_flags2 => ["--timescale 10ns/1ns --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_order_timing.py b/test_regress/t/t_order_timing.py new file mode 100755 index 000000000..cee17e347 --- /dev/null +++ b/test_regress/t/t_order_timing.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_order.v" +test.main_time_multiplier = 1e-8 / 1e-9 + +test.compile(timing_loop=True, verilator_flags2=["--timescale 10ns/1ns --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_order_wireloop.pl b/test_regress/t/t_order_wireloop.pl deleted file mode 100755 index 41a50e716..000000000 --- a/test_regress/t/t_order_wireloop.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2005 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - fails => $Self->{vlt_all}, - # Used to be %Error: t/t_order_wireloop.v:\d+: Wire inputs its own output, creating circular logic .wire x=x. - # However we no longer gate optimize this - # Can't use expect_filename here as unstable output - expect => -'%Warning-UNOPTFLAT: t/t_order_wireloop.v:\d+:\d+: Signal unoptimizable: Circular combinational logic: \'bar\' -', - ); - -ok(1); -1; diff --git a/test_regress/t/t_order_wireloop.py b/test_regress/t/t_order_wireloop.py new file mode 100755 index 000000000..b89510f69 --- /dev/null +++ b/test_regress/t/t_order_wireloop.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + fails=test.vlt_all, + # Used to be %Error: t/t_order_wireloop.v:\d+: Wire inputs its own output, creating circular logic .wire x=x. + # However we no longer gate optimize this + # Can't use expect_filename here as unstable output + expect= + r"%Warning-UNOPTFLAT: t/t_order_wireloop.v:\d+:\d+: Signal unoptimizable: Circular combinational logic: \'bar\'" +) + +test.passes() diff --git a/test_regress/t/t_package.pl b/test_regress/t/t_package.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_package.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_package.py b/test_regress/t/t_package.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_package.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_package_abs.pl b/test_regress/t/t_package_abs.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_package_abs.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_package_abs.py b/test_regress/t/t_package_abs.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_package_abs.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_package_alone_bad.pl b/test_regress/t/t_package_alone_bad.pl deleted file mode 100755 index 27159da5b..000000000 --- a/test_regress/t/t_package_alone_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_package_alone_bad.py b/test_regress/t/t_package_alone_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_package_alone_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_package_ddecl.pl b/test_regress/t/t_package_ddecl.pl deleted file mode 100755 index cfd2608b3..000000000 --- a/test_regress/t/t_package_ddecl.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--binary --no-timing'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_package_ddecl.py b/test_regress/t/t_package_ddecl.py new file mode 100755 index 000000000..46560bc9c --- /dev/null +++ b/test_regress/t/t_package_ddecl.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--binary --no-timing']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_package_ddecl_timing.pl b/test_regress/t/t_package_ddecl_timing.pl deleted file mode 100755 index 04bf33739..000000000 --- a/test_regress/t/t_package_ddecl_timing.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_package_ddecl.v"); - -compile( - verilator_flags2 => ['--binary --timing'], - timing_loop => 1, - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_package_ddecl_timing.py b/test_regress/t/t_package_ddecl_timing.py new file mode 100755 index 000000000..092a05315 --- /dev/null +++ b/test_regress/t/t_package_ddecl_timing.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_package_ddecl.v" + +test.compile(verilator_flags2=['--binary --timing'], timing_loop=True) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_package_dimport.pl b/test_regress/t/t_package_dimport.pl deleted file mode 100755 index 1e8c14055..000000000 --- a/test_regress/t/t_package_dimport.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -# Compile only - -ok(1); -1; diff --git a/test_regress/t/t_package_dimport.py b/test_regress/t/t_package_dimport.py new file mode 100755 index 000000000..d474feea7 --- /dev/null +++ b/test_regress/t/t_package_dimport.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +# Compile only + +test.passes() diff --git a/test_regress/t/t_package_dot.pl b/test_regress/t/t_package_dot.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_package_dot.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_package_dot.py b/test_regress/t/t_package_dot.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_package_dot.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_package_dup_bad.pl b/test_regress/t/t_package_dup_bad.pl deleted file mode 100755 index c35c8bc93..000000000 --- a/test_regress/t/t_package_dup_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_package_dup_bad.py b/test_regress/t/t_package_dup_bad.py new file mode 100755 index 000000000..efe8cc01c --- /dev/null +++ b/test_regress/t/t_package_dup_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_package_enum.pl b/test_regress/t/t_package_enum.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_package_enum.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_package_enum.py b/test_regress/t/t_package_enum.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_package_enum.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_package_export.pl b/test_regress/t/t_package_export.pl deleted file mode 100755 index 10877144a..000000000 --- a/test_regress/t/t_package_export.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ['+define+T_PACKAGE_EXPORT',], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_package_export.py b/test_regress/t/t_package_export.py new file mode 100755 index 000000000..06f34925c --- /dev/null +++ b/test_regress/t/t_package_export.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=['+define+T_PACKAGE_EXPORT']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_package_export_bad.pl b/test_regress/t/t_package_export_bad.pl deleted file mode 100755 index e454e2252..000000000 --- a/test_regress/t/t_package_export_bad.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -top_filename("t/t_package_export.v"); - -lint( - v_flags2 => ['+define+T_PACKAGE_EXPORT_BAD',], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - - -ok(1); -1; diff --git a/test_regress/t/t_package_export_bad.py b/test_regress/t/t_package_export_bad.py new file mode 100755 index 000000000..593de1e5b --- /dev/null +++ b/test_regress/t/t_package_export_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_package_export.v" + +test.lint(v_flags2=['+define+T_PACKAGE_EXPORT_BAD'], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_package_local_bad.pl b/test_regress/t/t_package_local_bad.pl deleted file mode 100755 index 27159da5b..000000000 --- a/test_regress/t/t_package_local_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_package_local_bad.py b/test_regress/t/t_package_local_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_package_local_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_package_param.pl b/test_regress/t/t_package_param.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_package_param.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_package_param.py b/test_regress/t/t_package_param.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_package_param.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_package_struct.pl b/test_regress/t/t_package_struct.pl deleted file mode 100755 index d22fe4afb..000000000 --- a/test_regress/t/t_package_struct.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_package_struct.py b/test_regress/t/t_package_struct.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_package_struct.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_package_twodeep.pl b/test_regress/t/t_package_twodeep.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_package_twodeep.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_package_twodeep.py b/test_regress/t/t_package_twodeep.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_package_twodeep.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_package_verb.pl b/test_regress/t/t_package_verb.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_package_verb.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_package_verb.py b/test_regress/t/t_package_verb.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_package_verb.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_packed_concat_bad.pl b/test_regress/t/t_packed_concat_bad.pl deleted file mode 100755 index 27159da5b..000000000 --- a/test_regress/t/t_packed_concat_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_packed_concat_bad.py b/test_regress/t/t_packed_concat_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_packed_concat_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_param.pl b/test_regress/t/t_param.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_param.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param.py b/test_regress/t/t_param.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_array.pl b/test_regress/t/t_param_array.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_param_array.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_array.py b/test_regress/t/t_param_array.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_array.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_array2.pl b/test_regress/t/t_param_array2.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_param_array2.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_array2.py b/test_regress/t/t_param_array2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_array2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_array3.pl b/test_regress/t/t_param_array3.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_param_array3.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_array3.py b/test_regress/t/t_param_array3.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_array3.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_array4.pl b/test_regress/t/t_param_array4.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_param_array4.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_array4.py b/test_regress/t/t_param_array4.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_array4.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_array5.pl b/test_regress/t/t_param_array5.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_param_array5.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_array5.py b/test_regress/t/t_param_array5.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_array5.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_array6.pl b/test_regress/t/t_param_array6.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_param_array6.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_array6.py b/test_regress/t/t_param_array6.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_array6.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_array7.pl b/test_regress/t/t_param_array7.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_param_array7.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_array7.py b/test_regress/t/t_param_array7.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_array7.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_array8.pl b/test_regress/t/t_param_array8.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_param_array8.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_array8.py b/test_regress/t/t_param_array8.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_array8.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_avec.pl b/test_regress/t/t_param_avec.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_param_avec.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_avec.py b/test_regress/t/t_param_avec.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_avec.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_bit_sel.pl b/test_regress/t/t_param_bit_sel.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_param_bit_sel.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_bit_sel.py b/test_regress/t/t_param_bit_sel.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_bit_sel.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_bracket.pl b/test_regress/t/t_param_bracket.pl deleted file mode 100755 index 09b2ce4eb..000000000 --- a/test_regress/t/t_param_bracket.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_bracket.py b/test_regress/t/t_param_bracket.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_param_bracket.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_param_ceil.pl b/test_regress/t/t_param_ceil.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_param_ceil.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_ceil.py b/test_regress/t/t_param_ceil.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_ceil.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_chain.pl b/test_regress/t/t_param_chain.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_param_chain.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_chain.py b/test_regress/t/t_param_chain.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_chain.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_circ_bad.pl b/test_regress/t/t_param_circ_bad.pl deleted file mode 100755 index a82cf66cb..000000000 --- a/test_regress/t/t_param_circ_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_circ_bad.py b/test_regress/t/t_param_circ_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_param_circ_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_param_concat.pl b/test_regress/t/t_param_concat.pl deleted file mode 100755 index 1eac7a827..000000000 --- a/test_regress/t/t_param_concat.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--Wno-WIDTHCONCAT"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_concat.py b/test_regress/t/t_param_concat.py new file mode 100755 index 000000000..8ecb93fe4 --- /dev/null +++ b/test_regress/t/t_param_concat.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--Wno-WIDTHCONCAT"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_concat_bad.pl b/test_regress/t/t_param_concat_bad.pl deleted file mode 100755 index 33177b739..000000000 --- a/test_regress/t/t_param_concat_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -top_filename("t/t_param_concat.v"); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_concat_bad.py b/test_regress/t/t_param_concat_bad.py new file mode 100755 index 000000000..65a84a628 --- /dev/null +++ b/test_regress/t/t_param_concat_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_param_concat.v" + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_param_const_part.pl b/test_regress/t/t_param_const_part.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_param_const_part.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_const_part.py b/test_regress/t/t_param_const_part.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_const_part.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_ddeep_width.pl b/test_regress/t/t_param_ddeep_width.pl deleted file mode 100755 index 13c6e2b71..000000000 --- a/test_regress/t/t_param_ddeep_width.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_param_ddeep_width.py b/test_regress/t/t_param_ddeep_width.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_param_ddeep_width.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_param_default.pl b/test_regress/t/t_param_default.pl deleted file mode 100755 index cb14ffd4a..000000000 --- a/test_regress/t/t_param_default.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_default.py b/test_regress/t/t_param_default.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_default.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_default_bad.pl b/test_regress/t/t_param_default_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_param_default_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_default_bad.py b/test_regress/t/t_param_default_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_param_default_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_param_default_presv_bad.pl b/test_regress/t/t_param_default_presv_bad.pl deleted file mode 100755 index 7cc88a04c..000000000 --- a/test_regress/t/t_param_default_presv_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -top_filename("t/t_param_default_bad.v"); - -lint( - verilator_flags2 => ["--lint-only --language 1800-2005"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_default_presv_bad.py b/test_regress/t/t_param_default_presv_bad.py new file mode 100755 index 000000000..a99a63850 --- /dev/null +++ b/test_regress/t/t_param_default_presv_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_param_default_bad.v" + +test.lint(verilator_flags2=["--lint-only --language 1800-2005"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_param_first.pl b/test_regress/t/t_param_first.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_param_first.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_first.py b/test_regress/t/t_param_first.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_first.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_func.pl b/test_regress/t/t_param_func.pl deleted file mode 100755 index 552bd97db..000000000 --- a/test_regress/t/t_param_func.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_func.py b/test_regress/t/t_param_func.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_param_func.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_param_func2.pl b/test_regress/t/t_param_func2.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_param_func2.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_func2.py b/test_regress/t/t_param_func2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_func2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_if_blk.pl b/test_regress/t/t_param_if_blk.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_param_if_blk.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_if_blk.py b/test_regress/t/t_param_if_blk.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_if_blk.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_implicit_local_bad.pl b/test_regress/t/t_param_implicit_local_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_param_implicit_local_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_implicit_local_bad.py b/test_regress/t/t_param_implicit_local_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_param_implicit_local_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_param_in_func.pl b/test_regress/t/t_param_in_func.pl deleted file mode 100755 index 3d3e9f795..000000000 --- a/test_regress/t/t_param_in_func.pl +++ /dev/null @@ -1,33 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -execute(); - -# The parameter array should have been put in the constant pool -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/ConstPool, Tables emitted\s+(\d+)/, 3); -} - -# Shouldn't have any references to the parameter array -foreach my $file ( - glob_all("$Self->{obj_dir}/$Self->{vm_prefix}*.h"), - glob_all("$Self->{obj_dir}/$Self->{vm_prefix}*.cpp") - ) { - file_grep_not($file, qr/digits/); -} - -ok(1); -1; diff --git a/test_regress/t/t_param_in_func.py b/test_regress/t/t_param_in_func.py new file mode 100755 index 000000000..e636de991 --- /dev/null +++ b/test_regress/t/t_param_in_func.py @@ -0,0 +1,27 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats"]) + +test.execute() + +# The parameter array should have been put in the constant pool +if test.vlt_all: + test.file_grep(test.stats, r'ConstPool, Tables emitted\s+(\d+)', 3) + +# Shouldn't have any references to the parameter array +for filename in (test.glob_some(test.obj_dir + "/" + test.vm_prefix + "*.h") + + test.glob_some(test.obj_dir + "/" + test.vm_prefix + "*.cpp")): + test.file_grep_not(filename, r'digits') + +test.passes() diff --git a/test_regress/t/t_param_in_func_noinline.pl b/test_regress/t/t_param_in_func_noinline.pl deleted file mode 100755 index 31ad69d3c..000000000 --- a/test_regress/t/t_param_in_func_noinline.pl +++ /dev/null @@ -1,35 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_param_in_func.v"); - -compile( - verilator_flags2 => ["--stats", "+define+NO_INLINE=1"], - ); - -execute(); - -# The parameter array should have been put in the constant pool -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/ConstPool, Tables emitted\s+(\d+)/, 3); -} - -# Shouldn't have any references to the parameter array -foreach my $file ( - glob_all("$Self->{obj_dir}/$Self->{vm_prefix}*.h"), - glob_all("$Self->{obj_dir}/$Self->{vm_prefix}*.cpp") - ) { - file_grep_not($file, qr/digits/); -} - -ok(1); -1; diff --git a/test_regress/t/t_param_in_func_noinline.py b/test_regress/t/t_param_in_func_noinline.py new file mode 100755 index 000000000..6fe5459f1 --- /dev/null +++ b/test_regress/t/t_param_in_func_noinline.py @@ -0,0 +1,28 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_param_in_func.v" + +test.compile(verilator_flags2=["--stats", "+define+NO_INLINE=1"]) + +test.execute() + +# The parameter array should have been put in the constant pool +if test.vlt_all: + test.file_grep(test.stats, r'ConstPool, Tables emitted\s+(\d+)', 3) + +# Shouldn't have any references to the parameter array +for filename in (test.glob_some(test.obj_dir + "/" + test.vm_prefix + "*.h") + + test.glob_some(test.obj_dir + "/" + test.vm_prefix + "*.cpp")): + test.file_grep_not(filename, r'digits') + +test.passes() diff --git a/test_regress/t/t_param_local.pl b/test_regress/t/t_param_local.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_param_local.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_local.py b/test_regress/t/t_param_local.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_local.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_long.pl b/test_regress/t/t_param_long.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_param_long.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_long.py b/test_regress/t/t_param_long.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_long.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_mem_attr.pl b/test_regress/t/t_param_mem_attr.pl deleted file mode 100755 index 184ceb13d..000000000 --- a/test_regress/t/t_param_mem_attr.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -# Compile only test. -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_mem_attr.py b/test_regress/t/t_param_mem_attr.py new file mode 100755 index 000000000..84ad9365e --- /dev/null +++ b/test_regress/t/t_param_mem_attr.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +# Compile only test. +test.compile() + +test.passes() diff --git a/test_regress/t/t_param_mintypmax.pl b/test_regress/t/t_param_mintypmax.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_param_mintypmax.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_mintypmax.py b/test_regress/t/t_param_mintypmax.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_mintypmax.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_module.pl b/test_regress/t/t_param_module.pl deleted file mode 100755 index ff81d20cd..000000000 --- a/test_regress/t/t_param_module.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -# Compile only test -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_module.py b/test_regress/t/t_param_module.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_module.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_named.pl b/test_regress/t/t_param_named.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_param_named.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_named.py b/test_regress/t/t_param_named.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_named.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_named_2.pl b/test_regress/t/t_param_named_2.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_param_named_2.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_named_2.py b/test_regress/t/t_param_named_2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_named_2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_no_parentheses.pl b/test_regress/t/t_param_no_parentheses.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_param_no_parentheses.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_no_parentheses.py b/test_regress/t/t_param_no_parentheses.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_no_parentheses.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_noval_bad.pl b/test_regress/t/t_param_noval_bad.pl deleted file mode 100755 index a82cf66cb..000000000 --- a/test_regress/t/t_param_noval_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_noval_bad.py b/test_regress/t/t_param_noval_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_param_noval_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_param_package.pl b/test_regress/t/t_param_package.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_param_package.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_package.py b/test_regress/t/t_param_package.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_package.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_passed_to_port.pl b/test_regress/t/t_param_passed_to_port.pl deleted file mode 100755 index 176f35697..000000000 --- a/test_regress/t/t_param_passed_to_port.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile(); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_passed_to_port.py b/test_regress/t/t_param_passed_to_port.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_passed_to_port.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_pattern.pl b/test_regress/t/t_param_pattern.pl deleted file mode 100755 index 1a59dd30b..000000000 --- a/test_regress/t/t_param_pattern.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--dump-tree'] - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_pattern.py b/test_regress/t/t_param_pattern.py new file mode 100755 index 000000000..835a031c1 --- /dev/null +++ b/test_regress/t/t_param_pattern.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--dump-tree']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_public.pl b/test_regress/t/t_param_public.pl deleted file mode 100755 index d47a09882..000000000 --- a/test_regress/t/t_param_public.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if ($Self->{vlt_all}) { - compile( - verilator_flags2 => ["-GTOP_PARAM=30 --exe $Self->{t_dir}/$Self->{name}.cpp"], - make_top_shell => 0, - make_main => 0, - ); -} else { - compile( - ); -} - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_public.py b/test_regress/t/t_param_public.py new file mode 100755 index 000000000..a5d71a2d5 --- /dev/null +++ b/test_regress/t/t_param_public.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if test.vlt_all: + test.compile(verilator_flags2=["-GTOP_PARAM=30 --exe", test.pli_filename], + make_top_shell=False, + make_main=False) +else: + test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_real.pl b/test_regress/t/t_param_real.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_param_real.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_real.py b/test_regress/t/t_param_real.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_real.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_real2.pl b/test_regress/t/t_param_real2.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_param_real2.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_real2.py b/test_regress/t/t_param_real2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_real2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_real2_collision.pl b/test_regress/t/t_param_real2_collision.pl deleted file mode 100755 index d3343fb27..000000000 --- a/test_regress/t/t_param_real2_collision.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Todd Strader. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_param_real2.v"); - -compile( - verilator_flags2 => ["--debug-collision"] - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_real2_collision.py b/test_regress/t/t_param_real2_collision.py new file mode 100755 index 000000000..9d6a5295f --- /dev/null +++ b/test_regress/t/t_param_real2_collision.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_param_real2.v" + +test.compile(verilator_flags2=["--debug-collision"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_repl.pl b/test_regress/t/t_param_repl.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_param_repl.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_repl.py b/test_regress/t/t_param_repl.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_repl.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_scope_bad.pl b/test_regress/t/t_param_scope_bad.pl deleted file mode 100755 index 35d749208..000000000 --- a/test_regress/t/t_param_scope_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_scope_bad.py b/test_regress/t/t_param_scope_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_param_scope_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_param_seg.pl b/test_regress/t/t_param_seg.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_param_seg.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_seg.py b/test_regress/t/t_param_seg.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_seg.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_sel.pl b/test_regress/t/t_param_sel.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_param_sel.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_sel.py b/test_regress/t/t_param_sel.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_sel.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_sel_range.pl b/test_regress/t/t_param_sel_range.pl deleted file mode 100755 index 0a78f9749..000000000 --- a/test_regress/t/t_param_sel_range.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only -Wno-SELRANGE"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_sel_range.py b/test_regress/t/t_param_sel_range.py new file mode 100755 index 000000000..905b4884b --- /dev/null +++ b/test_regress/t/t_param_sel_range.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only -Wno-SELRANGE"]) + +test.passes() diff --git a/test_regress/t/t_param_sel_range_bad.pl b/test_regress/t/t_param_sel_range_bad.pl deleted file mode 100755 index d1780f53f..000000000 --- a/test_regress/t/t_param_sel_range_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -top_filename("t/t_param_sel_range.v"); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_sel_range_bad.py b/test_regress/t/t_param_sel_range_bad.py new file mode 100755 index 000000000..916df8696 --- /dev/null +++ b/test_regress/t/t_param_sel_range_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_param_sel_range.v" + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_param_shift.pl b/test_regress/t/t_param_shift.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_param_shift.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_shift.py b/test_regress/t/t_param_shift.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_shift.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_type.pl b/test_regress/t/t_param_type.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_param_type.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_type.py b/test_regress/t/t_param_type.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_type.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_type2.pl b/test_regress/t/t_param_type2.pl deleted file mode 100755 index 9b828f5f7..000000000 --- a/test_regress/t/t_param_type2.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -#execute( -# ); - -ok(1); -1; diff --git a/test_regress/t/t_param_type2.py b/test_regress/t/t_param_type2.py new file mode 100755 index 000000000..3aafd524c --- /dev/null +++ b/test_regress/t/t_param_type2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +#test.execute() + +test.passes() diff --git a/test_regress/t/t_param_type3.pl b/test_regress/t/t_param_type3.pl deleted file mode 100755 index 9b828f5f7..000000000 --- a/test_regress/t/t_param_type3.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -#execute( -# ); - -ok(1); -1; diff --git a/test_regress/t/t_param_type3.py b/test_regress/t/t_param_type3.py new file mode 100755 index 000000000..3aafd524c --- /dev/null +++ b/test_regress/t/t_param_type3.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +#test.execute() + +test.passes() diff --git a/test_regress/t/t_param_type4.pl b/test_regress/t/t_param_type4.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_param_type4.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_type4.py b/test_regress/t/t_param_type4.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_type4.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_type4_collision.pl b/test_regress/t/t_param_type4_collision.pl deleted file mode 100755 index d08668638..000000000 --- a/test_regress/t/t_param_type4_collision.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_param_type4.v"); - -compile( - verilator_flags2 => ["--debug-collision"] - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_type4_collision.py b/test_regress/t/t_param_type4_collision.py new file mode 100755 index 000000000..202e9dda9 --- /dev/null +++ b/test_regress/t/t_param_type4_collision.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_param_type4.v" + +test.compile(verilator_flags2=["--debug-collision"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_type5.pl b/test_regress/t/t_param_type5.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_param_type5.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_type5.py b/test_regress/t/t_param_type5.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_type5.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_type_bad.pl b/test_regress/t/t_param_type_bad.pl deleted file mode 100755 index 7e61cd843..000000000 --- a/test_regress/t/t_param_type_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - # Bug1575 required trace to crash - verilator_flags2 => ["--trace"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_type_bad.py b/test_regress/t/t_param_type_bad.py new file mode 100755 index 000000000..13aced9dc --- /dev/null +++ b/test_regress/t/t_param_type_bad.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint( + # Bug1575 required trace to crash + verilator_flags2=["--trace"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_param_type_bad2.pl b/test_regress/t/t_param_type_bad2.pl deleted file mode 100755 index 9151f32e0..000000000 --- a/test_regress/t/t_param_type_bad2.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - # Bug1575 required trace to crash - verilator_flags2 => ["--trace --cc"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_type_bad2.py b/test_regress/t/t_param_type_bad2.py new file mode 100755 index 000000000..dd2d92256 --- /dev/null +++ b/test_regress/t/t_param_type_bad2.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint( + # Bug1575 required trace to crash + verilator_flags2=["--trace --cc"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_param_type_bit.pl b/test_regress/t/t_param_type_bit.pl deleted file mode 100755 index 552bd97db..000000000 --- a/test_regress/t/t_param_type_bit.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_type_bit.py b/test_regress/t/t_param_type_bit.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_param_type_bit.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_param_type_cmp.pl b/test_regress/t/t_param_type_cmp.pl deleted file mode 100755 index d2f1bb598..000000000 --- a/test_regress/t/t_param_type_cmp.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--binary'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_type_cmp.py b/test_regress/t/t_param_type_cmp.py new file mode 100755 index 000000000..671072f97 --- /dev/null +++ b/test_regress/t/t_param_type_cmp.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--binary']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_type_collision.pl b/test_regress/t/t_param_type_collision.pl deleted file mode 100755 index 5964adca6..000000000 --- a/test_regress/t/t_param_type_collision.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_param_type.v"); - -compile( - verilator_flags2 => ["--debug-collision"] - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_type_collision.py b/test_regress/t/t_param_type_collision.py new file mode 100755 index 000000000..9cc944889 --- /dev/null +++ b/test_regress/t/t_param_type_collision.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_param_type.v" + +test.compile(verilator_flags2=["--debug-collision"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_type_fwd.pl b/test_regress/t/t_param_type_fwd.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_param_type_fwd.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_type_fwd.py b/test_regress/t/t_param_type_fwd.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_param_type_fwd.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_param_unreachable.pl b/test_regress/t/t_param_unreachable.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_param_unreachable.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_unreachable.py b/test_regress/t/t_param_unreachable.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_unreachable.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_up_bad.pl b/test_regress/t/t_param_up_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_param_up_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_up_bad.py b/test_regress/t/t_param_up_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_param_up_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_param_value.pl b/test_regress/t/t_param_value.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_param_value.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_value.py b/test_regress/t/t_param_value.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_value.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_while.pl b/test_regress/t/t_param_while.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_param_while.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_while.py b/test_regress/t/t_param_while.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_while.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_wide_io.pl b/test_regress/t/t_param_wide_io.pl deleted file mode 100755 index bc18ea2b2..000000000 --- a/test_regress/t/t_param_wide_io.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -#execute(); - -ok(1); -1; diff --git a/test_regress/t/t_param_wide_io.py b/test_regress/t/t_param_wide_io.py new file mode 100755 index 000000000..3aafd524c --- /dev/null +++ b/test_regress/t/t_param_wide_io.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +#test.execute() + +test.passes() diff --git a/test_regress/t/t_param_width.pl b/test_regress/t/t_param_width.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_param_width.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_width.py b/test_regress/t/t_param_width.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_param_width.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_width_loc_bad.pl b/test_regress/t/t_param_width_loc_bad.pl deleted file mode 100755 index 27159da5b..000000000 --- a/test_regress/t/t_param_width_loc_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_width_loc_bad.py b/test_regress/t/t_param_width_loc_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_param_width_loc_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_param_x_unique.pl b/test_regress/t/t_param_x_unique.pl deleted file mode 100755 index 97d855c49..000000000 --- a/test_regress/t/t_param_x_unique.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--trace-fst --x-assign unique"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_param_x_unique.py b/test_regress/t/t_param_x_unique.py new file mode 100755 index 000000000..b60fcce63 --- /dev/null +++ b/test_regress/t/t_param_x_unique.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--trace-fst --x-assign unique"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_parse_delay.pl b/test_regress/t/t_parse_delay.pl deleted file mode 100755 index d399f16df..000000000 --- a/test_regress/t/t_parse_delay.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--binary --no-timing'], - ); - -ok(1); -1; diff --git a/test_regress/t/t_parse_delay.py b/test_regress/t/t_parse_delay.py new file mode 100755 index 000000000..3436d0b33 --- /dev/null +++ b/test_regress/t/t_parse_delay.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--binary --no-timing']) + +test.passes() diff --git a/test_regress/t/t_parse_delay_timing.pl b/test_regress/t/t_parse_delay_timing.pl deleted file mode 100755 index c5543a880..000000000 --- a/test_regress/t/t_parse_delay_timing.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_parse_delay.v"); - -compile( - verilator_flags2 => ['--binary --timing'], - ); - -ok(1); -1; diff --git a/test_regress/t/t_parse_delay_timing.py b/test_regress/t/t_parse_delay_timing.py new file mode 100755 index 000000000..8143451d7 --- /dev/null +++ b/test_regress/t/t_parse_delay_timing.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_parse_delay.v" + +test.compile(verilator_flags2=['--binary --timing']) + +test.passes() diff --git a/test_regress/t/t_past.pl b/test_regress/t/t_past.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_past.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_past.py b/test_regress/t/t_past.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_past.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_past_bad.pl b/test_regress/t/t_past_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_past_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_past_bad.py b/test_regress/t/t_past_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_past_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_past_funcs.pl b/test_regress/t/t_past_funcs.pl deleted file mode 100755 index c88a04ad2..000000000 --- a/test_regress/t/t_past_funcs.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--assert'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_past_funcs.py b/test_regress/t/t_past_funcs.py new file mode 100755 index 000000000..e55d87378 --- /dev/null +++ b/test_regress/t/t_past_funcs.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--assert']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_past_strobe.pl b/test_regress/t/t_past_strobe.pl deleted file mode 100755 index d22fe4afb..000000000 --- a/test_regress/t/t_past_strobe.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_past_strobe.py b/test_regress/t/t_past_strobe.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_past_strobe.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_past_unsup.pl b/test_regress/t/t_past_unsup.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_past_unsup.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_past_unsup.py b/test_regress/t/t_past_unsup.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_past_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_pgo_profoutofdate_bad.pl b/test_regress/t/t_pgo_profoutofdate_bad.pl deleted file mode 100755 index 3e78104a6..000000000 --- a/test_regress/t/t_pgo_profoutofdate_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vltmt => 1); - -compile( - threads => 2, - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_pgo_profoutofdate_bad.py b/test_regress/t/t_pgo_profoutofdate_bad.py new file mode 100755 index 000000000..dcb5636b3 --- /dev/null +++ b/test_regress/t/t_pgo_profoutofdate_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vltmt') + +test.compile(threads=2, fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_pgo_threads.pl b/test_regress/t/t_pgo_threads.pl deleted file mode 100755 index 4605edb22..000000000 --- a/test_regress/t/t_pgo_threads.pl +++ /dev/null @@ -1,41 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vltmt => 1); - -# It doesn't really matter what test -top_filename("t/t_gen_alw.v"); - -compile( - v_flags2 => ["--prof-pgo"], - threads => 2 - ); - -execute( - all_run_flags => ["+verilator+prof+exec+start+0", - " +verilator+prof+exec+file+/dev/null", - " +verilator+prof+vlt+file+$Self->{obj_dir}/profile.vlt", - ], - ); - -file_grep("$Self->{obj_dir}/profile.vlt", qr/profile_data/); - -compile( - # Intentionally no --prof-pgo here to make sure profile data can be read in - # without it (that is: --prof-pgo has no effect on profile_data hash names) - v_flags2 => [" $Self->{obj_dir}/profile.vlt"], - threads => 2 - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_pgo_threads.py b/test_regress/t/t_pgo_threads.py new file mode 100755 index 000000000..9527e06d0 --- /dev/null +++ b/test_regress/t/t_pgo_threads.py @@ -0,0 +1,32 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vltmt') +test.top_filename = "t/t_gen_alw.v" # It doesn't really matter what test + +test.compile(v_flags2=["--prof-pgo"], threads=2) + +test.execute(all_run_flags=[ + "+verilator+prof+exec+start+0", + " +verilator+prof+exec+file+/dev/null", + " +verilator+prof+vlt+file+" + test.obj_dir + "/profile.vlt"]) # yapf:disable + +test.file_grep(test.obj_dir + "/profile.vlt", r'profile_data ') + +test.compile( + # Intentionally no --prof-pgo here to make sure profile data can be read in + # without it (that is: --prof-pgo has no effect on profile_data hash names) + v_flags2=[" " + test.obj_dir + "/profile.vlt"], + threads=2) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_pipe_exit_bad.pl b/test_regress/t/t_pipe_exit_bad.pl deleted file mode 100755 index 8f2cbbab7..000000000 --- a/test_regress/t/t_pipe_exit_bad.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010-2011 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_pipe_filter.v"); - -lint( - verilator_flags2 => ['-E --pipe-filter \'python3 t/t_pipe_exit_bad_pf.pf\' '], - stdout_filename => $stdout_filename, - fails => 1, - expect => -'%Error: t_pipe_exit_bad_pf.pf: Intentional bad exit status....*', - ); -ok(1); - -1; diff --git a/test_regress/t/t_pipe_exit_bad.py b/test_regress/t/t_pipe_exit_bad.py new file mode 100755 index 000000000..db106b66d --- /dev/null +++ b/test_regress/t/t_pipe_exit_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_pipe_filter.v" + +test.lint(verilator_flags2=['-E --pipe-filter \'python3 t/t_pipe_exit_bad_pf.pf\' '], + fails=True, + expect=r'%Error: t_pipe_exit_bad_pf.pf: Intentional bad exit status....*') + +test.passes() diff --git a/test_regress/t/t_pipe_filter.pl b/test_regress/t/t_pipe_filter.pl deleted file mode 100755 index 0e41c9854..000000000 --- a/test_regress/t/t_pipe_filter.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010-2011 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $stdout_filename = "$Self->{obj_dir}/$Self->{name}__test.vpp"; - -compile( - verilator_flags2 => ['-E --pipe-filter \'python3 t/t_pipe_filter_pf.pf\' '], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - stdout_filename => $stdout_filename, - ); - -files_identical($stdout_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_pipe_filter.py b/test_regress/t/t_pipe_filter.py new file mode 100755 index 000000000..0ca83d0d1 --- /dev/null +++ b/test_regress/t/t_pipe_filter.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +stdout_filename = os.path.join(test.obj_dir, test.name + "__test.vpp") + +test.compile(verilator_flags2=['-E --pipe-filter \'python3 t/t_pipe_filter_pf.pf\' '], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False, + stdout_filename=stdout_filename) + +test.files_identical(stdout_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_pkg_identifier_bad.pl b/test_regress/t/t_pkg_identifier_bad.pl deleted file mode 100755 index 376c2d2ee..000000000 --- a/test_regress/t/t_pkg_identifier_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_pkg_identifier_bad.py b/test_regress/t/t_pkg_identifier_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_pkg_identifier_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_pkg_using_dollar_unit_items.pl b/test_regress/t/t_pkg_using_dollar_unit_items.pl deleted file mode 100755 index db100371d..000000000 --- a/test_regress/t/t_pkg_using_dollar_unit_items.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile(); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_pkg_using_dollar_unit_items.py b/test_regress/t/t_pkg_using_dollar_unit_items.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_pkg_using_dollar_unit_items.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_pli_bad.pl b/test_regress/t/t_pli_bad.pl deleted file mode 100755 index 828e0df38..000000000 --- a/test_regress/t/t_pli_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_pli_bad.py b/test_regress/t/t_pli_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_pli_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_pli_bbox.pl b/test_regress/t/t_pli_bbox.pl deleted file mode 100755 index b30ede91e..000000000 --- a/test_regress/t/t_pli_bbox.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_pli_bad.v"); - -lint( - verilator_flags2 => ["--bbox-sys"], - ); - -ok(1); - -1; diff --git a/test_regress/t/t_pli_bbox.py b/test_regress/t/t_pli_bbox.py new file mode 100755 index 000000000..6962d0be1 --- /dev/null +++ b/test_regress/t/t_pli_bbox.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_pli_bad.v" + +test.lint(verilator_flags2=["--bbox-sys"]) + +test.passes() diff --git a/test_regress/t/t_pp_circ_subst_bad.pl b/test_regress/t/t_pp_circ_subst_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_pp_circ_subst_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_pp_circ_subst_bad.py b/test_regress/t/t_pp_circ_subst_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_pp_circ_subst_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_pp_circdef_bad.pl b/test_regress/t/t_pp_circdef_bad.pl deleted file mode 100755 index 98a317817..000000000 --- a/test_regress/t/t_pp_circdef_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - # EOF result varies with Bison version, so can't use .out - expect => qr/define or other nested inclusion/, - ); - -ok(1); -1; diff --git a/test_regress/t/t_pp_circdef_bad.py b/test_regress/t/t_pp_circdef_bad.py new file mode 100755 index 000000000..c7236cb6f --- /dev/null +++ b/test_regress/t/t_pp_circdef_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint( + fails=True, + # EOF result varies with Bison version, so can't use .out + expect=r'define or other nested inclusion') + +test.passes() diff --git a/test_regress/t/t_pp_defkwd_bad.pl b/test_regress/t/t_pp_defkwd_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_pp_defkwd_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_pp_defkwd_bad.py b/test_regress/t/t_pp_defkwd_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_pp_defkwd_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_pp_defnettype_bad.pl b/test_regress/t/t_pp_defnettype_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_pp_defnettype_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_pp_defnettype_bad.py b/test_regress/t/t_pp_defnettype_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_pp_defnettype_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_pp_defparen_bad.pl b/test_regress/t/t_pp_defparen_bad.pl deleted file mode 100755 index 9de6b85ee..000000000 --- a/test_regress/t/t_pp_defparen_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["-Wpedantic"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_pp_defparen_bad.py b/test_regress/t/t_pp_defparen_bad.py new file mode 100755 index 000000000..4cc015636 --- /dev/null +++ b/test_regress/t/t_pp_defparen_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["-Wpedantic"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_pp_display.pl b/test_regress/t/t_pp_display.pl deleted file mode 100755 index e988c6264..000000000 --- a/test_regress/t/t_pp_display.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_pp_display.py b/test_regress/t/t_pp_display.py new file mode 100755 index 000000000..97abb660e --- /dev/null +++ b/test_regress/t/t_pp_display.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_pp_dupdef.pl b/test_regress/t/t_pp_dupdef.pl deleted file mode 100755 index 723508870..000000000 --- a/test_regress/t/t_pp_dupdef.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["-Wno-REDEFMACRO"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_pp_dupdef.py b/test_regress/t/t_pp_dupdef.py new file mode 100755 index 000000000..759a466d9 --- /dev/null +++ b/test_regress/t/t_pp_dupdef.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["-Wno-REDEFMACRO"]) + +test.passes() diff --git a/test_regress/t/t_pp_dupdef_bad.pl b/test_regress/t/t_pp_dupdef_bad.pl deleted file mode 100755 index b2d49e566..000000000 --- a/test_regress/t/t_pp_dupdef_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_pp_dupdef.v"); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_pp_dupdef_bad.py b/test_regress/t/t_pp_dupdef_bad.py new file mode 100755 index 000000000..e9153a9f4 --- /dev/null +++ b/test_regress/t/t_pp_dupdef_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_pp_dupdef.v" + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_pp_dupdef_pragma_bad.pl b/test_regress/t/t_pp_dupdef_pragma_bad.pl deleted file mode 100755 index b5861b2ab..000000000 --- a/test_regress/t/t_pp_dupdef_pragma_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_pp_dupdef_pragma_bad.py b/test_regress/t/t_pp_dupdef_pragma_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_pp_dupdef_pragma_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_pp_lib.pl b/test_regress/t/t_pp_lib.pl deleted file mode 100755 index 5fbd6a959..000000000 --- a/test_regress/t/t_pp_lib.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - v_flags2 => ['-v', 't/t_pp_lib_library.v'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_pp_lib.py b/test_regress/t/t_pp_lib.py new file mode 100755 index 000000000..1fc2440ba --- /dev/null +++ b/test_regress/t/t_pp_lib.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(v_flags2=['-v', 't/t_pp_lib_library.v']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_pp_line.pl b/test_regress/t/t_pp_line.pl deleted file mode 100755 index d1ed9a923..000000000 --- a/test_regress/t/t_pp_line.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_pp_line.py b/test_regress/t/t_pp_line.py new file mode 100755 index 000000000..ccec64024 --- /dev/null +++ b/test_regress/t/t_pp_line.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_pp_line_bad.pl b/test_regress/t/t_pp_line_bad.pl deleted file mode 100755 index 887b07b64..000000000 --- a/test_regress/t/t_pp_line_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ['-no-std'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_pp_line_bad.py b/test_regress/t/t_pp_line_bad.py new file mode 100755 index 000000000..2819d29cf --- /dev/null +++ b/test_regress/t/t_pp_line_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=['-no-std'], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_pp_misdef_bad.pl b/test_regress/t/t_pp_misdef_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_pp_misdef_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_pp_misdef_bad.py b/test_regress/t/t_pp_misdef_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_pp_misdef_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_pp_pragma_bad.pl b/test_regress/t/t_pp_pragma_bad.pl deleted file mode 100755 index 219eb9526..000000000 --- a/test_regress/t/t_pp_pragma_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["-E -Wpedantic"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_pp_pragma_bad.py b/test_regress/t/t_pp_pragma_bad.py new file mode 100755 index 000000000..f570493aa --- /dev/null +++ b/test_regress/t/t_pp_pragma_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["-E -Wpedantic"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_pp_pragmas.pl b/test_regress/t/t_pp_pragmas.pl deleted file mode 100755 index 9957dd7b9..000000000 --- a/test_regress/t/t_pp_pragmas.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_pp_pragmas.py b/test_regress/t/t_pp_pragmas.py new file mode 100755 index 000000000..fc5a55e3f --- /dev/null +++ b/test_regress/t/t_pp_pragmas.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_pp_recursedef_bad.pl b/test_regress/t/t_pp_recursedef_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_pp_recursedef_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_pp_recursedef_bad.py b/test_regress/t/t_pp_recursedef_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_pp_recursedef_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_pp_resetall_bad.pl b/test_regress/t/t_pp_resetall_bad.pl deleted file mode 100755 index bfb6f2bb1..000000000 --- a/test_regress/t/t_pp_resetall_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["-Wpedantic"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_pp_resetall_bad.py b/test_regress/t/t_pp_resetall_bad.py new file mode 100755 index 000000000..8df222dcf --- /dev/null +++ b/test_regress/t/t_pp_resetall_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["-Wpedantic"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_pp_underline_bad.pl b/test_regress/t/t_pp_underline_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_pp_underline_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_pp_underline_bad.py b/test_regress/t/t_pp_underline_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_pp_underline_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_premit_rw.pl b/test_regress/t/t_premit_rw.pl deleted file mode 100755 index f24a18e5a..000000000 --- a/test_regress/t/t_premit_rw.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -#execute( -# ); - -ok(1); -1; diff --git a/test_regress/t/t_premit_rw.py b/test_regress/t/t_premit_rw.py new file mode 100755 index 000000000..3aafd524c --- /dev/null +++ b/test_regress/t/t_premit_rw.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +#test.execute() + +test.passes() diff --git a/test_regress/t/t_preproc.pl b/test_regress/t/t_preproc.pl deleted file mode 100755 index 1a9daee70..000000000 --- a/test_regress/t/t_preproc.pl +++ /dev/null @@ -1,62 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $stdout_filename = "$Self->{obj_dir}/$Self->{name}__test.vpp"; - -compile( - verilator_flags2 => ['-DDEF_A0 -DPREDEF_COMMAND_LINE -E'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - stdout_filename => $stdout_filename, - ); - -preproc_check($Self->{top_filename}, $stdout_filename); -files_identical($stdout_filename, $Self->{golden_filename}); -ok(1); - -sub preproc_check { - my $filename1 = shift; - my $filename2 = shift; - - my @Line_Checks; - { # Read line comments. - my $fh = IO::File->new($filename1) or die "%Error: $! $filename1\n"; - while (defined(my $line = $fh->getline)) { - if ($line =~ /^Line_Preproc_Check/) { - push @Line_Checks, $.; - } - } - $fh->close; - } - { # See if output file agrees. - my $fh = IO::File->new($filename2) or die "%Error: $! $filename2\n"; - my $lineno = 0; - while (defined(my $line = $fh->getline)) { - $lineno++; - if ($line =~ /^\`line\s+(\d+)/) { - $lineno = $1 - 1; - } - if ($line =~ /^Line_Preproc_Check\s+(\d+)/) { - my $linecmt = $1; - my $check = shift @Line_Checks; - if (!$check) { error("$filename2:$.: Extra Line_Preproc_Check\n"); } - if ($linecmt != $check) { error("$filename2:$.: __LINE__ inserted $linecmt, exp=$check\n"); } - if ($lineno != $check) { error("$filename2:$.: __LINE__ on `line $lineno, exp=$check\n"); } - } - } - $fh->close; - } - if ($Line_Checks[0]) { error("$filename2: Missing a Line_Preproc_Check\n"); } -} - -1; diff --git a/test_regress/t/t_preproc.py b/test_regress/t/t_preproc.py new file mode 100755 index 000000000..8ccc75e7a --- /dev/null +++ b/test_regress/t/t_preproc.py @@ -0,0 +1,63 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import collections + +test.scenarios('vlt') + + +def preproc_check(filename1, filename2): + # Read line comments. + line_checks = collections.deque() + with open(filename1, 'r', encoding="latin-1", newline='\n') as fh: + lineno = 0 + for line in fh: + lineno += 1 + if re.match(r'^Line_Preproc_Check', line): + line_checks.append(lineno) + + # See if output file agrees. + with open(filename2, 'r', encoding="latin-1", newline='\n') as fh: + lineno = 0 + for line in fh: + lineno += 1 + m = re.match(r'^\`line\s+(\d+)', line) + if m: + lineno = int(m.group(1)) - 1 + m = re.match(r'^Line_Preproc_Check\s+(\d+)', line) + if m: + linecmt = m.group(1) + check = line_checks.popleft() + file2ln = filename2 + ":" + str(lineno) + if not check: + test.error(file2ln + ": Extra Line_Preproc_Check") + if str(linecmt) != str(check): + test.error(file2ln + ": __LINE__ inserted " + str(linecmt) + ", exp=" + + str(check)) + if str(lineno) != str(check): + test.error(file2ln + ": __LINE__ on `line " + str(lineno) + ", exp=" + + str(check)) + + if len(line_checks): + test.error(filename2 + ": Missing a Line_Preproc_Check") + + +stdout_filename = test.obj_dir + "/" + test.name + "__test.vpp" + +test.compile(verilator_flags2=['-DDEF_A0 -DPREDEF_COMMAND_LINE -E'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False, + stdout_filename=stdout_filename) + +preproc_check(test.top_filename, stdout_filename) +test.files_identical(stdout_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_cmtend_bad.pl b/test_regress/t/t_preproc_cmtend_bad.pl deleted file mode 100755 index 47d394e3b..000000000 --- a/test_regress/t/t_preproc_cmtend_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - verilator_flags2 => ['--no-std'], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_cmtend_bad.py b/test_regress/t/t_preproc_cmtend_bad.py new file mode 100755 index 000000000..889534217 --- /dev/null +++ b/test_regress/t/t_preproc_cmtend_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, verilator_flags2=['--no-std'], expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_comments.pl b/test_regress/t/t_preproc_comments.pl deleted file mode 100755 index 7aa405ee4..000000000 --- a/test_regress/t/t_preproc_comments.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_preproc.v"); - -my $stdout_filename = "$Self->{obj_dir}/$Self->{name}__test.vpp"; - -compile( - verilator_flags2 => ['-DDEF_A0 -DPREDEF_COMMAND_LINE -E --pp-comments'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - stdout_filename => $stdout_filename, - ); - -files_identical($stdout_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_comments.py b/test_regress/t/t_preproc_comments.py new file mode 100755 index 000000000..87b6cbeb8 --- /dev/null +++ b/test_regress/t/t_preproc_comments.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_preproc.v" + +stdout_filename = os.path.join(test.obj_dir, test.name + "__test.vpp") + +test.compile(verilator_flags2=['-DDEF_A0 -DPREDEF_COMMAND_LINE -E --pp-comments'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False, + stdout_filename=stdout_filename) + +test.files_identical(stdout_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_debugi.pl b/test_regress/t/t_preproc_debugi.pl deleted file mode 100755 index 11755e0d7..000000000 --- a/test_regress/t/t_preproc_debugi.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -# Hit the debug statements in the preprocessor for internal coverage - -run(cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator", - "-E", - "t/t_preproc_debugi.v", - "--debug", - "--debugi-V3PreShell 10", - ], - tee => $Self->{verbose}, - logfile => "$Self->{obj_dir}/sim.log", - verilator_run => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_debugi.py b/test_regress/t/t_preproc_debugi.py new file mode 100755 index 000000000..a8df3f568 --- /dev/null +++ b/test_regress/t/t_preproc_debugi.py @@ -0,0 +1,27 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +# Hit the debug statements in the preprocessor for internal coverage + +test.run(cmd=[ + os.environ["VERILATOR_ROOT"] + "/bin/verilator", + "-E", + "t/t_preproc_debugi.v", + "--debug", + "--debugi-V3PreShell 10", +], + tee=test.verbose, + logfile=test.obj_dir + "/sim.log", + verilator_run=True) + +test.passes() diff --git a/test_regress/t/t_preproc_def09.pl b/test_regress/t/t_preproc_def09.pl deleted file mode 100755 index e0a41bb51..000000000 --- a/test_regress/t/t_preproc_def09.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $stdout_filename = "$Self->{obj_dir}/$Self->{name}__test.vpp"; - -compile( - verilator_flags2 => ['-E'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - stdout_filename => $stdout_filename, - ); - -files_identical($stdout_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_def09.py b/test_regress/t/t_preproc_def09.py new file mode 100755 index 000000000..fe9e90689 --- /dev/null +++ b/test_regress/t/t_preproc_def09.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +stdout_filename = os.path.join(test.obj_dir, test.name + "__test.vpp") + +test.compile(verilator_flags2=['-E'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False, + stdout_filename=stdout_filename) + +test.files_identical(stdout_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_defarg_bad.pl b/test_regress/t/t_preproc_defarg_bad.pl deleted file mode 100755 index aa47819e1..000000000 --- a/test_regress/t/t_preproc_defarg_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - verilator_flags2 => ["-Wno-context"], - # The .vh file has the error, not the .v file - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_defarg_bad.py b/test_regress/t/t_preproc_defarg_bad.py new file mode 100755 index 000000000..8e1a07120 --- /dev/null +++ b/test_regress/t/t_preproc_defarg_bad.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint( + fails=True, + verilator_flags2=["-Wno-context"], + # The .vh file has the error, not the .v file + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_defines.pl b/test_regress/t/t_preproc_defines.pl deleted file mode 100755 index c632aecf7..000000000 --- a/test_regress/t/t_preproc_defines.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_preproc.v"); - -my $stdout_filename = "$Self->{obj_dir}/$Self->{name}__test.vpp"; - -compile( - verilator_flags2 => ['-DDEF_A0 -DPREDEF_COMMAND_LINE -E --dump-defines'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - stdout_filename => $stdout_filename, - ); - -files_identical($stdout_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_defines.py b/test_regress/t/t_preproc_defines.py new file mode 100755 index 000000000..433946a97 --- /dev/null +++ b/test_regress/t/t_preproc_defines.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_preproc.v" + +stdout_filename = os.path.join(test.obj_dir, test.name + "__test.vpp") + +test.compile(verilator_flags2=['-DDEF_A0 -DPREDEF_COMMAND_LINE -E --dump-defines'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False, + stdout_filename=stdout_filename) + +test.files_identical(stdout_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_dos.pl b/test_regress/t/t_preproc_dos.pl deleted file mode 100755 index f43a54cd5..000000000 --- a/test_regress/t/t_preproc_dos.pl +++ /dev/null @@ -1,32 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2006-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("$Self->{obj_dir}/$Self->{name}.v"); -golden_filename("$Self->{obj_dir}/$Self->{name}.out"); - -# Rather then having to maintain a new .v and .out, add returns -# to all lines of the existing t_preproc test. - -{ - my $wholefile = file_contents("$Self->{t_dir}/t_preproc.v"); - $wholefile =~ s/\n/\r\n/og; - write_wholefile("$Self->{obj_dir}/$Self->{name}.v", $wholefile); -} -{ - my $wholefile = file_contents("$Self->{t_dir}/t_preproc.out"); - $wholefile =~ s!t/t_preproc.v!$Self->{obj_dir}/t_preproc_dos.v!og; # Fix `line's - write_wholefile($Self->{golden_filename}, $wholefile); -} - -do 't/t_preproc.pl'; - -1; diff --git a/test_regress/t/t_preproc_dos.py b/test_regress/t/t_preproc_dos.py new file mode 100755 index 000000000..ca72b6ab7 --- /dev/null +++ b/test_regress/t/t_preproc_dos.py @@ -0,0 +1,28 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import runpy + +test.scenarios('vlt') +test.top_filename = test.obj_dir + "/" + test.name + ".v" +test.golden_filename = test.obj_dir + "/" + test.name + ".out" + +# Rather then having to maintain a new .v and .out, add returns +# to all lines of the existing t_preproc test. + +wholefile = test.file_contents(test.t_dir + "/t_preproc.v") +wholefile = re.sub(r'\n', r'\r\n', wholefile) +test.write_wholefile(test.obj_dir + "/" + test.name + ".v", wholefile) + +wholefile = test.file_contents(test.t_dir + "/t_preproc.out") +wholefile = re.sub(r't/t_preproc.v', test.obj_dir + "/t_preproc_dos.v", wholefile) # Fix `line's +test.write_wholefile(test.golden_filename, wholefile) + +runpy.run_path('t/t_preproc.py', globals()) diff --git a/test_regress/t/t_preproc_elsif_bad.pl b/test_regress/t/t_preproc_elsif_bad.pl deleted file mode 100755 index cdeb5a8e1..000000000 --- a/test_regress/t/t_preproc_elsif_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - # The .vh file has the error, not the .v file - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_elsif_bad.py b/test_regress/t/t_preproc_elsif_bad.py new file mode 100755 index 000000000..b16466729 --- /dev/null +++ b/test_regress/t/t_preproc_elsif_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint( + fails=True, + # The .vh file has the error, not the .v file + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_eof1_bad.pl b/test_regress/t/t_preproc_eof1_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_preproc_eof1_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_eof1_bad.py b/test_regress/t/t_preproc_eof1_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_preproc_eof1_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_eof2_bad.pl b/test_regress/t/t_preproc_eof2_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_preproc_eof2_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_eof2_bad.py b/test_regress/t/t_preproc_eof2_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_preproc_eof2_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_eof3_bad.pl b/test_regress/t/t_preproc_eof3_bad.pl deleted file mode 100755 index 47d394e3b..000000000 --- a/test_regress/t/t_preproc_eof3_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - verilator_flags2 => ['--no-std'], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_eof3_bad.py b/test_regress/t/t_preproc_eof3_bad.py new file mode 100755 index 000000000..889534217 --- /dev/null +++ b/test_regress/t/t_preproc_eof3_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, verilator_flags2=['--no-std'], expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_eof4_bad.pl b/test_regress/t/t_preproc_eof4_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_preproc_eof4_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_eof4_bad.py b/test_regress/t/t_preproc_eof4_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_preproc_eof4_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_eof5_bad.pl b/test_regress/t/t_preproc_eof5_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_preproc_eof5_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_eof5_bad.py b/test_regress/t/t_preproc_eof5_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_preproc_eof5_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_eof6_bad.pl b/test_regress/t/t_preproc_eof6_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_preproc_eof6_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_eof6_bad.py b/test_regress/t/t_preproc_eof6_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_preproc_eof6_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_ifdef.pl b/test_regress/t/t_preproc_ifdef.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_preproc_ifdef.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_ifdef.py b/test_regress/t/t_preproc_ifdef.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_preproc_ifdef.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_preproc_ifexpr.pl b/test_regress/t/t_preproc_ifexpr.pl deleted file mode 100755 index 37bb50fe5..000000000 --- a/test_regress/t/t_preproc_ifexpr.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $stdout_filename = "$Self->{obj_dir}/$Self->{name}__test.vpp"; - -compile( - verilator_flags2 => ['-E -P'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - stdout_filename => $stdout_filename, - ); - -files_identical($stdout_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_ifexpr.py b/test_regress/t/t_preproc_ifexpr.py new file mode 100755 index 000000000..977858180 --- /dev/null +++ b/test_regress/t/t_preproc_ifexpr.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +stdout_filename = os.path.join(test.obj_dir, test.name + "__test.vpp") + +test.compile(verilator_flags2=['-E -P'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False, + stdout_filename=stdout_filename) + +test.files_identical(stdout_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_ifexpr_bad.pl b/test_regress/t/t_preproc_ifexpr_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_preproc_ifexpr_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_ifexpr_bad.py b/test_regress/t/t_preproc_ifexpr_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_preproc_ifexpr_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_inc_bad.pl b/test_regress/t/t_preproc_inc_bad.pl deleted file mode 100755 index cdeb5a8e1..000000000 --- a/test_regress/t/t_preproc_inc_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - # The .vh file has the error, not the .v file - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_inc_bad.py b/test_regress/t/t_preproc_inc_bad.py new file mode 100755 index 000000000..b16466729 --- /dev/null +++ b/test_regress/t/t_preproc_inc_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint( + fails=True, + # The .vh file has the error, not the .v file + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_inc_fn_bad.pl b/test_regress/t/t_preproc_inc_fn_bad.pl deleted file mode 100755 index cdeb5a8e1..000000000 --- a/test_regress/t/t_preproc_inc_fn_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - # The .vh file has the error, not the .v file - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_inc_fn_bad.py b/test_regress/t/t_preproc_inc_fn_bad.py new file mode 100755 index 000000000..b16466729 --- /dev/null +++ b/test_regress/t/t_preproc_inc_fn_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint( + fails=True, + # The .vh file has the error, not the .v file + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_inc_notfound_bad.pl b/test_regress/t/t_preproc_inc_notfound_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_preproc_inc_notfound_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_inc_notfound_bad.py b/test_regress/t/t_preproc_inc_notfound_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_preproc_inc_notfound_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_inc_recurse_bad.pl b/test_regress/t/t_preproc_inc_recurse_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_preproc_inc_recurse_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_inc_recurse_bad.py b/test_regress/t/t_preproc_inc_recurse_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_preproc_inc_recurse_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_kwd.pl b/test_regress/t/t_preproc_kwd.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_preproc_kwd.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_kwd.py b/test_regress/t/t_preproc_kwd.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_preproc_kwd.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_preproc_kwd_bad.pl b/test_regress/t/t_preproc_kwd_bad.pl deleted file mode 100755 index 47f9bc97a..000000000 --- a/test_regress/t/t_preproc_kwd_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - verilator_flags2 => ['--no-std'], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_kwd_bad.py b/test_regress/t/t_preproc_kwd_bad.py new file mode 100755 index 000000000..291d7509d --- /dev/null +++ b/test_regress/t/t_preproc_kwd_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, verilator_flags2=['--no-std'], expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_nodef_bad.pl b/test_regress/t/t_preproc_nodef_bad.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_preproc_nodef_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_nodef_bad.py b/test_regress/t/t_preproc_nodef_bad.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_preproc_nodef_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_noline.pl b/test_regress/t/t_preproc_noline.pl deleted file mode 100755 index 6ecbb7651..000000000 --- a/test_regress/t/t_preproc_noline.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $stdout_filename = "$Self->{obj_dir}/$Self->{name}__test.vpp"; - -top_filename("t/t_preproc_noline.v"); - -compile( - verilator_flags2 => ['-E -P'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - stdout_filename => $stdout_filename, - ); - -files_identical($stdout_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_noline.py b/test_regress/t/t_preproc_noline.py new file mode 100755 index 000000000..60dd75a8c --- /dev/null +++ b/test_regress/t/t_preproc_noline.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_preproc_noline.v" + +stdout_filename = os.path.join(test.obj_dir, test.name + "__test.vpp") + +test.compile(verilator_flags2=['-E -P'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False, + stdout_filename=stdout_filename) + +test.files_identical(stdout_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_persist.pl b/test_regress/t/t_preproc_persist.pl deleted file mode 100755 index 4f6ffcf30..000000000 --- a/test_regress/t/t_preproc_persist.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2017 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $stdout_filename = "$Self->{obj_dir}/$Self->{name}__test.vpp"; - -compile( - # Override default flags - v_flags => [''], - v_other_filenames => ["t_preproc_persist2.v"], - verilator_flags => ["-E -P +incdir+t -Mdir $Self->{obj_dir}", ], - verilator_flags2 => ['',], - verilator_flags3 => ['',], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - stdout_filename => $stdout_filename, - ); - -files_identical($stdout_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_persist.py b/test_regress/t/t_preproc_persist.py new file mode 100755 index 000000000..1fba47b6f --- /dev/null +++ b/test_regress/t/t_preproc_persist.py @@ -0,0 +1,30 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +stdout_filename = os.path.join(test.obj_dir, test.name + "__test.vpp") + +test.compile( + # Override default flags + v_flags=[''], + v_other_filenames=["t_preproc_persist2.v"], + verilator_flags=["-E -P +incdir+t -Mdir", test.obj_dir], + verilator_flags2=[''], + verilator_flags3=[''], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False, + stdout_filename=stdout_filename) + +test.files_identical(stdout_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_preproczero_bad.pl b/test_regress/t/t_preproc_preproczero_bad.pl deleted file mode 100755 index abcaaca95..000000000 --- a/test_regress/t/t_preproc_preproczero_bad.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $stdout_filename = "$Self->{obj_dir}/$Self->{name}__test.vpp"; - -compile( - verilator_flags2 => ['-E -P'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - stdout_filename => $stdout_filename, - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_preproczero_bad.py b/test_regress/t/t_preproc_preproczero_bad.py new file mode 100755 index 000000000..b213d98c3 --- /dev/null +++ b/test_regress/t/t_preproc_preproczero_bad.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +stdout_filename = os.path.join(test.obj_dir, test.name + "__test.vpp") + +test.compile(verilator_flags2=['-E -P'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False, + stdout_filename=stdout_filename, + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_str_undef.pl b/test_regress/t/t_preproc_str_undef.pl deleted file mode 100755 index ba6e69d67..000000000 --- a/test_regress/t/t_preproc_str_undef.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_str_undef.py b/test_regress/t/t_preproc_str_undef.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_preproc_str_undef.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_stringend_bad.pl b/test_regress/t/t_preproc_stringend_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_preproc_stringend_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_stringend_bad.py b/test_regress/t/t_preproc_stringend_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_preproc_stringend_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_ttempty.pl b/test_regress/t/t_preproc_ttempty.pl deleted file mode 100755 index 411276940..000000000 --- a/test_regress/t/t_preproc_ttempty.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2017 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $stdout_filename = "$Self->{obj_dir}/$Self->{name}__test.vpp"; - -compile( - # Override default flags - v_flags => [''], - verilator_flags => ["-E -P +incdir+t -Mdir $Self->{obj_dir}", ], - verilator_flags2 => ['',], - verilator_flags3 => ['',], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - stdout_filename => $stdout_filename, - ); - -files_identical($stdout_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_ttempty.py b/test_regress/t/t_preproc_ttempty.py new file mode 100755 index 000000000..28ad7e4b2 --- /dev/null +++ b/test_regress/t/t_preproc_ttempty.py @@ -0,0 +1,29 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +stdout_filename = os.path.join(test.obj_dir, test.name + "__test.vpp") + +test.compile( + # Override default flags + v_flags=[''], + verilator_flags=["-E -P +incdir+t -Mdir", test.obj_dir], + verilator_flags2=[''], + verilator_flags3=[''], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False, + stdout_filename=stdout_filename) + +test.files_identical(stdout_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_preproc_undefineall.pl b/test_regress/t/t_preproc_undefineall.pl deleted file mode 100755 index 26a1f8cbb..000000000 --- a/test_regress/t/t_preproc_undefineall.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - v_flags2 => ['+define+PREDEF_COMMAND_LINE'], - ); - -ok(1); -1; diff --git a/test_regress/t/t_preproc_undefineall.py b/test_regress/t/t_preproc_undefineall.py new file mode 100755 index 000000000..07b8cc53a --- /dev/null +++ b/test_regress/t/t_preproc_undefineall.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(v_flags2=['+define+PREDEF_COMMAND_LINE']) + +test.passes() diff --git a/test_regress/t/t_priority_case.pl b/test_regress/t/t_priority_case.pl deleted file mode 100755 index 4f29861db..000000000 --- a/test_regress/t/t_priority_case.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_priority_case.py b/test_regress/t/t_priority_case.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_priority_case.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_probdist.pl b/test_regress/t/t_probdist.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_probdist.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_probdist.py b/test_regress/t/t_probdist.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_probdist.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_probdist_bad.pl b/test_regress/t/t_probdist_bad.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_probdist_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_probdist_bad.py b/test_regress/t/t_probdist_bad.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_probdist_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_probdist_cmake.pl b/test_regress/t/t_probdist_cmake.pl deleted file mode 100755 index de8a99173..000000000 --- a/test_regress/t/t_probdist_cmake.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_probdist.v"); - -compile( - verilator_make_gmake => 0, - verilator_make_cmake => 1, - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_probdist_cmake.py b/test_regress/t/t_probdist_cmake.py new file mode 100755 index 000000000..3dba41365 --- /dev/null +++ b/test_regress/t/t_probdist_cmake.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_probdist.v" + +test.compile(verilator_make_gmake=False, verilator_make_cmake=1) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_process.pl b/test_regress/t/t_process.pl deleted file mode 100755 index 241772b81..000000000 --- a/test_regress/t/t_process.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["--binary --timing"], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_process.py b/test_regress/t/t_process.py new file mode 100755 index 000000000..2d2607d45 --- /dev/null +++ b/test_regress/t/t_process.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["--binary --timing"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_process.v b/test_regress/t/t_process.v index 9d4f3fbb8..63844225e 100644 --- a/test_regress/t/t_process.v +++ b/test_regress/t/t_process.v @@ -34,7 +34,7 @@ module t(/*AUTOARG*/); if (0) p.await(); if (0) p.suspend(); if (0) p.resume(); - // See also t_urandom.pl + // See also t_urandom.py p.srandom(0); p.set_randstate(p.get_randstate()); diff --git a/test_regress/t/t_process_bad.pl b/test_regress/t/t_process_bad.pl deleted file mode 100755 index 6c378f2d6..000000000 --- a/test_regress/t/t_process_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--json-only", "--timing"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_process_bad.py b/test_regress/t/t_process_bad.py new file mode 100755 index 000000000..786f00c3e --- /dev/null +++ b/test_regress/t/t_process_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--json-only", "--timing"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_process_finished.pl b/test_regress/t/t_process_finished.pl deleted file mode 100755 index 55432b280..000000000 --- a/test_regress/t/t_process_finished.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_process_finished.py b/test_regress/t/t_process_finished.py new file mode 100755 index 000000000..34b0247e9 --- /dev/null +++ b/test_regress/t/t_process_finished.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_process_fork.pl b/test_regress/t/t_process_fork.pl deleted file mode 100755 index 859251cfa..000000000 --- a/test_regress/t/t_process_fork.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--binary --timing"], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_process_fork.py b/test_regress/t/t_process_fork.py new file mode 100755 index 000000000..a74b0c7ec --- /dev/null +++ b/test_regress/t/t_process_fork.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary --timing"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_process_kill.pl b/test_regress/t/t_process_kill.pl deleted file mode 100755 index 55432b280..000000000 --- a/test_regress/t/t_process_kill.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_process_kill.py b/test_regress/t/t_process_kill.py new file mode 100755 index 000000000..34b0247e9 --- /dev/null +++ b/test_regress/t/t_process_kill.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_process_notiming.pl b/test_regress/t/t_process_notiming.pl deleted file mode 100755 index f7118bd7d..000000000 --- a/test_regress/t/t_process_notiming.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_process.v"); - -lint( - expect_filename => $Self->{golden_filename}, - v_flags2 => ["+define+T_PROCESS+std::process", "--no-timing"], - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_process_notiming.py b/test_regress/t/t_process_notiming.py new file mode 100755 index 000000000..a4f6917ce --- /dev/null +++ b/test_regress/t/t_process_notiming.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_process.v" + +test.lint(expect_filename=test.golden_filename, + v_flags2=["+define+T_PROCESS+std::process", "--no-timing"], + fails=True) + +test.passes() diff --git a/test_regress/t/t_process_parse.pl b/test_regress/t/t_process_parse.pl deleted file mode 100755 index 4b6b64de0..000000000 --- a/test_regress/t/t_process_parse.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t_process.v"); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - verilator_flags2 => ["--debug-exit-uvm", "--json-only"], - make_main => 0, - make_top_shell => 0, - verilator_make_gmake => 0, - ); - -file_grep($out_filename, qr/./); # Exists - -ok(1); -1; diff --git a/test_regress/t/t_process_parse.py b/test_regress/t/t_process_parse.py new file mode 100755 index 000000000..5bda0b542 --- /dev/null +++ b/test_regress/t/t_process_parse.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t_process.v" + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(verilator_flags2=["--debug-exit-uvm", "--json-only"], + make_main=False, + make_top_shell=False, + verilator_make_gmake=False) + +test.file_grep(out_filename, r'.') # Exists + +test.passes() diff --git a/test_regress/t/t_process_propagation.pl b/test_regress/t/t_process_propagation.pl deleted file mode 100755 index dee19d2aa..000000000 --- a/test_regress/t/t_process_propagation.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_process_propagation.py b/test_regress/t/t_process_propagation.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_process_propagation.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_process_rand.pl b/test_regress/t/t_process_rand.pl deleted file mode 100755 index 7ad99b35f..000000000 --- a/test_regress/t/t_process_rand.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["--binary --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_process_rand.py b/test_regress/t/t_process_rand.py new file mode 100755 index 000000000..bef04b878 --- /dev/null +++ b/test_regress/t/t_process_rand.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["--binary --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_process_redecl.pl b/test_regress/t/t_process_redecl.pl deleted file mode 100755 index 10266d6f8..000000000 --- a/test_regress/t/t_process_redecl.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - ); - -ok(1); -1; diff --git a/test_regress/t/t_process_redecl.py b/test_regress/t/t_process_redecl.py new file mode 100755 index 000000000..c8dddaddf --- /dev/null +++ b/test_regress/t/t_process_redecl.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_process_std.pl b/test_regress/t/t_process_std.pl deleted file mode 100755 index 2010b7b92..000000000 --- a/test_regress/t/t_process_std.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_process.v"); - -compile( - v_flags2 => ["--binary --timing", "+define+T_PROCESS+std::process"], - ); - -execute( - ) if !$Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_process_std.py b/test_regress/t/t_process_std.py new file mode 100755 index 000000000..7d37afe6f --- /dev/null +++ b/test_regress/t/t_process_std.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_process.v" + +test.compile(v_flags2=["--binary --timing", "+define+T_PROCESS+std::process"]) + +if not test.vlt_all: + test.execute() + +test.passes() diff --git a/test_regress/t/t_process_task.pl b/test_regress/t/t_process_task.pl deleted file mode 100755 index a09126270..000000000 --- a/test_regress/t/t_process_task.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_process_task.py b/test_regress/t/t_process_task.py new file mode 100755 index 000000000..a57ed056c --- /dev/null +++ b/test_regress/t/t_process_task.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_prof.pl b/test_regress/t/t_prof.pl deleted file mode 100755 index 4216a5544..000000000 --- a/test_regress/t/t_prof.pl +++ /dev/null @@ -1,49 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -# TODO below might no longer be required as configure checks for -pg -if ($ENV{VERILATOR_TEST_NO_GPROF}) { - skip("Skipping due to VERILATOR_TEST_NO_GPROF"); -} else { - dotest(); -} - -ok(1); - -sub dotest { - compile( - verilator_flags2 => ["--stats --prof-cfuncs +define+T_PROF"], - ); - - unlink $_ foreach (glob "$Self->{obj_dir}/gmon.out.*"); - setenv('GMON_OUT_PREFIX', "$Self->{obj_dir}/gmon.out"); - - execute( - ); - - my $gmon_path; - $gmon_path = $_ foreach (glob "$Self->{obj_dir}/gmon.out.*"); - $gmon_path or error("Profiler did not create a gmon.out"); - (my $gmon_base = $gmon_path) =~ s!.*[/\\]!!; - - run(cmd => ["cd $Self->{obj_dir} && gprof $Self->{vm_prefix} $gmon_base > gprof.log"], - check_finished => 0); - - run(cmd => ["cd $Self->{obj_dir} && $ENV{VERILATOR_ROOT}/bin/verilator_profcfunc gprof.log > profcfuncs.log"], - check_finished => 0); - - file_grep("$Self->{obj_dir}/profcfuncs.log", qr/Overall summary by/); - file_grep("$Self->{obj_dir}/profcfuncs.log", qr/VLib + VL_POWSS_QQQ/); - file_grep("$Self->{obj_dir}/profcfuncs.log", qr/VBlock + t_prof:/); -} - -1; diff --git a/test_regress/t/t_prof.py b/test_regress/t/t_prof.py new file mode 100755 index 000000000..f47b92805 --- /dev/null +++ b/test_regress/t/t_prof.py @@ -0,0 +1,47 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(verilator_flags2=["--stats --prof-cfuncs +define+T_PROF"]) + +# TODO below might no longer be required as configure checks for -pg +if 'VERILATOR_TEST_NO_GPROF' in os.environ: + test.skip("Skipping due to VERILATOR_TEST_NO_GPROF") + +for filename in glob.glob(test.obj_dir + "/gmon.out.*"): + test.unlink_ok(filename) +test.setenv('GMON_OUT_PREFIX', test.obj_dir + "/gmon.out") + +test.execute() + +gmon_path = None +for filename in glob.glob(test.obj_dir + "/gmon.out.*"): + gmon_path = filename +if not gmon_path: + test.error("Profiler did not create a gmon.out") +gmon_base = re.sub(r'.*[/\\]', '', gmon_path) + +test.run( + cmd=["cd " + test.obj_dir + " && gprof " + test.vm_prefix + " " + gmon_base + " > gprof.log"], + check_finished=False) + +test.run(cmd=[ + "cd " + test.obj_dir + " && " + os.environ["VERILATOR_ROOT"] + + "/bin/verilator_profcfunc gprof.log > profcfuncs.log" +], + check_finished=False) + +test.file_grep(test.obj_dir + "/profcfuncs.log", r'Overall summary by') +test.file_grep(test.obj_dir + "/profcfuncs.log", r'VLib + VL_POWSS_QQQ') +test.file_grep(test.obj_dir + "/profcfuncs.log", r'VBlock + t_prof:') + +test.passes() diff --git a/test_regress/t/t_prof_timing.pl b/test_regress/t/t_prof_timing.pl deleted file mode 100755 index 82883251a..000000000 --- a/test_regress/t/t_prof_timing.pl +++ /dev/null @@ -1,56 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_prof.v"); - -# TODO below might no longer be required as configure checks for -pg -if ($ENV{VERILATOR_TEST_NO_GPROF}) { - skip("Skipping due to VERILATOR_TEST_NO_GPROF"); -} elsif (!$Self->have_coroutines) { - skip("No coroutine support"); -} else { - dotest(); -} - -ok(1); - -sub dotest { - compile( - verilator_flags2 => ["--stats --prof-cfuncs --binary"], - ); - - unlink $_ foreach (glob "$Self->{obj_dir}/gmon.out.*"); - setenv('GMON_OUT_PREFIX', "$Self->{obj_dir}/gmon.out"); - - execute( - ); - - my $gmon_path; - $gmon_path = $_ foreach (glob "$Self->{obj_dir}/gmon.out.*"); - $gmon_path or error("Profiler did not create a gmon.out"); - (my $gmon_base = $gmon_path) =~ s!.*[/\\]!!; - - run(cmd => ["cd $Self->{obj_dir} && gprof $Self->{vm_prefix} $gmon_base > gprof.log"], - check_finished => 0); - - run(cmd => ["cd $Self->{obj_dir} && $ENV{VERILATOR_ROOT}/bin/verilator_profcfunc gprof.log > profcfuncs.log"], - check_finished => 0); - - file_grep("$Self->{obj_dir}/profcfuncs.log", qr/Overall summary by/); -# Appears that GCC 11.4 has a bug whereby it doesn't trace function calls -# within coroutines; CLang seems to work correctly. -# file_grep("$Self->{obj_dir}/profcfuncs.log", qr/VLib + VL_POWSS_QQQ/); - file_grep("$Self->{obj_dir}/profcfuncs.log", qr/VLib + VL_WRITEF/); - file_grep("$Self->{obj_dir}/profcfuncs.log", qr/VBlock + t_prof:/); -} - -1; diff --git a/test_regress/t/t_prof_timing.py b/test_regress/t/t_prof_timing.py new file mode 100755 index 000000000..e06dc0024 --- /dev/null +++ b/test_regress/t/t_prof_timing.py @@ -0,0 +1,53 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_prof.v" + +# TODO below might no longer be required as configure checks for -pg +if 'VERILATOR_TEST_NO_GPROF' in os.environ: + test.skip("Skipping due to VERILATOR_TEST_NO_GPROF") +if not test.have_coroutines: + test.skip("No coroutine support") + +test.compile(verilator_flags2=["--stats --prof-cfuncs --binary"]) + +for filename in glob.glob(test.obj_dir + "/gmon.out.*"): + test.unlink_ok(filename) +test.setenv('GMON_OUT_PREFIX', test.obj_dir + "/gmon.out") + +test.execute() + +gmon_path = None +for filename in glob.glob(test.obj_dir + "/gmon.out.*"): + gmon_path = filename +if not gmon_path: + test.error("Profiler did not create a gmon.out") +gmon_base = re.sub(r'.*[/\\]', '', gmon_path) + +test.run( + cmd=["cd " + test.obj_dir + " && gprof " + test.vm_prefix + " " + gmon_base + " > gprof.log"], + check_finished=False) + +test.run(cmd=[ + "cd " + test.obj_dir + " && " + os.environ["VERILATOR_ROOT"] + + "/bin/verilator_profcfunc gprof.log > profcfuncs.log" +], + check_finished=False) + +test.file_grep(test.obj_dir + "/profcfuncs.log", r'Overall summary by') +# Appears that GCC 11.4 has a bug whereby it doesn't trace function calls +# within coroutines; CLang seems to work correctly. +# test.file_grep(test.obj_dir + "/profcfuncs.log", r'VLib + VL_POWSS_QQQ') +test.file_grep(test.obj_dir + "/profcfuncs.log", r'VLib + VL_WRITEF') +test.file_grep(test.obj_dir + "/profcfuncs.log", r'VBlock + t_prof:') + +test.passes() diff --git a/test_regress/t/t_profc.pl b/test_regress/t/t_profc.pl deleted file mode 100755 index 83feeac3b..000000000 --- a/test_regress/t/t_profc.pl +++ /dev/null @@ -1,39 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t_prof.v"); - -dotest(); - -ok(1); - -sub dotest { - compile( - verilator_flags2 => ["--stats --prof-c +define+T_PROF"], - ); - - unlink $_ foreach (glob "$Self->{obj_dir}/gmon.out.*"); - setenv('GMON_OUT_PREFIX', "$Self->{obj_dir}/gmon.out"); - - execute( - ); - - my $gmon_path; - $gmon_path = $_ foreach (glob "$Self->{obj_dir}/gmon.out.*"); - $gmon_path or error("Profiler did not create a gmon.out"); - (my $gmon_base = $gmon_path) =~ s!.*[/\\]!!; - - run(cmd => ["cd $Self->{obj_dir} && gprof $Self->{vm_prefix} $gmon_base > gprof.log"], - check_finished => 0); -} - -1; diff --git a/test_regress/t/t_profc.py b/test_regress/t/t_profc.py new file mode 100755 index 000000000..74f928bb9 --- /dev/null +++ b/test_regress/t/t_profc.py @@ -0,0 +1,38 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t_prof.v" + +test.compile(verilator_flags2=["--stats --prof-c +define+T_PROF"]) + +# TODO below might no longer be required as configure checks for -pg +if 'VERILATOR_TEST_NO_GPROF' in os.environ: + test.skip("Skipping due to VERILATOR_TEST_NO_GPROF") + +for filename in glob.glob(test.obj_dir + "/gmon.out.*"): + test.unlink_ok(filename) +test.setenv('GMON_OUT_PREFIX', test.obj_dir + "/gmon.out") + +test.execute() + +gmon_path = None +for filename in glob.glob(test.obj_dir + "/gmon.out.*"): + gmon_path = filename +if not gmon_path: + test.error("Profiler did not create a gmon.out") +gmon_base = re.sub(r'.*[/\\]', '', gmon_path) + +test.run( + cmd=["cd " + test.obj_dir + " && gprof " + test.vm_prefix + " " + gmon_base + " > gprof.log"], + check_finished=False) + +test.passes() diff --git a/test_regress/t/t_profcfunc.pl b/test_regress/t/t_profcfunc.pl deleted file mode 100755 index ec29d69ff..000000000 --- a/test_regress/t/t_profcfunc.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(dist => 1); - -run(cmd => ["cd $Self->{obj_dir} && $ENV{VERILATOR_ROOT}/bin/verilator_profcfunc $Self->{t_dir}/t_profcfunc.gprof > profcfuncs.log"], - check_finished => 0); - -files_identical("$Self->{obj_dir}/profcfuncs.log", $Self->{golden_filename}); - -ok(1); - -1; diff --git a/test_regress/t/t_profcfunc.py b/test_regress/t/t_profcfunc.py new file mode 100755 index 000000000..b9523a78b --- /dev/null +++ b/test_regress/t/t_profcfunc.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +test.run(cmd=[ + "cd " + test.obj_dir + " && " + os.environ["VERILATOR_ROOT"] + "/bin/verilator_profcfunc", + test.t_dir + "/t_profcfunc.gprof > profcfuncs.log" +], + check_finished=False) + +test.files_identical(test.obj_dir + "/profcfuncs.log", test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_program.pl b/test_regress/t/t_program.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_program.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_program.py b/test_regress/t/t_program.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_program.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_program_anonymous.pl b/test_regress/t/t_program_anonymous.pl deleted file mode 100755 index 391ec23fd..000000000 --- a/test_regress/t/t_program_anonymous.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -execute( - ) if !$Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_program_anonymous.py b/test_regress/t/t_program_anonymous.py new file mode 100755 index 000000000..966dc53da --- /dev/null +++ b/test_regress/t/t_program_anonymous.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) + +if not test.vlt_all: + test.execute() + +test.passes() diff --git a/test_regress/t/t_program_extern.pl b/test_regress/t/t_program_extern.pl deleted file mode 100755 index 391ec23fd..000000000 --- a/test_regress/t/t_program_extern.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -execute( - ) if !$Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_program_extern.py b/test_regress/t/t_program_extern.py new file mode 100755 index 000000000..966dc53da --- /dev/null +++ b/test_regress/t/t_program_extern.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) + +if not test.vlt_all: + test.execute() + +test.passes() diff --git a/test_regress/t/t_protect_ids.pl b/test_regress/t/t_protect_ids.pl deleted file mode 100755 index b35f6f3cb..000000000 --- a/test_regress/t/t_protect_ids.pl +++ /dev/null @@ -1,53 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -# Use --debug-protect to assist debug - -# This test makes randomly named .cpp/.h files, which tend to collect, so remove them first -foreach my $filename (glob ("$Self->{obj_dir}/*_PS*.cpp" - . " $Self->{obj_dir}/*_PS*.h" - . " $Self->{obj_dir}/*.d")) { - print "rm $filename\n" if $Self->{verbose}; - unlink $filename; -} - -compile( - verilator_flags2 => ["--protect-ids", - "--protect-key SECRET_KEY", - "--trace", - "--coverage", - "-Wno-INSECURE", - "t/t_protect_ids_c.cpp"], - ); - -execute( - ); - -# 'to="PS"' indicates means we probably mis-protected something already protected -# Use --debug-protect to assist debugging these -file_grep_not("$Self->{obj_dir}/$Self->{vm_prefix}__idmap.xml", qr/to="PS/); - -if ($Self->{vlt_all}) { - # Check for secret in any outputs - my $any; - foreach my $filename (glob $Self->{obj_dir} . "/*.[ch]*") { - if ($filename =~ /secret/i) { - $Self->error("Secret found in a filename: " . $filename); - } - file_grep_not($filename, qr/secret/); - $any = 1; - } - $any or $Self->error("No outputs found"); -} - -ok(1); -1; diff --git a/test_regress/t/t_protect_ids.py b/test_regress/t/t_protect_ids.py new file mode 100755 index 000000000..1c610fc8e --- /dev/null +++ b/test_regress/t/t_protect_ids.py @@ -0,0 +1,39 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +# Use --debug-protect to assist debug + +# This test makes randomly named .cpp/.h files, which tend to collect, so remove them first +for filename in (glob.glob(test.obj_dir + "/*_PS*.cpp") + glob.glob(test.obj_dir + "/*_PS*.h") + + glob.glob(test.obj_dir + "/*.d")): + test.unlink_ok(filename) + +test.compile(verilator_flags2=[ + "--protect-ids", "--protect-key SECRET_KEY", "--trace", "--coverage", "-Wno-INSECURE", + "t/t_protect_ids_c.cpp" +]) + +test.execute() + +# 'to="PS"' indicates means we probably mis-protected something already protected +# Use --debug-protect to assist debugging these +test.file_grep_not(test.obj_dir + "/" + test.vm_prefix + "__idmap.xml", r'to="PS') + +if test.vlt_all: + # Check for secret in any outputs + for filename in test.glob_some(test.obj_dir + "/*.[ch]*"): + if re.search(r'secret', filename, re.IGNORECASE): + test.error("Secret found in a filename: " + filename) + test.file_grep_not(filename, r'secret') + +test.passes() diff --git a/test_regress/t/t_protect_ids_bad.pl b/test_regress/t/t_protect_ids_bad.pl deleted file mode 100755 index 47ea4d4e1..000000000 --- a/test_regress/t/t_protect_ids_bad.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["--protect-ids", - "--trace", - "--public", - "--vpi", - ], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_protect_ids_bad.py b/test_regress/t/t_protect_ids_bad.py new file mode 100755 index 000000000..934f802f7 --- /dev/null +++ b/test_regress/t/t_protect_ids_bad.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=[ + "--protect-ids", + "--trace", + "--public", + "--vpi", +], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_protect_ids_debug.pl b/test_regress/t/t_protect_ids_debug.pl deleted file mode 100755 index d1da5019c..000000000 --- a/test_regress/t/t_protect_ids_debug.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_protect_ids.v"); - -compile( - verilator_flags2 => ["--protect-ids", - "--protect-key SECRET_KEY", - "--trace", - "--debug-protect", - "--coverage", - "-Wno-INSECURE",], - verilator_make_gmake => 0, - ); - -ok(1); -1; diff --git a/test_regress/t/t_protect_ids_debug.py b/test_regress/t/t_protect_ids_debug.py new file mode 100755 index 000000000..10b0e15bb --- /dev/null +++ b/test_regress/t/t_protect_ids_debug.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_protect_ids.v" + +test.compile(verilator_flags2=[ + "--protect-ids", + "--protect-key SECRET_KEY", + "--trace", + "--debug-protect", + "--coverage", + "-Wno-INSECURE", +], + verilator_make_gmake=False) + +test.passes() diff --git a/test_regress/t/t_protect_ids_key.pl b/test_regress/t/t_protect_ids_key.pl deleted file mode 100755 index 63dae3ebb..000000000 --- a/test_regress/t/t_protect_ids_key.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_protect_ids.v"); - -compile( - verilator_flags2 => ["--protect-ids --protect-key SECRET_KEY", - "t/t_protect_ids_c.cpp"], - ); - -execute( - ); - -# Since using a named key, we can check for always identical map -files_identical("$Self->{obj_dir}/$Self->{vm_prefix}__idmap.xml", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_protect_ids_key.py b/test_regress/t/t_protect_ids_key.py new file mode 100755 index 000000000..3cf278fdf --- /dev/null +++ b/test_regress/t/t_protect_ids_key.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_protect_ids.v" + +test.compile(verilator_flags2=["--protect-ids --protect-key SECRET_KEY", "t/t_protect_ids_c.cpp"]) + +test.execute() + +# Since using a named key, we can check for always identical maptest.files_identical(test.obj_dir + "/"+test.vm_prefix+"__idmap.xml", test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_pub_unpacked_port.pl b/test_regress/t/t_pub_unpacked_port.pl deleted file mode 100755 index 55bd57e5c..000000000 --- a/test_regress/t/t_pub_unpacked_port.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile(); - -execute(); - -ok(1); -1; diff --git a/test_regress/t/t_pub_unpacked_port.py b/test_regress/t/t_pub_unpacked_port.py new file mode 100755 index 000000000..fc5a55e3f --- /dev/null +++ b/test_regress/t/t_pub_unpacked_port.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_public_clk.pl b/test_regress/t/t_public_clk.pl deleted file mode 100755 index 643d1a934..000000000 --- a/test_regress/t/t_public_clk.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => [ - "--exe", - "$Self->{t_dir}/$Self->{name}.cpp" - ], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_public_clk.py b/test_regress/t/t_public_clk.py new file mode 100755 index 000000000..f37ad07c8 --- /dev/null +++ b/test_regress/t/t_public_clk.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_public_seq.pl b/test_regress/t/t_public_seq.pl deleted file mode 100755 index 643d1a934..000000000 --- a/test_regress/t/t_public_seq.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => [ - "--exe", - "$Self->{t_dir}/$Self->{name}.cpp" - ], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_public_seq.py b/test_regress/t/t_public_seq.py new file mode 100755 index 000000000..f37ad07c8 --- /dev/null +++ b/test_regress/t/t_public_seq.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_queue.pl b/test_regress/t/t_queue.pl deleted file mode 100755 index 56363dab6..000000000 --- a/test_regress/t/t_queue.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_queue.py b/test_regress/t/t_queue.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_queue.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_queue_back.pl b/test_regress/t/t_queue_back.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_queue_back.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_queue_back.py b/test_regress/t/t_queue_back.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_queue_back.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_queue_bounded.pl b/test_regress/t/t_queue_bounded.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_queue_bounded.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_queue_bounded.py b/test_regress/t/t_queue_bounded.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_queue_bounded.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_queue_class.pl b/test_regress/t/t_queue_class.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_queue_class.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_queue_class.py b/test_regress/t/t_queue_class.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_queue_class.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_queue_compare.pl b/test_regress/t/t_queue_compare.pl deleted file mode 100755 index 56363dab6..000000000 --- a/test_regress/t/t_queue_compare.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_queue_compare.py b/test_regress/t/t_queue_compare.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_queue_compare.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_queue_empty_bad.pl b/test_regress/t/t_queue_empty_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_queue_empty_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_queue_empty_bad.py b/test_regress/t/t_queue_empty_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_queue_empty_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_queue_empty_pin.pl b/test_regress/t/t_queue_empty_pin.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_queue_empty_pin.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_queue_empty_pin.py b/test_regress/t/t_queue_empty_pin.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_queue_empty_pin.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_queue_init.pl b/test_regress/t/t_queue_init.pl deleted file mode 100755 index 56363dab6..000000000 --- a/test_regress/t/t_queue_init.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_queue_init.py b/test_regress/t/t_queue_init.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_queue_init.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_queue_insert_at_end.pl b/test_regress/t/t_queue_insert_at_end.pl deleted file mode 100755 index e22e7f5d9..000000000 --- a/test_regress/t/t_queue_insert_at_end.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_queue_insert_at_end.py b/test_regress/t/t_queue_insert_at_end.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_queue_insert_at_end.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_queue_method.pl b/test_regress/t/t_queue_method.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_queue_method.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_queue_method.py b/test_regress/t/t_queue_method.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_queue_method.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_queue_method2_bad.pl b/test_regress/t/t_queue_method2_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_queue_method2_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_queue_method2_bad.py b/test_regress/t/t_queue_method2_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_queue_method2_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_queue_method3_bad.pl b/test_regress/t/t_queue_method3_bad.pl deleted file mode 100755 index a083f46f5..000000000 --- a/test_regress/t/t_queue_method3_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_queue_method3_bad.py b/test_regress/t/t_queue_method3_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_queue_method3_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_queue_method_bad.pl b/test_regress/t/t_queue_method_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_queue_method_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_queue_method_bad.py b/test_regress/t/t_queue_method_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_queue_method_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_queue_persistence_inl.pl b/test_regress/t/t_queue_persistence_inl.pl deleted file mode 100755 index d4bd5293c..000000000 --- a/test_regress/t/t_queue_persistence_inl.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_queue_persistence.v"); - -if (!$Self->have_coroutines) { - skip("No coroutine support"); -} -else { - compile( - timing_loop => 1, - verilator_flags2 => ["--timing"], - ); - - execute( - ); -} - -ok(1); -1; diff --git a/test_regress/t/t_queue_persistence_inl.py b/test_regress/t/t_queue_persistence_inl.py new file mode 100755 index 000000000..07551a9f2 --- /dev/null +++ b/test_regress/t/t_queue_persistence_inl.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_queue_persistence.v" + +if not test.have_coroutines: + test.skip("No coroutine support") + +test.compile(timing_loop=True, verilator_flags2=["--timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_queue_persistence_noinl.pl b/test_regress/t/t_queue_persistence_noinl.pl deleted file mode 100755 index 56c26bff4..000000000 --- a/test_regress/t/t_queue_persistence_noinl.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_queue_persistence.v"); - -if (!$Self->have_coroutines) { - skip("No coroutine support"); -} -else { - compile( - timing_loop => 1, - verilator_flags2 => ["--binary --timing --fno-inline +define+TEST_NOINLINE"], - ); - - execute( - ); -} - -ok(1); -1; diff --git a/test_regress/t/t_queue_persistence_noinl.py b/test_regress/t/t_queue_persistence_noinl.py new file mode 100755 index 000000000..4737dc169 --- /dev/null +++ b/test_regress/t/t_queue_persistence_noinl.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_queue_persistence.v" + +if not test.have_coroutines: + test.skip("No coroutine support") + +test.compile(timing_loop=True, + verilator_flags2=["--binary --timing --fno-inline +define+TEST_NOINLINE"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_queue_pushpop.pl b/test_regress/t/t_queue_pushpop.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_queue_pushpop.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_queue_pushpop.py b/test_regress/t/t_queue_pushpop.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_queue_pushpop.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_queue_slice.pl b/test_regress/t/t_queue_slice.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_queue_slice.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_queue_slice.py b/test_regress/t/t_queue_slice.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_queue_slice.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_queue_struct.pl b/test_regress/t/t_queue_struct.pl deleted file mode 100755 index 56363dab6..000000000 --- a/test_regress/t/t_queue_struct.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_queue_struct.py b/test_regress/t/t_queue_struct.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_queue_struct.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_queue_unknown_sel.pl b/test_regress/t/t_queue_unknown_sel.pl deleted file mode 100755 index 157d7a50b..000000000 --- a/test_regress/t/t_queue_unknown_sel.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_queue_unknown_sel.py b/test_regress/t/t_queue_unknown_sel.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_queue_unknown_sel.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_queue_unpacked.pl b/test_regress/t/t_queue_unpacked.pl deleted file mode 100755 index 56363dab6..000000000 --- a/test_regress/t/t_queue_unpacked.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_queue_unpacked.py b/test_regress/t/t_queue_unpacked.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_queue_unpacked.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_queue_var_slice.pl b/test_regress/t/t_queue_var_slice.pl deleted file mode 100755 index e22e7f5d9..000000000 --- a/test_regress/t/t_queue_var_slice.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_queue_var_slice.py b/test_regress/t/t_queue_var_slice.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_queue_var_slice.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_queue_void_ops.pl b/test_regress/t/t_queue_void_ops.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_queue_void_ops.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_queue_void_ops.py b/test_regress/t/t_queue_void_ops.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_queue_void_ops.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randc.pl b/test_regress/t/t_randc.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_randc.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_randc.py b/test_regress/t/t_randc.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_randc.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randc_oversize_bad.pl b/test_regress/t/t_randc_oversize_bad.pl deleted file mode 100755 index 009248fc5..000000000 --- a/test_regress/t/t_randc_oversize_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_randc_oversize_bad.py b/test_regress/t/t_randc_oversize_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_randc_oversize_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_randcase.pl b/test_regress/t/t_randcase.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_randcase.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_randcase.py b/test_regress/t/t_randcase.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_randcase.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randcase_bad.pl b/test_regress/t/t_randcase_bad.pl deleted file mode 100755 index e988c6264..000000000 --- a/test_regress/t/t_randcase_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_randcase_bad.py b/test_regress/t/t_randcase_bad.py new file mode 100755 index 000000000..97abb660e --- /dev/null +++ b/test_regress/t/t_randcase_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_randomize.pl b/test_regress/t/t_randomize.pl deleted file mode 100755 index 63947fd00..000000000 --- a/test_regress/t/t_randomize.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_randomize.py b/test_regress/t/t_randomize.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_randomize.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_randomize_bbox.pl b/test_regress/t/t_randomize_bbox.pl deleted file mode 100755 index 2f89e3fb1..000000000 --- a/test_regress/t/t_randomize_bbox.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_randomize.v"); - -lint( - verilator_flags => ["--bbox-unsup"], - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_randomize_bbox.py b/test_regress/t/t_randomize_bbox.py new file mode 100755 index 000000000..706273143 --- /dev/null +++ b/test_regress/t/t_randomize_bbox.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_randomize.v" + +test.lint(verilator_flags=["--bbox-unsup"], fails=True) + +test.passes() diff --git a/test_regress/t/t_randomize_extern.pl b/test_regress/t/t_randomize_extern.pl deleted file mode 100755 index 63947fd00..000000000 --- a/test_regress/t/t_randomize_extern.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_randomize_extern.py b/test_regress/t/t_randomize_extern.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_randomize_extern.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_randomize_inline_var_ctl.pl b/test_regress/t/t_randomize_inline_var_ctl.pl deleted file mode 100755 index 1e40acc90..000000000 --- a/test_regress/t/t_randomize_inline_var_ctl.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_solver) { - skip("No constraint solver installed"); -} else { - compile( - ); - - execute( - ); -} - -ok(1); -1; diff --git a/test_regress/t/t_randomize_inline_var_ctl.py b/test_regress/t/t_randomize_inline_var_ctl.py new file mode 100755 index 000000000..a2b131082 --- /dev/null +++ b/test_regress/t/t_randomize_inline_var_ctl.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randomize_inline_var_ctl_bad.pl b/test_regress/t/t_randomize_inline_var_ctl_bad.pl deleted file mode 100755 index 14a6e3229..000000000 --- a/test_regress/t/t_randomize_inline_var_ctl_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_randomize_inline_var_ctl_bad.py b/test_regress/t/t_randomize_inline_var_ctl_bad.py new file mode 100755 index 000000000..6038b562c --- /dev/null +++ b/test_regress/t/t_randomize_inline_var_ctl_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_randomize_inline_var_ctl_unsup_1.pl b/test_regress/t/t_randomize_inline_var_ctl_unsup_1.pl deleted file mode 100755 index 14a6e3229..000000000 --- a/test_regress/t/t_randomize_inline_var_ctl_unsup_1.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_randomize_inline_var_ctl_unsup_1.py b/test_regress/t/t_randomize_inline_var_ctl_unsup_1.py new file mode 100755 index 000000000..6038b562c --- /dev/null +++ b/test_regress/t/t_randomize_inline_var_ctl_unsup_1.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_randomize_inline_var_ctl_unsup_2.pl b/test_regress/t/t_randomize_inline_var_ctl_unsup_2.pl deleted file mode 100755 index 14a6e3229..000000000 --- a/test_regress/t/t_randomize_inline_var_ctl_unsup_2.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_randomize_inline_var_ctl_unsup_2.py b/test_regress/t/t_randomize_inline_var_ctl_unsup_2.py new file mode 100755 index 000000000..6038b562c --- /dev/null +++ b/test_regress/t/t_randomize_inline_var_ctl_unsup_2.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_randomize_method.pl b/test_regress/t/t_randomize_method.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_randomize_method.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_randomize_method.py b/test_regress/t/t_randomize_method.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_randomize_method.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randomize_method_bad.pl b/test_regress/t/t_randomize_method_bad.pl deleted file mode 100755 index 66fa61649..000000000 --- a/test_regress/t/t_randomize_method_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_randomize_method_bad.py b/test_regress/t/t_randomize_method_bad.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_randomize_method_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_randomize_method_complex_bad.pl b/test_regress/t/t_randomize_method_complex_bad.pl deleted file mode 100755 index 66fa61649..000000000 --- a/test_regress/t/t_randomize_method_complex_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_randomize_method_complex_bad.py b/test_regress/t/t_randomize_method_complex_bad.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_randomize_method_complex_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_randomize_method_constraints.pl b/test_regress/t/t_randomize_method_constraints.pl deleted file mode 100755 index 9562a55db..000000000 --- a/test_regress/t/t_randomize_method_constraints.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_solver) { - skip("No constraint solver installed"); -} else { - compile( - ); - - execute( - ); -} - -ok(1); -1; diff --git a/test_regress/t/t_randomize_method_constraints.py b/test_regress/t/t_randomize_method_constraints.py new file mode 100755 index 000000000..a2b131082 --- /dev/null +++ b/test_regress/t/t_randomize_method_constraints.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randomize_method_nclass_bad.pl b/test_regress/t/t_randomize_method_nclass_bad.pl deleted file mode 100755 index 66fa61649..000000000 --- a/test_regress/t/t_randomize_method_nclass_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_randomize_method_nclass_bad.py b/test_regress/t/t_randomize_method_nclass_bad.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_randomize_method_nclass_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_randomize_method_types_unsup.pl b/test_regress/t/t_randomize_method_types_unsup.pl deleted file mode 100755 index 6ad7137de..000000000 --- a/test_regress/t/t_randomize_method_types_unsup.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_randomize_method_types_unsup.py b/test_regress/t/t_randomize_method_types_unsup.py new file mode 100755 index 000000000..710a094ab --- /dev/null +++ b/test_regress/t/t_randomize_method_types_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_randomize_method_with.pl b/test_regress/t/t_randomize_method_with.pl deleted file mode 100755 index 1de0e32ff..000000000 --- a/test_regress/t/t_randomize_method_with.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_solver) { - skip("No constraint solver installed"); -} else { - compile( - # Ensure we test captures of static variables - verilator_flags2 => ["--fno-inline"], - ); - - execute( - ); -} - -for my $file (glob_all("$Self->{obj_dir}/$Self->{vm_prefix}*Baz*.cpp")) { - # Check that "Baz" has no constrained random generator - file_grep_not($file, "this->__PVT__constraint"); -} - -ok(1); -1; diff --git a/test_regress/t/t_randomize_method_with.py b/test_regress/t/t_randomize_method_with.py new file mode 100755 index 000000000..0652adf1b --- /dev/null +++ b/test_regress/t/t_randomize_method_with.py @@ -0,0 +1,27 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile( + # Ensure we test captures of static variables + verilator_flags2=["--fno-inline"]) + +test.execute() + +for filename in test.glob_some(test.obj_dir + "/" + test.vm_prefix + "*Baz*.cpp"): + # Check that "Baz" has no constrained random generator + test.file_grep_not(filename, "this->__PVT__constraint") + +test.passes() diff --git a/test_regress/t/t_randomize_method_with_bad.pl b/test_regress/t/t_randomize_method_with_bad.pl deleted file mode 100755 index f48f2cb92..000000000 --- a/test_regress/t/t_randomize_method_with_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_randomize_method_with_bad.py b/test_regress/t/t_randomize_method_with_bad.py new file mode 100755 index 000000000..24e87157b --- /dev/null +++ b/test_regress/t/t_randomize_method_with_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_randomize_method_with_scoping.pl b/test_regress/t/t_randomize_method_with_scoping.pl deleted file mode 100755 index 1973412e8..000000000 --- a/test_regress/t/t_randomize_method_with_scoping.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_solver) { - skip("No constraint solver installed"); -} else { - compile( - ); - - execute( - ); -} - -ok(1); -1; diff --git a/test_regress/t/t_randomize_method_with_scoping.py b/test_regress/t/t_randomize_method_with_scoping.py new file mode 100755 index 000000000..a2b131082 --- /dev/null +++ b/test_regress/t/t_randomize_method_with_scoping.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randomize_prepost.pl b/test_regress/t/t_randomize_prepost.pl deleted file mode 100755 index 9562a55db..000000000 --- a/test_regress/t/t_randomize_prepost.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_solver) { - skip("No constraint solver installed"); -} else { - compile( - ); - - execute( - ); -} - -ok(1); -1; diff --git a/test_regress/t/t_randomize_prepost.py b/test_regress/t/t_randomize_prepost.py new file mode 100755 index 000000000..a2b131082 --- /dev/null +++ b/test_regress/t/t_randomize_prepost.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randomize_rand_mode.pl b/test_regress/t/t_randomize_rand_mode.pl deleted file mode 100755 index 546025930..000000000 --- a/test_regress/t/t_randomize_rand_mode.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - - -ok(1); -1; diff --git a/test_regress/t/t_randomize_rand_mode.py b/test_regress/t/t_randomize_rand_mode.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_randomize_rand_mode.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randomize_rand_mode_bad.pl b/test_regress/t/t_randomize_rand_mode_bad.pl deleted file mode 100755 index 63947fd00..000000000 --- a/test_regress/t/t_randomize_rand_mode_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_randomize_rand_mode_bad.py b/test_regress/t/t_randomize_rand_mode_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_randomize_rand_mode_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_randomize_rand_mode_constr.pl b/test_regress/t/t_randomize_rand_mode_constr.pl deleted file mode 100755 index 1e40acc90..000000000 --- a/test_regress/t/t_randomize_rand_mode_constr.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_solver) { - skip("No constraint solver installed"); -} else { - compile( - ); - - execute( - ); -} - -ok(1); -1; diff --git a/test_regress/t/t_randomize_rand_mode_constr.py b/test_regress/t/t_randomize_rand_mode_constr.py new file mode 100755 index 000000000..a2b131082 --- /dev/null +++ b/test_regress/t/t_randomize_rand_mode_constr.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randomize_rand_mode_unsup.pl b/test_regress/t/t_randomize_rand_mode_unsup.pl deleted file mode 100755 index 63947fd00..000000000 --- a/test_regress/t/t_randomize_rand_mode_unsup.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_randomize_rand_mode_unsup.py b/test_regress/t/t_randomize_rand_mode_unsup.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_randomize_rand_mode_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_randomize_srandom.pl b/test_regress/t/t_randomize_srandom.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_randomize_srandom.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_randomize_srandom.py b/test_regress/t/t_randomize_srandom.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_randomize_srandom.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randomize_this.pl b/test_regress/t/t_randomize_this.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_randomize_this.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_randomize_this.py b/test_regress/t/t_randomize_this.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_randomize_this.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randomize_union.pl b/test_regress/t/t_randomize_union.pl deleted file mode 100755 index 7b520d284..000000000 --- a/test_regress/t/t_randomize_union.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_solver) { - skip("No constraint solver installed"); -} else { - compile( - ); - - execute( - check_finished => 1, - ); -} - -ok(1); -1; diff --git a/test_regress/t/t_randomize_union.py b/test_regress/t/t_randomize_union.py new file mode 100755 index 000000000..a2b131082 --- /dev/null +++ b/test_regress/t/t_randomize_union.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randomize_union_bad.pl b/test_regress/t/t_randomize_union_bad.pl deleted file mode 100755 index f48f2cb92..000000000 --- a/test_regress/t/t_randomize_union_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_randomize_union_bad.py b/test_regress/t/t_randomize_union_bad.py new file mode 100755 index 000000000..efe8cc01c --- /dev/null +++ b/test_regress/t/t_randomize_union_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_randsequence.pl b/test_regress/t/t_randsequence.pl deleted file mode 100755 index a90e02ed1..000000000 --- a/test_regress/t/t_randsequence.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - - -execute( - ) if !$Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_randsequence.py b/test_regress/t/t_randsequence.py new file mode 100755 index 000000000..966dc53da --- /dev/null +++ b/test_regress/t/t_randsequence.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) + +if not test.vlt_all: + test.execute() + +test.passes() diff --git a/test_regress/t/t_randsequence_bad.pl b/test_regress/t/t_randsequence_bad.pl deleted file mode 100755 index a083f46f5..000000000 --- a/test_regress/t/t_randsequence_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_randsequence_bad.py b/test_regress/t/t_randsequence_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_randsequence_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_randstate_func.pl b/test_regress/t/t_randstate_func.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_randstate_func.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_randstate_func.py b/test_regress/t/t_randstate_func.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_randstate_func.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randstate_obj.pl b/test_regress/t/t_randstate_obj.pl deleted file mode 100755 index b50a85167..000000000 --- a/test_regress/t/t_randstate_obj.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - expect_filename => $Self->{golden_filename}, - fails => $Self->{vlt_all}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_randstate_obj.py b/test_regress/t/t_randstate_obj.py new file mode 100755 index 000000000..710a094ab --- /dev/null +++ b/test_regress/t/t_randstate_obj.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_randstate_seed_bad.pl b/test_regress/t/t_randstate_seed_bad.pl deleted file mode 100755 index c7c7ef8ca..000000000 --- a/test_regress/t/t_randstate_seed_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_randstate_seed_bad.py b/test_regress/t/t_randstate_seed_bad.py new file mode 100755 index 000000000..97abb660e --- /dev/null +++ b/test_regress/t/t_randstate_seed_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_real_param.pl b/test_regress/t/t_real_param.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_real_param.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_real_param.py b/test_regress/t/t_real_param.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_real_param.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_recursive_method.pl b/test_regress/t/t_recursive_method.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_recursive_method.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_recursive_method.py b/test_regress/t/t_recursive_method.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_recursive_method.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_recursive_module_bug.pl b/test_regress/t/t_recursive_module_bug.pl deleted file mode 100755 index 2ef6db6a2..000000000 --- a/test_regress/t/t_recursive_module_bug.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile(); - -ok(1); -1; diff --git a/test_regress/t/t_recursive_module_bug.py b/test_regress/t/t_recursive_module_bug.py new file mode 100755 index 000000000..16de8f485 --- /dev/null +++ b/test_regress/t/t_recursive_module_bug.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_recursive_module_bug_2.pl b/test_regress/t/t_recursive_module_bug_2.pl deleted file mode 100755 index 2ef6db6a2..000000000 --- a/test_regress/t/t_recursive_module_bug_2.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile(); - -ok(1); -1; diff --git a/test_regress/t/t_recursive_module_bug_2.py b/test_regress/t/t_recursive_module_bug_2.py new file mode 100755 index 000000000..16de8f485 --- /dev/null +++ b/test_regress/t/t_recursive_module_bug_2.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_reloop_cam.pl b/test_regress/t/t_reloop_cam.pl deleted file mode 100755 index 03ab7adf6..000000000 --- a/test_regress/t/t_reloop_cam.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["-unroll-count 1024", - "--expand-limit 1024", - $Self->wno_unopthreads_for_few_cores(), - "--stats"], - ); - -execute( - ); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, Reloop iterations\s+(\d+)/, - 768); - file_grep($Self->{stats}, qr/Optimizations, Reloops\s+(\d+)/, - 3); -} - -ok(1); -1; diff --git a/test_regress/t/t_reloop_cam.py b/test_regress/t/t_reloop_cam.py new file mode 100755 index 000000000..44a025926 --- /dev/null +++ b/test_regress/t/t_reloop_cam.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=[ + "-unroll-count 1024", "--expand-limit 1024", test.wno_unopthreads_for_few_cores, "--stats" +]) + +test.execute() + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, Reloop iterations\s+(\d+)', 768) + test.file_grep(test.stats, r'Optimizations, Reloops\s+(\d+)', 3) + +test.passes() diff --git a/test_regress/t/t_reloop_local.pl b/test_regress/t/t_reloop_local.pl deleted file mode 100755 index 286b1bbc8..000000000 --- a/test_regress/t/t_reloop_local.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--assert'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_reloop_local.py b/test_regress/t/t_reloop_local.py new file mode 100755 index 000000000..2c4ffdce2 --- /dev/null +++ b/test_regress/t/t_reloop_local.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--assert']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_reloop_offset.pl b/test_regress/t/t_reloop_offset.pl deleted file mode 100755 index 4fda91784..000000000 --- a/test_regress/t/t_reloop_offset.pl +++ /dev/null @@ -1,32 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["-unroll-count 1024", - $Self->wno_unopthreads_for_few_cores(), - "--stats"], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -if ($Self->{vlt}) { - # Note, with vltmt this might be split differently, so only checking vlt - file_grep($Self->{stats}, qr/Optimizations, Reloop iterations\s+(\d+)/, - 125); - file_grep($Self->{stats}, qr/Optimizations, Reloops\s+(\d+)/, - 2); -} - -ok(1); -1; diff --git a/test_regress/t/t_reloop_offset.py b/test_regress/t/t_reloop_offset.py new file mode 100755 index 000000000..a391e447b --- /dev/null +++ b/test_regress/t/t_reloop_offset.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + verilator_flags2=["-unroll-count 1024", test.wno_unopthreads_for_few_cores, "--stats"]) + +test.execute(expect_filename=test.golden_filename) + +if test.vlt: + # Note, with vltmt this might be split differently, so only checking vlt + test.file_grep(test.stats, r'Optimizations, Reloop iterations\s+(\d+)', 125) + test.file_grep(test.stats, r'Optimizations, Reloops\s+(\d+)', 2) + +test.passes() diff --git a/test_regress/t/t_reloop_offset_lim_63.pl b/test_regress/t/t_reloop_offset_lim_63.pl deleted file mode 100755 index 535f6d934..000000000 --- a/test_regress/t/t_reloop_offset_lim_63.pl +++ /dev/null @@ -1,36 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_reloop_offset.v"); -golden_filename("t/t_reloop_offset.out"); - -compile( - verilator_flags2 => ["-unroll-count 1024", - $Self->wno_unopthreads_for_few_cores(), - "--reloop-limit 63", - "--stats"], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -if ($Self->{vlt}) { - # Note, with vltmt this might be split differently, so only checking vlt - file_grep($Self->{stats}, qr/Optimizations, Reloop iterations\s+(\d+)/, - 63); - file_grep($Self->{stats}, qr/Optimizations, Reloops\s+(\d+)/, - 1); -} - -ok(1); -1; diff --git a/test_regress/t/t_reloop_offset_lim_63.py b/test_regress/t/t_reloop_offset_lim_63.py new file mode 100755 index 000000000..9e9bd8b5f --- /dev/null +++ b/test_regress/t/t_reloop_offset_lim_63.py @@ -0,0 +1,27 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_reloop_offset.v" +test.golden_filename = "t/t_reloop_offset.out" + +test.compile(verilator_flags2=[ + "-unroll-count 1024", test.wno_unopthreads_for_few_cores, "--reloop-limit 63", "--stats" +]) + +test.execute(expect_filename=test.golden_filename) + +if test.vlt: + # Note, with vltmt this might be split differently, so only checking vlt + test.file_grep(test.stats, r'Optimizations, Reloop iterations\s+(\d+)', 63) + test.file_grep(test.stats, r'Optimizations, Reloops\s+(\d+)', 1) + +test.passes() diff --git a/test_regress/t/t_repeat.pl b/test_regress/t/t_repeat.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_repeat.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_repeat.py b/test_regress/t/t_repeat.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_repeat.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_rnd.pl b/test_regress/t/t_rnd.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_rnd.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_rnd.py b/test_regress/t/t_rnd.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_rnd.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_runflag.pl b/test_regress/t/t_runflag.pl deleted file mode 100755 index e93edce74..000000000 --- a/test_regress/t/t_runflag.pl +++ /dev/null @@ -1,45 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - ); - -execute( - all_run_flags => ["+verilator+debug +verilator+debugi+9 +verilator+rand+reset+1"], - expect => (q{.*Verilated::debug is on.*}), - ); - -execute( - all_run_flags => ["+verilator+help"], - fails => 1, - expect => ( -q{.*For help, please see 'verilator --help' -.*}), - ); - -execute( - all_run_flags => ["+verilator+V"], - fails => 1, - expect => ( -q{.*Version:}), - ); - -execute( - all_run_flags => ["+verilator+version"], - fails => 1, - expect => ( -q{.*Version:}), - ); - -ok(1); - -1; diff --git a/test_regress/t/t_runflag.py b/test_regress/t/t_runflag.py new file mode 100755 index 000000000..2ec96c029 --- /dev/null +++ b/test_regress/t/t_runflag.py @@ -0,0 +1,27 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile() + +test.execute(all_run_flags=["+verilator+debug +verilator+debugi+9 +verilator+rand+reset+1"], + expect=r'.*Verilated::debug is on.*') + +test.execute(all_run_flags=["+verilator+help"], + fails=True, + expect=r".*For help, please see 'verilator --help'.*") + +test.execute(all_run_flags=["+verilator+V"], fails=True, expect=r'.*Version:.*') + +test.execute(all_run_flags=["+verilator+version"], fails=True, expect=r'.*Version:.*') + +test.passes() diff --git a/test_regress/t/t_runflag_bad.pl b/test_regress/t/t_runflag_bad.pl deleted file mode 100755 index d96c0ccbf..000000000 --- a/test_regress/t/t_runflag_bad.pl +++ /dev/null @@ -1,48 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - ); - -execute( - all_run_flags => ["+verilator+bad+flag+testing"], - fails => 1, - expect_filename => "t/" . $Self->{name} . "_a.out", - ); - -execute( - all_run_flags => ["+verilator+rand+reset+-1"], - fails => 1, - expect_filename => "t/" . $Self->{name} . "_b.out", - ); - -execute( - all_run_flags => ["+verilator+rand+reset+3"], - fails => 1, - expect_filename => "t/" . $Self->{name} . "_c.out", - ); - -execute( - all_run_flags => ["+verilator+prof+exec+window+0"], - fails => 1, - expect_filename => "t/" . $Self->{name} . "_d.out", - ); - -execute( - all_run_flags => ["+verilator+prof+exec+window+1000000000000000000000000"], - fails => 1, - expect_filename => "t/" . $Self->{name} . "_e.out", - ); - -ok(1); - -1; diff --git a/test_regress/t/t_runflag_bad.py b/test_regress/t/t_runflag_bad.py new file mode 100755 index 000000000..fc3933b43 --- /dev/null +++ b/test_regress/t/t_runflag_bad.py @@ -0,0 +1,36 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile() + +test.execute(all_run_flags=["+verilator+bad+flag+testing"], + fails=True, + expect_filename="t/" + test.name + "_a.out") + +test.execute(all_run_flags=["+verilator+rand+reset+-1"], + fails=True, + expect_filename="t/" + test.name + "_b.out") + +test.execute(all_run_flags=["+verilator+rand+reset+3"], + fails=True, + expect_filename="t/" + test.name + "_c.out") + +test.execute(all_run_flags=["+verilator+prof+exec+window+0"], + fails=True, + expect_filename="t/" + test.name + "_d.out") + +test.execute(all_run_flags=["+verilator+prof+exec+window+1000000000000000000000000"], + fails=True, + expect_filename="t/" + test.name + "_e.out") + +test.passes() diff --git a/test_regress/t/t_runflag_errorlimit_bad.pl b/test_regress/t/t_runflag_errorlimit_bad.pl deleted file mode 100755 index 6651f9189..000000000 --- a/test_regress/t/t_runflag_errorlimit_bad.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - ); - -execute( - all_run_flags => ["+verilator+error+limit+3"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_runflag_errorlimit_bad.py b/test_regress/t/t_runflag_errorlimit_bad.py new file mode 100755 index 000000000..2370a882b --- /dev/null +++ b/test_regress/t/t_runflag_errorlimit_bad.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile() + +test.execute(all_run_flags=["+verilator+error+limit+3"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_runflag_quiet.pl b/test_regress/t/t_runflag_quiet.pl deleted file mode 100755 index cd6acaae8..000000000 --- a/test_regress/t/t_runflag_quiet.pl +++ /dev/null @@ -1,35 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - verilator_flags2 => ["--binary --quiet"], - ); - -execute( - all_run_flags => ["+verilator+quiet"], - logfile => "$Self->{obj_dir}/sim__quiet.log", - ); - -file_grep_not("$Self->{obj_dir}/sim__quiet.log", qr/S i m u l a t/); - -#--- - -execute( - all_run_flags => [""], - logfile => "$Self->{obj_dir}/sim__noquiet.log", - ); - -file_grep("$Self->{obj_dir}/sim__noquiet.log", qr/S i m u l a t/); - -ok(1); - -1; diff --git a/test_regress/t/t_runflag_quiet.py b/test_regress/t/t_runflag_quiet.py new file mode 100755 index 000000000..34c826b21 --- /dev/null +++ b/test_regress/t/t_runflag_quiet.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(verilator_flags2=["--binary --quiet"]) + +test.execute(all_run_flags=["+verilator+quiet"], logfile=test.obj_dir + "/sim__quiet.log") + +test.file_grep_not(test.obj_dir + "/sim__quiet.log", r'S i m u l a t') + +#--- + +test.execute(all_run_flags=[""], logfile=test.obj_dir + "/sim__noquiet.log") + +test.file_grep(test.obj_dir + "/sim__noquiet.log", r'S i m u l a t') + +test.passes() diff --git a/test_regress/t/t_runflag_seed.pl b/test_regress/t/t_runflag_seed.pl deleted file mode 100755 index 71a259e41..000000000 --- a/test_regress/t/t_runflag_seed.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - ); - -execute( - all_run_flags => ["+verilator+seed+5 +SEED=fffffff4"], - ); - -execute( - all_run_flags => ["+verilator+seed+6 +SEED=fffffff2"], - ); - -ok(1); - -1; diff --git a/test_regress/t/t_runflag_seed.py b/test_regress/t/t_runflag_seed.py new file mode 100755 index 000000000..836f602cd --- /dev/null +++ b/test_regress/t/t_runflag_seed.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile() + +test.execute(all_run_flags=["+verilator+seed+5 +SEED=fffffff4"]) + +test.execute(all_run_flags=["+verilator+seed+6 +SEED=fffffff2"]) + +test.passes() diff --git a/test_regress/t/t_runflag_uninit_bad.pl b/test_regress/t/t_runflag_uninit_bad.pl deleted file mode 100755 index dada1b80d..000000000 --- a/test_regress/t/t_runflag_uninit_bad.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - v_flags2 => ["--savable --exe $Self->{t_dir}/t_runflag_uninit_bad.cpp"], - make_main => 0, - ); - -execute( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_runflag_uninit_bad.py b/test_regress/t/t_runflag_uninit_bad.py new file mode 100755 index 000000000..54b3952a5 --- /dev/null +++ b/test_regress/t/t_runflag_uninit_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(v_flags2=["--savable --exe", test.pli_filename], make_main=False) + +test.execute(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_sampled_expr.pl b/test_regress/t/t_sampled_expr.pl deleted file mode 100755 index f96aad9b7..000000000 --- a/test_regress/t/t_sampled_expr.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--assert'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_sampled_expr.py b/test_regress/t/t_sampled_expr.py new file mode 100755 index 000000000..2c4ffdce2 --- /dev/null +++ b/test_regress/t/t_sampled_expr.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--assert']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_sampled_expr_unsup.pl b/test_regress/t/t_sampled_expr_unsup.pl deleted file mode 100755 index 244d49cbd..000000000 --- a/test_regress/t/t_sampled_expr_unsup.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - expect_filename=>$Self->{golden_filename}, - verilator_flags2=> ['--assert -Wno-UNSIGNED'], - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_sampled_expr_unsup.py b/test_regress/t/t_sampled_expr_unsup.py new file mode 100755 index 000000000..09fb4cfa3 --- /dev/null +++ b/test_regress/t/t_sampled_expr_unsup.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(expect_filename=test.golden_filename, + verilator_flags2=['--assert -Wno-UNSIGNED'], + fails=True) + +test.passes() diff --git a/test_regress/t/t_savable.pl b/test_regress/t/t_savable.pl deleted file mode 100755 index eeaa8181f..000000000 --- a/test_regress/t/t_savable.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["--savable"], - save_time => 500, - ); - -execute( - check_finished => 0, - all_run_flags => ['+save_time=500'], - ); - --r "$Self->{obj_dir}/saved.vltsv" or error("Saved.vltsv not created\n"); - -execute( - all_run_flags => ['+save_restore=1'], - ); - -ok(1); -1; diff --git a/test_regress/t/t_savable.py b/test_regress/t/t_savable.py new file mode 100755 index 000000000..289d8f855 --- /dev/null +++ b/test_regress/t/t_savable.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["--savable"], save_time=500) + +test.execute(check_finished=False, all_run_flags=['+save_time=500']) + +if not os.path.exists(test.obj_dir + "/saved.vltsv"): + test.error("Saved.vltsv not created") + +test.execute(all_run_flags=['+save_restore=1']) + +test.passes() diff --git a/test_regress/t/t_savable_class_bad.pl b/test_regress/t/t_savable_class_bad.pl deleted file mode 100755 index 3911aee04..000000000 --- a/test_regress/t/t_savable_class_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - v_flags2 => ["--savable"], - save_time => 500, - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_savable_class_bad.py b/test_regress/t/t_savable_class_bad.py new file mode 100755 index 000000000..9ac0fdbc6 --- /dev/null +++ b/test_regress/t/t_savable_class_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(v_flags2=["--savable"], + save_time=500, + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_savable_coverage_bad.pl b/test_regress/t/t_savable_coverage_bad.pl deleted file mode 100755 index cb1123397..000000000 --- a/test_regress/t/t_savable_coverage_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - v_flags2 => ["--savable --coverage"], - save_time => 500, - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_savable_coverage_bad.py b/test_regress/t/t_savable_coverage_bad.py new file mode 100755 index 000000000..15eec4d60 --- /dev/null +++ b/test_regress/t/t_savable_coverage_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(v_flags2=["--savable --coverage"], + save_time=500, + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_savable_format1_bad.pl b/test_regress/t/t_savable_format1_bad.pl deleted file mode 100755 index 0731b7fe1..000000000 --- a/test_regress/t/t_savable_format1_bad.pl +++ /dev/null @@ -1,40 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_savable.v"); - -compile( - v_flags2 => ["--savable"], - save_time => 500, - ); - -execute( - check_finished => 0, - all_run_flags => ['+save_time=500'], - ); - --r "$Self->{obj_dir}/saved.vltsv" or error("Saved.vltsv not created\n"); -sleep(1); # Avoid make getting confused by very fast build - -compile( - v_flags2 => ["--savable -GMODEL_WIDTH=40"], - save_time => 500, - ); - -execute( - all_run_flags => ['+save_restore=1'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_savable_format1_bad.py b/test_regress/t/t_savable_format1_bad.py new file mode 100755 index 000000000..6965c4a35 --- /dev/null +++ b/test_regress/t/t_savable_format1_bad.py @@ -0,0 +1,30 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import time + +test.scenarios('vlt') +test.top_filename = "t/t_savable.v" + +test.compile(v_flags2=["--savable"], save_time=500) + +test.execute(check_finished=False, all_run_flags=['+save_time=500']) + +if not os.path.exists(test.obj_dir + "/saved.vltsv"): + test.error("Saved.vltsv not created") + +time.sleep(1) +# Avoid make getting confused by very fast build + +test.compile(v_flags2=["--savable -GMODEL_WIDTH=40"], save_time=500) + +test.execute(all_run_flags=['+save_restore=1'], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_savable_format2_bad.pl b/test_regress/t/t_savable_format2_bad.pl deleted file mode 100755 index ee0a4d518..000000000 --- a/test_regress/t/t_savable_format2_bad.pl +++ /dev/null @@ -1,39 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_savable.v"); - -compile( - v_flags2 => ["--savable"], - save_time => 500, - ); - -execute( - check_finished => 0, - all_run_flags => ['+save_time=500'], - ); - --r "$Self->{obj_dir}/saved.vltsv" or error("Saved.vltsv not created\n"); - -# Break the header -file_sed("$Self->{obj_dir}/saved.vltsv", - "$Self->{obj_dir}/saved.vltsv", - sub { s/verilatorsave/verilatorsavBAD/g; }); - -execute( - all_run_flags => ['+save_restore=1'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_savable_format2_bad.py b/test_regress/t/t_savable_format2_bad.py new file mode 100755 index 000000000..8940d15ca --- /dev/null +++ b/test_regress/t/t_savable_format2_bad.py @@ -0,0 +1,28 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_savable.v" + +test.compile(v_flags2=["--savable"], save_time=500) + +test.execute(check_finished=False, all_run_flags=['+save_time=500']) + +if not os.path.exists(test.obj_dir + "/saved.vltsv"): + test.error("Saved.vltsv not created") + +# Break the header +test.file_sed(test.obj_dir + "/saved.vltsv", test.obj_dir + "/saved.vltsv", + lambda line: re.sub(r'verilatorsave', 'verilatorsavBAD', line)) + +test.execute(all_run_flags=['+save_restore=1'], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_savable_format3_bad.pl b/test_regress/t/t_savable_format3_bad.pl deleted file mode 100755 index ce78e55f1..000000000 --- a/test_regress/t/t_savable_format3_bad.pl +++ /dev/null @@ -1,39 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_savable.v"); - -compile( - v_flags2 => ["--savable"], - save_time => 500, - ); - -execute( - check_finished => 0, - all_run_flags => ['+save_time=500'], - ); - --r "$Self->{obj_dir}/saved.vltsv" or error("Saved.vltsv not created\n"); - -# Break the header -file_sed("$Self->{obj_dir}/saved.vltsv", - "$Self->{obj_dir}/saved.vltsv", - sub { s/vltsaved/vltNOTed/g; }); - -execute( - all_run_flags => ['+save_restore=1'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_savable_format3_bad.py b/test_regress/t/t_savable_format3_bad.py new file mode 100755 index 000000000..cadd098c2 --- /dev/null +++ b/test_regress/t/t_savable_format3_bad.py @@ -0,0 +1,28 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_savable.v" + +test.compile(v_flags2=["--savable"], save_time=500) + +test.execute(check_finished=False, all_run_flags=['+save_time=500']) + +if not os.path.exists(test.obj_dir + "/saved.vltsv"): + test.error("saved.vltsv not created") + +# Break the header +test.file_sed(test.obj_dir + "/saved.vltsv", test.obj_dir + "/saved.vltsv", + lambda line: re.sub(r'vltsaved', 'vltNOTed', line)) + +test.execute(all_run_flags=['+save_restore=1'], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_savable_open_bad.pl b/test_regress/t/t_savable_open_bad.pl deleted file mode 100755 index a2160366f..000000000 --- a/test_regress/t/t_savable_open_bad.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_savable.v"); - -compile( - v_flags2 => ["--savable"], - save_time => 500, - ); - -execute( - all_run_flags => ['+save_restore=1'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_savable_open_bad.py b/test_regress/t/t_savable_open_bad.py new file mode 100755 index 000000000..b7a64c02d --- /dev/null +++ b/test_regress/t/t_savable_open_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_savable.v" + +test.compile(v_flags2=["--savable"], save_time=500) + +test.execute(all_run_flags=['+save_restore=1'], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_savable_open_bad2.pl b/test_regress/t/t_savable_open_bad2.pl deleted file mode 100755 index 445737f1a..000000000 --- a/test_regress/t/t_savable_open_bad2.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - v_flags2 => ["--savable --exe $Self->{t_dir}/t_savable_open_bad2.cpp"], - make_main => 0, - ); - -execute( - check_finished => 0, - ); - -ok(1); -1; diff --git a/test_regress/t/t_savable_open_bad2.py b/test_regress/t/t_savable_open_bad2.py new file mode 100755 index 000000000..3a759f54f --- /dev/null +++ b/test_regress/t/t_savable_open_bad2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(v_flags2=["--savable --exe", test.pli_filename], make_main=False) + +test.execute(check_finished=False) + +test.passes() diff --git a/test_regress/t/t_sc_names.pl b/test_regress/t/t_sc_names.pl deleted file mode 100755 index 90c113b6f..000000000 --- a/test_regress/t/t_sc_names.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_sc) { - skip("No SystemC installed"); -} -else { - compile( - make_main => 0, - verilator_flags2 => ["-sc --exe $Self->{t_dir}/$Self->{name}.cpp"], - ); - - execute( - ); -} - -ok(1); -1; diff --git a/test_regress/t/t_sc_names.py b/test_regress/t/t_sc_names.py new file mode 100755 index 000000000..c891a1ee0 --- /dev/null +++ b/test_regress/t/t_sc_names.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_sc: + test.skip("No SystemC installed") + +test.compile(make_main=False, verilator_flags2=["-sc --exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_scheduling_0.pl b/test_regress/t/t_scheduling_0.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_scheduling_0.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_scheduling_0.py b/test_regress/t/t_scheduling_0.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_scheduling_0.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_scheduling_1.pl b/test_regress/t/t_scheduling_1.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_scheduling_1.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_scheduling_1.py b/test_regress/t/t_scheduling_1.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_scheduling_1.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_scheduling_2.pl b/test_regress/t/t_scheduling_2.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_scheduling_2.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_scheduling_2.py b/test_regress/t/t_scheduling_2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_scheduling_2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_scheduling_3.pl b/test_regress/t/t_scheduling_3.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_scheduling_3.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_scheduling_3.py b/test_regress/t/t_scheduling_3.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_scheduling_3.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_scheduling_4.pl b/test_regress/t/t_scheduling_4.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_scheduling_4.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_scheduling_4.py b/test_regress/t/t_scheduling_4.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_scheduling_4.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_scheduling_5.pl b/test_regress/t/t_scheduling_5.pl deleted file mode 100755 index 2f4e2067e..000000000 --- a/test_regress/t/t_scheduling_5.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["-Wno-MULTIDRIVEN"] - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_scheduling_5.py b/test_regress/t/t_scheduling_5.py new file mode 100755 index 000000000..b80b4f79f --- /dev/null +++ b/test_regress/t/t_scheduling_5.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["-Wno-MULTIDRIVEN"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_scope_map.pl b/test_regress/t/t_scope_map.pl deleted file mode 100755 index 25b773a45..000000000 --- a/test_regress/t/t_scope_map.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2015 by Todd Strader. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ["--trace --exe $Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_scope_map.py b/test_regress/t/t_scope_map.py new file mode 100755 index 000000000..ec6142999 --- /dev/null +++ b/test_regress/t/t_scope_map.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_top_shell=False, make_main=False, v_flags2=["--trace --exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_select_2d.pl b/test_regress/t/t_select_2d.pl deleted file mode 100755 index 6e1338f8e..000000000 --- a/test_regress/t/t_select_2d.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_2d.py b/test_regress/t/t_select_2d.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_select_2d.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_select_ascending.pl b/test_regress/t/t_select_ascending.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_select_ascending.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_ascending.py b/test_regress/t/t_select_ascending.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_select_ascending.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_select_bad_msb.pl b/test_regress/t/t_select_bad_msb.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_select_bad_msb.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_bad_msb.py b/test_regress/t/t_select_bad_msb.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_select_bad_msb.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_select_bad_range.pl b/test_regress/t/t_select_bad_range.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_select_bad_range.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_bad_range.py b/test_regress/t/t_select_bad_range.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_select_bad_range.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_select_bad_range2.pl b/test_regress/t/t_select_bad_range2.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_select_bad_range2.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_bad_range2.py b/test_regress/t/t_select_bad_range2.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_select_bad_range2.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_select_bad_range3.pl b/test_regress/t/t_select_bad_range3.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_select_bad_range3.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_bad_range3.py b/test_regress/t/t_select_bad_range3.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_select_bad_range3.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_select_bad_range4.pl b/test_regress/t/t_select_bad_range4.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_select_bad_range4.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_bad_range4.py b/test_regress/t/t_select_bad_range4.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_select_bad_range4.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_select_bad_range5.pl b/test_regress/t/t_select_bad_range5.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_select_bad_range5.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_bad_range5.py b/test_regress/t/t_select_bad_range5.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_select_bad_range5.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_select_bad_range6.pl b/test_regress/t/t_select_bad_range6.pl deleted file mode 100755 index 18791b049..000000000 --- a/test_regress/t/t_select_bad_range6.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_bad_range6.py b/test_regress/t/t_select_bad_range6.py new file mode 100755 index 000000000..a6f7c2c22 --- /dev/null +++ b/test_regress/t/t_select_bad_range6.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_select_bad_tri.pl b/test_regress/t/t_select_bad_tri.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_select_bad_tri.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_bad_tri.py b/test_regress/t/t_select_bad_tri.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_select_bad_tri.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_select_bad_width0.pl b/test_regress/t/t_select_bad_width0.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_select_bad_width0.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_bad_width0.py b/test_regress/t/t_select_bad_width0.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_select_bad_width0.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_select_bound1.pl b/test_regress/t/t_select_bound1.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_select_bound1.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_bound1.py b/test_regress/t/t_select_bound1.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_select_bound1.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_select_bound2.pl b/test_regress/t/t_select_bound2.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_select_bound2.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_bound2.py b/test_regress/t/t_select_bound2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_select_bound2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_select_crazy.pl b/test_regress/t/t_select_crazy.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_select_crazy.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_crazy.py b/test_regress/t/t_select_crazy.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_select_crazy.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_select_index.pl b/test_regress/t/t_select_index.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_select_index.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_index.py b/test_regress/t/t_select_index.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_select_index.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_select_index2.pl b/test_regress/t/t_select_index2.pl deleted file mode 100755 index 13c6e2b71..000000000 --- a/test_regress/t/t_select_index2.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_select_index2.py b/test_regress/t/t_select_index2.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_select_index2.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_select_lhs_oob.pl b/test_regress/t/t_select_lhs_oob.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_select_lhs_oob.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_lhs_oob.py b/test_regress/t/t_select_lhs_oob.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_select_lhs_oob.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_select_lhs_oob2.pl b/test_regress/t/t_select_lhs_oob2.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_select_lhs_oob2.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_lhs_oob2.py b/test_regress/t/t_select_lhs_oob2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_select_lhs_oob2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_select_little.pl b/test_regress/t/t_select_little.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_select_little.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_little.py b/test_regress/t/t_select_little.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_select_little.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_select_little_pack.pl b/test_regress/t/t_select_little_pack.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_select_little_pack.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_little_pack.py b/test_regress/t/t_select_little_pack.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_select_little_pack.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_select_loop.pl b/test_regress/t/t_select_loop.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_select_loop.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_loop.py b/test_regress/t/t_select_loop.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_select_loop.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_select_mul_extend.pl b/test_regress/t/t_select_mul_extend.pl deleted file mode 100755 index 3708008f8..000000000 --- a/test_regress/t/t_select_mul_extend.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_mul_extend.py b/test_regress/t/t_select_mul_extend.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_select_mul_extend.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_select_negative.pl b/test_regress/t/t_select_negative.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_select_negative.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_negative.py b/test_regress/t/t_select_negative.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_select_negative.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_select_param.pl b/test_regress/t/t_select_param.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_select_param.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_param.py b/test_regress/t/t_select_param.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_select_param.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_select_plus.pl b/test_regress/t/t_select_plus.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_select_plus.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_plus.py b/test_regress/t/t_select_plus.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_select_plus.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_select_plus_mul_pow2.pl b/test_regress/t/t_select_plus_mul_pow2.pl deleted file mode 100755 index 56363dab6..000000000 --- a/test_regress/t/t_select_plus_mul_pow2.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_plus_mul_pow2.py b/test_regress/t/t_select_plus_mul_pow2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_select_plus_mul_pow2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_select_plusloop.pl b/test_regress/t/t_select_plusloop.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_select_plusloop.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_plusloop.py b/test_regress/t/t_select_plusloop.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_select_plusloop.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_select_runtime_range.pl b/test_regress/t/t_select_runtime_range.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_select_runtime_range.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_runtime_range.py b/test_regress/t/t_select_runtime_range.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_select_runtime_range.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_select_set.pl b/test_regress/t/t_select_set.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_select_set.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_set.py b/test_regress/t/t_select_set.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_select_set.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_select_width.pl b/test_regress/t/t_select_width.pl deleted file mode 100755 index 09b2ce4eb..000000000 --- a/test_regress/t/t_select_width.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - ); - -ok(1); -1; diff --git a/test_regress/t/t_select_width.py b/test_regress/t/t_select_width.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_select_width.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_selextract_in_paramextends.pl b/test_regress/t/t_selextract_in_paramextends.pl deleted file mode 100755 index a8264f47b..000000000 --- a/test_regress/t/t_selextract_in_paramextends.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--binary --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_selextract_in_paramextends.py b/test_regress/t/t_selextract_in_paramextends.py new file mode 100755 index 000000000..7bd93561b --- /dev/null +++ b/test_regress/t/t_selextract_in_paramextends.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_semaphore.pl b/test_regress/t/t_semaphore.pl deleted file mode 100755 index 860c9a749..000000000 --- a/test_regress/t/t_semaphore.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing -Wall"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_semaphore.py b/test_regress/t/t_semaphore.py new file mode 100755 index 000000000..e84a7d7e7 --- /dev/null +++ b/test_regress/t/t_semaphore.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing -Wall"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_semaphore_always.pl b/test_regress/t/t_semaphore_always.pl deleted file mode 100755 index 55432b280..000000000 --- a/test_regress/t/t_semaphore_always.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_semaphore_always.py b/test_regress/t/t_semaphore_always.py new file mode 100755 index 000000000..34b0247e9 --- /dev/null +++ b/test_regress/t/t_semaphore_always.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_semaphore_bad.pl b/test_regress/t/t_semaphore_bad.pl deleted file mode 100755 index a083f46f5..000000000 --- a/test_regress/t/t_semaphore_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_semaphore_bad.py b/test_regress/t/t_semaphore_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_semaphore_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_semaphore_class.pl b/test_regress/t/t_semaphore_class.pl deleted file mode 100755 index 91589388d..000000000 --- a/test_regress/t/t_semaphore_class.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--binary --timing"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_semaphore_class.py b/test_regress/t/t_semaphore_class.py new file mode 100755 index 000000000..bbbcfc078 --- /dev/null +++ b/test_regress/t/t_semaphore_class.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary --timing"]) + +test.passes() diff --git a/test_regress/t/t_semaphore_concurrent.pl b/test_regress/t/t_semaphore_concurrent.pl deleted file mode 100755 index 27000793f..000000000 --- a/test_regress/t/t_semaphore_concurrent.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Liam Braun and Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--binary --timing"] - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_semaphore_concurrent.py b/test_regress/t/t_semaphore_concurrent.py new file mode 100755 index 000000000..a74b0c7ec --- /dev/null +++ b/test_regress/t/t_semaphore_concurrent.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary --timing"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_semaphore_std.pl b/test_regress/t/t_semaphore_std.pl deleted file mode 100755 index 6863d1f93..000000000 --- a/test_regress/t/t_semaphore_std.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_semaphore.v"); - -compile( - verilator_flags2 => ["--exe --main --timing -Wall -DSEMAPHORE_T=std::semaphore"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_semaphore_std.py b/test_regress/t/t_semaphore_std.py new file mode 100755 index 000000000..1b61c0548 --- /dev/null +++ b/test_regress/t/t_semaphore_std.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_semaphore.v" + +test.compile(verilator_flags2=["--exe --main --timing -Wall -DSEMAPHORE_T=std::semaphore"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_sequence_sexpr_unsup.pl b/test_regress/t/t_sequence_sexpr_unsup.pl deleted file mode 100755 index 7284ec30e..000000000 --- a/test_regress/t/t_sequence_sexpr_unsup.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - expect_filename => $Self->{golden_filename}, - verilator_flags2 => ['--assert --error-limit 1000'], - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_sequence_sexpr_unsup.py b/test_regress/t/t_sequence_sexpr_unsup.py new file mode 100755 index 000000000..25f9960b8 --- /dev/null +++ b/test_regress/t/t_sequence_sexpr_unsup.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(expect_filename=test.golden_filename, + verilator_flags2=['--assert --error-limit 1000'], + fails=True) + +test.passes() diff --git a/test_regress/t/t_slice_cmp.pl b/test_regress/t/t_slice_cmp.pl deleted file mode 100755 index 6e1338f8e..000000000 --- a/test_regress/t/t_slice_cmp.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_slice_cmp.py b/test_regress/t/t_slice_cmp.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_slice_cmp.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_slice_cond.pl b/test_regress/t/t_slice_cond.pl deleted file mode 100755 index 552bd97db..000000000 --- a/test_regress/t/t_slice_cond.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_slice_cond.py b/test_regress/t/t_slice_cond.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_slice_cond.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_slice_init.pl b/test_regress/t/t_slice_init.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_slice_init.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_slice_init.py b/test_regress/t/t_slice_init.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_slice_init.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_slice_struct_array_modport.pl b/test_regress/t/t_slice_struct_array_modport.pl deleted file mode 100755 index 13c6e2b71..000000000 --- a/test_regress/t/t_slice_struct_array_modport.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_slice_struct_array_modport.py b/test_regress/t/t_slice_struct_array_modport.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_slice_struct_array_modport.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_source_sync.pl b/test_regress/t/t_source_sync.pl deleted file mode 100755 index 63947fd00..000000000 --- a/test_regress/t/t_source_sync.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_source_sync.py b/test_regress/t/t_source_sync.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_source_sync.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_split_var_0.pl b/test_regress/t/t_split_var_0.pl deleted file mode 100755 index 6b89bd7c3..000000000 --- a/test_regress/t/t_split_var_0.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. -# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. -# So use 6 threads here though it's not optimal in performance, but ok. -compile( - verilator_flags2 => ['--stats', "$Self->{t_dir}/t_split_var_0.vlt"], - threads => $Self->{vltmt} ? 6 : 1 - ); - -execute( - ); - -file_grep($Self->{stats}, qr/SplitVar,\s+Split packed variables\s+(\d+)/, 13); -file_grep($Self->{stats}, qr/SplitVar,\s+Split unpacked arrays\s+(\d+)/, 27); -ok(1); -1; diff --git a/test_regress/t/t_split_var_0.py b/test_regress/t/t_split_var_0.py new file mode 100755 index 000000000..552901963 --- /dev/null +++ b/test_regress/t/t_split_var_0.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. +# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. +# So use 6 threads here though it's not optimal in performance, but ok. +test.compile(verilator_flags2=['--stats', test.t_dir + "/t_split_var_0.vlt"], + threads=(6 if test.vltmt else 1)) + +test.execute() + +test.file_grep(test.stats, r'SplitVar,\s+Split packed variables\s+(\d+)', 13) +test.file_grep(test.stats, r'SplitVar,\s+Split unpacked arrays\s+(\d+)', 27) +test.passes() diff --git a/test_regress/t/t_split_var_1_bad.pl b/test_regress/t/t_split_var_1_bad.pl deleted file mode 100755 index 256bd9bc6..000000000 --- a/test_regress/t/t_split_var_1_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - verilator_flags2 => ['--stats'], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_split_var_1_bad.py b/test_regress/t/t_split_var_1_bad.py new file mode 100755 index 000000000..699eafaf5 --- /dev/null +++ b/test_regress/t/t_split_var_1_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, verilator_flags2=['--stats'], expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_split_var_2_trace.pl b/test_regress/t/t_split_var_2_trace.pl deleted file mode 100755 index 0e6afe8b4..000000000 --- a/test_regress/t/t_split_var_2_trace.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); -top_filename("t/t_split_var_0.v"); - -# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. -# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. -# So use 6 threads here though it's not optimal in performance, but ok. -compile( - verilator_flags2 => ['--cc --trace --stats +define+TEST_ATTRIBUTES'], - threads => $Self->{vltmt} ? 6 : 1 - ); - -execute( - ); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); -file_grep($Self->{stats}, qr/SplitVar,\s+Split packed variables\s+(\d+)/, 12); -file_grep($Self->{stats}, qr/SplitVar,\s+Split unpacked arrays\s+(\d+)/, 27); - -ok(1); -1; diff --git a/test_regress/t/t_split_var_2_trace.py b/test_regress/t/t_split_var_2_trace.py new file mode 100755 index 000000000..0c529d123 --- /dev/null +++ b/test_regress/t/t_split_var_2_trace.py @@ -0,0 +1,27 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_split_var_0.v" + +# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. +# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. +# So use 6 threads here though it's not optimal in performance, but ok. +test.compile(verilator_flags2=['--cc --trace --stats +define+TEST_ATTRIBUTES'], + threads=(6 if test.vltmt else 1)) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) +test.file_grep(test.stats, r'SplitVar,\s+Split packed variables\s+(\d+)', 12) +test.file_grep(test.stats, r'SplitVar,\s+Split unpacked arrays\s+(\d+)', 27) + +test.passes() diff --git a/test_regress/t/t_split_var_3_wreal.pl b/test_regress/t/t_split_var_3_wreal.pl deleted file mode 100755 index bfc48f7d0..000000000 --- a/test_regress/t/t_split_var_3_wreal.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--stats'], - ); - -execute( - ); - -file_grep($Self->{stats}, qr/SplitVar,\s+Split packed variables\s+(\d+)/, 0); -file_grep($Self->{stats}, qr/SplitVar,\s+Split unpacked arrays\s+(\d+)/, 3); -ok(1); -1; diff --git a/test_regress/t/t_split_var_3_wreal.py b/test_regress/t/t_split_var_3_wreal.py new file mode 100755 index 000000000..ad0e1af0e --- /dev/null +++ b/test_regress/t/t_split_var_3_wreal.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--stats']) + +test.execute() + +test.file_grep(test.stats, r'SplitVar,\s+Split packed variables\s+(\d+)', 0) +test.file_grep(test.stats, r'SplitVar,\s+Split unpacked arrays\s+(\d+)', 3) + +test.passes() diff --git a/test_regress/t/t_split_var_4.pl b/test_regress/t/t_split_var_4.pl deleted file mode 100755 index cb683da73..000000000 --- a/test_regress/t/t_split_var_4.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--stats', '-DENABLE_SPLIT_VAR=1'], - ); - -execute( - ); - -file_grep($Self->{stats}, qr/SplitVar,\s+Split packed variables\s+(\d+)/, 1); -file_grep($Self->{stats}, qr/SplitVar,\s+Split unpacked arrays\s+(\d+)/, 0); -ok(1); -1; diff --git a/test_regress/t/t_split_var_4.py b/test_regress/t/t_split_var_4.py new file mode 100755 index 000000000..60672ac88 --- /dev/null +++ b/test_regress/t/t_split_var_4.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--stats', '-DENABLE_SPLIT_VAR=1']) + +test.execute() + +test.file_grep(test.stats, r'SplitVar,\s+Split packed variables\s+(\d+)', 1) +test.file_grep(test.stats, r'SplitVar,\s+Split unpacked arrays\s+(\d+)', 0) + +test.passes() diff --git a/test_regress/t/t_split_var_5.pl b/test_regress/t/t_split_var_5.pl deleted file mode 100755 index 6b5464499..000000000 --- a/test_regress/t/t_split_var_5.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); -top_filename("t/t_split_var_4.v"); - -compile( - verilator_flags2 => ['--stats'] - ); - -execute( - ); - -file_grep($Self->{stats}, qr/SplitVar,\s+Split packed variables\s+(\d+)/, 0); -file_grep($Self->{stats}, qr/SplitVar,\s+Split unpacked arrays\s+(\d+)/, 0); -ok(1); -1; diff --git a/test_regress/t/t_split_var_5.py b/test_regress/t/t_split_var_5.py new file mode 100755 index 000000000..2e70a4379 --- /dev/null +++ b/test_regress/t/t_split_var_5.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_split_var_4.v" + +test.compile(verilator_flags2=['--stats']) + +test.execute() + +test.file_grep(test.stats, r'SplitVar,\s+Split packed variables\s+(\d+)', 0) +test.file_grep(test.stats, r'SplitVar,\s+Split unpacked arrays\s+(\d+)', 0) + +test.passes() diff --git a/test_regress/t/t_srandom_class_dep.pl b/test_regress/t/t_srandom_class_dep.pl deleted file mode 100755 index c74d44be5..000000000 --- a/test_regress/t/t_srandom_class_dep.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile(); - -ok(1); -1; diff --git a/test_regress/t/t_srandom_class_dep.py b/test_regress/t/t_srandom_class_dep.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_srandom_class_dep.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_stack_check.pl b/test_regress/t/t_stack_check.pl deleted file mode 100755 index 2cf86f001..000000000 --- a/test_regress/t/t_stack_check.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ['--binary --debug-stack-check'], - ); - -execute(); - -ok(1); -1; diff --git a/test_regress/t/t_stack_check.py b/test_regress/t/t_stack_check.py new file mode 100755 index 000000000..34009ba06 --- /dev/null +++ b/test_regress/t/t_stack_check.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['--binary --debug-stack-check']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_stack_check_fail.pl b/test_regress/t/t_stack_check_fail.pl deleted file mode 100755 index a2ef01d76..000000000 --- a/test_regress/t/t_stack_check_fail.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -top_filename("t/t_stack_check.v"); - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ['--binary --debug-stack-check', '--CFLAGS', '"-D_VL_TEST_RLIMIT_FAIL"'], - ); - -execute(); - -file_grep($Self->{run_log_filename}, qr/.*%Warning: System has stack size/); -ok(1); -1; diff --git a/test_regress/t/t_stack_check_fail.py b/test_regress/t/t_stack_check_fail.py new file mode 100755 index 000000000..fee5f470b --- /dev/null +++ b/test_regress/t/t_stack_check_fail.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_stack_check.v" + +test.compile( + verilator_flags2=['--binary --debug-stack-check', '--CFLAGS', '"-D_VL_TEST_RLIMIT_FAIL"']) + +test.execute() + +test.file_grep(test.run_log_filename, r'.*%Warning: System has stack size') +test.passes() diff --git a/test_regress/t/t_stacktrace.pl b/test_regress/t/t_stacktrace.pl deleted file mode 100755 index 9a67c9c44..000000000 --- a/test_regress/t/t_stacktrace.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); - -1; diff --git a/test_regress/t/t_stacktrace.py b/test_regress/t/t_stacktrace.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_stacktrace.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_static_dup_name.pl b/test_regress/t/t_static_dup_name.pl deleted file mode 100755 index 037482f42..000000000 --- a/test_regress/t/t_static_dup_name.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -$Self->{verilated_randReset} = 1; - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_static_dup_name.py b/test_regress/t/t_static_dup_name.py new file mode 100755 index 000000000..629441927 --- /dev/null +++ b/test_regress/t/t_static_dup_name.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.verilated_randReset = 1 + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_static_elab.pl b/test_regress/t/t_static_elab.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_static_elab.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_static_elab.py b/test_regress/t/t_static_elab.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_static_elab.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_static_function_in_class.pl b/test_regress/t/t_static_function_in_class.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_static_function_in_class.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_static_function_in_class.py b/test_regress/t/t_static_function_in_class.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_static_function_in_class.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_static_function_in_class_call_without_parentheses.pl b/test_regress/t/t_static_function_in_class_call_without_parentheses.pl deleted file mode 100755 index e22e7f5d9..000000000 --- a/test_regress/t/t_static_function_in_class_call_without_parentheses.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_static_function_in_class_call_without_parentheses.py b/test_regress/t/t_static_function_in_class_call_without_parentheses.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_static_function_in_class_call_without_parentheses.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_static_in_loop_unsup.pl b/test_regress/t/t_static_in_loop_unsup.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_static_in_loop_unsup.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_static_in_loop_unsup.py b/test_regress/t/t_static_in_loop_unsup.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_static_in_loop_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_std_identifier_bad.pl b/test_regress/t/t_std_identifier_bad.pl deleted file mode 100755 index 3e2acea9f..000000000 --- a/test_regress/t/t_std_identifier_bad.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -lint( - verilator_flags2 => ["-DTEST_DECLARE_STD"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_std_identifier_bad.py b/test_regress/t/t_std_identifier_bad.py new file mode 100755 index 000000000..afd26c0f2 --- /dev/null +++ b/test_regress/t/t_std_identifier_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.lint(verilator_flags2=["-DTEST_DECLARE_STD"]) + +test.passes() diff --git a/test_regress/t/t_std_pkg_bad.pl b/test_regress/t/t_std_pkg_bad.pl deleted file mode 100755 index 44783b1f6..000000000 --- a/test_regress/t/t_std_pkg_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_std_pkg_bad.py b/test_regress/t/t_std_pkg_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_std_pkg_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_std_process_self.pl b/test_regress/t/t_std_process_self.pl deleted file mode 100755 index 80841859b..000000000 --- a/test_regress/t/t_std_process_self.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint( - verilator_flags2 => ["--exe --main --timing"], - ); - -lint( - verilator_flags2 => ["--exe --main --timing --DUSE_STD_PREFIX"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_std_process_self.py b/test_regress/t/t_std_process_self.py new file mode 100755 index 000000000..3cb02e323 --- /dev/null +++ b/test_regress/t/t_std_process_self.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(verilator_flags2=["--exe --main --timing"]) + +test.lint(verilator_flags2=["--exe --main --timing --DUSE_STD_PREFIX"]) + +test.passes() diff --git a/test_regress/t/t_std_randomize_unsup_bad.pl b/test_regress/t/t_std_randomize_unsup_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_std_randomize_unsup_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_std_randomize_unsup_bad.py b/test_regress/t/t_std_randomize_unsup_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_std_randomize_unsup_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_stmt_incr_unsup.pl b/test_regress/t/t_stmt_incr_unsup.pl deleted file mode 100755 index 35d749208..000000000 --- a/test_regress/t/t_stmt_incr_unsup.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_stmt_incr_unsup.py b/test_regress/t/t_stmt_incr_unsup.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_stmt_incr_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_stop_bad.pl b/test_regress/t/t_stop_bad.pl deleted file mode 100755 index 9ec2a9c52..000000000 --- a/test_regress/t/t_stop_bad.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_stop_bad.py b/test_regress/t/t_stop_bad.py new file mode 100755 index 000000000..2fdd6e92d --- /dev/null +++ b/test_regress/t/t_stop_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_stream.pl b/test_regress/t/t_stream.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_stream.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_stream.py b/test_regress/t/t_stream.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_stream.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_stream2.pl b/test_regress/t/t_stream2.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_stream2.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_stream2.py b/test_regress/t/t_stream2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_stream2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_stream3.pl b/test_regress/t/t_stream3.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_stream3.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_stream3.py b/test_regress/t/t_stream3.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_stream3.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_stream4.pl b/test_regress/t/t_stream4.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_stream4.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_stream4.py b/test_regress/t/t_stream4.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_stream4.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_stream5.pl b/test_regress/t/t_stream5.pl deleted file mode 100755 index 21a2189cc..000000000 --- a/test_regress/t/t_stream5.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_stream5.py b/test_regress/t/t_stream5.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_stream5.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_stream_bad.pl b/test_regress/t/t_stream_bad.pl deleted file mode 100755 index a29ead0ed..000000000 --- a/test_regress/t/t_stream_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_stream_bad.py b/test_regress/t/t_stream_bad.py new file mode 100755 index 000000000..efe8cc01c --- /dev/null +++ b/test_regress/t/t_stream_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_stream_dynamic.pl b/test_regress/t/t_stream_dynamic.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_stream_dynamic.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_stream_dynamic.py b/test_regress/t/t_stream_dynamic.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_stream_dynamic.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_stream_integer_type.pl b/test_regress/t/t_stream_integer_type.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_stream_integer_type.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_stream_integer_type.py b/test_regress/t/t_stream_integer_type.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_stream_integer_type.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_stream_string_array.pl b/test_regress/t/t_stream_string_array.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_stream_string_array.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_stream_string_array.py b/test_regress/t/t_stream_string_array.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_stream_string_array.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_stream_struct.pl b/test_regress/t/t_stream_struct.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_stream_struct.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_stream_struct.py b/test_regress/t/t_stream_struct.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_stream_struct.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_stream_unpack.pl b/test_regress/t/t_stream_unpack.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_stream_unpack.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_stream_unpack.py b/test_regress/t/t_stream_unpack.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_stream_unpack.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_stream_unpack_lhs.pl b/test_regress/t/t_stream_unpack_lhs.pl deleted file mode 100755 index f486bc76e..000000000 --- a/test_regress/t/t_stream_unpack_lhs.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -execute( - ) if !$Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_stream_unpack_lhs.py b/test_regress/t/t_stream_unpack_lhs.py new file mode 100755 index 000000000..7b6840f68 --- /dev/null +++ b/test_regress/t/t_stream_unpack_lhs.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) + +if not test.vlt_all: + test.execute() + +test.passes() diff --git a/test_regress/t/t_stream_unpack_narrower.pl b/test_regress/t/t_stream_unpack_narrower.pl deleted file mode 100755 index a29ead0ed..000000000 --- a/test_regress/t/t_stream_unpack_narrower.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_stream_unpack_narrower.py b/test_regress/t/t_stream_unpack_narrower.py new file mode 100755 index 000000000..efe8cc01c --- /dev/null +++ b/test_regress/t/t_stream_unpack_narrower.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_stream_unpack_wider.pl b/test_regress/t/t_stream_unpack_wider.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_stream_unpack_wider.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_stream_unpack_wider.py b/test_regress/t/t_stream_unpack_wider.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_stream_unpack_wider.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_strength_2_uneq_assign.pl b/test_regress/t/t_strength_2_uneq_assign.pl deleted file mode 100755 index 44783b1f6..000000000 --- a/test_regress/t/t_strength_2_uneq_assign.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_strength_2_uneq_assign.py b/test_regress/t/t_strength_2_uneq_assign.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_strength_2_uneq_assign.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_strength_assignments_constants.pl b/test_regress/t/t_strength_assignments_constants.pl deleted file mode 100755 index 401463aa7..000000000 --- a/test_regress/t/t_strength_assignments_constants.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -lint( - verilator_flags2 => ["--language 1364-2005"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_strength_assignments_constants.py b/test_regress/t/t_strength_assignments_constants.py new file mode 100755 index 000000000..c30c310ba --- /dev/null +++ b/test_regress/t/t_strength_assignments_constants.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.lint(verilator_flags2=["--language 1364-2005"]) + +test.passes() diff --git a/test_regress/t/t_strength_bufif1.pl b/test_regress/t/t_strength_bufif1.pl deleted file mode 100755 index 52f7cc53a..000000000 --- a/test_regress/t/t_strength_bufif1.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_strength_bufif1.py b/test_regress/t/t_strength_bufif1.py new file mode 100755 index 000000000..6585af685 --- /dev/null +++ b/test_regress/t/t_strength_bufif1.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_strength_equal_strength.pl b/test_regress/t/t_strength_equal_strength.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_strength_equal_strength.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_strength_equal_strength.py b/test_regress/t/t_strength_equal_strength.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_strength_equal_strength.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_strength_highz.pl b/test_regress/t/t_strength_highz.pl deleted file mode 100755 index 6537d741c..000000000 --- a/test_regress/t/t_strength_highz.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--language 1364-2005"], - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_strength_highz.py b/test_regress/t/t_strength_highz.py new file mode 100755 index 000000000..3c9bbc984 --- /dev/null +++ b/test_regress/t/t_strength_highz.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--language 1364-2005"], + fails=test.vlt_all, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_strength_strong1_strong1_bad.pl b/test_regress/t/t_strength_strong1_strong1_bad.pl deleted file mode 100755 index 44783b1f6..000000000 --- a/test_regress/t/t_strength_strong1_strong1_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_strength_strong1_strong1_bad.py b/test_regress/t/t_strength_strong1_strong1_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_strength_strong1_strong1_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_strength_strongest_constant.pl b/test_regress/t/t_strength_strongest_constant.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_strength_strongest_constant.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_strength_strongest_constant.py b/test_regress/t/t_strength_strongest_constant.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_strength_strongest_constant.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_strength_strongest_non_tristate.pl b/test_regress/t/t_strength_strongest_non_tristate.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_strength_strongest_non_tristate.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_strength_strongest_non_tristate.py b/test_regress/t/t_strength_strongest_non_tristate.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_strength_strongest_non_tristate.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_string.pl b/test_regress/t/t_string.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_string.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_string.py b/test_regress/t/t_string.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_string.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_string_byte.pl b/test_regress/t/t_string_byte.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_string_byte.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_string_byte.py b/test_regress/t/t_string_byte.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_string_byte.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_string_dyn_num.pl b/test_regress/t/t_string_dyn_num.pl deleted file mode 100755 index d22fe4afb..000000000 --- a/test_regress/t/t_string_dyn_num.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_string_dyn_num.py b/test_regress/t/t_string_dyn_num.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_string_dyn_num.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_string_repl.pl b/test_regress/t/t_string_repl.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_string_repl.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_string_repl.py b/test_regress/t/t_string_repl.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_string_repl.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_string_size.pl b/test_regress/t/t_string_size.pl deleted file mode 100755 index ae71f01e3..000000000 --- a/test_regress/t/t_string_size.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_string_size.py b/test_regress/t/t_string_size.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_string_size.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_string_to_bit.pl b/test_regress/t/t_string_to_bit.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_string_to_bit.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_string_to_bit.py b/test_regress/t/t_string_to_bit.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_string_to_bit.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_string_type_methods.pl b/test_regress/t/t_string_type_methods.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_string_type_methods.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_string_type_methods.py b/test_regress/t/t_string_type_methods.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_string_type_methods.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_string_type_methods_bad.pl b/test_regress/t/t_string_type_methods_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_string_type_methods_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_string_type_methods_bad.py b/test_regress/t/t_string_type_methods_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_string_type_methods_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_struct_anon.pl b/test_regress/t/t_struct_anon.pl deleted file mode 100755 index 13c6e2b71..000000000 --- a/test_regress/t/t_struct_anon.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_struct_anon.py b/test_regress/t/t_struct_anon.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_struct_anon.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_struct_array.pl b/test_regress/t/t_struct_array.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_struct_array.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_array.py b/test_regress/t/t_struct_array.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_struct_array.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_struct_assign.pl b/test_regress/t/t_struct_assign.pl deleted file mode 100755 index d22fe4afb..000000000 --- a/test_regress/t/t_struct_assign.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_assign.py b/test_regress/t/t_struct_assign.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_struct_assign.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_struct_clk.pl b/test_regress/t/t_struct_clk.pl deleted file mode 100755 index e22e7f5d9..000000000 --- a/test_regress/t/t_struct_clk.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_clk.py b/test_regress/t/t_struct_clk.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_struct_clk.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_struct_cons_cast.pl b/test_regress/t/t_struct_cons_cast.pl deleted file mode 100755 index e22e7f5d9..000000000 --- a/test_regress/t/t_struct_cons_cast.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_cons_cast.py b/test_regress/t/t_struct_cons_cast.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_struct_cons_cast.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_struct_contents.pl b/test_regress/t/t_struct_contents.pl deleted file mode 100755 index e22e7f5d9..000000000 --- a/test_regress/t/t_struct_contents.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_contents.py b/test_regress/t/t_struct_contents.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_struct_contents.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_struct_contents_bad.pl b/test_regress/t/t_struct_contents_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_struct_contents_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_contents_bad.py b/test_regress/t/t_struct_contents_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_struct_contents_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_struct_genfor.pl b/test_regress/t/t_struct_genfor.pl deleted file mode 100755 index 13c6e2b71..000000000 --- a/test_regress/t/t_struct_genfor.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_struct_genfor.py b/test_regress/t/t_struct_genfor.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_struct_genfor.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_struct_init.pl b/test_regress/t/t_struct_init.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_struct_init.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_init.py b/test_regress/t/t_struct_init.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_struct_init.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_struct_init_bad.pl b/test_regress/t/t_struct_init_bad.pl deleted file mode 100755 index c7da11338..000000000 --- a/test_regress/t/t_struct_init_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -top_filename("t/t_struct_init.v"); - -lint( - v_flags2 => ['+define+T_STRUCT_INIT_BAD'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_init_bad.py b/test_regress/t/t_struct_init_bad.py new file mode 100755 index 000000000..eed2c4efc --- /dev/null +++ b/test_regress/t/t_struct_init_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_struct_init.v" + +test.lint(v_flags2=['+define+T_STRUCT_INIT_BAD'], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_struct_init_trace.pl b/test_regress/t/t_struct_init_trace.pl deleted file mode 100755 index c21f8b6ac..000000000 --- a/test_regress/t/t_struct_init_trace.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_struct_init.v"); - -compile( - verilator_flags2 => ['--cc --trace'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_init_trace.py b/test_regress/t/t_struct_init_trace.py new file mode 100755 index 000000000..4ca547717 --- /dev/null +++ b/test_regress/t/t_struct_init_trace.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_struct_init.v" + +test.compile(verilator_flags2=['--cc --trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_struct_nest.pl b/test_regress/t/t_struct_nest.pl deleted file mode 100755 index 13c6e2b71..000000000 --- a/test_regress/t/t_struct_nest.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_struct_nest.py b/test_regress/t/t_struct_nest.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_struct_nest.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_struct_nest_uarray.pl b/test_regress/t/t_struct_nest_uarray.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_struct_nest_uarray.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_nest_uarray.py b/test_regress/t/t_struct_nest_uarray.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_struct_nest_uarray.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_struct_notfound_bad.pl b/test_regress/t/t_struct_notfound_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_struct_notfound_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_notfound_bad.py b/test_regress/t/t_struct_notfound_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_struct_notfound_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_struct_packed_init_bad.pl b/test_regress/t/t_struct_packed_init_bad.pl deleted file mode 100755 index 35096464e..000000000 --- a/test_regress/t/t_struct_packed_init_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -#execute() - -ok(1); -1; diff --git a/test_regress/t/t_struct_packed_init_bad.py b/test_regress/t/t_struct_packed_init_bad.py new file mode 100755 index 000000000..5be413421 --- /dev/null +++ b/test_regress/t/t_struct_packed_init_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +#test.execute() + +test.passes() diff --git a/test_regress/t/t_struct_packed_sysfunct.pl b/test_regress/t/t_struct_packed_sysfunct.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_struct_packed_sysfunct.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_packed_sysfunct.py b/test_regress/t/t_struct_packed_sysfunct.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_struct_packed_sysfunct.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_struct_packed_value_list.pl b/test_regress/t/t_struct_packed_value_list.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_struct_packed_value_list.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_packed_value_list.py b/test_regress/t/t_struct_packed_value_list.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_struct_packed_value_list.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_struct_packed_write_read.pl b/test_regress/t/t_struct_packed_write_read.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_struct_packed_write_read.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_packed_write_read.py b/test_regress/t/t_struct_packed_write_read.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_struct_packed_write_read.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_struct_param.pl b/test_regress/t/t_struct_param.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_struct_param.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_param.py b/test_regress/t/t_struct_param.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_struct_param.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_struct_param_overflow.pl b/test_regress/t/t_struct_param_overflow.pl deleted file mode 100755 index e22e7f5d9..000000000 --- a/test_regress/t/t_struct_param_overflow.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_param_overflow.py b/test_regress/t/t_struct_param_overflow.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_struct_param_overflow.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_struct_pat.pl b/test_regress/t/t_struct_pat.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_struct_pat.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_pat.py b/test_regress/t/t_struct_pat.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_struct_pat.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_struct_pat_width.pl b/test_regress/t/t_struct_pat_width.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_struct_pat_width.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_pat_width.py b/test_regress/t/t_struct_pat_width.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_struct_pat_width.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_struct_port.pl b/test_regress/t/t_struct_port.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_struct_port.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_port.py b/test_regress/t/t_struct_port.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_struct_port.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_struct_portsel.pl b/test_regress/t/t_struct_portsel.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_struct_portsel.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_portsel.py b/test_regress/t/t_struct_portsel.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_struct_portsel.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_struct_unaligned.pl b/test_regress/t/t_struct_unaligned.pl deleted file mode 100755 index f966e5652..000000000 --- a/test_regress/t/t_struct_unaligned.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -# Note: need to run at a higher optimization level to reproduce the issue -$Self->{benchmark} = 1; - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_unaligned.py b/test_regress/t/t_struct_unaligned.py new file mode 100755 index 000000000..97da89c5f --- /dev/null +++ b/test_regress/t/t_struct_unaligned.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +# Note: need to run at a higher optimization level to reproduce the issue +test.benchmark = True + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_struct_unpacked.pl b/test_regress/t/t_struct_unpacked.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_struct_unpacked.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_unpacked.py b/test_regress/t/t_struct_unpacked.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_struct_unpacked.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_struct_unpacked_array.pl b/test_regress/t/t_struct_unpacked_array.pl deleted file mode 100755 index e3ff738db..000000000 --- a/test_regress/t/t_struct_unpacked_array.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2=>["--x-assign unique --x-initial unique -Wno-WIDTH -O0"] - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_unpacked_array.py b/test_regress/t/t_struct_unpacked_array.py new file mode 100755 index 000000000..1d39072e8 --- /dev/null +++ b/test_regress/t/t_struct_unpacked_array.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--x-assign unique --x-initial unique -Wno-WIDTH -O0"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_struct_unpacked_clean.pl b/test_regress/t/t_struct_unpacked_clean.pl deleted file mode 100755 index e3ff738db..000000000 --- a/test_regress/t/t_struct_unpacked_clean.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2=>["--x-assign unique --x-initial unique -Wno-WIDTH -O0"] - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_unpacked_clean.py b/test_regress/t/t_struct_unpacked_clean.py new file mode 100755 index 000000000..1d39072e8 --- /dev/null +++ b/test_regress/t/t_struct_unpacked_clean.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--x-assign unique --x-initial unique -Wno-WIDTH -O0"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_struct_unpacked_init.pl b/test_regress/t/t_struct_unpacked_init.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_struct_unpacked_init.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_struct_unpacked_init.py b/test_regress/t/t_struct_unpacked_init.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_struct_unpacked_init.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_struct_unused.pl b/test_regress/t/t_struct_unused.pl deleted file mode 100755 index 14a2db81b..000000000 --- a/test_regress/t/t_struct_unused.pl +++ /dev/null @@ -1,32 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -# Use --debug-protect to assist debug - -compile( - ); - -execute( - ); - -if ($Self->{vlt_all}) { - # Check for unused structs in any outputs - my $any; - foreach my $filename (glob $Self->{obj_dir} . "/*.[ch]*") { - file_grep_not($filename, qr/useless/); - $any = 1; - } - $any or $Self->error("No outputs found"); -} - -ok(1); -1; diff --git a/test_regress/t/t_struct_unused.py b/test_regress/t/t_struct_unused.py new file mode 100755 index 000000000..143e17cb5 --- /dev/null +++ b/test_regress/t/t_struct_unused.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +# Use --debug-protect to assist debug + +test.compile() + +test.execute() + +if test.vlt_all: + # Check for unused structs in any outputs + for filename in test.glob_some(test.obj_dir + "/*.[ch]*"): + test.file_grep_not(filename, r'useless') + +test.passes() diff --git a/test_regress/t/t_structu_dataType_assignment.pl b/test_regress/t/t_structu_dataType_assignment.pl deleted file mode 100755 index 2b40a1bc6..000000000 --- a/test_regress/t/t_structu_dataType_assignment.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--structs-packed'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_structu_dataType_assignment.py b/test_regress/t/t_structu_dataType_assignment.py new file mode 100755 index 000000000..d80083531 --- /dev/null +++ b/test_regress/t/t_structu_dataType_assignment.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--structs-packed']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_structu_dataType_assignment_bad.pl b/test_regress/t/t_structu_dataType_assignment_bad.pl deleted file mode 100755 index d593ee907..000000000 --- a/test_regress/t/t_structu_dataType_assignment_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint( - verilator_flags2 => ['--structs-packed'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_structu_dataType_assignment_bad.py b/test_regress/t/t_structu_dataType_assignment_bad.py new file mode 100755 index 000000000..a5aa131e7 --- /dev/null +++ b/test_regress/t/t_structu_dataType_assignment_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(verilator_flags2=['--structs-packed'], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_structu_wide.pl b/test_regress/t/t_structu_wide.pl deleted file mode 100755 index 954c29b84..000000000 --- a/test_regress/t/t_structu_wide.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => [ '-DWIDE_WIDTH=128' ], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_structu_wide.py b/test_regress/t/t_structu_wide.py new file mode 100755 index 000000000..b1fdec1e8 --- /dev/null +++ b/test_regress/t/t_structu_wide.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['-DWIDE_WIDTH=128']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_suspendable_deep.pl b/test_regress/t/t_suspendable_deep.pl deleted file mode 100755 index 3b4f977f4..000000000 --- a/test_regress/t/t_suspendable_deep.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["--binary --timing"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_suspendable_deep.py b/test_regress/t/t_suspendable_deep.py new file mode 100755 index 000000000..6e837dc78 --- /dev/null +++ b/test_regress/t/t_suspendable_deep.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--binary --timing"]) + +test.passes() diff --git a/test_regress/t/t_sv_bus_mux_demux.pl b/test_regress/t/t_sv_bus_mux_demux.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_sv_bus_mux_demux.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_sv_bus_mux_demux.py b/test_regress/t/t_sv_bus_mux_demux.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_sv_bus_mux_demux.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_sv_conditional.pl b/test_regress/t/t_sv_conditional.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_sv_conditional.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_sv_conditional.py b/test_regress/t/t_sv_conditional.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_sv_conditional.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_sv_cpu.pl b/test_regress/t/t_sv_cpu.pl deleted file mode 100755 index 1486efc3c..000000000 --- a/test_regress/t/t_sv_cpu.pl +++ /dev/null @@ -1,46 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -# 22-Mar-2012: Modifications for this test contributed by Jeremy Bennett, -# Embecosm. - -compile( - # Taken from the original VCS command line. - v_flags2 => ["t/t_sv_cpu_code/timescale.sv", - "t/t_sv_cpu_code/program_h.sv", - "t/t_sv_cpu_code/pads_h.sv", - "t/t_sv_cpu_code/ports_h.sv", - "t/t_sv_cpu_code/pinout_h.sv", - "t/t_sv_cpu_code/genbus_if.sv", - "t/t_sv_cpu_code/pads_if.sv", - "t/t_sv_cpu_code/adrdec.sv", - "t/t_sv_cpu_code/pad_gpio.sv", - "t/t_sv_cpu_code/pad_vdd.sv", - "t/t_sv_cpu_code/pad_gnd.sv", - "t/t_sv_cpu_code/pads.sv", - "t/t_sv_cpu_code/ports.sv", - "t/t_sv_cpu_code/ac_dig.sv", - "t/t_sv_cpu_code/ac_ana.sv", - "t/t_sv_cpu_code/ac.sv", - "t/t_sv_cpu_code/cpu.sv", - "t/t_sv_cpu_code/chip.sv"], - vcs_flags2 => ["-R -sverilog +memcbk -y t/t_sv_cpu_code +libext+.sv+ +incdir+t/t_sv_cpu_code"], - verilator_flags2 => ["-y t/t_sv_cpu_code +libext+.sv+ +incdir+t/t_sv_cpu_code --top-module t", - "--timescale-override 1ns/1ps"], - iv_flags2 => ["-yt/t_sv_cpu_code -It/t_sv_cpu_code -Y.sv"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_sv_cpu.py b/test_regress/t/t_sv_cpu.py new file mode 100755 index 000000000..84a49ebb7 --- /dev/null +++ b/test_regress/t/t_sv_cpu.py @@ -0,0 +1,37 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +# 22-Mar-2012: Modifications for this test contributed by Jeremy Bennett, +# Embecosm. + +test.compile( + # Taken from the original VCS command line. + v_flags2=[ + "t/t_sv_cpu_code/timescale.sv", "t/t_sv_cpu_code/program_h.sv", + "t/t_sv_cpu_code/pads_h.sv", "t/t_sv_cpu_code/ports_h.sv", "t/t_sv_cpu_code/pinout_h.sv", + "t/t_sv_cpu_code/genbus_if.sv", "t/t_sv_cpu_code/pads_if.sv", "t/t_sv_cpu_code/adrdec.sv", + "t/t_sv_cpu_code/pad_gpio.sv", "t/t_sv_cpu_code/pad_vdd.sv", "t/t_sv_cpu_code/pad_gnd.sv", + "t/t_sv_cpu_code/pads.sv", "t/t_sv_cpu_code/ports.sv", "t/t_sv_cpu_code/ac_dig.sv", + "t/t_sv_cpu_code/ac_ana.sv", "t/t_sv_cpu_code/ac.sv", "t/t_sv_cpu_code/cpu.sv", + "t/t_sv_cpu_code/chip.sv" + ], + vcs_flags2=["-R -sverilog +memcbk -y t/t_sv_cpu_code +libext+.sv+ +incdir+t/t_sv_cpu_code"], + verilator_flags2=[ + "-y t/t_sv_cpu_code +libext+.sv+ +incdir+t/t_sv_cpu_code --top-module t", + "--timescale-override 1ns/1ps" + ], + iv_flags2=["-yt/t_sv_cpu_code -It/t_sv_cpu_code -Y.sv"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_sys_delta_monitor.pl b/test_regress/t/t_sys_delta_monitor.pl deleted file mode 100755 index b30043275..000000000 --- a/test_regress/t/t_sys_delta_monitor.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing --timescale 1ns/1ns"], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_sys_delta_monitor.py b/test_regress/t/t_sys_delta_monitor.py new file mode 100755 index 000000000..f9e3a2b05 --- /dev/null +++ b/test_regress/t/t_sys_delta_monitor.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing --timescale 1ns/1ns"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_sys_file_autoflush.pl b/test_regress/t/t_sys_file_autoflush.pl deleted file mode 100755 index 71ad6da28..000000000 --- a/test_regress/t/t_sys_file_autoflush.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_sys_file_basic.v"); - -compile( - v_flags2 => ['+incdir+../include', - '+define+AUTOFLUSH'], - verilator_flags2 => ['--autoflush'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_sys_file_autoflush.py b/test_regress/t/t_sys_file_autoflush.py new file mode 100755 index 000000000..c753bd0e8 --- /dev/null +++ b/test_regress/t/t_sys_file_autoflush.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_sys_file_basic.v" + +test.compile(v_flags2=['+incdir+../include', '+define+AUTOFLUSH'], + verilator_flags2=['--autoflush']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_sys_file_basic.pl b/test_regress/t/t_sys_file_basic.pl deleted file mode 100755 index 7f1928eae..000000000 --- a/test_regress/t/t_sys_file_basic.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -unlink("$Self->{obj_dir}/t_sys_file_basic_test.log"); - -compile( - # Build without cached objects, see bug363 - make_flags => 'VM_PARALLEL_BUILDS=0', - ); - -execute( - ); - -files_identical("$Self->{obj_dir}/t_sys_file_basic_test.log", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_sys_file_basic.py b/test_regress/t/t_sys_file_basic.py new file mode 100755 index 000000000..d36d66d7c --- /dev/null +++ b/test_regress/t/t_sys_file_basic.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.unlink_ok(test.obj_dir + "/t_sys_file_basic_test.log") + +test.compile( + # Build without cached objects, see bug363 + make_flags=['VM_PARALLEL_BUILDS=0']) + +test.execute() +test.files_identical(test.obj_dir + "/t_sys_file_basic_test.log", test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_sys_file_basic_mcd.pl b/test_regress/t/t_sys_file_basic_mcd.pl deleted file mode 100755 index 6846c2ebd..000000000 --- a/test_regress/t/t_sys_file_basic_mcd.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -unlink("$Self->{obj_dir}/t_sys_file_basic_mcd.log"); - -compile(); -execute( - expect_filename => $Self->{golden_filename}, - ); - -files_identical("$Self->{obj_dir}/t_sys_file_basic_mcd_test2_0.dat", - "$Self->{t_dir}/t_sys_file_basic_mcd_test2_0.dat"); -files_identical("$Self->{obj_dir}/t_sys_file_basic_mcd_test2_1.dat", - "$Self->{t_dir}/t_sys_file_basic_mcd_test2_1.dat"); -files_identical("$Self->{obj_dir}/t_sys_file_basic_mcd_test2_2.dat", - "$Self->{t_dir}/t_sys_file_basic_mcd_test2_2.dat"); -files_identical("$Self->{obj_dir}/t_sys_file_basic_mcd_test5.dat", - "$Self->{t_dir}/t_sys_file_basic_mcd_test5.dat"); - -ok(1); -1; diff --git a/test_regress/t/t_sys_file_basic_mcd.py b/test_regress/t/t_sys_file_basic_mcd.py new file mode 100755 index 000000000..307f60dff --- /dev/null +++ b/test_regress/t/t_sys_file_basic_mcd.py @@ -0,0 +1,29 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.unlink_ok(test.obj_dir + "/t_sys_file_basic_mcd.log") + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.files_identical(test.obj_dir + "/t_sys_file_basic_mcd_test2_0.dat", + test.t_dir + "/t_sys_file_basic_mcd_test2_0.dat") +test.files_identical(test.obj_dir + "/t_sys_file_basic_mcd_test2_1.dat", + test.t_dir + "/t_sys_file_basic_mcd_test2_1.dat") +test.files_identical(test.obj_dir + "/t_sys_file_basic_mcd_test2_2.dat", + test.t_dir + "/t_sys_file_basic_mcd_test2_2.dat") +test.files_identical(test.obj_dir + "/t_sys_file_basic_mcd_test5.dat", + test.t_dir + "/t_sys_file_basic_mcd_test5.dat") + +test.passes() diff --git a/test_regress/t/t_sys_file_basic_uz.pl b/test_regress/t/t_sys_file_basic_uz.pl deleted file mode 100755 index 6821e854f..000000000 --- a/test_regress/t/t_sys_file_basic_uz.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -unlink("$Self->{obj_dir}/t_sys_file_basic_uz_test.log"); - -compile(); - -execute( - ); - -files_identical("$Self->{obj_dir}/t_sys_file_basic_uz_test.log", $Self->{golden_filename}); - -files_identical("$Self->{obj_dir}/t_sys_file_basic_uz_test.bin", - "$Self->{t_dir}/t_sys_file_basic_uz.dat"); - -ok(1); -1; diff --git a/test_regress/t/t_sys_file_basic_uz.py b/test_regress/t/t_sys_file_basic_uz.py new file mode 100755 index 000000000..8afc2b9d3 --- /dev/null +++ b/test_regress/t/t_sys_file_basic_uz.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.unlink_ok(test.obj_dir + "/t_sys_file_basic_uz_test.log") + +test.compile() + +test.execute() + +test.files_identical(test.obj_dir + "/t_sys_file_basic_uz_test.log", test.golden_filename) +test.files_identical(test.obj_dir + "/t_sys_file_basic_uz_test.bin", + test.t_dir + "/t_sys_file_basic_uz.dat") + +test.passes() diff --git a/test_regress/t/t_sys_file_eof.pl b/test_regress/t/t_sys_file_eof.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_sys_file_eof.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_sys_file_eof.py b/test_regress/t/t_sys_file_eof.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_sys_file_eof.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_sys_file_null.pl b/test_regress/t/t_sys_file_null.pl deleted file mode 100755 index f8bc4bb67..000000000 --- a/test_regress/t/t_sys_file_null.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -my $fn = "$Self->{obj_dir}/zeros.log"; -if (-s $fn != 16) { - $Self->error("$fn: Wrong file size"); -} - -ok(1); -1; diff --git a/test_regress/t/t_sys_file_null.py b/test_regress/t/t_sys_file_null.py new file mode 100755 index 000000000..29e82f03c --- /dev/null +++ b/test_regress/t/t_sys_file_null.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +filename = test.obj_dir + "/zeros.log" +if os.path.getsize(filename) != 16: + test.error(filename + ": Wrong file size") + +test.passes() diff --git a/test_regress/t/t_sys_file_scan.pl b/test_regress/t/t_sys_file_scan.pl deleted file mode 100755 index 48f7587e5..000000000 --- a/test_regress/t/t_sys_file_scan.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -unlink("$Self->{obj_dir}/t_sys_file_scan_test.log"); - -compile( - ); - -execute( - ); - -file_grep("$Self->{obj_dir}/t_sys_file_scan_test.log", -"# a - 1 -"); - -ok(1); -1; diff --git a/test_regress/t/t_sys_file_scan.py b/test_regress/t/t_sys_file_scan.py new file mode 100755 index 000000000..3f737df94 --- /dev/null +++ b/test_regress/t/t_sys_file_scan.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.unlink_ok(test.obj_dir + "/t_sys_file_scan_test.log") + +test.compile() + +test.execute() + +test.file_grep(test.obj_dir + "/t_sys_file_scan_test.log", r"""# a + 1 +""") + +test.passes() diff --git a/test_regress/t/t_sys_file_zero.pl b/test_regress/t/t_sys_file_zero.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_sys_file_zero.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_sys_file_zero.py b/test_regress/t/t_sys_file_zero.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_sys_file_zero.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_sys_fmonitor.pl b/test_regress/t/t_sys_fmonitor.pl deleted file mode 100755 index 42f9edddc..000000000 --- a/test_regress/t/t_sys_fmonitor.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -files_identical("$Self->{obj_dir}/open.log", $Self->{golden_filename}); - -ok(1); - -1; diff --git a/test_regress/t/t_sys_fmonitor.py b/test_regress/t/t_sys_fmonitor.py new file mode 100755 index 000000000..8ec472516 --- /dev/null +++ b/test_regress/t/t_sys_fmonitor.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() +test.files_identical(test.obj_dir + "/open.log", test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_sys_fopen_bad.pl b/test_regress/t/t_sys_fopen_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_sys_fopen_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_sys_fopen_bad.py b/test_regress/t/t_sys_fopen_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_sys_fopen_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_sys_fread.pl b/test_regress/t/t_sys_fread.pl deleted file mode 100755 index 135463223..000000000 --- a/test_regress/t/t_sys_fread.pl +++ /dev/null @@ -1,38 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -use IO::File; -#use Data::Dumper; -use strict; -use vars qw($Self); - -scenarios(simulator => 1); - -sub gen { - my $filename = shift; - - my $fh = IO::File->new(">$filename"); - for (my $copy = 0; $copy < 32; ++$copy) { - for (my $i = 0; $i <= 255; ++$i) { - $fh->print(chr($i)); - } - } -} - -gen("$Self->{obj_dir}/t_sys_fread.mem"); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_sys_fread.py b/test_regress/t/t_sys_fread.py new file mode 100755 index 000000000..29f0832f0 --- /dev/null +++ b/test_regress/t/t_sys_fread.py @@ -0,0 +1,28 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + + +def gen(filename): + with open(filename, 'w', encoding="latin-1") as fh: + for copy in range(0, 32): # pylint: disable=unused-variable + for i in range(0, 256): + fh.write(chr(i)) + + +gen(test.obj_dir + "/t_sys_fread.mem") + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_sys_fscanf_bad.pl b/test_regress/t/t_sys_fscanf_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_sys_fscanf_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_sys_fscanf_bad.py b/test_regress/t/t_sys_fscanf_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_sys_fscanf_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_sys_fstrobe.pl b/test_regress/t/t_sys_fstrobe.pl deleted file mode 100755 index 381298c61..000000000 --- a/test_regress/t/t_sys_fstrobe.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); # Not vltmt due to possible race - -compile( - ); - -execute( - ); - -files_identical("$Self->{obj_dir}/open.log", $Self->{golden_filename}); - -ok(1); - -1; diff --git a/test_regress/t/t_sys_fstrobe.py b/test_regress/t/t_sys_fstrobe.py new file mode 100755 index 000000000..63d3560f9 --- /dev/null +++ b/test_regress/t/t_sys_fstrobe.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') # Not vltmt due to possible race + +test.compile() + +test.execute() + +test.files_identical(test.obj_dir + "/open.log", test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_sys_monitor.pl b/test_regress/t/t_sys_monitor.pl deleted file mode 100755 index 0dd6234fe..000000000 --- a/test_regress/t/t_sys_monitor.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_sys_monitor.py b/test_regress/t/t_sys_monitor.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_sys_monitor.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_sys_plusargs.pl b/test_regress/t/t_sys_plusargs.pl deleted file mode 100755 index 026eb7c76..000000000 --- a/test_regress/t/t_sys_plusargs.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ['-v', 't/t_flag_libinc.v'], - ); - -execute( - all_run_flags => ['+PLUS +INT=1234 +STRSTR +REAL=1.2345 +IP%P101'], - ); - -ok(1); -1; diff --git a/test_regress/t/t_sys_plusargs.py b/test_regress/t/t_sys_plusargs.py new file mode 100755 index 000000000..51529220e --- /dev/null +++ b/test_regress/t/t_sys_plusargs.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=['-v', 't/t_flag_libinc.v']) + +test.execute(all_run_flags=['+PLUS +INT=1234 +STRSTR +REAL=1.2345 +IP%P101']) + +test.passes() diff --git a/test_regress/t/t_sys_plusargs_bad.pl b/test_regress/t/t_sys_plusargs_bad.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_sys_plusargs_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_sys_plusargs_bad.py b/test_regress/t/t_sys_plusargs_bad.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_sys_plusargs_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_sys_psprintf.pl b/test_regress/t/t_sys_psprintf.pl deleted file mode 100755 index 2a2d2d496..000000000 --- a/test_regress/t/t_sys_psprintf.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['-Wno-NONSTD'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_sys_psprintf.py b/test_regress/t/t_sys_psprintf.py new file mode 100755 index 000000000..45836a507 --- /dev/null +++ b/test_regress/t/t_sys_psprintf.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['-Wno-NONSTD']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_sys_psprintf_warn_bad.pl b/test_regress/t/t_sys_psprintf_warn_bad.pl deleted file mode 100755 index 903983f53..000000000 --- a/test_regress/t/t_sys_psprintf_warn_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_sys_psprintf.v"); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_sys_psprintf_warn_bad.py b/test_regress/t/t_sys_psprintf_warn_bad.py new file mode 100755 index 000000000..092329b04 --- /dev/null +++ b/test_regress/t/t_sys_psprintf_warn_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_sys_psprintf.v" + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_sys_rand.pl b/test_regress/t/t_sys_rand.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_sys_rand.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_sys_rand.py b/test_regress/t/t_sys_rand.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_sys_rand.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_sys_rand_concat.pl b/test_regress/t/t_sys_rand_concat.pl deleted file mode 100755 index 8ad4c11dd..000000000 --- a/test_regress/t/t_sys_rand_concat.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -for my $file (glob_all("$Self->{obj_dir}/$Self->{vm_prefix}___024root__DepSet*__Slow.cpp")) { - file_grep_not($file, qr/(<<|>>)/); -} - -ok(1); -1; diff --git a/test_regress/t/t_sys_rand_concat.py b/test_regress/t/t_sys_rand_concat.py new file mode 100755 index 000000000..48dfd22b5 --- /dev/null +++ b/test_regress/t/t_sys_rand_concat.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +for filename in test.glob_some(test.obj_dir + "/" + test.vm_prefix + + "___024root__DepSet*__Slow.cpp"): + test.file_grep_not(filename, r'(<<|>>)') + +test.passes() diff --git a/test_regress/t/t_sys_rand_seed.pl b/test_regress/t/t_sys_rand_seed.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_sys_rand_seed.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_sys_rand_seed.py b/test_regress/t/t_sys_rand_seed.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_sys_rand_seed.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_sys_readmem.pl b/test_regress/t/t_sys_readmem.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_sys_readmem.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_sys_readmem.py b/test_regress/t/t_sys_readmem.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_sys_readmem.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_sys_readmem_4state.pl b/test_regress/t/t_sys_readmem_4state.pl deleted file mode 100755 index c65d2fa5f..000000000 --- a/test_regress/t/t_sys_readmem_4state.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--x-initial unique"], - ); - -execute( - all_run_flags => ["+verilator+rand+reset+1"], - ); - -files_identical("$Self->{obj_dir}/t_sys_readmem_4state_b.mem", "t/t_sys_readmem_4state_b.out"); -files_identical("$Self->{obj_dir}/t_sys_readmem_4state_h.mem", "t/t_sys_readmem_4state_h.out"); - -ok(1); -1; diff --git a/test_regress/t/t_sys_readmem_4state.py b/test_regress/t/t_sys_readmem_4state.py new file mode 100755 index 000000000..3995ab993 --- /dev/null +++ b/test_regress/t/t_sys_readmem_4state.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--x-initial unique"]) + +test.execute(all_run_flags=["+verilator+rand+reset+1"]) + +test.files_identical(test.obj_dir + "/t_sys_readmem_4state_b.mem", "t/t_sys_readmem_4state_b.out") +test.files_identical(test.obj_dir + "/t_sys_readmem_4state_h.mem", "t/t_sys_readmem_4state_h.out") + +test.passes() diff --git a/test_regress/t/t_sys_readmem_assoc.pl b/test_regress/t/t_sys_readmem_assoc.pl deleted file mode 100755 index 775cf31ce..000000000 --- a/test_regress/t/t_sys_readmem_assoc.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -files_identical("$Self->{obj_dir}/t_sys_writemem_c_b.mem", "t/t_sys_readmem_assoc_c_b.out"); -files_identical("$Self->{obj_dir}/t_sys_writemem_w_h.mem", "t/t_sys_readmem_assoc_w_h.out"); - -ok(1); -1; diff --git a/test_regress/t/t_sys_readmem_assoc.py b/test_regress/t/t_sys_readmem_assoc.py new file mode 100755 index 000000000..78cda062b --- /dev/null +++ b/test_regress/t/t_sys_readmem_assoc.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.files_identical(test.obj_dir + "/t_sys_writemem_c_b.mem", "t/t_sys_readmem_assoc_c_b.out") +test.files_identical(test.obj_dir + "/t_sys_writemem_w_h.mem", "t/t_sys_readmem_assoc_w_h.out") + +test.passes() diff --git a/test_regress/t/t_sys_readmem_assoc_bad.pl b/test_regress/t/t_sys_readmem_assoc_bad.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_sys_readmem_assoc_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_sys_readmem_assoc_bad.py b/test_regress/t/t_sys_readmem_assoc_bad.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_sys_readmem_assoc_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_sys_readmem_bad_addr.pl b/test_regress/t/t_sys_readmem_bad_addr.pl deleted file mode 100755 index d89f1290d..000000000 --- a/test_regress/t/t_sys_readmem_bad_addr.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_sys_readmem_bad_addr.py b/test_regress/t/t_sys_readmem_bad_addr.py new file mode 100755 index 000000000..be2efa43f --- /dev/null +++ b/test_regress/t/t_sys_readmem_bad_addr.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_sys_readmem_bad_addr2.pl b/test_regress/t/t_sys_readmem_bad_addr2.pl deleted file mode 100755 index 0530bf7e8..000000000 --- a/test_regress/t/t_sys_readmem_bad_addr2.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_sys_readmem_bad_addr2.py b/test_regress/t/t_sys_readmem_bad_addr2.py new file mode 100755 index 000000000..be2efa43f --- /dev/null +++ b/test_regress/t/t_sys_readmem_bad_addr2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_sys_readmem_bad_digit.pl b/test_regress/t/t_sys_readmem_bad_digit.pl deleted file mode 100755 index d89f1290d..000000000 --- a/test_regress/t/t_sys_readmem_bad_digit.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_sys_readmem_bad_digit.py b/test_regress/t/t_sys_readmem_bad_digit.py new file mode 100755 index 000000000..be2efa43f --- /dev/null +++ b/test_regress/t/t_sys_readmem_bad_digit.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_sys_readmem_bad_end.pl b/test_regress/t/t_sys_readmem_bad_end.pl deleted file mode 100755 index 56cc415df..000000000 --- a/test_regress/t/t_sys_readmem_bad_end.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_sys_readmem_bad_end.py b/test_regress/t/t_sys_readmem_bad_end.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_sys_readmem_bad_end.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_sys_readmem_bad_notfound.pl b/test_regress/t/t_sys_readmem_bad_notfound.pl deleted file mode 100755 index 56cc415df..000000000 --- a/test_regress/t/t_sys_readmem_bad_notfound.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_sys_readmem_bad_notfound.py b/test_regress/t/t_sys_readmem_bad_notfound.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_sys_readmem_bad_notfound.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_sys_readmem_eof.pl b/test_regress/t/t_sys_readmem_eof.pl deleted file mode 100755 index 79d05e488..000000000 --- a/test_regress/t/t_sys_readmem_eof.pl +++ /dev/null @@ -1,33 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -sub gen { - # Generate using file to avoid missing newline in repository - my $filename = shift; - my $fh = IO::File->new(">$filename"); - $fh->print("// Generated by t_vthread.pl\n"); - $fh->print("1\n"); - $fh->print("10\n"); - $fh->print("20\n"); - $fh->print("30"); # No newline -} - -gen($Self->{obj_dir} . "/dat.mem"); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_sys_readmem_eof.py b/test_regress/t/t_sys_readmem_eof.py new file mode 100755 index 000000000..a34d539d0 --- /dev/null +++ b/test_regress/t/t_sys_readmem_eof.py @@ -0,0 +1,32 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + + +def gen(filename): + # Generate using file to avoid missing newline in repository + with open(filename, 'w', encoding="utf8") as fh: + fh.write("// Generated by t_vthread.py\n") + fh.write("1\n") + fh.write("10\n") + fh.write("20\n") + fh.write("30") + # No newline + + +gen(test.obj_dir + "/dat.mem") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_sys_sformat.pl b/test_regress/t/t_sys_sformat.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_sys_sformat.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_sys_sformat.py b/test_regress/t/t_sys_sformat.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_sys_sformat.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_sys_sformat_noopt.pl b/test_regress/t/t_sys_sformat_noopt.pl deleted file mode 100755 index 562c3b5c4..000000000 --- a/test_regress/t/t_sys_sformat_noopt.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_sys_sformat.v"); - -compile( - # Avoid inlining our simple example, to make sure verilated.h works right - verilator_flags2 => ["-O0"], - ); - -if ($Self->cxx_version =~ /clang/) { - skip("Known clang bug"); - #Here: if (VL_UNLIKELY(VL_NEQ_W(12, __Vtemp1, vlSymsp->TOP__t.__PVT__str))) -} else { - execute( - ); -} - -ok(1); -1; diff --git a/test_regress/t/t_sys_sformat_noopt.py b/test_regress/t/t_sys_sformat_noopt.py new file mode 100755 index 000000000..ad41c3d45 --- /dev/null +++ b/test_regress/t/t_sys_sformat_noopt.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_sys_sformat.v" + +test.compile( + # Avoid inlining our simple example, to make sure verilated.h works right + verilator_flags2=["-O0"]) + +if re.search(r'clang', test.cxx_version): + test.skip("Known clang bug") + #Here: if (VL_UNLIKELY(VL_NEQ_W(12, __Vtemp1, vlSymsp->TOP__t.__PVT__str))) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_sys_strobe.pl b/test_regress/t/t_sys_strobe.pl deleted file mode 100755 index 0dd6234fe..000000000 --- a/test_regress/t/t_sys_strobe.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_sys_strobe.py b/test_regress/t/t_sys_strobe.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_sys_strobe.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_sys_system.pl b/test_regress/t/t_sys_system.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_sys_system.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_sys_system.py b/test_regress/t/t_sys_system.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_sys_system.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_sys_time.pl b/test_regress/t/t_sys_time.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_sys_time.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_sys_time.py b/test_regress/t/t_sys_time.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_sys_time.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_sys_writemem.pl b/test_regress/t/t_sys_writemem.pl deleted file mode 100755 index f69ac67db..000000000 --- a/test_regress/t/t_sys_writemem.pl +++ /dev/null @@ -1,43 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_sys_readmem.v"); - -# Use random reset to ensure we're fully initializing arrays before -# $writememh, to avoid miscompares with X's on 4-state simulators. -$Self->{verilated_randReset} = 2; # 2 == truly random - -# TODO make test more generic to take the data type as a define -# then we can call test multiple times in different tests -compile(v_flags2 => [ - "+define+WRITEMEM_READ_BACK=1", - "+define+OUT_TMP1=\\\"$Self->{obj_dir}/tmp1.mem\\\"", - "+define+OUT_TMP2=\\\"$Self->{obj_dir}/tmp2.mem\\\"", - "+define+OUT_TMP3=\\\"$Self->{obj_dir}/tmp3.mem\\\"", - "+define+OUT_TMP4=\\\"$Self->{obj_dir}/tmp4.mem\\\"", - "+define+OUT_TMP5=\\\"$Self->{obj_dir}/tmp5.mem\\\"", - "+define+OUT_TMP6=\\\"$Self->{obj_dir}/tmp6.mem\\\"", - "+define+OUT_TMP7=\\\"$Self->{obj_dir}/tmp7.mem\\\"", - "+define+OUT_TMP8=\\\"$Self->{obj_dir}/tmp8.mem\\\"", - ]); - -execute( - ); - -for (my $i = 1; $i <= 8; $i++) { - my $gold = "$Self->{t_dir}/t_sys_writemem.gold${i}.mem"; - my $out = "$Self->{obj_dir}/tmp${i}.mem"; - files_identical($out, $gold); -} - -ok(1); -1; diff --git a/test_regress/t/t_sys_writemem.py b/test_regress/t/t_sys_writemem.py new file mode 100755 index 000000000..27786c641 --- /dev/null +++ b/test_regress/t/t_sys_writemem.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_sys_readmem.v" + +# Use random reset to ensure we're fully initializing arrays before +# $writememh, to avoid miscompares with X's on 4-state simulators. +test.verilated_randReset = 2 # 2 == truly random + +# TODO make test more generic to take the data type as a define +# then we can call test multiple times in different tests +test.compile(v_flags2=[ + '+define+WRITEMEM_READ_BACK=1', + '\'+define+OUT_TMP1=\"' + test.obj_dir + '/tmp1.mem\"\'', + '\'+define+OUT_TMP2=\"' + test.obj_dir + '/tmp2.mem\"\'', + '\'+define+OUT_TMP3=\"' + test.obj_dir + '/tmp3.mem\"\'', + '\'+define+OUT_TMP4=\"' + test.obj_dir + '/tmp4.mem\"\'', + '\'+define+OUT_TMP5=\"' + test.obj_dir + '/tmp5.mem\"\'', + '\'+define+OUT_TMP6=\"' + test.obj_dir + '/tmp6.mem\"\'', + '\'+define+OUT_TMP7=\"' + test.obj_dir + '/tmp7.mem\"\'', + '\'+define+OUT_TMP8=\"' + test.obj_dir + '/tmp8.mem\"\'', +]) + +test.execute() + +for i in range(1, 9): + gold = test.t_dir + "/t_sys_writemem.gold" + str(i) + ".mem" + out = test.obj_dir + "/tmp" + str(i) + ".mem" + test.files_identical(out, gold) + +test.passes() diff --git a/test_regress/t/t_sys_writemem_b.pl b/test_regress/t/t_sys_writemem_b.pl deleted file mode 100755 index 6f3070539..000000000 --- a/test_regress/t/t_sys_writemem_b.pl +++ /dev/null @@ -1,42 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_sys_readmem.v"); - -# Use random reset to ensure we're fully initializing arrays before -# $writememh, to avoid miscompares with X's on 4-state simulators. -$Self->{verilated_randReset} = 2; # 2 == truly random - -compile(v_flags2 => [ - "+define+WRITEMEM_READ_BACK=1", - "+define+WRITEMEM_BIN=1", - "+define+OUT_TMP1=\\\"$Self->{obj_dir}/tmp1.mem\\\"", - "+define+OUT_TMP2=\\\"$Self->{obj_dir}/tmp2.mem\\\"", - "+define+OUT_TMP3=\\\"$Self->{obj_dir}/tmp3.mem\\\"", - "+define+OUT_TMP4=\\\"$Self->{obj_dir}/tmp4.mem\\\"", - "+define+OUT_TMP5=\\\"$Self->{obj_dir}/tmp5.mem\\\"", - "+define+OUT_TMP6=\\\"$Self->{obj_dir}/tmp6.mem\\\"", - "+define+OUT_TMP7=\\\"$Self->{obj_dir}/tmp7.mem\\\"", - "+define+OUT_TMP8=\\\"$Self->{obj_dir}/tmp8.mem\\\"", - ]); - -execute( - ); - -for (my $i = 1; $i <= 8; $i++) { - my $gold = "$Self->{t_dir}/t_sys_writemem_b.gold${i}.mem"; - my $out = "$Self->{obj_dir}/tmp${i}.mem"; - files_identical($out, $gold); -} - -ok(1); -1; diff --git a/test_regress/t/t_sys_writemem_b.py b/test_regress/t/t_sys_writemem_b.py new file mode 100755 index 000000000..902f273e2 --- /dev/null +++ b/test_regress/t/t_sys_writemem_b.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_sys_readmem.v" + +# Use random reset to ensure we're fully initializing arrays before +# $writememh, to avoid miscompares with X's on 4-state simulators. +test.verilated_randReset = 2 # 2 == truly random + +test.compile(v_flags2=[ + "+define+WRITEMEM_READ_BACK=1", + "+define+WRITEMEM_BIN=1", + '+define+WRITEMEM_READ_BACK=1', + '\'+define+OUT_TMP1=\"' + test.obj_dir + '/tmp1.mem\"\'', + '\'+define+OUT_TMP2=\"' + test.obj_dir + '/tmp2.mem\"\'', + '\'+define+OUT_TMP3=\"' + test.obj_dir + '/tmp3.mem\"\'', + '\'+define+OUT_TMP4=\"' + test.obj_dir + '/tmp4.mem\"\'', + '\'+define+OUT_TMP5=\"' + test.obj_dir + '/tmp5.mem\"\'', + '\'+define+OUT_TMP6=\"' + test.obj_dir + '/tmp6.mem\"\'', + '\'+define+OUT_TMP7=\"' + test.obj_dir + '/tmp7.mem\"\'', + '\'+define+OUT_TMP8=\"' + test.obj_dir + '/tmp8.mem\"\'', +]) + +test.execute() + +for i in range(1, 9): + gold = test.t_dir + "/t_sys_writemem_b.gold" + str(i) + ".mem" + out = test.obj_dir + "/tmp" + str(i) + ".mem" + test.files_identical(out, gold) + +test.passes() diff --git a/test_regress/t/t_table_fsm.pl b/test_regress/t/t_table_fsm.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_table_fsm.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_table_fsm.py b/test_regress/t/t_table_fsm.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_table_fsm.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tagged.pl b/test_regress/t/t_tagged.pl deleted file mode 100755 index 877e6133a..000000000 --- a/test_regress/t/t_tagged.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tagged.py b/test_regress/t/t_tagged.py new file mode 100755 index 000000000..710a094ab --- /dev/null +++ b/test_regress/t/t_tagged.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_threads_counter_0.pl b/test_regress/t/t_threads_counter_0.pl deleted file mode 100755 index ed4dedd9c..000000000 --- a/test_regress/t/t_threads_counter_0.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_threads_counter.v"); - -compile( - verilator_flags2 => ['--cc'], - threads => 1, - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_threads_counter_0.py b/test_regress/t/t_threads_counter_0.py new file mode 100755 index 000000000..0dfdcdbb2 --- /dev/null +++ b/test_regress/t/t_threads_counter_0.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_threads_counter.v" + +test.compile(verilator_flags2=['--cc'], threads=1) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_threads_counter_1.pl b/test_regress/t/t_threads_counter_1.pl deleted file mode 100755 index 4b41c24fa..000000000 --- a/test_regress/t/t_threads_counter_1.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vltmt => 1); - -top_filename("t/t_threads_counter.v"); - -compile( - verilator_flags2 => ['--cc'], - threads => 1 - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_threads_counter_1.py b/test_regress/t/t_threads_counter_1.py new file mode 100755 index 000000000..7cbd7389e --- /dev/null +++ b/test_regress/t/t_threads_counter_1.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vltmt') +test.top_filename = "t/t_threads_counter.v" + +test.compile(verilator_flags2=['--cc'], threads=1) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_threads_counter_2.pl b/test_regress/t/t_threads_counter_2.pl deleted file mode 100755 index 97f70bfaf..000000000 --- a/test_regress/t/t_threads_counter_2.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vltmt => 1); - -top_filename("t/t_threads_counter.v"); - -compile( - verilator_flags2 => ['--cc'], - threads => 2 - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_threads_counter_2.py b/test_regress/t/t_threads_counter_2.py new file mode 100755 index 000000000..d4ab7e2ba --- /dev/null +++ b/test_regress/t/t_threads_counter_2.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vltmt') +test.top_filename = "t/t_threads_counter.v" + +test.compile(verilator_flags2=['--cc'], threads=2) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_threads_counter_4.pl b/test_regress/t/t_threads_counter_4.pl deleted file mode 100755 index 7efd91cd9..000000000 --- a/test_regress/t/t_threads_counter_4.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vltmt => 1); - -top_filename("t/t_threads_counter.v"); - -compile( - verilator_flags2 => ['--cc'], - threads => 4 - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_threads_counter_4.py b/test_regress/t/t_threads_counter_4.py new file mode 100755 index 000000000..50e637eae --- /dev/null +++ b/test_regress/t/t_threads_counter_4.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vltmt') +test.top_filename = "t/t_threads_counter.v" + +test.compile(verilator_flags2=['--cc'], threads=4) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_threads_crazy.pl b/test_regress/t/t_threads_crazy.pl deleted file mode 100755 index c72858f2c..000000000 --- a/test_regress/t/t_threads_crazy.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vltmt => 1); - -compile( - verilator_flags2 => ['--cc'], - threads => 4, - context_threads => 2 - ); - -execute( - fails => 1 - ); - -file_grep($Self->{run_log_filename}, qr/%Error: .*\/verilated\.cpp:\d+: VerilatedContext has 2 threads but model 'Vt_threads_crazy' \(instantiated as 'top'\) was Verilated with --threads 4\./); -ok(1); -1; diff --git a/test_regress/t/t_threads_crazy.py b/test_regress/t/t_threads_crazy.py new file mode 100755 index 000000000..625fc874d --- /dev/null +++ b/test_regress/t/t_threads_crazy.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vltmt') + +test.compile(verilator_flags2=['--cc'], threads=4, context_threads=2) + +test.execute(fails=True) + +test.file_grep( + test.run_log_filename, + r"%Error: .*\/verilated\.cpp:\d+: VerilatedContext has 2 threads but model 'Vt_threads_crazy' \(instantiated as 'top'\) was Verilated with --threads 4\." +) + +test.passes() diff --git a/test_regress/t/t_threads_crazy_context.pl b/test_regress/t/t_threads_crazy_context.pl deleted file mode 100755 index e92f3aebf..000000000 --- a/test_regress/t/t_threads_crazy_context.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_threads_crazy.v"); - -compile( - verilator_flags2 => ['--cc'], - threads => $Self->{vltmt} ? 2 : 1, - context_threads => 1024 - ); - -execute( - ); - -if ($Self->{vltmt}) { - file_grep($Self->{run_log_filename}, qr/System has \d+ hardware threads but simulation thread count set to 1024\. This will likely cause significant slowdown\./); -} - -ok(1); -1; diff --git a/test_regress/t/t_threads_crazy_context.py b/test_regress/t/t_threads_crazy_context.py new file mode 100755 index 000000000..6ef9e273d --- /dev/null +++ b/test_regress/t/t_threads_crazy_context.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_threads_crazy.v" + +test.compile(verilator_flags2=['--cc'], threads=(2 if test.vltmt else 1), context_threads=1024) + +test.execute() + +if test.vltmt: + test.file_grep( + test.run_log_filename, + r'System has \d+ hardware threads but simulation thread count set to 1024\. This will likely cause significant slowdown\.' + ) + +test.passes() diff --git a/test_regress/t/t_threads_nondeterminism.pl b/test_regress/t/t_threads_nondeterminism.pl deleted file mode 100755 index 202a0adb0..000000000 --- a/test_regress/t/t_threads_nondeterminism.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vltmt => 1); - -top_filename("t/t_threads_counter.v"); - -compile( - verilator_flags2 => ['--cc --debug-nondeterminism --no-skip-identical'], - threads => 2 - ); - -execute( - ); - -file_grep("$Self->{obj_dir}/vlt_compile.log", qr/Hash of shape/); - -ok(1); -1; diff --git a/test_regress/t/t_threads_nondeterminism.py b/test_regress/t/t_threads_nondeterminism.py new file mode 100755 index 000000000..f0a847a26 --- /dev/null +++ b/test_regress/t/t_threads_nondeterminism.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vltmt') +test.top_filename = "t/t_threads_counter.v" + +test.compile(verilator_flags2=['--cc --debug-nondeterminism --no-skip-identical'], threads=2) + +test.execute() + +test.file_grep(test.obj_dir + "/vlt_compile.log", r'Hash of shape') + +test.passes() diff --git a/test_regress/t/t_time.pl b/test_regress/t/t_time.pl deleted file mode 100755 index 564c09ea7..000000000 --- a/test_regress/t/t_time.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_time.py b/test_regress/t/t_time.py new file mode 100755 index 000000000..88cfbe63f --- /dev/null +++ b/test_regress/t/t_time.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_time_literals.pl b/test_regress/t/t_time_literals.pl deleted file mode 100755 index 7e8b0e7e2..000000000 --- a/test_regress/t/t_time_literals.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_time_literals.py b/test_regress/t/t_time_literals.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_time_literals.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_time_passed.pl b/test_regress/t/t_time_passed.pl deleted file mode 100755 index 0dd6234fe..000000000 --- a/test_regress/t/t_time_passed.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_time_passed.py b/test_regress/t/t_time_passed.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_time_passed.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_time_print.pl b/test_regress/t/t_time_print.pl deleted file mode 100755 index 0dd6234fe..000000000 --- a/test_regress/t/t_time_print.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_time_print.py b/test_regress/t/t_time_print.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_time_print.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_time_sc_bad.pl b/test_regress/t/t_time_sc_bad.pl deleted file mode 100755 index 1c293ef05..000000000 --- a/test_regress/t/t_time_sc_bad.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_time_sc.v"); - -$Self->{sc_time_resolution} = 'SC_NS'; - -compile( - verilator_flags2 => ['-sc', '-timescale 1ps/1ps', # Mismatch w/sc_time_resolution - '+define+TEST_EXPECT=2us'], - ); - -execute( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_time_sc_bad.py b/test_regress/t/t_time_sc_bad.py new file mode 100755 index 000000000..0ca15940f --- /dev/null +++ b/test_regress/t/t_time_sc_bad.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_time_sc.v" + +test.sc_time_resolution = 'SC_NS' + +test.compile(verilator_flags2=[ + '-sc', + '-timescale 1ps/1ps', # Mismatch w/sc_time_resolution + '+define+TEST_EXPECT=2us' +]) + +test.execute(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_time_sc_bad_mt.pl b/test_regress/t/t_time_sc_bad_mt.pl deleted file mode 100755 index 6b6f6d637..000000000 --- a/test_regress/t/t_time_sc_bad_mt.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vltmt => 1); - -top_filename("t/t_time_sc.v"); - -$Self->{sc_time_resolution} = 'SC_NS'; - -compile( - verilator_flags2 => ['-sc', '-timescale 1ps/1ps', # Mismatch w/sc_time_resolution - '+define+TEST_EXPECT=2us'], - threads => 2, - ); - -execute( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_time_sc_bad_mt.py b/test_regress/t/t_time_sc_bad_mt.py new file mode 100755 index 000000000..cf927d9fa --- /dev/null +++ b/test_regress/t/t_time_sc_bad_mt.py @@ -0,0 +1,27 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vltmt') +test.top_filename = "t/t_time_sc.v" + +test.sc_time_resolution = 'SC_NS' + +test.compile( + verilator_flags2=[ + '-sc', + '-timescale 1ps/1ps', # Mismatch w/sc_time_resolution + '+define+TEST_EXPECT=2us' + ], + threads=2) + +test.execute(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_time_sc_fs.pl b/test_regress/t/t_time_sc_fs.pl deleted file mode 100755 index 4e80c2001..000000000 --- a/test_regress/t/t_time_sc_fs.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_time_sc.v"); - -$Self->{sc_time_resolution} = 'SC_FS'; - -compile( - verilator_flags2 => ['-sc', '-timescale 1fs/1fs', - '+define+TEST_EXPECT=20fs'], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_time_sc_fs.py b/test_regress/t/t_time_sc_fs.py new file mode 100755 index 000000000..70225625c --- /dev/null +++ b/test_regress/t/t_time_sc_fs.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_time_sc.v" + +test.sc_time_resolution = 'SC_FS' + +test.compile(verilator_flags2=['-sc', '-timescale 1fs/1fs', '+define+TEST_EXPECT=20fs']) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_time_sc_ms.pl b/test_regress/t/t_time_sc_ms.pl deleted file mode 100755 index ddd848ef3..000000000 --- a/test_regress/t/t_time_sc_ms.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_time_sc.v"); - -$Self->{sc_time_resolution} = 'SC_MS'; - -compile( - verilator_flags2 => ['-sc', '-timescale 1ms/1ms', - '+define+TEST_EXPECT=20ms'], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_time_sc_ms.py b/test_regress/t/t_time_sc_ms.py new file mode 100755 index 000000000..8027dd32b --- /dev/null +++ b/test_regress/t/t_time_sc_ms.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_time_sc.v" + +test.sc_time_resolution = 'SC_MS' + +test.compile(verilator_flags2=['-sc', '-timescale 1ms/1ms', '+define+TEST_EXPECT=20ms']) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_time_sc_ns.pl b/test_regress/t/t_time_sc_ns.pl deleted file mode 100755 index 8b64e99de..000000000 --- a/test_regress/t/t_time_sc_ns.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_time_sc.v"); - -$Self->{sc_time_resolution} = 'SC_NS'; - -compile( - verilator_flags2 => ['-sc', '-timescale 1ns/1ns', - '+define+TEST_EXPECT=20ns'], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_time_sc_ns.py b/test_regress/t/t_time_sc_ns.py new file mode 100755 index 000000000..5db5c0710 --- /dev/null +++ b/test_regress/t/t_time_sc_ns.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_time_sc.v" + +test.sc_time_resolution = 'SC_NS' + +test.compile(verilator_flags2=['-sc', '-timescale 1ns/1ns', '+define+TEST_EXPECT=20ns']) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_time_sc_sec.pl b/test_regress/t/t_time_sc_sec.pl deleted file mode 100755 index eeb148d71..000000000 --- a/test_regress/t/t_time_sc_sec.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_time_sc.v"); - -$Self->{sc_time_resolution} = 'SC_SEC'; - -compile( - verilator_flags2 => ['-sc', '-timescale 1s/1s', - '+define+TEST_EXPECT=20s'], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_time_sc_sec.py b/test_regress/t/t_time_sc_sec.py new file mode 100755 index 000000000..4dc51c0c4 --- /dev/null +++ b/test_regress/t/t_time_sc_sec.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_time_sc.v" + +test.sc_time_resolution = 'SC_SEC' + +test.compile(verilator_flags2=['-sc', '-timescale 1s/1s', '+define+TEST_EXPECT=20s']) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_time_sc_us.pl b/test_regress/t/t_time_sc_us.pl deleted file mode 100755 index 77e1b89d2..000000000 --- a/test_regress/t/t_time_sc_us.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_time_sc.v"); - -$Self->{sc_time_resolution} = 'SC_US'; - -compile( - verilator_flags2 => ['-sc', '-timescale 1us/1us', - '+define+TEST_EXPECT=20us'], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_time_sc_us.py b/test_regress/t/t_time_sc_us.py new file mode 100755 index 000000000..c93e31e4e --- /dev/null +++ b/test_regress/t/t_time_sc_us.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_time_sc.v" + +test.sc_time_resolution = 'SC_US' + +test.compile(verilator_flags2=['-sc', '-timescale 1us/1us', '+define+TEST_EXPECT=20us']) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_time_stamp64.pl b/test_regress/t/t_time_stamp64.pl deleted file mode 100755 index 105781f27..000000000 --- a/test_regress/t/t_time_stamp64.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -# Verilator before 4.033 had 'double sc_time_stamp()', make sure new form compiles -$self->{vl_time_stamp64} = 1; - -compile( - verilator_flags2 => ['-DVL_TIME_STAMP64=1'], - ); - -execute( - ); - -ok(1); - -1; diff --git a/test_regress/t/t_time_stamp64.py b/test_regress/t/t_time_stamp64.py new file mode 100755 index 000000000..b1ae8bfb1 --- /dev/null +++ b/test_regress/t/t_time_stamp64.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +# Verilator before 4.033 had 'double sc_time_stamp()', make sure new form compiles +test.vl_time_stamp64 = True + +test.compile(verilator_flags2=['-DVL_TIME_STAMP64=1']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_time_stamp_double.pl b/test_regress/t/t_time_stamp_double.pl deleted file mode 100755 index 053a247fe..000000000 --- a/test_regress/t/t_time_stamp_double.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename('t/t_time_stamp64.v'); - -# Verilator before 4.033 had 'double sc_time_stamp()', make sure this still compiles -$self->{vl_time_stamp64} = 0; - -compile( - verilator_flags2 => [], - ); - -execute( - ); - -ok(1); - -1; diff --git a/test_regress/t/t_time_stamp_double.py b/test_regress/t/t_time_stamp_double.py new file mode 100755 index 000000000..860803ab8 --- /dev/null +++ b/test_regress/t/t_time_stamp_double.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = 't/t_time_stamp64.v' + +# Verilator before 4.033 had 'double sc_time_stamp()', make sure this still compiles +test.vl_time_stamp64 = False + +test.compile(verilator_flags2=[]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_time_timeunit.pl b/test_regress/t/t_time_timeunit.pl deleted file mode 100755 index 9a67c9c44..000000000 --- a/test_regress/t/t_time_timeunit.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); - -1; diff --git a/test_regress/t/t_time_timeunit.py b/test_regress/t/t_time_timeunit.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_time_timeunit.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_time_vpi_100s10ms.pl b/test_regress/t/t_time_vpi_100s10ms.pl deleted file mode 100755 index 8a7efff09..000000000 --- a/test_regress/t/t_time_vpi_100s10ms.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator_st => 1); - -top_filename("t/t_time_vpi.v"); - -$Self->{main_time_multiplier} = 100e0 / 10e-6; - -compile( - v_flags2 => ['+define+time_scale_units=100s +define+time_scale_prec=10ms', - 't/t_time_vpi_c.cpp'], - verilator_flags2 => ['--vpi'], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_time_vpi_100s10ms.py b/test_regress/t/t_time_vpi_100s10ms.py new file mode 100755 index 000000000..cfcf44e95 --- /dev/null +++ b/test_regress/t/t_time_vpi_100s10ms.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.pli_filename = "t/t_time_vpi_c.cpp" +test.top_filename = "t/t_time_vpi.v" +test.main_time_multiplier = 100e0 / 10e-6 + +test.compile( + v_flags2=['+define+time_scale_units=100s +define+time_scale_prec=10ms', test.pli_filename], + verilator_flags2=['--vpi']) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_time_vpi_10ms10ns.pl b/test_regress/t/t_time_vpi_10ms10ns.pl deleted file mode 100755 index d3a705b12..000000000 --- a/test_regress/t/t_time_vpi_10ms10ns.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator_st => 1); - -top_filename("t/t_time_vpi.v"); - -$Self->{main_time_multiplier} = 10e-3 / 10e-9; - -compile( - v_flags2 => ['+define+time_scale_units=10ms +define+time_scale_prec=10ns', - 't/t_time_vpi_c.cpp'], - verilator_flags2 => ['--vpi'], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_time_vpi_10ms10ns.py b/test_regress/t/t_time_vpi_10ms10ns.py new file mode 100755 index 000000000..1851ccf3e --- /dev/null +++ b/test_regress/t/t_time_vpi_10ms10ns.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.pli_filename = "t/t_time_vpi_c.cpp" +test.top_filename = "t/t_time_vpi.v" +test.main_time_multiplier = 10e-3 / 10e-9 + +test.compile( + v_flags2=['+define+time_scale_units=10ms +define+time_scale_prec=10ns', test.pli_filename], + verilator_flags2=['--vpi']) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_time_vpi_1fs1fs.pl b/test_regress/t/t_time_vpi_1fs1fs.pl deleted file mode 100755 index 951ad8b59..000000000 --- a/test_regress/t/t_time_vpi_1fs1fs.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator_st => 1); - -top_filename("t/t_time_vpi.v"); - -$Self->{main_time_multiplier} = 1e-15 / 1e-15; - -compile( - v_flags2 => ['+define+time_scale_units=1fs +define+time_scale_prec=1fs', - 't/t_time_vpi_c.cpp'], - verilator_flags2 => ['--vpi'], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_time_vpi_1fs1fs.py b/test_regress/t/t_time_vpi_1fs1fs.py new file mode 100755 index 000000000..c95d44318 --- /dev/null +++ b/test_regress/t/t_time_vpi_1fs1fs.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.pli_filename = "t/t_time_vpi_c.cpp" +test.top_filename = "t/t_time_vpi.v" +test.main_time_multiplier = 1e-15 / 1e-15 + +test.compile( + v_flags2=['+define+time_scale_units=1fs +define+time_scale_prec=1fs', test.pli_filename], + verilator_flags2=['--vpi']) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_time_vpi_1ms10ns.pl b/test_regress/t/t_time_vpi_1ms10ns.pl deleted file mode 100755 index 77db73099..000000000 --- a/test_regress/t/t_time_vpi_1ms10ns.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator_st => 1); - -top_filename("t/t_time_vpi.v"); - -$Self->{main_time_multiplier} = 1e-3 / 10e-9; - -compile( - v_flags2 => ['+define+time_scale_units=1ms +define+time_scale_prec=10ns', - 't/t_time_vpi_c.cpp'], - verilator_flags2 => ['--vpi --trace'], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -file_grep($Self->trace_filename, qr!timescale +10ns!); - -ok(1); - -1; diff --git a/test_regress/t/t_time_vpi_1ms10ns.py b/test_regress/t/t_time_vpi_1ms10ns.py new file mode 100755 index 000000000..b7460eb4e --- /dev/null +++ b/test_regress/t/t_time_vpi_1ms10ns.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.pli_filename = "t/t_time_vpi_c.cpp" +test.top_filename = "t/t_time_vpi.v" +test.main_time_multiplier = 1e-3 / 10e-9 + +test.compile( + v_flags2=['+define+time_scale_units=1ms +define+time_scale_prec=10ns', test.pli_filename], + verilator_flags2=['--vpi --trace']) + +test.execute(expect_filename=test.golden_filename) + +test.file_grep(test.trace_filename, r'timescale +10ns') + +test.passes() diff --git a/test_regress/t/t_time_vpi_1ns1ns.pl b/test_regress/t/t_time_vpi_1ns1ns.pl deleted file mode 100755 index d35ce9bf4..000000000 --- a/test_regress/t/t_time_vpi_1ns1ns.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator_st => 1); - -top_filename("t/t_time_vpi.v"); - -$Self->{main_time_multiplier} = 1e-9 / 1e-9; - -compile( - v_flags2 => ['+define+time_scale_units=1ns +define+time_scale_prec=1ns', - 't/t_time_vpi_c.cpp'], - verilator_flags2 => ['--vpi --trace'], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -file_grep($Self->trace_filename, qr!timescale +1ns!); - -ok(1); - -1; diff --git a/test_regress/t/t_time_vpi_1ns1ns.py b/test_regress/t/t_time_vpi_1ns1ns.py new file mode 100755 index 000000000..ac7e49500 --- /dev/null +++ b/test_regress/t/t_time_vpi_1ns1ns.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.pli_filename = "t/t_time_vpi_c.cpp" +test.top_filename = "t/t_time_vpi.v" +test.main_time_multiplier = 1e-9 / 1e-9 + +test.compile( + v_flags2=['+define+time_scale_units=1ns +define+time_scale_prec=1ns', test.pli_filename], + verilator_flags2=['--vpi --trace']) + +test.execute(expect_filename=test.golden_filename) + +test.file_grep(test.trace_filename, r'timescale +1ns') + +test.passes() diff --git a/test_regress/t/t_time_vpi_1ps1fs.pl b/test_regress/t/t_time_vpi_1ps1fs.pl deleted file mode 100755 index 5e34c7e64..000000000 --- a/test_regress/t/t_time_vpi_1ps1fs.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator_st => 1); - -top_filename("t/t_time_vpi.v"); - -$Self->{main_time_multiplier} = 1e-12 / 10e-15; - -compile( - v_flags2 => ['+define+time_scale_units=1ps +define+time_scale_prec=1fs', - 't/t_time_vpi_c.cpp'], - verilator_flags2 => ['--vpi'], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_time_vpi_1ps1fs.py b/test_regress/t/t_time_vpi_1ps1fs.py new file mode 100755 index 000000000..a85054b1c --- /dev/null +++ b/test_regress/t/t_time_vpi_1ps1fs.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.pli_filename = "t/t_time_vpi_c.cpp" +test.top_filename = "t/t_time_vpi.v" +test.main_time_multiplier = 1e-12 / 10e-15 + +test.compile( + v_flags2=['+define+time_scale_units=1ps +define+time_scale_prec=1fs', test.pli_filename], + verilator_flags2=['--vpi']) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_time_vpi_1s10ns.pl b/test_regress/t/t_time_vpi_1s10ns.pl deleted file mode 100755 index 3d41bb518..000000000 --- a/test_regress/t/t_time_vpi_1s10ns.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator_st => 1); - -top_filename("t/t_time_vpi.v"); - -$Self->{main_time_multiplier} = 1e0 / 10e-9; - -compile( - v_flags2 => ['+define+time_scale_units=1s +define+time_scale_prec=10ns', - 't/t_time_vpi_c.cpp'], - verilator_flags2 => ['--vpi'], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_time_vpi_1s10ns.py b/test_regress/t/t_time_vpi_1s10ns.py new file mode 100755 index 000000000..ebed040b9 --- /dev/null +++ b/test_regress/t/t_time_vpi_1s10ns.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.pli_filename = "t/t_time_vpi_c.cpp" +test.top_filename = "t/t_time_vpi.v" +test.main_time_multiplier = 1e0 / 10e-9 + +test.compile( + v_flags2=['+define+time_scale_units=1s +define+time_scale_prec=10ns', test.pli_filename], + verilator_flags2=['--vpi']) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_time_vpi_1us1ns.pl b/test_regress/t/t_time_vpi_1us1ns.pl deleted file mode 100755 index 7d58ba3f3..000000000 --- a/test_regress/t/t_time_vpi_1us1ns.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator_st => 1); - -top_filename("t/t_time_vpi.v"); - -$Self->{main_time_multiplier} = 1e-6 / 1e-9; - -compile( - v_flags2 => ['+define+time_scale_units=1us +define+time_scale_prec=1ns', - 't/t_time_vpi_c.cpp'], - verilator_flags2 => ['--vpi'], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_time_vpi_1us1ns.py b/test_regress/t/t_time_vpi_1us1ns.py new file mode 100755 index 000000000..547804dae --- /dev/null +++ b/test_regress/t/t_time_vpi_1us1ns.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.pli_filename = "t/t_time_vpi_c.cpp" +test.top_filename = "t/t_time_vpi.v" +test.main_time_multiplier = 1e-6 / 1e-9 + +test.compile( + v_flags2=['+define+time_scale_units=1us +define+time_scale_prec=1ns', test.pli_filename], + verilator_flags2=['--vpi']) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_timescale_default.pl b/test_regress/t/t_timescale_default.pl deleted file mode 100755 index 0dd6234fe..000000000 --- a/test_regress/t/t_timescale_default.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_timescale_default.py b/test_regress/t/t_timescale_default.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_timescale_default.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_timescale_lint.pl b/test_regress/t/t_timescale_lint.pl deleted file mode 100755 index 051f08f78..000000000 --- a/test_regress/t/t_timescale_lint.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only --timescale-override 1ns/1ns"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_timescale_lint.py b/test_regress/t/t_timescale_lint.py new file mode 100755 index 000000000..5e513aa7c --- /dev/null +++ b/test_regress/t/t_timescale_lint.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only --timescale-override 1ns/1ns"]) + +test.passes() diff --git a/test_regress/t/t_timescale_lint2.pl b/test_regress/t/t_timescale_lint2.pl deleted file mode 100755 index 6a8798deb..000000000 --- a/test_regress/t/t_timescale_lint2.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -top_filename("t/t_timescale_lint.v"); - -lint( - verilator_flags2 => ["--lint-only --timescale 1ns/1ns"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_timescale_lint2.py b/test_regress/t/t_timescale_lint2.py new file mode 100755 index 000000000..6e393030b --- /dev/null +++ b/test_regress/t/t_timescale_lint2.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_timescale_lint.v" + +test.lint(verilator_flags2=["--lint-only --timescale 1ns/1ns"]) + +test.passes() diff --git a/test_regress/t/t_timescale_lint_bad.pl b/test_regress/t/t_timescale_lint_bad.pl deleted file mode 100755 index 022ca4683..000000000 --- a/test_regress/t/t_timescale_lint_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -top_filename("t/t_timescale_lint.v"); - -lint( - verilator_flags2 => ["--lint-only"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timescale_lint_bad.py b/test_regress/t/t_timescale_lint_bad.py new file mode 100755 index 000000000..8842c380b --- /dev/null +++ b/test_regress/t/t_timescale_lint_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_timescale_lint.v" + +test.lint(verilator_flags2=["--lint-only"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_timescale_parse.pl b/test_regress/t/t_timescale_parse.pl deleted file mode 100755 index 80d73f08e..000000000 --- a/test_regress/t/t_timescale_parse.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_timescale_parse.py b/test_regress/t/t_timescale_parse.py new file mode 100755 index 000000000..f37ad07c8 --- /dev/null +++ b/test_regress/t/t_timescale_parse.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timescale_parse_bad.pl b/test_regress/t/t_timescale_parse_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_timescale_parse_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timescale_parse_bad.py b/test_regress/t/t_timescale_parse_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_timescale_parse_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_timescale_udp.pl b/test_regress/t/t_timescale_udp.pl deleted file mode 100755 index 9a67c9c44..000000000 --- a/test_regress/t/t_timescale_udp.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); - -1; diff --git a/test_regress/t/t_timescale_udp.py b/test_regress/t/t_timescale_udp.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_timescale_udp.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timescale_unit.pl b/test_regress/t/t_timescale_unit.pl deleted file mode 100755 index 0dd6234fe..000000000 --- a/test_regress/t/t_timescale_unit.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_timescale_unit.py b/test_regress/t/t_timescale_unit.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_timescale_unit.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_timing_always.pl b/test_regress/t/t_timing_always.pl deleted file mode 100755 index 21a2189cc..000000000 --- a/test_regress/t/t_timing_always.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_always.py b/test_regress/t/t_timing_always.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_timing_always.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_class.pl b/test_regress/t/t_timing_class.pl deleted file mode 100755 index d3fae3953..000000000 --- a/test_regress/t/t_timing_class.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_class.py b/test_regress/t/t_timing_class.py new file mode 100755 index 000000000..664ad3bec --- /dev/null +++ b/test_regress/t/t_timing_class.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_class_static_delay.pl b/test_regress/t/t_timing_class_static_delay.pl deleted file mode 100755 index d3fae3953..000000000 --- a/test_regress/t/t_timing_class_static_delay.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_class_static_delay.py b/test_regress/t/t_timing_class_static_delay.py new file mode 100755 index 000000000..664ad3bec --- /dev/null +++ b/test_regress/t/t_timing_class_static_delay.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_clkgen1.pl b/test_regress/t/t_timing_clkgen1.pl deleted file mode 100755 index 4aa32b018..000000000 --- a/test_regress/t/t_timing_clkgen1.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing -Wno-MINTYPMAXDLY"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_clkgen1.py b/test_regress/t/t_timing_clkgen1.py new file mode 100755 index 000000000..19a494154 --- /dev/null +++ b/test_regress/t/t_timing_clkgen1.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing -Wno-MINTYPMAXDLY"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_clkgen2.pl b/test_regress/t/t_timing_clkgen2.pl deleted file mode 100755 index 21a2189cc..000000000 --- a/test_regress/t/t_timing_clkgen2.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_clkgen2.py b/test_regress/t/t_timing_clkgen2.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_timing_clkgen2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_clkgen3.pl b/test_regress/t/t_timing_clkgen3.pl deleted file mode 100755 index 21a2189cc..000000000 --- a/test_regress/t/t_timing_clkgen3.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_clkgen3.py b/test_regress/t/t_timing_clkgen3.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_timing_clkgen3.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_clkgen_sc.pl b/test_regress/t/t_timing_clkgen_sc.pl deleted file mode 100755 index 619374e4c..000000000 --- a/test_regress/t/t_timing_clkgen_sc.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_timing_clkgen2.v"); - -compile( - verilator_flags2 => ["--sc --exe --timing --timescale 10ps/1ps"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_clkgen_sc.py b/test_regress/t/t_timing_clkgen_sc.py new file mode 100755 index 000000000..f64e24169 --- /dev/null +++ b/test_regress/t/t_timing_clkgen_sc.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_timing_clkgen2.v" + +test.compile(verilator_flags2=["--sc --exe --timing --timescale 10ps/1ps"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_clkgen_unsup.pl b/test_regress/t/t_timing_clkgen_unsup.pl deleted file mode 100755 index b380d0484..000000000 --- a/test_regress/t/t_timing_clkgen_unsup.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -top_filename("t/t_timing_clkgen1.v"); - -lint( - verilator_flags2 => ["--timing"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_clkgen_unsup.py b/test_regress/t/t_timing_clkgen_unsup.py new file mode 100755 index 000000000..3d960dc96 --- /dev/null +++ b/test_regress/t/t_timing_clkgen_unsup.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_timing_clkgen1.v" + +test.lint(verilator_flags2=["--timing"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_timing_cmake.pl b/test_regress/t/t_timing_cmake.pl deleted file mode 100755 index acd0f0d36..000000000 --- a/test_regress/t/t_timing_cmake.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_coroutines) { - skip("No coroutine support"); -} elsif (!$Self->have_cmake) { - skip("cmake is not installed"); -} else { - top_filename("t/t_timing_events.v"); - - compile( - verilator_flags2 => ["--timescale 10ns/1ns --main --timing"], - verilator_make_gmake => 0, - verilator_make_cmake => 1, - ); -} - -ok(1); -1; diff --git a/test_regress/t/t_timing_cmake.py b/test_regress/t/t_timing_cmake.py new file mode 100755 index 000000000..01e454245 --- /dev/null +++ b/test_regress/t/t_timing_cmake.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_timing_events.v" + +if not test.have_coroutines: + test.skip("No coroutine support") +if not test.have_cmake: + test.skip("cmake is not installed") + +test.compile(verilator_flags2=["--timescale 10ns/1ns --main --timing"], + verilator_make_gmake=False, + verilator_make_cmake=True) + +test.passes() diff --git a/test_regress/t/t_timing_debug1.pl b/test_regress/t/t_timing_debug1.pl deleted file mode 100755 index d5d5d4e8b..000000000 --- a/test_regress/t/t_timing_debug1.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_timing_sched.v"); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - all_run_flags => ["+verilator+debug"], - ); - -if (!$Self->{vltmt}) { # vltmt output may vary between thread exec order - files_identical("$Self->{obj_dir}/vlt_sim.log", $Self->{golden_filename}, "logfile"); -} - -ok(1); -1; diff --git a/test_regress/t/t_timing_debug1.py b/test_regress/t/t_timing_debug1.py new file mode 100755 index 000000000..edded70be --- /dev/null +++ b/test_regress/t/t_timing_debug1.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_timing_sched.v" + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute(all_run_flags=["+verilator+debug"]) + +if not test.vltmt: # vltmt output may vary between thread exec order + test.files_identical(test.obj_dir + "/vlt_sim.log", test.golden_filename, "logfile") + +test.passes() diff --git a/test_regress/t/t_timing_debug2.pl b/test_regress/t/t_timing_debug2.pl deleted file mode 100755 index d7e052101..000000000 --- a/test_regress/t/t_timing_debug2.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_timing_class.v"); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - all_run_flags => ["+verilator+debug"], - ); - -if (!$Self->{vltmt}) { # vltmt output may vary between thread exec order - files_identical("$Self->{obj_dir}/vlt_sim.log", $Self->{golden_filename}, "logfile"); -} - -ok(1); -1; diff --git a/test_regress/t/t_timing_debug2.py b/test_regress/t/t_timing_debug2.py new file mode 100755 index 000000000..e6f816ca2 --- /dev/null +++ b/test_regress/t/t_timing_debug2.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_timing_class.v" + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute(all_run_flags=["+verilator+debug"]) + +if not test.vltmt: # vltmt output may vary between thread exec order + test.files_identical(test.obj_dir + "/vlt_sim.log", test.golden_filename, "logfile") + +test.passes() diff --git a/test_regress/t/t_timing_delay_callstack.pl b/test_regress/t/t_timing_delay_callstack.pl deleted file mode 100755 index 21a2189cc..000000000 --- a/test_regress/t/t_timing_delay_callstack.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_delay_callstack.py b/test_regress/t/t_timing_delay_callstack.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_timing_delay_callstack.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_dlyassign.pl b/test_regress/t/t_timing_dlyassign.pl deleted file mode 100755 index 21a2189cc..000000000 --- a/test_regress/t/t_timing_dlyassign.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_dlyassign.py b/test_regress/t/t_timing_dlyassign.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_timing_dlyassign.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_dpi_unsup.pl b/test_regress/t/t_timing_dpi_unsup.pl deleted file mode 100755 index a6399f3f7..000000000 --- a/test_regress/t/t_timing_dpi_unsup.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -top_filename("t/t_timing_dpi_unsup.v"); - -lint( - verilator_flags2 => ["--timing"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_dpi_unsup.py b/test_regress/t/t_timing_dpi_unsup.py new file mode 100755 index 000000000..f0fcfa7f8 --- /dev/null +++ b/test_regress/t/t_timing_dpi_unsup.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_timing_dpi_unsup.v" + +test.lint(verilator_flags2=["--timing"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_timing_dynscope.pl b/test_regress/t/t_timing_dynscope.pl deleted file mode 100755 index 21a2189cc..000000000 --- a/test_regress/t/t_timing_dynscope.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_dynscope.py b/test_regress/t/t_timing_dynscope.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_timing_dynscope.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_events.pl b/test_regress/t/t_timing_events.pl deleted file mode 100755 index d3fae3953..000000000 --- a/test_regress/t/t_timing_events.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_events.py b/test_regress/t/t_timing_events.py new file mode 100755 index 000000000..664ad3bec --- /dev/null +++ b/test_regress/t/t_timing_events.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_fork_comb.pl b/test_regress/t/t_timing_fork_comb.pl deleted file mode 100755 index 6adc63381..000000000 --- a/test_regress/t/t_timing_fork_comb.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -# Should convert the first always into combo and detect cycle -compile( - fails => 1, - verilator_flags2 => ["--timing"], - expect => - '%Warning-UNOPTFLAT: t/t_timing_fork_comb.v:\d+:\d+: Signal unoptimizable: Circular combinational logic:' - ); - -compile( - verilator_flags2 => ["--exe --main --timing -Wno-UNOPTFLAT"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_fork_comb.py b/test_regress/t/t_timing_fork_comb.py new file mode 100755 index 000000000..224405dec --- /dev/null +++ b/test_regress/t/t_timing_fork_comb.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +# Should convert the first always into combo and detect cycle +test.compile( + fails=True, + verilator_flags2=["--timing"], + expect= + r'%Warning-UNOPTFLAT: t/t_timing_fork_comb.v:\d+:\d+: Signal unoptimizable: Circular combinational logic:' +) + +test.compile(verilator_flags2=["--exe --main --timing -Wno-UNOPTFLAT"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_fork_join.pl b/test_regress/t/t_timing_fork_join.pl deleted file mode 100755 index 067c2a81f..000000000 --- a/test_regress/t/t_timing_fork_join.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_fork_join.py b/test_regress/t/t_timing_fork_join.py new file mode 100755 index 000000000..bded720e2 --- /dev/null +++ b/test_regress/t/t_timing_fork_join.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_timing_fork_join_forkproc.pl b/test_regress/t/t_timing_fork_join_forkproc.pl deleted file mode 100755 index 1048a1fe1..000000000 --- a/test_regress/t/t_timing_fork_join_forkproc.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_timing_fork_join.v"); - -compile( - verilator_flags2 => ["--exe --main --timing --ftaskify-all-forked"], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_fork_join_forkproc.py b/test_regress/t/t_timing_fork_join_forkproc.py new file mode 100755 index 000000000..75f4712aa --- /dev/null +++ b/test_regress/t/t_timing_fork_join_forkproc.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_timing_fork_join.v" + +test.compile(verilator_flags2=["--exe --main --timing --ftaskify-all-forked"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_timing_fork_many.pl b/test_regress/t/t_timing_fork_many.pl deleted file mode 100755 index 21a2189cc..000000000 --- a/test_regress/t/t_timing_fork_many.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_fork_many.py b/test_regress/t/t_timing_fork_many.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_timing_fork_many.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_fork_nba.pl b/test_regress/t/t_timing_fork_nba.pl deleted file mode 100755 index e23c975f9..000000000 --- a/test_regress/t/t_timing_fork_nba.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --timing"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_fork_nba.py b/test_regress/t/t_timing_fork_nba.py new file mode 100755 index 000000000..c12d9cce8 --- /dev/null +++ b/test_regress/t/t_timing_fork_nba.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --timing"]) + +test.passes() diff --git a/test_regress/t/t_timing_fork_no_timing_ctrl.pl b/test_regress/t/t_timing_fork_no_timing_ctrl.pl deleted file mode 100755 index 21a2189cc..000000000 --- a/test_regress/t/t_timing_fork_no_timing_ctrl.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_fork_no_timing_ctrl.py b/test_regress/t/t_timing_fork_no_timing_ctrl.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_timing_fork_no_timing_ctrl.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_fork_rec_method.pl b/test_regress/t/t_timing_fork_rec_method.pl deleted file mode 100755 index 21a2189cc..000000000 --- a/test_regress/t/t_timing_fork_rec_method.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_fork_rec_method.py b/test_regress/t/t_timing_fork_rec_method.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_timing_fork_rec_method.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_fork_taskcall.pl b/test_regress/t/t_timing_fork_taskcall.pl deleted file mode 100755 index 21a2189cc..000000000 --- a/test_regress/t/t_timing_fork_taskcall.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_fork_taskcall.py b/test_regress/t/t_timing_fork_taskcall.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_timing_fork_taskcall.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_func_bad.pl b/test_regress/t/t_timing_func_bad.pl deleted file mode 100755 index 0ee17366a..000000000 --- a/test_regress/t/t_timing_func_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - verilator_flags2 => ['--no-timing'], - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_func_bad.py b/test_regress/t/t_timing_func_bad.py new file mode 100755 index 000000000..7e3cbabde --- /dev/null +++ b/test_regress/t/t_timing_func_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename, verilator_flags2=['--no-timing']) + +test.passes() diff --git a/test_regress/t/t_timing_initial_always.pl b/test_regress/t/t_timing_initial_always.pl deleted file mode 100755 index 21a2189cc..000000000 --- a/test_regress/t/t_timing_initial_always.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_initial_always.py b/test_regress/t/t_timing_initial_always.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_timing_initial_always.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_intra_assign.pl b/test_regress/t/t_timing_intra_assign.pl deleted file mode 100755 index 6a7c671d8..000000000 --- a/test_regress/t/t_timing_intra_assign.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--binary"], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -compile( - verilator_flags2 => ["--binary -fno-localize"], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_intra_assign.py b/test_regress/t/t_timing_intra_assign.py new file mode 100755 index 000000000..2331869f2 --- /dev/null +++ b/test_regress/t/t_timing_intra_assign.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute(expect_filename=test.golden_filename) + +test.compile(verilator_flags2=["--binary -fno-localize"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_timing_localevent.pl b/test_regress/t/t_timing_localevent.pl deleted file mode 100755 index 9c8061375..000000000 --- a/test_regress/t/t_timing_localevent.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_localevent.py b/test_regress/t/t_timing_localevent.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_timing_localevent.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_long.pl b/test_regress/t/t_timing_long.pl deleted file mode 100755 index 5a1fcdf36..000000000 --- a/test_regress/t/t_timing_long.pl +++ /dev/null @@ -1,76 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -use IO::File; - -scenarios(simulator => 1); - -# Look for O(n^2) problems in process handling - -sub gen { - my $filename = shift; - - my $fh = IO::File->new(">$filename"); - $fh->print("// Generated by t_timing_long.pl\n"); - - $fh->print("\n"); - $fh->print("`ifdef TEST_VERBOSE\n"); - $fh->print(" `define MSG(m) \$display m\n"); - $fh->print("`else\n"); - $fh->print(" `define MSG(m)\n"); - $fh->print("`endif\n"); - $fh->print("\n"); - - $fh->print("module t;\n"); - $fh->print("\n"); - $fh->print(" int cnt;\n"); - $fh->print("\n"); - $fh->print(" initial begin\n"); - - my $n = 100; - for (my $i = 1; $i < $n; ++$i) { - # If statement around the timing is important to make the code scheduling - # mostly unpredictable - $fh->printf(" if (cnt == %d) begin\n", $i - 1); - $fh->printf(" #1; ++cnt; `MSG((\"[%0t] cnt?=${i}\", \$time));" - . " if (cnt != %d) \$stop;\n", $i); - $fh->printf(" end\n"); - } - - $fh->print("\n"); - $fh->print(' $write("*-* All Finished *-*\n");', "\n"); - $fh->print(' $finish;', "\n"); - $fh->print(" end\n"); - $fh->print("endmodule\n"); -} - -top_filename("$Self->{obj_dir}/t_timing_long.v"); - -gen($Self->{top_filename}); - -if ($Self->have_coroutines) { - compile( - verilator_flags2 => ["--exe --build --main --tim" . "ing"], - make_top => 1, - ); - - execute( - ); -} - -compile( - verilator_flags2 => ["--exe --build --main --no-timing -Wno-STMTDLY"], - make_top => 1, - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_long.py b/test_regress/t/t_timing_long.py new file mode 100755 index 000000000..a523eb21d --- /dev/null +++ b/test_regress/t/t_timing_long.py @@ -0,0 +1,63 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = test.obj_dir + "/t_timing_long.v" + +# Look for O(n^2) problems in process handling + + +def gen(filename): + with open(filename, 'w', encoding="utf8") as fh: + fh.write("// Generated by t_timing_long.py\n") + + fh.write("\n") + fh.write("`ifdef TEST_VERBOSE\n") + fh.write(" `define MSG(m) $display m\n") + fh.write("`else\n") + fh.write(" `define MSG(m)\n") + fh.write("`endif\n") + fh.write("\n") + + fh.write("module t;\n") + fh.write("\n") + fh.write(" int cnt;\n") + fh.write("\n") + fh.write(" initial begin\n") + + n = 100 + for i in range(1, n): + # If statement around the timing is important to make the code scheduling + # mostly unpredictable + fh.write(" if (cnt == " + str(i - 1) + ") begin\n") + fh.write(" #1; ++cnt; `MSG((\"[%0t] cnt?=" + str(i) + "\", $time));" + + " if (cnt != " + str(i) + ") $stop;\n") + fh.write(" end\n") + + fh.write("\n") + fh.write(' $write("*-* All Finished *-*\\n");' + "\n") + fh.write(" $finish;\n") + fh.write(" end\n") + fh.write("endmodule\n") + + +gen(test.top_filename) + +if test.have_coroutines: + test.compile(verilator_flags2=["--exe --build --main --timing"], make_top=1) + + test.execute() + +test.compile(verilator_flags2=["--exe --build --main --no-timing -Wno-STMTDLY"], make_top=1) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_nba_1.pl b/test_regress/t/t_timing_nba_1.pl deleted file mode 100755 index 21a2189cc..000000000 --- a/test_regress/t/t_timing_nba_1.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_nba_1.py b/test_regress/t/t_timing_nba_1.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_timing_nba_1.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_nba_2.pl b/test_regress/t/t_timing_nba_2.pl deleted file mode 100755 index 21a2189cc..000000000 --- a/test_regress/t/t_timing_nba_2.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_nba_2.py b/test_regress/t/t_timing_nba_2.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_timing_nba_2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_nested_assignment_on_lhs.pl b/test_regress/t/t_timing_nested_assignment_on_lhs.pl deleted file mode 100755 index 658376a53..000000000 --- a/test_regress/t/t_timing_nested_assignment_on_lhs.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_net_delay.v"); - -compile( - timing_loop => 1, - verilator_flags2 => ["--timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_nested_assignment_on_lhs.py b/test_regress/t/t_timing_nested_assignment_on_lhs.py new file mode 100755 index 000000000..bc41b20a9 --- /dev/null +++ b/test_regress/t/t_timing_nested_assignment_on_lhs.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_net_delay.v" + +test.compile(timing_loop=True, verilator_flags2=["--timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_off.pl b/test_regress/t/t_timing_off.pl deleted file mode 100755 index 21a2189cc..000000000 --- a/test_regress/t/t_timing_off.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_off.py b/test_regress/t/t_timing_off.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_timing_off.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_osc.pl b/test_regress/t/t_timing_osc.pl deleted file mode 100755 index a75f323ce..000000000 --- a/test_regress/t/t_timing_osc.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing --trace"], - make_main => 0, - ); - -execute( - ); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_timing_osc.py b/test_regress/t/t_timing_osc.py new file mode 100755 index 000000000..bc97f4d76 --- /dev/null +++ b/test_regress/t/t_timing_osc.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing --trace"], make_main=False) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_timing_pong.pl b/test_regress/t/t_timing_pong.pl deleted file mode 100755 index 21a2189cc..000000000 --- a/test_regress/t/t_timing_pong.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_pong.py b/test_regress/t/t_timing_pong.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_timing_pong.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_protect.pl b/test_regress/t/t_timing_protect.pl deleted file mode 100755 index 4ecb6cff6..000000000 --- a/test_regress/t/t_timing_protect.pl +++ /dev/null @@ -1,42 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -if (!$Self->have_coroutines) { - skip("No coroutine support"); -} -else { - top_filename("t/t_timing_fork_join.v"); # Contains all relevant constructs - - compile( - verilator_flags2 => ["--exe --main --timing --protect-ids", - "--protect-key SECRET_KEY"], - ); - - execute( - ); - - if ($Self->{vlt_all}) { - # Check for secret in any outputs - my $any; - foreach my $filename (glob $Self->{obj_dir} . "/*.[ch]*") { - file_grep_not($filename, qr/event[123]/); - file_grep_not($filename, qr/t_timing_fork_join/); - $any = 1; - } - $any or $Self->error("No outputs found"); - -} - -} - -ok(1); -1; diff --git a/test_regress/t/t_timing_protect.py b/test_regress/t/t_timing_protect.py new file mode 100755 index 000000000..9e828acb2 --- /dev/null +++ b/test_regress/t/t_timing_protect.py @@ -0,0 +1,28 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_timing_fork_join.v" # Contains all relevant constructs + +if not test.have_coroutines: + test.skip("No coroutine support") + +test.compile(verilator_flags2=["--exe --main --timing --protect-ids", "--protect-key SECRET_KEY"]) + +test.execute() + +if test.vlt_all: + # Check for secret in any outputs + for filename in test.glob_some(test.obj_dir + "/*.[ch]*"): + test.file_grep_not(filename, r'event[123]') + test.file_grep_not(filename, r't_timing_fork_join') + +test.passes() diff --git a/test_regress/t/t_timing_reentry.pl b/test_regress/t/t_timing_reentry.pl deleted file mode 100755 index 21a2189cc..000000000 --- a/test_regress/t/t_timing_reentry.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_reentry.py b/test_regress/t/t_timing_reentry.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_timing_reentry.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_sched.pl b/test_regress/t/t_timing_sched.pl deleted file mode 100755 index 21a2189cc..000000000 --- a/test_regress/t/t_timing_sched.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_sched.py b/test_regress/t/t_timing_sched.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_timing_sched.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_sched_if.pl b/test_regress/t/t_timing_sched_if.pl deleted file mode 100755 index 21a2189cc..000000000 --- a/test_regress/t/t_timing_sched_if.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_sched_if.py b/test_regress/t/t_timing_sched_if.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_timing_sched_if.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_sched_nba.pl b/test_regress/t/t_timing_sched_nba.pl deleted file mode 100755 index 21a2189cc..000000000 --- a/test_regress/t/t_timing_sched_nba.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_sched_nba.py b/test_regress/t/t_timing_sched_nba.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_timing_sched_nba.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_split.pl b/test_regress/t/t_timing_split.pl deleted file mode 100755 index cfaf42ceb..000000000 --- a/test_regress/t/t_timing_split.pl +++ /dev/null @@ -1,39 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - timing_loop => 1, - verilator_flags2 => ["--timing --output-split-cfuncs 1 -CFLAGS -Werror"], - ); - -execute( - ); - -check_splits(); - -ok(1); -1; - -sub check_splits { - my $got1; - my $gotSyms1; - return if !$Self->have_coroutines; - foreach my $file (glob("$Self->{obj_dir}/*.cpp")) { - if ($file =~ /Syms__1/) { - $gotSyms1 = 1; - } elsif ($file =~ /__1/) { - $got1 = 1; - } - } - $got1 or error("No __1 split file found"); - $gotSyms1 or error("No Syms__1 split file found"); -} diff --git a/test_regress/t/t_timing_split.py b/test_regress/t/t_timing_split.py new file mode 100755 index 000000000..54cfda002 --- /dev/null +++ b/test_regress/t/t_timing_split.py @@ -0,0 +1,37 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + + +def check_splits(): + got1 = False + gotSyms1 = False + for filename in test.glob_some(test.obj_dir + "/*.cpp"): + if re.search(r'Syms__1', filename): + gotSyms1 = True + elif re.search(r'__1', filename): + got1 = True + if not got1: + test.error("No __1 split file found") + if not gotSyms1: + test.error("No Syms__1 split file found") + + +test.compile(timing_loop=True, + verilator_flags2=["--timing --output-split-cfuncs 1 -CFLAGS -Werror"]) + +test.execute() + +if test.have_coroutines: + check_splits() + +test.passes() diff --git a/test_regress/t/t_timing_strobe.pl b/test_regress/t/t_timing_strobe.pl deleted file mode 100755 index 067c2a81f..000000000 --- a/test_regress/t/t_timing_strobe.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_strobe.py b/test_regress/t/t_timing_strobe.py new file mode 100755 index 000000000..bded720e2 --- /dev/null +++ b/test_regress/t/t_timing_strobe.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_timing_timescale.pl b/test_regress/t/t_timing_timescale.pl deleted file mode 100755 index 067c2a81f..000000000 --- a/test_regress/t/t_timing_timescale.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_timescale.py b/test_regress/t/t_timing_timescale.py new file mode 100755 index 000000000..bded720e2 --- /dev/null +++ b/test_regress/t/t_timing_timescale.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_timing_trace.pl b/test_regress/t/t_timing_trace.pl deleted file mode 100755 index 8965e5507..000000000 --- a/test_regress/t/t_timing_trace.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing --trace -Wno-MINTYPMAXDLY"], - ); - -execute( - ); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_timing_trace.py b/test_regress/t/t_timing_trace.py new file mode 100755 index 000000000..6a9d5689d --- /dev/null +++ b/test_regress/t/t_timing_trace.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing --trace -Wno-MINTYPMAXDLY"]) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_timing_trace_fst.pl b/test_regress/t/t_timing_trace_fst.pl deleted file mode 100755 index 0d087dfe5..000000000 --- a/test_regress/t/t_timing_trace_fst.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 Yves Mathieu. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_timing_trace.v"); - -compile( - verilator_flags2 => ["--exe --main --timing --trace-fst -Wno-MINTYPMAXDLY"], - ); - -execute( - ); - -fst_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_timing_trace_fst.py b/test_regress/t/t_timing_trace_fst.py new file mode 100755 index 000000000..727cb9ff6 --- /dev/null +++ b/test_regress/t/t_timing_trace_fst.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_timing_trace.v" + +test.compile(verilator_flags2=["--exe --main --timing --trace-fst -Wno-MINTYPMAXDLY"]) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_timing_unset1.pl b/test_regress/t/t_timing_unset1.pl deleted file mode 100755 index 167a6cf70..000000000 --- a/test_regress/t/t_timing_unset1.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_notiming.v"); - -compile( - # --timing/--no-timing not specified - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_unset1.py b/test_regress/t/t_timing_unset1.py new file mode 100755 index 000000000..d50e1d8f9 --- /dev/null +++ b/test_regress/t/t_timing_unset1.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_notiming.v" + +test.compile( + # --timing/--no-timing not specified + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_timing_unset2.pl b/test_regress/t/t_timing_unset2.pl deleted file mode 100755 index be9ccffa3..000000000 --- a/test_regress/t/t_timing_unset2.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_timing_off.v"); - -compile( - # --timing/--no-timing not specified - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_unset2.py b/test_regress/t/t_timing_unset2.py new file mode 100755 index 000000000..e19a52246 --- /dev/null +++ b/test_regress/t/t_timing_unset2.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_timing_off.v" + +test.compile( + # --timing/--no-timing not specified + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_timing_unset3.pl b/test_regress/t/t_timing_unset3.pl deleted file mode 100755 index 8c206a0f0..000000000 --- a/test_regress/t/t_timing_unset3.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_clocking_notiming.v"); - -compile( - # --timing/--no-timing not specified - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_unset3.py b/test_regress/t/t_timing_unset3.py new file mode 100755 index 000000000..5ff23db31 --- /dev/null +++ b/test_regress/t/t_timing_unset3.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_clocking_notiming.v" + +test.compile( + # --timing/--no-timing not specified + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_timing_wait1.pl b/test_regress/t/t_timing_wait1.pl deleted file mode 100755 index 79beadd2c..000000000 --- a/test_regress/t/t_timing_wait1.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing -Wno-WAITCONST"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_wait1.py b/test_regress/t/t_timing_wait1.py new file mode 100755 index 000000000..d1f037fe6 --- /dev/null +++ b/test_regress/t/t_timing_wait1.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing -Wno-WAITCONST"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_wait2.pl b/test_regress/t/t_timing_wait2.pl deleted file mode 100755 index 067c2a81f..000000000 --- a/test_regress/t/t_timing_wait2.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_wait2.py b/test_regress/t/t_timing_wait2.py new file mode 100755 index 000000000..bded720e2 --- /dev/null +++ b/test_regress/t/t_timing_wait2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_timing_wait3.pl b/test_regress/t/t_timing_wait3.pl deleted file mode 100755 index 21a2189cc..000000000 --- a/test_regress/t/t_timing_wait3.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_wait3.py b/test_regress/t/t_timing_wait3.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_timing_wait3.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_wait_long.pl b/test_regress/t/t_timing_wait_long.pl deleted file mode 100755 index 067c2a81f..000000000 --- a/test_regress/t/t_timing_wait_long.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_wait_long.py b/test_regress/t/t_timing_wait_long.py new file mode 100755 index 000000000..bded720e2 --- /dev/null +++ b/test_regress/t/t_timing_wait_long.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_timing_write_expr.pl b/test_regress/t/t_timing_write_expr.pl deleted file mode 100755 index a8cdfc5f4..000000000 --- a/test_regress/t/t_timing_write_expr.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - make_main => 0, - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_write_expr.py b/test_regress/t/t_timing_write_expr.py new file mode 100755 index 000000000..d05629d98 --- /dev/null +++ b/test_regress/t/t_timing_write_expr.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"], make_main=False) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_zerodly.pl b/test_regress/t/t_timing_zerodly.pl deleted file mode 100755 index b6b6711d8..000000000 --- a/test_regress/t/t_timing_zerodly.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_zerodly.py b/test_regress/t/t_timing_zerodly.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_timing_zerodly.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_zerodly_consecutive.pl b/test_regress/t/t_timing_zerodly_consecutive.pl deleted file mode 100755 index d1d43291d..000000000 --- a/test_regress/t/t_timing_zerodly_consecutive.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_zerodly_consecutive.py b/test_regress/t/t_timing_zerodly_consecutive.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_timing_zerodly_consecutive.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_timing_zerodly_unsup.pl b/test_regress/t/t_timing_zerodly_unsup.pl deleted file mode 100755 index 5439c7838..000000000 --- a/test_regress/t/t_timing_zerodly_unsup.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_timing_zerodly_unsup.py b/test_regress/t/t_timing_zerodly_unsup.py new file mode 100755 index 000000000..ea4425d51 --- /dev/null +++ b/test_regress/t/t_timing_zerodly_unsup.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_abort.pl b/test_regress/t/t_trace_abort.pl deleted file mode 100755 index 894b31a7e..000000000 --- a/test_regress/t/t_trace_abort.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - verilator_flags2 => ['--cc --trace'], - ); - -execute( - fails => 1, - ); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_abort.py b/test_regress/t/t_trace_abort.py new file mode 100755 index 000000000..ed957bcf9 --- /dev/null +++ b/test_regress/t/t_trace_abort.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(verilator_flags2=['--cc --trace']) + +test.execute(fails=True) + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_abort_fst.pl b/test_regress/t/t_trace_abort_fst.pl deleted file mode 100755 index 7d88526ba..000000000 --- a/test_regress/t/t_trace_abort_fst.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_trace_abort.v"); - -compile( - verilator_flags2 => ['--cc --trace-fst'], - ); - -execute( - fails => 1, - ); - -fst_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_abort_fst.py b/test_regress/t/t_trace_abort_fst.py new file mode 100755 index 000000000..d3606912a --- /dev/null +++ b/test_regress/t/t_trace_abort_fst.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_trace_abort.v" + +test.compile(verilator_flags2=['--cc --trace-fst']) + +test.execute(fails=True) + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_abort_fst_sc.pl b/test_regress/t/t_trace_abort_fst_sc.pl deleted file mode 100755 index 23e421465..000000000 --- a/test_regress/t/t_trace_abort_fst_sc.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); -if (!$Self->have_sc) { - skip("No SystemC installed"); -} -else { - top_filename("t/t_trace_abort.v"); - - compile( - verilator_flags2 => ['--sc --trace-fst'], - ); - - execute( - fails => 1, - ); - - fst_identical($Self->trace_filename, $Self->{golden_filename}); -} -ok(1); -1; diff --git a/test_regress/t/t_trace_abort_fst_sc.py b/test_regress/t/t_trace_abort_fst_sc.py new file mode 100755 index 000000000..1e6f9c314 --- /dev/null +++ b/test_regress/t/t_trace_abort_fst_sc.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_trace_abort.v" + +if not test.have_sc: + test.skip("No SystemC installed") + +test.compile(verilator_flags2=['--sc --trace-fst']) + +test.execute(fails=True) + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_array.pl b/test_regress/t/t_trace_array.pl deleted file mode 100755 index de7d257c9..000000000 --- a/test_regress/t/t_trace_array.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--cc --trace --trace-structs'], - ); - -execute( - ); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_array.py b/test_regress/t/t_trace_array.py new file mode 100755 index 000000000..e178ccb9b --- /dev/null +++ b/test_regress/t/t_trace_array.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--cc --trace --trace-structs']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_array_fst.pl b/test_regress/t/t_trace_array_fst.pl deleted file mode 100755 index 9f07b2554..000000000 --- a/test_regress/t/t_trace_array_fst.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_trace_array.v"); - -compile( - verilator_flags2 => ['--cc --trace-fst --trace-structs'], - ); - -execute( - ); - -fst_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_array_fst.py b/test_regress/t/t_trace_array_fst.py new file mode 100755 index 000000000..7bb8aa3c4 --- /dev/null +++ b/test_regress/t/t_trace_array_fst.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_trace_array.v" + +test.compile(verilator_flags2=['--cc --trace-fst --trace-structs']) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_array_fst_portable.pl b/test_regress/t/t_trace_array_fst_portable.pl deleted file mode 100755 index fa704d636..000000000 --- a/test_regress/t/t_trace_array_fst_portable.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_trace_array.v"); -golden_filename("t/t_trace_array_fst.out"); - -compile( - verilator_flags2 => ['--cc --trace-fst --trace-structs', - '-CFLAGS -DVL_PORTABLE_ONLY'], - ); - -execute( - ); - -fst_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_array_fst_portable.py b/test_regress/t/t_trace_array_fst_portable.py new file mode 100755 index 000000000..3942969f8 --- /dev/null +++ b/test_regress/t/t_trace_array_fst_portable.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_trace_array.v" +test.golden_filename = "t/t_trace_array_fst.out" + +test.compile(verilator_flags2=['--cc --trace-fst --trace-structs', '-CFLAGS -DVL_PORTABLE_ONLY']) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_array_fst_portable_sc.pl b/test_regress/t/t_trace_array_fst_portable_sc.pl deleted file mode 100755 index 145165eef..000000000 --- a/test_regress/t/t_trace_array_fst_portable_sc.pl +++ /dev/null @@ -1,32 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -if (!$Self->have_sc) { - skip("No SystemC installed"); -} -else { - top_filename("t/t_trace_array.v"); - golden_filename("t/t_trace_array_fst_sc.out"); - - compile( - verilator_flags2 => ['--sc --trace-fst --trace-structs', - '-CFLAGS -DVL_PORTABLE_ONLY'], - ); - - execute( - ); - - fst_identical($Self->trace_filename, $Self->{golden_filename}); -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_array_fst_portable_sc.py b/test_regress/t/t_trace_array_fst_portable_sc.py new file mode 100755 index 000000000..024b64e9b --- /dev/null +++ b/test_regress/t/t_trace_array_fst_portable_sc.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_trace_array.v" +test.golden_filename = "t/t_trace_array_fst_sc.out" + +if not test.have_sc: + test.skip("No SystemC installed") + +test.compile(verilator_flags2=['--sc --trace-fst --trace-structs', '-CFLAGS -DVL_PORTABLE_ONLY']) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_array_fst_sc.pl b/test_regress/t/t_trace_array_fst_sc.pl deleted file mode 100755 index ff2f91fe0..000000000 --- a/test_regress/t/t_trace_array_fst_sc.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -if (!$Self->have_sc) { - skip("No SystemC installed"); -} -else { - top_filename("t/t_trace_array.v"); - - compile( - verilator_flags2 => ['--sc --trace-fst --trace-structs'], - ); - - execute( - ); - - fst_identical($Self->trace_filename, $Self->{golden_filename}); -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_array_fst_sc.py b/test_regress/t/t_trace_array_fst_sc.py new file mode 100755 index 000000000..1f95faff6 --- /dev/null +++ b/test_regress/t/t_trace_array_fst_sc.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_trace_array.v" + +if not test.have_sc: + test.skip("No SystemC installed") + +test.compile(verilator_flags2=['--sc --trace-fst --trace-structs']) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_array_fst_threads_1.pl b/test_regress/t/t_trace_array_fst_threads_1.pl deleted file mode 100755 index 5539524df..000000000 --- a/test_regress/t/t_trace_array_fst_threads_1.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_trace_array.v"); -golden_filename("t/t_trace_array_fst.out"); - -compile( - verilator_flags2 => ['--cc --trace-fst --trace-threads 1 --trace-structs'], - ); - -execute( - ); - -fst_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_array_fst_threads_1.py b/test_regress/t/t_trace_array_fst_threads_1.py new file mode 100755 index 000000000..9c19b8e41 --- /dev/null +++ b/test_regress/t/t_trace_array_fst_threads_1.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_trace_array.v" +test.golden_filename = "t/t_trace_array_fst.out" + +test.compile(verilator_flags2=['--cc --trace-fst --trace-threads 1 --trace-structs']) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_array_fst_threads_1_sc.pl b/test_regress/t/t_trace_array_fst_threads_1_sc.pl deleted file mode 100755 index 9aacb5270..000000000 --- a/test_regress/t/t_trace_array_fst_threads_1_sc.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -if (!$Self->have_sc) { - skip("No SystemC installed"); -} -else { - top_filename("t/t_trace_array.v"); - golden_filename("t/t_trace_array_fst_sc.out"); - - compile( - verilator_flags2 => ['--sc --trace-fst --trace-threads 1 --trace-structs'], - ); - - execute( - ); - - fst_identical($Self->trace_filename, $Self->{golden_filename}); -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_array_fst_threads_1_sc.py b/test_regress/t/t_trace_array_fst_threads_1_sc.py new file mode 100755 index 000000000..b788ded44 --- /dev/null +++ b/test_regress/t/t_trace_array_fst_threads_1_sc.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_trace_array.v" +test.golden_filename = "t/t_trace_array_fst_sc.out" + +if not test.have_sc: + test.skip("No SystemC installed") + +test.compile(verilator_flags2=['--sc --trace-fst --trace-threads 1 --trace-structs']) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_array_fst_threads_2.pl b/test_regress/t/t_trace_array_fst_threads_2.pl deleted file mode 100755 index e6ce4179a..000000000 --- a/test_regress/t/t_trace_array_fst_threads_2.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_trace_array.v"); -golden_filename("t/t_trace_array_fst.out"); - -compile( - verilator_flags2 => ['--cc --trace-fst --trace-threads 2 --trace-structs'], - ); - -execute( - ); - -fst_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_array_fst_threads_2.py b/test_regress/t/t_trace_array_fst_threads_2.py new file mode 100755 index 000000000..95c7a0913 --- /dev/null +++ b/test_regress/t/t_trace_array_fst_threads_2.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_trace_array.v" +test.golden_filename = "t/t_trace_array_fst.out" + +test.compile(verilator_flags2=['--cc --trace-fst --trace-threads 2 --trace-structs']) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_array_fst_threads_2_sc.pl b/test_regress/t/t_trace_array_fst_threads_2_sc.pl deleted file mode 100755 index 52a29e09c..000000000 --- a/test_regress/t/t_trace_array_fst_threads_2_sc.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -if (!$Self->have_sc) { - skip("No SystemC installed"); -} -else { - top_filename("t/t_trace_array.v"); - golden_filename("t/t_trace_array_fst_sc.out"); - - compile( - verilator_flags2 => ['--sc --trace-fst --trace-threads 2 --trace-structs'], - ); - - execute( - ); - - fst_identical($Self->trace_filename, $Self->{golden_filename}); -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_array_fst_threads_2_sc.py b/test_regress/t/t_trace_array_fst_threads_2_sc.py new file mode 100755 index 000000000..34965a006 --- /dev/null +++ b/test_regress/t/t_trace_array_fst_threads_2_sc.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_trace_array.v" +test.golden_filename = "t/t_trace_array_fst_sc.out" + +if not test.have_sc: + test.skip("No SystemC installed") + +test.compile(verilator_flags2=['--sc --trace-fst --trace-threads 2 --trace-structs']) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_array_threads_1.pl b/test_regress/t/t_trace_array_threads_1.pl deleted file mode 100755 index 1daff6873..000000000 --- a/test_regress/t/t_trace_array_threads_1.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_trace_array.v"); -golden_filename("t/t_trace_array.out"); - -compile( - verilator_flags2 => ['--cc --trace --trace-threads 1 --trace-structs'], - ); - -execute( - ); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_array_threads_1.py b/test_regress/t/t_trace_array_threads_1.py new file mode 100755 index 000000000..3400f7771 --- /dev/null +++ b/test_regress/t/t_trace_array_threads_1.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_trace_array.v" +test.golden_filename = "t/t_trace_array.out" + +test.compile(verilator_flags2=['--cc --trace --trace-threads 1 --trace-structs']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_ascendingrange.pl b/test_regress/t/t_trace_ascendingrange.pl deleted file mode 100755 index 74afdd21d..000000000 --- a/test_regress/t/t_trace_ascendingrange.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. -# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. -# Strangely, asking for more threads makes it go away. -compile( - verilator_flags2 => ['--cc --trace --trace-params -Wno-ASCRANGE'], - threads => $Self->{vltmt} ? 6 : 1 - ); - -execute( - ); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_ascendingrange.py b/test_regress/t/t_trace_ascendingrange.py new file mode 100755 index 000000000..d90888a48 --- /dev/null +++ b/test_regress/t/t_trace_ascendingrange.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. +# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. +# Strangely, asking for more threads makes it go away. +test.compile(verilator_flags2=['--cc --trace --trace-params -Wno-ASCRANGE'], + threads=(6 if test.vltmt else 1)) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_ascendingrange_fst.pl b/test_regress/t/t_trace_ascendingrange_fst.pl deleted file mode 100755 index 53259fada..000000000 --- a/test_regress/t/t_trace_ascendingrange_fst.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_trace_ascendingrange.v"); - -# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. -# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. -# Strangely, asking for more threads makes it go away. -compile( - verilator_flags2 => ['--cc --trace-fst --trace-params -Wno-ASCRANGE'], - threads => $Self->{vltmt} ? 6 : 1 - ); - -execute( - ); - -fst_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_ascendingrange_fst.py b/test_regress/t/t_trace_ascendingrange_fst.py new file mode 100755 index 000000000..2f812bb4c --- /dev/null +++ b/test_regress/t/t_trace_ascendingrange_fst.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_ascendingrange.v" + +# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. +# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. +# Strangely, asking for more threads makes it go away. +test.compile(verilator_flags2=['--cc --trace-fst --trace-params -Wno-ASCRANGE'], + threads=(6 if test.vltmt else 1)) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_ascendingrange_fst_sc.pl b/test_regress/t/t_trace_ascendingrange_fst_sc.pl deleted file mode 100755 index bebbd5e49..000000000 --- a/test_regress/t/t_trace_ascendingrange_fst_sc.pl +++ /dev/null @@ -1,34 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_sc) { - skip("No SystemC installed"); -} -else { - top_filename("t/t_trace_ascendingrange.v"); - - # CI environment offers 2 VCPUs, 2 thread setting causes the following warning. - # %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. - # Strangely, asking for more threads makes it go away. - compile( - verilator_flags2 => ['--sc --trace-fst --trace-params -Wno-ASCRANGE'], - threads => $Self->{vltmt} ? 6 : 1 - ); - - execute( - ); - - fst_identical($Self->trace_filename, $Self->{golden_filename}); -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_ascendingrange_fst_sc.py b/test_regress/t/t_trace_ascendingrange_fst_sc.py new file mode 100755 index 000000000..a01e6692e --- /dev/null +++ b/test_regress/t/t_trace_ascendingrange_fst_sc.py @@ -0,0 +1,28 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_ascendingrange.v" + +if not test.have_sc: + test.skip("No SystemC installed") + +# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. +# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. +# Strangely, asking for more threads makes it go away. +test.compile(verilator_flags2=['--sc --trace-fst --trace-params -Wno-ASCRANGE'], + threads=(6 if test.vltmt else 1)) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_binary.pl b/test_regress/t/t_trace_binary.pl deleted file mode 100755 index 68d10ec9b..000000000 --- a/test_regress/t/t_trace_binary.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags => [# Custom as don't want -cc - "-Mdir $Self->{obj_dir}", - "--debug-check", ], - verilator_flags2 => ['--binary --trace'], - ); - -execute( - ); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_binary.py b/test_regress/t/t_trace_binary.py new file mode 100755 index 000000000..2737cb863 --- /dev/null +++ b/test_regress/t/t_trace_binary.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile( + verilator_flags=[ # Custom as don't want -cc + "-Mdir " + test.obj_dir, "--debug-check" + ], + verilator_flags2=['--binary --trace']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_binary_flag_off.pl b/test_regress/t/t_trace_binary_flag_off.pl deleted file mode 100755 index 521677772..000000000 --- a/test_regress/t/t_trace_binary_flag_off.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_trace_binary.v"); - -compile( - verilator_flags => [# Custom as don't want -cc - "-Mdir $Self->{obj_dir}", - "--debug-check", ], - verilator_flags2 => ['--binary'], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_trace_binary_flag_off.py b/test_regress/t/t_trace_binary_flag_off.py new file mode 100755 index 000000000..2e846b7e1 --- /dev/null +++ b/test_regress/t/t_trace_binary_flag_off.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_trace_binary.v" + +test.compile( + verilator_flags=[ # Custom as don't want -cc + "-Mdir " + test.obj_dir, "--debug-check" + ], + verilator_flags2=['--binary']) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_cat.pl b/test_regress/t/t_trace_cat.pl deleted file mode 100755 index 06f238c1f..000000000 --- a/test_regress/t/t_trace_cat.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2013 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ["--trace --exe $Self->{t_dir}/t_trace_cat.cpp"], - ); - -execute( - ); - -system("cat $Self->{obj_dir}/simpart_0000.vcd " - . " $Self->{obj_dir}/simpart_0000_cat*.vcd > $Self->{obj_dir}/simall.vcd"); - -vcd_identical("$Self->{obj_dir}/simall.vcd", - $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_cat.py b/test_regress/t/t_trace_cat.py new file mode 100755 index 000000000..5b89b99fd --- /dev/null +++ b/test_regress/t/t_trace_cat.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_top_shell=False, make_main=False, v_flags2=["--trace --exe", test.pli_filename]) + +test.execute() + +os.system("cat " + test.obj_dir + "/simpart_0000.vcd " + " " + test.obj_dir + + "/simpart_0000_cat*.vcd > " + test.obj_dir + "/simall.vcd") + +test.vcd_identical(test.obj_dir + "/simall.vcd", test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_cat_fst.pl b/test_regress/t/t_trace_cat_fst.pl deleted file mode 100755 index a0b65b90d..000000000 --- a/test_regress/t/t_trace_cat_fst.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2013 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ["--trace-fst --exe $Self->{t_dir}/t_trace_cat_fst.cpp"], - ); - -execute( - ); - -fst_identical("$Self->{obj_dir}/simpart_0000.fst", - "t/$Self->{name}_0000.out"); -fst_identical("$Self->{obj_dir}/simpart_0100.fst", - "t/$Self->{name}_0100.out"); - -ok(1); -1; diff --git a/test_regress/t/t_trace_cat_fst.py b/test_regress/t/t_trace_cat_fst.py new file mode 100755 index 000000000..9f94e690c --- /dev/null +++ b/test_regress/t/t_trace_cat_fst.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_top_shell=False, + make_main=False, + v_flags2=["--trace-fst --exe", test.pli_filename]) + +test.execute() + +test.fst_identical(test.obj_dir + "/simpart_0000.fst", "t/" + test.name + "_0000.out") +test.fst_identical(test.obj_dir + "/simpart_0100.fst", "t/" + test.name + "_0100.out") + +test.passes() diff --git a/test_regress/t/t_trace_cat_renew.pl b/test_regress/t/t_trace_cat_renew.pl deleted file mode 100755 index 4268ff4a7..000000000 --- a/test_regress/t/t_trace_cat_renew.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2013 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_trace_cat.v"); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ["--trace --exe $Self->{t_dir}/t_trace_cat.cpp"], - ); - -execute( - ); - -vcd_identical("$Self->{obj_dir}/simpart_0000.vcd", - "t/$Self->{name}_0000.out"); -vcd_identical("$Self->{obj_dir}/simpart_0100.vcd", - "t/$Self->{name}_0100.out"); - -ok(1); -1; diff --git a/test_regress/t/t_trace_cat_renew.py b/test_regress/t/t_trace_cat_renew.py new file mode 100755 index 000000000..99db77d20 --- /dev/null +++ b/test_regress/t/t_trace_cat_renew.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_trace_cat.cpp" +test.top_filename = "t/t_trace_cat.v" + +test.compile(make_top_shell=False, make_main=False, v_flags2=["--trace --exe", test.pli_filename]) + +test.execute() + +test.vcd_identical(test.obj_dir + "/simpart_0000.vcd", "t/" + test.name + "_0000.out") +test.vcd_identical(test.obj_dir + "/simpart_0100.vcd", "t/" + test.name + "_0100.out") + +test.passes() diff --git a/test_regress/t/t_trace_cat_reopen.pl b/test_regress/t/t_trace_cat_reopen.pl deleted file mode 100755 index 4268ff4a7..000000000 --- a/test_regress/t/t_trace_cat_reopen.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2013 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_trace_cat.v"); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ["--trace --exe $Self->{t_dir}/t_trace_cat.cpp"], - ); - -execute( - ); - -vcd_identical("$Self->{obj_dir}/simpart_0000.vcd", - "t/$Self->{name}_0000.out"); -vcd_identical("$Self->{obj_dir}/simpart_0100.vcd", - "t/$Self->{name}_0100.out"); - -ok(1); -1; diff --git a/test_regress/t/t_trace_cat_reopen.py b/test_regress/t/t_trace_cat_reopen.py new file mode 100755 index 000000000..99db77d20 --- /dev/null +++ b/test_regress/t/t_trace_cat_reopen.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_trace_cat.cpp" +test.top_filename = "t/t_trace_cat.v" + +test.compile(make_top_shell=False, make_main=False, v_flags2=["--trace --exe", test.pli_filename]) + +test.execute() + +test.vcd_identical(test.obj_dir + "/simpart_0000.vcd", "t/" + test.name + "_0000.out") +test.vcd_identical(test.obj_dir + "/simpart_0100.vcd", "t/" + test.name + "_0100.out") + +test.passes() diff --git a/test_regress/t/t_trace_class.pl b/test_regress/t/t_trace_class.pl deleted file mode 100755 index fe872bf63..000000000 --- a/test_regress/t/t_trace_class.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - # verilator_flags2 => ['--binary --trace'], - verilator_flags2 => ['--binary --trace'], - ); - -execute( - ); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_class.py b/test_regress/t/t_trace_class.py new file mode 100755 index 000000000..c57dc225f --- /dev/null +++ b/test_regress/t/t_trace_class.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile( + # verilator_flags2 = ['--binary --trace'], + verilator_flags2=['--binary --trace']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_complex.pl b/test_regress/t/t_trace_complex.pl deleted file mode 100755 index 656517185..000000000 --- a/test_regress/t/t_trace_complex.pl +++ /dev/null @@ -1,33 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--cc --trace'], - ); - -execute( - ); - -file_grep($Self->trace_filename, qr/ v_strp /); -file_grep($Self->trace_filename, qr/ v_strp_strp /); -file_grep($Self->trace_filename, qr/ v_arrp /); -file_grep($Self->trace_filename, qr/ v_arrp_arrp /); -file_grep($Self->trace_filename, qr/ v_arrp_strp /); -file_grep($Self->trace_filename, qr/ v_arru\[/); -file_grep($Self->trace_filename, qr/ v_arru_arru\[/); -file_grep($Self->trace_filename, qr/ v_arru_arrp\[/); -file_grep($Self->trace_filename, qr/ v_arru_strp\[/); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_complex.py b/test_regress/t/t_trace_complex.py new file mode 100755 index 000000000..b7da0f5f5 --- /dev/null +++ b/test_regress/t/t_trace_complex.py @@ -0,0 +1,30 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--cc --trace']) + +test.execute() + +test.file_grep(test.trace_filename, r' v_arrp ') +test.file_grep(test.trace_filename, r' v_arrp_arrp ') +test.file_grep(test.trace_filename, r' v_arrp_strp ') +test.file_grep(test.trace_filename, r' v_arru\[') +test.file_grep(test.trace_filename, r' v_arru_arrp\[') +test.file_grep(test.trace_filename, r' v_arru_arru\[') +test.file_grep(test.trace_filename, r' v_arru_strp\[') +test.file_grep(test.trace_filename, r' v_strp ') +test.file_grep(test.trace_filename, r' v_strp_strp ') + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_complex_fst.pl b/test_regress/t/t_trace_complex_fst.pl deleted file mode 100755 index a82076ee4..000000000 --- a/test_regress/t/t_trace_complex_fst.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_trace_complex.v"); - -compile( - verilator_flags2 => ['--cc --trace-fst'], - ); - -execute( - ); - -fst_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_complex_fst.py b/test_regress/t/t_trace_complex_fst.py new file mode 100755 index 000000000..2d1104166 --- /dev/null +++ b/test_regress/t/t_trace_complex_fst.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_complex.v" + +test.compile(verilator_flags2=['--cc --trace-fst']) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_complex_fst_sc.pl b/test_regress/t/t_trace_complex_fst_sc.pl deleted file mode 100755 index 39a304883..000000000 --- a/test_regress/t/t_trace_complex_fst_sc.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_sc) { - skip("No SystemC installed"); -} -else { - top_filename("t/t_trace_complex.v"); - - compile( - verilator_flags2 => ['--sc --trace-fst'], - ); - - execute( - ); - - fst_identical($Self->trace_filename, $Self->{golden_filename}); -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_complex_fst_sc.py b/test_regress/t/t_trace_complex_fst_sc.py new file mode 100755 index 000000000..0e4fe6ff3 --- /dev/null +++ b/test_regress/t/t_trace_complex_fst_sc.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_complex.v" + +if not test.have_sc: + test.skip("No SystemC installed") + +test.compile(verilator_flags2=['--sc --trace-fst']) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_complex_fst_threads_1.pl b/test_regress/t/t_trace_complex_fst_threads_1.pl deleted file mode 100755 index 0f82c6002..000000000 --- a/test_regress/t/t_trace_complex_fst_threads_1.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_trace_complex.v"); -golden_filename("t/t_trace_complex_fst.out"); - -compile( - verilator_flags2 => ['--cc --trace-fst --trace-threads 1'], - ); - -execute( - ); - -fst_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_complex_fst_threads_1.py b/test_regress/t/t_trace_complex_fst_threads_1.py new file mode 100755 index 000000000..b1a3f7e85 --- /dev/null +++ b/test_regress/t/t_trace_complex_fst_threads_1.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_complex.v" +test.golden_filename = "t/t_trace_complex_fst.out" + +test.compile(verilator_flags2=['--cc --trace-fst --trace-threads 1']) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_complex_fst_threads_1_sc.pl b/test_regress/t/t_trace_complex_fst_threads_1_sc.pl deleted file mode 100755 index 0e2303711..000000000 --- a/test_regress/t/t_trace_complex_fst_threads_1_sc.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_sc) { - skip("No SystemC installed"); -} -else { - top_filename("t/t_trace_complex.v"); - golden_filename("t/t_trace_complex_fst_sc.out"); - - compile( - verilator_flags2 => ['--sc --trace-fst --trace-threads 1'], - ); - - execute( - ); - - fst_identical($Self->trace_filename, $Self->{golden_filename}); -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_complex_fst_threads_1_sc.py b/test_regress/t/t_trace_complex_fst_threads_1_sc.py new file mode 100755 index 000000000..6a62c90e9 --- /dev/null +++ b/test_regress/t/t_trace_complex_fst_threads_1_sc.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_complex.v" +test.golden_filename = "t/t_trace_complex_fst_sc.out" + +if not test.have_sc: + test.skip("No SystemC installed") + +test.compile(verilator_flags2=['--sc --trace-fst --trace-threads 1']) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_complex_fst_threads_2.pl b/test_regress/t/t_trace_complex_fst_threads_2.pl deleted file mode 100755 index 398057446..000000000 --- a/test_regress/t/t_trace_complex_fst_threads_2.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_trace_complex.v"); -golden_filename("t/t_trace_complex_fst.out"); - -compile( - verilator_flags2 => ['--cc --trace-fst --trace-threads 2'], - ); - -execute( - ); - -fst_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_complex_fst_threads_2.py b/test_regress/t/t_trace_complex_fst_threads_2.py new file mode 100755 index 000000000..451fad715 --- /dev/null +++ b/test_regress/t/t_trace_complex_fst_threads_2.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_complex.v" +test.golden_filename = "t/t_trace_complex_fst.out" + +test.compile(verilator_flags2=['--cc --trace-fst --trace-threads 2']) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_complex_fst_threads_2_sc.pl b/test_regress/t/t_trace_complex_fst_threads_2_sc.pl deleted file mode 100755 index f843304f5..000000000 --- a/test_regress/t/t_trace_complex_fst_threads_2_sc.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_sc) { - skip("No SystemC installed"); -} -else { - top_filename("t/t_trace_complex.v"); - golden_filename("t/t_trace_complex_fst_sc.out"); - - compile( - verilator_flags2 => ['--sc --trace-fst --trace-threads 2'], - ); - - execute( - ); - - fst_identical($Self->trace_filename, $Self->{golden_filename}); -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_complex_fst_threads_2_sc.py b/test_regress/t/t_trace_complex_fst_threads_2_sc.py new file mode 100755 index 000000000..7ddc967bd --- /dev/null +++ b/test_regress/t/t_trace_complex_fst_threads_2_sc.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_complex.v" +test.golden_filename = "t/t_trace_complex_fst_sc.out" + +if not test.have_sc: + test.skip("No SystemC installed") + +test.compile(verilator_flags2=['--sc --trace-fst --trace-threads 2']) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_complex_params.pl b/test_regress/t/t_trace_complex_params.pl deleted file mode 100755 index 822041625..000000000 --- a/test_regress/t/t_trace_complex_params.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_trace_complex.v"); - -compile( - verilator_flags2 => ['--cc --trace --no-trace-structs --trace-params'], - ); - -execute( - ); - -file_grep($Self->trace_filename, qr/ PARAM /); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_complex_params.py b/test_regress/t/t_trace_complex_params.py new file mode 100755 index 000000000..566dc8a73 --- /dev/null +++ b/test_regress/t/t_trace_complex_params.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_complex.v" + +test.compile(verilator_flags2=['--cc --trace --no-trace-structs --trace-params']) + +test.execute() + +test.file_grep(test.trace_filename, r' PARAM ') + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_complex_params_fst.pl b/test_regress/t/t_trace_complex_params_fst.pl deleted file mode 100755 index 90e0ffc4e..000000000 --- a/test_regress/t/t_trace_complex_params_fst.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_trace_complex.v"); - -compile( - verilator_flags2 => ['--cc --trace-fst --no-trace-structs --trace-params'], - ); - -execute( - ); - -fst_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_complex_params_fst.py b/test_regress/t/t_trace_complex_params_fst.py new file mode 100755 index 000000000..cd052c278 --- /dev/null +++ b/test_regress/t/t_trace_complex_params_fst.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_complex.v" + +test.compile(verilator_flags2=['--cc --trace-fst --no-trace-structs --trace-params']) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_complex_params_fst_sc.pl b/test_regress/t/t_trace_complex_params_fst_sc.pl deleted file mode 100755 index 7af8b1361..000000000 --- a/test_regress/t/t_trace_complex_params_fst_sc.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_sc) { - skip("No SystemC installed"); -} -else { - top_filename("t/t_trace_complex.v"); - - compile( - verilator_flags2 => ['--sc --trace-fst --no-trace-structs --trace-params'], - ); - - execute( - ); - - fst_identical($Self->trace_filename, $Self->{golden_filename}); -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_complex_params_fst_sc.py b/test_regress/t/t_trace_complex_params_fst_sc.py new file mode 100755 index 000000000..99007833e --- /dev/null +++ b/test_regress/t/t_trace_complex_params_fst_sc.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_complex.v" + +if not test.have_sc: + test.skip("No SystemC installed") + +test.compile(verilator_flags2=['--sc --trace-fst --no-trace-structs --trace-params']) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_complex_portable.pl b/test_regress/t/t_trace_complex_portable.pl deleted file mode 100755 index 2f8d3f5d7..000000000 --- a/test_regress/t/t_trace_complex_portable.pl +++ /dev/null @@ -1,38 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# Same test as t_trace_complex, but exercising the old VCD tracing API - -scenarios(vlt => 1); - -top_filename("t/t_trace_complex.v"); -golden_filename("t/t_trace_complex.out"); - -compile( - verilator_flags2 => ['--cc --trace -CFLAGS -DVL_PORTABLE_ONLY'], - ); - -execute( - ); - -file_grep($Self->trace_filename, qr/ v_strp /); -file_grep($Self->trace_filename, qr/ v_strp_strp /); -file_grep($Self->trace_filename, qr/ v_arrp /); -file_grep($Self->trace_filename, qr/ v_arrp_arrp /); -file_grep($Self->trace_filename, qr/ v_arrp_strp /); -file_grep($Self->trace_filename, qr/ v_arru\[/); -file_grep($Self->trace_filename, qr/ v_arru_arru\[/); -file_grep($Self->trace_filename, qr/ v_arru_arrp\[/); -file_grep($Self->trace_filename, qr/ v_arru_strp\[/); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_complex_portable.py b/test_regress/t/t_trace_complex_portable.py new file mode 100755 index 000000000..4e0bdcff1 --- /dev/null +++ b/test_regress/t/t_trace_complex_portable.py @@ -0,0 +1,34 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +# Same test as t_trace_complex, but exercising the old VCD tracing API + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_trace_complex.v" +test.golden_filename = "t/t_trace_complex.out" + +test.compile(verilator_flags2=['--cc --trace -CFLAGS -DVL_PORTABLE_ONLY']) + +test.execute() + +test.file_grep(test.trace_filename, r' v_strp ') +test.file_grep(test.trace_filename, r' v_strp_strp ') +test.file_grep(test.trace_filename, r' v_arrp ') +test.file_grep(test.trace_filename, r' v_arrp_arrp ') +test.file_grep(test.trace_filename, r' v_arrp_strp ') +test.file_grep(test.trace_filename, r' v_arru\[') +test.file_grep(test.trace_filename, r' v_arru_arru\[') +test.file_grep(test.trace_filename, r' v_arru_arrp\[') +test.file_grep(test.trace_filename, r' v_arru_strp\[') + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_complex_structs.pl b/test_regress/t/t_trace_complex_structs.pl deleted file mode 100755 index bc303627d..000000000 --- a/test_regress/t/t_trace_complex_structs.pl +++ /dev/null @@ -1,35 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_trace_complex.v"); - -compile( - verilator_flags2 => ['--cc --trace --trace-structs --no-trace-params'], - ); - -execute( - ); - -file_grep($Self->trace_filename, qr/ v_strp /); -file_grep($Self->trace_filename, qr/ v_strp_strp /); -file_grep($Self->trace_filename, qr/ v_arrp /); -file_grep_not($Self->trace_filename, qr/ v_arrp_arrp /); -file_grep_not($Self->trace_filename, qr/ v_arrp_strp /); -file_grep($Self->trace_filename, qr/ v_arru\[/); -file_grep($Self->trace_filename, qr/ v_arru_arru\[/); -file_grep($Self->trace_filename, qr/ v_arru_arrp\[/); -file_grep($Self->trace_filename, qr/ v_arru_strp\[/); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_complex_structs.py b/test_regress/t/t_trace_complex_structs.py new file mode 100755 index 000000000..9e8df28e9 --- /dev/null +++ b/test_regress/t/t_trace_complex_structs.py @@ -0,0 +1,31 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_complex.v" + +test.compile(verilator_flags2=['--cc --trace --trace-structs --no-trace-params']) + +test.execute() + +test.file_grep(test.trace_filename, r' v_strp ') +test.file_grep(test.trace_filename, r' v_strp_strp ') +test.file_grep(test.trace_filename, r' v_arrp ') +test.file_grep_not(test.trace_filename, r' v_arrp_arrp ') +test.file_grep_not(test.trace_filename, r' v_arrp_strp ') +test.file_grep(test.trace_filename, r' v_arru\[') +test.file_grep(test.trace_filename, r' v_arru_arru\[') +test.file_grep(test.trace_filename, r' v_arru_arrp\[') +test.file_grep(test.trace_filename, r' v_arru_strp\[') + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_complex_structs_fst.pl b/test_regress/t/t_trace_complex_structs_fst.pl deleted file mode 100755 index 53371234d..000000000 --- a/test_regress/t/t_trace_complex_structs_fst.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_trace_complex.v"); - -compile( - verilator_flags2 => ['--cc --trace-fst --trace-structs --no-trace-params'], - ); - -execute( - ); - -fst_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_complex_structs_fst.py b/test_regress/t/t_trace_complex_structs_fst.py new file mode 100755 index 000000000..879cd5e97 --- /dev/null +++ b/test_regress/t/t_trace_complex_structs_fst.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_complex.v" + +test.compile(verilator_flags2=['--cc --trace-fst --trace-structs --no-trace-params']) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_complex_structs_fst_sc.pl b/test_regress/t/t_trace_complex_structs_fst_sc.pl deleted file mode 100755 index 099934eaf..000000000 --- a/test_regress/t/t_trace_complex_structs_fst_sc.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_sc) { - skip("No SystemC installed"); -} -else { - top_filename("t/t_trace_complex.v"); - - compile( - verilator_flags2 => ['--sc --trace-fst --trace-structs --no-trace-params'], - ); - - execute( - ); - - fst_identical($Self->trace_filename, $Self->{golden_filename}); -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_complex_structs_fst_sc.py b/test_regress/t/t_trace_complex_structs_fst_sc.py new file mode 100755 index 000000000..4e88e7f62 --- /dev/null +++ b/test_regress/t/t_trace_complex_structs_fst_sc.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_complex.v" + +if not test.have_sc: + test.skip("No SystemC installed") + +test.compile(verilator_flags2=['--sc --trace-fst --trace-structs --no-trace-params']) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_complex_threads_1.pl b/test_regress/t/t_trace_complex_threads_1.pl deleted file mode 100755 index 1aec6885a..000000000 --- a/test_regress/t/t_trace_complex_threads_1.pl +++ /dev/null @@ -1,36 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_trace_complex.v"); -golden_filename("t/t_trace_complex.out"); - -compile( - verilator_flags2 => ['--cc --trace --trace-threads 1'] - ); - -execute( - ); - -file_grep($Self->trace_filename, qr/ v_strp /); -file_grep($Self->trace_filename, qr/ v_strp_strp /); -file_grep($Self->trace_filename, qr/ v_arrp /); -file_grep($Self->trace_filename, qr/ v_arrp_arrp /); -file_grep($Self->trace_filename, qr/ v_arrp_strp /); -file_grep($Self->trace_filename, qr/ v_arru\[/); -file_grep($Self->trace_filename, qr/ v_arru_arru\[/); -file_grep($Self->trace_filename, qr/ v_arru_arrp\[/); -file_grep($Self->trace_filename, qr/ v_arru_strp\[/); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_complex_threads_1.py b/test_regress/t/t_trace_complex_threads_1.py new file mode 100755 index 000000000..bf3e9e999 --- /dev/null +++ b/test_regress/t/t_trace_complex_threads_1.py @@ -0,0 +1,32 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_complex.v" +test.golden_filename = "t/t_trace_complex.out" + +test.compile(verilator_flags2=['--cc --trace --trace-threads 1']) + +test.execute() + +test.file_grep(test.trace_filename, r' v_strp ') +test.file_grep(test.trace_filename, r' v_strp_strp ') +test.file_grep(test.trace_filename, r' v_arrp ') +test.file_grep(test.trace_filename, r' v_arrp_arrp ') +test.file_grep(test.trace_filename, r' v_arrp_strp ') +test.file_grep(test.trace_filename, r' v_arru\[') +test.file_grep(test.trace_filename, r' v_arru_arru\[') +test.file_grep(test.trace_filename, r' v_arru_arrp\[') +test.file_grep(test.trace_filename, r' v_arru_strp\[') + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_decoration.pl b/test_regress/t/t_trace_decoration.pl deleted file mode 100755 index e96c62761..000000000 --- a/test_regress/t/t_trace_decoration.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--cc --trace --no-decoration'], - ); - -execute( - ); - -file_grep_not("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr!// Body!); - -ok(1); -1; diff --git a/test_regress/t/t_trace_decoration.py b/test_regress/t/t_trace_decoration.py new file mode 100755 index 000000000..86750fc3c --- /dev/null +++ b/test_regress/t/t_trace_decoration.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--cc --trace --no-decoration']) + +test.execute() + +test.file_grep_not(test.obj_dir + "/" + test.vm_prefix + ".h", r'// Body') + +test.passes() diff --git a/test_regress/t/t_trace_dumporder_bad.pl b/test_regress/t/t_trace_dumporder_bad.pl deleted file mode 100755 index fc035719b..000000000 --- a/test_regress/t/t_trace_dumporder_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["-trace"], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_trace_dumporder_bad.py b/test_regress/t/t_trace_dumporder_bad.py new file mode 100755 index 000000000..0e9c44d04 --- /dev/null +++ b/test_regress/t/t_trace_dumporder_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["-trace"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars_dyn_fst_0.pl b/test_regress/t/t_trace_dumpvars_dyn_fst_0.pl deleted file mode 100755 index 472628a4e..000000000 --- a/test_regress/t/t_trace_dumpvars_dyn_fst_0.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t_trace_dumpvars_dyn.v"); - -compile( - make_main => 0, - verilator_flags2 => ["--trace-fst --exe $Self->{t_dir}/t_trace_dumpvars_dyn.cpp"], - ); - -execute( - ); - -fst_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_dumpvars_dyn_fst_0.py b/test_regress/t/t_trace_dumpvars_dyn_fst_0.py new file mode 100755 index 000000000..00778c82c --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_dyn_fst_0.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_trace_dumpvars_dyn.cpp" +test.top_filename = "t/t_trace_dumpvars_dyn.v" + +test.compile(make_main=False, verilator_flags2=["--trace-fst --exe", test.pli_filename]) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars_dyn_fst_1.pl b/test_regress/t/t_trace_dumpvars_dyn_fst_1.pl deleted file mode 100755 index 472628a4e..000000000 --- a/test_regress/t/t_trace_dumpvars_dyn_fst_1.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t_trace_dumpvars_dyn.v"); - -compile( - make_main => 0, - verilator_flags2 => ["--trace-fst --exe $Self->{t_dir}/t_trace_dumpvars_dyn.cpp"], - ); - -execute( - ); - -fst_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_dumpvars_dyn_fst_1.py b/test_regress/t/t_trace_dumpvars_dyn_fst_1.py new file mode 100755 index 000000000..00778c82c --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_dyn_fst_1.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_trace_dumpvars_dyn.cpp" +test.top_filename = "t/t_trace_dumpvars_dyn.v" + +test.compile(make_main=False, verilator_flags2=["--trace-fst --exe", test.pli_filename]) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars_dyn_vcd_0.pl b/test_regress/t/t_trace_dumpvars_dyn_vcd_0.pl deleted file mode 100755 index 2ddb9d015..000000000 --- a/test_regress/t/t_trace_dumpvars_dyn_vcd_0.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t_trace_dumpvars_dyn.v"); - -compile( - make_main => 0, - verilator_flags2 => ["--trace --exe $Self->{t_dir}/t_trace_dumpvars_dyn.cpp"], - ); - -execute( - ); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_dumpvars_dyn_vcd_0.py b/test_regress/t/t_trace_dumpvars_dyn_vcd_0.py new file mode 100755 index 000000000..17f76e69b --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_dyn_vcd_0.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_trace_dumpvars_dyn.cpp" +test.top_filename = "t/t_trace_dumpvars_dyn.v" + +test.compile(make_main=False, verilator_flags2=["--trace --exe", test.pli_filename]) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars_dyn_vcd_1.pl b/test_regress/t/t_trace_dumpvars_dyn_vcd_1.pl deleted file mode 100755 index 4e0bdc01b..000000000 --- a/test_regress/t/t_trace_dumpvars_dyn_vcd_1.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t_trace_dumpvars_dyn.v"); - -compile( - make_main => 0, - verilator_flags2 => ["--trace --exe $Self->{t_dir}/t_trace_dumpvars_dyn.cpp -CFLAGS -DVL_DEBUG"], - ); - -execute( - ); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_dumpvars_dyn_vcd_1.py b/test_regress/t/t_trace_dumpvars_dyn_vcd_1.py new file mode 100755 index 000000000..9e369b46e --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_dyn_vcd_1.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_trace_dumpvars_dyn.cpp" +test.top_filename = "t/t_trace_dumpvars_dyn.v" + +test.compile(make_main=False, + verilator_flags2=["--trace --exe", test.pli_filename, "-CFLAGS -DVL_DEBUG"]) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_empty.pl b/test_regress/t/t_trace_empty.pl deleted file mode 100755 index cfb786a40..000000000 --- a/test_regress/t/t_trace_empty.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--trace'], - ); - -execute( - ); - -file_grep_not($Self->trace_filename, qr/var/); - -ok(1); -1; diff --git a/test_regress/t/t_trace_empty.py b/test_regress/t/t_trace_empty.py new file mode 100755 index 000000000..317f700bc --- /dev/null +++ b/test_regress/t/t_trace_empty.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--trace']) + +test.execute() + +test.file_grep_not(test.trace_filename, r'var') + +test.passes() diff --git a/test_regress/t/t_trace_ena_cc.pl b/test_regress/t/t_trace_ena_cc.pl deleted file mode 100755 index 45818c373..000000000 --- a/test_regress/t/t_trace_ena_cc.pl +++ /dev/null @@ -1,32 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_trace_ena.v"); - -compile( - verilator_flags2 => ['-trace'], - ); - -execute( - ); - -if ($Self->{vlt_all}) { - file_grep("$Self->{obj_dir}/V$Self->{name}__Trace__0__Slow.cpp", qr/c_trace_on\"/); - file_grep_not("$Self->{obj_dir}/V$Self->{name}__Trace__0__Slow.cpp", qr/_trace_off\"/); - file_grep($Self->trace_filename, qr/\$enddefinitions/); - file_grep_not($Self->trace_filename, qr/inside_sub/); - - vcd_identical($Self->trace_filename, $Self->{golden_filename}); -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_ena_cc.py b/test_regress/t/t_trace_ena_cc.py new file mode 100755 index 000000000..925abfaf4 --- /dev/null +++ b/test_regress/t/t_trace_ena_cc.py @@ -0,0 +1,27 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_ena.v" + +test.compile(verilator_flags2=['-trace']) + +test.execute() + +if test.vlt_all: + test.file_grep(test.obj_dir + "/V" + test.name + "__Trace__0__Slow.cpp", r'c_trace_on\"') + test.file_grep_not(test.obj_dir + "/V" + test.name + "__Trace__0__Slow.cpp", r'_trace_off\"') + test.file_grep(test.trace_filename, r'\$enddefinitions') + test.file_grep_not(test.trace_filename, r'inside_sub') + + test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_ena_sc.pl b/test_regress/t/t_trace_ena_sc.pl deleted file mode 100755 index e2b01ac3f..000000000 --- a/test_regress/t/t_trace_ena_sc.pl +++ /dev/null @@ -1,35 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_sc) { - skip("No SystemC installed"); -} -else { - top_filename("t/t_trace_ena.v"); - - compile( - verilator_flags2 => ['-trace -sc'], - ); - - execute( - ); - - if ($Self->{vlt_all}) { - # Note more checks in _cc.pl - file_grep($Self->trace_filename, qr/\$enddefinitions/); - - vcd_identical($Self->trace_filename, $Self->{golden_filename}); - } -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_ena_sc.py b/test_regress/t/t_trace_ena_sc.py new file mode 100755 index 000000000..7b26b4db3 --- /dev/null +++ b/test_regress/t/t_trace_ena_sc.py @@ -0,0 +1,28 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_ena.v" + +if not test.have_sc: + test.skip("No SystemC installed") + +test.compile(verilator_flags2=['-trace -sc']) + +test.execute() + +if test.vlt_all: + # Note more checks in _cc.py + test.file_grep(test.trace_filename, r'\$enddefinitions') + + test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_enum_fst.pl b/test_regress/t/t_trace_enum_fst.pl deleted file mode 100755 index 582d0e773..000000000 --- a/test_regress/t/t_trace_enum_fst.pl +++ /dev/null @@ -1,33 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_trace_enum.v"); - -compile( - verilator_flags2 => ['--cc --trace-fst --output-split-ctrace 1'], - ); - -execute( - ); - -fst_identical($Self->trace_filename, $Self->{golden_filename}); - -# Five $attrbegin expected: -# - state_t declaration -# - t.v_enumed -# - t.sink.state -# - other_state_t declaration -# - t.v_other_enumed -file_grep_count($Self->{golden_filename}, qr/attrbegin/, 5); - -ok(1); -1; diff --git a/test_regress/t/t_trace_enum_fst.py b/test_regress/t/t_trace_enum_fst.py new file mode 100755 index 000000000..1f9a54afa --- /dev/null +++ b/test_regress/t/t_trace_enum_fst.py @@ -0,0 +1,29 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_enum.v" + +test.compile(verilator_flags2=['--cc --trace-fst --output-split-ctrace 1']) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +# Five $attrbegin expected: +# - state_t declaration +# - t.v_enumed +# - t.sink.state +# - other_state_t declaration +# - t.v_other_enumed +test.file_grep_count(test.golden_filename, r'attrbegin', 5) + +test.passes() diff --git a/test_regress/t/t_trace_flag_off.pl b/test_regress/t/t_trace_flag_off.pl deleted file mode 100755 index 32a214e08..000000000 --- a/test_regress/t/t_trace_flag_off.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# Test that without --trace we get a message when turning on traces -scenarios(vlt => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_trace_flag_off.py b/test_regress/t/t_trace_flag_off.py new file mode 100755 index 000000000..d0074dd4a --- /dev/null +++ b/test_regress/t/t_trace_flag_off.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +# Test that without --trace we get a message when turning on traces +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_fst.pl b/test_regress/t/t_trace_fst.pl deleted file mode 100755 index 7182a675f..000000000 --- a/test_regress/t/t_trace_fst.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } - -scenarios(vlt_all => 1); - -compile( - v_flags2 => ["--trace-fst"], -); - -execute( -); - -fst_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_fst.py b/test_regress/t/t_trace_fst.py new file mode 100755 index 000000000..c1d629013 --- /dev/null +++ b/test_regress/t/t_trace_fst.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(v_flags2=["--trace-fst"]) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_fst_cmake.pl b/test_regress/t/t_trace_fst_cmake.pl deleted file mode 100755 index 5fa31192c..000000000 --- a/test_regress/t/t_trace_fst_cmake.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } - -scenarios(vlt_all => 1); - -compile( - v_flags2 => ["--trace-fst"], - verilator_make_gmake => 0, - verilator_make_cmake => 1, -); - -execute( -); - -fst_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_fst_cmake.py b/test_regress/t/t_trace_fst_cmake.py new file mode 100755 index 000000000..8e70813e5 --- /dev/null +++ b/test_regress/t/t_trace_fst_cmake.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(v_flags2=["--trace-fst"], verilator_make_gmake=False, verilator_make_cmake=1) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_fst_sc.pl b/test_regress/t/t_trace_fst_sc.pl deleted file mode 100755 index ab25a627c..000000000 --- a/test_regress/t/t_trace_fst_sc.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } - -scenarios(vlt_all => 1); - -if (!$Self->have_sc) { - skip("No SystemC installed"); -} -else { - compile( - verilator_flags2 => ["--trace-fst --sc"], - ); - - execute( - ); - - fst_identical($Self->trace_filename, $Self->{golden_filename}); -} -ok(1); -1; diff --git a/test_regress/t/t_trace_fst_sc.py b/test_regress/t/t_trace_fst_sc.py new file mode 100755 index 000000000..70d59dba1 --- /dev/null +++ b/test_regress/t/t_trace_fst_sc.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +if not test.have_sc: + test.skip("No SystemC installed") + +test.compile(verilator_flags2=["--trace-fst --sc"]) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_fst_sc_cmake.pl b/test_regress/t/t_trace_fst_sc_cmake.pl deleted file mode 100755 index c2da5f054..000000000 --- a/test_regress/t/t_trace_fst_sc_cmake.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } - -scenarios(vlt_all => 1); - -if (!$Self->have_sc) { - skip("No SystemC installed"); -} -else { - compile( - verilator_flags2 => ["--trace-fst --sc"], - verilator_make_gmake => 0, - verilator_make_cmake => 1, - ); - - execute( - ); - - fst_identical($Self->trace_filename, $Self->{golden_filename}); -} -ok(1); -1; diff --git a/test_regress/t/t_trace_fst_sc_cmake.py b/test_regress/t/t_trace_fst_sc_cmake.py new file mode 100755 index 000000000..b5d8f5f0e --- /dev/null +++ b/test_regress/t/t_trace_fst_sc_cmake.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +if not test.have_sc: + test.skip("No SystemC installed") + +test.compile(verilator_flags2=["--trace-fst --sc"], + verilator_make_gmake=False, + verilator_make_cmake=1) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_iface.pl b/test_regress/t/t_trace_iface.pl deleted file mode 100755 index 7d0f5b87a..000000000 --- a/test_regress/t/t_trace_iface.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ['--trace'], - ); - -execute( - ); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_iface.py b/test_regress/t/t_trace_iface.py new file mode 100755 index 000000000..de8cf58ff --- /dev/null +++ b/test_regress/t/t_trace_iface.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['--trace']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_no_top_name.pl b/test_regress/t/t_trace_no_top_name.pl deleted file mode 100755 index 1d12a56ce..000000000 --- a/test_regress/t/t_trace_no_top_name.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--binary --main-top-name '-' --trace -Wno-MULTITOP"], - ); - -execute( - ); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_no_top_name.py b/test_regress/t/t_trace_no_top_name.py new file mode 100755 index 000000000..e3e6887f1 --- /dev/null +++ b/test_regress/t/t_trace_no_top_name.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary --main-top-name '-' --trace -Wno-MULTITOP"]) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_noflag_bad.pl b/test_regress/t/t_trace_noflag_bad.pl deleted file mode 100755 index 8271fa41d..000000000 --- a/test_regress/t/t_trace_noflag_bad.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - # We need to list verilated_vcd_c.cpp because without --trace Verilator - # won't build it itself automatically. - verilator_flags2 => ["--cc --exe $Self->{t_dir}/$Self->{name}_c.cpp verilated_vcd_c.cpp"], - make_top_shell => 0, - make_main => 0, - ); - -execute( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_trace_noflag_bad.py b/test_regress/t/t_trace_noflag_bad.py new file mode 100755 index 000000000..a61eb9bdd --- /dev/null +++ b/test_regress/t/t_trace_noflag_bad.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile( + # We need to list verilated_vcd_c.cpp because without --trace Verilator + # won't build it itself automatically. + verilator_flags2=["--cc --exe", test.t_dir + "/" + test.name + "_c.cpp verilated_vcd_c.cpp"], + make_top_shell=False, + make_main=False) + +test.execute(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_off_cc.pl b/test_regress/t/t_trace_off_cc.pl deleted file mode 100755 index 358ef5613..000000000 --- a/test_regress/t/t_trace_off_cc.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_trace_ena.v"); - -compile( - verilator_flags2 => ['-notrace'], - ); - -execute( - ); - -if ($Self->{vlt_all}) { - !-r $Self->trace_filename or error("Tracing should be off\n"); -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_off_cc.py b/test_regress/t/t_trace_off_cc.py new file mode 100755 index 000000000..27f02bff7 --- /dev/null +++ b/test_regress/t/t_trace_off_cc.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_ena.v" + +test.compile(verilator_flags2=['-notrace']) + +test.execute() + +if test.vlt_all: + if os.path.exists(test.trace_filename): + test.error("Tracing should be off") + +test.passes() diff --git a/test_regress/t/t_trace_off_sc.pl b/test_regress/t/t_trace_off_sc.pl deleted file mode 100755 index 4a09fc7e3..000000000 --- a/test_regress/t/t_trace_off_sc.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_trace_ena.v"); - -compile( - verilator_flags2 => ['-notrace -sc'], - ); - -execute( - ); - -if ($Self->{vlt_all}) { - !-r $Self->trace_filename or error("Tracing should be off\n"); -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_off_sc.py b/test_regress/t/t_trace_off_sc.py new file mode 100755 index 000000000..44a184b75 --- /dev/null +++ b/test_regress/t/t_trace_off_sc.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_ena.v" + +test.compile(verilator_flags2=['-notrace -sc']) + +test.execute() + +if test.vlt_all: + if os.path.exists(test.trace_filename): + test.error("Tracing should be off") + +test.passes() diff --git a/test_regress/t/t_trace_open_wrong_order_bad.pl b/test_regress/t/t_trace_open_wrong_order_bad.pl deleted file mode 100755 index 0d55a8647..000000000 --- a/test_regress/t/t_trace_open_wrong_order_bad.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["--cc --trace --exe $Self->{t_dir}/$Self->{name}.cpp"], - make_top_shell => 0, - make_main => 0, - ); - -execute( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_trace_open_wrong_order_bad.py b/test_regress/t/t_trace_open_wrong_order_bad.py new file mode 100755 index 000000000..691cb579b --- /dev/null +++ b/test_regress/t/t_trace_open_wrong_order_bad.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--cc --trace --exe", test.pli_filename], + make_top_shell=False, + make_main=False) + +test.execute(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_packed_struct.pl b/test_regress/t/t_trace_packed_struct.pl deleted file mode 100755 index 4517dd6c0..000000000 --- a/test_regress/t/t_trace_packed_struct.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["--trace"] - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_trace_packed_struct.py b/test_regress/t/t_trace_packed_struct.py new file mode 100755 index 000000000..66b2dd8cd --- /dev/null +++ b/test_regress/t/t_trace_packed_struct.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["--trace"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_trace_packed_struct_fst.pl b/test_regress/t/t_trace_packed_struct_fst.pl deleted file mode 100755 index d9d78af7e..000000000 --- a/test_regress/t/t_trace_packed_struct_fst.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_trace_packed_struct.v"); - -compile( - v_flags2 => ["--trace-fst"] - ); - -execute( - ); - -fst_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_packed_struct_fst.py b/test_regress/t/t_trace_packed_struct_fst.py new file mode 100755 index 000000000..4add1a2b6 --- /dev/null +++ b/test_regress/t/t_trace_packed_struct_fst.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_packed_struct.v" + +test.compile(v_flags2=["--trace-fst"]) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_packed_struct_fst_sc.pl b/test_regress/t/t_trace_packed_struct_fst_sc.pl deleted file mode 100755 index 6db94e45e..000000000 --- a/test_regress/t/t_trace_packed_struct_fst_sc.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_sc) { - skip("No SystemC installed"); -} -else { - top_filename("t/t_trace_packed_struct.v"); - - compile( - v_flags2 => ["--sc --trace-fst"] - ); - - execute( - ); - - fst_identical($Self->trace_filename, $Self->{golden_filename}); -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_packed_struct_fst_sc.py b/test_regress/t/t_trace_packed_struct_fst_sc.py new file mode 100755 index 000000000..e329e22e9 --- /dev/null +++ b/test_regress/t/t_trace_packed_struct_fst_sc.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_packed_struct.v" + +if not test.have_sc: + test.skip("No SystemC installed") + +test.compile(v_flags2=["--sc --trace-fst"]) + +test.execute() + +test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_param.pl b/test_regress/t/t_trace_param.pl deleted file mode 100755 index db2703aa7..000000000 --- a/test_regress/t/t_trace_param.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2013 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - v_flags2 => ["--trace"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_trace_param.py b/test_regress/t/t_trace_param.py new file mode 100755 index 000000000..7ed3e770d --- /dev/null +++ b/test_regress/t/t_trace_param.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(v_flags2=["--trace"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_trace_param_fst.pl b/test_regress/t/t_trace_param_fst.pl deleted file mode 100755 index d05f34a0b..000000000 --- a/test_regress/t/t_trace_param_fst.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2013 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_trace_param.v"); - -compile( - v_flags2 => ["--trace-fst"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_trace_param_fst.py b/test_regress/t/t_trace_param_fst.py new file mode 100755 index 000000000..863328841 --- /dev/null +++ b/test_regress/t/t_trace_param_fst.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_trace_param.v" + +test.compile(v_flags2=["--trace-fst"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_trace_param_override.pl b/test_regress/t/t_trace_param_override.pl deleted file mode 100755 index df4172e40..000000000 --- a/test_regress/t/t_trace_param_override.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --trace -GPOVERRODE=31"], - ); - -execute( - ); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_param_override.py b/test_regress/t/t_trace_param_override.py new file mode 100755 index 000000000..928c0acde --- /dev/null +++ b/test_regress/t/t_trace_param_override.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --trace -GPOVERRODE=31"]) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_primitive.pl b/test_regress/t/t_trace_primitive.pl deleted file mode 100755 index afbe303cb..000000000 --- a/test_regress/t/t_trace_primitive.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2013 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["--trace"], - ); - -execute( - ); - -if ($Self->{vlt_all}) { - file_grep($Self->trace_filename, "sub_t_i"); -}; - -ok(1); -1; diff --git a/test_regress/t/t_trace_primitive.py b/test_regress/t/t_trace_primitive.py new file mode 100755 index 000000000..7d9702fd0 --- /dev/null +++ b/test_regress/t/t_trace_primitive.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["--trace"]) + +test.execute() + +if test.vlt_all: + test.file_grep(test.trace_filename, "sub_t_i") + +test.passes() diff --git a/test_regress/t/t_trace_primitive_fst.pl b/test_regress/t/t_trace_primitive_fst.pl deleted file mode 100755 index 882e2e68d..000000000 --- a/test_regress/t/t_trace_primitive_fst.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2013 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_trace_primitive.v"); - -compile( - v_flags2 => ["--trace-fst"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_trace_primitive_fst.py b/test_regress/t/t_trace_primitive_fst.py new file mode 100755 index 000000000..186eb317d --- /dev/null +++ b/test_regress/t/t_trace_primitive_fst.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_primitive.v" + +test.compile(v_flags2=["--trace-fst"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_trace_primitive_fst_sc.pl b/test_regress/t/t_trace_primitive_fst_sc.pl deleted file mode 100755 index c0b821017..000000000 --- a/test_regress/t/t_trace_primitive_fst_sc.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2013 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_sc) { - skip("No SystemC installed"); -} -else { - top_filename("t/t_trace_primitive.v"); - - compile( - v_flags2 => ["--sc --trace-fst"], - ); - - execute( - ); -} -ok(1); -1; diff --git a/test_regress/t/t_trace_primitive_fst_sc.py b/test_regress/t/t_trace_primitive_fst_sc.py new file mode 100755 index 000000000..2c19efdfe --- /dev/null +++ b/test_regress/t/t_trace_primitive_fst_sc.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_primitive.v" + +if not test.have_sc: + test.skip("No SystemC installed") + +test.compile(v_flags2=["--sc --trace-fst"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_trace_public_func.pl b/test_regress/t/t_trace_public_func.pl deleted file mode 100755 index 8620cd080..000000000 --- a/test_regress/t/t_trace_public_func.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_trace_public.v"); -golden_filename("t/t_trace_public.out"); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ["-DATTRIBUTES -DPUB_FUNC --trace --exe $Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - ); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_public_func.py b/test_regress/t/t_trace_public_func.py new file mode 100755 index 000000000..415f64bc3 --- /dev/null +++ b/test_regress/t/t_trace_public_func.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_trace_public.v" +test.golden_filename = "t/t_trace_public.out" + +test.compile(make_top_shell=False, + make_main=False, + v_flags2=["-DATTRIBUTES -DPUB_FUNC --trace --exe", test.pli_filename]) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_public_func_vlt.pl b/test_regress/t/t_trace_public_func_vlt.pl deleted file mode 100755 index d4bc5e0eb..000000000 --- a/test_regress/t/t_trace_public_func_vlt.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_trace_public.v"); -golden_filename("t/t_trace_public.out"); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ["-DPUB_FUNC --trace --exe $Self->{t_dir}/t_trace_public_func.cpp $Self->{t_dir}/t_trace_public_func.vlt"], - ); - -execute( - ); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_public_func_vlt.py b/test_regress/t/t_trace_public_func_vlt.py new file mode 100755 index 000000000..da815dcdd --- /dev/null +++ b/test_regress/t/t_trace_public_func_vlt.py @@ -0,0 +1,28 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_trace_public_func.cpp" +test.top_filename = "t/t_trace_public.v" +test.golden_filename = "t/t_trace_public.out" + +test.compile(make_top_shell=False, + make_main=False, + v_flags2=[ + "-DPUB_FUNC --trace --exe", test.pli_filename, + test.t_dir + "/t_trace_public_func.vlt" + ]) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_public_sig.pl b/test_regress/t/t_trace_public_sig.pl deleted file mode 100755 index ab7ffefe2..000000000 --- a/test_regress/t/t_trace_public_sig.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_trace_public.v"); -golden_filename("t/t_trace_public.out"); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ["-DATTRIBUTES --trace --exe $Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - ); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); - -# vcd_identical doesn't detect "$var a.b;" vs "$scope module a; $var b;" -file_grep($Self->trace_filename, qr/module glbl/); - -ok(1); -1; diff --git a/test_regress/t/t_trace_public_sig.py b/test_regress/t/t_trace_public_sig.py new file mode 100755 index 000000000..21f4444c9 --- /dev/null +++ b/test_regress/t/t_trace_public_sig.py @@ -0,0 +1,27 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_trace_public.v" +test.golden_filename = "t/t_trace_public.out" + +test.compile(make_top_shell=False, + make_main=False, + v_flags2=["-DATTRIBUTES --trace --exe", test.pli_filename]) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +# vcd_identical doesn't detect "$var a.b;" vs "$scope module a; $var b;" +test.file_grep(test.trace_filename, r'module glbl') + +test.passes() diff --git a/test_regress/t/t_trace_public_sig_vlt.pl b/test_regress/t/t_trace_public_sig_vlt.pl deleted file mode 100755 index 1e853faa7..000000000 --- a/test_regress/t/t_trace_public_sig_vlt.pl +++ /dev/null @@ -1,37 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_trace_public.v"); -golden_filename("t/t_trace_public.out"); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ["--trace --exe $Self->{t_dir}/t_trace_public_sig.cpp $Self->{t_dir}/t_trace_public_sig.vlt --no-json-edit-nums"], - ); - -if ($Self->{vlt_all}) { - file_grep("$out_filename", qr/{"type":"VAR","name":"GSR",.*"loc":"f,47:[^"]*",.*"origName":"GSR",.*"isSigPublic":true,.*"dtypeName":"logic",.*"isSigUserRdPublic":true.*"isSigUserRWPublic":true/); -} - -execute( - ); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); - -# vcd_identical doesn't detect "$var a.b;" vs "$scope module a; $var b;" -file_grep($Self->trace_filename, qr/module glbl/); - -ok(1); -1; diff --git a/test_regress/t/t_trace_public_sig_vlt.py b/test_regress/t/t_trace_public_sig_vlt.py new file mode 100755 index 000000000..743751fa9 --- /dev/null +++ b/test_regress/t/t_trace_public_sig_vlt.py @@ -0,0 +1,39 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_trace_public_sig.cpp" +test.top_filename = "t/t_trace_public.v" +test.golden_filename = "t/t_trace_public.out" + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(make_top_shell=False, + make_main=False, + v_flags2=[ + "--trace --exe", test.pli_filename, + test.t_dir + "/t_trace_public_sig.vlt --no-json-edit-nums" + ]) + +if test.vlt_all: + test.file_grep( + out_filename, + r'{"type":"VAR","name":"GSR",.*"loc":"f,47:[^"]*",.*"origName":"GSR",.*"isSigPublic":true,.*"dtypeName":"logic",.*"isSigUserRdPublic":true.*"isSigUserRWPublic":true' + ) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +# vcd_identical doesn't detect "$var a.b;" vs "$scope module a; $var b;" +test.file_grep(test.trace_filename, r'module glbl') + +test.passes() diff --git a/test_regress/t/t_trace_rollover.pl b/test_regress/t/t_trace_rollover.pl deleted file mode 100755 index df8c2e695..000000000 --- a/test_regress/t/t_trace_rollover.pl +++ /dev/null @@ -1,35 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2013 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t_trace_cat.v"); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ["--trace --exe $Self->{t_dir}/t_trace_rollover.cpp"], - ); - -execute( - ); - -system("cat $Self->{obj_dir}/simrollover_cat*.vcd " - . " > $Self->{obj_dir}/simall.vcd"); - -vcd_identical("$Self->{obj_dir}/simall.vcd", - $Self->{golden_filename}); - -file_grep_not("$Self->{obj_dir}/simrollover_cat0000.vcd", qr/^#/); -file_grep("$Self->{obj_dir}/simrollover_cat0001.vcd", qr/^#/); -file_grep("$Self->{obj_dir}/simrollover_cat0002.vcd", qr/^#/); - -ok(1); -1; diff --git a/test_regress/t/t_trace_rollover.py b/test_regress/t/t_trace_rollover.py new file mode 100755 index 000000000..4764e4ba6 --- /dev/null +++ b/test_regress/t/t_trace_rollover.py @@ -0,0 +1,27 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t_trace_cat.v" + +test.compile(make_top_shell=False, make_main=False, v_flags2=["--trace --exe", test.pli_filename]) + +test.execute() + +os.system("cat " + test.obj_dir + "/simrollover_cat*.vcd " + " > " + test.obj_dir + "/simall.vcd") + +test.vcd_identical(test.obj_dir + "/simall.vcd", test.golden_filename) + +test.file_grep_not(test.obj_dir + "/simrollover_cat0000.vcd", r'^#') +test.file_grep(test.obj_dir + "/simrollover_cat0001.vcd", r'^#') +test.file_grep(test.obj_dir + "/simrollover_cat0002.vcd", r'^#') + +test.passes() diff --git a/test_regress/t/t_trace_sc_empty.pl b/test_regress/t/t_trace_sc_empty.pl deleted file mode 100755 index e8d7ccc84..000000000 --- a/test_regress/t/t_trace_sc_empty.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['-sc', '--trace'], - ); - -ok(1); -1; diff --git a/test_regress/t/t_trace_sc_empty.py b/test_regress/t/t_trace_sc_empty.py new file mode 100755 index 000000000..ae5b13494 --- /dev/null +++ b/test_regress/t/t_trace_sc_empty.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['-sc', '--trace']) + +test.passes() diff --git a/test_regress/t/t_trace_scope_no_inline.pl b/test_regress/t/t_trace_scope_no_inline.pl deleted file mode 100755 index 6c1c43d30..000000000 --- a/test_regress/t/t_trace_scope_no_inline.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["--cc --trace -fno-inline t/$Self->{name}.vlt"], - ); - -execute( - ); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_scope_no_inline.py b/test_regress/t/t_trace_scope_no_inline.py new file mode 100755 index 000000000..0944e381c --- /dev/null +++ b/test_regress/t/t_trace_scope_no_inline.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--cc --trace -fno-inline t/" + test.name + ".vlt"]) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_scope_vlt.pl b/test_regress/t/t_trace_scope_vlt.pl deleted file mode 100755 index ddf12b376..000000000 --- a/test_regress/t/t_trace_scope_vlt.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_trace_scope_vlt.v"); - -compile( - v_flags2 => ["--trace t/t_trace_scope_vlt.vlt"], - ); - -execute( - ); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_scope_vlt.py b/test_regress/t/t_trace_scope_vlt.py new file mode 100755 index 000000000..7c58f9479 --- /dev/null +++ b/test_regress/t/t_trace_scope_vlt.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_trace_scope_vlt.v" + +test.compile(v_flags2=["--trace t/t_trace_scope_vlt.vlt"]) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_scstruct.pl b/test_regress/t/t_trace_scstruct.pl deleted file mode 100755 index fb375c474..000000000 --- a/test_regress/t/t_trace_scstruct.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--sc --trace --trace-structs --pins-bv 2'], - ); - -#execute(); # didn't bother with top shell - -ok(1); -1; diff --git a/test_regress/t/t_trace_scstruct.py b/test_regress/t/t_trace_scstruct.py new file mode 100755 index 000000000..3dd077924 --- /dev/null +++ b/test_regress/t/t_trace_scstruct.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--sc --trace --trace-structs --pins-bv 2']) + +#test.execute() # didn't bother with top shell + +test.passes() diff --git a/test_regress/t/t_trace_split_cfuncs.pl b/test_regress/t/t_trace_split_cfuncs.pl deleted file mode 100755 index 4959ee710..000000000 --- a/test_regress/t/t_trace_split_cfuncs.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["--trace", "--output-split-cfuncs", "1"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_trace_split_cfuncs.py b/test_regress/t/t_trace_split_cfuncs.py new file mode 100755 index 000000000..b1b588c76 --- /dev/null +++ b/test_regress/t/t_trace_split_cfuncs.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["--trace", "--output-split-cfuncs", "1"]) + +test.passes() diff --git a/test_regress/t/t_trace_split_cfuncs_dpi_export.pl b/test_regress/t/t_trace_split_cfuncs_dpi_export.pl deleted file mode 100755 index 4959ee710..000000000 --- a/test_regress/t/t_trace_split_cfuncs_dpi_export.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["--trace", "--output-split-cfuncs", "1"] - ); - -ok(1); -1; diff --git a/test_regress/t/t_trace_split_cfuncs_dpi_export.py b/test_regress/t/t_trace_split_cfuncs_dpi_export.py new file mode 100755 index 000000000..b1b588c76 --- /dev/null +++ b/test_regress/t/t_trace_split_cfuncs_dpi_export.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["--trace", "--output-split-cfuncs", "1"]) + +test.passes() diff --git a/test_regress/t/t_trace_string.pl b/test_regress/t/t_trace_string.pl deleted file mode 100755 index 3b56b40ca..000000000 --- a/test_regress/t/t_trace_string.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--cc --trace'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_trace_string.py b/test_regress/t/t_trace_string.py new file mode 100755 index 000000000..f9c1f82de --- /dev/null +++ b/test_regress/t/t_trace_string.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--cc --trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_trace_string_fst.pl b/test_regress/t/t_trace_string_fst.pl deleted file mode 100755 index 2ead118b7..000000000 --- a/test_regress/t/t_trace_string_fst.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_trace_string.v"); - -compile( - verilator_flags2 => ['--cc --trace'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_trace_string_fst.py b/test_regress/t/t_trace_string_fst.py new file mode 100755 index 000000000..cf926f0d2 --- /dev/null +++ b/test_regress/t/t_trace_string_fst.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_string.v" + +test.compile(verilator_flags2=['--cc --trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_trace_string_fst_sc.pl b/test_regress/t/t_trace_string_fst_sc.pl deleted file mode 100755 index a40fdd595..000000000 --- a/test_regress/t/t_trace_string_fst_sc.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_sc) { - skip("No SystemC installed"); -} -else { - top_filename("t/t_trace_string.v"); - - compile( - verilator_flags2 => ['--sc --trace'], - ); - - execute( - ); -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_string_fst_sc.py b/test_regress/t/t_trace_string_fst_sc.py new file mode 100755 index 000000000..dc56e4069 --- /dev/null +++ b/test_regress/t/t_trace_string_fst_sc.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_string.v" + +if not test.have_sc: + test.skip("No SystemC installed") + +test.compile(verilator_flags2=['--sc --trace']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_trace_timescale.pl b/test_regress/t/t_trace_timescale.pl deleted file mode 100755 index 58eb89383..000000000 --- a/test_regress/t/t_trace_timescale.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2013 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - v_flags2 => ["--trace"], - ); - -execute( - ); - -vcd_identical($Self->trace_filename, - $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_timescale.py b/test_regress/t/t_trace_timescale.py new file mode 100755 index 000000000..8c2aacbfb --- /dev/null +++ b/test_regress/t/t_trace_timescale.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(v_flags2=["--trace"]) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_timing1.pl b/test_regress/t/t_trace_timing1.pl deleted file mode 100755 index b0f66538a..000000000 --- a/test_regress/t/t_trace_timing1.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags => [# Custom as don't want -cc - "-Mdir $Self->{obj_dir}", - "--debug-check", ], - verilator_flags2 => ['--binary --trace'], - make_main => 0, - ); - -execute( - ); - -vcd_identical($Self->trace_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_trace_timing1.py b/test_regress/t/t_trace_timing1.py new file mode 100755 index 000000000..1ddc50dab --- /dev/null +++ b/test_regress/t/t_trace_timing1.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + verilator_flags=[ # Custom as don't want -cc + "-Mdir", test.obj_dir, "--debug-check" + ], + verilator_flags2=['--binary --trace'], + make_main=False) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_two_dump_cc.pl b/test_regress/t/t_trace_two_dump_cc.pl deleted file mode 100755 index aeb3cbacd..000000000 --- a/test_regress/t/t_trace_two_dump_cc.pl +++ /dev/null @@ -1,45 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# Test tracing with two models instanced -scenarios(vlt_all => 1); - -top_filename("t_trace_two_a.v"); - -compile( - make_main => 0, - verilator_make_gmake => 0, - top_filename => 't_trace_two_b.v', - vm_prefix => 'Vt_trace_two_b', - verilator_flags2 => ['-trace'], - ); - -run( - logfile => "$Self->{obj_dir}/make_first_ALL.log", - cmd => ["make", "-C", "$Self->{obj_dir}", "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp"] - ); - -compile( - make_main => 0, - top_filename => 't_trace_two_a.v', - verilator_flags2 => ['-exe', '-trace', "$Self->{t_dir}/t_trace_two_cc.cpp"], - v_flags2 => ['+define+TEST_DUMP'], - ); - -execute( - ); - -if ($Self->{vlt_all}) { - file_grep($Self->trace_filename, qr/\$enddefinitions/); - vcd_identical($Self->trace_filename, $Self->{golden_filename}); -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_two_dump_cc.py b/test_regress/t/t_trace_two_dump_cc.py new file mode 100755 index 000000000..6170a75b7 --- /dev/null +++ b/test_regress/t/t_trace_two_dump_cc.py @@ -0,0 +1,37 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +# Test tracing with two models instanced +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t_trace_two_a.v" + +test.compile(make_main=False, + verilator_make_gmake=False, + top_filename='t_trace_two_b.v', + vm_prefix='Vt_trace_two_b', + verilator_flags2=['-trace']) + +test.run( + logfile=test.obj_dir + "/make_first_ALL.log", + cmd=["make", "-C", "" + test.obj_dir, "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp"]) + +test.compile(make_main=False, + top_filename='t_trace_two_a.v', + verilator_flags2=['-exe', '-trace', test.t_dir + "/t_trace_two_cc.cpp"], + v_flags2=['+define+TEST_DUMP']) + +test.execute() + +if test.vlt_all: + test.file_grep(test.trace_filename, r'\$enddefinitions') + test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_two_dump_sc.pl b/test_regress/t/t_trace_two_dump_sc.pl deleted file mode 100755 index b5ac703ad..000000000 --- a/test_regress/t/t_trace_two_dump_sc.pl +++ /dev/null @@ -1,50 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_sc) { - skip("No SystemC installed"); -} -else { - top_filename("t_trace_two_a.v"); - - compile( - make_main => 0, - verilator_make_gmake => 0, - top_filename => 't_trace_two_b.v', - vm_prefix => 'Vt_trace_two_b', - verilator_flags2 => ['-sc -trace'], - ); - - run( - logfile => "$Self->{obj_dir}/make_first_ALL.log", - cmd => ["make", "-C", "$Self->{obj_dir}", "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp"] - ); - - compile( - make_main => 0, - top_filename => 't_trace_two_a.v', - verilator_flags2 => ['-sc', '-exe', '-trace', - "$Self->{t_dir}/t_trace_two_sc.cpp"], - v_flags2 => ['+define+TEST_DUMP'], - ); - - execute( - ); - - if ($Self->{vlt_all}) { - file_grep($Self->trace_filename, qr/\$enddefinitions/); - vcd_identical($Self->trace_filename, $Self->{golden_filename}); - } -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_two_dump_sc.py b/test_regress/t/t_trace_two_dump_sc.py new file mode 100755 index 000000000..1dc86e098 --- /dev/null +++ b/test_regress/t/t_trace_two_dump_sc.py @@ -0,0 +1,38 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t_trace_two_a.v" + +if not test.have_sc: + test.skip("No SystemC installed") + +test.compile(make_main=False, + verilator_make_gmake=False, + top_filename='t_trace_two_b.v', + vm_prefix='Vt_trace_two_b', + verilator_flags2=['-sc -trace']) + +test.run(logfile=test.obj_dir + "/make_first_ALL.log", + cmd=["make", "-C", test.obj_dir, "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp"]) + +test.compile(make_main=False, + top_filename='t_trace_two_a.v', + verilator_flags2=['-sc', '-exe', '-trace', test.t_dir + "/t_trace_two_sc.cpp"], + v_flags2=['+define+TEST_DUMP']) + +test.execute() + +if test.vlt_all: + test.file_grep(test.trace_filename, r'\$enddefinitions') + test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_two_dumpfst_cc.pl b/test_regress/t/t_trace_two_dumpfst_cc.pl deleted file mode 100755 index 29620901d..000000000 --- a/test_regress/t/t_trace_two_dumpfst_cc.pl +++ /dev/null @@ -1,46 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# Test tracing with two models instanced -scenarios(vlt_all => 1); - -top_filename("t_trace_two_a.v"); - -compile( - make_main => 0, - verilator_make_gmake => 0, - top_filename => 't_trace_two_b.v', - vm_prefix => 'Vt_trace_two_b', - verilator_flags2 => ['--trace-fst --trace-threads 1 -DTEST_FST'], - ); - -run( - logfile => "$Self->{obj_dir}/make_first_ALL.log", - cmd => ["make", "-C", "$Self->{obj_dir}", "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp"] - ); - -compile( - make_main => 0, - top_filename => 't_trace_two_a.v', - verilator_flags2 => ['-exe', '--trace-fst --trace-threads 1', - '-DTEST_FST', - "$Self->{t_dir}/t_trace_two_cc.cpp"], - v_flags2 => ['+define+TEST_DUMP'], - ); - -execute( - ); - -if ($Self->{vlt_all}) { - fst_identical($Self->trace_filename, $Self->{golden_filename}); -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_two_dumpfst_cc.py b/test_regress/t/t_trace_two_dumpfst_cc.py new file mode 100755 index 000000000..525c4698a --- /dev/null +++ b/test_regress/t/t_trace_two_dumpfst_cc.py @@ -0,0 +1,38 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +# Test tracing with two models instanced +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t_trace_two_a.v" + +test.compile(make_main=False, + verilator_make_gmake=False, + top_filename='t_trace_two_b.v', + vm_prefix='Vt_trace_two_b', + verilator_flags2=['--trace-fst --trace-threads 1 -DTEST_FST']) + +test.run(logfile=test.obj_dir + "/make_first_ALL.log", + cmd=["make", "-C", test.obj_dir, "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp"]) + +test.compile(make_main=False, + top_filename='t_trace_two_a.v', + verilator_flags2=[ + '-exe', '--trace-fst --trace-threads 1', '-DTEST_FST', + test.t_dir + "/t_trace_two_cc.cpp" + ], + v_flags2=['+define+TEST_DUMP']) + +test.execute() + +if test.vlt_all: + test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_two_hdr_cc.pl b/test_regress/t/t_trace_two_hdr_cc.pl deleted file mode 100755 index cd68e6945..000000000 --- a/test_regress/t/t_trace_two_hdr_cc.pl +++ /dev/null @@ -1,45 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# Test tracing with two models instanced -scenarios(vlt_all => 1); - -top_filename("t_trace_two_a.v"); - -compile( - make_main => 0, - verilator_make_gmake => 0, - top_filename => 't_trace_two_b.v', - vm_prefix => 'Vt_trace_two_b', - verilator_flags2 => ['-trace'], - ); - -run( - logfile => "$Self->{obj_dir}/make_first_ALL.log", - cmd => ["make", "-C", "$Self->{obj_dir}", "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp"] - ); - -compile( - make_main => 0, - top_filename => 't_trace_two_a.v', - make_flags => 'CPPFLAGS_ADD=-DTEST_HDR_TRACE=1', - verilator_flags2 => ['-exe', '-trace', "$Self->{t_dir}/t_trace_two_cc.cpp"], - ); - -execute( - ); - -if ($Self->{vlt_all}) { - file_grep($Self->trace_filename, qr/\$enddefinitions/); - vcd_identical($Self->trace_filename, $Self->{golden_filename}); -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_two_hdr_cc.py b/test_regress/t/t_trace_two_hdr_cc.py new file mode 100755 index 000000000..3aef38dc9 --- /dev/null +++ b/test_regress/t/t_trace_two_hdr_cc.py @@ -0,0 +1,36 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +# Test tracing with two models instanced +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t_trace_two_a.v" + +test.compile(make_main=False, + verilator_make_gmake=False, + top_filename='t_trace_two_b.v', + vm_prefix='Vt_trace_two_b', + verilator_flags2=['-trace']) + +test.run(logfile=test.obj_dir + "/make_first_ALL.log", + cmd=["make", "-C", test.obj_dir, "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp"]) + +test.compile(make_main=False, + top_filename='t_trace_two_a.v', + make_flags=['CPPFLAGS_ADD=-DTEST_HDR_TRACE=1'], + verilator_flags2=['-exe', '-trace', test.t_dir + "/t_trace_two_cc.cpp"]) + +test.execute() + +if test.vlt_all: + test.file_grep(test.trace_filename, r'\$enddefinitions') + test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_two_hdr_sc.pl b/test_regress/t/t_trace_two_hdr_sc.pl deleted file mode 100755 index 6592dc147..000000000 --- a/test_regress/t/t_trace_two_hdr_sc.pl +++ /dev/null @@ -1,50 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_sc) { - skip("No SystemC installed"); -} -else { - top_filename("t_trace_two_a.v"); - - compile( - make_main => 0, - verilator_make_gmake => 0, - top_filename => 't_trace_two_b.v', - vm_prefix => 'Vt_trace_two_b', - verilator_flags2 => ['-sc -trace'], - ); - - run( - logfile => "$Self->{obj_dir}/make_first_ALL.log", - cmd => ["make", "-C", "$Self->{obj_dir}", "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp"] - ); - - compile( - make_main => 0, - top_filename => 't_trace_two_a.v', - make_flags => 'CPPFLAGS_ADD=-DTEST_HDR_TRACE', - verilator_flags2 => ['-sc', '-exe', '-trace', - "$Self->{t_dir}/t_trace_two_sc.cpp"], - ); - - execute( - ); - - if ($Self->{vlt_all}) { - file_grep($Self->trace_filename, qr/\$enddefinitions/); - vcd_identical($Self->trace_filename, $Self->{golden_filename}); - } -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_two_hdr_sc.py b/test_regress/t/t_trace_two_hdr_sc.py new file mode 100755 index 000000000..5f2557ce7 --- /dev/null +++ b/test_regress/t/t_trace_two_hdr_sc.py @@ -0,0 +1,38 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t_trace_two_a.v" + +if not test.have_sc: + test.skip("No SystemC installed") + +test.compile(make_main=False, + verilator_make_gmake=False, + top_filename='t_trace_two_b.v', + vm_prefix='Vt_trace_two_b', + verilator_flags2=['-sc -trace']) + +test.run(logfile=test.obj_dir + "/make_first_ALL.log", + cmd=["make", "-C", test.obj_dir, "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp"]) + +test.compile(make_main=False, + top_filename='t_trace_two_a.v', + make_flags=['CPPFLAGS_ADD=-DTEST_HDR_TRACE'], + verilator_flags2=['-sc', '-exe', '-trace', test.t_dir + "/t_trace_two_sc.cpp"]) + +test.execute() + +if test.vlt_all: + test.file_grep(test.trace_filename, r'\$enddefinitions') + test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_two_hdrfst_cc.pl b/test_regress/t/t_trace_two_hdrfst_cc.pl deleted file mode 100755 index de1e78491..000000000 --- a/test_regress/t/t_trace_two_hdrfst_cc.pl +++ /dev/null @@ -1,46 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# Test tracing with two models instanced -scenarios(vlt_all => 1); - -top_filename("t_trace_two_a.v"); - -compile( - make_main => 0, - verilator_make_gmake => 0, - top_filename => 't_trace_two_b.v', - vm_prefix => 'Vt_trace_two_b', - verilator_flags2 => ['--trace-fst --trace-threads 1'], - ); - -run( - logfile => "$Self->{obj_dir}/make_first_ALL.log", - cmd => ["make", "-C", "$Self->{obj_dir}", "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp"] - ); - -compile( - make_main => 0, - top_filename => 't_trace_two_a.v', - make_flags => 'CPPFLAGS_ADD="-DTEST_HDR_TRACE=1 -DTEST_FST=1"', - verilator_flags2 => ['-exe', '--trace-fst --trace-threads 1', - '-DTEST_FST', - "$Self->{t_dir}/t_trace_two_cc.cpp"], - ); - -execute( - ); - -if ($Self->{vlt_all}) { - fst_identical($Self->trace_filename, $Self->{golden_filename}); -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_two_hdrfst_cc.py b/test_regress/t/t_trace_two_hdrfst_cc.py new file mode 100755 index 000000000..8b0157b74 --- /dev/null +++ b/test_regress/t/t_trace_two_hdrfst_cc.py @@ -0,0 +1,39 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +# Test tracing with two models instanced +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t_trace_two_a.v" + +test.compile(make_main=False, + verilator_make_gmake=False, + top_filename='t_trace_two_b.v', + vm_prefix='Vt_trace_two_b', + verilator_flags2=['--trace-fst --trace-threads 1']) + +test.run( + logfile=test.obj_dir + "/make_first_ALL.log", + cmd=["make", "-C", "" + test.obj_dir, "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp"]) + +test.compile(make_main=False, + top_filename='t_trace_two_a.v', + make_flags=['CPPFLAGS_ADD="-DTEST_HDR_TRACE=1 -DTEST_FST=1"'], + verilator_flags2=[ + '-exe', '--trace-fst --trace-threads 1', '-DTEST_FST', + test.t_dir + "/t_trace_two_cc.cpp" + ]) + +test.execute() + +if test.vlt_all: + test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_two_port_cc.pl b/test_regress/t/t_trace_two_port_cc.pl deleted file mode 100755 index efef151d8..000000000 --- a/test_regress/t/t_trace_two_port_cc.pl +++ /dev/null @@ -1,45 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# Test tracing with two models instanced -scenarios(vlt_all => 1); - -top_filename("t_trace_two_a.v"); - -compile( - make_main => 0, - verilator_make_gmake => 0, - top_filename => 't_trace_two_b.v', - vm_prefix => 'Vt_trace_two_b', - verilator_flags2 => ['-trace'], - ); - -run( - logfile => "$Self->{obj_dir}/make_first_ALL.log", - cmd => ["make", "-C", "$Self->{obj_dir}", "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp"] - ); - -compile( - make_main => 0, - top_filename => 't_trace_two_a.v', - verilator_flags2 => ['-exe', '-trace', "$Self->{t_dir}/t_trace_two_cc.cpp"], - v_flags2 => ['+define+TEST_DUMPPORTS'], - ); - -execute( - ); - -if ($Self->{vlt_all}) { - file_grep($Self->trace_filename, qr/\$enddefinitions/); - vcd_identical($Self->trace_filename, $Self->{golden_filename}); -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_two_port_cc.py b/test_regress/t/t_trace_two_port_cc.py new file mode 100755 index 000000000..4c3461f0d --- /dev/null +++ b/test_regress/t/t_trace_two_port_cc.py @@ -0,0 +1,36 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +# Test tracing with two models instanced +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t_trace_two_a.v" + +test.compile(make_main=False, + verilator_make_gmake=False, + top_filename='t_trace_two_b.v', + vm_prefix='Vt_trace_two_b', + verilator_flags2=['-trace']) + +test.run(logfile=test.obj_dir + "/make_first_ALL.log", + cmd=["make", "-C", test.obj_dir, "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp"]) + +test.compile(make_main=False, + top_filename='t_trace_two_a.v', + verilator_flags2=['-exe', '-trace', test.t_dir + "/t_trace_two_cc.cpp"], + v_flags2=['+define+TEST_DUMPPORTS']) + +test.execute() + +if test.vlt_all: + test.file_grep(test.trace_filename, r'\$enddefinitions') + test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_two_port_sc.pl b/test_regress/t/t_trace_two_port_sc.pl deleted file mode 100755 index 085bb2b11..000000000 --- a/test_regress/t/t_trace_two_port_sc.pl +++ /dev/null @@ -1,50 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -if (!$Self->have_sc) { - skip("No SystemC installed"); -} -else { - top_filename("t_trace_two_a.v"); - - compile( - make_main => 0, - verilator_make_gmake => 0, - top_filename => 't_trace_two_b.v', - vm_prefix => 'Vt_trace_two_b', - verilator_flags2 => ['-sc -trace'], - ); - - run( - logfile => "$Self->{obj_dir}/make_first_ALL.log", - cmd => ["make", "-C", "$Self->{obj_dir}", "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp"] - ); - - compile( - make_main => 0, - top_filename => 't_trace_two_a.v', - verilator_flags2 => ['-sc', '-exe', '-trace', - "$Self->{t_dir}/t_trace_two_sc.cpp"], - v_flags2 => ['+define+TEST_DUMPPORTS'], - ); - - execute( - ); - - if ($Self->{vlt_all}) { - file_grep($Self->trace_filename, qr/\$enddefinitions/); - vcd_identical($Self->trace_filename, $Self->{golden_filename}); - } -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_two_port_sc.py b/test_regress/t/t_trace_two_port_sc.py new file mode 100755 index 000000000..051ed305b --- /dev/null +++ b/test_regress/t/t_trace_two_port_sc.py @@ -0,0 +1,39 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_sc: + test.skip("No SystemC installed") + +top_filename = "t_trace_two_a.v" + +test.compile(make_main=False, + verilator_make_gmake=False, + top_filename='t_trace_two_b.v', + vm_prefix='Vt_trace_two_b', + verilator_flags2=['-sc -trace']) + +test.run(logfile=test.obj_dir + "/make_first_ALL.log", + cmd=["make", "-C", test.obj_dir, "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp"]) + +test.compile(make_main=False, + top_filename='t_trace_two_a.v', + verilator_flags2=['-sc', '-exe', '-trace', test.t_dir + "/t_trace_two_sc.cpp"], + v_flags2=['+define+TEST_DUMPPORTS']) + +test.execute() + +if test.vlt_all: + test.file_grep(test.trace_filename, r'\$enddefinitions') + test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_two_portfst_cc.pl b/test_regress/t/t_trace_two_portfst_cc.pl deleted file mode 100755 index db60aecfa..000000000 --- a/test_regress/t/t_trace_two_portfst_cc.pl +++ /dev/null @@ -1,46 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# Test tracing with two models instanced -scenarios(vlt_all => 1); - -top_filename("t_trace_two_a.v"); - -compile( - make_main => 0, - verilator_make_gmake => 0, - top_filename => 't_trace_two_b.v', - vm_prefix => 'Vt_trace_two_b', - verilator_flags2 => ['--trace-fst --trace-threads 1'], - ); - -run( - logfile => "$Self->{obj_dir}/make_first_ALL.log", - cmd => ["make", "-C", "$Self->{obj_dir}", "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp"] - ); - -compile( - make_main => 0, - top_filename => 't_trace_two_a.v', - verilator_flags2 => ['-exe', '--trace-fst --trace-threads 1', - '-DTEST_FST', - "$Self->{t_dir}/t_trace_two_cc.cpp"], - v_flags2 => ['+define+TEST_DUMPPORTS'], - ); - -execute( - ); - -if ($Self->{vlt_all}) { - fst_identical($Self->trace_filename, $Self->{golden_filename}); -} - -ok(1); -1; diff --git a/test_regress/t/t_trace_two_portfst_cc.py b/test_regress/t/t_trace_two_portfst_cc.py new file mode 100755 index 000000000..060eda528 --- /dev/null +++ b/test_regress/t/t_trace_two_portfst_cc.py @@ -0,0 +1,39 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +# Test tracing with two models instanced +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t_trace_two_a.v" + +test.compile(make_main=False, + verilator_make_gmake=False, + top_filename='t_trace_two_b.v', + vm_prefix='Vt_trace_two_b', + verilator_flags2=['--trace-fst --trace-threads 1']) + +test.run( + logfile=test.obj_dir + "/make_first_ALL.log", + cmd=["make", "-C", "" + test.obj_dir, "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp"]) + +test.compile(make_main=False, + top_filename='t_trace_two_a.v', + verilator_flags2=[ + '-exe', '--trace-fst --trace-threads 1', '-DTEST_FST', + test.t_dir + "/t_trace_two_cc.cpp" + ], + v_flags2=['+define+TEST_DUMPPORTS']) + +test.execute() + +if test.vlt_all: + test.fst_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_ub_misaligned_address.pl b/test_regress/t/t_trace_ub_misaligned_address.pl deleted file mode 100755 index aa1f7c66c..000000000 --- a/test_regress/t/t_trace_ub_misaligned_address.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_trace_ub_misaligned_address.v"); - -compile( - verilator_flags2 => ["--binary --trace", - "-CFLAGS -fsanitize=address,undefined", - "-LDFLAGS -fsanitize=address,undefined"], - ); - -execute( - aslr_off => 1, # Some GCC versions hit an address-sanitizer bug otherwise - ); - -# Make sure that there are no additional messages (such as runtime messages -# regarding undefined behavior). -files_identical("$Self->{obj_dir}/vlt_sim.log", $Self->{golden_filename}, "logfile"); - -ok(1); -1; diff --git a/test_regress/t/t_trace_ub_misaligned_address.py b/test_regress/t/t_trace_ub_misaligned_address.py new file mode 100755 index 000000000..b86a92b34 --- /dev/null +++ b/test_regress/t/t_trace_ub_misaligned_address.py @@ -0,0 +1,27 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_trace_ub_misaligned_address.v" + +test.compile(verilator_flags2=[ + "--binary --trace", "-CFLAGS -fsanitize=address,undefined", + "-LDFLAGS -fsanitize=address,undefined" +]) + +test.execute( + # Some GCC versions hit an address-sanitizer bug otherwise) + aslr_off=True) + +# Make sure that there are no additional messages (such as runtime messages +# regarding undefined behavior).test.files_identical(test.obj_dir + "/vlt_sim.log", test.golden_filename, "logfile") + +test.passes() diff --git a/test_regress/t/t_trace_wide_struct.pl b/test_regress/t/t_trace_wide_struct.pl deleted file mode 100755 index 7914ddcc8..000000000 --- a/test_regress/t/t_trace_wide_struct.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile (verilator_flags2 => ['--trace --trace-structs'],); - -ok(1); -1; diff --git a/test_regress/t/t_trace_wide_struct.py b/test_regress/t/t_trace_wide_struct.py new file mode 100755 index 000000000..89f022528 --- /dev/null +++ b/test_regress/t/t_trace_wide_struct.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--trace --trace-structs']) + +test.passes() diff --git a/test_regress/t/t_tri_and_eqcase.pl b/test_regress/t/t_tri_and_eqcase.pl deleted file mode 100755 index 48bf31461..000000000 --- a/test_regress/t/t_tri_and_eqcase.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_and_eqcase.py b/test_regress/t/t_tri_and_eqcase.py new file mode 100755 index 000000000..6585af685 --- /dev/null +++ b/test_regress/t/t_tri_and_eqcase.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_tri_array.pl b/test_regress/t/t_tri_array.pl deleted file mode 100755 index bf01b0247..000000000 --- a/test_regress/t/t_tri_array.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator_st => 1); - -compile( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -execute( - ) if !$Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_tri_array.py b/test_regress/t/t_tri_array.py new file mode 100755 index 000000000..d0b1f865e --- /dev/null +++ b/test_regress/t/t_tri_array.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') + +test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) + +if not test.vlt_all: + test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_array_bufif.pl b/test_regress/t/t_tri_array_bufif.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_tri_array_bufif.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_array_bufif.py b/test_regress/t/t_tri_array_bufif.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_tri_array_bufif.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_array_pull.pl b/test_regress/t/t_tri_array_pull.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_tri_array_pull.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_array_pull.py b/test_regress/t/t_tri_array_pull.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_tri_array_pull.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_compass_bad.pl b/test_regress/t/t_tri_compass_bad.pl deleted file mode 100755 index da8086e04..000000000 --- a/test_regress/t/t_tri_compass_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - expect_filename => $Self->{golden_filename}, - fails => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_compass_bad.py b/test_regress/t/t_tri_compass_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_tri_compass_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_tri_cond_eqcase_with_1.pl b/test_regress/t/t_tri_cond_eqcase_with_1.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_tri_cond_eqcase_with_1.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_cond_eqcase_with_1.py b/test_regress/t/t_tri_cond_eqcase_with_1.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_tri_cond_eqcase_with_1.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_dangle.pl b/test_regress/t/t_tri_dangle.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_tri_dangle.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_dangle.py b/test_regress/t/t_tri_dangle.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_tri_dangle.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_eqcase.pl b/test_regress/t/t_tri_eqcase.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_tri_eqcase.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_eqcase.py b/test_regress/t/t_tri_eqcase.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_tri_eqcase.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_eqcase_input.pl b/test_regress/t/t_tri_eqcase_input.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_tri_eqcase_input.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_eqcase_input.py b/test_regress/t/t_tri_eqcase_input.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_tri_eqcase_input.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_gate_bufif0.pl b/test_regress/t/t_tri_gate_bufif0.pl deleted file mode 100755 index a40314f28..000000000 --- a/test_regress/t/t_tri_gate_bufif0.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_tri_gate.v"); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ['+define+T_BUFIF0',], - make_flags => 'CPPFLAGS_ADD=-DT_BUFIF0', - verilator_flags2 => ["--exe $Self->{t_dir}/t_tri_gate.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_gate_bufif0.py b/test_regress/t/t_tri_gate_bufif0.py new file mode 100755 index 000000000..4634d4e76 --- /dev/null +++ b/test_regress/t/t_tri_gate_bufif0.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_tri_gate.cpp" +test.top_filename = "t/t_tri_gate.v" + +test.compile(make_top_shell=False, + make_main=False, + v_flags2=['+define+T_BUFIF0'], + make_flags=['CPPFLAGS_ADD=-DT_BUFIF0'], + verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_gate_bufif0_pins_inout.pl b/test_regress/t/t_tri_gate_bufif0_pins_inout.pl deleted file mode 100755 index 0846af5e7..000000000 --- a/test_regress/t/t_tri_gate_bufif0_pins_inout.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_tri_gate.v"); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ['+define+T_BUFIF0',], - make_flags => 'CPPFLAGS_ADD=-DT_BUFIF0', - verilator_flags2 => ["--exe --pins-inout-enables $Self->{t_dir}/t_tri_gate.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_gate_bufif0_pins_inout.py b/test_regress/t/t_tri_gate_bufif0_pins_inout.py new file mode 100755 index 000000000..76fc851c5 --- /dev/null +++ b/test_regress/t/t_tri_gate_bufif0_pins_inout.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_tri_gate.cpp" +test.top_filename = "t/t_tri_gate.v" + +test.compile(make_top_shell=False, + make_main=False, + v_flags2=['+define+T_BUFIF0'], + make_flags=['CPPFLAGS_ADD=-DT_BUFIF0'], + verilator_flags2=["--exe --pins-inout-enables", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_gate_bufif1.pl b/test_regress/t/t_tri_gate_bufif1.pl deleted file mode 100755 index a8f27211f..000000000 --- a/test_regress/t/t_tri_gate_bufif1.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_tri_gate.v"); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ['+define+T_BUFIF1',], - make_flags => 'CPPFLAGS_ADD=-DT_BUFIF1', - verilator_flags2 => ["--exe $Self->{t_dir}/t_tri_gate.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_gate_bufif1.py b/test_regress/t/t_tri_gate_bufif1.py new file mode 100755 index 000000000..1a14c142e --- /dev/null +++ b/test_regress/t/t_tri_gate_bufif1.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_tri_gate.cpp" +test.top_filename = "t/t_tri_gate.v" + +test.compile(make_top_shell=False, + make_main=False, + v_flags2=['+define+T_BUFIF1'], + make_flags=['CPPFLAGS_ADD=-DT_BUFIF1'], + verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_gate_bufif1_pins_inout.pl b/test_regress/t/t_tri_gate_bufif1_pins_inout.pl deleted file mode 100755 index 955df3c0b..000000000 --- a/test_regress/t/t_tri_gate_bufif1_pins_inout.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } - -scenarios(vlt_all => 1); - -top_filename("t/t_tri_gate.v"); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ['+define+T_BUFIF1',], - make_flags => 'CPPFLAGS_ADD=-DT_BUFIF1', - verilator_flags2 => ["--exe --pins-inout-enables $Self->{t_dir}/t_tri_gate.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_gate_bufif1_pins_inout.py b/test_regress/t/t_tri_gate_bufif1_pins_inout.py new file mode 100755 index 000000000..6a4dce294 --- /dev/null +++ b/test_regress/t/t_tri_gate_bufif1_pins_inout.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_tri_gate.cpp" +test.top_filename = "t/t_tri_gate.v" + +test.compile(make_top_shell=False, + make_main=False, + v_flags2=['+define+T_BUFIF1'], + make_flags=['CPPFLAGS_ADD=-DT_BUFIF1'], + verilator_flags2=["--exe --pins-inout-enables", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_gate_cond.pl b/test_regress/t/t_tri_gate_cond.pl deleted file mode 100755 index 6096e5a8f..000000000 --- a/test_regress/t/t_tri_gate_cond.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_tri_gate.v"); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ['+define+T_COND',], - make_flags => 'CPPFLAGS_ADD=-DT_COND', - verilator_flags2 => ["--exe $Self->{t_dir}/t_tri_gate.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_gate_cond.py b/test_regress/t/t_tri_gate_cond.py new file mode 100755 index 000000000..c4b5851c4 --- /dev/null +++ b/test_regress/t/t_tri_gate_cond.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_tri_gate.cpp" +test.top_filename = "t/t_tri_gate.v" + +test.compile(make_top_shell=False, + make_main=False, + v_flags2=['+define+T_COND'], + make_flags=['CPPFLAGS_ADD=-DT_COND'], + verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_gate_cond_pins_inout.pl b/test_regress/t/t_tri_gate_cond_pins_inout.pl deleted file mode 100755 index b0750d2e0..000000000 --- a/test_regress/t/t_tri_gate_cond_pins_inout.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_tri_gate.v"); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ['+define+T_COND',], - make_flags => 'CPPFLAGS_ADD=-DT_COND', - verilator_flags2 => ["--exe --pins-inout-enables $Self->{t_dir}/t_tri_gate.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_gate_cond_pins_inout.py b/test_regress/t/t_tri_gate_cond_pins_inout.py new file mode 100755 index 000000000..20ffe23ea --- /dev/null +++ b/test_regress/t/t_tri_gate_cond_pins_inout.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_tri_gate.cpp" +test.top_filename = "t/t_tri_gate.v" + +test.compile(make_top_shell=False, + make_main=False, + v_flags2=['+define+T_COND'], + make_flags=['CPPFLAGS_ADD=-DT_COND'], + verilator_flags2=["--exe --pins-inout-enables", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_gate_nmos.pl b/test_regress/t/t_tri_gate_nmos.pl deleted file mode 100755 index dda094050..000000000 --- a/test_regress/t/t_tri_gate_nmos.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_tri_gate.v"); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ['+define+T_NMOS',], - make_flags => 'CPPFLAGS_ADD=-DT_NMOS', - verilator_flags2 => ["--exe $Self->{t_dir}/t_tri_gate.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_gate_nmos.py b/test_regress/t/t_tri_gate_nmos.py new file mode 100755 index 000000000..8b8c924f2 --- /dev/null +++ b/test_regress/t/t_tri_gate_nmos.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_tri_gate.cpp" +test.top_filename = "t/t_tri_gate.v" + +test.compile(make_top_shell=False, + make_main=False, + v_flags2=['+define+T_NMOS'], + make_flags=['CPPFLAGS_ADD=-DT_NMOS'], + verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_gate_nmos_pins_inout.pl b/test_regress/t/t_tri_gate_nmos_pins_inout.pl deleted file mode 100755 index ad140f182..000000000 --- a/test_regress/t/t_tri_gate_nmos_pins_inout.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_tri_gate.v"); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ['+define+T_NMOS',], - make_flags => 'CPPFLAGS_ADD=-DT_NMOS', - verilator_flags2 => ["--exe --pins-inout-enables $Self->{t_dir}/t_tri_gate.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_gate_nmos_pins_inout.py b/test_regress/t/t_tri_gate_nmos_pins_inout.py new file mode 100755 index 000000000..fc4bbaa5c --- /dev/null +++ b/test_regress/t/t_tri_gate_nmos_pins_inout.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_tri_gate.cpp" +test.top_filename = "t/t_tri_gate.v" + +test.compile(make_top_shell=False, + make_main=False, + v_flags2=['+define+T_NMOS'], + make_flags=['CPPFLAGS_ADD=-DT_NMOS'], + verilator_flags2=["--exe --pins-inout-enables", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_gate_notif0.pl b/test_regress/t/t_tri_gate_notif0.pl deleted file mode 100755 index 357c22042..000000000 --- a/test_regress/t/t_tri_gate_notif0.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_tri_gate.v"); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ['+define+T_NOTIF0',], - make_flags => 'CPPFLAGS_ADD=-DT_NOTIF0', - verilator_flags2 => ["--exe $Self->{t_dir}/t_tri_gate.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_gate_notif0.py b/test_regress/t/t_tri_gate_notif0.py new file mode 100755 index 000000000..a9dd77046 --- /dev/null +++ b/test_regress/t/t_tri_gate_notif0.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_tri_gate.cpp" +test.top_filename = "t/t_tri_gate.v" + +test.compile(make_top_shell=False, + make_main=False, + v_flags2=['+define+T_NOTIF0'], + make_flags=['CPPFLAGS_ADD=-DT_NOTIF0'], + verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_gate_notif0_pins_inout.pl b/test_regress/t/t_tri_gate_notif0_pins_inout.pl deleted file mode 100755 index e9370a94d..000000000 --- a/test_regress/t/t_tri_gate_notif0_pins_inout.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_tri_gate.v"); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ['+define+T_NOTIF0',], - make_flags => 'CPPFLAGS_ADD=-DT_NOTIF0', - verilator_flags2 => ["--exe --pins-inout-enables $Self->{t_dir}/t_tri_gate.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_gate_notif0_pins_inout.py b/test_regress/t/t_tri_gate_notif0_pins_inout.py new file mode 100755 index 000000000..797e8d163 --- /dev/null +++ b/test_regress/t/t_tri_gate_notif0_pins_inout.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_tri_gate.cpp" +test.top_filename = "t/t_tri_gate.v" + +test.compile(make_top_shell=False, + make_main=False, + v_flags2=['+define+T_NOTIF0'], + make_flags=['CPPFLAGS_ADD=-DT_NOTIF0'], + verilator_flags2=["--exe --pins-inout-enables", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_gate_notif1.pl b/test_regress/t/t_tri_gate_notif1.pl deleted file mode 100755 index 9d0cb50d1..000000000 --- a/test_regress/t/t_tri_gate_notif1.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_tri_gate.v"); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ['+define+T_NOTIF1',], - make_flags => 'CPPFLAGS_ADD=-DT_NOTIF1', - verilator_flags2 => ["--exe $Self->{t_dir}/t_tri_gate.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_gate_notif1.py b/test_regress/t/t_tri_gate_notif1.py new file mode 100755 index 000000000..09350a74e --- /dev/null +++ b/test_regress/t/t_tri_gate_notif1.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_tri_gate.cpp" +test.top_filename = "t/t_tri_gate.v" + +test.compile(make_top_shell=False, + make_main=False, + v_flags2=['+define+T_NOTIF1'], + make_flags=['CPPFLAGS_ADD=-DT_NOTIF1'], + verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_gate_notif1_pins_inout.pl b/test_regress/t/t_tri_gate_notif1_pins_inout.pl deleted file mode 100755 index cb649cb06..000000000 --- a/test_regress/t/t_tri_gate_notif1_pins_inout.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_tri_gate.v"); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ['+define+T_NOTIF1',], - make_flags => 'CPPFLAGS_ADD=-DT_NOTIF1', - verilator_flags2 => ["--exe --pins-inout-enables $Self->{t_dir}/t_tri_gate.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_gate_notif1_pins_inout.py b/test_regress/t/t_tri_gate_notif1_pins_inout.py new file mode 100755 index 000000000..c03f247c7 --- /dev/null +++ b/test_regress/t/t_tri_gate_notif1_pins_inout.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_tri_gate.cpp" +test.top_filename = "t/t_tri_gate.v" + +test.compile(make_top_shell=False, + make_main=False, + v_flags2=['+define+T_NOTIF1'], + make_flags=['CPPFLAGS_ADD=-DT_NOTIF1'], + verilator_flags2=["--exe --pins-inout-enables", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_gate_pmos.pl b/test_regress/t/t_tri_gate_pmos.pl deleted file mode 100755 index 768abc722..000000000 --- a/test_regress/t/t_tri_gate_pmos.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_tri_gate.v"); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ['+define+T_PMOS',], - make_flags => 'CPPFLAGS_ADD=-DT_PMOS', - verilator_flags2 => ["--exe $Self->{t_dir}/t_tri_gate.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_gate_pmos.py b/test_regress/t/t_tri_gate_pmos.py new file mode 100755 index 000000000..9f23ab621 --- /dev/null +++ b/test_regress/t/t_tri_gate_pmos.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_tri_gate.cpp" +test.top_filename = "t/t_tri_gate.v" + +test.compile(make_top_shell=False, + make_main=False, + v_flags2=['+define+T_PMOS'], + make_flags=['CPPFLAGS_ADD=-DT_PMOS'], + verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_gate_pmos_pins_inout.pl b/test_regress/t/t_tri_gate_pmos_pins_inout.pl deleted file mode 100755 index 8a38ce4eb..000000000 --- a/test_regress/t/t_tri_gate_pmos_pins_inout.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_tri_gate.v"); - -compile( - make_top_shell => 0, - make_main => 0, - v_flags2 => ['+define+T_PMOS',], - make_flags => 'CPPFLAGS_ADD=-DT_PMOS', - verilator_flags2 => ["--exe --pins-inout-enables $Self->{t_dir}/t_tri_gate.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_gate_pmos_pins_inout.py b/test_regress/t/t_tri_gate_pmos_pins_inout.py new file mode 100755 index 000000000..c9177fd57 --- /dev/null +++ b/test_regress/t/t_tri_gate_pmos_pins_inout.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_tri_gate.cpp" +test.top_filename = "t/t_tri_gate.v" + +test.compile(make_top_shell=False, + make_main=False, + v_flags2=['+define+T_PMOS'], + make_flags=['CPPFLAGS_ADD=-DT_PMOS'], + verilator_flags2=["--exe --pins-inout-enables", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_gen.pl b/test_regress/t/t_tri_gen.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_tri_gen.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_gen.py b/test_regress/t/t_tri_gen.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_tri_gen.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_graph.pl b/test_regress/t/t_tri_graph.pl deleted file mode 100755 index 079bb20a8..000000000 --- a/test_regress/t/t_tri_graph.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -# Compile only test -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_graph.py b/test_regress/t/t_tri_graph.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_tri_graph.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_tri_ifbegin.pl b/test_regress/t/t_tri_ifbegin.pl deleted file mode 100755 index dd4fed003..000000000 --- a/test_regress/t/t_tri_ifbegin.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -# No execution - -ok(1); -1; diff --git a/test_regress/t/t_tri_ifbegin.py b/test_regress/t/t_tri_ifbegin.py new file mode 100755 index 000000000..3aafd524c --- /dev/null +++ b/test_regress/t/t_tri_ifbegin.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +#test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_inout.pl b/test_regress/t/t_tri_inout.pl deleted file mode 100755 index 68460aeed..000000000 --- a/test_regress/t/t_tri_inout.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_inout.py b/test_regress/t/t_tri_inout.py new file mode 100755 index 000000000..273ccc85c --- /dev/null +++ b/test_regress/t/t_tri_inout.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_inout2.pl b/test_regress/t/t_tri_inout2.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_tri_inout2.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_inout2.py b/test_regress/t/t_tri_inout2.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_tri_inout2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_inout_pins_inout.pl b/test_regress/t/t_tri_inout_pins_inout.pl deleted file mode 100755 index 387f0b610..000000000 --- a/test_regress/t/t_tri_inout_pins_inout.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -top_filename("t/t_tri_inout.v"); - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe --pins-inout-enables $Self->{t_dir}/t_tri_inout.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_inout_pins_inout.py b/test_regress/t/t_tri_inout_pins_inout.py new file mode 100755 index 000000000..1d13da5b0 --- /dev/null +++ b/test_regress/t/t_tri_inout_pins_inout.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +test.top_filename = "t/t_tri_inout.v" + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_tri_inout.cpp" + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--exe --pins-inout-enables", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_inz.pl b/test_regress/t/t_tri_inz.pl deleted file mode 100755 index 1d6d3c6be..000000000 --- a/test_regress/t/t_tri_inz.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2018 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_inz.py b/test_regress/t/t_tri_inz.py new file mode 100755 index 000000000..273ccc85c --- /dev/null +++ b/test_regress/t/t_tri_inz.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_no_top.pl b/test_regress/t/t_tri_no_top.pl deleted file mode 100755 index e7806589d..000000000 --- a/test_regress/t/t_tri_no_top.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe --pins-inout-enables --timing --main", "$Self->{t_dir}/t_tri_top_en_out.v"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_no_top.py b/test_regress/t/t_tri_no_top.py new file mode 100755 index 000000000..22d83a776 --- /dev/null +++ b/test_regress/t/t_tri_no_top.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=[ + "--exe --pins-inout-enables --timing --main", test.t_dir + "/t_tri_top_en_out.v" + ]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_public.pl b/test_regress/t/t_tri_public.pl deleted file mode 100755 index 079bb20a8..000000000 --- a/test_regress/t/t_tri_public.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -# Compile only test -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_public.py b/test_regress/t/t_tri_public.py new file mode 100755 index 000000000..c23e16d62 --- /dev/null +++ b/test_regress/t/t_tri_public.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +# Compile only test + +test.passes() diff --git a/test_regress/t/t_tri_pull01.pl b/test_regress/t/t_tri_pull01.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_tri_pull01.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_pull01.py b/test_regress/t/t_tri_pull01.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_tri_pull01.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_pull2_bad.pl b/test_regress/t/t_tri_pull2_bad.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_tri_pull2_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_pull2_bad.py b/test_regress/t/t_tri_pull2_bad.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_tri_pull2_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_tri_pull_bad.pl b/test_regress/t/t_tri_pull_bad.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_tri_pull_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_pull_bad.py b/test_regress/t/t_tri_pull_bad.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_tri_pull_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_tri_pull_implicit.pl b/test_regress/t/t_tri_pull_implicit.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_tri_pull_implicit.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_pull_implicit.py b/test_regress/t/t_tri_pull_implicit.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_tri_pull_implicit.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_pullup.pl b/test_regress/t/t_tri_pullup.pl deleted file mode 100755 index 68460aeed..000000000 --- a/test_regress/t/t_tri_pullup.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_pullup.py b/test_regress/t/t_tri_pullup.py new file mode 100755 index 000000000..273ccc85c --- /dev/null +++ b/test_regress/t/t_tri_pullup.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_pullup_pins_inout.pl b/test_regress/t/t_tri_pullup_pins_inout.pl deleted file mode 100755 index 3ec289738..000000000 --- a/test_regress/t/t_tri_pullup_pins_inout.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_tri_pullup.v"); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe --pins-inout-enables $Self->{t_dir}/t_tri_pullup.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_pullup_pins_inout.py b/test_regress/t/t_tri_pullup_pins_inout.py new file mode 100755 index 000000000..fcfabc5fe --- /dev/null +++ b/test_regress/t/t_tri_pullup_pins_inout.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_tri_pullup.cpp" +test.top_filename = "t/t_tri_pullup.v" + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--exe --pins-inout-enables", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_pullvec_bad.pl b/test_regress/t/t_tri_pullvec_bad.pl deleted file mode 100755 index 48bf31461..000000000 --- a/test_regress/t/t_tri_pullvec_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_pullvec_bad.py b/test_regress/t/t_tri_pullvec_bad.py new file mode 100755 index 000000000..6585af685 --- /dev/null +++ b/test_regress/t/t_tri_pullvec_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_tri_select.pl b/test_regress/t/t_tri_select.pl deleted file mode 100755 index 68460aeed..000000000 --- a/test_regress/t/t_tri_select.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_select.py b/test_regress/t/t_tri_select.py new file mode 100755 index 000000000..273ccc85c --- /dev/null +++ b/test_regress/t/t_tri_select.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_select_eqcase.pl b/test_regress/t/t_tri_select_eqcase.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_tri_select_eqcase.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_select_eqcase.py b/test_regress/t/t_tri_select_eqcase.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_tri_select_eqcase.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_select_pins_inout.pl b/test_regress/t/t_tri_select_pins_inout.pl deleted file mode 100755 index 4739b373c..000000000 --- a/test_regress/t/t_tri_select_pins_inout.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_tri_select.v"); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe --pins-inout-enables $Self->{t_dir}/t_tri_select.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_select_pins_inout.py b/test_regress/t/t_tri_select_pins_inout.py new file mode 100755 index 000000000..da7c9bb9c --- /dev/null +++ b/test_regress/t/t_tri_select_pins_inout.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_tri_select.cpp" +test.top_filename = "t/t_tri_select.v" + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--exe --pins-inout-enables", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_select_unsized.pl b/test_regress/t/t_tri_select_unsized.pl deleted file mode 100755 index 11a648d2d..000000000 --- a/test_regress/t/t_tri_select_unsized.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -# Compile only test -compile( - verilator_flags2 => ["-Wno-WIDTH"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_select_unsized.py b/test_regress/t/t_tri_select_unsized.py new file mode 100755 index 000000000..55e4826e3 --- /dev/null +++ b/test_regress/t/t_tri_select_unsized.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["-Wno-WIDTH"]) + +test.passes() diff --git a/test_regress/t/t_tri_struct.pl b/test_regress/t/t_tri_struct.pl deleted file mode 100755 index d0e88ac55..000000000 --- a/test_regress/t/t_tri_struct.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator_st => 1); - -compile( - verilator_flags2 => ['--exe --main --timing'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_struct.py b/test_regress/t/t_tri_struct.py new file mode 100755 index 000000000..2ffd2b3e0 --- /dev/null +++ b/test_regress/t/t_tri_struct.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') + +test.compile(verilator_flags2=['--exe --main --timing']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_struct_packed.pl b/test_regress/t/t_tri_struct_packed.pl deleted file mode 100755 index 680393eab..000000000 --- a/test_regress/t/t_tri_struct_packed.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--exe --main --timing'], - ); - -execute( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_struct_packed.py b/test_regress/t/t_tri_struct_packed.py new file mode 100755 index 000000000..b5b4b8643 --- /dev/null +++ b/test_regress/t/t_tri_struct_packed.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--exe --main --timing']) + +test.execute(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_tri_struct_pins_inout.pl b/test_regress/t/t_tri_struct_pins_inout.pl deleted file mode 100755 index 02c8a730d..000000000 --- a/test_regress/t/t_tri_struct_pins_inout.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator_st => 1); - -top_filename("t/t_tri_struct.v"); - -compile( - verilator_flags2 => ['--exe --pins-inout-enables --main --timing'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_struct_pins_inout.py b/test_regress/t/t_tri_struct_pins_inout.py new file mode 100755 index 000000000..3bcf9231a --- /dev/null +++ b/test_regress/t/t_tri_struct_pins_inout.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.top_filename = "t/t_tri_struct.v" + +test.compile(verilator_flags2=['--exe --pins-inout-enables --main --timing']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_top_en_out.pl b/test_regress/t/t_tri_top_en_out.pl deleted file mode 100755 index 647be6b06..000000000 --- a/test_regress/t/t_tri_top_en_out.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe --timing --pins-inout-enables", "$Self->{t_dir}/$Self->{name}.cpp"], -); - -execute( -); -ok(1); -1; diff --git a/test_regress/t/t_tri_top_en_out.py b/test_regress/t/t_tri_top_en_out.py new file mode 100755 index 000000000..da6e614c5 --- /dev/null +++ b/test_regress/t/t_tri_top_en_out.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--exe --timing --pins-inout-enables", test.pli_filename]) + +test.execute() +test.passes() diff --git a/test_regress/t/t_tri_top_en_out_bad.pl b/test_regress/t/t_tri_top_en_out_bad.pl deleted file mode 100755 index 54537bf8c..000000000 --- a/test_regress/t/t_tri_top_en_out_bad.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - make_top_shell => 0, - make_main => 1, - verilator_make_gmake => 1, - verilator_flags2 => ["--exe --pins-inout-enables --no-timing -Wno-STMTDLY"] -); -file_grep_not("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/internal_sub_io__out/); -file_grep_not("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/internal_sub_io__en/); - -ok(1); -1; diff --git a/test_regress/t/t_tri_top_en_out_bad.py b/test_regress/t/t_tri_top_en_out_bad.py new file mode 100755 index 000000000..6b0e5e228 --- /dev/null +++ b/test_regress/t/t_tri_top_en_out_bad.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(make_top_shell=False, + make_main=1, + verilator_make_gmake=True, + verilator_flags2=["--exe --pins-inout-enables --no-timing -Wno-STMTDLY"]) + +test.file_grep_not(test.obj_dir + "/" + test.vm_prefix + ".h", r'internal_sub_io__out') +test.file_grep_not(test.obj_dir + "/" + test.vm_prefix + ".h", r'internal_sub_io__en') + +test.passes() diff --git a/test_regress/t/t_tri_unconn.pl b/test_regress/t/t_tri_unconn.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_tri_unconn.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_unconn.py b/test_regress/t/t_tri_unconn.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_tri_unconn.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_various.pl b/test_regress/t/t_tri_various.pl deleted file mode 100755 index 72847408e..000000000 --- a/test_regress/t/t_tri_various.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_tri_various.py b/test_regress/t/t_tri_various.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_tri_various.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_type.pl b/test_regress/t/t_type.pl deleted file mode 100755 index fdc76316a..000000000 --- a/test_regress/t/t_type.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_type.py b/test_regress/t/t_type.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_type.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_type_compare.pl b/test_regress/t/t_type_compare.pl deleted file mode 100755 index fdc76316a..000000000 --- a/test_regress/t/t_type_compare.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_type_compare.py b/test_regress/t/t_type_compare.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_type_compare.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_type_compare_bad.pl b/test_regress/t/t_type_compare_bad.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_type_compare_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_type_compare_bad.py b/test_regress/t/t_type_compare_bad.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_type_compare_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_type_match.pl b/test_regress/t/t_type_match.pl deleted file mode 100755 index b528adf4d..000000000 --- a/test_regress/t/t_type_match.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["-Wno-UNOPTFLAT"] - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_type_match.py b/test_regress/t/t_type_match.py new file mode 100755 index 000000000..c37bc018e --- /dev/null +++ b/test_regress/t/t_type_match.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["-Wno-UNOPTFLAT"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_type_param.pl b/test_regress/t/t_type_param.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_type_param.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_type_param.py b/test_regress/t/t_type_param.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_type_param.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_type_param_circ_bad.pl b/test_regress/t/t_type_param_circ_bad.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_type_param_circ_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_type_param_circ_bad.py b/test_regress/t/t_type_param_circ_bad.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_type_param_circ_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_type_param_collision.pl b/test_regress/t/t_type_param_collision.pl deleted file mode 100755 index 43db7290a..000000000 --- a/test_regress/t/t_type_param_collision.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Todd Strader. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_type_param.v"); - -compile( - verilator_flags2 => ["--debug-collision"] - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_type_param_collision.py b/test_regress/t/t_type_param_collision.py new file mode 100755 index 000000000..a4337c4ed --- /dev/null +++ b/test_regress/t/t_type_param_collision.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_type_param.v" + +test.compile(verilator_flags2=["--debug-collision"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_typedef.pl b/test_regress/t/t_typedef.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_typedef.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_typedef.py b/test_regress/t/t_typedef.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_typedef.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_typedef_array.pl b/test_regress/t/t_typedef_array.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_typedef_array.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_typedef_array.py b/test_regress/t/t_typedef_array.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_typedef_array.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_typedef_circ_bad.pl b/test_regress/t/t_typedef_circ_bad.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_typedef_circ_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_typedef_circ_bad.py b/test_regress/t/t_typedef_circ_bad.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_typedef_circ_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_typedef_consistency_0.pl b/test_regress/t/t_typedef_consistency_0.pl deleted file mode 100755 index 3708008f8..000000000 --- a/test_regress/t/t_typedef_consistency_0.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_typedef_consistency_0.py b/test_regress/t/t_typedef_consistency_0.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_typedef_consistency_0.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_typedef_package.pl b/test_regress/t/t_typedef_package.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_typedef_package.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_typedef_package.py b/test_regress/t/t_typedef_package.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_typedef_package.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_typedef_param.pl b/test_regress/t/t_typedef_param.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_typedef_param.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_typedef_param.py b/test_regress/t/t_typedef_param.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_typedef_param.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_typedef_port.pl b/test_regress/t/t_typedef_port.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_typedef_port.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_typedef_port.py b/test_regress/t/t_typedef_port.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_typedef_port.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_typedef_signed.pl b/test_regress/t/t_typedef_signed.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_typedef_signed.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_typedef_signed.py b/test_regress/t/t_typedef_signed.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_typedef_signed.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_typedef_unused_bad.pl b/test_regress/t/t_typedef_unused_bad.pl deleted file mode 100755 index eb5a450f9..000000000 --- a/test_regress/t/t_typedef_unused_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--Wpedantic"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_typedef_unused_bad.py b/test_regress/t/t_typedef_unused_bad.py new file mode 100755 index 000000000..285f30e23 --- /dev/null +++ b/test_regress/t/t_typedef_unused_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--Wpedantic"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_typename.pl b/test_regress/t/t_typename.pl deleted file mode 100755 index ea22aab6b..000000000 --- a/test_regress/t/t_typename.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_typename.py b/test_regress/t/t_typename.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_typename.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_typename_min.pl b/test_regress/t/t_typename_min.pl deleted file mode 100755 index 3708008f8..000000000 --- a/test_regress/t/t_typename_min.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_typename_min.py b/test_regress/t/t_typename_min.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_typename_min.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_udp.pl b/test_regress/t/t_udp.pl deleted file mode 100755 index 4f8c004cf..000000000 --- a/test_regress/t/t_udp.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_udp.v"); - -compile( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -execute( - ) if !$Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_udp.py b/test_regress/t/t_udp.py new file mode 100755 index 000000000..204d47313 --- /dev/null +++ b/test_regress/t/t_udp.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_udp.v" + +test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) + +if not test.vlt_all: + test.execute() + +test.passes() diff --git a/test_regress/t/t_udp_bad.pl b/test_regress/t/t_udp_bad.pl deleted file mode 100755 index fc220ea47..000000000 --- a/test_regress/t/t_udp_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only --bbox-unsup"], - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_udp_bad.py b/test_regress/t/t_udp_bad.py new file mode 100755 index 000000000..a0f699e19 --- /dev/null +++ b/test_regress/t/t_udp_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only --bbox-unsup"], + fails=test.vlt_all, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_udp_lint.pl b/test_regress/t/t_udp_lint.pl deleted file mode 100755 index bce98ae52..000000000 --- a/test_regress/t/t_udp_lint.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_udp.v"); - -lint( - # Unsupported: UDP Tables - verilator_flags2 => ["--lint-only --bbox-unsup"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_udp_lint.py b/test_regress/t/t_udp_lint.py new file mode 100755 index 000000000..c817fb894 --- /dev/null +++ b/test_regress/t/t_udp_lint.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_udp.v" + +test.lint( + # Unsupported: UDP Tables + verilator_flags2=["--lint-only --bbox-unsup"]) + +test.passes() diff --git a/test_regress/t/t_udp_noname.pl b/test_regress/t/t_udp_noname.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_udp_noname.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_udp_noname.py b/test_regress/t/t_udp_noname.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_udp_noname.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_udp_param_bad.pl b/test_regress/t/t_udp_param_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_udp_param_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_udp_param_bad.py b/test_regress/t/t_udp_param_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_udp_param_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_udp_tableend_bad.pl b/test_regress/t/t_udp_tableend_bad.pl deleted file mode 100755 index fc220ea47..000000000 --- a/test_regress/t/t_udp_tableend_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only --bbox-unsup"], - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_udp_tableend_bad.py b/test_regress/t/t_udp_tableend_bad.py new file mode 100755 index 000000000..a0f699e19 --- /dev/null +++ b/test_regress/t/t_udp_tableend_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only --bbox-unsup"], + fails=test.vlt_all, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_udp_tableeof_bad.pl b/test_regress/t/t_udp_tableeof_bad.pl deleted file mode 100755 index 677258838..000000000 --- a/test_regress/t/t_udp_tableeof_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only --bbox-unsup"], - fails => $Self->{vlt_all}, - # Cannot use .out, get "$end" or "end of file" depending on bison version - expect => qr/EOF in 'table'/, - ); - -ok(1); -1; diff --git a/test_regress/t/t_udp_tableeof_bad.py b/test_regress/t/t_udp_tableeof_bad.py new file mode 100755 index 000000000..8b3cadf85 --- /dev/null +++ b/test_regress/t/t_udp_tableeof_bad.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint( + verilator_flags2=["--lint-only --bbox-unsup"], + fails=test.vlt_all, + # Cannot use .out, get "$end" or "end of file" depending on bison version + expect=r"EOF in 'table'") + +test.passes() diff --git a/test_regress/t/t_unbounded.pl b/test_regress/t/t_unbounded.pl deleted file mode 100755 index 72847408e..000000000 --- a/test_regress/t/t_unbounded.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_unbounded.py b/test_regress/t/t_unbounded.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_unbounded.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unbounded_bad.pl b/test_regress/t/t_unbounded_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_unbounded_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_unbounded_bad.py b/test_regress/t/t_unbounded_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_unbounded_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_unconnected.pl b/test_regress/t/t_unconnected.pl deleted file mode 100755 index fdc76316a..000000000 --- a/test_regress/t/t_unconnected.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_unconnected.py b/test_regress/t/t_unconnected.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_unconnected.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unconnected_bad.pl b/test_regress/t/t_unconnected_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_unconnected_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_unconnected_bad.py b/test_regress/t/t_unconnected_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_unconnected_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_unicode.pl b/test_regress/t/t_unicode.pl deleted file mode 100755 index a989452d5..000000000 --- a/test_regress/t/t_unicode.pl +++ /dev/null @@ -1,56 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -use IO::File; -#use Data::Dumper; -use strict; -use vars qw($Self); - -scenarios(simulator => 1); - -# Greek Hi -my $hi = "Greek: " . c(0xce) . c(0xb3) . c(0xce) . c(0xb5) . c(0xce) . c(0xb9) . c(0xce) . c(0xb1); -sub c { - # Appease https://www.virustotal.com NANO-Antivirus gives Trojan.Script.Vbs-heuristic flag - my $code = shift; - return eval("c" . "h" . "r(" . $code . ")"); -} - -sub gen { - my $filename = shift; - - my $fh = IO::File->new(">$filename"); - $fh->print(c(0xEF)); - $fh->print(c(0xBB)); - $fh->print(c(0xBF)); # BOM - $fh->print("// Bom\n"); - $fh->print("// Generated by t_unicode.pl\n"); - $fh->print("module t;\n"); - $fh->print(" // " . $hi . "\n"); - $fh->print(" initial begin\n"); - $fh->print(" \$write(\"" . $hi . "\\n\");\n"); - $fh->print(" \$write(\"*-* All Finished *-*\\n\");\n"); - $fh->print(" \$finish;\n"); - $fh->print(" end\n"); - $fh->print("endmodule\n"); -} - -top_filename("$Self->{obj_dir}/t_unicode.v"); - -gen($Self->{top_filename}); - -compile( - ); - -execute( - expect => $hi, - ); - -ok(1); -1; diff --git a/test_regress/t/t_unicode.py b/test_regress/t/t_unicode.py new file mode 100755 index 000000000..4af354bed --- /dev/null +++ b/test_regress/t/t_unicode.py @@ -0,0 +1,48 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = test.obj_dir + "/t_unicode.v" + + +def c(code): + # Appease https://www.virustotal.com NANO-Antivirus gives Trojan.Script.Vbs-heuristic flag + return eval("c" + "h" + "r(" + str(code) + ")") # pylint: disable=eval-used + + +# Greek Hi +hi = "Greek: " + c(0xce) + c(0xb3) + c(0xce) + c(0xb5) + c(0xce) + c(0xb9) + c(0xce) + c(0xb1) + + +def gen(filename): + with open(filename, 'w', encoding="latin-1") as fh: + fh.write(c(0xEF)) + fh.write(c(0xBB)) + fh.write(c(0xBF)) # BOM + fh.write("// Bom\n") + fh.write("// Generated by t_unicode.py\n") + fh.write("module t;\n") + fh.write(" // " + hi + "\n") + fh.write(" initial begin\n") + fh.write(" $write(\"" + hi + "\\n\");\n") + fh.write(" $write(\"*-* All Finished *-*\\n\");\n") + fh.write(" $finish;\n") + fh.write(" end\n") + fh.write("endmodule\n") + + +gen(test.top_filename) + +test.compile() + +test.execute(expect=hi) + +test.passes() diff --git a/test_regress/t/t_union_soft.pl b/test_regress/t/t_union_soft.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_union_soft.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_union_soft.py b/test_regress/t/t_union_soft.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_union_soft.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_union_unpacked.pl b/test_regress/t/t_union_unpacked.pl deleted file mode 100755 index e22e7f5d9..000000000 --- a/test_regress/t/t_union_unpacked.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_union_unpacked.py b/test_regress/t/t_union_unpacked.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_union_unpacked.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_uniqueif.pl b/test_regress/t/t_uniqueif.pl deleted file mode 100755 index 4a1de974b..000000000 --- a/test_regress/t/t_uniqueif.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--assert'], - nc_flags2 => ['+assert'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_uniqueif.py b/test_regress/t/t_uniqueif.py new file mode 100755 index 000000000..d97aaff01 --- /dev/null +++ b/test_regress/t/t_uniqueif.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--assert'], nc_flags2=['+assert']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_uniqueif_fail1.pl b/test_regress/t/t_uniqueif_fail1.pl deleted file mode 100755 index 0b8089a46..000000000 --- a/test_regress/t/t_uniqueif_fail1.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_uniqueif.v"); - -compile( - v_flags2 => ['+define+FAILING_ASSERTION1'], - verilator_flags2 => ['--assert'], - nc_flags2 => ['+assert'], - fails => $Self->{nc}, - ); - -execute( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_uniqueif_fail1.py b/test_regress/t/t_uniqueif_fail1.py new file mode 100755 index 000000000..8eeaeefee --- /dev/null +++ b/test_regress/t/t_uniqueif_fail1.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_uniqueif.v" + +test.compile(v_flags2=['+define+FAILING_ASSERTION1'], + verilator_flags2=['--assert'], + nc_flags2=['+assert'], + fails=test.nc) + +test.execute(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_uniqueif_fail2.pl b/test_regress/t/t_uniqueif_fail2.pl deleted file mode 100755 index 0f3406ade..000000000 --- a/test_regress/t/t_uniqueif_fail2.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_uniqueif.v"); - -compile( - v_flags2 => ['+define+FAILING_ASSERTION2'], - verilator_flags2 => ['--assert'], - nc_flags2 => ['+assert'], - fails => $Self->{nc}, - ); - -execute( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_uniqueif_fail2.py b/test_regress/t/t_uniqueif_fail2.py new file mode 100755 index 000000000..f94dedc48 --- /dev/null +++ b/test_regress/t/t_uniqueif_fail2.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_uniqueif.v" + +test.compile(v_flags2=['+define+FAILING_ASSERTION2'], + verilator_flags2=['--assert'], + nc_flags2=['+assert'], + fails=test.nc) + +test.execute(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_uniqueif_fail3.pl b/test_regress/t/t_uniqueif_fail3.pl deleted file mode 100755 index eb8c557ae..000000000 --- a/test_regress/t/t_uniqueif_fail3.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_uniqueif.v"); - -compile( - v_flags2 => ['+define+FAILING_ASSERTION3'], - verilator_flags2 => ['--assert'], - nc_flags2 => ['+assert'], - fails => $Self->{nc}, - ); - -execute( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_uniqueif_fail3.py b/test_regress/t/t_uniqueif_fail3.py new file mode 100755 index 000000000..e52b3e975 --- /dev/null +++ b/test_regress/t/t_uniqueif_fail3.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_uniqueif.v" + +test.compile(v_flags2=['+define+FAILING_ASSERTION3'], + verilator_flags2=['--assert'], + nc_flags2=['+assert'], + fails=test.nc) + +test.execute(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_uniqueif_fail4.pl b/test_regress/t/t_uniqueif_fail4.pl deleted file mode 100755 index 6f236b834..000000000 --- a/test_regress/t/t_uniqueif_fail4.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_uniqueif.v"); - -compile( - v_flags2 => ['+define+FAILING_ASSERTION4'], - verilator_flags2 => ['--assert'], - nc_flags2 => ['+assert'], - fails => $Self->{nc}, - ); - -execute( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_uniqueif_fail4.py b/test_regress/t/t_uniqueif_fail4.py new file mode 100755 index 000000000..ee0e4f768 --- /dev/null +++ b/test_regress/t/t_uniqueif_fail4.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_uniqueif.v" + +test.compile(v_flags2=['+define+FAILING_ASSERTION4'], + verilator_flags2=['--assert'], + nc_flags2=['+assert'], + fails=test.nc) + +test.execute(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_unopt_array.pl b/test_regress/t/t_unopt_array.pl deleted file mode 100755 index 9310b2337..000000000 --- a/test_regress/t/t_unopt_array.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["-Wno-UNOPTFLAT"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_unopt_array.py b/test_regress/t/t_unopt_array.py new file mode 100755 index 000000000..c37bc018e --- /dev/null +++ b/test_regress/t/t_unopt_array.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["-Wno-UNOPTFLAT"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unopt_array_csplit.pl b/test_regress/t/t_unopt_array_csplit.pl deleted file mode 100755 index 1f4b87ab9..000000000 --- a/test_regress/t/t_unopt_array_csplit.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_unopt_array.v"); -compile( - v_flags2 => ["--trace --output-split 1 --output-split-cfuncs 1 -Wno-UNOPTFLAT"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_unopt_array_csplit.py b/test_regress/t/t_unopt_array_csplit.py new file mode 100755 index 000000000..26fd8b3d1 --- /dev/null +++ b/test_regress/t/t_unopt_array_csplit.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_unopt_array.v" + +test.compile(v_flags2=["--trace --output-split 1 --output-split-cfuncs 1 -Wno-UNOPTFLAT"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unopt_array_typedef.pl b/test_regress/t/t_unopt_array_typedef.pl deleted file mode 100755 index e326b982d..000000000 --- a/test_regress/t/t_unopt_array_typedef.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_unopt_array.v"); - -compile( - verilator_flags2 => ["-Wno-UNOPTFLAT +define+USE_TYPEDEF"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_unopt_array_typedef.py b/test_regress/t/t_unopt_array_typedef.py new file mode 100755 index 000000000..809e92873 --- /dev/null +++ b/test_regress/t/t_unopt_array_typedef.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_unopt_array.v" + +test.compile(verilator_flags2=["-Wno-UNOPTFLAT +define+USE_TYPEDEF"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unopt_bound.pl b/test_regress/t/t_unopt_bound.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_unopt_bound.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_unopt_bound.py b/test_regress/t/t_unopt_bound.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_unopt_bound.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unopt_combo.pl b/test_regress/t/t_unopt_combo.pl deleted file mode 100755 index 9c3faf8e9..000000000 --- a/test_regress/t/t_unopt_combo.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ['+define+ALLOW_UNOPT'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_unopt_combo.py b/test_regress/t/t_unopt_combo.py new file mode 100755 index 000000000..64265ff66 --- /dev/null +++ b/test_regress/t/t_unopt_combo.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=['+define+ALLOW_UNOPT']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unopt_combo_bad.pl b/test_regress/t/t_unopt_combo_bad.pl deleted file mode 100755 index 5590ecd32..000000000 --- a/test_regress/t/t_unopt_combo_bad.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_unopt_combo.v"); - -compile( - v_flags2 => ['+define+ATTRIBUTES'], - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -execute( - ) if !$Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_unopt_combo_bad.py b/test_regress/t/t_unopt_combo_bad.py new file mode 100755 index 000000000..1592b6d48 --- /dev/null +++ b/test_regress/t/t_unopt_combo_bad.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_unopt_combo.v" + +test.compile(v_flags2=['+define+ATTRIBUTES'], + fails=test.vlt_all, + expect_filename=test.golden_filename) + +if not test.vlt_all: + test.execute() + +test.passes() diff --git a/test_regress/t/t_unopt_combo_isolate.pl b/test_regress/t/t_unopt_combo_isolate.pl deleted file mode 100755 index a06f61a8d..000000000 --- a/test_regress/t/t_unopt_combo_isolate.pl +++ /dev/null @@ -1,33 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_unopt_combo.v"); -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - verilator_flags2 => ["--no-json-edit-nums +define+ISOLATE --stats"], - ); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, isolate_assignments blocks\s+3/); - file_grep("$out_filename", qr/{"type":"VAR","name":"t.b",.*"loc":"e,23:[^"]*",.*"origName":"b",.*"attrIsolateAssign":true,.*"dtypeName":"logic"/); - file_grep("$out_filename", qr/{"type":"VAR","name":"__Vfunc_t.file.get_31_16__0__Vfuncout",.*"loc":"e,99:[^"]*",.*"origName":"__Vfunc_t__DOT__file__DOT__get_31_16__0__Vfuncout",.*"attrIsolateAssign":true,.*"dtypeName":"logic"/); - file_grep("$out_filename", qr/{"type":"VAR","name":"__Vfunc_t.file.get_31_16__0__t_crc",.*"loc":"e,100:[^"]*",.*"origName":"__Vfunc_t__DOT__file__DOT__get_31_16__0__t_crc",.*"attrIsolateAssign":true,.*"dtypeName":"logic"/); - file_grep("$out_filename", qr/{"type":"VAR","name":"__Vtask_t.file.set_b_d__1__t_crc",.*"loc":"e,112:[^"]*",.*"origName":"__Vtask_t__DOT__file__DOT__set_b_d__1__t_crc",.*"attrIsolateAssign":true,.*"dtypeName":"logic"/); - file_grep("$out_filename", qr/{"type":"VAR","name":"__Vtask_t.file.set_b_d__1__t_c",.*"loc":"e,113:[^"]*",.*"origName":"__Vtask_t__DOT__file__DOT__set_b_d__1__t_c",.*"attrIsolateAssign":true,.*"dtypeName":"logic"/); -} - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_unopt_combo_isolate.py b/test_regress/t/t_unopt_combo_isolate.py new file mode 100755 index 000000000..c7f9f968d --- /dev/null +++ b/test_regress/t/t_unopt_combo_isolate.py @@ -0,0 +1,44 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_unopt_combo.v" + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(verilator_flags2=["--no-json-edit-nums +define+ISOLATE --stats"]) + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, isolate_assignments blocks\s+3') + test.file_grep( + out_filename, + r'{"type":"VAR","name":"t.b",.*"loc":"e,23:[^"]*",.*"origName":"b",.*"attrIsolateAssign":true,.*"dtypeName":"logic"' + ) + test.file_grep( + out_filename, + r'{"type":"VAR","name":"__Vfunc_t.file.get_31_16__0__Vfuncout",.*"loc":"e,99:[^"]*",.*"origName":"__Vfunc_t__DOT__file__DOT__get_31_16__0__Vfuncout",.*"attrIsolateAssign":true,.*"dtypeName":"logic"' + ) + test.file_grep( + out_filename, + r'{"type":"VAR","name":"__Vfunc_t.file.get_31_16__0__t_crc",.*"loc":"e,100:[^"]*",.*"origName":"__Vfunc_t__DOT__file__DOT__get_31_16__0__t_crc",.*"attrIsolateAssign":true,.*"dtypeName":"logic"' + ) + test.file_grep( + out_filename, + r'{"type":"VAR","name":"__Vtask_t.file.set_b_d__1__t_crc",.*"loc":"e,112:[^"]*",.*"origName":"__Vtask_t__DOT__file__DOT__set_b_d__1__t_crc",.*"attrIsolateAssign":true,.*"dtypeName":"logic"' + ) + test.file_grep( + out_filename, + r'{"type":"VAR","name":"__Vtask_t.file.set_b_d__1__t_c",.*"loc":"e,113:[^"]*",.*"origName":"__Vtask_t__DOT__file__DOT__set_b_d__1__t_c",.*"attrIsolateAssign":true,.*"dtypeName":"logic"' + ) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unopt_combo_isolate_vlt.pl b/test_regress/t/t_unopt_combo_isolate_vlt.pl deleted file mode 100755 index cea7051ed..000000000 --- a/test_regress/t/t_unopt_combo_isolate_vlt.pl +++ /dev/null @@ -1,33 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_unopt_combo.v"); -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - verilator_flags2 => ["--no-json-edit-nums --stats $Self->{t_dir}/t_unopt_combo_isolate.vlt"], - ); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, isolate_assignments blocks\s+3/); - file_grep("$out_filename", qr/{"type":"VAR","name":"t.b",.*"loc":"f,23:[^"]*",.*"origName":"b",.*"attrIsolateAssign":true,.*"dtypeName":"logic"/); - file_grep("$out_filename", qr/{"type":"VAR","name":"__Vfunc_t.file.get_31_16__0__Vfuncout",.*"loc":"f,104:[^"]*",.*"origName":"__Vfunc_t__DOT__file__DOT__get_31_16__0__Vfuncout",.*"attrIsolateAssign":true,.*"dtypeName":"logic"/); - file_grep("$out_filename", qr/{"type":"VAR","name":"__Vfunc_t.file.get_31_16__0__t_crc",.*"loc":"f,105:[^"]*",.*"origName":"__Vfunc_t__DOT__file__DOT__get_31_16__0__t_crc",.*"attrIsolateAssign":true,.*"dtypeName":"logic"/); - file_grep("$out_filename", qr/{"type":"VAR","name":"__Vtask_t.file.set_b_d__1__t_crc",.*"loc":"f,115:[^"]*",.*"origName":"__Vtask_t__DOT__file__DOT__set_b_d__1__t_crc",.*"attrIsolateAssign":true,.*"dtypeName":"logic"/); - file_grep("$out_filename", qr/{"type":"VAR","name":"__Vtask_t.file.set_b_d__1__t_c",.*"loc":"f,116:[^"]*",.*"origName":"__Vtask_t__DOT__file__DOT__set_b_d__1__t_c",.*"attrIsolateAssign":true,.*"dtypeName":"logic"/); -} - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_unopt_combo_isolate_vlt.py b/test_regress/t/t_unopt_combo_isolate_vlt.py new file mode 100755 index 000000000..eab58591c --- /dev/null +++ b/test_regress/t/t_unopt_combo_isolate_vlt.py @@ -0,0 +1,45 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_unopt_combo.v" + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile( + verilator_flags2=["--no-json-edit-nums --stats", test.t_dir + "/t_unopt_combo_isolate.vlt"]) + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, isolate_assignments blocks\s+3') + test.file_grep( + out_filename, + r'{"type":"VAR","name":"t.b",.*"loc":"f,23:[^"]*",.*"origName":"b",.*"attrIsolateAssign":true,.*"dtypeName":"logic"' + ) + test.file_grep( + out_filename, + r'{"type":"VAR","name":"__Vfunc_t.file.get_31_16__0__Vfuncout",.*"loc":"f,104:[^"]*",.*"origName":"__Vfunc_t__DOT__file__DOT__get_31_16__0__Vfuncout",.*"attrIsolateAssign":true,.*"dtypeName":"logic"' + ) + test.file_grep( + out_filename, + r'{"type":"VAR","name":"__Vfunc_t.file.get_31_16__0__t_crc",.*"loc":"f,105:[^"]*",.*"origName":"__Vfunc_t__DOT__file__DOT__get_31_16__0__t_crc",.*"attrIsolateAssign":true,.*"dtypeName":"logic"' + ) + test.file_grep( + out_filename, + r'{"type":"VAR","name":"__Vtask_t.file.set_b_d__1__t_crc",.*"loc":"f,115:[^"]*",.*"origName":"__Vtask_t__DOT__file__DOT__set_b_d__1__t_crc",.*"attrIsolateAssign":true,.*"dtypeName":"logic"' + ) + test.file_grep( + out_filename, + r'{"type":"VAR","name":"__Vtask_t.file.set_b_d__1__t_c",.*"loc":"f,116:[^"]*",.*"origName":"__Vtask_t__DOT__file__DOT__set_b_d__1__t_c",.*"attrIsolateAssign":true,.*"dtypeName":"logic"' + ) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unopt_combo_waive.pl b/test_regress/t/t_unopt_combo_waive.pl deleted file mode 100755 index 99f3041e4..000000000 --- a/test_regress/t/t_unopt_combo_waive.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_unopt_combo.v"); - -compile( - v_flags2 => ['+define+ATTRIBUTES', "t/t_unopt_combo.vlt"], - # Passes, as we waived - ); - -ok(1); -1; diff --git a/test_regress/t/t_unopt_combo_waive.py b/test_regress/t/t_unopt_combo_waive.py new file mode 100755 index 000000000..508a70141 --- /dev/null +++ b/test_regress/t/t_unopt_combo_waive.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_unopt_combo.v" + +test.compile(v_flags2=['+define+ATTRIBUTES', "t/t_unopt_combo.vlt"], + # Passes, as we waived + ) + +test.passes() diff --git a/test_regress/t/t_unopt_converge_initial_run_bad.pl b/test_regress/t/t_unopt_converge_initial_run_bad.pl deleted file mode 100755 index 8825ddf1e..000000000 --- a/test_regress/t/t_unopt_converge_initial_run_bad.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2007 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_unopt_converge_initial.v"); - -compile( - v_flags2 => ['+define+ALLOW_UNOPT --output-split 0'], - ); - -execute( - fails => 1, - expect_filename => $Self->{golden_filename}, - ) if $Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_unopt_converge_initial_run_bad.py b/test_regress/t/t_unopt_converge_initial_run_bad.py new file mode 100755 index 000000000..ebc9607d7 --- /dev/null +++ b/test_regress/t/t_unopt_converge_initial_run_bad.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_unopt_converge_initial.v" + +test.compile(v_flags2=['+define+ALLOW_UNOPT --output-split 0']) + +if test.vlt_all: + test.execute(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_unopt_converge_ndbg_bad.pl b/test_regress/t/t_unopt_converge_ndbg_bad.pl deleted file mode 100755 index 929013cbc..000000000 --- a/test_regress/t/t_unopt_converge_ndbg_bad.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2007 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_unopt_converge.v"); - -compile( - v_flags2 => ['+define+ALLOW_UNOPT'], - make_flags => 'CPPFLAGS_ADD=-UVL_DEBUG', - ); - -execute( - fails => 1, - expect_filename => $Self->{golden_filename}, - ) if $Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_unopt_converge_ndbg_bad.py b/test_regress/t/t_unopt_converge_ndbg_bad.py new file mode 100755 index 000000000..65b34b60c --- /dev/null +++ b/test_regress/t/t_unopt_converge_ndbg_bad.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_unopt_converge.v" + +test.compile(v_flags2=['+define+ALLOW_UNOPT'], make_flags=['CPPFLAGS_ADD=-UVL_DEBUG']) + +if test.vlt_all: + test.execute(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_unopt_converge_print_bad.pl b/test_regress/t/t_unopt_converge_print_bad.pl deleted file mode 100755 index c20b4c98f..000000000 --- a/test_regress/t/t_unopt_converge_print_bad.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2007 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_unopt_converge.v"); -#$Self->{verilated_debug} = 1; - -compile( - v_flags2 => ['+define+ALLOW_UNOPT --output-split 0'], - make_flags => 'CPPFLAGS_ADD=-DVL_DEBUG', - ); - -execute( - fails => 1, - expect_filename => $Self->{golden_filename}, - ) if $Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_unopt_converge_print_bad.py b/test_regress/t/t_unopt_converge_print_bad.py new file mode 100755 index 000000000..d38fcc4a0 --- /dev/null +++ b/test_regress/t/t_unopt_converge_print_bad.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_unopt_converge.v" +#test.verilated_debug = 1 + +test.compile(v_flags2=['+define+ALLOW_UNOPT --output-split 0'], + make_flags=['CPPFLAGS_ADD=-DVL_DEBUG']) + +if test.vlt_all: + test.execute(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_unopt_converge_run_bad.pl b/test_regress/t/t_unopt_converge_run_bad.pl deleted file mode 100755 index ce55a1d72..000000000 --- a/test_regress/t/t_unopt_converge_run_bad.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2007 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_unopt_converge.v"); - -compile( - v_flags2 => ['+define+ALLOW_UNOPT --output-split 0'], - ); - -execute( - fails => 1, - expect_filename => $Self->{golden_filename}, - ) if $Self->{vlt_all}; - -ok(1); -1; diff --git a/test_regress/t/t_unopt_converge_run_bad.py b/test_regress/t/t_unopt_converge_run_bad.py new file mode 100755 index 000000000..846df0093 --- /dev/null +++ b/test_regress/t/t_unopt_converge_run_bad.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_unopt_converge.v" + +test.compile(v_flags2=['+define+ALLOW_UNOPT --output-split 0']) + +if test.vlt_all: + test.execute(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_unopt_converge_unopt_bad.pl b/test_regress/t/t_unopt_converge_unopt_bad.pl deleted file mode 100755 index cd6d7d7c5..000000000 --- a/test_regress/t/t_unopt_converge_unopt_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2007 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_unopt_converge.v"); - -compile( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_unopt_converge_unopt_bad.py b/test_regress/t/t_unopt_converge_unopt_bad.py new file mode 100755 index 000000000..23a3f47d2 --- /dev/null +++ b/test_regress/t/t_unopt_converge_unopt_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_unopt_converge.v" + +test.compile(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_unoptflat_simple_2_bad.pl b/test_regress/t/t_unoptflat_simple_2_bad.pl deleted file mode 100755 index 285d1dffd..000000000 --- a/test_regress/t/t_unoptflat_simple_2_bad.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_unoptflat_simple_2.v"); - -# Compile only -compile( - verilator_flags3 => [], - verilator_flags2 => ["--report-unoptflat"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - - -ok(1); -1; diff --git a/test_regress/t/t_unoptflat_simple_2_bad.py b/test_regress/t/t_unoptflat_simple_2_bad.py new file mode 100755 index 000000000..5c6e4b955 --- /dev/null +++ b/test_regress/t/t_unoptflat_simple_2_bad.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_unoptflat_simple_2.v" + +# Compile only +test.compile(verilator_flags3=[], + verilator_flags2=["--report-unoptflat"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_unoptflat_simple_3_bad.pl b/test_regress/t/t_unoptflat_simple_3_bad.pl deleted file mode 100755 index b838ad45f..000000000 --- a/test_regress/t/t_unoptflat_simple_3_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_unoptflat_simple_3.v"); - -# Compile only -compile( - fails => 1 - ); - -ok(1); -1; diff --git a/test_regress/t/t_unoptflat_simple_3_bad.py b/test_regress/t/t_unoptflat_simple_3_bad.py new file mode 100755 index 000000000..7c3da3bf6 --- /dev/null +++ b/test_regress/t/t_unoptflat_simple_3_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_unoptflat_simple_3.v" + +# Compile only +test.compile(fails=True) + +test.passes() diff --git a/test_regress/t/t_unoptflat_simple_bad.pl b/test_regress/t/t_unoptflat_simple_bad.pl deleted file mode 100755 index 2a9c4d934..000000000 --- a/test_regress/t/t_unoptflat_simple_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_unoptflat_simple.v"); - -# Compile only -compile( - fails => 1 - ); - -ok(1); -1; diff --git a/test_regress/t/t_unoptflat_simple_bad.py b/test_regress/t/t_unoptflat_simple_bad.py new file mode 100755 index 000000000..85da89728 --- /dev/null +++ b/test_regress/t/t_unoptflat_simple_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_unoptflat_simple.v" + +# Compile only +test.compile(fails=True) + +test.passes() diff --git a/test_regress/t/t_unpack_array_direct_assignment.pl b/test_regress/t/t_unpack_array_direct_assignment.pl deleted file mode 100755 index 1fc209e80..000000000 --- a/test_regress/t/t_unpack_array_direct_assignment.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_unpack_array_no_expand.v"); - -compile( - verilator_flags2 => ['-fno-expand'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_unpack_array_direct_assignment.py b/test_regress/t/t_unpack_array_direct_assignment.py new file mode 100755 index 000000000..dd7cd31de --- /dev/null +++ b/test_regress/t/t_unpack_array_direct_assignment.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_unpack_array_no_expand.v" + +test.compile(verilator_flags2=['-fno-expand']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unpack_array_no_expand.pl b/test_regress/t/t_unpack_array_no_expand.pl deleted file mode 100755 index e22e7f5d9..000000000 --- a/test_regress/t/t_unpack_array_no_expand.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_unpack_array_no_expand.py b/test_regress/t/t_unpack_array_no_expand.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_unpack_array_no_expand.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unpacked_array_order.pl b/test_regress/t/t_unpacked_array_order.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_unpacked_array_order.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_unpacked_array_order.py b/test_regress/t/t_unpacked_array_order.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_unpacked_array_order.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unpacked_array_p_fmt.pl b/test_regress/t/t_unpacked_array_p_fmt.pl deleted file mode 100755 index e48bd2921..000000000 --- a/test_regress/t/t_unpacked_array_p_fmt.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_unpacked_array_p_fmt.py b/test_regress/t/t_unpacked_array_p_fmt.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_unpacked_array_p_fmt.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_unpacked_concat.pl b/test_regress/t/t_unpacked_concat.pl deleted file mode 100755 index ec466bc06..000000000 --- a/test_regress/t/t_unpacked_concat.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); -execute( - ); - - -ok(1); -1; diff --git a/test_regress/t/t_unpacked_concat.py b/test_regress/t/t_unpacked_concat.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_unpacked_concat.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unpacked_concat_bad.pl b/test_regress/t/t_unpacked_concat_bad.pl deleted file mode 100755 index 63947fd00..000000000 --- a/test_regress/t/t_unpacked_concat_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_unpacked_concat_bad.py b/test_regress/t/t_unpacked_concat_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_unpacked_concat_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_unpacked_concat_bad2.pl b/test_regress/t/t_unpacked_concat_bad2.pl deleted file mode 100755 index 63947fd00..000000000 --- a/test_regress/t/t_unpacked_concat_bad2.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_unpacked_concat_bad2.py b/test_regress/t/t_unpacked_concat_bad2.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_unpacked_concat_bad2.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_unpacked_init.pl b/test_regress/t/t_unpacked_init.pl deleted file mode 100755 index 56363dab6..000000000 --- a/test_regress/t/t_unpacked_init.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_unpacked_init.py b/test_regress/t/t_unpacked_init.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_unpacked_init.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unpacked_slice.pl b/test_regress/t/t_unpacked_slice.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_unpacked_slice.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_unpacked_slice.py b/test_regress/t/t_unpacked_slice.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_unpacked_slice.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unpacked_slice_range.pl b/test_regress/t/t_unpacked_slice_range.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_unpacked_slice_range.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_unpacked_slice_range.py b/test_regress/t/t_unpacked_slice_range.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_unpacked_slice_range.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unpacked_str_init.pl b/test_regress/t/t_unpacked_str_init.pl deleted file mode 100755 index baf0745f9..000000000 --- a/test_regress/t/t_unpacked_str_init.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -# No execute, not self-checking - -ok(1); -1; diff --git a/test_regress/t/t_unpacked_str_init.py b/test_regress/t/t_unpacked_str_init.py new file mode 100755 index 000000000..e77872b79 --- /dev/null +++ b/test_regress/t/t_unpacked_str_init.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +# No execute, not self-checking + +test.passes() diff --git a/test_regress/t/t_unpacked_str_init2.pl b/test_regress/t/t_unpacked_str_init2.pl deleted file mode 100755 index bd9d5665a..000000000 --- a/test_regress/t/t_unpacked_str_init2.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - expect_filename => $Self->{golden_filename} - ); - -ok(1); -1; diff --git a/test_regress/t/t_unpacked_str_init2.py b/test_regress/t/t_unpacked_str_init2.py new file mode 100755 index 000000000..ab5dca066 --- /dev/null +++ b/test_regress/t/t_unpacked_str_init2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_unpacked_str_pair.pl b/test_regress/t/t_unpacked_str_pair.pl deleted file mode 100755 index 3708008f8..000000000 --- a/test_regress/t/t_unpacked_str_pair.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_unpacked_str_pair.py b/test_regress/t/t_unpacked_str_pair.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_unpacked_str_pair.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unpacked_struct_eq.pl b/test_regress/t/t_unpacked_struct_eq.pl deleted file mode 100755 index fdc76316a..000000000 --- a/test_regress/t/t_unpacked_struct_eq.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_unpacked_struct_eq.py b/test_regress/t/t_unpacked_struct_eq.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_unpacked_struct_eq.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unpacked_struct_redef.pl b/test_regress/t/t_unpacked_struct_redef.pl deleted file mode 100755 index e22e7f5d9..000000000 --- a/test_regress/t/t_unpacked_struct_redef.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_unpacked_struct_redef.py b/test_regress/t/t_unpacked_struct_redef.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_unpacked_struct_redef.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unpacked_struct_sel.pl b/test_regress/t/t_unpacked_struct_sel.pl deleted file mode 100755 index 9320d7bec..000000000 --- a/test_regress/t/t_unpacked_struct_sel.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_unpacked_struct_sel.py b/test_regress/t/t_unpacked_struct_sel.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_unpacked_struct_sel.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unroll_complexcond.pl b/test_regress/t/t_unroll_complexcond.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_unroll_complexcond.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_unroll_complexcond.py b/test_regress/t/t_unroll_complexcond.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_unroll_complexcond.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unroll_delay.pl b/test_regress/t/t_unroll_delay.pl deleted file mode 100755 index 2fa7afd8b..000000000 --- a/test_regress/t/t_unroll_delay.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--binary --timing --trace'], - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_unroll_delay.py b/test_regress/t/t_unroll_delay.py new file mode 100755 index 000000000..47049c4c4 --- /dev/null +++ b/test_regress/t/t_unroll_delay.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--binary --timing --trace']) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_unroll_forfor.pl b/test_regress/t/t_unroll_forfor.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_unroll_forfor.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_unroll_forfor.py b/test_regress/t/t_unroll_forfor.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_unroll_forfor.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unroll_genf.pl b/test_regress/t/t_unroll_genf.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_unroll_genf.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_unroll_genf.py b/test_regress/t/t_unroll_genf.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_unroll_genf.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unroll_pragma_disable.pl b/test_regress/t/t_unroll_pragma_disable.pl deleted file mode 100755 index 5768e83d0..000000000 --- a/test_regress/t/t_unroll_pragma_disable.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_unroll_pragma.v"); - -compile( - verilator_flags2 => ['--unroll-count 4 --unroll-stmts 9999 --stats -DTEST_DISABLE'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -file_grep($Self->{stats}, qr/Optimizations, Unrolled Loops\s+(\d+)/, 1); - -ok(1); -1; diff --git a/test_regress/t/t_unroll_pragma_disable.py b/test_regress/t/t_unroll_pragma_disable.py new file mode 100755 index 000000000..62b1b7832 --- /dev/null +++ b/test_regress/t/t_unroll_pragma_disable.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_unroll_pragma.v" + +test.compile(verilator_flags2=['--unroll-count 4 --unroll-stmts 9999 --stats -DTEST_DISABLE'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.file_grep(test.stats, r'Optimizations, Unrolled Loops\s+(\d+)', 1) + +test.passes() diff --git a/test_regress/t/t_unroll_pragma_full.pl b/test_regress/t/t_unroll_pragma_full.pl deleted file mode 100755 index d50c226d3..000000000 --- a/test_regress/t/t_unroll_pragma_full.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_unroll_pragma.v"); - -compile( - verilator_flags2 => ['--unroll-count 4 --unroll-stmts 9999 --stats -DTEST_FULL'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -file_grep($Self->{stats}, qr/Optimizations, Unrolled Loops\s+(\d+)/, 5); - -ok(1); -1; diff --git a/test_regress/t/t_unroll_pragma_full.py b/test_regress/t/t_unroll_pragma_full.py new file mode 100755 index 000000000..6018f47de --- /dev/null +++ b/test_regress/t/t_unroll_pragma_full.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_unroll_pragma.v" + +test.compile(verilator_flags2=['--unroll-count 4 --unroll-stmts 9999 --stats -DTEST_FULL'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.file_grep(test.stats, r'Optimizations, Unrolled Loops\s+(\d+)', 5) + +test.passes() diff --git a/test_regress/t/t_unroll_pragma_none.pl b/test_regress/t/t_unroll_pragma_none.pl deleted file mode 100755 index 346bf6caf..000000000 --- a/test_regress/t/t_unroll_pragma_none.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_unroll_pragma.v"); - -compile( - verilator_flags2 => ['--unroll-count 4 --unroll-stmts 9999 --stats -DTEST_NONE'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -file_grep($Self->{stats}, qr/Optimizations, Unrolled Loops\s+(\d+)/, 3); - -ok(1); -1; diff --git a/test_regress/t/t_unroll_pragma_none.py b/test_regress/t/t_unroll_pragma_none.py new file mode 100755 index 000000000..34fedcad9 --- /dev/null +++ b/test_regress/t/t_unroll_pragma_none.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_unroll_pragma.v" + +test.compile(verilator_flags2=['--unroll-count 4 --unroll-stmts 9999 --stats -DTEST_NONE'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.file_grep(test.stats, r'Optimizations, Unrolled Loops\s+(\d+)', 3) + +test.passes() diff --git a/test_regress/t/t_unroll_signed.pl b/test_regress/t/t_unroll_signed.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_unroll_signed.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_unroll_signed.py b/test_regress/t/t_unroll_signed.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_unroll_signed.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_unroll_unopt_io.pl b/test_regress/t/t_unroll_unopt_io.pl deleted file mode 100755 index 1df6afd70..000000000 --- a/test_regress/t/t_unroll_unopt_io.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--x-assign fast'], - ); - -ok(1); -1; diff --git a/test_regress/t/t_unroll_unopt_io.py b/test_regress/t/t_unroll_unopt_io.py new file mode 100755 index 000000000..af1f37c0c --- /dev/null +++ b/test_regress/t/t_unroll_unopt_io.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--x-assign fast']) + +test.passes() diff --git a/test_regress/t/t_urandom.pl b/test_regress/t/t_urandom.pl deleted file mode 100755 index 49330a5fe..000000000 --- a/test_regress/t/t_urandom.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_urandom.py b/test_regress/t/t_urandom.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_urandom.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_uvm_all.pl b/test_regress/t/t_uvm_all.pl deleted file mode 100755 index 532569c82..000000000 --- a/test_regress/t/t_uvm_all.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - v_flags2 => ["--binary --timing", - "-Wno-PKGNODECL -Wno-IMPLICITSTATIC -Wno-CONSTRAINTIGN -Wno-MISINDENT", - "-Wno-WIDTHEXPAND -Wno-WIDTHTRUNC -Wno-CASTCONST -Wno-REALCVT", - "--error-limit 200 --debug-exit-uvm"], - verilator_make_gmake => 0, - ); - -#execute( -# ); - -ok(1); -1; diff --git a/test_regress/t/t_uvm_all.py b/test_regress/t/t_uvm_all.py new file mode 100755 index 000000000..99de0e34b --- /dev/null +++ b/test_regress/t/t_uvm_all.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(v_flags2=[ + "--binary --timing", "-Wno-PKGNODECL -Wno-IMPLICITSTATIC -Wno-CONSTRAINTIGN -Wno-MISINDENT", + "-Wno-WIDTHEXPAND -Wno-WIDTHTRUNC -Wno-CASTCONST -Wno-REALCVT", + "--error-limit 200 --debug-exit-uvm" +], + verilator_make_gmake=False) + +#test.execute() + +test.passes() diff --git a/test_regress/t/t_uvm_pkg_all.vh b/test_regress/t/t_uvm_pkg_all.vh index 2c97fecb3..362e714b8 100644 --- a/test_regress/t/t_uvm_pkg_all.vh +++ b/test_regress/t/t_uvm_pkg_all.vh @@ -3,7 +3,7 @@ //------------------------------------------------------------------------------ // To recreate: // Using verilator_ext_tests -// t/t_uvm_parse.pl --debug --no-dump-tree +// t/t_uvm_parse.py --debug --no-dump-tree // Copy to here t/obj_vlt/Vt_uvm_parse/Vt_uvm_parse__inputs.vpp // M-x untabify // (global-replace-regexp "[ ]+$" "") diff --git a/test_regress/t/t_uvm_pkg_todo.vh b/test_regress/t/t_uvm_pkg_todo.vh index 97b5b50f7..e0c8d49ce 100644 --- a/test_regress/t/t_uvm_pkg_todo.vh +++ b/test_regress/t/t_uvm_pkg_todo.vh @@ -3,7 +3,7 @@ //------------------------------------------------------------------------------ // To recreate: // Using verilator_ext_tests -// t/t_uvm_parse.pl --debug --no-dump-tree +// t/t_uvm_parse.py --debug --no-dump-tree // Copy to here t/obj_vlt/Vt_uvm_parse/Vt_uvm_parse__inputs.vpp // M-x untabify // (global-replace-regexp "[ ]+$" "") diff --git a/test_regress/t/t_uvm_todo.pl b/test_regress/t/t_uvm_todo.pl deleted file mode 100755 index 23a99f9ab..000000000 --- a/test_regress/t/t_uvm_todo.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - v_flags2 => ["--timing", - "-Wno-PKGNODECL -Wno-IMPLICITSTATIC -Wno-CONSTRAINTIGN -Wno-MISINDENT", - "-Wno-CASEINCOMPLETE -Wno-CASTCONST -Wno-SYMRSVDWORD -Wno-WIDTHEXPAND -Wno-WIDTHTRUNC", - "-Wno-REALCVT", # TODO note mostly related to $realtime - could suppress or fix upstream - "-Wno-ZERODLY", # TODO issue #4494, add support - ], - make_flags => '-k -j ' . ::max_procs(), - verilator_make_gmake => 0, - ); - -#execute( -# ); - -ok(1); -1; diff --git a/test_regress/t/t_uvm_todo.py b/test_regress/t/t_uvm_todo.py new file mode 100755 index 000000000..fa2facbf8 --- /dev/null +++ b/test_regress/t/t_uvm_todo.py @@ -0,0 +1,28 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import multiprocessing + +test.scenarios('vlt') + +test.compile( + v_flags2=[ + "--timing", + "-Wno-PKGNODECL -Wno-IMPLICITSTATIC -Wno-CONSTRAINTIGN -Wno-MISINDENT", + "-Wno-CASEINCOMPLETE -Wno-CASTCONST -Wno-SYMRSVDWORD -Wno-WIDTHEXPAND -Wno-WIDTHTRUNC", + "-Wno-REALCVT", # TODO note mostly related to $realtime - could suppress or fix upstream + "-Wno-ZERODLY", # TODO issue #4494, add support + ], + make_flags=['-k -j ' + str(multiprocessing.cpu_count())], + verilator_make_gmake=False) + +#test.execute() + +test.passes() diff --git a/test_regress/t/t_vams_basic.pl b/test_regress/t/t_vams_basic.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_vams_basic.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_vams_basic.py b/test_regress/t/t_vams_basic.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_vams_basic.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_vams_kwd_bad.pl b/test_regress/t/t_vams_kwd_bad.pl deleted file mode 100755 index 623dba016..000000000 --- a/test_regress/t/t_vams_kwd_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - verilator_flags2 => ["--error-limit 1000"], - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_vams_kwd_bad.py b/test_regress/t/t_vams_kwd_bad.py new file mode 100755 index 000000000..45a114b8a --- /dev/null +++ b/test_regress/t/t_vams_kwd_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, + verilator_flags2=["--error-limit 1000"], + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_vams_wreal.pl b/test_regress/t/t_vams_wreal.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_vams_wreal.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_vams_wreal.py b/test_regress/t/t_vams_wreal.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_vams_wreal.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_assign_landr.pl b/test_regress/t/t_var_assign_landr.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_var_assign_landr.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_assign_landr.py b/test_regress/t/t_var_assign_landr.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_var_assign_landr.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_assign_landr_noexpand.pl b/test_regress/t/t_var_assign_landr_noexpand.pl deleted file mode 100755 index af086b69c..000000000 --- a/test_regress/t/t_var_assign_landr_noexpand.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_var_assign_landr.v"); - -compile( - verilator_flags2 => ['-fno-expand'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_assign_landr_noexpand.py b/test_regress/t/t_var_assign_landr_noexpand.py new file mode 100755 index 000000000..5b4129fff --- /dev/null +++ b/test_regress/t/t_var_assign_landr_noexpand.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_var_assign_landr.v" + +test.compile(verilator_flags2=['-fno-expand']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_bad_hide.pl b/test_regress/t/t_var_bad_hide.pl deleted file mode 100755 index f1eef1686..000000000 --- a/test_regress/t/t_var_bad_hide.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only -Wwarn-VARHIDDEN"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_bad_hide.py b/test_regress/t/t_var_bad_hide.py new file mode 100755 index 000000000..2076da382 --- /dev/null +++ b/test_regress/t/t_var_bad_hide.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only -Wwarn-VARHIDDEN"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_bad_hide2.pl b/test_regress/t/t_var_bad_hide2.pl deleted file mode 100755 index fc5822886..000000000 --- a/test_regress/t/t_var_bad_hide2.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ["--lint-only -Wwarn-VARHIDDEN"], - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_bad_hide2.py b/test_regress/t/t_var_bad_hide2.py new file mode 100755 index 000000000..d546b464e --- /dev/null +++ b/test_regress/t/t_var_bad_hide2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--lint-only -Wwarn-VARHIDDEN"], + fails=test.vlt_all, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_bad_hide_docs.pl b/test_regress/t/t_var_bad_hide_docs.pl deleted file mode 100755 index c683326f1..000000000 --- a/test_regress/t/t_var_bad_hide_docs.pl +++ /dev/null @@ -1,37 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -my $root = ".."; - -if (!-r "$root/.git") { - skip("Not in a git repository"); -} else { - lint( - verilator_flags2 => ["--lint-only -Wwarn-VARHIDDEN"], - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - - extract( - in => $Self->{top_filename}, - out => "../docs/gen/ex_VARHIDDEN_faulty.rst", - regexp => qr/(module t|integer|endmodule)/); - - extract( - in => $Self->{golden_filename}, - out => "../docs/gen/ex_VARHIDDEN_msg.rst", - lineno_adjust => -6, - regexp => qr/(var_bad_hide)/); -} - -ok(1); -1; diff --git a/test_regress/t/t_var_bad_hide_docs.py b/test_regress/t/t_var_bad_hide_docs.py new file mode 100755 index 000000000..fea969814 --- /dev/null +++ b/test_regress/t/t_var_bad_hide_docs.py @@ -0,0 +1,32 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +root = ".." + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +test.lint(verilator_flags2=["--lint-only -Wwarn-VARHIDDEN"], + fails=test.vlt_all, + expect_filename=test.golden_filename) + +test.extract(in_filename=test.top_filename, + out_filename="../docs/gen/ex_VARHIDDEN_faulty.rst", + regexp=r'(module t|integer|endmodule)') + +test.extract(in_filename=test.golden_filename, + out_filename="../docs/gen/ex_VARHIDDEN_msg.rst", + lineno_adjust=-6, + regexp=r'(var_bad_hide)') + +test.passes() diff --git a/test_regress/t/t_var_bad_sameas.pl b/test_regress/t/t_var_bad_sameas.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_var_bad_sameas.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_bad_sameas.py b/test_regress/t/t_var_bad_sameas.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_var_bad_sameas.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_bad_sv.pl b/test_regress/t/t_var_bad_sv.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_var_bad_sv.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_bad_sv.py b/test_regress/t/t_var_bad_sv.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_var_bad_sv.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_const.pl b/test_regress/t/t_var_const.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_var_const.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_const.py b/test_regress/t/t_var_const.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_var_const.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_const_bad.pl b/test_regress/t/t_var_const_bad.pl deleted file mode 100755 index 5e419b352..000000000 --- a/test_regress/t/t_var_const_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2005 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_const_bad.py b/test_regress/t/t_var_const_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_var_const_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_dotted1_inl0.pl b/test_regress/t/t_var_dotted1_inl0.pl deleted file mode 100755 index 48d876034..000000000 --- a/test_regress/t/t_var_dotted1_inl0.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_var_dotted1.v"); - -compile( - v_flags2 => ['+define+NOUSE_INLINE',], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_dotted1_inl0.py b/test_regress/t/t_var_dotted1_inl0.py new file mode 100755 index 000000000..4fc10fede --- /dev/null +++ b/test_regress/t/t_var_dotted1_inl0.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_var_dotted1.v" + +test.compile(v_flags2=['+define+NOUSE_INLINE']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_dotted1_inl1.pl b/test_regress/t/t_var_dotted1_inl1.pl deleted file mode 100755 index 9fa8ca09c..000000000 --- a/test_regress/t/t_var_dotted1_inl1.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_var_dotted1.v"); - -compile( - v_flags2 => ['+define+USE_INLINE',], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_dotted1_inl1.py b/test_regress/t/t_var_dotted1_inl1.py new file mode 100755 index 000000000..e2a6573e0 --- /dev/null +++ b/test_regress/t/t_var_dotted1_inl1.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_var_dotted1.v" + +test.compile(v_flags2=['+define+USE_INLINE']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_dotted1_inl2.pl b/test_regress/t/t_var_dotted1_inl2.pl deleted file mode 100755 index f18eb7cbe..000000000 --- a/test_regress/t/t_var_dotted1_inl2.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_var_dotted1.v"); - -compile( - v_flags2 => ['+define+USE_INLINE_MID',], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_dotted1_inl2.py b/test_regress/t/t_var_dotted1_inl2.py new file mode 100755 index 000000000..9af70f709 --- /dev/null +++ b/test_regress/t/t_var_dotted1_inl2.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_var_dotted1.v" + +test.compile(v_flags2=['+define+USE_INLINE_MID']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_dotted2_inl0.pl b/test_regress/t/t_var_dotted2_inl0.pl deleted file mode 100755 index 2664fc302..000000000 --- a/test_regress/t/t_var_dotted2_inl0.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_var_dotted2.v"); - -compile( - v_flags2 => ['+define+NOUSE_INLINE',], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_dotted2_inl0.py b/test_regress/t/t_var_dotted2_inl0.py new file mode 100755 index 000000000..d1929af8d --- /dev/null +++ b/test_regress/t/t_var_dotted2_inl0.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_var_dotted2.v" + +test.compile(v_flags2=['+define+NOUSE_INLINE']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_dotted2_inl1.pl b/test_regress/t/t_var_dotted2_inl1.pl deleted file mode 100755 index f98268605..000000000 --- a/test_regress/t/t_var_dotted2_inl1.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_var_dotted2.v"); - -compile( - v_flags2 => ['+define+USE_INLINE',], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_dotted2_inl1.py b/test_regress/t/t_var_dotted2_inl1.py new file mode 100755 index 000000000..1638e3047 --- /dev/null +++ b/test_regress/t/t_var_dotted2_inl1.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_var_dotted2.v" + +test.compile(v_flags2=['+define+USE_INLINE']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_dotted_dup_bad.pl b/test_regress/t/t_var_dotted_dup_bad.pl deleted file mode 100755 index f25e38708..000000000 --- a/test_regress/t/t_var_dotted_dup_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2005 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_dotted_dup_bad.py b/test_regress/t/t_var_dotted_dup_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_var_dotted_dup_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_dup2.pl b/test_regress/t/t_var_dup2.pl deleted file mode 100755 index 09b2ce4eb..000000000 --- a/test_regress/t/t_var_dup2.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_dup2.py b/test_regress/t/t_var_dup2.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_var_dup2.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_var_dup2_bad.pl b/test_regress/t/t_var_dup2_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_var_dup2_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_dup2_bad.py b/test_regress/t/t_var_dup2_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_var_dup2_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_dup3.pl b/test_regress/t/t_var_dup3.pl deleted file mode 100755 index 09b2ce4eb..000000000 --- a/test_regress/t/t_var_dup3.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_dup3.py b/test_regress/t/t_var_dup3.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_var_dup3.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_var_dup_bad.pl b/test_regress/t/t_var_dup_bad.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_var_dup_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_dup_bad.py b/test_regress/t/t_var_dup_bad.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_var_dup_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_escape.pl b/test_regress/t/t_var_escape.pl deleted file mode 100755 index 74430bac0..000000000 --- a/test_regress/t/t_var_escape.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - # Access is so we can dump waves - v_flags2 => [$Self->{vlt_all} ? '-trace' : ' +access+rwc'], - ); - -execute( - ); - -if ($Self->{vlt_all}) { - file_grep($Self->trace_filename, qr/\$enddefinitions/); - my $sig = quotemeta("bra[ket]slash/dash-colon:9"); - file_grep($Self->trace_filename, qr/ $sig/); - file_grep($Self->trace_filename, qr/ other\.cyc /); - file_grep($Self->trace_filename, qr/ module mod\.with_dot /); - vcd_identical($Self->trace_filename, $Self->{golden_filename}); -} - -ok(1); -1; diff --git a/test_regress/t/t_var_escape.py b/test_regress/t/t_var_escape.py new file mode 100755 index 000000000..c4d5794db --- /dev/null +++ b/test_regress/t/t_var_escape.py @@ -0,0 +1,28 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + # Access is so we can dump waves + v_flags2=['-trace' if test.vlt_all else ' +access+rwc']) + +test.execute() + +if test.vlt_all: + test.file_grep(test.trace_filename, r'\$enddefinitions') + sigre = re.escape("bra[ket]slash/dash-colon:9") + test.file_grep(test.trace_filename, sigre) + test.file_grep(test.trace_filename, r' other\.cyc ') + test.file_grep(test.trace_filename, r' module mod\.with_dot ') + test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_extern_method_lifetime.pl b/test_regress/t/t_var_extern_method_lifetime.pl deleted file mode 100755 index 21a2189cc..000000000 --- a/test_regress/t/t_var_extern_method_lifetime.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_extern_method_lifetime.py b/test_regress/t/t_var_extern_method_lifetime.py new file mode 100755 index 000000000..a4e75e7ad --- /dev/null +++ b/test_regress/t/t_var_extern_method_lifetime.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_in_assign.pl b/test_regress/t/t_var_in_assign.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_var_in_assign.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_in_assign.py b/test_regress/t/t_var_in_assign.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_var_in_assign.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_in_assign_bad.pl b/test_regress/t/t_var_in_assign_bad.pl deleted file mode 100755 index 4fa14760f..000000000 --- a/test_regress/t/t_var_in_assign_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2005 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only --Mdir obj_lint_only"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -(!-d "obj_lint_only") or error("%Error: lint-only shouldn't make output directory"); - -ok(1); -1; diff --git a/test_regress/t/t_var_in_assign_bad.py b/test_regress/t/t_var_in_assign_bad.py new file mode 100755 index 000000000..b7ddcf7bd --- /dev/null +++ b/test_regress/t/t_var_in_assign_bad.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only --Mdir obj_lint_only"], + fails=True, + expect_filename=test.golden_filename) + +if os.path.exists("obj_lint_only"): + test.error("%Error: lint-only shouldn't make output directory") + +test.passes() diff --git a/test_regress/t/t_var_in_assign_pedantic.pl b/test_regress/t/t_var_in_assign_pedantic.pl deleted file mode 100755 index 205a9bca8..000000000 --- a/test_regress/t/t_var_in_assign_pedantic.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2005 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_var_in_assign_bad.v"); - -lint( - verilator_flags2 => ['-Wpedantic -Wno-fatal'], - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_in_assign_pedantic.py b/test_regress/t/t_var_in_assign_pedantic.py new file mode 100755 index 000000000..7b97942aa --- /dev/null +++ b/test_regress/t/t_var_in_assign_pedantic.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_var_in_assign_bad.v" + +test.lint(verilator_flags2=['-Wpedantic -Wno-fatal']) + +test.passes() diff --git a/test_regress/t/t_var_in_fork.pl b/test_regress/t/t_var_in_fork.pl deleted file mode 100755 index a8264f47b..000000000 --- a/test_regress/t/t_var_in_fork.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--binary --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_in_fork.py b/test_regress/t/t_var_in_fork.py new file mode 100755 index 000000000..7bd93561b --- /dev/null +++ b/test_regress/t/t_var_in_fork.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_init.pl b/test_regress/t/t_var_init.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_var_init.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_init.py b/test_regress/t/t_var_init.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_var_init.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_life.pl b/test_regress/t/t_var_life.pl deleted file mode 100755 index 2ea441dcb..000000000 --- a/test_regress/t/t_var_life.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--stats"], - ); - -if ($Self->{vlt_all}) { - file_grep($Self->{stats}, qr/Optimizations, Lifetime assign deletions\s+(\d+)/, 4); - file_grep($Self->{stats}, qr/Optimizations, Lifetime constant prop\s+(\d+)/, 2); -} - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_life.py b/test_regress/t/t_var_life.py new file mode 100755 index 000000000..09d396a1b --- /dev/null +++ b/test_regress/t/t_var_life.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--stats"]) + +if test.vlt_all: + test.file_grep(test.stats, r'Optimizations, Lifetime assign deletions\s+(\d+)', 4) + test.file_grep(test.stats, r'Optimizations, Lifetime constant prop\s+(\d+)', 2) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_local.pl b/test_regress/t/t_var_local.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_var_local.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_local.py b/test_regress/t/t_var_local.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_var_local.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_nonamebegin.pl b/test_regress/t/t_var_nonamebegin.pl deleted file mode 100755 index d2c433697..000000000 --- a/test_regress/t/t_var_nonamebegin.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['-trace'], - ); - -execute( - expect_filename => "t/$Self->{name}__log.out" - ); - -if ($Self->{vlt_all}) { - vcd_identical($Self->trace_filename, - $Self->{golden_filename}); -} -ok(1); -1; diff --git a/test_regress/t/t_var_nonamebegin.py b/test_regress/t/t_var_nonamebegin.py new file mode 100755 index 000000000..a6754718f --- /dev/null +++ b/test_regress/t/t_var_nonamebegin.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['-trace']) + +test.execute(expect_filename="t/" + test.name + "__log.out") + +if test.vlt_all: + test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_notfound_bad.pl b/test_regress/t/t_var_notfound_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_var_notfound_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_notfound_bad.py b/test_regress/t/t_var_notfound_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_var_notfound_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_outoforder.pl b/test_regress/t/t_var_outoforder.pl deleted file mode 100755 index fdc76316a..000000000 --- a/test_regress/t/t_var_outoforder.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2004 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_outoforder.py b/test_regress/t/t_var_outoforder.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_var_outoforder.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_overcmp.pl b/test_regress/t/t_var_overcmp.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_var_overcmp.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_overcmp.py b/test_regress/t/t_var_overcmp.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_var_overcmp.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_overwidth_bad.pl b/test_regress/t/t_var_overwidth_bad.pl deleted file mode 100755 index cecc640a5..000000000 --- a/test_regress/t/t_var_overwidth_bad.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/t_var_overwidth_bad.cpp"], - ); - -execute( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_overwidth_bad.py b/test_regress/t/t_var_overwidth_bad.py new file mode 100755 index 000000000..8f9635a27 --- /dev/null +++ b/test_regress/t/t_var_overwidth_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_overzero.pl b/test_regress/t/t_var_overzero.pl deleted file mode 100755 index 3d0750613..000000000 --- a/test_regress/t/t_var_overzero.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["--x-initial fast"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_overzero.py b/test_regress/t/t_var_overzero.py new file mode 100755 index 000000000..a2adc5082 --- /dev/null +++ b/test_regress/t/t_var_overzero.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--x-initial fast"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_pins_cc.pl b/test_regress/t/t_var_pins_cc.pl deleted file mode 100755 index 90a0a6d02..000000000 --- a/test_regress/t/t_var_pins_cc.pl +++ /dev/null @@ -1,39 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_var_pinsizes.v"); - -compile( - verilator_flags2 => ['-cc'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -{ - file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_IN8\(&i1,0,0\);/); - file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_IN8\(&i8,7,0\);/); - file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_IN16\(&i16,15,0\);/); - file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_IN\(&i32,31,0\);/); - file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_IN64\(&i64,63,0\);/); - file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_INW\(&i65,64,0,3\);/); - - file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_OUT8\(&o1,0,0\);/); - file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_OUT8\(&o8,7,0\);/); - file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_OUT16\(&o16,15,0\);/); - file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_OUT\(&o32,31,0\);/); - file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_OUT64\(&o64,63,0\);/); - file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_OUTW\(&o65,64,0,3\);/); -} - -ok(1); -1; diff --git a/test_regress/t/t_var_pins_cc.py b/test_regress/t/t_var_pins_cc.py new file mode 100755 index 000000000..1912bf071 --- /dev/null +++ b/test_regress/t/t_var_pins_cc.py @@ -0,0 +1,39 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_var_pinsizes.v" + +test.compile(verilator_flags2=['-cc'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + + +def hgrep(re): + test.file_grep(os.path.join(test.obj_dir, test.vm_prefix + ".h"), re) + + +hgrep(r'VL_IN8\(&i1,0,0\);') +hgrep(r'VL_IN8\(&i8,7,0\);') +hgrep(r'VL_IN16\(&i16,15,0\);') +hgrep(r'VL_IN\(&i32,31,0\);') +hgrep(r'VL_IN64\(&i64,63,0\);') +hgrep(r'VL_INW\(&i65,64,0,3\);') + +hgrep(r'VL_OUT8\(&o1,0,0\);') +hgrep(r'VL_OUT8\(&o8,7,0\);') +hgrep(r'VL_OUT16\(&o16,15,0\);') +hgrep(r'VL_OUT\(&o32,31,0\);') +hgrep(r'VL_OUT64\(&o64,63,0\);') +hgrep(r'VL_OUTW\(&o65,64,0,3\);') + +test.passes() diff --git a/test_regress/t/t_var_pins_sc1.pl b/test_regress/t/t_var_pins_sc1.pl deleted file mode 100755 index d9b080f93..000000000 --- a/test_regress/t/t_var_pins_sc1.pl +++ /dev/null @@ -1,47 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_var_pinsizes.v"); - -compile( - verilator_flags2 => ["-sc -pins-bv 1 --trace --exe $Self->{t_dir}/t_var_pinsizes.cpp $Self->{t_dir}/t_var_pinsizes.vlt"], - make_main => 0, - ); - -if ($Self->{vlt_all}) { - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&i1;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&i8;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&i16;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&i32;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&i64;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&i65;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&ibv1;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&ibv16;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&ibv1_vlt;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&ibv16_vlt;/); - - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&o1;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&o8;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&o16;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&o32;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&o64;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&o65;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&obv1;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&obv16;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&obv1_vlt;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&obv16_vlt;/); -} - -execute(); - -ok(1); -1; diff --git a/test_regress/t/t_var_pins_sc1.py b/test_regress/t/t_var_pins_sc1.py new file mode 100755 index 000000000..69d66746d --- /dev/null +++ b/test_regress/t/t_var_pins_sc1.py @@ -0,0 +1,50 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.pli_filename = "t/t_var_pinsizes.cpp" +test.top_filename = "t/t_var_pinsizes.v" + +test.compile(verilator_flags2=[ + "-sc -pins-bv 1 --trace --exe", test.pli_filename, test.t_dir + "/t_var_pinsizes.vlt" +], + make_main=False) + + +def hgrep(re): + test.file_grep(os.path.join(test.obj_dir, test.vm_prefix + ".h"), re) + + +hgrep(r'sc_core::sc_in\s>\s+&i1;') +hgrep(r'sc_core::sc_in\s>\s+&i8;') +hgrep(r'sc_core::sc_in\s>\s+&i16;') +hgrep(r'sc_core::sc_in\s>\s+&i32;') +hgrep(r'sc_core::sc_in\s>\s+&i64;') +hgrep(r'sc_core::sc_in\s>\s+&i65;') +hgrep(r'sc_core::sc_in\s>\s+&ibv1;') +hgrep(r'sc_core::sc_in\s>\s+&ibv16;') +hgrep(r'sc_core::sc_in\s>\s+&ibv1_vlt;') +hgrep(r'sc_core::sc_in\s>\s+&ibv16_vlt;') + +hgrep(r'sc_core::sc_out\s>\s+&o1;') +hgrep(r'sc_core::sc_out\s>\s+&o8;') +hgrep(r'sc_core::sc_out\s>\s+&o16;') +hgrep(r'sc_core::sc_out\s>\s+&o32;') +hgrep(r'sc_core::sc_out\s>\s+&o64;') +hgrep(r'sc_core::sc_out\s>\s+&o65;') +hgrep(r'sc_core::sc_out\s>\s+&obv1;') +hgrep(r'sc_core::sc_out\s>\s+&obv16;') +hgrep(r'sc_core::sc_out\s>\s+&obv1_vlt;') +hgrep(r'sc_core::sc_out\s>\s+&obv16_vlt;') + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_pins_sc2.pl b/test_regress/t/t_var_pins_sc2.pl deleted file mode 100755 index 756e41c48..000000000 --- a/test_regress/t/t_var_pins_sc2.pl +++ /dev/null @@ -1,47 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_var_pinsizes.v"); - -compile( - verilator_flags2 => ["-sc -pins-bv 2 --trace --exe $Self->{t_dir}/t_var_pinsizes.cpp $Self->{t_dir}/t_var_pinsizes.vlt"], - make_main => 0, - ); - -{ - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s+&i1;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&i8;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&i16;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&i32;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&i64;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&i65;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&ibv1;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&ibv16;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&ibv1_vlt;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&ibv16_vlt;/); - - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s+&o1;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&o8;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&o16;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&o32;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&o64;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&o65;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&obv1;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&obv16;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&obv1_vlt;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&obv16_vlt;/); -} - -execute(); - -ok(1); -1; diff --git a/test_regress/t/t_var_pins_sc2.py b/test_regress/t/t_var_pins_sc2.py new file mode 100755 index 000000000..ef358bd83 --- /dev/null +++ b/test_regress/t/t_var_pins_sc2.py @@ -0,0 +1,50 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.pli_filename = "t/t_var_pinsizes.cpp" +test.top_filename = "t/t_var_pinsizes.v" + +test.compile(verilator_flags2=[ + "-sc -pins-bv 2 --trace --exe", test.pli_filename, test.t_dir + "/t_var_pinsizes.vlt" +], + make_main=False) + + +def hgrep(re): + test.file_grep(os.path.join(test.obj_dir, test.vm_prefix + ".h"), re) + + +hgrep(r'sc_core::sc_in\s+&i1;') +hgrep(r'sc_core::sc_in\s>\s+&i8;') +hgrep(r'sc_core::sc_in\s>\s+&i16;') +hgrep(r'sc_core::sc_in\s>\s+&i32;') +hgrep(r'sc_core::sc_in\s>\s+&i64;') +hgrep(r'sc_core::sc_in\s>\s+&i65;') +hgrep(r'sc_core::sc_in\s>\s+&ibv1;') +hgrep(r'sc_core::sc_in\s>\s+&ibv16;') +hgrep(r'sc_core::sc_in\s>\s+&ibv1_vlt;') +hgrep(r'sc_core::sc_in\s>\s+&ibv16_vlt;') + +hgrep(r'sc_core::sc_out\s+&o1;') +hgrep(r'sc_core::sc_out\s>\s+&o8;') +hgrep(r'sc_core::sc_out\s>\s+&o16;') +hgrep(r'sc_core::sc_out\s>\s+&o32;') +hgrep(r'sc_core::sc_out\s>\s+&o64;') +hgrep(r'sc_core::sc_out\s>\s+&o65;') +hgrep(r'sc_core::sc_out\s>\s+&obv1;') +hgrep(r'sc_core::sc_out\s>\s+&obv16;') +hgrep(r'sc_core::sc_out\s>\s+&obv1_vlt;') +hgrep(r'sc_core::sc_out\s>\s+&obv16_vlt;') + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_pins_sc32.pl b/test_regress/t/t_var_pins_sc32.pl deleted file mode 100755 index 60c70e04c..000000000 --- a/test_regress/t/t_var_pins_sc32.pl +++ /dev/null @@ -1,47 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_var_pinsizes.v"); - -compile( - verilator_flags2 => ["-sc -no-pins64 --trace --exe $Self->{t_dir}/t_var_pinsizes.cpp $Self->{t_dir}/t_var_pinsizes.vlt"], - make_main => 0, - ); - -{ - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s+&i1;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s+&i8;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s+&i16;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s+&i32;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&i64;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&i65;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&ibv1;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&ibv16;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&ibv1_vlt;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&ibv16_vlt;/); - - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s+&o1;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s+&o8;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s+&o16;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s+&o32;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&o64;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&o65;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&obv1;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&obv16;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&obv1_vlt;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&obv16_vlt;/); -} - -execute(); - -ok(1); -1; diff --git a/test_regress/t/t_var_pins_sc32.py b/test_regress/t/t_var_pins_sc32.py new file mode 100755 index 000000000..184ba2d2b --- /dev/null +++ b/test_regress/t/t_var_pins_sc32.py @@ -0,0 +1,50 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.pli_filename = "t/t_var_pinsizes.cpp" +test.top_filename = "t/t_var_pinsizes.v" + +test.compile(verilator_flags2=[ + "-sc -no-pins64 --trace --exe", test.pli_filename, test.t_dir + "/t_var_pinsizes.vlt" +], + make_main=False) + + +def hgrep(re): + test.file_grep(os.path.join(test.obj_dir, test.vm_prefix + ".h"), re) + + +hgrep(r'sc_core::sc_in\s+&i1;') +hgrep(r'sc_core::sc_in\s+&i8;') +hgrep(r'sc_core::sc_in\s+&i16;') +hgrep(r'sc_core::sc_in\s+&i32;') +hgrep(r'sc_core::sc_in\s>\s+&i64;') +hgrep(r'sc_core::sc_in\s>\s+&i65;') +hgrep(r'sc_core::sc_in\s>\s+&ibv1;') +hgrep(r'sc_core::sc_in\s>\s+&ibv16;') +hgrep(r'sc_core::sc_in\s>\s+&ibv1_vlt;') +hgrep(r'sc_core::sc_in\s>\s+&ibv16_vlt;') + +hgrep(r'sc_core::sc_out\s+&o1;') +hgrep(r'sc_core::sc_out\s+&o8;') +hgrep(r'sc_core::sc_out\s+&o16;') +hgrep(r'sc_core::sc_out\s+&o32;') +hgrep(r'sc_core::sc_out\s>\s+&o64;') +hgrep(r'sc_core::sc_out\s>\s+&o65;') +hgrep(r'sc_core::sc_out\s>\s+&obv1;') +hgrep(r'sc_core::sc_out\s>\s+&obv16;') +hgrep(r'sc_core::sc_out\s>\s+&obv1_vlt;') +hgrep(r'sc_core::sc_out\s>\s+&obv16_vlt;') + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_pins_sc64.pl b/test_regress/t/t_var_pins_sc64.pl deleted file mode 100755 index 0c014a722..000000000 --- a/test_regress/t/t_var_pins_sc64.pl +++ /dev/null @@ -1,47 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_var_pinsizes.v"); - -compile( - verilator_flags2 => ["-sc -pins64 --trace --exe $Self->{t_dir}/t_var_pinsizes.cpp $Self->{t_dir}/t_var_pinsizes.vlt"], - make_main => 0, - ); - -if ($Self->{vlt_all}) { - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s+&i1;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s+&i8;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s+&i16;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s+&i32;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s+&i64;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&i65;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&ibv1;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&ibv16;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&ibv1_vlt;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&ibv16_vlt;/); - - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s+&o1;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s+&o8;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s+&o16;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s+&o32;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s+&o64;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&o65;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&obv1;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&obv16;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&obv1_vlt;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&obv16_vlt;/); -} - -execute(); - -ok(1); -1; diff --git a/test_regress/t/t_var_pins_sc64.py b/test_regress/t/t_var_pins_sc64.py new file mode 100755 index 000000000..4dca57a9d --- /dev/null +++ b/test_regress/t/t_var_pins_sc64.py @@ -0,0 +1,50 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.pli_filename = "t/t_var_pinsizes.cpp" +test.top_filename = "t/t_var_pinsizes.v" + +test.compile(verilator_flags2=[ + "-sc -pins64 --trace --exe", test.pli_filename, test.t_dir + "/t_var_pinsizes.vlt" +], + make_main=False) + + +def hgrep(re): + test.file_grep(os.path.join(test.obj_dir, test.vm_prefix + ".h"), re) + + +hgrep(r'sc_core::sc_in\s+&i1;') +hgrep(r'sc_core::sc_in\s+&i8;') +hgrep(r'sc_core::sc_in\s+&i16;') +hgrep(r'sc_core::sc_in\s+&i32;') +hgrep(r'sc_core::sc_in\s+&i64;') +hgrep(r'sc_core::sc_in\s>\s+&i65;') +hgrep(r'sc_core::sc_in\s>\s+&ibv1;') +hgrep(r'sc_core::sc_in\s>\s+&ibv16;') +hgrep(r'sc_core::sc_in\s>\s+&ibv1_vlt;') +hgrep(r'sc_core::sc_in\s>\s+&ibv16_vlt;') + +hgrep(r'sc_core::sc_out\s+&o1;') +hgrep(r'sc_core::sc_out\s+&o8;') +hgrep(r'sc_core::sc_out\s+&o16;') +hgrep(r'sc_core::sc_out\s+&o32;') +hgrep(r'sc_core::sc_out\s+&o64;') +hgrep(r'sc_core::sc_out\s>\s+&o65;') +hgrep(r'sc_core::sc_out\s>\s+&obv1;') +hgrep(r'sc_core::sc_out\s>\s+&obv16;') +hgrep(r'sc_core::sc_out\s>\s+&obv1_vlt;') +hgrep(r'sc_core::sc_out\s>\s+&obv16_vlt;') + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_pins_sc_biguint.pl b/test_regress/t/t_var_pins_sc_biguint.pl deleted file mode 100755 index 30a25337a..000000000 --- a/test_regress/t/t_var_pins_sc_biguint.pl +++ /dev/null @@ -1,47 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_var_pinsizes.v"); - -compile( - verilator_flags2 => ["-sc --pins-sc-biguint --trace --exe $Self->{t_dir}/t_var_pinsizes.cpp"], - make_main => 0, - ); - -if ($Self->{vlt_all}) { - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s+&i1;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s+&i8;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s+&i16;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s+&i32;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s+&i64;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&i65;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&i128;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&i513;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&ibv1;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&ibv16;/); - - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s+&o1;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s+&o8;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s+&o16;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s+&o32;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s+&o64;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&o65;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&o128;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&o513;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&obv1;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&obv16;/); -} - -execute(); - -ok(1); -1; diff --git a/test_regress/t/t_var_pins_sc_biguint.py b/test_regress/t/t_var_pins_sc_biguint.py new file mode 100755 index 000000000..a50232864 --- /dev/null +++ b/test_regress/t/t_var_pins_sc_biguint.py @@ -0,0 +1,48 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.pli_filename = "t/t_var_pinsizes.cpp" +test.top_filename = "t/t_var_pinsizes.v" + +test.compile(verilator_flags2=["-sc --pins-sc-biguint --trace --exe", test.pli_filename], + make_main=False) + + +def hgrep(re): + test.file_grep(os.path.join(test.obj_dir, test.vm_prefix + ".h"), re) + + +hgrep(r'sc_core::sc_in\s+&i1;') +hgrep(r'sc_core::sc_in\s+&i8;') +hgrep(r'sc_core::sc_in\s+&i16;') +hgrep(r'sc_core::sc_in\s+&i32;') +hgrep(r'sc_core::sc_in\s+&i64;') +hgrep(r'sc_core::sc_in\s>\s+&i65;') +hgrep(r'sc_core::sc_in\s>\s+&i128;') +hgrep(r'sc_core::sc_in\s>\s+&i513;') +hgrep(r'sc_core::sc_in\s>\s+&ibv1;') +hgrep(r'sc_core::sc_in\s>\s+&ibv16;') + +hgrep(r'sc_core::sc_out\s+&o1;') +hgrep(r'sc_core::sc_out\s+&o8;') +hgrep(r'sc_core::sc_out\s+&o16;') +hgrep(r'sc_core::sc_out\s+&o32;') +hgrep(r'sc_core::sc_out\s+&o64;') +hgrep(r'sc_core::sc_out\s>\s+&o65;') +hgrep(r'sc_core::sc_out\s>\s+&o128;') +hgrep(r'sc_core::sc_out\s>\s+&o513;') +hgrep(r'sc_core::sc_out\s>\s+&obv1;') +hgrep(r'sc_core::sc_out\s>\s+&obv16;') + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_pins_sc_uint.pl b/test_regress/t/t_var_pins_sc_uint.pl deleted file mode 100755 index b69cbd08c..000000000 --- a/test_regress/t/t_var_pins_sc_uint.pl +++ /dev/null @@ -1,47 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_var_pinsizes.v"); - -compile( - verilator_flags2 => ["-sc --pins-sc-uint --trace --exe $Self->{t_dir}/t_var_pinsizes.cpp"], - make_main => 0, - ); - -{ - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s+&i1;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&i8;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&i16;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&i32;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&i64;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&i65;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&i128;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&i513;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&ibv1;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&ibv16;/); - - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s+&o1;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&o8;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&o16;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&o32;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&o64;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&o65;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&o128;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&o513;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&obv1;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&obv16;/); -} - -execute(); - -ok(1); -1; diff --git a/test_regress/t/t_var_pins_sc_uint.py b/test_regress/t/t_var_pins_sc_uint.py new file mode 100755 index 000000000..42602c6d0 --- /dev/null +++ b/test_regress/t/t_var_pins_sc_uint.py @@ -0,0 +1,48 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.pli_filename = "t/t_var_pinsizes.cpp" +test.top_filename = "t/t_var_pinsizes.v" + +test.compile(verilator_flags2=["-sc --pins-sc-uint --trace --exe", test.pli_filename], + make_main=False) + + +def hgrep(re): + test.file_grep(os.path.join(test.obj_dir, test.vm_prefix + ".h"), re) + + +hgrep(r'sc_core::sc_in\s+&i1;') +hgrep(r'sc_core::sc_in\s>\s+&i8;') +hgrep(r'sc_core::sc_in\s>\s+&i16;') +hgrep(r'sc_core::sc_in\s>\s+&i32;') +hgrep(r'sc_core::sc_in\s>\s+&i64;') +hgrep(r'sc_core::sc_in\s>\s+&i65;') +hgrep(r'sc_core::sc_in\s>\s+&i128;') +hgrep(r'sc_core::sc_in\s>\s+&i513;') +hgrep(r'sc_core::sc_in\s>\s+&ibv1;') +hgrep(r'sc_core::sc_in\s>\s+&ibv16;') + +hgrep(r'sc_core::sc_out\s+&o1;') +hgrep(r'sc_core::sc_out\s>\s+&o8;') +hgrep(r'sc_core::sc_out\s>\s+&o16;') +hgrep(r'sc_core::sc_out\s>\s+&o32;') +hgrep(r'sc_core::sc_out\s>\s+&o64;') +hgrep(r'sc_core::sc_out\s>\s+&o65;') +hgrep(r'sc_core::sc_out\s>\s+&o128;') +hgrep(r'sc_core::sc_out\s>\s+&o513;') +hgrep(r'sc_core::sc_out\s>\s+&obv1;') +hgrep(r'sc_core::sc_out\s>\s+&obv16;') + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_pins_sc_uint_biguint.pl b/test_regress/t/t_var_pins_sc_uint_biguint.pl deleted file mode 100755 index 3f0197b8e..000000000 --- a/test_regress/t/t_var_pins_sc_uint_biguint.pl +++ /dev/null @@ -1,47 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_var_pinsizes.v"); - -compile( - verilator_flags2 => ["-sc --pins-sc-uint --pins-sc-biguint --trace --exe $Self->{t_dir}/t_var_pinsizes.cpp"], - make_main => 0, - ); - -{ - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s+&i1;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&i8;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&i16;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&i32;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&i64;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&i65;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&i128;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&i513;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&ibv1;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&ibv16;/); - - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s+&o1;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&o8;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&o16;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&o32;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&o64;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&o65;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&o128;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&o513;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&obv1;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&obv16;/); -} - -execute(); - -ok(1); -1; diff --git a/test_regress/t/t_var_pins_sc_uint_biguint.py b/test_regress/t/t_var_pins_sc_uint_biguint.py new file mode 100755 index 000000000..c480b6b87 --- /dev/null +++ b/test_regress/t/t_var_pins_sc_uint_biguint.py @@ -0,0 +1,49 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.pli_filename = "t/t_var_pinsizes.cpp" +test.top_filename = "t/t_var_pinsizes.v" + +test.compile( + verilator_flags2=["-sc --pins-sc-uint --pins-sc-biguint --trace --exe", test.pli_filename], + make_main=False) + + +def hgrep(re): + test.file_grep(os.path.join(test.obj_dir, test.vm_prefix + ".h"), re) + + +hgrep(r'sc_core::sc_in\s+&i1;') +hgrep(r'sc_core::sc_in\s>\s+&i8;') +hgrep(r'sc_core::sc_in\s>\s+&i16;') +hgrep(r'sc_core::sc_in\s>\s+&i32;') +hgrep(r'sc_core::sc_in\s>\s+&i64;') +hgrep(r'sc_core::sc_in\s>\s+&i65;') +hgrep(r'sc_core::sc_in\s>\s+&i128;') +hgrep(r'sc_core::sc_in\s>\s+&i513;') +hgrep(r'sc_core::sc_in\s>\s+&ibv1;') +hgrep(r'sc_core::sc_in\s>\s+&ibv16;') + +hgrep(r'sc_core::sc_out\s+&o1;') +hgrep(r'sc_core::sc_out\s>\s+&o8;') +hgrep(r'sc_core::sc_out\s>\s+&o16;') +hgrep(r'sc_core::sc_out\s>\s+&o32;') +hgrep(r'sc_core::sc_out\s>\s+&o64;') +hgrep(r'sc_core::sc_out\s>\s+&o65;') +hgrep(r'sc_core::sc_out\s>\s+&o128;') +hgrep(r'sc_core::sc_out\s>\s+&o513;') +hgrep(r'sc_core::sc_out\s>\s+&obv1;') +hgrep(r'sc_core::sc_out\s>\s+&obv16;') + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_pins_sc_uint_bool.pl b/test_regress/t/t_var_pins_sc_uint_bool.pl deleted file mode 100755 index db6bdbd22..000000000 --- a/test_regress/t/t_var_pins_sc_uint_bool.pl +++ /dev/null @@ -1,43 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_var_pinsizes.v"); - -compile( - verilator_flags2 => ["-sc --pins-sc-uint-bool --trace --exe $Self->{t_dir}/t_var_pinsizes.cpp"], - make_main => 0, - ); - -{ - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&i1;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s+&i8;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s+&i16;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s+&i32;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s+&i64;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&i65;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&i128;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&i513;/); - - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&o1;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s+&o8;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s+&o16;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s+&o32;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s+&o64;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&o65;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&o128;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&o513;/); -} - -execute(); - -ok(1); -1; diff --git a/test_regress/t/t_var_pins_sc_uint_bool.py b/test_regress/t/t_var_pins_sc_uint_bool.py new file mode 100755 index 000000000..20acac5fe --- /dev/null +++ b/test_regress/t/t_var_pins_sc_uint_bool.py @@ -0,0 +1,44 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.pli_filename = "t/t_var_pinsizes.cpp" +test.top_filename = "t/t_var_pinsizes.v" + +test.compile(verilator_flags2=["-sc --pins-sc-uint-bool --trace --exe", test.pli_filename], + make_main=False) + + +def hgrep(re): + test.file_grep(os.path.join(test.obj_dir, test.vm_prefix + ".h"), re) + + +hgrep(r'sc_core::sc_in\s>\s+&i1;') +hgrep(r'sc_core::sc_in\s+&i8;') +hgrep(r'sc_core::sc_in\s+&i16;') +hgrep(r'sc_core::sc_in\s+&i32;') +hgrep(r'sc_core::sc_in\s+&i64;') +hgrep(r'sc_core::sc_in\s>\s+&i65;') +hgrep(r'sc_core::sc_in\s>\s+&i128;') +hgrep(r'sc_core::sc_in\s>\s+&i513;') + +hgrep(r'sc_core::sc_out\s>\s+&o1;') +hgrep(r'sc_core::sc_out\s+&o8;') +hgrep(r'sc_core::sc_out\s+&o16;') +hgrep(r'sc_core::sc_out\s+&o32;') +hgrep(r'sc_core::sc_out\s+&o64;') +hgrep(r'sc_core::sc_out\s>\s+&o65;') +hgrep(r'sc_core::sc_out\s>\s+&o128;') +hgrep(r'sc_core::sc_out\s>\s+&o513;') + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_pins_sc_uint_bool_nomain.pl b/test_regress/t/t_var_pins_sc_uint_bool_nomain.pl deleted file mode 100755 index e14f761da..000000000 --- a/test_regress/t/t_var_pins_sc_uint_bool_nomain.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# This test runs the very first time we've executed Verilator --sc -# after building so we make sure to run with --gdbbt, so if it dumps we'll -# get a trace. - -scenarios(simulator => 1); - -top_filename("t/t_a1_first_cc.v"); - -$DEBUG_QUIET = "--debug --debugi 0 --gdbbt --no-dump-tree"; - -compile( - verilator_flags2 => [$DEBUG_QUIET, "-sc --trace --pins-sc-uint-bool"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_pins_sc_uint_bool_nomain.py b/test_regress/t/t_var_pins_sc_uint_bool_nomain.py new file mode 100755 index 000000000..a6e5a22f5 --- /dev/null +++ b/test_regress/t/t_var_pins_sc_uint_bool_nomain.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +# This test runs the very first time we've executed Verilator --sc +# after building so we make sure to run with --gdbbt, so if it dumps we'll +# get a trace. + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_a1_first_cc.v" + +DEBUG_QUIET = "--debug --debugi 0 --gdbbt --no-dump-tree" + +test.compile(verilator_flags2=[DEBUG_QUIET, "-sc --trace --pins-sc-uint-bool"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_pins_scui.pl b/test_regress/t/t_var_pins_scui.pl deleted file mode 100755 index 1fbdc4de7..000000000 --- a/test_regress/t/t_var_pins_scui.pl +++ /dev/null @@ -1,43 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_var_pinsizes.v"); - -compile( - verilator_flags2 => ["-sc -pins-uint8 --trace --exe $Self->{t_dir}/t_var_pinsizes.cpp"], - make_main => 0, - ); - -if ($Self->{vlt_all}) { - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s+&i1;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s+&i8;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s+&i16;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s+&i32;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s+&i64;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&i65;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&ibv1;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_in\s>\s+&ibv16;/); - - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s+&o1;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s+&o8;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s+&o16;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s+&o32;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s+&o64;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&o65;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&obv1;/); - file_grep("$Self->{obj_dir}/$Self->{vm_prefix}.h", qr/sc_core::sc_out\s>\s+&obv16;/); -} - -execute(); - -ok(1); -1; diff --git a/test_regress/t/t_var_pins_scui.py b/test_regress/t/t_var_pins_scui.py new file mode 100755 index 000000000..0f9beb9a2 --- /dev/null +++ b/test_regress/t/t_var_pins_scui.py @@ -0,0 +1,45 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.pli_filename = "t/t_var_pinsizes.cpp" +test.top_filename = "t/t_var_pinsizes.v" + +test.compile(verilator_flags2=["-sc -pins-uint8 --trace --exe", test.pli_filename], + make_main=False) + +test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_in\s+&i1;') +test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_in\s+&i8;') +test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_in\s+&i16;') +test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_in\s+&i32;') +test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_in\s+&i64;') +test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", + r'sc_core::sc_in\s>\s+&i65;') +test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", + r'sc_core::sc_in\s>\s+&ibv1;') +test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", + r'sc_core::sc_in\s>\s+&ibv16;') + +test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_out\s+&o1;') +test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_out\s+&o8;') +test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_out\s+&o16;') +test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_out\s+&o32;') +test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_out\s+&o64;') +test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", + r'sc_core::sc_out\s>\s+&o65;') +test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", + r'sc_core::sc_out\s>\s+&obv1;') +test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", + r'sc_core::sc_out\s>\s+&obv16;') + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_port2_bad.pl b/test_regress/t/t_var_port2_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_var_port2_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_port2_bad.py b/test_regress/t/t_var_port2_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_var_port2_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_port_bad.pl b/test_regress/t/t_var_port_bad.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_var_port_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_port_bad.py b/test_regress/t/t_var_port_bad.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_var_port_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_port_json_only.pl b/test_regress/t/t_var_port_json_only.pl deleted file mode 100755 index 0230deada..000000000 --- a/test_regress/t/t_var_port_json_only.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.tree.json"; - -compile( - verilator_flags2 => ['--no-std', '--json-only', '--no-json-edit-nums'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -files_identical($out_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_var_port_json_only.py b/test_regress/t/t_var_port_json_only.py new file mode 100755 index 000000000..5fa0ddc00 --- /dev/null +++ b/test_regress/t/t_var_port_json_only.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(verilator_flags2=['--no-std', '--json-only', '--no-json-edit-nums'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.files_identical(out_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_port_xml.pl b/test_regress/t/t_var_port_xml.pl deleted file mode 100755 index fe03f41d4..000000000 --- a/test_regress/t/t_var_port_xml.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml"; - -compile( - verilator_flags2 => ['--no-std', '--xml-only'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -files_identical($out_filename, $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_var_port_xml.py b/test_regress/t/t_var_port_xml.py new file mode 100755 index 000000000..e24dca19d --- /dev/null +++ b/test_regress/t/t_var_port_xml.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +out_filename = test.obj_dir + "/V" + test.name + ".xml" + +test.compile(verilator_flags2=['--no-std', '--xml-only'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.files_identical(out_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_ref.pl b/test_regress/t/t_var_ref.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_var_ref.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_ref.py b/test_regress/t/t_var_ref.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_var_ref.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_ref_bad1.pl b/test_regress/t/t_var_ref_bad1.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_var_ref_bad1.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_ref_bad1.py b/test_regress/t/t_var_ref_bad1.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_var_ref_bad1.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_ref_bad2.pl b/test_regress/t/t_var_ref_bad2.pl deleted file mode 100755 index a60503a1f..000000000 --- a/test_regress/t/t_var_ref_bad2.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_ref_bad2.py b/test_regress/t/t_var_ref_bad2.py new file mode 100755 index 000000000..31228c9a7 --- /dev/null +++ b/test_regress/t/t_var_ref_bad2.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_ref_bad3.pl b/test_regress/t/t_var_ref_bad3.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_var_ref_bad3.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_ref_bad3.py b/test_regress/t/t_var_ref_bad3.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_var_ref_bad3.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_ref_noinline.pl b/test_regress/t/t_var_ref_noinline.pl deleted file mode 100755 index 8103b3c26..000000000 --- a/test_regress/t/t_var_ref_noinline.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -top_filename("t/t_var_ref.v"); - -scenarios(simulator => 1); - -compile( - v_flags2 => ['+define+T_NOINLINE'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_ref_noinline.py b/test_regress/t/t_var_ref_noinline.py new file mode 100755 index 000000000..f5064fa95 --- /dev/null +++ b/test_regress/t/t_var_ref_noinline.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +test.top_filename = "t/t_var_ref.v" + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=['+define+T_NOINLINE']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_ref_static.pl b/test_regress/t/t_var_ref_static.pl deleted file mode 100755 index a5846c699..000000000 --- a/test_regress/t/t_var_ref_static.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_ref_static.py b/test_regress/t/t_var_ref_static.py new file mode 100755 index 000000000..e33e10acf --- /dev/null +++ b/test_regress/t/t_var_ref_static.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_rsvd.pl b/test_regress/t/t_var_rsvd.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_var_rsvd.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_rsvd.py b/test_regress/t/t_var_rsvd.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_var_rsvd.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_rsvd_bad.pl b/test_regress/t/t_var_rsvd_bad.pl deleted file mode 100755 index a034e8fa8..000000000 --- a/test_regress/t/t_var_rsvd_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -top_filename("t/t_var_rsvd_port.v"); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_rsvd_bad.py b/test_regress/t/t_var_rsvd_bad.py new file mode 100755 index 000000000..113352b72 --- /dev/null +++ b/test_regress/t/t_var_rsvd_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_var_rsvd_port.v" + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_rsvd_port.pl b/test_regress/t/t_var_rsvd_port.pl deleted file mode 100755 index 76a08e9aa..000000000 --- a/test_regress/t/t_var_rsvd_port.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ["-Wno-SYMRSVDWORD"], - ); - -execute(); - -ok(1); -1; diff --git a/test_regress/t/t_var_rsvd_port.py b/test_regress/t/t_var_rsvd_port.py new file mode 100755 index 000000000..13c220107 --- /dev/null +++ b/test_regress/t/t_var_rsvd_port.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["-Wno-SYMRSVDWORD"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_sc_bv.pl b/test_regress/t/t_var_sc_bv.pl deleted file mode 100755 index 58d0b0d30..000000000 --- a/test_regress/t/t_var_sc_bv.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/t_var_sc_bv.cpp --sc -fno-inline"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_sc_bv.py b/test_regress/t/t_var_sc_bv.py new file mode 100755 index 000000000..fb4049cf1 --- /dev/null +++ b/test_regress/t/t_var_sc_bv.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--exe", test.pli_filename, "--sc -fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_set_link.pl b/test_regress/t/t_var_set_link.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_var_set_link.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_set_link.py b/test_regress/t/t_var_set_link.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_var_set_link.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_static.pl b/test_regress/t/t_var_static.pl deleted file mode 100755 index 433f5f6b3..000000000 --- a/test_regress/t/t_var_static.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['-Wno-IMPLICITSTATIC'], - ); - -execute( - all_run_flags => ['+plusarg=value'], - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_static.py b/test_regress/t/t_var_static.py new file mode 100755 index 000000000..df3c5c280 --- /dev/null +++ b/test_regress/t/t_var_static.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['-Wno-IMPLICITSTATIC']) + +test.execute(all_run_flags=['+plusarg=value']) + +test.passes() diff --git a/test_regress/t/t_var_static_assign_decl_bad.pl b/test_regress/t/t_var_static_assign_decl_bad.pl deleted file mode 100755 index dbc037440..000000000 --- a/test_regress/t/t_var_static_assign_decl_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_static_assign_decl_bad.py b/test_regress/t/t_var_static_assign_decl_bad.py new file mode 100755 index 000000000..efe8cc01c --- /dev/null +++ b/test_regress/t/t_var_static_assign_decl_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_static_param.pl b/test_regress/t/t_var_static_param.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_var_static_param.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_static_param.py b/test_regress/t/t_var_static_param.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_var_static_param.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_suggest_bad.pl b/test_regress/t/t_var_suggest_bad.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_var_suggest_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_suggest_bad.py b/test_regress/t/t_var_suggest_bad.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_var_suggest_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_tieout.pl b/test_regress/t/t_var_tieout.pl deleted file mode 100755 index ce81a9bb4..000000000 --- a/test_regress/t/t_var_tieout.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_tieout.py b/test_regress/t/t_var_tieout.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_var_tieout.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_top_struct.pl b/test_regress/t/t_var_top_struct.pl deleted file mode 100755 index 157d7a50b..000000000 --- a/test_regress/t/t_var_top_struct.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_top_struct.py b/test_regress/t/t_var_top_struct.py new file mode 100755 index 000000000..c3bd7274f --- /dev/null +++ b/test_regress/t/t_var_top_struct.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_var_types.pl b/test_regress/t/t_var_types.pl deleted file mode 100755 index d1d03f4d0..000000000 --- a/test_regress/t/t_var_types.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -$Self->{verilated_randReset} = 1; # allow checking if we initialize vars to zero only when needed - -compile( - verilator_flags2 => ["--x-assign 1"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_types.py b/test_regress/t/t_var_types.py new file mode 100755 index 000000000..9964558dd --- /dev/null +++ b/test_regress/t/t_var_types.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.verilated_randReset = 1 # allow checking if we initialize vars to zero only when needed + +test.compile(verilator_flags2=["--x-assign 1"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_types_bad.pl b/test_regress/t/t_var_types_bad.pl deleted file mode 100755 index d2715e7c7..000000000 --- a/test_regress/t/t_var_types_bad.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -$Self->{verilated_randReset} = 1; # allow checking if we initialize vars to zero only when needed - -lint( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_types_bad.py b/test_regress/t/t_var_types_bad.py new file mode 100755 index 000000000..8e9543a6c --- /dev/null +++ b/test_regress/t/t_var_types_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.verilated_randReset = 1 # allow checking if we initialize vars to zero only when needed + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_vec_sel.pl b/test_regress/t/t_var_vec_sel.pl deleted file mode 100755 index 13c6e2b71..000000000 --- a/test_regress/t/t_var_vec_sel.pl +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint(); - -ok(1); -1; diff --git a/test_regress/t/t_var_vec_sel.py b/test_regress/t/t_var_vec_sel.py new file mode 100755 index 000000000..c2d985114 --- /dev/null +++ b/test_regress/t/t_var_vec_sel.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_var_xref_bad.pl b/test_regress/t/t_var_xref_bad.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_var_xref_bad.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_var_xref_bad.py b/test_regress/t/t_var_xref_bad.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_var_xref_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_xref_gen.pl b/test_regress/t/t_var_xref_gen.pl deleted file mode 100755 index d862fcf2e..000000000 --- a/test_regress/t/t_var_xref_gen.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["--debug-check"], - ); - -ok(1); - -1; diff --git a/test_regress/t/t_var_xref_gen.py b/test_regress/t/t_var_xref_gen.py new file mode 100755 index 000000000..75684187a --- /dev/null +++ b/test_regress/t/t_var_xref_gen.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--debug-check"]) + +test.passes() diff --git a/test_regress/t/t_verilated_all.pl b/test_regress/t/t_verilated_all.pl deleted file mode 100755 index 7f7169908..000000000 --- a/test_regress/t/t_verilated_all.pl +++ /dev/null @@ -1,65 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vltmt => 1); - -my $root = ".."; - -compile( - # Can't use --coverage and --savable together, so cheat and compile inline - verilator_flags2 => ["--cc", - "--coverage-toggle --coverage-line --coverage-user", - "--trace --vpi ", - "--trace-threads 1", - $Self->have_coroutines ? "--timing" : "--no-timing -Wno-STMTDLY", - "--prof-exec", "--prof-pgo", - "$root/include/verilated_save.cpp"], - threads => 2 - ); - -execute( - all_run_flags => [" +verilator+prof+exec+file+/dev/null", - " +verilator+prof+vlt+file+/dev/null", - ], - ); - -my %hit; -foreach my $file (glob("$root/include/*.cpp $root/include/*.h")) { - $file =~ s!.*/!!; - - # This file isn't actually used by the runtime (though - # it might be in the future? hence it's under include/) - # It is used to build verilator. - if ($file =~ /verilated_unordered_set_map\.h/) { next; } - - print "NEED: $file\n" if $Self->{verbose}; - $hit{$file} = 0; -} -foreach my $dfile (glob("$Self->{obj_dir}/*.d")) { - my $wholefile = file_contents($dfile); - foreach my $file (split /\s+/, $wholefile) { - $file =~ s!.*/!!; - print "USED: $file\n" if $Self->{verbose}; - $hit{$file} = 1; - } -} - -foreach my $file (sort keys %hit) { - if (!$hit{$file} - && $file !~ /_sc/ - && $file !~ /_fst/ - && ($file !~ /_timing/ || $Self->have_coroutines) - && ($file !~ /_thread/)) { - error("Include file not covered by t_verilated_all test: ", $file); - } -} - -ok(1); -1; diff --git a/test_regress/t/t_verilated_all.py b/test_regress/t/t_verilated_all.py new file mode 100755 index 000000000..14301bd7b --- /dev/null +++ b/test_regress/t/t_verilated_all.py @@ -0,0 +1,53 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vltmt') + +root = ".." + +if not os.path.exists(root + "/.git"): + test.skip("Not in a git repository") + +test.compile( + # Can't use --coverage and --savable together, so cheat and compile inline + verilator_flags2=[ + "--cc", "--coverage-toggle --coverage-line --coverage-user", + "--trace --vpi ", "--trace-threads 1", + ("--timing" if test.have_coroutines else "--no-timing -Wno-STMTDLY"), "--prof-exec", + "--prof-pgo", root + "/include/verilated_save.cpp" + ], + threads=2) + +test.execute( + all_run_flags=[" +verilator+prof+exec+file+/dev/null", " +verilator+prof+vlt+file+/dev/null"]) + +hit = {} +for filename in (test.glob_some(root + "/include/*.cpp") + test.glob_some(root + "/include/*.h")): + filename = os.path.basename(filename) + if test.verbose: + print("NEED: " + filename) + hit[filename] = False + +for dfile in test.glob_some(test.obj_dir + "/*.d"): + wholefile = test.file_contents(dfile) + for filename in wholefile.split(): + filename = os.path.basename(filename) + if test.verbose: + print("USED: " + filename) + hit[filename] = True + +for filename in sorted(hit.keys()): + if (not hit[filename] and not re.search(r'_sc', filename) and not re.search(r'_fst', filename) + and not re.search(r'_thread', filename) + and (not re.search(r'_timing', filename) or test.have_coroutines)): + test.error("Include file not covered by t_verilated_all test: ", filename) + +test.passes() diff --git a/test_regress/t/t_verilated_all_newest.pl b/test_regress/t/t_verilated_all_newest.pl deleted file mode 100755 index 9e7f35a66..000000000 --- a/test_regress/t/t_verilated_all_newest.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_verilated_all.v"); - -my $root = ".."; - -compile( - # Can't use --coverage and --savable together, so cheat and compile inline - verilator_flags2 => ["--cc --coverage-toggle --coverage-line --coverage-user --trace --prof-exec --prof-pgo --vpi $root/include/verilated_save.cpp", - $Self->have_coroutines ? "--timing" : "--no-timing -Wno-STMTDLY"], - make_flags => 'DRIVER_STD=newest', - ); - -execute( - all_run_flags => [" +verilator+prof+exec+file+/dev/null", - " +verilator+prof+vlt+file+/dev/null", - ], - ); - -ok(1); -1; diff --git a/test_regress/t/t_verilated_all_newest.py b/test_regress/t/t_verilated_all_newest.py new file mode 100755 index 000000000..3a22434c1 --- /dev/null +++ b/test_regress/t/t_verilated_all_newest.py @@ -0,0 +1,29 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_verilated_all.v" + +root = ".." + +test.compile( + # Can't use --coverage and --savable together, so cheat and compile inline + verilator_flags2=[ + "--cc --coverage-toggle --coverage-line --coverage-user --trace --prof-exec --prof-pgo --vpi " + + root + "/include/verilated_save.cpp", + ("--timing" if test.have_coroutines else "--no-timing -Wno-STMTDLY") + ], + make_flags=['DRIVER_STD=newest']) + +test.execute( + all_run_flags=[" +verilator+prof+exec+file+/dev/null", " +verilator+prof+vlt+file+/dev/null"]) + +test.passes() diff --git a/test_regress/t/t_verilated_all_oldest.pl b/test_regress/t/t_verilated_all_oldest.pl deleted file mode 100755 index 103e2e197..000000000 --- a/test_regress/t/t_verilated_all_oldest.pl +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(dist => 1); - -# This test now does nothing, because using DRIVER_STD=oldest tends to blow up glibc. -# Support for DRIVER_STD=oldest was removed from makefiles. This file remains for commentary. - -ok(1); -1; diff --git a/test_regress/t/t_verilated_all_oldest.py b/test_regress/t/t_verilated_all_oldest.py new file mode 100755 index 000000000..c07c374b9 --- /dev/null +++ b/test_regress/t/t_verilated_all_oldest.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +# This test now does nothing, because using DRIVER_STD=oldest tends to blow up glibc. +# Support for DRIVER_STD=oldest was removed from makefiles. This file remains for commentary. + +test.passes() diff --git a/test_regress/t/t_verilated_debug.pl b/test_regress/t/t_verilated_debug.pl deleted file mode 100755 index ab72415ef..000000000 --- a/test_regress/t/t_verilated_debug.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -$Self->{verilated_debug} = 1; - -compile( - verilator_flags2 => [], - ); - -execute( - ); - -if (!$Self->{vltmt}) { # vltmt output may vary between thread exec order - files_identical("$Self->{obj_dir}/vlt_sim.log", $Self->{golden_filename}, "logfile"); -} - -ok(1); -1; diff --git a/test_regress/t/t_verilated_debug.py b/test_regress/t/t_verilated_debug.py new file mode 100755 index 000000000..221a3478d --- /dev/null +++ b/test_regress/t/t_verilated_debug.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.verilated_debug = True + +test.compile(verilator_flags2=[]) + +test.execute() + +if not test.vltmt: # vltmt output may vary between thread exec order + test.files_identical(test.obj_dir + "/vlt_sim.log", test.golden_filename, "logfile") + +test.passes() diff --git a/test_regress/t/t_verilated_header.pl b/test_regress/t/t_verilated_header.pl deleted file mode 100755 index dd1a112e6..000000000 --- a/test_regress/t/t_verilated_header.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator_st => 1); - -compile( - verilator_flags2 => ["+incdir+$ENV{VERILATOR_ROOT}/include"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_verilated_header.py b/test_regress/t/t_verilated_header.py new file mode 100755 index 000000000..64fff6852 --- /dev/null +++ b/test_regress/t/t_verilated_header.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') + +test.compile(verilator_flags2=["+incdir+" + os.environ["VERILATOR_ROOT"] + "/include"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_verilated_threaded.pl b/test_regress/t/t_verilated_threaded.pl deleted file mode 100755 index 110ed26f6..000000000 --- a/test_regress/t/t_verilated_threaded.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vltmt => 1); - -top_filename("t/t_verilated_all.v"); - -my $root = ".."; - -compile( - # Can't use --coverage and --savable together, so cheat and compile inline - verilator_flags2 => ["--cc --coverage-toggle --coverage-line --coverage-user --trace --vpi $root/include/verilated_save.cpp", - $Self->have_coroutines ? "--timing" : "--no-timing -Wno-STMTDLY"], - threads => 1 - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_verilated_threaded.py b/test_regress/t/t_verilated_threaded.py new file mode 100755 index 000000000..af80be73f --- /dev/null +++ b/test_regress/t/t_verilated_threaded.py @@ -0,0 +1,28 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vltmt') +test.top_filename = "t/t_verilated_all.v" + +root = ".." + +test.compile( + # Can't use --coverage and --savable together, so cheat and compile inline + verilator_flags2=[ + "--cc --coverage-toggle --coverage-line --coverage-user --trace --vpi " + root + + "/include/verilated_save.cpp", + ("--timing" if test.have_coroutines else "--no-timing -Wno-STMTDLY") + ], + threads=1) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_virtual_interface_method.pl b/test_regress/t/t_virtual_interface_method.pl deleted file mode 100755 index 8c8dcd0d4..000000000 --- a/test_regress/t/t_virtual_interface_method.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["--binary"], - verilator_make_gmake => 0, - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_virtual_interface_method.py b/test_regress/t/t_virtual_interface_method.py new file mode 100755 index 000000000..d2e0fe791 --- /dev/null +++ b/test_regress/t/t_virtual_interface_method.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["--binary"], verilator_make_gmake=False) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_virtual_interface_method_bad.pl b/test_regress/t/t_virtual_interface_method_bad.pl deleted file mode 100755 index 85114ac5d..000000000 --- a/test_regress/t/t_virtual_interface_method_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only --language 1800-2017"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_virtual_interface_method_bad.py b/test_regress/t/t_virtual_interface_method_bad.py new file mode 100755 index 000000000..54f436672 --- /dev/null +++ b/test_regress/t/t_virtual_interface_method_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only --language 1800-2017"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_vl_assign_sbw.pl b/test_regress/t/t_vl_assign_sbw.pl deleted file mode 100755 index f958c8686..000000000 --- a/test_regress/t/t_vl_assign_sbw.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe --pins-sc-biguint --sc $Self->{t_dir}/t_vl_assign_sbw.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_vl_assign_sbw.py b/test_regress/t/t_vl_assign_sbw.py new file mode 100755 index 000000000..1a06f784b --- /dev/null +++ b/test_regress/t/t_vl_assign_sbw.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--exe --pins-sc-biguint --sc", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_vlcov_debugi.pl b/test_regress/t/t_vlcov_debugi.pl deleted file mode 100755 index 5e6046a73..000000000 --- a/test_regress/t/t_vlcov_debugi.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(dist => 1); - -foreach my $basename ("t_vlcov_data_a.dat", - "t_vlcov_data_b.dat", - "t_vlcov_data_c.dat", - "t_vlcov_data_d.dat", - ) { - run(cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator_coverage", - "t/${basename}", - "--debug", - "--debugi 9", - ], - tee => $Self->{verbose}, - verilator_run => 1, - ); -} - -ok(1); -1; diff --git a/test_regress/t/t_vlcov_debugi.py b/test_regress/t/t_vlcov_debugi.py new file mode 100755 index 000000000..b3d310b71 --- /dev/null +++ b/test_regress/t/t_vlcov_debugi.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +for basename in [ + "t_vlcov_data_a.dat", "t_vlcov_data_b.dat", "t_vlcov_data_c.dat", "t_vlcov_data_d.dat" +]: + test.run(cmd=[ + os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "t/" + basename, "--debug", + "--debugi 9" + ], + tee=test.verbose, + verilator_run=True) + +test.passes() diff --git a/test_regress/t/t_vlcov_flag_invalid_bad.pl b/test_regress/t/t_vlcov_flag_invalid_bad.pl deleted file mode 100755 index 18ad2d42b..000000000 --- a/test_regress/t/t_vlcov_flag_invalid_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -run(cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator_coverage", '--invalid-dash'], - logfile => $Self->{run_log_filename}, - fails => 1, - expect_filename => $Self->{golden_filename}, - verilator_run => 1, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_vlcov_flag_invalid_bad.py b/test_regress/t/t_vlcov_flag_invalid_bad.py new file mode 100755 index 000000000..8e3fec647 --- /dev/null +++ b/test_regress/t/t_vlcov_flag_invalid_bad.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.run(cmd=[os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", '--invalid-dash'], + logfile=test.run_log_filename, + fails=True, + expect_filename=test.golden_filename, + verilator_run=True) + +test.passes() diff --git a/test_regress/t/t_vlcov_info.pl b/test_regress/t/t_vlcov_info.pl deleted file mode 100755 index dbb8bb48f..000000000 --- a/test_regress/t/t_vlcov_info.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(dist => 1); - -run(cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator_coverage", - "--write-info", "$Self->{obj_dir}/coverage.info", - "t/t_vlcov_data_a.dat", - "t/t_vlcov_data_b.dat", - "t/t_vlcov_data_c.dat", - "t/t_vlcov_data_d.dat", - ], - verilator_run => 1, - ); - -files_identical("$Self->{obj_dir}/coverage.info", "t/" . $Self->{name} . ".info.out"); - -ok(1); -1; diff --git a/test_regress/t/t_vlcov_info.py b/test_regress/t/t_vlcov_info.py new file mode 100755 index 000000000..19def3282 --- /dev/null +++ b/test_regress/t/t_vlcov_info.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +test.run(cmd=[ + os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--write-info", + test.obj_dir + "/coverage.info", "t/t_vlcov_data_a.dat", "t/t_vlcov_data_b.dat", + "t/t_vlcov_data_c.dat", "t/t_vlcov_data_d.dat" +], + verilator_run=True) + +test.files_identical(test.obj_dir + "/coverage.info", "t/" + test.name + ".info.out") + +test.passes() diff --git a/test_regress/t/t_vlcov_merge.pl b/test_regress/t/t_vlcov_merge.pl deleted file mode 100755 index 0671dde4b..000000000 --- a/test_regress/t/t_vlcov_merge.pl +++ /dev/null @@ -1,33 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(dist => 1); - -run(cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator_coverage", - "--no-unlink", "--nounlink", - "--write", "$Self->{obj_dir}/coverage.dat", - "t/t_vlcov_data_a.dat", - "t/t_vlcov_data_b.dat", - "t/t_vlcov_data_c.dat", - "t/t_vlcov_data_d.dat", - ], - verilator_run => 1, - ); - -# Not deleted e.g. parsed --no-unlink properly -files_identical("$Self->{t_dir}/t_vlcov_data_a.dat", - "$Self->{t_dir}/t_vlcov_data_a.dat"); - -# Older clib's didn't properly sort maps, but the coverage data doesn't -# really care about ordering. So avoid false failures by sorting. -files_identical_sorted("$Self->{obj_dir}/coverage.dat", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_vlcov_merge.py b/test_regress/t/t_vlcov_merge.py new file mode 100755 index 000000000..271a8d1c7 --- /dev/null +++ b/test_regress/t/t_vlcov_merge.py @@ -0,0 +1,32 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +test.run(cmd=[ + os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", + "--no-unlink", + "--nounlink", + "--write", + test.obj_dir + "/coverage.dat", + "t/t_vlcov_data_a.dat", + "t/t_vlcov_data_b.dat", + "t/t_vlcov_data_c.dat", + "t/t_vlcov_data_d.dat", +], + verilator_run=True) + +# Not deleted e.g. parsed --no-unlink properlytest.files_identical(test.t_dir + "/t_vlcov_data_a.dat", test.t_dir + "/t_vlcov_data_a.dat") + +# Older clib's didn't properly sort maps, but the coverage data doesn't +# really care about ordering. So avoid false failures by sorting.test.files_identical_sorted(test.obj_dir + "/coverage.dat", test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_vlcov_nfound_bad.pl b/test_regress/t/t_vlcov_nfound_bad.pl deleted file mode 100755 index 6a4a9be42..000000000 --- a/test_regress/t/t_vlcov_nfound_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(dist => 1); - -run(fails => 1, - cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator_coverage", - "t/t_NOT_FOUND",], - logfile => $Self->{run_log_filename}, - expect_filename => $Self->{golden_filename}, - verilator_run => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_vlcov_nfound_bad.py b/test_regress/t/t_vlcov_nfound_bad.py new file mode 100755 index 000000000..d435f38ee --- /dev/null +++ b/test_regress/t/t_vlcov_nfound_bad.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +test.run(fails=True, + cmd=[os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "t/t_NOT_FOUND"], + logfile=test.run_log_filename, + expect_filename=test.golden_filename, + verilator_run=True) + +test.passes() diff --git a/test_regress/t/t_vlcov_rank.pl b/test_regress/t/t_vlcov_rank.pl deleted file mode 100755 index 703de90d5..000000000 --- a/test_regress/t/t_vlcov_rank.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(dist => 1); - -run(cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator_coverage", - "--rank", - "t/t_vlcov_data_a.dat", - "t/t_vlcov_data_b.dat", - "t/t_vlcov_data_c.dat", - "t/t_vlcov_data_d.dat", - ], - logfile => "$Self->{obj_dir}/vlcov.log", - tee => 0, - verilator_run => 1, - ); - -files_identical("$Self->{obj_dir}/vlcov.log", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_vlcov_rank.py b/test_regress/t/t_vlcov_rank.py new file mode 100755 index 000000000..6013b047c --- /dev/null +++ b/test_regress/t/t_vlcov_rank.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +test.run(cmd=[ + os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--rank", "t/t_vlcov_data_a.dat", + "t/t_vlcov_data_b.dat", "t/t_vlcov_data_c.dat", "t/t_vlcov_data_d.dat" +], + logfile=test.obj_dir + "/vlcov.log", + tee=False, + verilator_run=True) + +test.files_identical(test.obj_dir + "/vlcov.log", test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_vlcov_rewrite.pl b/test_regress/t/t_vlcov_rewrite.pl deleted file mode 100755 index 0affb5b9c..000000000 --- a/test_regress/t/t_vlcov_rewrite.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(dist => 1); - -foreach my $basename ("t_vlcov_data_a.dat", - "t_vlcov_data_b.dat", - "t_vlcov_data_c.dat", - "t_vlcov_data_d.dat", - ) { - run(cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator_coverage", - "t/${basename}", - "--write", "$Self->{obj_dir}/${basename}" - ], - tee => 0, - verilator_run => 1, - ); - files_identical("$Self->{obj_dir}/${basename}", "t/${basename}"); -} - -ok(1); -1; diff --git a/test_regress/t/t_vlcov_rewrite.py b/test_regress/t/t_vlcov_rewrite.py new file mode 100755 index 000000000..91fdfa1d0 --- /dev/null +++ b/test_regress/t/t_vlcov_rewrite.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + +for basename in [ + "t_vlcov_data_a.dat", "t_vlcov_data_b.dat", "t_vlcov_data_c.dat", "t_vlcov_data_d.dat" +]: + test.run(cmd=[ + os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "t/" + basename, "--write", + test.obj_dir + "/" + basename + ], + tee=False, + verilator_run=True) + + test.files_identical(test.obj_dir + "/" + basename, "t/" + basename) + +test.passes() diff --git a/test_regress/t/t_vlcov_unlink.pl b/test_regress/t/t_vlcov_unlink.pl deleted file mode 100755 index e2a054967..000000000 --- a/test_regress/t/t_vlcov_unlink.pl +++ /dev/null @@ -1,32 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -use File::Copy; - -scenarios(dist => 1); - -my $tmp = "$Self->{obj_dir}/copied.dat"; -File::Copy::copy("$Self->{t_dir}/t_vlcov_data_a.dat", $tmp); - -run(cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator_coverage", - "--unlink", - $tmp, - "--write", "$Self->{obj_dir}/output.dat"], - verilator_run => 1, - ); - -files_identical("$Self->{obj_dir}/output.dat", "t/t_vlcov_data_a.dat"); - -# --unlink should have removed it -!-r $tmp or error("Not unlinked"); - -ok(1); - -1; diff --git a/test_regress/t/t_vlcov_unlink.py b/test_regress/t/t_vlcov_unlink.py new file mode 100755 index 000000000..90f9428f4 --- /dev/null +++ b/test_regress/t/t_vlcov_unlink.py @@ -0,0 +1,30 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import shutil + +test.scenarios('dist') + +tmp = test.obj_dir + "/copied.dat" +shutil.copy(test.t_dir + "/t_vlcov_data_a.dat", tmp) + +test.run(cmd=[ + os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--unlink", tmp, "--write", + test.obj_dir + "/output.dat" +], + verilator_run=True) + +test.files_identical(test.obj_dir + "/output.dat", "t/t_vlcov_data_a.dat") + +# --unlink should have removed it +if os.path.exists(tmp): + test.error("Wan't unlinked") + +test.passes() diff --git a/test_regress/t/t_vlt_match_error_1.pl b/test_regress/t/t_vlt_match_error_1.pl deleted file mode 100755 index 7de7b8d1b..000000000 --- a/test_regress/t/t_vlt_match_error_1.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder and Ethan Sifferman. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_vlt_match_error.v"); - -lint( - verilator_flags2 => ["-DT_VLT_MATCH_ERROR_1 --lint-only -Wall t/t_vlt_match_error.v t/t_vlt_match_error.vlt"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_vlt_match_error_1.py b/test_regress/t/t_vlt_match_error_1.py new file mode 100755 index 000000000..14c18fda5 --- /dev/null +++ b/test_regress/t/t_vlt_match_error_1.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_vlt_match_error.v" + +test.lint(verilator_flags2=[ + "-DT_VLT_MATCH_ERROR_1 --lint-only -Wall t/t_vlt_match_error.v t/t_vlt_match_error.vlt" +], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_vlt_match_error_2.pl b/test_regress/t/t_vlt_match_error_2.pl deleted file mode 100755 index 0e046489a..000000000 --- a/test_regress/t/t_vlt_match_error_2.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder and Ethan Sifferman. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_vlt_match_error.v"); - -lint( - verilator_flags2 => ["-DT_VLT_MATCH_ERROR_2 --lint-only -Wall t/t_vlt_match_error.v t/t_vlt_match_error.vlt"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_vlt_match_error_2.py b/test_regress/t/t_vlt_match_error_2.py new file mode 100755 index 000000000..98c8b2327 --- /dev/null +++ b/test_regress/t/t_vlt_match_error_2.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_vlt_match_error.v" + +test.lint(verilator_flags2=[ + "-DT_VLT_MATCH_ERROR_2 --lint-only -Wall t/t_vlt_match_error.v t/t_vlt_match_error.vlt" +], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_vlt_match_error_3.pl b/test_regress/t/t_vlt_match_error_3.pl deleted file mode 100755 index 43093cc2e..000000000 --- a/test_regress/t/t_vlt_match_error_3.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder and Ethan Sifferman. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_vlt_match_error.v"); - -lint( - verilator_flags2 => ["-DT_VLT_MATCH_ERROR_3 --lint-only -Wall t/t_vlt_match_error.v t/t_vlt_match_error.vlt"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_vlt_match_error_3.py b/test_regress/t/t_vlt_match_error_3.py new file mode 100755 index 000000000..53a1dae32 --- /dev/null +++ b/test_regress/t/t_vlt_match_error_3.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_vlt_match_error.v" + +test.lint(verilator_flags2=[ + "-DT_VLT_MATCH_ERROR_3 --lint-only -Wall t/t_vlt_match_error.v t/t_vlt_match_error.vlt" +], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_vlt_syntax_bad.pl b/test_regress/t/t_vlt_syntax_bad.pl deleted file mode 100755 index 5d79360fb..000000000 --- a/test_regress/t/t_vlt_syntax_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["t/t_vlt_syntax_bad.vlt"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_vlt_syntax_bad.py b/test_regress/t/t_vlt_syntax_bad.py new file mode 100755 index 000000000..90b3aecba --- /dev/null +++ b/test_regress/t/t_vlt_syntax_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["t/t_vlt_syntax_bad.vlt"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_vlt_timing.pl b/test_regress/t/t_vlt_timing.pl deleted file mode 100755 index 903cb26e0..000000000 --- a/test_regress/t/t_vlt_timing.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -top_filename("t/t_timing_off.v"); - -compile( - verilator_flags2 => ["--exe --main --timing t/t_vlt_timing.vlt"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_vlt_timing.py b/test_regress/t/t_vlt_timing.py new file mode 100755 index 000000000..0feac9429 --- /dev/null +++ b/test_regress/t/t_vlt_timing.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_timing_off.v" + +test.compile(verilator_flags2=["--exe --main --timing t/t_vlt_timing.vlt"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_vlt_warn.pl b/test_regress/t/t_vlt_warn.pl deleted file mode 100755 index 32163cf4e..000000000 --- a/test_regress/t/t_vlt_warn.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only -Wall t/t_vlt_warn.vlt"], - ); - -ok(1); -1; diff --git a/test_regress/t/t_vlt_warn.py b/test_regress/t/t_vlt_warn.py new file mode 100755 index 000000000..58ef49915 --- /dev/null +++ b/test_regress/t/t_vlt_warn.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only -Wall t/t_vlt_warn.vlt"]) + +test.passes() diff --git a/test_regress/t/t_vlt_warn_bad.pl b/test_regress/t/t_vlt_warn_bad.pl deleted file mode 100755 index 43047c39e..000000000 --- a/test_regress/t/t_vlt_warn_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_vlt_warn.v"); - -lint( - verilator_flags2 => ["--lint-only t/t_vlt_warn_bad.vlt"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_vlt_warn_bad.py b/test_regress/t/t_vlt_warn_bad.py new file mode 100755 index 000000000..b55f59369 --- /dev/null +++ b/test_regress/t/t_vlt_warn_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_vlt_warn.v" + +test.lint(verilator_flags2=["--lint-only t/t_vlt_warn_bad.vlt"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_vlt_warn_ecode_bad.pl b/test_regress/t/t_vlt_warn_ecode_bad.pl deleted file mode 100755 index ebf322c30..000000000 --- a/test_regress/t/t_vlt_warn_ecode_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_vlt_warn.v"); - -lint( - verilator_flags2 => ["--lint-only t/t_vlt_warn_ecode_bad.vlt"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_vlt_warn_ecode_bad.py b/test_regress/t/t_vlt_warn_ecode_bad.py new file mode 100755 index 000000000..28f9b6683 --- /dev/null +++ b/test_regress/t/t_vlt_warn_ecode_bad.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_vlt_warn.v" + +test.lint(verilator_flags2=["--lint-only t/t_vlt_warn_ecode_bad.vlt"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_vlt_warn_file_bad.pl b/test_regress/t/t_vlt_warn_file_bad.pl deleted file mode 100755 index 83d974461..000000000 --- a/test_regress/t/t_vlt_warn_file_bad.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2008 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - # See also t/t_lint_warn_incfile1_bad - # See also t/t_lint_warn_incfile2_bad - verilator_flags2 => ["--no-std t/t_vlt_warn_file_bad.vlt"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_vlt_warn_file_bad.py b/test_regress/t/t_vlt_warn_file_bad.py new file mode 100755 index 000000000..35484f938 --- /dev/null +++ b/test_regress/t/t_vlt_warn_file_bad.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint( + # See also t/t_lint_warn_incfile1_bad + # See also t/t_lint_warn_incfile2_bad + verilator_flags2=["--no-std t/t_vlt_warn_file_bad.vlt"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_vpi_cb_iter.pl b/test_regress/t/t_vpi_cb_iter.pl deleted file mode 100755 index aa7b7b2d3..000000000 --- a/test_regress/t/t_vpi_cb_iter.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder and Marlon James. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe --vpi $Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_cb_iter.py b/test_regress/t/t_vpi_cb_iter.py new file mode 100755 index 000000000..663e45330 --- /dev/null +++ b/test_regress/t/t_vpi_cb_iter.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--exe --vpi", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_vpi_const_type.pl b/test_regress/t/t_vpi_const_type.pl deleted file mode 100755 index f0844224f..000000000 --- a/test_regress/t/t_vpi_const_type.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_top_shell => 0, - make_main => 0, - make_pli => 1, - verilator_flags2 => ["--exe --vpi --no-l2name $Self->{t_dir}/t_vpi_const_type.cpp"], - ); - -execute( - use_libvpi => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_const_type.py b/test_regress/t/t_vpi_const_type.py new file mode 100755 index 000000000..61cf61c9e --- /dev/null +++ b/test_regress/t/t_vpi_const_type.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_top_shell=False, + make_main=False, + make_pli=True, + verilator_flags2=["--exe --vpi --no-l2name", test.pli_filename]) + +test.execute(use_libvpi=True) + +test.passes() diff --git a/test_regress/t/t_vpi_dump.pl b/test_regress/t/t_vpi_dump.pl deleted file mode 100755 index 63872e680..000000000 --- a/test_regress/t/t_vpi_dump.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_top_shell => 0, - make_main => 0, - make_pli => 1, - iv_flags2 => ["-g2005-sv"], - verilator_flags2 => ["--exe --vpi --public-flat-rw --no-l2name $Self->{t_dir}/t_vpi_dump.cpp $Self->{t_dir}/TestVpiMain.cpp"], - make_flags => 'CPPFLAGS_ADD=-DVL_NO_LEGACY', - ); - -execute( - use_libvpi => 1, - expect_filename => $Self->{golden_filename}, - xrun_run_expect_filename => ($Self->{golden_filename} =~ s/\.out$/.xrun.out/r), - iv_run_expect_filename => ($Self->{golden_filename} =~ s/\.out$/.iv.out/r), - ); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_dump.py b/test_regress/t/t_vpi_dump.py new file mode 100755 index 000000000..6a54e966f --- /dev/null +++ b/test_regress/t/t_vpi_dump.py @@ -0,0 +1,29 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_top_shell=False, + make_main=False, + make_pli=True, + iv_flags2=["-g2005-sv"], + verilator_flags2=[ + "--exe --vpi --public-flat-rw --no-l2name", test.pli_filename, + test.t_dir + "/TestVpiMain.cpp" + ], + make_flags=['CPPFLAGS_ADD=-DVL_NO_LEGACY']) + +test.execute(use_libvpi=True, + expect_filename=test.golden_filename, + xrun_run_expect_filename=re.sub(r'\.out$', '.xrun.out', test.golden_filename), + iv_run_expect_filename=re.sub(r'\.out$', '.iv.out', test.golden_filename)) + +test.passes() diff --git a/test_regress/t/t_vpi_dump_missing_scopes.pl b/test_regress/t/t_vpi_dump_missing_scopes.pl deleted file mode 100755 index d42aaae80..000000000 --- a/test_regress/t/t_vpi_dump_missing_scopes.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_top_shell => 0, - make_main => 0, - make_pli => "t_vpi_dump.cpp", - iv_flags2 => ["-g2005-sv"], - verilator_flags2 => ["--exe --vpi --public-flat-rw --no-l2name $Self->{t_dir}/t_vpi_dump.cpp $Self->{t_dir}/TestVpiMain.cpp"], - make_flags => 'CPPFLAGS_ADD=-DVL_NO_LEGACY', - ); - -execute( - use_libvpi => 1, - expect_filename => $Self->{golden_filename}, - xrun_run_expect_filename => ($Self->{golden_filename} =~ s/\.out$/.xrun.out/r), - iv_run_expect_filename => ($Self->{golden_filename} =~ s/\.out$/.iv.out/r), - ); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_dump_missing_scopes.py b/test_regress/t/t_vpi_dump_missing_scopes.py new file mode 100755 index 000000000..6c016e888 --- /dev/null +++ b/test_regress/t/t_vpi_dump_missing_scopes.py @@ -0,0 +1,30 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.pli_filename = "t/t_vpi_dump.cpp" + +test.compile(make_top_shell=False, + make_main=False, + make_pli=True, + iv_flags2=["-g2005-sv"], + verilator_flags2=[ + "--exe --vpi --public-flat-rw --no-l2name", test.pli_filename, + test.t_dir + "/TestVpiMain.cpp" + ], + make_flags=['CPPFLAGS_ADD=-DVL_NO_LEGACY']) + +test.execute(use_libvpi=True, + expect_filename=test.golden_filename, + xrun_run_expect_filename=re.sub(r'\.out$', '.xrun.out', test.golden_filename), + iv_run_expect_filename=re.sub(r'\.out$', '.iv.out', test.golden_filename)) + +test.passes() diff --git a/test_regress/t/t_vpi_escape.pl b/test_regress/t/t_vpi_escape.pl deleted file mode 100755 index 0a2b1efef..000000000 --- a/test_regress/t/t_vpi_escape.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -pli_filename("t_vpi_escape.cpp"); -compile( - make_top_shell => 0, - make_main => 0, - make_pli => 1, - sim_time => 100, - iv_flags2 => ["-g2005-sv -D USE_VPI_NOT_DPI -DWAVES"], - v_flags2 => ["+define+USE_VPI_NOT_DPI"], - verilator_flags2 => ["--exe --vpi --no-l2name --public-flat-rw $Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - # run_env => "VPI_TRACE=" . Cwd::getcwd() . "/$Self->{obj_dir}/$Self->{name}_vpi.log", - # run_env => "VPI_TRACE=/tmp/$Self->{name}_vpi.log", - use_libvpi => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_escape.py b/test_regress/t/t_vpi_escape.py new file mode 100755 index 000000000..e216188d9 --- /dev/null +++ b/test_regress/t/t_vpi_escape.py @@ -0,0 +1,28 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.pli_filename = "t/t_vpi_escape.cpp" + +test.compile(make_top_shell=False, + make_main=False, + make_pli=True, + sim_time=100, + iv_flags2=["-g2005-sv -D USE_VPI_NOT_DPI -DWAVES"], + v_flags2=["+define+USE_VPI_NOT_DPI"], + verilator_flags2=["--exe --vpi --no-l2name --public-flat-rw", test.pli_filename]) + +test.execute( + # run_env = "VPI_TRACE=" . Cwd::getcwd() . "/" + test.obj_dir + "/" + test.name + "_vpi.log", + # run_env = "VPI_TRACE=/tmp/"+test.name+"_vpi.log", + use_libvpi=True) + +test.passes() diff --git a/test_regress/t/t_vpi_finish.pl b/test_regress/t/t_vpi_finish.pl deleted file mode 100755 index f23494a33..000000000 --- a/test_regress/t/t_vpi_finish.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["t/t_vpi_finish_c.cpp"], - verilator_flags2 => ["--vpi"], - ); - -execute( - ); - -ok(1); - -1; diff --git a/test_regress/t/t_vpi_finish.py b/test_regress/t/t_vpi_finish.py new file mode 100755 index 000000000..34a4cc6f1 --- /dev/null +++ b/test_regress/t/t_vpi_finish.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["t/t_vpi_finish_c.cpp"], verilator_flags2=["--vpi"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_vpi_get.pl b/test_regress/t/t_vpi_get.pl deleted file mode 100755 index ffc7c5cff..000000000 --- a/test_regress/t/t_vpi_get.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe --vpi --no-l2name $Self->{t_dir}/t_vpi_get.cpp"], - make_pli => 1, - iv_flags2 => ["-g2005-sv -D USE_VPI_NOT_DPI"], - v_flags2 => ["+define+USE_VPI_NOT_DPI +define+VERILATOR_COMMENTS"], -); - -execute( - use_libvpi => 1, -); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_get.py b/test_regress/t/t_vpi_get.py new file mode 100755 index 000000000..9f7ed1832 --- /dev/null +++ b/test_regress/t/t_vpi_get.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_top_shell=False, + make_main=False, + make_pli=True, + verilator_flags2=["--exe --vpi --no-l2name", test.pli_filename], + iv_flags2=["-g2005-sv -D USE_VPI_NOT_DPI"], + v_flags2=["+define+USE_VPI_NOT_DPI +define+VERILATOR_COMMENTS"]) + +test.execute(use_libvpi=True) + +test.passes() diff --git a/test_regress/t/t_vpi_get_public_rw_switch.pl b/test_regress/t/t_vpi_get_public_rw_switch.pl deleted file mode 100755 index f3b80b49d..000000000 --- a/test_regress/t/t_vpi_get_public_rw_switch.pl +++ /dev/null @@ -1,33 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -vm_prefix("Vt_vpi_get"); -top_filename("t/t_vpi_get.v"); -pli_filename("t_vpi_get.cpp"); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe --vpi" - . " --public-flat-rw --prefix Vt_vpi_get --no-l2name" - . " $Self->{t_dir}/t_vpi_get.cpp"], - make_pli => 1, - iv_flags2 => ["-g2005-sv -D USE_VPI_NOT_DPI"], - v_flags2 => ["+define+USE_VPI_NOT_DPI"], - ); - -execute( - use_libvpi => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_get_public_rw_switch.py b/test_regress/t/t_vpi_get_public_rw_switch.py new file mode 100755 index 000000000..88e7cd71c --- /dev/null +++ b/test_regress/t/t_vpi_get_public_rw_switch.py @@ -0,0 +1,29 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.vm_prefix = "Vt_vpi_get" +test.top_filename = "t/t_vpi_get.v" +test.pli_filename = "t/t_vpi_get.cpp" + +test.compile(make_top_shell=False, + make_main=False, + make_pli=True, + verilator_flags2=[ + "--exe --vpi --public-flat-rw --prefix Vt_vpi_get --no-l2name", + test.t_dir + "/t_vpi_get.cpp" + ], + iv_flags2=["-g2005-sv -D USE_VPI_NOT_DPI"], + v_flags2=["+define+USE_VPI_NOT_DPI"]) + +test.execute(use_libvpi=True) + +test.passes() diff --git a/test_regress/t/t_vpi_memory.pl b/test_regress/t/t_vpi_memory.pl deleted file mode 100755 index d0eaba406..000000000 --- a/test_regress/t/t_vpi_memory.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_top_shell => 0, - make_main => 0, - make_pli => 1, - iv_flags2 => ["-g2005-sv -D USE_VPI_NOT_DPI"], - v_flags2 => ["+define+USE_VPI_NOT_DPI"], - verilator_flags2 => ["--exe --vpi --no-l2name $Self->{t_dir}/t_vpi_memory.cpp"], - ); - -execute( - use_libvpi => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_memory.py b/test_regress/t/t_vpi_memory.py new file mode 100755 index 000000000..31a4ce4b1 --- /dev/null +++ b/test_regress/t/t_vpi_memory.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_top_shell=False, + make_main=False, + make_pli=True, + iv_flags2=["-g2005-sv -D USE_VPI_NOT_DPI"], + v_flags2=["+define+USE_VPI_NOT_DPI"], + verilator_flags2=["--exe --vpi --no-l2name", test.pli_filename]) + +test.execute(use_libvpi=True) + +test.passes() diff --git a/test_regress/t/t_vpi_module.pl b/test_regress/t/t_vpi_module.pl deleted file mode 100755 index a19359ec3..000000000 --- a/test_regress/t/t_vpi_module.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_top_shell => 0, - make_main => 0, - make_pli => 1, - iv_flags2 => ["-g2005-sv"], - verilator_flags2 => ["+define+USE_DOLLAR_C32 --exe --vpi --no-l2name $Self->{t_dir}/t_vpi_module.cpp"], - ); - -execute( - use_libvpi => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_module.py b/test_regress/t/t_vpi_module.py new file mode 100755 index 000000000..ef8a5d334 --- /dev/null +++ b/test_regress/t/t_vpi_module.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + make_top_shell=False, + make_main=False, + make_pli=True, + iv_flags2=["-g2005-sv"], + verilator_flags2=["+define+USE_DOLLAR_C32 --exe --vpi --no-l2name", test.pli_filename]) + +test.execute(use_libvpi=True) + +test.passes() diff --git a/test_regress/t/t_vpi_module_dpi.pl b/test_regress/t/t_vpi_module_dpi.pl deleted file mode 100755 index 1b4fc72a9..000000000 --- a/test_regress/t/t_vpi_module_dpi.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -vm_prefix("Vt_vpi_module"); -top_filename("t/t_vpi_module.v"); -pli_filename("t_vpi_module.cpp"); - -compile( - make_top_shell => 0, - make_main => 0, - make_pli => 1, - iv_flags2 => ["-g2005-sv"], - verilator_flags2 => ["--exe --vpi --no-l2name $Self->{t_dir}/t_vpi_module.cpp"], - ); - -execute( - use_libvpi => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_module_dpi.py b/test_regress/t/t_vpi_module_dpi.py new file mode 100755 index 000000000..879bda0ca --- /dev/null +++ b/test_regress/t/t_vpi_module_dpi.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_vpi_module.v" +test.pli_filename = "t/t_vpi_module.cpp" +test.vm_prefix = "Vt_vpi_module" + +test.compile(make_top_shell=False, + make_main=False, + make_pli=True, + iv_flags2=["-g2005-sv"], + verilator_flags2=["--exe --vpi --no-l2name", test.pli_filename]) + +test.execute(use_libvpi=True) + +test.passes() diff --git a/test_regress/t/t_vpi_module_empty.pl b/test_regress/t/t_vpi_module_empty.pl deleted file mode 100755 index be16f1cf3..000000000 --- a/test_regress/t/t_vpi_module_empty.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_top_shell => 0, - make_main => 0, - make_pli => 1, - iv_flags2 => ["-g2005-sv"], - verilator_flags2 => ["+define+USE_DOLLAR_C32 --exe --vpi --no-l2name $Self->{t_dir}/t_vpi_module_empty.cpp"], - ); - -execute( - use_libvpi => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_module_empty.py b/test_regress/t/t_vpi_module_empty.py new file mode 100755 index 000000000..ef8a5d334 --- /dev/null +++ b/test_regress/t/t_vpi_module_empty.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + make_top_shell=False, + make_main=False, + make_pli=True, + iv_flags2=["-g2005-sv"], + verilator_flags2=["+define+USE_DOLLAR_C32 --exe --vpi --no-l2name", test.pli_filename]) + +test.execute(use_libvpi=True) + +test.passes() diff --git a/test_regress/t/t_vpi_onetime_cbs.pl b/test_regress/t/t_vpi_onetime_cbs.pl deleted file mode 100755 index 2ce1f5ac6..000000000 --- a/test_regress/t/t_vpi_onetime_cbs.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder and Marlon James. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -$Self->{sanitize} = 0; # Test neads cleanup to reclaim all callbacks - -compile( - make_top_shell => 0, - make_main => 0, - make_pli => 1, - verilator_flags2 => ["--exe --vpi $Self->{t_dir}/$Self->{name}.cpp"], - iv_flags2 => ["-g2005-sv -D USE_VPI_NOT_DPI -DIVERILOG"], - v_flags2 => ["+define+USE_VPI_NOT_DPI"], - ); - -execute( - use_libvpi => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_onetime_cbs.py b/test_regress/t/t_vpi_onetime_cbs.py new file mode 100755 index 000000000..2a2646bfd --- /dev/null +++ b/test_regress/t/t_vpi_onetime_cbs.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.sanitize = False # Test neads cleanup to reclaim all callbacks + +test.compile(make_top_shell=False, + make_main=False, + make_pli=True, + verilator_flags2=["--exe --vpi", test.pli_filename], + iv_flags2=["-g2005-sv -D USE_VPI_NOT_DPI -DIVERILOG"], + v_flags2=["+define+USE_VPI_NOT_DPI"]) + +test.execute(use_libvpi=True) + +test.passes() diff --git a/test_regress/t/t_vpi_package.pl b/test_regress/t/t_vpi_package.pl deleted file mode 100755 index 6bc13b32f..000000000 --- a/test_regress/t/t_vpi_package.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_top_shell => 0, - make_main => 0, - make_pli => 1, - verilator_flags2 => ["--exe --vpi --no-l2name $Self->{t_dir}/t_vpi_package.cpp"], - ); - -execute( - use_libvpi => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_package.py b/test_regress/t/t_vpi_package.py new file mode 100755 index 000000000..61cf61c9e --- /dev/null +++ b/test_regress/t/t_vpi_package.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_top_shell=False, + make_main=False, + make_pli=True, + verilator_flags2=["--exe --vpi --no-l2name", test.pli_filename]) + +test.execute(use_libvpi=True) + +test.passes() diff --git a/test_regress/t/t_vpi_param.pl b/test_regress/t/t_vpi_param.pl deleted file mode 100755 index 91be3146f..000000000 --- a/test_regress/t/t_vpi_param.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_top_shell => 0, - make_main => 0, - make_pli => 1, - iv_flags2 => ["-g2005-sv -D USE_VPI_NOT_DPI"], - v_flags2 => ["+define+USE_VPI_NOT_DPI"], - verilator_flags2 => ["--exe --vpi --no-l2name $Self->{t_dir}/t_vpi_param.cpp"], - ); - -execute( - use_libvpi => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_param.py b/test_regress/t/t_vpi_param.py new file mode 100755 index 000000000..31a4ce4b1 --- /dev/null +++ b/test_regress/t/t_vpi_param.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_top_shell=False, + make_main=False, + make_pli=True, + iv_flags2=["-g2005-sv -D USE_VPI_NOT_DPI"], + v_flags2=["+define+USE_VPI_NOT_DPI"], + verilator_flags2=["--exe --vpi --no-l2name", test.pli_filename]) + +test.execute(use_libvpi=True) + +test.passes() diff --git a/test_regress/t/t_vpi_public_depth.pl b/test_regress/t/t_vpi_public_depth.pl deleted file mode 100755 index d88768602..000000000 --- a/test_regress/t/t_vpi_public_depth.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_top_shell => 0, - make_main => 0, - make_pli => 1, - iv_flags2 => ["-g2005-sv"], - verilator_flags2 => ["+define+USE_DOLLAR_C32 --exe --vpi --no-l2name $Self->{t_dir}/t_vpi_public_depth.cpp --public-depth 3"], - make_flags => 'CPPFLAGS_ADD=-DTEST_VPI_PUBLIC_DEPTH', - ); - -execute( - use_libvpi => 1, - v_flags2, - ); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_public_depth.py b/test_regress/t/t_vpi_public_depth.py new file mode 100755 index 000000000..d5766b917 --- /dev/null +++ b/test_regress/t/t_vpi_public_depth.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_top_shell=False, + make_main=False, + make_pli=True, + iv_flags2=["-g2005-sv"], + verilator_flags2=[ + "+define+USE_DOLLAR_C32 --exe --vpi --no-l2name", test.pli_filename, + "--public-depth 3" + ], + make_flags=['CPPFLAGS_ADD=-DTEST_VPI_PUBLIC_DEPTH']) + +test.execute(use_libvpi=True, v_flags2=[]) + +test.passes() diff --git a/test_regress/t/t_vpi_public_depth_off.pl b/test_regress/t/t_vpi_public_depth_off.pl deleted file mode 100755 index 85d8a09aa..000000000 --- a/test_regress/t/t_vpi_public_depth_off.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -pli_filename("t_vpi_public_depth.cpp"); -top_filename("t/t_vpi_public_depth.v"); - -compile( - make_top_shell => 0, - make_main => 0, - make_pli => 1, - iv_flags2 => ["-g2005-sv"], - verilator_flags2 => ["+define+USE_DOLLAR_C32 --exe --vpi --no-l2name $Self->{t_dir}/t_vpi_public_depth.cpp --public-depth 2"], - make_flags => 'CPPFLAGS_ADD=-DTEST_VPI_PUBLIC_DEPTH_OFF', - ); - -execute( - use_libvpi => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_public_depth_off.py b/test_regress/t/t_vpi_public_depth_off.py new file mode 100755 index 000000000..925b535de --- /dev/null +++ b/test_regress/t/t_vpi_public_depth_off.py @@ -0,0 +1,28 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.pli_filename = "t/t_vpi_public_depth.cpp" +test.top_filename = "t/t_vpi_public_depth.v" + +test.compile(make_top_shell=False, + make_main=False, + make_pli=True, + iv_flags2=["-g2005-sv"], + verilator_flags2=[ + "+define+USE_DOLLAR_C32 --exe --vpi --no-l2name", test.pli_filename, + "--public-depth 2" + ], + make_flags=['CPPFLAGS_ADD=-DTEST_VPI_PUBLIC_DEPTH_OFF']) + +test.execute(use_libvpi=True) + +test.passes() diff --git a/test_regress/t/t_vpi_public_params.pl b/test_regress/t/t_vpi_public_params.pl deleted file mode 100755 index 816218e57..000000000 --- a/test_regress/t/t_vpi_public_params.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -# same vpi script should work with --public-params instead of inline publics -pli_filename("t_vpi_param.cpp"); - -compile( - make_top_shell => 0, - make_main => 0, - make_pli => 1, - iv_flags2 => ["-g2005-sv -D USE_VPI_NOT_DPI"], - v_flags2 => ["+define+USE_VPI_NOT_DPI"], - verilator_flags2 => ["--exe --vpi --no-l2name $Self->{t_dir}/t_vpi_param.cpp --public-params "], - ); - -execute( - use_libvpi => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_public_params.py b/test_regress/t/t_vpi_public_params.py new file mode 100755 index 000000000..43d10bc97 --- /dev/null +++ b/test_regress/t/t_vpi_public_params.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.pli_filename = "t/t_vpi_param.cpp" + +# same vpi script should work with --public-params instead of inline publics + +test.compile(make_top_shell=False, + make_main=False, + make_pli=True, + iv_flags2=["-g2005-sv -D USE_VPI_NOT_DPI"], + v_flags2=["+define+USE_VPI_NOT_DPI"], + verilator_flags2=["--exe --vpi --no-l2name", test.pli_filename, "--public-params"]) + +test.execute(use_libvpi=True) + +test.passes() diff --git a/test_regress/t/t_vpi_release_dup_bad.pl b/test_regress/t/t_vpi_release_dup_bad.pl deleted file mode 100755 index 66aceab2e..000000000 --- a/test_regress/t/t_vpi_release_dup_bad.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - v_flags2 => ["t/$Self->{name}_c.cpp"], - verilator_flags2 => ['--vpi'], - ); - -execute( - fails => 1, - ); - -file_grep($Self->{run_log_filename}, qr/vpi_release_handle.*called on same object twice/); - -ok(1); - -1; diff --git a/test_regress/t/t_vpi_release_dup_bad.py b/test_regress/t/t_vpi_release_dup_bad.py new file mode 100755 index 000000000..f49cdbdec --- /dev/null +++ b/test_regress/t/t_vpi_release_dup_bad.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(v_flags2=["t/" + test.name + "_c.cpp"], verilator_flags2=['--vpi']) + +test.execute(fails=True) + +test.file_grep(test.run_log_filename, r'vpi_release_handle.*called on same object twice') + +test.passes() diff --git a/test_regress/t/t_vpi_repetitive_cbs.pl b/test_regress/t/t_vpi_repetitive_cbs.pl deleted file mode 100755 index 0f892be35..000000000 --- a/test_regress/t/t_vpi_repetitive_cbs.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder and Marlon James. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_top_shell => 0, - make_main => 0, - make_pli => 1, - verilator_flags2 => ["--exe --vpi $Self->{t_dir}/$Self->{name}.cpp"], - iv_flags2 => ["-g2005-sv -D USE_VPI_NOT_DPI -DIVERILOG"], - v_flags2 => ["+define+USE_VPI_NOT_DPI"], - ); - -execute( - use_libvpi => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_repetitive_cbs.py b/test_regress/t/t_vpi_repetitive_cbs.py new file mode 100755 index 000000000..620a74cde --- /dev/null +++ b/test_regress/t/t_vpi_repetitive_cbs.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_top_shell=False, + make_main=False, + make_pli=True, + verilator_flags2=["--exe --vpi", test.pli_filename], + iv_flags2=["-g2005-sv -D USE_VPI_NOT_DPI -DIVERILOG"], + v_flags2=["+define+USE_VPI_NOT_DPI"]) + +test.execute(use_libvpi=True) + +test.passes() diff --git a/test_regress/t/t_vpi_sc.pl b/test_regress/t/t_vpi_sc.pl deleted file mode 100755 index f25861069..000000000 --- a/test_regress/t/t_vpi_sc.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - # Must not make shell/main or hides bug - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe --vpi --sc $Self->{t_dir}/t_vpi_sc.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_sc.py b/test_regress/t/t_vpi_sc.py new file mode 100755 index 000000000..cf18f768b --- /dev/null +++ b/test_regress/t/t_vpi_sc.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + # Must not make shell/main or hides bug + make_top_shell=False, + make_main=False, + verilator_flags2=["--exe --vpi --sc", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_vpi_stop_bad.pl b/test_regress/t/t_vpi_stop_bad.pl deleted file mode 100755 index 061b4561c..000000000 --- a/test_regress/t/t_vpi_stop_bad.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - v_flags2 => ["t/t_vpi_stop_bad_c.cpp"], - verilator_flags2 => ["--vpi"], - ); - -execute( - fails => $Self->{vlt_all}, - check_finished => 0, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); - -1; diff --git a/test_regress/t/t_vpi_stop_bad.py b/test_regress/t/t_vpi_stop_bad.py new file mode 100755 index 000000000..fb9404ffa --- /dev/null +++ b/test_regress/t/t_vpi_stop_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["t/t_vpi_stop_bad_c.cpp"], verilator_flags2=["--vpi"]) + +test.execute(fails=test.vlt_all, check_finished=False, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_vpi_time_cb.pl b/test_regress/t/t_vpi_time_cb.pl deleted file mode 100755 index abdef5cc1..000000000 --- a/test_regress/t/t_vpi_time_cb.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_top_shell => 0, - make_main => 0, - sim_time => 2100, - v_flags2 => ["t/t_vpi_time_cb_c.cpp"], - iv_flags2 => ["-g2005-sv -DWAVES -DIVERILOG"], - verilator_flags2 => ["--exe --vpi --no-l2name $Self->{t_dir}/t_vpi_time_cb.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_time_cb.py b/test_regress/t/t_vpi_time_cb.py new file mode 100755 index 000000000..a0b1ae435 --- /dev/null +++ b/test_regress/t/t_vpi_time_cb.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_top_shell=False, + make_main=False, + sim_time=2100, + v_flags2=["t/t_vpi_time_cb_c.cpp"], + iv_flags2=["-g2005-sv -DWAVES -DIVERILOG"], + verilator_flags2=["--exe --vpi --no-l2name", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_vpi_unimpl.pl b/test_regress/t/t_vpi_unimpl.pl deleted file mode 100755 index 65c0f6070..000000000 --- a/test_regress/t/t_vpi_unimpl.pl +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe --vpi --no-l2name $Self->{t_dir}/t_vpi_unimpl.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_unimpl.py b/test_regress/t/t_vpi_unimpl.py new file mode 100755 index 000000000..24ecd0ed9 --- /dev/null +++ b/test_regress/t/t_vpi_unimpl.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--exe --vpi --no-l2name", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_vpi_var.pl b/test_regress/t/t_vpi_var.pl deleted file mode 100755 index ac6ccbb43..000000000 --- a/test_regress/t/t_vpi_var.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_top_shell => 0, - make_main => 0, - make_pli => 1, - sim_time => 2100, - iv_flags2 => ["-g2005-sv -D USE_VPI_NOT_DPI -DWAVES"], - v_flags2 => ["+define+USE_VPI_NOT_DPI"], - verilator_flags2 => ["--exe --vpi --no-l2name $Self->{t_dir}/t_vpi_var.cpp"], - ); - -execute( - use_libvpi => 1, - all_run_flags => ['+PLUS +INT=1234 +STRSTR'] - ); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_var.py b/test_regress/t/t_vpi_var.py new file mode 100755 index 000000000..14985718b --- /dev/null +++ b/test_regress/t/t_vpi_var.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_top_shell=False, + make_main=False, + make_pli=True, + sim_time=2100, + iv_flags2=["-g2005-sv -D USE_VPI_NOT_DPI -DWAVES"], + v_flags2=["+define+USE_VPI_NOT_DPI"], + verilator_flags2=["--exe --vpi --no-l2name", test.pli_filename]) + +test.execute(use_libvpi=True, all_run_flags=['+PLUS +INT=1234 +STRSTR']) + +test.passes() diff --git a/test_regress/t/t_vpi_var2.pl b/test_regress/t/t_vpi_var2.pl deleted file mode 100755 index 8edb8c28e..000000000 --- a/test_regress/t/t_vpi_var2.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -pli_filename("t_vpi_var.cpp"); -compile( - make_top_shell => 0, - make_main => 0, - make_pli => 1, - sim_time => 2100, - iv_flags2 => ["-g2005-sv -D USE_VPI_NOT_DPI -DWAVES -DT_VPI_VAR2"], - v_flags2 => ["+define+USE_VPI_NOT_DPI"], - verilator_flags2 => ["--exe --vpi --no-l2name $Self->{t_dir}/t_vpi_var.cpp"], - ); - -execute( - use_libvpi => 1, - all_run_flags => ['+PLUS +INT=1234 +STRSTR'] - ); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_var2.py b/test_regress/t/t_vpi_var2.py new file mode 100755 index 000000000..478afcebb --- /dev/null +++ b/test_regress/t/t_vpi_var2.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.pli_filename = "t/t_vpi_var.cpp" + +test.compile(make_top_shell=False, + make_main=False, + make_pli=True, + sim_time=2100, + iv_flags2=["-g2005-sv -D USE_VPI_NOT_DPI -DWAVES -DT_VPI_VAR2"], + v_flags2=["+define+USE_VPI_NOT_DPI"], + verilator_flags2=["--exe --vpi --no-l2name", test.pli_filename]) + +test.execute(use_libvpi=True, all_run_flags=['+PLUS +INT=1234 +STRSTR']) + +test.passes() diff --git a/test_regress/t/t_vpi_var3.pl b/test_regress/t/t_vpi_var3.pl deleted file mode 100755 index 4ef824aa8..000000000 --- a/test_regress/t/t_vpi_var3.pl +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -pli_filename("t_vpi_var.cpp"); -compile( - make_top_shell => 0, - make_main => 0, - make_pli => 1, - sim_time => 2100, - iv_flags2 => ["-g2005-sv -D USE_VPI_NOT_DPI -DWAVES -DT_VPI_VAR3"], - v_flags2 => ["+define+USE_VPI_NOT_DPI"], - verilator_flags2 => ["--exe --vpi --no-l2name --public-flat-rw $Self->{t_dir}/t_vpi_var.cpp"], - ); - -execute( - use_libvpi => 1, - all_run_flags => ['+PLUS +INT=1234 +STRSTR'] - ); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_var3.py b/test_regress/t/t_vpi_var3.py new file mode 100755 index 000000000..f4a2b3cc4 --- /dev/null +++ b/test_regress/t/t_vpi_var3.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.pli_filename = "t/t_vpi_var.cpp" + +test.compile(make_top_shell=False, + make_main=False, + make_pli=True, + sim_time=2100, + iv_flags2=["-g2005-sv -D USE_VPI_NOT_DPI -DWAVES -DT_VPI_VAR3"], + v_flags2=["+define+USE_VPI_NOT_DPI"], + verilator_flags2=["--exe --vpi --no-l2name --public-flat-rw", test.pli_filename]) + +test.execute(use_libvpi=True, all_run_flags=['+PLUS +INT=1234 +STRSTR']) + +test.passes() diff --git a/test_regress/t/t_vpi_zero_time_cb.pl b/test_regress/t/t_vpi_zero_time_cb.pl deleted file mode 100755 index 9ad5e439b..000000000 --- a/test_regress/t/t_vpi_zero_time_cb.pl +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - make_main => 0, - make_pli => 1, - sim_time => 2100, - iv_flags2 => ["-g2005-sv -D USE_VPI_NOT_DPI -DWAVES -DIVERILOG"], - v_flags2 => ["+define+USE_VPI_NOT_DPI"], - verilator_flags2 => ["--exe --vpi --no-l2name $Self->{t_dir}/t_vpi_zero_time_cb.cpp -LDFLAGS '-ldl -rdynamic'"], - ); - -execute( - use_libvpi => 1, - all_run_flags => ['+PLUS +INT=1234 +STRSTR'] - ); - -ok(1); -1; diff --git a/test_regress/t/t_vpi_zero_time_cb.py b/test_regress/t/t_vpi_zero_time_cb.py new file mode 100755 index 000000000..aff674d1e --- /dev/null +++ b/test_regress/t/t_vpi_zero_time_cb.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + make_main=False, + make_pli=True, + sim_time=2100, + iv_flags2=["-g2005-sv -D USE_VPI_NOT_DPI -DWAVES -DIVERILOG"], + v_flags2=["+define+USE_VPI_NOT_DPI"], + verilator_flags2=["--exe --vpi --no-l2name", test.pli_filename, "-LDFLAGS '-ldl -rdynamic'"]) + +test.execute(use_libvpi=True, all_run_flags=['+PLUS +INT=1234 +STRSTR']) + +test.passes() diff --git a/test_regress/t/t_vthread.pl b/test_regress/t/t_vthread.pl deleted file mode 100755 index 041763899..000000000 --- a/test_regress/t/t_vthread.pl +++ /dev/null @@ -1,59 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -use IO::File; - -scenarios(vlt => 1); - -$Self->{sanitize} = 0; # GCC takes too long otherwise - -sub gen { - my $filename = shift; - my $n = shift; - - my $fh = IO::File->new(">$filename"); - $fh->print("// Generated by t_vthread.pl\n"); - $fh->print("module genmod #(int val = 0)(clk, o);\n"); - $fh->print(" input clk;\n"); - $fh->print(" output int o;\n"); - $fh->print(" always @ (posedge clk) begin\n"); - $fh->print(" o <= val;\n"); - $fh->print(" end\n"); - $fh->print("endmodule\n"); - $fh->print("module t (clk, o);\n"); - $fh->print(" input clk;\n"); - $fh->print(" output int o;\n"); - for (my $i = 0; $i < ($n + 1); ++$i) { - $fh->print(" int r$i;\n"); - $fh->print(" genmod #(.val($i)) rm$i (.clk(clk), .o(r$i));\n"); - } - $fh->print(" always @ (posedge clk) begin\n"); - $fh->print(" o <= r$n;\n"); - $fh->print(' $write("*-* All Finished *-*\n");', "\n"); - $fh->print(' $finish;', "\n"); - $fh->print(" end\n"); - $fh->print("endmodule\n"); -} - -top_filename("$Self->{obj_dir}/t_vthread.v"); - -gen($Self->{top_filename}, 6000); - -compile( - # use --trace to generate trace files that can be parallelized - verilator_flags2=>["--stats --trace --verilate-jobs 2"], - ); - -execute( - ); - -file_grep($Self->{stats}, qr/Verilate jobs: 2/); - -ok(1); -1; diff --git a/test_regress/t/t_vthread.py b/test_regress/t/t_vthread.py new file mode 100755 index 000000000..f0c0d547c --- /dev/null +++ b/test_regress/t/t_vthread.py @@ -0,0 +1,52 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = test.obj_dir + "/t_vthread.v" +test.sanitize = False # GCC takes too long otherwise + + +def gen(filename, n): + with open(filename, 'w', encoding="utf8") as fh: + fh.write("// Generated by t_vthread.py\n") + fh.write("module genmod #(int val = 0)(clk, o);\n") + fh.write(" input clk;\n") + fh.write(" output int o;\n") + fh.write(" always @ (posedge clk) begin\n") + fh.write(" o <= val;\n") + fh.write(" end\n") + fh.write("endmodule\n") + fh.write("module t (clk, o);\n") + fh.write(" input clk;\n") + fh.write(" output int o;\n") + for i in range(0, n + 1): + fh.write(" int r" + str(i) + ";\n") + fh.write(" genmod #(.val(" + str(i) + ")) rm" + str(i) + " (.clk, .o(r" + str(i) + + "));\n") + fh.write(" always @ (posedge clk) begin\n") + fh.write(" o <= r" + str(n) + ";\n") + fh.write(' $write("*-* All Finished *-*\\n");' + "\n") + fh.write(' $finish;' + "\n") + fh.write(" end\n") + fh.write("endmodule\n") + + +gen(test.top_filename, 6000) + +test.compile( + # use --trace to generate trace files that can be parallelized + verilator_flags2=["--stats --trace --verilate-jobs 2"]) + +test.execute() + +test.file_grep(test.stats, r'Verilate jobs: 2') + +test.passes() diff --git a/test_regress/t/t_wait.pl b/test_regress/t/t_wait.pl deleted file mode 100755 index c586a8d47..000000000 --- a/test_regress/t/t_wait.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - verilator_flags2 => ['--lint-only --no-timing'], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_wait.py b/test_regress/t/t_wait.py new file mode 100755 index 000000000..c2eb14c07 --- /dev/null +++ b/test_regress/t/t_wait.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=['--lint-only --no-timing'], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_wait_const.pl b/test_regress/t/t_wait_const.pl deleted file mode 100755 index b6ad59e52..000000000 --- a/test_regress/t/t_wait_const.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - verilator_flags2 => ["--binary"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_wait_const.py b/test_regress/t/t_wait_const.py new file mode 100755 index 000000000..a1700c6d9 --- /dev/null +++ b/test_regress/t/t_wait_const.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_wait_fork.pl b/test_regress/t/t_wait_fork.pl deleted file mode 100755 index 564c09ea7..000000000 --- a/test_regress/t/t_wait_fork.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2019 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -compile( - verilator_flags2 => ["--exe --main --timing"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_wait_fork.py b/test_regress/t/t_wait_fork.py new file mode 100755 index 000000000..88cfbe63f --- /dev/null +++ b/test_regress/t/t_wait_fork.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_wait_order.pl b/test_regress/t/t_wait_order.pl deleted file mode 100755 index eba12604c..000000000 --- a/test_regress/t/t_wait_order.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - expect_filename => $Self->{golden_filename}, - verilator_flags2 => ['--binary --timing'], - fails => $Self->{vlt_all}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_wait_order.py b/test_regress/t/t_wait_order.py new file mode 100755 index 000000000..f65962575 --- /dev/null +++ b/test_regress/t/t_wait_order.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(expect_filename=test.golden_filename, + verilator_flags2=['--binary --timing'], + fails=test.vlt_all) + +test.passes() diff --git a/test_regress/t/t_wait_timing.pl b/test_regress/t/t_wait_timing.pl deleted file mode 100755 index e8db4b9ca..000000000 --- a/test_regress/t/t_wait_timing.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -top_filename("t/t_wait.v"); - -compile( - timing_loop => 1, - verilator_flags2 => ["--binary --timing -Wno-WAITCONST"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_wait_timing.py b/test_regress/t/t_wait_timing.py new file mode 100755 index 000000000..eb0a58c0b --- /dev/null +++ b/test_regress/t/t_wait_timing.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_wait.v" + +test.compile(timing_loop=True, verilator_flags2=["--binary --timing -Wno-WAITCONST"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_waiveroutput.pl b/test_regress/t/t_waiveroutput.pl deleted file mode 100755 index c995f2cde..000000000 --- a/test_regress/t/t_waiveroutput.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/$Self->{name}_waiver_gen.out"; -my $waiver_filename = "t/$Self->{name}.vlt"; - -top_filename("t/t_waiveroutput.v"); - -compile( - v_flags2 => [$waiver_filename, '--waiver-output', $out_filename], - ); - -files_identical("$out_filename", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_waiveroutput.py b/test_regress/t/t_waiveroutput.py new file mode 100755 index 000000000..67b6355da --- /dev/null +++ b/test_regress/t/t_waiveroutput.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_waiveroutput.v" + +out_filename = test.obj_dir + "/" + test.name + ".waiver_gen.out" +waiver_filename = "t/" + test.name + ".vlt" + +test.compile(v_flags2=[waiver_filename, '--waiver-output', out_filename]) + +test.files_identical(out_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_waiveroutput_allgood.pl b/test_regress/t/t_waiveroutput_allgood.pl deleted file mode 100755 index 8a1846a0d..000000000 --- a/test_regress/t/t_waiveroutput_allgood.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/$Self->{name}_waiver_gen.vlt"; -my $waiver_filename = "t/$Self->{name}.vlt"; - -top_filename("t/t_waiveroutput.v"); - -compile( - v_flags2 => [$waiver_filename, '--waiver-output', $out_filename], - ); - -files_identical("$out_filename", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_waiveroutput_allgood.py b/test_regress/t/t_waiveroutput_allgood.py new file mode 100755 index 000000000..fd20a2c37 --- /dev/null +++ b/test_regress/t/t_waiveroutput_allgood.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_waiveroutput.v" + +out_filename = test.obj_dir + "/" + test.name + ".waiver_gen.vlt" +waiver_filename = "t/" + test.name + ".vlt" + +test.compile(v_flags2=[waiver_filename, '--waiver-output', out_filename]) + +test.files_identical(out_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_waiveroutput_wall.pl b/test_regress/t/t_waiveroutput_wall.pl deleted file mode 100755 index ff30db361..000000000 --- a/test_regress/t/t_waiveroutput_wall.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/$Self->{name}_waiver_gen.out"; -my $waiver_filename = "t/$Self->{name}.vlt"; - -top_filename("t/t_waiveroutput.v"); - -compile( - v_flags2 => ['-Wall', $waiver_filename, '--waiver-output', $out_filename], - ); - -files_identical("$out_filename", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_waiveroutput_wall.py b/test_regress/t/t_waiveroutput_wall.py new file mode 100755 index 000000000..9128c7d89 --- /dev/null +++ b/test_regress/t/t_waiveroutput_wall.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_waiveroutput.v" + +out_filename = test.obj_dir + "/" + test.name + ".waiver_gen.out" +waiver_filename = "t/" + test.name + ".vlt" + +test.compile(v_flags2=['-Wall', waiver_filename, '--waiver-output', out_filename]) + +test.files_identical(out_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_while_cond_is_stmt.pl b/test_regress/t/t_while_cond_is_stmt.pl deleted file mode 100755 index b3335ee60..000000000 --- a/test_regress/t/t_while_cond_is_stmt.pl +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile(); - -execute(); - -ok(1); -1; diff --git a/test_regress/t/t_while_cond_is_stmt.py b/test_regress/t/t_while_cond_is_stmt.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_while_cond_is_stmt.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_while_timing_control.pl b/test_regress/t/t_while_timing_control.pl deleted file mode 100755 index a17021b9d..000000000 --- a/test_regress/t/t_while_timing_control.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2022 by Antmicro Ltd. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -$Self->{main_time_multiplier} = 10e-7 / 10e-9; - -compile( - timing_loop => 1, - verilator_flags2 => ['--binary --timing -Wno-ZERODLY'], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_while_timing_control.py b/test_regress/t/t_while_timing_control.py new file mode 100755 index 000000000..5a15b96a8 --- /dev/null +++ b/test_regress/t/t_while_timing_control.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.main_time_multiplier = 10e-7 / 10e-9 + +test.compile(timing_loop=True, verilator_flags2=['--binary --timing -Wno-ZERODLY']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_wire_beh1364_bad.pl b/test_regress/t/t_wire_beh1364_bad.pl deleted file mode 100755 index 6a33667e2..000000000 --- a/test_regress/t/t_wire_beh1364_bad.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $waiver_filename = "$Self->{obj_dir}/$Self->{name}_waiver.vlt"; - -lint( - verilator_flags2 => ["--lint-only --language 1364-2001 --waiver-output ${waiver_filename}"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -if (-e $waiver_filename) { - error("Waiver file generated, not expected"); -} - -ok(1); -1; diff --git a/test_regress/t/t_wire_beh1364_bad.py b/test_regress/t/t_wire_beh1364_bad.py new file mode 100755 index 000000000..9e2f7e267 --- /dev/null +++ b/test_regress/t/t_wire_beh1364_bad.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +waiver_filename = test.obj_dir + "/" + test.name + "_waiver.vlt" + +test.lint(verilator_flags2=["--lint-only --language 1364-2001 --waiver-output", waiver_filename], + fails=True, + expect_filename=test.golden_filename) + +if os.path.exists(waiver_filename): + test.error("Waiver file generated, not expected") + +test.passes() diff --git a/test_regress/t/t_wire_beh1800_bad.pl b/test_regress/t/t_wire_beh1800_bad.pl deleted file mode 100755 index 85114ac5d..000000000 --- a/test_regress/t/t_wire_beh1800_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only --language 1800-2017"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_wire_beh1800_bad.py b/test_regress/t/t_wire_beh1800_bad.py new file mode 100755 index 000000000..54f436672 --- /dev/null +++ b/test_regress/t/t_wire_beh1800_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only --language 1800-2017"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_wire_behp1364_bad.pl b/test_regress/t/t_wire_behp1364_bad.pl deleted file mode 100755 index 77f34c903..000000000 --- a/test_regress/t/t_wire_behp1364_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only --language 1364-2001"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_wire_behp1364_bad.py b/test_regress/t/t_wire_behp1364_bad.py new file mode 100755 index 000000000..773f8b8e1 --- /dev/null +++ b/test_regress/t/t_wire_behp1364_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only --language 1364-2001"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_wire_behp1800_bad.pl b/test_regress/t/t_wire_behp1800_bad.pl deleted file mode 100755 index 85114ac5d..000000000 --- a/test_regress/t/t_wire_behp1800_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only --language 1800-2017"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_wire_behp1800_bad.py b/test_regress/t/t_wire_behp1800_bad.py new file mode 100755 index 000000000..54f436672 --- /dev/null +++ b/test_regress/t/t_wire_behp1800_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only --language 1800-2017"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_wire_self_bad.pl b/test_regress/t/t_wire_self_bad.pl deleted file mode 100755 index 85114ac5d..000000000 --- a/test_regress/t/t_wire_self_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only --language 1800-2017"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_wire_self_bad.py b/test_regress/t/t_wire_self_bad.py new file mode 100755 index 000000000..54f436672 --- /dev/null +++ b/test_regress/t/t_wire_self_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only --language 1800-2017"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_wire_triand.pl b/test_regress/t/t_wire_triand.pl deleted file mode 100755 index 59ba0d6c6..000000000 --- a/test_regress/t/t_wire_triand.pl +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(linter => 1); - -lint( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_wire_triand.py b/test_regress/t/t_wire_triand.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_wire_triand.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_wire_types.pl b/test_regress/t/t_wire_types.pl deleted file mode 100755 index 7927a1d7d..000000000 --- a/test_regress/t/t_wire_types.pl +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -$Self->{verilated_randReset} = 1; # allow checking if we initialize vars to zero only when needed - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_wire_types.py b/test_regress/t/t_wire_types.py new file mode 100755 index 000000000..8b49c4409 --- /dev/null +++ b/test_regress/t/t_wire_types.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.verilated_randReset = 1 # allow checking if we initialize vars to zero only when needed + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_with.pl b/test_regress/t/t_with.pl deleted file mode 100755 index 5a84db80d..000000000 --- a/test_regress/t/t_with.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_with.py b/test_regress/t/t_with.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_with.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_with_suggest_bad.pl b/test_regress/t/t_with_suggest_bad.pl deleted file mode 100755 index 85114ac5d..000000000 --- a/test_regress/t/t_with_suggest_bad.pl +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -lint( - verilator_flags2 => ["--lint-only --language 1800-2017"], - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_with_suggest_bad.py b/test_regress/t/t_with_suggest_bad.py new file mode 100755 index 000000000..54f436672 --- /dev/null +++ b/test_regress/t/t_with_suggest_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only --language 1800-2017"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_wrapper_clone.pl b/test_regress/t/t_wrapper_clone.pl deleted file mode 100755 index aef52675f..000000000 --- a/test_regress/t/t_wrapper_clone.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use strict; use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test module for prepareClone/atClone APIs -# -# Copyright 2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp", - "-cc"], - threads => $Self->{vltmt} ? 2 : 1, - ); - -execute( - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_wrapper_clone.py b/test_regress/t/t_wrapper_clone.py new file mode 100755 index 000000000..123fd2a37 --- /dev/null +++ b/test_regress/t/t_wrapper_clone.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test module for prepareClone/atClone APIs +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--exe", test.pli_filename, "-cc"], + threads=(2 if test.vltmt else 1)) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_wrapper_context.pl b/test_regress/t/t_wrapper_context.pl deleted file mode 100755 index b08ddb69e..000000000 --- a/test_regress/t/t_wrapper_context.pl +++ /dev/null @@ -1,33 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use strict; use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Multiple Model Test Module -# -# Copyright 2020-2021 by Andreas Kuster. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - # link threads library, add custom .cpp code, add tracing & coverage support - verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp", - "--trace --coverage -cc"], - threads => 1, - make_flags => 'CPPFLAGS_ADD=-DVL_NO_LEGACY', - ); - -execute( - ); - -files_identical_sorted("$Self->{obj_dir}/coverage_top0.dat", "t/t_wrapper_context_top0.out"); -files_identical_sorted("$Self->{obj_dir}/coverage_top1.dat", "t/t_wrapper_context_top1.out"); - -vcd_identical("$Self->{obj_dir}/trace0.vcd", "t/t_wrapper_context_trace0.out"); -vcd_identical("$Self->{obj_dir}/trace1.vcd", "t/t_wrapper_context_trace1.out"); - -ok(1); -1; diff --git a/test_regress/t/t_wrapper_context.py b/test_regress/t/t_wrapper_context.py new file mode 100755 index 000000000..62943d1c4 --- /dev/null +++ b/test_regress/t/t_wrapper_context.py @@ -0,0 +1,29 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Multiple Model Test Module +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile( + make_top_shell=False, + make_main=False, + # link threads library, add custom .cpp code, add tracing & coverage support + verilator_flags2=["--exe", test.pli_filename, "--trace --coverage -cc"], + threads=1, + make_flags=['CPPFLAGS_ADD=-DVL_NO_LEGACY']) + +test.execute() +test.files_identical_sorted(test.obj_dir + "/coverage_top0.dat", "t/t_wrapper_context_top0.out") +test.files_identical_sorted(test.obj_dir + "/coverage_top1.dat", "t/t_wrapper_context_top1.out") + +test.vcd_identical(test.obj_dir + "/trace0.vcd", "t/t_wrapper_context_trace0.out") +test.vcd_identical(test.obj_dir + "/trace1.vcd", "t/t_wrapper_context_trace1.out") + +test.passes() diff --git a/test_regress/t/t_wrapper_context_fst.pl b/test_regress/t/t_wrapper_context_fst.pl deleted file mode 100755 index b66019d4d..000000000 --- a/test_regress/t/t_wrapper_context_fst.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use strict; use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Multiple Model Test Module -# -# Copyright 2020-2021 by Andreas Kuster. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_wrapper_context.v"); - -compile( - make_top_shell => 0, - make_main => 0, - # link threads library, add custom .cpp code, add tracing & coverage support - verilator_flags2 => ["--exe $Self->{t_dir}/t_wrapper_context.cpp", - "--trace-fst --coverage -cc"], - threads => 1, - make_flags => 'CPPFLAGS_ADD=-DVL_NO_LEGACY', - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_wrapper_context_fst.py b/test_regress/t/t_wrapper_context_fst.py new file mode 100755 index 000000000..16290df42 --- /dev/null +++ b/test_regress/t/t_wrapper_context_fst.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Multiple Model Test Module +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_wrapper_context.cpp" +test.top_filename = "t/t_wrapper_context.v" + +test.compile( + make_top_shell=False, + make_main=False, + # link threads library, add custom .cpp code, add tracing & coverage support + verilator_flags2=["--exe", test.pli_filename, "--trace-fst --coverage -cc"], + threads=1, + make_flags=['CPPFLAGS_ADD=-DVL_NO_LEGACY']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_wrapper_context_seq.pl b/test_regress/t/t_wrapper_context_seq.pl deleted file mode 100755 index e6058bc58..000000000 --- a/test_regress/t/t_wrapper_context_seq.pl +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use strict; use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Multiple Model Test Module -# -# Copyright 2020-2021 by Andreas Kuster. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_wrapper_context.v"); - -compile( - make_top_shell => 0, - make_main => 0, - # link threads library, add custom .cpp code, add tracing & coverage support - verilator_flags2 => ["--exe $Self->{t_dir}/t_wrapper_context.cpp", - "--trace --coverage -cc"], - threads => 1, - make_flags => 'CPPFLAGS_ADD=-DVL_NO_LEGACY', - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_wrapper_context_seq.py b/test_regress/t/t_wrapper_context_seq.py new file mode 100755 index 000000000..94fe6aa28 --- /dev/null +++ b/test_regress/t/t_wrapper_context_seq.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Multiple Model Test Module +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_wrapper_context.cpp" +test.top_filename = "t/t_wrapper_context.v" + +test.compile( + make_top_shell=False, + make_main=False, + # link threads library, add custom .cpp code, add tracing & coverage support + verilator_flags2=["--exe", test.pli_filename, "--trace --coverage -cc"], + threads=1, + make_flags=['CPPFLAGS_ADD=-DVL_NO_LEGACY']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_wrapper_del_context_bad.pl b/test_regress/t/t_wrapper_del_context_bad.pl deleted file mode 100755 index 82a4ea9cf..000000000 --- a/test_regress/t/t_wrapper_del_context_bad.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use strict; use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Multiple Model Test Module -# -# Copyright 2020-2021 by Andreas Kuster. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_wrapper_del_context_bad.py b/test_regress/t/t_wrapper_del_context_bad.py new file mode 100755 index 000000000..a7310eb61 --- /dev/null +++ b/test_regress/t/t_wrapper_del_context_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Multiple Model Test Module +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_wrapper_legacy.pl b/test_regress/t/t_wrapper_legacy.pl deleted file mode 100755 index 3da70b1e1..000000000 --- a/test_regress/t/t_wrapper_legacy.pl +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder and Marlon James. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"], - make_flags => 'CPPFLAGS_ADD=-DVL_TIME_CONTEXT', - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_wrapper_legacy.py b/test_regress/t/t_wrapper_legacy.py new file mode 100755 index 000000000..5aaf32d75 --- /dev/null +++ b/test_regress/t/t_wrapper_legacy.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--exe", test.pli_filename], + make_flags=['CPPFLAGS_ADD=-DVL_TIME_CONTEXT']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_wrapper_legacy_time64.pl b/test_regress/t/t_wrapper_legacy_time64.pl deleted file mode 100755 index 887dfa2d0..000000000 --- a/test_regress/t/t_wrapper_legacy_time64.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder and Marlon James. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_wrapper_legacy.v"); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/t_wrapper_legacy.cpp"], - make_flags => 'CPPFLAGS_ADD=-DVL_TIME_STAMP64', - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_wrapper_legacy_time64.py b/test_regress/t/t_wrapper_legacy_time64.py new file mode 100755 index 000000000..1e14ef94a --- /dev/null +++ b/test_regress/t/t_wrapper_legacy_time64.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_wrapper_legacy.cpp" +test.top_filename = "t/t_wrapper_legacy.v" + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--exe", test.pli_filename], + make_flags=['CPPFLAGS_ADD=-DVL_TIME_STAMP64']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_wrapper_legacy_timed.pl b/test_regress/t/t_wrapper_legacy_timed.pl deleted file mode 100755 index 6c664fc8e..000000000 --- a/test_regress/t/t_wrapper_legacy_timed.pl +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Wilson Snyder and Marlon James. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_wrapper_legacy.v"); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/t_wrapper_legacy.cpp"], - make_flags => 'CPPFLAGS_ADD=-UVL_TIME_CONTEXT', - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_wrapper_legacy_timed.py b/test_regress/t/t_wrapper_legacy_timed.py new file mode 100755 index 000000000..74ebc2c1b --- /dev/null +++ b/test_regress/t/t_wrapper_legacy_timed.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_wrapper_legacy.cpp" +test.top_filename = "t/t_wrapper_legacy.v" + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--exe", test.pli_filename], + make_flags=['CPPFLAGS_ADD=-UVL_TIME_CONTEXT']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_wrapper_reuse_context_bad.pl b/test_regress/t/t_wrapper_reuse_context_bad.pl deleted file mode 100755 index 2aedd72bc..000000000 --- a/test_regress/t/t_wrapper_reuse_context_bad.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use strict; use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Multiple Model Test Module -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"], - ); - -execute( - fails => 1, - expect_filename => $Self->{golden_filename}, - ); - -ok(1); -1; diff --git a/test_regress/t/t_wrapper_reuse_context_bad.py b/test_regress/t/t_wrapper_reuse_context_bad.py new file mode 100755 index 000000000..a7310eb61 --- /dev/null +++ b/test_regress/t/t_wrapper_reuse_context_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Multiple Model Test Module +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_x_assign_0.pl b/test_regress/t/t_x_assign_0.pl deleted file mode 100755 index 2d47a9ee0..000000000 --- a/test_regress/t/t_x_assign_0.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_x_assign.v"); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--x-assign 0 --exe $Self->{t_dir}/t_x_assign.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_x_assign_0.py b/test_regress/t/t_x_assign_0.py new file mode 100755 index 000000000..37663b85c --- /dev/null +++ b/test_regress/t/t_x_assign_0.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_x_assign.cpp" +test.top_filename = "t/t_x_assign.v" + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--x-assign 0 --exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_x_assign_1.pl b/test_regress/t/t_x_assign_1.pl deleted file mode 100755 index b4bb4a1cf..000000000 --- a/test_regress/t/t_x_assign_1.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_x_assign.v"); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--x-assign 1 --exe $Self->{t_dir}/t_x_assign.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_x_assign_1.py b/test_regress/t/t_x_assign_1.py new file mode 100755 index 000000000..97778b4f0 --- /dev/null +++ b/test_regress/t/t_x_assign_1.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_x_assign.cpp" +test.top_filename = "t/t_x_assign.v" + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--x-assign 1 --exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_x_assign_unique_0.pl b/test_regress/t/t_x_assign_unique_0.pl deleted file mode 100755 index 59bcd76b1..000000000 --- a/test_regress/t/t_x_assign_unique_0.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_x_assign.v"); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--x-assign unique --exe $Self->{t_dir}/t_x_assign.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_x_assign_unique_0.py b/test_regress/t/t_x_assign_unique_0.py new file mode 100755 index 000000000..22aa92b35 --- /dev/null +++ b/test_regress/t/t_x_assign_unique_0.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_x_assign.cpp" +test.top_filename = "t/t_x_assign.v" + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--x-assign unique --exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_x_assign_unique_1.pl b/test_regress/t/t_x_assign_unique_1.pl deleted file mode 100755 index 59bcd76b1..000000000 --- a/test_regress/t/t_x_assign_unique_1.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2020 by Geza Lore. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt_all => 1); - -top_filename("t/t_x_assign.v"); - -compile( - make_top_shell => 0, - make_main => 0, - verilator_flags2 => ["--x-assign unique --exe $Self->{t_dir}/t_x_assign.cpp"], - ); - -execute( - ); - -ok(1); -1; diff --git a/test_regress/t/t_x_assign_unique_1.py b/test_regress/t/t_x_assign_unique_1.py new file mode 100755 index 000000000..22aa92b35 --- /dev/null +++ b/test_regress/t/t_x_assign_unique_1.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.pli_filename = "t/t_x_assign.cpp" +test.top_filename = "t/t_x_assign.v" + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=["--x-assign unique --exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_xml_begin_hier.pl b/test_regress/t/t_xml_begin_hier.pl deleted file mode 100755 index d25c191ff..000000000 --- a/test_regress/t/t_xml_begin_hier.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml"; - -compile( - verilator_flags2 => ['--no-std', '--xml-only'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -files_identical("$out_filename", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_xml_begin_hier.py b/test_regress/t/t_xml_begin_hier.py new file mode 100755 index 000000000..e24dca19d --- /dev/null +++ b/test_regress/t/t_xml_begin_hier.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +out_filename = test.obj_dir + "/V" + test.name + ".xml" + +test.compile(verilator_flags2=['--no-std', '--xml-only'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.files_identical(out_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_xml_debugcheck.pl b/test_regress/t/t_xml_debugcheck.pl deleted file mode 100755 index 78c58fd99..000000000 --- a/test_regress/t/t_xml_debugcheck.pl +++ /dev/null @@ -1,37 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml"; - -top_filename("t/t_enum_type_methods.v"); - -compile( - verilator_flags2 => ['--no-std', '--debug-check', '--flatten'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -files_identical("$out_filename", $Self->{golden_filename}, 'logfile'); - -# make sure that certain tags are present in --debug-check -# that would not be present in --xml-only -file_grep("$out_filename", qr//); # for and -file_grep("$out_filename", qr/ signed=/); # for -file_grep("$out_filename", qr/ func=/); # for - -ok(1); -1; diff --git a/test_regress/t/t_xml_debugcheck.py b/test_regress/t/t_xml_debugcheck.py new file mode 100755 index 000000000..c88859559 --- /dev/null +++ b/test_regress/t/t_xml_debugcheck.py @@ -0,0 +1,34 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_enum_type_methods.v" + +out_filename = test.obj_dir + "/V" + test.name + ".xml" + +test.compile(verilator_flags2=['--no-std', '--debug-check', '--flatten'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.files_identical(out_filename, test.golden_filename, 'logfile') + +# make sure that certain tags are present in --debug-check +# that would not be present in --xml-only +test.file_grep(out_filename, r'') # for and +test.file_grep(out_filename, r' signed=') # for +test.file_grep(out_filename, r' func=') # for + +test.passes() diff --git a/test_regress/t/t_xml_first.pl b/test_regress/t/t_xml_first.pl deleted file mode 100755 index d25c191ff..000000000 --- a/test_regress/t/t_xml_first.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml"; - -compile( - verilator_flags2 => ['--no-std', '--xml-only'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -files_identical("$out_filename", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_xml_first.py b/test_regress/t/t_xml_first.py new file mode 100755 index 000000000..e24dca19d --- /dev/null +++ b/test_regress/t/t_xml_first.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +out_filename = test.obj_dir + "/V" + test.name + ".xml" + +test.compile(verilator_flags2=['--no-std', '--xml-only'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.files_identical(out_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_xml_flat.pl b/test_regress/t/t_xml_flat.pl deleted file mode 100755 index 9d4890c52..000000000 --- a/test_regress/t/t_xml_flat.pl +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml"; - -top_filename("t/t_xml_first.v"); - -compile( - verilator_flags2 => ['--no-std', '--xml-only', '--flatten'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -files_identical("$out_filename", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_xml_flat.py b/test_regress/t/t_xml_flat.py new file mode 100755 index 000000000..39b3babd7 --- /dev/null +++ b/test_regress/t/t_xml_flat.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_xml_first.v" + +out_filename = test.obj_dir + "/V" + test.name + ".xml" + +test.compile(verilator_flags2=['--no-std', '--xml-only', '--flatten'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.files_identical(out_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_xml_flat_no_inline_mod.pl b/test_regress/t/t_xml_flat_no_inline_mod.pl deleted file mode 100755 index 9763b0cc1..000000000 --- a/test_regress/t/t_xml_flat_no_inline_mod.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml"; - -compile( - verilator_flags2 => ['--no-std', '--xml-only', '--flatten'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -files_identical("$out_filename", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_xml_flat_no_inline_mod.py b/test_regress/t/t_xml_flat_no_inline_mod.py new file mode 100755 index 000000000..d011198ac --- /dev/null +++ b/test_regress/t/t_xml_flat_no_inline_mod.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +out_filename = test.obj_dir + "/V" + test.name + ".xml" + +test.compile(verilator_flags2=['--no-std', '--xml-only', '--flatten'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.files_identical(out_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_xml_flat_pub_mod.pl b/test_regress/t/t_xml_flat_pub_mod.pl deleted file mode 100755 index 9763b0cc1..000000000 --- a/test_regress/t/t_xml_flat_pub_mod.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml"; - -compile( - verilator_flags2 => ['--no-std', '--xml-only', '--flatten'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -files_identical("$out_filename", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_xml_flat_pub_mod.py b/test_regress/t/t_xml_flat_pub_mod.py new file mode 100755 index 000000000..d011198ac --- /dev/null +++ b/test_regress/t/t_xml_flat_pub_mod.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +out_filename = test.obj_dir + "/V" + test.name + ".xml" + +test.compile(verilator_flags2=['--no-std', '--xml-only', '--flatten'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.files_identical(out_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_xml_flat_vlvbound.pl b/test_regress/t/t_xml_flat_vlvbound.pl deleted file mode 100755 index 9763b0cc1..000000000 --- a/test_regress/t/t_xml_flat_vlvbound.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml"; - -compile( - verilator_flags2 => ['--no-std', '--xml-only', '--flatten'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -files_identical("$out_filename", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_xml_flat_vlvbound.py b/test_regress/t/t_xml_flat_vlvbound.py new file mode 100755 index 000000000..d011198ac --- /dev/null +++ b/test_regress/t/t_xml_flat_vlvbound.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +out_filename = test.obj_dir + "/V" + test.name + ".xml" + +test.compile(verilator_flags2=['--no-std', '--xml-only', '--flatten'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.files_identical(out_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_xml_output.pl b/test_regress/t/t_xml_output.pl deleted file mode 100755 index 8f7f7dc3e..000000000 --- a/test_regress/t/t_xml_output.pl +++ /dev/null @@ -1,32 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/renamed-$Self->{name}.xml"; - -compile( - verilator_flags2 => ["--no-std", "--xml-only --xml-output $out_filename"], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -files_identical("$out_filename", $Self->{golden_filename}); - -foreach my $file (glob("$Self->{obj_dir}/*")) { - next if $file =~ /\.log/; # Made by driver.pl, not Verilator - next if $file =~ /\.status/; # Made by driver.pl, not Verilator - next if $file =~ /renamed-/; # Requested output - error("%Error: Created $file, but --xml-only shouldn't create files"); -} - -ok(1); -1; diff --git a/test_regress/t/t_xml_output.py b/test_regress/t/t_xml_output.py new file mode 100755 index 000000000..640e36eca --- /dev/null +++ b/test_regress/t/t_xml_output.py @@ -0,0 +1,30 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +out_filename = test.obj_dir + "/renamed-" + test.name + ".xml" + +test.compile(verilator_flags2=["--no-std", "--xml-only --xml-output", out_filename], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.files_identical(out_filename, test.golden_filename) + +for filename in test.glob_some(test.obj_dir + "/*"): + if (re.search(r'\.log', filename) # Made by driver.py, not Verilator sources + or re.search(r'\.status', filename) # Made by driver.py, not Verilator sources + or re.search(r'renamed-', filename)): # Requested output + continue + test.error("%Error: Created '" + filename + "', but --xml-only shouldn't create files") + +test.passes() diff --git a/test_regress/t/t_xml_tag.pl b/test_regress/t/t_xml_tag.pl deleted file mode 100755 index d25c191ff..000000000 --- a/test_regress/t/t_xml_tag.pl +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2012 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(vlt => 1); - -my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml"; - -compile( - verilator_flags2 => ['--no-std', '--xml-only'], - verilator_make_gmake => 0, - make_top_shell => 0, - make_main => 0, - ); - -files_identical("$out_filename", $Self->{golden_filename}); - -ok(1); -1; diff --git a/test_regress/t/t_xml_tag.py b/test_regress/t/t_xml_tag.py new file mode 100755 index 000000000..e24dca19d --- /dev/null +++ b/test_regress/t/t_xml_tag.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +out_filename = test.obj_dir + "/V" + test.name + ".xml" + +test.compile(verilator_flags2=['--no-std', '--xml-only'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.files_identical(out_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/vltest_bootstrap.py b/test_regress/t/vltest_bootstrap.py new file mode 100755 index 000000000..49684b191 --- /dev/null +++ b/test_regress/t/vltest_bootstrap.py @@ -0,0 +1,17 @@ +# DESCRIPTION: Verilator: Verilog Test bootstrap loader +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import os +import re +import sys + +os.chdir(os.path.dirname(os.path.realpath(__file__)) + "/..") +# Avoid chdir leaving the .. which confuses later commands +os.environ['PWD'] = os.getcwd() +args = list(map(lambda arg: re.sub(r'.*/test_regress/', '', arg), sys.argv)) +os.execl("./driver.py", "--bootstrapped", *args)