diff --git a/.github/workflows/build-test.yml b/.github/workflows/build-test.yml index 7817a3bf6..b1ae9dfdb 100644 --- a/.github/workflows/build-test.yml +++ b/.github/workflows/build-test.yml @@ -199,6 +199,13 @@ jobs: - {os: ubuntu-26.04, cc: gcc, reloc: 0, suite: vltmt-0} - {os: ubuntu-26.04, cc: gcc, reloc: 0, suite: vltmt-1} - {os: ubuntu-26.04, cc: gcc, reloc: 0, suite: vltmt-2} + - {os: ubuntu-26.04, cc: gcc, reloc: 0, suite: dist-vlt4-0} + - {os: ubuntu-26.04, cc: gcc, reloc: 0, suite: dist-vlt4-1} + - {os: ubuntu-26.04, cc: gcc, reloc: 0, suite: dist-vlt4-2} + - {os: ubuntu-26.04, cc: gcc, reloc: 0, suite: dist-vlt4-3} + - {os: ubuntu-26.04, cc: gcc, reloc: 0, suite: vltmt4-0} + - {os: ubuntu-26.04, cc: gcc, reloc: 0, suite: vltmt4-1} + - {os: ubuntu-26.04, cc: gcc, reloc: 0, suite: vltmt4-2} test-2604-clang: name: Test | ${{ matrix.os }} | ${{ matrix.cc }} | ${{ matrix.reloc && 'reloc | ' || '' }} ${{ matrix.suite }} @@ -223,6 +230,13 @@ jobs: - {os: ubuntu-26.04, cc: clang, reloc: 0, suite: vltmt-0} - {os: ubuntu-26.04, cc: clang, reloc: 0, suite: vltmt-1} - {os: ubuntu-26.04, cc: clang, reloc: 0, suite: vltmt-2} + - {os: ubuntu-26.04, cc: clang, reloc: 0, suite: dist-vlt4-0} + - {os: ubuntu-26.04, cc: clang, reloc: 0, suite: dist-vlt4-1} + - {os: ubuntu-26.04, cc: clang, reloc: 0, suite: dist-vlt4-2} + - {os: ubuntu-26.04, cc: clang, reloc: 0, suite: dist-vlt4-3} + - {os: ubuntu-26.04, cc: clang, reloc: 0, suite: vltmt4-0} + - {os: ubuntu-26.04, cc: clang, reloc: 0, suite: vltmt4-1} + - {os: ubuntu-26.04, cc: clang, reloc: 0, suite: vltmt4-2} test-2404-gcc: name: Test | ${{ matrix.os }} | ${{ matrix.cc }} | ${{ matrix.reloc && 'reloc | ' || '' }} ${{ matrix.suite }} @@ -247,6 +261,13 @@ jobs: - {os: ubuntu-24.04, cc: gcc, reloc: 0, suite: vltmt-0} - {os: ubuntu-24.04, cc: gcc, reloc: 0, suite: vltmt-1} - {os: ubuntu-24.04, cc: gcc, reloc: 0, suite: vltmt-2} + - {os: ubuntu-24.04, cc: gcc, reloc: 0, suite: dist-vlt4-0} + - {os: ubuntu-24.04, cc: gcc, reloc: 0, suite: dist-vlt4-1} + - {os: ubuntu-24.04, cc: gcc, reloc: 0, suite: dist-vlt4-2} + - {os: ubuntu-24.04, cc: gcc, reloc: 0, suite: dist-vlt4-3} + - {os: ubuntu-24.04, cc: gcc, reloc: 0, suite: vltmt4-0} + - {os: ubuntu-24.04, cc: gcc, reloc: 0, suite: vltmt4-1} + - {os: ubuntu-24.04, cc: gcc, reloc: 0, suite: vltmt4-2} test-2404-clang: name: Test | ${{ matrix.os }} | ${{ matrix.cc }} | ${{ matrix.reloc && 'reloc | ' || '' }} ${{ matrix.suite }} @@ -271,6 +292,13 @@ jobs: - {os: ubuntu-24.04, cc: clang, reloc: 0, suite: vltmt-0} - {os: ubuntu-24.04, cc: clang, reloc: 0, suite: vltmt-1} - {os: ubuntu-24.04, cc: clang, reloc: 0, suite: vltmt-2} + - {os: ubuntu-24.04, cc: clang, reloc: 0, suite: dist-vlt4-0} + - {os: ubuntu-24.04, cc: clang, reloc: 0, suite: dist-vlt4-1} + - {os: ubuntu-24.04, cc: clang, reloc: 0, suite: dist-vlt4-2} + - {os: ubuntu-24.04, cc: clang, reloc: 0, suite: dist-vlt4-3} + - {os: ubuntu-24.04, cc: clang, reloc: 0, suite: vltmt4-0} + - {os: ubuntu-24.04, cc: clang, reloc: 0, suite: vltmt4-1} + - {os: ubuntu-24.04, cc: clang, reloc: 0, suite: vltmt4-2} test-2204-gcc: name: Test | ${{ matrix.os }} | ${{ matrix.cc }} | ${{ matrix.reloc && 'reloc | ' || '' }} ${{ matrix.suite }} @@ -295,6 +323,13 @@ jobs: - {os: ubuntu-22.04, cc: gcc, reloc: 0, suite: vltmt-0} - {os: ubuntu-22.04, cc: gcc, reloc: 0, suite: vltmt-1} - {os: ubuntu-22.04, cc: gcc, reloc: 0, suite: vltmt-2} + - {os: ubuntu-22.04, cc: gcc, reloc: 0, suite: dist-vlt4-0} + - {os: ubuntu-22.04, cc: gcc, reloc: 0, suite: dist-vlt4-1} + - {os: ubuntu-22.04, cc: gcc, reloc: 0, suite: dist-vlt4-2} + - {os: ubuntu-22.04, cc: gcc, reloc: 0, suite: dist-vlt4-3} + - {os: ubuntu-22.04, cc: gcc, reloc: 0, suite: vltmt4-0} + - {os: ubuntu-22.04, cc: gcc, reloc: 0, suite: vltmt4-1} + - {os: ubuntu-22.04, cc: gcc, reloc: 0, suite: vltmt4-2} lint-py: name: Lint Python diff --git a/.github/workflows/coverage.yml b/.github/workflows/coverage.yml index cc6b463b0..124886c5f 100644 --- a/.github/workflows/coverage.yml +++ b/.github/workflows/coverage.yml @@ -62,7 +62,7 @@ jobs: strategy: fail-fast: false matrix: - test: [coverage-vlt-, coverage-vltmt-] + test: [coverage-vlt-, coverage-vltmt-, coverage-vlt4-, coverage-vltmt4-] num: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9] include: - {test: coverage-dist, num: ''} diff --git a/bin/verilator b/bin/verilator index cb866e243..08763eed9 100755 --- a/bin/verilator +++ b/bin/verilator @@ -628,6 +628,8 @@ detailed descriptions of these arguments. --x-initial Assign initial Xs to this value --x-initial-edge Enable initial X->0 and X->1 edge triggers -y Directory to search for modules + --zero-top-ports Enables initialization of top level ports with zeros in fourstate logic mode + --no-zero-top-ports Disables initialization of top level ports with zeros in fourstate logic mode This is a short summary of the simulation runtime arguments, i.e. for the final Verilated simulation runtime models. See diff --git a/ci/ci-script.bash b/ci/ci-script.bash index aa7a5987a..e1d26381a 100755 --- a/ci/ci-script.bash +++ b/ci/ci-script.bash @@ -128,6 +128,27 @@ elif [ "$CI_BUILD_STAGE_NAME" = "test" ]; then vltmt-2) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vltmt --driver-clean" DRIVER_HASHSET=--hashset=2/3 ;; + dist-vlt4-0) + "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--dist --vlt4 --driver-clean" DRIVER_HASHSET=--hashset=0/4 + ;; + dist-vlt4-1) + "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--dist --vlt4 --driver-clean" DRIVER_HASHSET=--hashset=1/4 + ;; + dist-vlt4-2) + "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--dist --vlt4 --driver-clean" DRIVER_HASHSET=--hashset=2/4 + ;; + dist-vlt4-3) + "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--dist --vlt4 --driver-clean" DRIVER_HASHSET=--hashset=3/4 + ;; + vltmt4-0) + "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vltmt4 --driver-clean" DRIVER_HASHSET=--hashset=0/3 + ;; + vltmt4-1) + "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vltmt4 --driver-clean" DRIVER_HASHSET=--hashset=1/3 + ;; + vltmt4-2) + "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vltmt4 --driver-clean" DRIVER_HASHSET=--hashset=2/3 + ;; coverage-dist) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--dist" ;; @@ -191,6 +212,66 @@ elif [ "$CI_BUILD_STAGE_NAME" = "test" ]; then coverage-vltmt-9) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vltmt" DRIVER_HASHSET=--hashset=9/10 ;; + coverage-vlt4-0) + "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vlt4" DRIVER_HASHSET=--hashset=0/10 + ;; + coverage-vlt4-1) + "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vlt4" DRIVER_HASHSET=--hashset=1/10 + ;; + coverage-vlt4-2) + "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vlt4" DRIVER_HASHSET=--hashset=2/10 + ;; + coverage-vlt4-3) + "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vlt4" DRIVER_HASHSET=--hashset=3/10 + ;; + coverage-vlt4-4) + "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vlt4" DRIVER_HASHSET=--hashset=4/10 + ;; + coverage-vlt4-5) + "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vlt4" DRIVER_HASHSET=--hashset=5/10 + ;; + coverage-vlt4-6) + "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vlt4" DRIVER_HASHSET=--hashset=6/10 + ;; + coverage-vlt4-7) + "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vlt4" DRIVER_HASHSET=--hashset=7/10 + ;; + coverage-vlt4-8) + "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vlt4" DRIVER_HASHSET=--hashset=8/10 + ;; + coverage-vlt4-9) + "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vlt4" DRIVER_HASHSET=--hashset=9/10 + ;; + coverage-vltmt4-0) + "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vltmt4" DRIVER_HASHSET=--hashset=0/10 + ;; + coverage-vltmt4-1) + "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vltmt4" DRIVER_HASHSET=--hashset=1/10 + ;; + coverage-vltmt4-2) + "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vltmt4" DRIVER_HASHSET=--hashset=2/10 + ;; + coverage-vltmt4-3) + "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vltmt4" DRIVER_HASHSET=--hashset=3/10 + ;; + coverage-vltmt4-4) + "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vltmt4" DRIVER_HASHSET=--hashset=4/10 + ;; + coverage-vltmt4-5) + "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vltmt4" DRIVER_HASHSET=--hashset=5/10 + ;; + coverage-vltmt4-6) + "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vltmt4" DRIVER_HASHSET=--hashset=6/10 + ;; + coverage-vltmt4-7) + "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vltmt4" DRIVER_HASHSET=--hashset=7/10 + ;; + coverage-vltmt4-8) + "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vltmt4" DRIVER_HASHSET=--hashset=8/10 + ;; + coverage-vltmt4-9) + "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vltmt4" DRIVER_HASHSET=--hashset=9/10 + ;; *) fatal "Unknown TESTS: $TESTS" ;; diff --git a/docs/guide/exe_verilator.rst b/docs/guide/exe_verilator.rst index 807216565..d1a873ca5 100644 --- a/docs/guide/exe_verilator.rst +++ b/docs/guide/exe_verilator.rst @@ -2380,3 +2380,12 @@ Summary: user-specified directories. This allows '-y "$(pwd)"' to be used if absolute filenames are desired for error messages instead of relative filenames. + +.. option:: --zero-top-ports + +.. option:: --no-zero-top-ports + + Options used with :vlopt:`--fourstate` to enable/disable + initialization of top module ports with zeros instead of `x`. + This is useful to keep the backward compatibility with existing C++. + Enabled by default with :vlopt:`--fourstate`. diff --git a/docs/guide/warnings.rst b/docs/guide/warnings.rst index ce3a0d58c..2a6b68540 100644 --- a/docs/guide/warnings.rst +++ b/docs/guide/warnings.rst @@ -443,6 +443,24 @@ List Of Warnings in decreased performance. +.. option:: CASTFOURSTATE + + Warns about not supported four-state logic feature. + When two-state logic variant of a feature is fully supported, + an implicit cast to two-state type is made + + .. code-block:: sv + :linenos: + :emphasize-lines: 5 + + module t; + integer fd; + initial begin + $fflush(fd); // <- implicit conversion to two-state value + end + endmodule + + .. option:: CDCRSTLOGIC Historical, never issued since version 5.008. @@ -1346,7 +1364,6 @@ List Of Warnings :option:`ASCRANGE`. While :option:`LITENDIAN` remains for backwards compatibility, new projects should use :option:`ASCRANGE`. - .. option:: MINTYPMAXDLY .. code-block:: sv diff --git a/include/verilated.cpp b/include/verilated.cpp index a5fdc91ac..f68a1a248 100644 --- a/include/verilated.cpp +++ b/include/verilated.cpp @@ -638,9 +638,29 @@ WDataOutP VL_RAND_RESET_W(int obits, WDataOutP outwp) VL_MT_SAFE { outwp[VL_WORDS_I(obits) - 1] = VL_RAND_RESET_I(32) & VL_MASK_E(obits); return outwp; } -WDataOutP VL_ZERO_RESET_W(int obits, WDataOutP outwp) VL_MT_SAFE { +WDataOutP VL_ZERO_RESET_W_T(int obits, WDataOutP outwp) VL_MT_SAFE { // Not inlined to speed up compilation of slowpath code - return VL_ZERO_W(obits, outwp); + return VL_ZERO_W_T(obits, outwp); +} +WDataOutP VL_ZERO_RESET_W_V(int obits, WDataOutP outwp) VL_MT_SAFE { + // Not inlined to speed up compilation of slowpath code + return VL_ZERO_W_V(obits, outwp); +} +WDataOutP VL_ZERO_RESET_W_X(int obits, WDataOutP outwp) VL_MT_SAFE { + // Not inlined to speed up compilation of slowpath code + return VL_ZERO_W_X(obits, outwp); +} +WDataOutP VL_ALLONES_RESET_W_T(int obits, WDataOutP outwp) VL_MT_SAFE { + // Not inlined to speed up compilation of slowpath code + return VL_ALLONES_W_T(obits, outwp); +} +WDataOutP VL_ALLONES_RESET_W_V(int obits, WDataOutP outwp) VL_MT_SAFE { + // Not inlined to speed up compilation of slowpath code + return VL_ALLONES_W_V(obits, outwp); +} +WDataOutP VL_ALLONES_RESET_W_X(int obits, WDataOutP outwp) VL_MT_SAFE { + // Not inlined to speed up compilation of slowpath code + return VL_ALLONES_W_X(obits, outwp); } //=========================================================================== @@ -655,20 +675,39 @@ void _vl_debug_print_w(int lbits, const WDataInP iwp) VL_MT_SAFE { //=========================================================================== // Slow expressions -WDataOutP _vl_moddiv_w(int lbits, WDataOutP owp, const WDataInP lwp, const WDataInP rwp, - bool is_modulus) VL_MT_SAFE { +WDataOutP _vl_moddiv_w(int lbits, WDataOutP owp, WDataInP lwp, WDataInP rwp, bool is_modulus, + const int outputOffset, int outputJump, const int lhsOffset, int lhsJump, + const int rhsOffset, int rhsJump) VL_MT_SAFE { // See Knuth Algorithm D. Computes u/v = q.r // This isn't massively tuned, as wide division is rare // for debug see V3Number version // Requires clean input + VL_DEBUG_IFDEF(assert((outputOffset == 0 && (outputJump == 1 || outputJump == 2)) + || (outputOffset == 1 && outputJump == 2));); + VL_DEBUG_IFDEF(assert((lhsOffset == 0 && (lhsJump == 1 || lhsJump == 2)) + || (lhsOffset == 1 && lhsJump == 2));); + VL_DEBUG_IFDEF(assert((rhsOffset == 0 && (rhsJump == 1 || rhsJump == 2)) + || (rhsOffset == 1 && rhsJump == 2));); const int words = VL_WORDS_I(lbits); - for (int i = 0; i < words; ++i) owp[i] = 0; // Find MSB and check for zero. - const int umsbp1 = VL_MOSTSETBITP1_W(words, lwp); // dividend - const int vmsbp1 = VL_MOSTSETBITP1_W(words, rwp); // divisor + const int umsbp1 = (lhsJump == 2) ? (lhsOffset ? VL_MOSTSETBITP1_W_X(words, lwp) + : VL_MOSTSETBITP1_W_V(words, lwp)) + : VL_MOSTSETBITP1_W_T(words, lwp); // dividend + const int vmsbp1 = (rhsJump == 2) ? (rhsOffset ? VL_MOSTSETBITP1_W_X(words, rwp) + : VL_MOSTSETBITP1_W_V(words, rwp)) + : VL_MOSTSETBITP1_W_T(words, rwp); // divisor + const WDataOutP resultp = owp; + owp += outputOffset; + lwp += lhsOffset; + rwp += rhsOffset; + // Since jump may be 1 or 2 we substract one to just use bit-shift left + --outputJump; + --lhsJump; + --rhsJump; + for (int i = 0; i < words; ++i) owp[i << outputJump] = 0; if (VL_UNLIKELY(vmsbp1 == 0) // rwp==0 so division by zero. Return 0. || VL_UNLIKELY(umsbp1 == 0)) { // 0/x so short circuit and return 0 - return owp; + return resultp; } const int uw = VL_WORDS_I(umsbp1); // aka "m" in the algorithm @@ -679,15 +718,16 @@ WDataOutP _vl_moddiv_w(int lbits, WDataOutP owp, const WDataInP lwp, const WData if (vw == 1) { // Single divisor word breaks rest of algorithm uint64_t k = 0; for (int j = uw - 1; j >= 0; --j) { - const uint64_t unw64 = ((k << 32ULL) + static_cast(lwp[j])); - owp[j] = unw64 / static_cast(rwp[0]); - k = unw64 - static_cast(owp[j]) * static_cast(rwp[0]); + const uint64_t unw64 = ((k << 32ULL) + static_cast(lwp[j << lhsJump])); + owp[j << outputJump] = unw64 / static_cast(rwp[0]); + k = unw64 + - static_cast(owp[j << outputJump]) * static_cast(rwp[0]); } if (is_modulus) { owp[0] = k; - for (int i = 1; i < words; ++i) owp[i] = 0; + for (int i = 1; i < words; ++i) owp[i << outputJump] = 0; } - return owp; + return resultp; } // +1 word as we may shift during normalization @@ -703,16 +743,20 @@ WDataOutP _vl_moddiv_w(int lbits, WDataOutP owp, const WDataInP lwp, const WData const int s = 31 - VL_BITBIT_I(vmsbp1 - 1); // shift amount (0...31) // Copy and shift dividend by same amount; may set new upper word if (s) { - for (int i = vw - 1; i > 0; --i) vn[i] = (rwp[i] << s) | (rwp[i - 1] >> (32 - s)); + for (int i = vw - 1; i > 0; --i) { + vn[i] = (rwp[i << rhsJump] << s) | (rwp[(i - 1) << rhsJump] >> (32 - s)); + } vn[0] = rwp[0] << s; - un[uw] = lwp[uw - 1] >> (32 - s); - for (int i = uw - 1; i > 0; --i) un[i] = (lwp[i] << s) | (lwp[i - 1] >> (32 - s)); + un[uw] = lwp[(uw - 1) << lhsJump] >> (32 - s); + for (int i = uw - 1; i > 0; --i) { + un[i] = (lwp[i << lhsJump] << s) | (lwp[(i - 1) << lhsJump] >> (32 - s)); + } un[0] = lwp[0] << s; } else { - for (int i = vw - 1; i > 0; --i) vn[i] = rwp[i]; + for (int i = vw - 1; i > 0; --i) vn[i] = rwp[i << rhsJump]; vn[0] = rwp[0]; un[uw] = 0; - for (int i = uw - 1; i > 0; --i) un[i] = lwp[i]; + for (int i = uw - 1; i > 0; --i) un[i] = lwp[i << lhsJump]; un[0] = lwp[0]; } @@ -741,11 +785,11 @@ WDataOutP _vl_moddiv_w(int lbits, WDataOutP owp, const WDataInP lwp, const WData } t = un[j + vw] - k; un[j + vw] = t; - owp[j] = qhat; // Save quotient digit + owp[j << outputJump] = qhat; // Save quotient digit if (t < 0) { // Over subtracted; correct by adding back - owp[j]--; + owp[j << outputJump]--; k = 0; for (int i = 0; i < vw; ++i) { t = static_cast(un[i + j]) + static_cast(vn[i]) + k; @@ -759,15 +803,17 @@ WDataOutP _vl_moddiv_w(int lbits, WDataOutP owp, const WDataInP lwp, const WData if (is_modulus) { // modulus // Need to reverse normalization on copy to output if (s) { - for (int i = 0; i < vw; ++i) owp[i] = (un[i] >> s) | (un[i + 1] << (32 - s)); + for (int i = 0; i < vw; ++i) { + owp[i << outputJump] = (un[i] >> s) | (un[i + 1] << (32 - s)); + } } else { - for (int i = 0; i < vw; ++i) owp[i] = un[i]; + for (int i = 0; i < vw; ++i) owp[i << outputJump] = un[i]; } - for (int i = vw; i < words; ++i) owp[i] = 0; - return owp; + for (int i = vw; i < words; ++i) owp[i << outputJump] = 0; + return resultp; } // division - return owp; + return resultp; } WDataOutP VL_POW_WWW(int obits, int, int rbits, WDataOutP owp, const WDataInP lwp, @@ -780,15 +826,15 @@ WDataOutP VL_POW_WWW(int obits, int, int rbits, WDataOutP owp, const WDataInP lw VlWide powstore; // Fixed size, as MSVC++ doesn't allow [words] here VlWide lastpowstore; // Fixed size, as MSVC++ doesn't allow [words] here VlWide lastoutstore; // Fixed size, as MSVC++ doesn't allow [words] here - VL_ASSIGN_W(obits, powstore, lwp); + VL_ASSIGN_W_TT(obits, powstore, lwp); for (int bit = 0; bit < rbits; ++bit) { if (bit > 0) { // power = power*power - VL_ASSIGN_W(obits, lastpowstore, powstore); - VL_MUL_W(owords, powstore, lastpowstore, lastpowstore); + VL_ASSIGN_W_TT(obits, lastpowstore, powstore); + VL_MUL_W_TTT(owords, powstore, lastpowstore, lastpowstore); } if (VL_BITISSET_W(rwp, bit)) { // out *= power - VL_ASSIGN_W(obits, lastoutstore, owp); - VL_MUL_W(owords, owp, lastoutstore, powstore); + VL_ASSIGN_W_TT(obits, lastoutstore, owp); + VL_MUL_W_TTT(owords, owp, lastoutstore, powstore); } } return owp; @@ -796,7 +842,7 @@ WDataOutP VL_POW_WWW(int obits, int, int rbits, WDataOutP owp, const WDataInP lw WDataOutP VL_POW_WWQ(int obits, int lbits, int rbits, WDataOutP owp, const WDataInP lwp, QData rhs) VL_MT_SAFE { VlWide rhsw; - VL_SET_WQ(rhsw, rhs); + VL_SET_WQ_T(rhsw, rhs); return VL_POW_WWW(obits, lbits, rbits, owp, lwp, rhsw); } QData VL_POW_QQW(int, int, int rbits, QData lhs, const WDataInP rwp) VL_MT_SAFE { @@ -817,9 +863,9 @@ QData VL_POW_QQW(int, int, int rbits, QData lhs, const WDataInP rwp) VL_MT_SAFE WDataOutP VL_POWSS_WWW(int obits, int, int rbits, WDataOutP owp, const WDataInP lwp, const WDataInP rwp, bool lsign, bool rsign) VL_MT_SAFE { // obits==lbits, rbits can be different - if (rsign && VL_SIGN_W(rbits, rwp)) { + if (rsign && VL_SIGN_W_T(rbits, rwp)) { const int words = VL_WORDS_I(obits); - VL_ZERO_W(obits, owp); + VL_ZERO_W_T(obits, owp); EData lor = 0; // 0=all zeros, ~0=all ones, else mix for (int i = 1; i < (words - 1); ++i) lor |= lwp[i]; lor |= ((lwp[words - 1] == VL_MASK_E(rbits)) ? ~VL_EUL(0) : 0); @@ -832,7 +878,7 @@ WDataOutP VL_POWSS_WWW(int obits, int, int rbits, WDataOutP owp, const WDataInP } if (lsign && lor == ~VL_EUL(0) && lwp[0] == ~VL_EUL(0)) { // -1 if (rwp[0] & 1) { // -1^odd=-1 - return VL_ALLONES_W(obits, owp); + return VL_ALLONES_W_T(obits, owp); } // -1^even=1 owp[0] = 1; @@ -845,13 +891,13 @@ WDataOutP VL_POWSS_WWW(int obits, int, int rbits, WDataOutP owp, const WDataInP WDataOutP VL_POWSS_WWQ(int obits, int lbits, int rbits, WDataOutP owp, const WDataInP lwp, QData rhs, bool lsign, bool rsign) VL_MT_SAFE { VlWide rhsw; - VL_SET_WQ(rhsw, rhs); + VL_SET_WQ_T(rhsw, rhs); return VL_POWSS_WWW(obits, lbits, rbits, owp, lwp, rhsw, lsign, rsign); } QData VL_POWSS_QQW(int obits, int, int rbits, QData lhs, const WDataInP rwp, bool lsign, bool rsign) VL_MT_SAFE { // Skip check for rhs == 0, as short-circuit doesn't save time - if (rsign && VL_SIGN_W(rbits, rwp)) { + if (rsign && VL_SIGN_W_T(rbits, rwp)) { if (lhs == 0) return 0; // "X" if (lhs == 1) return 1; if (lsign && lhs == VL_MASK_Q(obits)) { // -1 @@ -880,12 +926,12 @@ double VL_ITOR_D_W(int lbits, const WDataInP lwp) VL_PURE { return d; } double VL_ISTOR_D_W(int lbits, const WDataInP lwp) VL_MT_SAFE { - if (!VL_SIGN_W(lbits, lwp)) return VL_ITOR_D_W(lbits, lwp); + if (!VL_SIGN_W_T(lbits, lwp)) return VL_ITOR_D_W(lbits, lwp); const int words = VL_WORDS_I(lbits); VL_DEBUG_IFDEF(assert(words <= VL_MULS_MAX_WORDS);); VlWide pos; - VL_NEGATE_W(words, pos, lwp); - _vl_clean_inplace_w(lbits, pos); + VL_NEGATE_W_TT(words, pos, lwp); + _vl_clean_inplace_w_T(lbits, pos); return -VL_ITOR_D_W(lbits, pos); } @@ -898,7 +944,7 @@ std::string VL_DECIMAL_NW(int width, const WDataInP lwp) VL_MT_SAFE { // Or (maxdecwidth+7)/8], but can't have more than 4 BCD bits per word std::vector bcd(VL_WORDS_I(maxdecwidth)); WDataOutP bcdp = WDataOutP::external(bcd.data()); - VL_ZERO_W(maxdecwidth, bcdp); + VL_ZERO_W_T(maxdecwidth, bcdp); std::vector tmp(VL_WORDS_I(maxdecwidth)); std::vector tmp2(VL_WORDS_I(maxdecwidth)); WDataOutP tmpp = WDataOutP::external(tmp.data()); @@ -911,15 +957,15 @@ std::string VL_DECIMAL_NW(int width, const WDataInP lwp) VL_MT_SAFE { // Any digits >= 5 need an add 3 (via tmp) for (int nibble_bit = 0; nibble_bit < maxdecwidth; nibble_bit += 4) { if ((VL_BITRSHIFT_W(bcd, nibble_bit) & 0xf) >= 5) { - VL_ZERO_W(maxdecwidth, tmp2p); + VL_ZERO_W_T(maxdecwidth, tmp2p); tmp2[VL_BITWORD_E(nibble_bit)] |= VL_EUL(0x3) << VL_BITBIT_E(nibble_bit); - VL_ASSIGN_W(maxdecwidth, tmpp, bcdp); - VL_ADD_W(VL_WORDS_I(maxdecwidth), bcdp, tmpp, tmp2p); + VL_ASSIGN_W_TT(maxdecwidth, tmpp, bcdp); + VL_ADD_W_TTT(VL_WORDS_I(maxdecwidth), bcdp, tmpp, tmp2p); } } // Shift; bcd = bcd << 1 - VL_ASSIGN_W(maxdecwidth, tmpp, bcdp); - VL_SHIFTL_WWI(maxdecwidth, maxdecwidth, 32, bcdp, tmpp, 1); + VL_ASSIGN_W_TT(maxdecwidth, tmpp, bcdp); + VL_SHIFTL_WWI_TTT(maxdecwidth, maxdecwidth, 32, bcdp, tmpp, 1); // bcd[0] = lwp[from_bit] if (VL_BITISSET_W(lwp, from_bit)) bcd[0] |= 1; } @@ -951,36 +997,36 @@ std::string _vl_vsformat_time(std::string& tmp, T ld, int timeunit, bool left, VlWide tmp2; VlWide tmp3; - WDataInP shifted = VL_EXTEND_WQ(b, 0, tmp0, static_cast(ld)); + WDataInP shifted = VL_EXTEND_WQ_TT(b, 0, tmp0, static_cast(ld)); if (shift < 0) { - const WDataInP pow10 = VL_EXTEND_WQ(b, 0, tmp1, vl_time_pow10(-shift)); - shifted = VL_DIV_WWW(b, tmp2, shifted, pow10); + const WDataInP pow10 = VL_EXTEND_WQ_TT(b, 0, tmp1, vl_time_pow10(-shift)); + shifted = VL_DIV_WWW_TTT(b, tmp2, shifted, pow10); } else { - const WDataInP pow10 = VL_EXTEND_WQ(b, 0, tmp1, vl_time_pow10(shift)); - shifted = VL_MUL_W(w, tmp2, shifted, pow10); + const WDataInP pow10 = VL_EXTEND_WQ_TT(b, 0, tmp1, vl_time_pow10(shift)); + shifted = VL_MUL_W_TTT(w, tmp2, shifted, pow10); } - const WDataInP fracDigitsPow10 = VL_EXTEND_WQ(b, 0, tmp3, vl_time_pow10(fracDigits)); - const WDataInP integer = VL_DIV_WWW(b, tmp0, shifted, fracDigitsPow10); - const WDataInP frac = VL_MODDIV_WWW(b, tmp1, shifted, fracDigitsPow10); + const WDataInP fracDigitsPow10 = VL_EXTEND_WQ_TT(b, 0, tmp3, vl_time_pow10(fracDigits)); + const WDataInP integer = VL_DIV_WWW_TTT(b, tmp0, shifted, fracDigitsPow10); + const WDataInP frac = VL_MODDIV_WWW_TTT(b, tmp1, shifted, fracDigitsPow10); const WDataInP max64Bit - = VL_EXTEND_WQ(b, 0, tmp2, std::numeric_limits::max()); // breaks shifted - if (VL_GT_W(w, integer, max64Bit)) { - WDataOutP v = VL_ASSIGN_W(b, tmp3, integer); // breaks fracDigitsPow10 + = VL_EXTEND_WQ_TT(b, 0, tmp2, std::numeric_limits::max()); // breaks shifted + if (VL_GT_W_TT(w, integer, max64Bit)) { + WDataOutP v = VL_ASSIGN_W_TT(b, tmp3, integer); // breaks fracDigitsPow10 VlWide zero; VlWide ten; - VL_ZERO_W(b, zero); - VL_EXTEND_WI(b, 0, ten, 10); + VL_ZERO_W_T(b, zero); + VL_EXTEND_WI_TT(b, 0, ten, 10); char buf[128]; // 128B is obviously long enough to represent 128bit integer in decimal char* ptr = buf + sizeof(buf) - 1; *ptr = '\0'; - while (VL_GT_W(w, v, zero)) { + while (VL_GT_W_TT(w, v, zero)) { --ptr; - const WDataInP mod = VL_MODDIV_WWW(b, tmp2, v, ten); // breaks max64Bit + const WDataInP mod = VL_MODDIV_WWW_TTT(b, tmp2, v, ten); // breaks max64Bit *ptr = "0123456789"[VL_SET_QW(mod)]; VlWide divided; - VL_DIV_WWW(b, divided, v, ten); - VL_ASSIGN_W(b, v, divided); + VL_DIV_WWW_TTT(b, divided, v, ten); + VL_ASSIGN_W_TT(b, v, divided); } if (!fracDigits) { digits = _vl_snprintf_string(tmp, "%s%s", ptr, suffix.c_str()); @@ -1166,7 +1212,7 @@ void _vl_vsformat(std::string& output, const std::string& format, int argc, ld = VL_RTOIROUND_Q_D(real); strwide.resize(2); WDataOutP strwidep = WDataOutP::external(strwide.data()); - VL_SET_WQ(strwidep, ld); + VL_SET_WQ_T(strwidep, ld); lwp = strwidep; lbits = 64; // Not changint fmt == 'p' to fmt = 'g', as need fmts correct @@ -1179,7 +1225,7 @@ void _vl_vsformat(std::string& output, const std::string& format, int argc, ld = VL_VA_ARG_Q_(ap, lbits); strwide.resize(2); WDataOutP strwidep = WDataOutP::external(strwide.data()); - VL_SET_WQ(strwidep, ld); + VL_SET_WQ_T(strwidep, ld); lwp = strwidep; lsb = lbits - 1; ++argn; // Enum value is followed by the generated name string argument @@ -1207,7 +1253,7 @@ void _vl_vsformat(std::string& output, const std::string& format, int argc, ld = VL_VA_ARG_Q_(ap, lbits); strwide.resize(2); WDataOutP strwidep = WDataOutP::external(strwide.data()); - VL_SET_WQ(strwidep, ld); + VL_SET_WQ_T(strwidep, ld); lwp = strwidep; } else { lwp = WDataInP::external(va_arg(ap, EData*)); @@ -1291,13 +1337,13 @@ void _vl_vsformat(std::string& output, const std::string& format, int argc, if (lbits <= VL_QUADSIZE) { digits = _vl_snprintf_string( t_tmp, "%" PRId64, - static_cast(VL_EXTENDS_QQ(lbits, lbits, ld))); + static_cast(VL_EXTENDS_QQ_TT(lbits, lbits, ld))); append = t_tmp; } else { - if (VL_SIGN_E(lbits, lwp[VL_WORDS_I(lbits) - 1])) { + if (VL_SIGN_E_T(lbits, lwp[VL_WORDS_I(lbits) - 1])) { std::vector neg(VL_WORDS_I(lbits)); WDataOutP negp = WDataOutP::external(neg.data()); - VL_NEGATE_W(VL_WORDS_I(lbits), negp, lwp); + VL_NEGATE_W_TT(VL_WORDS_I(lbits), negp, lwp); append = "-"s + VL_DECIMAL_NW(lbits, negp); } else { append = VL_DECIMAL_NW(lbits, lwp); @@ -1372,7 +1418,7 @@ void _vl_vsformat(std::string& output, const std::string& format, int argc, } if (widthSet || left) { - lsb = VL_MOSTSETBITP1_W(VL_WORDS_I(lbits), lwp); + lsb = VL_MOSTSETBITP1_W_T(VL_WORDS_I(lbits), lwp); lsb = (lsb < 1) ? 0 : (lsb - 1); } @@ -1527,7 +1573,7 @@ static void _vl_vsss_setbit(WDataOutP iowp, int obits, int lsb, int nbits, IData void _vl_vsss_based(WDataOutP owp, int obits, int baseLog2, const char* strp, size_t posstart, size_t posend) VL_MT_SAFE { // Read in base "2^^baseLog2" digits from strp[posstart..posend-1] into owp of size obits. - VL_ZERO_W(obits, owp); + VL_ZERO_W_T(obits, owp); int lsb = 0; for (int i = 0, pos = static_cast(posend) - 1; i < obits && pos >= static_cast(posstart); --pos, ++i) { @@ -1648,7 +1694,7 @@ IData _vl_vsscanf(FILE* fp, // If a fscanf double real = 0; VlWide qowp; - VL_SET_WQ(qowp, 0ULL); + VL_SET_WQ_T(qowp, 0ULL); WDataOutP owp = WDataOutP::external((obits <= 64) ? qowp.data() : static_cast(thingp)); @@ -1684,11 +1730,11 @@ IData _vl_vsscanf(FILE* fp, // If a fscanf if (formatAttr == VL_VFORMATATTR_SIGNED) { QData ld = 0; std::sscanf(t_tmp.c_str(), "%30" PRIu64, &ld); - VL_SET_WQ(owp, ld); + VL_SET_WQ_T(owp, ld); } else if (formatAttr == VL_VFORMATATTR_UNSIGNED) { int64_t ld = 0; std::sscanf(t_tmp.c_str(), "%30" PRId64, &ld); - VL_SET_WQ(owp, ld); + VL_SET_WQ_T(owp, ld); } break; } @@ -1706,7 +1752,7 @@ IData _vl_vsscanf(FILE* fp, // If a fscanf } u; real = std::strtod(t_tmp.c_str(), nullptr); u.r = real; - VL_SET_WQ(owp, u.ld); + VL_SET_WQ_T(owp, u.ld); break; } case 't': { // Time @@ -1720,7 +1766,7 @@ IData _vl_vsscanf(FILE* fp, // If a fscanf // 0..-15 const int shift = -userUnits + timeunit; // 0..-15 real = std::strtod(t_tmp.c_str(), nullptr) * vl_time_multiplier(-shift); - VL_SET_WQ(owp, static_cast(real)); + VL_SET_WQ_T(owp, static_cast(real)); break; } case 'b': { @@ -1807,7 +1853,7 @@ IData _vl_vsscanf(FILE* fp, // If a fscanf QData* const p = static_cast(thingp); *p = VL_CLEAN_QQ(obits, obits, VL_SET_QW(owp)); } else { - _vl_clean_inplace_w(obits, owp); + _vl_clean_inplace_w_T(obits, owp); } } } // switch @@ -2137,7 +2183,7 @@ IData VL_SSCANF_IINX(int lbits, IData ld, const std::string& format, int argc, . } IData VL_SSCANF_IQNX(int lbits, QData ld, const std::string& format, int argc, ...) VL_MT_SAFE { VlWide fnw; - VL_SET_WQ(fnw, ld); + VL_SET_WQ_T(fnw, ld); va_list ap; va_start(ap, argc); @@ -2245,7 +2291,7 @@ IData VL_FREAD_I(int width, int array_lsb, int array_size, void* memp, IData fpi } else { const WDataOutP datap = WDataOutP::external( &(reinterpret_cast(memp))[entry * VL_WORDS_I(width)]); - if (shift == start_shift) VL_ZERO_W(width, datap); + if (shift == start_shift) VL_ZERO_W_T(width, datap); datap[VL_BITWORD_E(shift)] |= (static_cast(c) << VL_BITBIT_E(shift)); } // Prep for next @@ -2331,7 +2377,7 @@ void VL_STACKTRACE() VL_MT_SAFE { IData VL_SYSTEM_IQ(QData lhs) VL_MT_SAFE { VlWide lhsw; - VL_SET_WQ(lhsw, lhs); + VL_SET_WQ_T(lhsw, lhs); return VL_SYSTEM_IW(VL_WQ_WORDS_E, lhsw); } IData VL_SYSTEM_IW(int lhswords, const WDataInP lhsp) VL_MT_SAFE { @@ -2383,12 +2429,12 @@ IData VL_VALUEPLUSARGS_INW(int rbits, const std::string& ld, WDataOutP rwp) VL_M const char* const dp = match.c_str() + 1 /*leading + */ + prefix.length(); if (match.empty()) return 0; - VL_ZERO_W(rbits, rwp); + VL_ZERO_W_T(rbits, rwp); switch (std::tolower(fmt)) { case 'd': { int64_t lld = 0; std::sscanf(dp, "%30" PRId64, &lld); - VL_SET_WQ(rwp, lld); + VL_SET_WQ_T(rwp, lld); break; } case 'b': _vl_vsss_based(rwp, rbits, 1, dp, 0, std::strlen(dp)); break; @@ -2406,25 +2452,25 @@ IData VL_VALUEPLUSARGS_INW(int rbits, const std::string& ld, WDataOutP rwp) VL_M case 'e': { double temp = 0.F; std::sscanf(dp, "%le", &temp); - VL_SET_WQ(rwp, VL_CVT_Q_D(temp)); + VL_SET_WQ_T(rwp, VL_CVT_Q_D(temp)); break; } case 'f': { double temp = 0.F; std::sscanf(dp, "%lf", &temp); - VL_SET_WQ(rwp, VL_CVT_Q_D(temp)); + VL_SET_WQ_T(rwp, VL_CVT_Q_D(temp)); break; } case 'g': { double temp = 0.F; std::sscanf(dp, "%lg", &temp); - VL_SET_WQ(rwp, VL_CVT_Q_D(temp)); + VL_SET_WQ_T(rwp, VL_CVT_Q_D(temp)); break; } default: // Other simulators return 0 in these cases and don't error out return 0; } - _vl_clean_inplace_w(rbits, rwp); + _vl_clean_inplace_w_T(rbits, rwp); return 1; } IData VL_VALUEPLUSARGS_INN(int, const std::string& ld, std::string& rdr) VL_MT_SAFE { @@ -2744,7 +2790,7 @@ void VlReadMem::setData(void* valuep, const std::string& rhs) { & VL_MASK_Q(m_bits); } else { const WDataOutP datap = WDataOutP::external(reinterpret_cast(valuep)); - if (!innum) VL_ZERO_W(m_bits, datap); + if (!innum) VL_ZERO_W_T(m_bits, datap); _vl_shiftl_inplace_w(m_bits, datap, static_cast(shift)); datap[0] |= value; } diff --git a/include/verilated_dpi.cpp b/include/verilated_dpi.cpp index 23abb4594..7859603e6 100644 --- a/include/verilated_dpi.cpp +++ b/include/verilated_dpi.cpp @@ -286,7 +286,7 @@ static void _vl_svGetBitArrElemVecVal(svBitVecVal* d, const svOpenArrayHandle s, case VLVT_UINT32: d[0] = *(reinterpret_cast(datap)); return; case VLVT_UINT64: { VlWide<2> lwp; - VL_SET_WQ(lwp, *(reinterpret_cast(datap))); + VL_SET_WQ_T(lwp, *(reinterpret_cast(datap))); d[0] = lwp[0]; d[1] = lwp[1]; break; @@ -323,7 +323,7 @@ static void _vl_svGetLogicArrElemVecVal(svLogicVecVal* d, const svOpenArrayHandl return; case VLVT_UINT64: { VlWide<2> lwp; - VL_SET_WQ(lwp, *(reinterpret_cast(datap))); + VL_SET_WQ_T(lwp, *(reinterpret_cast(datap))); d[0].aval = lwp[0]; d[0].bval = 0; d[1].aval = lwp[1]; @@ -781,7 +781,7 @@ int svGetTime(const svScope /*scope*/, svTimeVal* time) { if (VL_UNLIKELY(!time)) return -1; const QData qtime = VL_TIME_Q(); VlWide<2> itime; - VL_SET_WQ(itime, qtime); + VL_SET_WQ_T(itime, qtime); time->low = itime[0]; time->high = itime[1]; return 0; diff --git a/include/verilated_dpi.h b/include/verilated_dpi.h index fd8f177ee..0d7ac75d3 100644 --- a/include/verilated_dpi.h +++ b/include/verilated_dpi.h @@ -63,7 +63,7 @@ static inline void VL_SET_SVBV_W(int obits, svBitVecVal* owp, const WDataInP lwp } static inline void VL_SET_SVBV_I(int, svBitVecVal* owp, const IData ld) VL_MT_SAFE { owp[0] = ld; } static inline void VL_SET_SVBV_Q(int, svBitVecVal* owp, const QData ld) VL_MT_SAFE { - VL_SET_WQ(WDataOutP::external(owp), ld); + VL_SET_WQ_T(WDataOutP::external(owp), ld); } // Convert svLogicVecVal to Verilator internal data @@ -100,7 +100,7 @@ static inline void VL_SET_SVLV_I(int, svLogicVecVal* owp, const IData ld) VL_MT_ } static inline void VL_SET_SVLV_Q(int, svLogicVecVal* owp, const QData ld) VL_MT_SAFE { VlWide<2> lwp; - VL_SET_WQ(lwp, ld); + VL_SET_WQ_T(lwp, ld); owp[0].aval = lwp[0]; owp[0].bval = 0; owp[1].aval = lwp[1]; diff --git a/include/verilated_force.h b/include/verilated_force.h index 5cbafdc62..c5a3d8afe 100644 --- a/include/verilated_force.h +++ b/include/verilated_force.h @@ -182,7 +182,7 @@ private: } WDataInP rhswp = WDataInP::external(static_cast(entry.m_rhsDatap)); - return VL_SEL_QWII(rhsWidth, rhswp, rhsLsb, width) & mask; + return VL_SEL_QWII_TTTT(rhsWidth, rhswp, rhsLsb, width) & mask; } template @@ -260,7 +260,7 @@ private: } void readSel(int lbits, WDataInP valp, WDataOutP reswp, int lsb, int width) const { - VL_SEL_WWII(width, lbits, reswp, valp, lsb, width); + VL_SEL_WWII_TTTT(width, lbits, reswp, valp, lsb, width); const int msb = lsb + width - 1; auto it = std::lower_bound(m_entries.begin(), m_entries.end(), lsb, [](const Entry& e, int bit) { return e.m_msb < bit; }); diff --git a/include/verilated_fst_c.cpp b/include/verilated_fst_c.cpp index 0e3706725..081538dce 100644 --- a/include/verilated_fst_c.cpp +++ b/include/verilated_fst_c.cpp @@ -383,6 +383,14 @@ void VerilatedFstBuffer::emitBit(uint32_t code, CData newval) { m_fst->emitValueChange(m_symbolp[code], uint64_t(newval)); } +VL_ATTR_ALWINLINE +void VerilatedFstBuffer::emitLogic(uint32_t code, CData newval, CData newvalXZ) { + VL_DEBUG_IFDEF(assert(m_symbolp[code]);); // LCOV_EXCL_BR_LINE + m_owner.emitTimeChangeMaybe(); + const uint32_t newvals[2] = {static_cast(newval), static_cast(newvalXZ)}; + m_fst->emitValueChange(m_symbolp[code], newvals, fst::EncodingType::VERILOG); +} + VL_ATTR_ALWINLINE void VerilatedFstBuffer::emitCData(uint32_t code, CData newval, int) { VL_DEBUG_IFDEF(assert(m_symbolp[code]);); // LCOV_EXCL_BR_LINE @@ -390,6 +398,14 @@ void VerilatedFstBuffer::emitCData(uint32_t code, CData newval, int) { m_fst->emitValueChange(m_symbolp[code], newval); } +VL_ATTR_ALWINLINE +void VerilatedFstBuffer::emitFourstateCData(uint32_t code, CData newval, CData newvalXZ, int) { + VL_DEBUG_IFDEF(assert(m_symbolp[code]);); // LCOV_EXCL_BR_LINE + m_owner.emitTimeChangeMaybe(); + const uint32_t newvals[2] = {static_cast(newval), static_cast(newvalXZ)}; + m_fst->emitValueChange(m_symbolp[code], newvals, fst::EncodingType::VERILOG); +} + VL_ATTR_ALWINLINE void VerilatedFstBuffer::emitSData(uint32_t code, SData newval, int) { VL_DEBUG_IFDEF(assert(m_symbolp[code]);); // LCOV_EXCL_BR_LINE @@ -397,6 +413,14 @@ void VerilatedFstBuffer::emitSData(uint32_t code, SData newval, int) { m_fst->emitValueChange(m_symbolp[code], newval); } +VL_ATTR_ALWINLINE +void VerilatedFstBuffer::emitFourstateSData(uint32_t code, SData newval, SData newvalXZ, int) { + VL_DEBUG_IFDEF(assert(m_symbolp[code]);); // LCOV_EXCL_BR_LINE + m_owner.emitTimeChangeMaybe(); + const uint32_t newvals[2] = {static_cast(newval), static_cast(newvalXZ)}; + m_fst->emitValueChange(m_symbolp[code], newvals, fst::EncodingType::VERILOG); +} + VL_ATTR_ALWINLINE void VerilatedFstBuffer::emitIData(uint32_t code, IData newval, int) { VL_DEBUG_IFDEF(assert(m_symbolp[code]);); // LCOV_EXCL_BR_LINE @@ -404,6 +428,14 @@ void VerilatedFstBuffer::emitIData(uint32_t code, IData newval, int) { m_fst->emitValueChange(m_symbolp[code], newval); } +VL_ATTR_ALWINLINE +void VerilatedFstBuffer::emitFourstateIData(uint32_t code, IData newval, IData newvalXZ, int) { + VL_DEBUG_IFDEF(assert(m_symbolp[code]);); // LCOV_EXCL_BR_LINE + m_owner.emitTimeChangeMaybe(); + const uint32_t newvals[2] = {newval, newvalXZ}; + m_fst->emitValueChange(m_symbolp[code], newvals, fst::EncodingType::VERILOG); +} + VL_ATTR_ALWINLINE void VerilatedFstBuffer::emitQData(uint32_t code, QData newval, int) { VL_DEBUG_IFDEF(assert(m_symbolp[code]);); // LCOV_EXCL_BR_LINE @@ -412,12 +444,28 @@ void VerilatedFstBuffer::emitQData(uint32_t code, QData newval, int) { } VL_ATTR_ALWINLINE -void VerilatedFstBuffer::emitWData(uint32_t code, WDataInP newval, int) { +void VerilatedFstBuffer::emitFourstateQData(uint32_t code, QData newval, QData newvalXZ, int) { + VL_DEBUG_IFDEF(assert(m_symbolp[code]);); // LCOV_EXCL_BR_LINE + m_owner.emitTimeChangeMaybe(); + const uint64_t newvals[2] = {newval, newvalXZ}; + m_fst->emitValueChange(m_symbolp[code], newvals, fst::EncodingType::VERILOG); +} + +VL_ATTR_ALWINLINE +void VerilatedFstBuffer::emitWData(uint32_t code, const WDataInP newval, int) { VL_DEBUG_IFDEF(assert(m_symbolp[code]);); // LCOV_EXCL_BR_LINE m_owner.emitTimeChangeMaybe(); m_fst->emitValueChange(m_symbolp[code], newval.datap()); } +VL_ATTR_ALWINLINE +void VerilatedFstBuffer::emitFourstateWData(uint32_t code, const WDataInP newval, int) { + VL_DEBUG_IFDEF(assert(m_symbolp[code]);); // LCOV_EXCL_BR_LINE + m_owner.emitTimeChangeMaybe(); + // call emitValueChange(handle, uint32_t*) + m_fst->emitValueChange(m_symbolp[code], newval); +} + VL_ATTR_ALWINLINE void VerilatedFstBuffer::emitDouble(uint32_t code, double newval) { VL_DEBUG_IFDEF(assert(m_symbolp[code]);); // LCOV_EXCL_BR_LINE diff --git a/include/verilated_fst_c.h b/include/verilated_fst_c.h index de1b0eeca..09cafda6d 100644 --- a/include/verilated_fst_c.h +++ b/include/verilated_fst_c.h @@ -228,11 +228,17 @@ class VerilatedFstBuffer VL_NOT_FINAL { // called from only one place (the full* methods), so always inline them. VL_ATTR_ALWINLINE void emitEvent(uint32_t code); VL_ATTR_ALWINLINE void emitBit(uint32_t code, CData newval); + VL_ATTR_ALWINLINE void emitLogic(uint32_t code, CData newval, CData newvalXZ); VL_ATTR_ALWINLINE void emitCData(uint32_t code, CData newval, int); + VL_ATTR_ALWINLINE void emitFourstateCData(uint32_t code, CData newval, CData newvalXZ, int); VL_ATTR_ALWINLINE void emitSData(uint32_t code, SData newval, int); + VL_ATTR_ALWINLINE void emitFourstateSData(uint32_t code, SData newval, SData newvalXZ, int); VL_ATTR_ALWINLINE void emitIData(uint32_t code, IData newval, int); + VL_ATTR_ALWINLINE void emitFourstateIData(uint32_t code, IData newval, IData newvalXZ, int); VL_ATTR_ALWINLINE void emitQData(uint32_t code, QData newval, int); + VL_ATTR_ALWINLINE void emitFourstateQData(uint32_t code, QData newval, QData newvalXZ, int); VL_ATTR_ALWINLINE void emitWData(uint32_t code, WDataInP newval, int); + VL_ATTR_ALWINLINE void emitFourstateWData(uint32_t code, WDataInP newval, int); VL_ATTR_ALWINLINE void emitDouble(uint32_t code, double newval); }; diff --git a/include/verilated_funcs.h b/include/verilated_funcs.h index 88da40387..e7c7ff253 100644 --- a/include/verilated_funcs.h +++ b/include/verilated_funcs.h @@ -28,6 +28,7 @@ #error "verilated_funcs.h should only be included by verilated.h" #endif +#include #include //========================================================================= @@ -59,6 +60,86 @@ extern void vl_fatal(const char* filename, int linenum, const char* hier, extern void vl_warn(const char* filename, int linenum, const char* hier, const char* msg) VL_MT_UNSAFE; +//========================================================================= +// Generator helpers + +// clang-format off +#define VL_GEN_HELPER_ONE_ARG(macro) \ + macro(T) \ + macro(V) \ + macro(X) + +#define VL_GEN_HELPER_TWO_ARG(macro) \ + macro(T, T) \ + macro(T, V) \ + macro(T, X) \ + macro(V, T) \ + macro(V, V) \ + macro(V, X) \ + macro(X, T) \ + macro(X, V) \ + macro(X, X) + +#define VL_GEN_HELPER_THREE_ARG(macro) \ + macro(T, T, T) \ + macro(T, T, V) \ + macro(T, T, X) \ + macro(T, V, T) \ + macro(T, V, V) \ + macro(T, V, X) \ + macro(T, X, T) \ + macro(T, X, V) \ + macro(T, X, X) \ + macro(V, T, T) \ + macro(V, T, V) \ + macro(V, T, X) \ + macro(V, V, T) \ + macro(V, V, V) \ + macro(V, V, X) \ + macro(V, X, T) \ + macro(V, X, V) \ + macro(V, X, X) \ + macro(X, T, T) \ + macro(X, T, V) \ + macro(X, T, X) \ + macro(X, V, T) \ + macro(X, V, V) \ + macro(X, V, X) \ + macro(X, X, T) \ + macro(X, X, V) \ + macro(X, X, X) +// clang-format on + +#define VL_TYPE_OFFSET_T (0) +#define VL_TYPE_OFFSET_V (0) +#define VL_TYPE_OFFSET_X (1) +#define VL_GET_TYPE_OFFSET(c) (VL_TYPE_OFFSET_##c) +#define VL_TYPE_JUMP_T (1) +#define VL_TYPE_JUMP_V (2) +#define VL_TYPE_JUMP_X (2) +#define VL_GET_TYPE_JUMP(c) (VL_TYPE_JUMP_##c) +// This is suboptimal since it calculates position everytime - we shall preferably just move +// pointers +#define VL_GET_ELEM(suffix, val, idx) \ + ((val) + static_cast(VL_GET_TYPE_OFFSET(suffix) + ((idx) * VL_GET_TYPE_JUMP(suffix)))) +#define VL_IF_VX_HELPER_T(stmt) \ + do { \ + } while (false); +#define VL_IF_VX_HELPER_V(stmt) \ + do { stmt } while (false); +#define VL_IF_VX_HELPER_X(stmt) \ + do { stmt } while (false); +#define VL_IF_VX(suffix, stmt) VL_IF_VX_HELPER_##suffix(stmt) +#define VL_IF_T_HELPER_T(stmt) \ + do { stmt } while (false); +#define VL_IF_T_HELPER_V(stmt) \ + do { \ + } while (false); +#define VL_IF_T_HELPER_X(stmt) \ + do { \ + } while (false); +#define VL_IF_T(suffix, stmt) VL_IF_T_HELPER_##suffix(stmt) + //========================================================================= // Extern functions -- Slow path @@ -104,6 +185,9 @@ inline IData VL_URANDOM_RANGE_I(IData hi, IData lo) { return (rnd % (lo - hi + 1)) + hi; } +// Random resets do not need four-state flavor since they are used to initialize x/z in two-state +// mode and x/z in four-state mode are just themselves + /// Random reset a signal of given width (init time only, var-specific PRNG) extern IData VL_SCOPED_RAND_RESET_I(int obits, uint64_t scopeHash, uint64_t salt) VL_MT_UNSAFE; /// Random reset a signal of given width (init time only, var-specific PRNG) @@ -130,13 +214,19 @@ extern QData VL_RAND_RESET_Q(int obits) VL_MT_SAFE; extern WDataOutP VL_RAND_RESET_W(int obits, WDataOutP outwp) VL_MT_SAFE; /// Zero reset a signal (slow - else use VL_ZERO_W) -extern WDataOutP VL_ZERO_RESET_W(int obits, WDataOutP outwp) VL_MT_SAFE; +extern WDataOutP VL_ZERO_RESET_W_T(int obits, WDataOutP outwp) VL_MT_SAFE; +extern WDataOutP VL_ZERO_RESET_W_V(int obits, WDataOutP outwp) VL_MT_SAFE; +extern WDataOutP VL_ZERO_RESET_W_X(int obits, WDataOutP outwp) VL_MT_SAFE; +extern WDataOutP VL_ALLONES_RESET_W_T(int obits, WDataOutP outwp) VL_MT_SAFE; +extern WDataOutP VL_ALLONES_RESET_W_V(int obits, WDataOutP outwp) VL_MT_SAFE; +extern WDataOutP VL_ALLONES_RESET_W_X(int obits, WDataOutP outwp) VL_MT_SAFE; extern void VL_PRINTTIMESCALE(const char* namep, const char* timeunitp, const VerilatedContext* contextp) VL_MT_SAFE; -extern WDataOutP _vl_moddiv_w(int lbits, WDataOutP owp, WDataInP const lwp, WDataInP const rwp, - bool is_modulus) VL_MT_SAFE; +extern WDataOutP _vl_moddiv_w(int lbits, WDataOutP owp, WDataInP lwp, WDataInP rwp, + bool is_modulus, int outputOffset, int outputJump, int lhsOffset, + int lhsJump, int rhsOffset, int rhsJump) VL_MT_SAFE; extern void _vl_vsss_based(WDataOutP owp, int obits, int baseLog2, const char* strp, size_t posstart, size_t posend) VL_MT_SAFE; @@ -209,20 +299,30 @@ extern const char* vl_mc_scan_plusargs(const char* prefixp) VL_MT_SAFE; // PLIi #define VL_BITRSHIFT_W(data, bit) ((data)[VL_BITWORD_E(bit)] >> VL_BITBIT_E(bit)) // Create two 32-bit words from quadword -// VLWide is always at least 2 words; does not clean upper bits -static inline WDataOutP VL_SET_WQ(WDataOutP owp, QData data) VL_PURE { - owp[0] = static_cast(data); - owp[1] = static_cast(data >> VL_EDATASIZE); - return owp; -} -static inline WDataOutP VL_SET_WI(WDataOutP owp, IData data) VL_PURE { - owp[0] = static_cast(data); - owp[1] = 0; - return owp; -} -static inline QData VL_SET_QW(WDataInP lwp) VL_PURE { - return (static_cast(lwp[1]) << VL_EDATASIZE) | static_cast(lwp[0]); -} +// WData is always at least 2 words; does not clean upper bits +#define VL_SET_WQ_T(owp, data) \ + do { \ + (owp)[0] = static_cast(data); \ + (owp)[1] = static_cast((data) >> VL_EDATASIZE); \ + } while (false) +#define VL_SET_WQ_V(owp, data) \ + do { \ + (owp)[VL_TYPE_OFFSET_V] = static_cast(data); \ + (owp)[VL_TYPE_OFFSET_V + VL_TYPE_JUMP_V] = static_cast((data) >> VL_EDATASIZE); \ + } while (false) +#define VL_SET_WQ_X(owp, data) \ + do { \ + (owp)[VL_TYPE_OFFSET_X] = static_cast(data); \ + (owp)[VL_TYPE_OFFSET_X + VL_TYPE_JUMP_X] = static_cast((data) >> VL_EDATASIZE); \ + } while (false) +#define VL_SET_WI(owp, data) \ + do { \ + (owp)[0] = static_cast(data); \ + (owp)[1] = 0; \ + } while (false) +#define VL_SET_QW(lwp) \ + ((static_cast((lwp)[0])) \ + | (static_cast((lwp)[1]) << (static_cast(VL_EDATASIZE)))) #define VL_SET_QII(ld, rd) ((static_cast(ld) << 32ULL) | static_cast(rd)) // Return FILE* from IData @@ -323,7 +423,7 @@ static inline double VL_ISTOR_D_I(int lbits, IData lhs) VL_MT_SAFE { static inline double VL_ISTOR_D_Q(int lbits, QData lhs) VL_MT_SAFE { if (lbits == 64) return static_cast(static_cast(lhs)); VlWide lwp; - VL_SET_WQ(lwp, lhs); + VL_SET_WQ_T(lwp, lhs); return VL_ISTOR_D_W(lbits, lwp); } // Return IData truncated from double (numeric) @@ -331,12 +431,16 @@ static inline IData VL_RTOI_I_D(double lhs) VL_PURE { return static_cast> VL_BITBIT_I((nbits) - VL_UL(1))) -#define VL_SIGN_Q(nbits, lhs) ((lhs) >> VL_BITBIT_Q((nbits) - 1ULL)) -#define VL_SIGN_E(nbits, lhs) ((lhs) >> VL_BITBIT_E((nbits) - VL_EUL(1))) -#define VL_SIGN_W(nbits, rwp) \ +#define VL_SIGN_I_T(nbits, lhs) ((lhs) >> VL_BITBIT_I((nbits) - VL_UL(1))) +#define VL_SIGN_Q_T(nbits, lhs) ((lhs) >> VL_BITBIT_Q((nbits) - 1ULL)) +#define VL_SIGN_E_T(nbits, lhs) ((lhs) >> VL_BITBIT_E((nbits) - VL_EUL(1))) +#define VL_SIGN_W_T(nbits, rwp) \ ((rwp)[VL_BITWORD_E((nbits) - VL_EUL(1))] >> VL_BITBIT_E((nbits) - VL_EUL(1))) -#define VL_SIGNONES_E(nbits, lhs) (-(VL_SIGN_E(nbits, lhs))) +#define VL_SIGN_W_V(nbits, rwp) \ + ((rwp)[VL_BITWORD_E((nbits) - VL_EUL(1)) << 1] >> VL_BITBIT_E((nbits) - VL_EUL(1))) +#define VL_SIGN_W_X(nbits, rwp) \ + ((rwp)[(VL_BITWORD_E((nbits) - VL_EUL(1)) << 1) + 1] >> VL_BITBIT_E((nbits) - VL_EUL(1))) +#define VL_SIGNONES_E(nbits, lhs) (-(VL_SIGN_E_T(nbits, lhs))) // Sign bit extended up to MSB, doesn't include unsigned portion // Optimization bug in GCC 3.3 returns different bitmasks to later states for @@ -445,36 +549,107 @@ static WDataOutP VL_MEMCPY_W(WDataOutP owp, WDataInP const iwp, int words) VL_MT #define VL_CLEAN_II(obits, lbits, lhs) ((lhs) & (VL_MASK_I(obits))) #define VL_CLEAN_QQ(obits, lbits, lhs) ((lhs) & (VL_MASK_Q(obits))) -// EMIT_RULE: VL_ASSIGNCLEAN: oclean=clean; obits==lbits; -#define VL_ASSIGNCLEAN_W(obits, owp, lwp) VL_CLEAN_WW((obits), (owp), (lwp)) -static inline WDataOutP _vl_clean_inplace_w(int obits, WDataOutP owp) VL_MT_SAFE { - const int words = VL_WORDS_I(obits); - owp[words - 1] &= VL_MASK_E(obits); - return owp; -} -static inline WDataOutP VL_CLEAN_WW(int obits, WDataOutP owp, WDataInP const lwp) VL_MT_SAFE { - const int words = VL_WORDS_I(obits); - VL_MEMCPY_W(owp, lwp, words - 1); - owp[words - 1] = lwp[words - 1] & VL_MASK_E(obits); - return owp; -} -static inline WDataOutP VL_ZERO_W(int obits, WDataOutP owp) VL_MT_SAFE { +// clang-format off +#define _vl_clean_inplace_w_GEN(outputSuffix) \ +static inline WDataOutP _vl_clean_inplace_w_##outputSuffix(int obits, WDataOutP owp) \ + VL_MT_SAFE { \ + const int words = VL_WORDS_I(obits); \ + *VL_GET_ELEM(outputSuffix, owp, words - 1) &= VL_MASK_E(obits); \ + return owp; \ + } +// clang-format on +VL_GEN_HELPER_ONE_ARG(_vl_clean_inplace_w_GEN) +#undef _vl_clean_inplace_w_GEN + +static inline WDataOutP VL_ZERO_W_T(int obits, WDataOutP owp) VL_MT_SAFE { return VL_MEMSET_ZERO_W(owp, VL_WORDS_I(obits)); } -static inline WDataOutP VL_ALLONES_W(int obits, WDataOutP owp) VL_MT_SAFE { + +// clang-format off +#define VL_ZERO_W_GEN(outputSuffix) \ +static inline WDataOutP VL_ZERO_W_##outputSuffix(int obits, WDataOutP owp) VL_MT_SAFE { \ + const WDataOutP resultp = owp; \ + owp += VL_GET_TYPE_OFFSET(outputSuffix); \ + for (int i = 0; i < VL_WORDS_I(obits); ++i) { \ + /* VL_MEMSET_ZERO_W is used because it uses std::memset which is kind of special \ + * since if no read from memory written by std::memset occur std::memset may be \ + * optimized away */ \ + VL_MEMSET_ZERO_W(owp, 1); \ + owp += VL_GET_TYPE_JUMP(outputSuffix); \ + } \ + return resultp; \ + } +// clang-format on +VL_ZERO_W_GEN(V) +VL_ZERO_W_GEN(X) +#undef VL_ZERO_W_GEN + +static inline WDataOutP VL_ALLONES_W_T(int obits, WDataOutP owp) VL_MT_SAFE { const int words = VL_WORDS_I(obits); - VL_MEMSET_ONES_W(owp, words - 1); + if (words) VL_MEMSET_ONES_W(owp, words - 1); owp[words - 1] = VL_MASK_E(obits); return owp; } +// clang-format off +#define VL_ALLONES_W_GEN(outputSuffix) \ +static inline WDataOutP VL_ALLONES_W_##outputSuffix(int obits, WDataOutP owp) VL_MT_SAFE { \ + const WDataOutP resultp = owp; \ + owp += VL_GET_TYPE_OFFSET(outputSuffix); \ + /* Note iteration starts from one not zero - but i is not used to access data so its \ + * fine, we just finish a bit earlier which is also fine since we set last word after the \ + * loop */ \ + for (int i = 1; i < VL_WORDS_I(obits); ++i) { \ + /* VL_MEMSET_ZERO_W is used because it uses std::memset which is kind of special \ + * since if no read from memory written by std::memset occur std::memset may be \ + * optimized away */ \ + VL_MEMSET_ONES_W(owp, 1); \ + owp += VL_GET_TYPE_JUMP(outputSuffix); \ + } \ + *owp = VL_MASK_E(obits); \ + return resultp; \ + } +// clang-format on +VL_ALLONES_W_GEN(V) +VL_ALLONES_W_GEN(X) +#undef VL_ALLONES_W_GEN + // EMIT_RULE: VL_ASSIGN: oclean=rclean; obits==lbits; // For now, we always have a clean rhs. // Note: If a ASSIGN isn't clean, use VL_ASSIGNCLEAN instead to do the same thing. -static inline WDataOutP VL_ASSIGN_W(int obits, WDataOutP owp, WDataInP const lwp) VL_MT_SAFE { +static inline WDataOutP VL_ASSIGN_W_TT(int obits, WDataOutP owp, WDataInP const lwp) VL_MT_SAFE { return VL_MEMCPY_W(owp, lwp, VL_WORDS_I(obits)); } +// clang-format off +#define VL_ASSIGN_W_GEN(outputSuffix, inputSuffix) \ +static inline WDataOutP VL_ASSIGN_W_##outputSuffix##inputSuffix(int obits, WDataOutP owp, WDataInP lwp) \ + VL_MT_SAFE { \ + const WDataOutP result = owp; \ + owp += VL_GET_TYPE_OFFSET(outputSuffix); \ + lwp += VL_GET_TYPE_OFFSET(inputSuffix); \ + for (int i = 0; i < VL_WORDS_I(obits); ++i) { \ + *owp = *lwp; \ + owp += VL_GET_TYPE_JUMP(outputSuffix); \ + lwp += VL_GET_TYPE_JUMP(inputSuffix); \ + } \ + return result; \ + } +// clang-format on + +// T - two state value +// V - value part +// X - xz part +VL_ASSIGN_W_GEN(V, V) +VL_ASSIGN_W_GEN(V, X) +VL_ASSIGN_W_GEN(V, T) +VL_ASSIGN_W_GEN(X, V) +VL_ASSIGN_W_GEN(X, X) +VL_ASSIGN_W_GEN(X, T) +VL_ASSIGN_W_GEN(T, V) +VL_ASSIGN_W_GEN(T, X) +#undef VL_ASSIGN_W_GEN + // EMIT_RULE: VL_ASSIGNBIT: rclean=clean; static inline void VL_ASSIGNBIT_II(int bit, CData& lhsr, IData rhs) VL_PURE { lhsr = ((lhsr & ~(VL_UL(1) << VL_BITBIT_I(bit))) | (rhs << VL_BITBIT_I(bit))); @@ -555,12 +730,12 @@ static inline void VL_ASSIGNBIT_WO(int bit, WDataOutP owp) VL_MT_SAFE { while (lsb < (obits) - BITS_PER_DIGIT) { \ const uint32_t data = *chunkp; \ ++chunkp; \ - _vl_insert_WI(owp, data, lsb + BITS_PER_DIGIT - 1, lsb); \ + _vl_insert_WI_T(owp, data, lsb + BITS_PER_DIGIT - 1, lsb); \ lsb += BITS_PER_DIGIT; \ } \ if (lsb < (obits)) { \ const uint32_t msb_data = *chunkp; \ - _vl_insert_WI(owp, msb_data, (obits) - 1, lsb); \ + _vl_insert_WI_T(owp, msb_data, (obits) - 1, lsb); \ } \ (owp)[words - 1] &= VL_MASK_E(obits); \ } @@ -611,19 +786,29 @@ static inline void VL_ASSIGNBIT_WO(int bit, WDataOutP owp) VL_MT_SAFE { while (lsb + BITS_PER_DIGIT < (obits)) { \ static_assert(std::is_same::value, "IData and EData mismatch"); \ const uint32_t data \ - = VL_SEL_IWII(lsb + BITS_PER_DIGIT + 1, rwp, lsb, BITS_PER_DIGIT); \ + = VL_SEL_IWII_TTTT(lsb + BITS_PER_DIGIT + 1, rwp, lsb, BITS_PER_DIGIT); \ *chunkp = data & VL_MASK_E(BITS_PER_DIGIT); \ ++chunkp; \ lsb += BITS_PER_DIGIT; \ } \ if (lsb < (obits)) { \ - const uint32_t msb_data = VL_SEL_IWII((obits) + 1, rwp, lsb, (obits) - lsb); \ + const uint32_t msb_data = VL_SEL_IWII_TTTT((obits) + 1, rwp, lsb, (obits) - lsb); \ *chunkp = msb_data & VL_MASK_E((obits) - lsb); \ } \ _butemp.set(0, rwp[0] & 1); /* force update the sign */ \ (svar).write(_butemp); \ } +#define VL_ZERO_OFFSET_W_T(obits, owp) VL_ZERO_W_T(obits, owp) +#define VL_ZERO_OFFSET_W_V(obits, owp) VL_ZERO_W_V(obits, owp) +#define VL_ZERO_OFFSET_W_X(obits, owp) VL_ZERO_W_V(obits, owp) +#define VL_ALLONES_OFFSET_W_T(obits, owp) VL_ALLONES_W_T(obits, owp) +#define VL_ALLONES_OFFSET_W_V(obits, owp) VL_ALLONES_W_V(obits, owp) +#define VL_ALLONES_OFFSET_W_X(obits, owp) VL_ALLONES_W_V(obits, owp) +// ^ it does the trick because VL_TYPE_OFFSET_T and VL_TYPE_OFFSET_V are 0 +static_assert(VL_TYPE_OFFSET_T == 0 && VL_TYPE_OFFSET_V == 0, + "The VL_TYPE_OFFSET_T/V is not zero so, VL_ZERO_OFFSET_W_* must be adjusted"); + //=================================================================== // Extending sizes @@ -631,98 +816,170 @@ static inline void VL_ASSIGNBIT_WO(int bit, WDataOutP owp) VL_MT_SAFE { // Right must be clean because otherwise size increase would pick up bad bits // EMIT_RULE: VL_EXTEND: oclean=clean; rclean==clean; -#define VL_EXTEND_II(obits, lbits, lhs) ((lhs)) -#define VL_EXTEND_QI(obits, lbits, lhs) (static_cast(lhs)) -#define VL_EXTEND_QQ(obits, lbits, lhs) ((lhs)) +#define VL_EXTEND_II_TT(obits, lbits, lhs) ((lhs)) +#define VL_EXTEND_QI_TT(obits, lbits, lhs) (static_cast(lhs)) +#define VL_EXTEND_QQ_TT(obits, lbits, lhs) ((lhs)) -static inline WDataOutP VL_EXTEND_WI(int obits, int, WDataOutP owp, IData ld) VL_MT_SAFE { - // Note for extracts that obits != lbits - owp[0] = ld; - VL_MEMSET_ZERO_W(owp + 1, VL_WORDS_I(obits) - 1); - return owp; -} -static inline WDataOutP VL_EXTEND_WQ(int obits, int, WDataOutP owp, QData ld) VL_MT_SAFE { - VL_SET_WQ(owp, ld); - VL_MEMSET_ZERO_W(owp + VL_WQ_WORDS_E, VL_WORDS_I(obits) - VL_WQ_WORDS_E); - return owp; -} -static inline WDataOutP VL_EXTEND_WW(int obits, int lbits, WDataOutP owp, - WDataInP const lwp) VL_MT_SAFE { - const int lwords = VL_WORDS_I(lbits); - VL_PREFETCH_RD(lwp.datap()); - VL_MEMSET_ZERO_W(owp + lwords, VL_WORDS_I(obits) - lwords); - return VL_MEMCPY_W(owp, lwp, lwords); -} +// clang-format off +#define VL_EXTEND_WI_GEN(outputSuffix) \ +static inline WDataOutP VL_EXTEND_WI_##outputSuffix##T(int obits, int, WDataOutP owp, IData ld) \ + VL_MT_SAFE { \ + /* Note for extracts that obits != lbits */ \ + const WDataOutP resultp = owp; \ + owp += VL_GET_TYPE_OFFSET(outputSuffix); \ + *owp = ld; \ + owp += VL_GET_TYPE_JUMP(outputSuffix); \ + VL_ZERO_OFFSET_W_##outputSuffix(obits - VL_EDATASIZE, owp); \ + return resultp; \ + } +// clang-format on +VL_GEN_HELPER_ONE_ARG(VL_EXTEND_WI_GEN) +#undef VL_EXTEND_WI_GEN + +// clang-format off +#define VL_EXTEND_WQ_GEN(outputSuffix) \ +static inline WDataOutP VL_EXTEND_WQ_##outputSuffix##T(int obits, int, WDataOutP const owp, \ + QData ld) VL_MT_SAFE { \ + VL_SET_WQ_##outputSuffix(owp, ld); \ + VL_ZERO_OFFSET_W_##outputSuffix(obits - VL_QUADSIZE, \ + VL_GET_ELEM(outputSuffix, owp, VL_WQ_WORDS_E)); \ + return owp; \ + } +// clang-format on +VL_GEN_HELPER_ONE_ARG(VL_EXTEND_WQ_GEN) +#undef VL_EXTEND_WQ_GEN + +// clang-format off +#define VL_EXTEND_WQ_GEN(outputSuffix, lhsSuffix) \ +static inline WDataOutP VL_EXTEND_WW_##outputSuffix##lhsSuffix( \ + int obits, int lbits, WDataOutP owp, WDataInP const lwp) VL_MT_SAFE { \ + const int lwords = VL_WORDS_I(lbits); \ + VL_PREFETCH_RD(lwp.datap()); \ + VL_ZERO_W_##outputSuffix((VL_WORDS_I(obits) - lwords) * VL_EDATASIZE, \ + VL_GET_ELEM(outputSuffix, owp, lwords)); \ + return VL_ASSIGN_W_##outputSuffix##lhsSuffix(lbits, owp, lwp); \ + } +// clang-format on +VL_GEN_HELPER_TWO_ARG(VL_EXTEND_WQ_GEN) +#undef VL_EXTEND_WQ_GEN // EMIT_RULE: VL_EXTENDS: oclean=*dirty*; obits=lbits; // Sign extension; output dirty -static inline IData VL_EXTENDS_II(int, int lbits, IData lhs) VL_PURE { +static inline IData VL_EXTENDS_II_TT(int, int lbits, IData lhs) VL_PURE { return VL_EXTENDSIGN_I(lbits, lhs) | lhs; } -static inline QData VL_EXTENDS_QI(int, int lbits, QData lhs /*Q_as_need_extended*/) VL_PURE { +static inline QData VL_EXTENDS_QI_TT(int, int lbits, QData lhs /*Q_as_need_extended*/) VL_PURE { return VL_EXTENDSIGN_Q(lbits, lhs) | lhs; } -static inline QData VL_EXTENDS_QQ(int, int lbits, QData lhs) VL_PURE { +static inline QData VL_EXTENDS_QQ_TT(int, int lbits, QData lhs) VL_PURE { return VL_EXTENDSIGN_Q(lbits, lhs) | lhs; } -static inline WDataOutP VL_EXTENDS_WI(int obits, int lbits, WDataOutP owp, IData ld) VL_MT_SAFE { - owp[0] = ld; - if (VL_SIGN_E(lbits, owp[0])) { - owp[0] |= ~VL_MASK_E(lbits); - VL_MEMSET_ONES_W(owp + 1, VL_WORDS_I(obits) - 1); - } else { - VL_MEMSET_ZERO_W(owp + 1, VL_WORDS_I(obits) - 1); +// clang-format off +#define VL_EXTENDS_WI_GEN(outputSuffix) \ +static inline WDataOutP VL_EXTENDS_WI_##outputSuffix##T(int obits, int lbits, WDataOutP owp, \ + IData ld) VL_MT_SAFE { \ + const WDataOutP resultp = owp; \ + owp += VL_GET_TYPE_OFFSET(outputSuffix); \ + *owp = ld; \ + if (VL_SIGN_I_T(lbits, ld)) { \ + *owp |= ~VL_MASK_E(lbits); \ + VL_ALLONES_OFFSET_W_##outputSuffix(obits - VL_EDATASIZE, \ + owp + VL_GET_TYPE_JUMP(outputSuffix)); \ + } else { \ + VL_ZERO_OFFSET_W_##outputSuffix(obits - VL_EDATASIZE, \ + owp + VL_GET_TYPE_JUMP(outputSuffix)); \ + } \ + return resultp; \ } - return owp; -} -static inline WDataOutP VL_EXTENDS_WQ(int obits, int lbits, WDataOutP owp, QData ld) VL_MT_SAFE { - VL_SET_WQ(owp, ld); - if (VL_SIGN_E(lbits, owp[1])) { - owp[1] |= ~VL_MASK_E(lbits); - VL_MEMSET_ONES_W(owp + VL_WQ_WORDS_E, VL_WORDS_I(obits) - VL_WQ_WORDS_E); - } else { - VL_MEMSET_ZERO_W(owp + VL_WQ_WORDS_E, VL_WORDS_I(obits) - VL_WQ_WORDS_E); +// clang-format on +VL_GEN_HELPER_ONE_ARG(VL_EXTENDS_WI_GEN) +#undef VL_EXTENDS_WI_GEN + +// clang-format off +#define VL_EXTENDS_WQ_GEN(outputSuffix) \ +static inline WDataOutP VL_EXTENDS_WQ_##outputSuffix##T(int obits, int lbits, WDataOutP owp, \ + QData ld) VL_MT_SAFE { \ + VL_SET_WQ_##outputSuffix(owp, ld); \ + if (VL_SIGN_Q_T(lbits, ld)) { \ + *VL_GET_ELEM(outputSuffix, owp, 1) |= ~VL_MASK_E(lbits); \ + VL_ALLONES_OFFSET_W_##outputSuffix(obits - VL_QUADSIZE, \ + VL_GET_ELEM(outputSuffix, owp, VL_WQ_WORDS_E)); \ + } else { \ + VL_ZERO_OFFSET_W_##outputSuffix(obits - VL_QUADSIZE, \ + VL_GET_ELEM(outputSuffix, owp, VL_WQ_WORDS_E)); \ + } \ + return owp; \ } - return owp; -} -static inline WDataOutP VL_EXTENDS_WW(int obits, int lbits, WDataOutP owp, - WDataInP const lwp) VL_MT_SAFE { - const int lwords = VL_WORDS_I(lbits); - VL_PREFETCH_RD(lwp.datap()); - owp[lwords - 1] = lwp[lwords - 1]; - if (VL_SIGN_E(lbits, lwp[lwords - 1])) { - owp[lwords - 1] |= ~VL_MASK_E(lbits); - VL_MEMSET_ONES_W(owp + lwords, VL_WORDS_I(obits) - lwords); - } else { - VL_MEMSET_ZERO_W(owp + lwords, VL_WORDS_I(obits) - lwords); +// clang-format on +VL_GEN_HELPER_ONE_ARG(VL_EXTENDS_WQ_GEN) +#undef VL_EXTENDS_WQ_GEN + +// clang-format off +#define VL_EXTENDS_WW_GEN(outputSuffix, lhsSuffix) \ +static inline WDataOutP VL_EXTENDS_WW_##outputSuffix##lhsSuffix( \ + int obits, int lbits, WDataOutP const owp, WDataInP const lwp) VL_MT_SAFE { \ + const int lwords = VL_WORDS_I(lbits); \ + VL_PREFETCH_RD(lwp.datap()); \ + VL_ASSIGN_W_##outputSuffix##lhsSuffix(lbits, owp, lwp); \ + if (VL_SIGN_W_##lhsSuffix(lbits, lwp)) { \ + *VL_GET_ELEM(outputSuffix, owp, lwords - 1) |= ~VL_MASK_E(lbits); \ + VL_ALLONES_OFFSET_W_##outputSuffix((VL_WORDS_I(obits) - lwords) * VL_EDATASIZE, \ + VL_GET_ELEM(outputSuffix, owp, lwords)); \ + } else { \ + VL_ZERO_OFFSET_W_##outputSuffix((VL_WORDS_I(obits) - lwords) * VL_EDATASIZE, \ + VL_GET_ELEM(outputSuffix, owp, lwords)); \ + } \ + return owp; \ } - return VL_MEMCPY_W(owp, lwp, lwords - 1); -} +// clang-format on +VL_GEN_HELPER_TWO_ARG(VL_EXTENDS_WW_GEN) +#undef VL_EXTENDS_WW_GEN //=================================================================== // REDUCTION OPERATORS // EMIT_RULE: VL_REDAND: oclean=clean; lclean==clean; obits=1; -#define VL_REDAND_II(lbits, lhs) ((lhs) == VL_MASK_I(lbits)) -#define VL_REDAND_IQ(lbits, lhs) ((lhs) == VL_MASK_Q(lbits)) -static inline IData VL_REDAND_IW(int lbits, WDataInP const lwp) VL_PURE { - const int words = VL_WORDS_I(lbits); - EData combine = lwp[0]; - for (int i = 1; i < words - 1; ++i) combine &= lwp[i]; - combine &= ~VL_MASK_E(lbits) | lwp[words - 1]; - // cppcheck-suppress knownConditionTrueFalse - return ((~combine) == 0); -} +#define VL_REDAND_I_T(lbits, lhs) ((lhs) == VL_MASK_I(lbits)) +#define VL_REDAND_Q_T(lbits, lhs) ((lhs) == VL_MASK_Q(lbits)) + +// clang-format off +#define VL_REDAND_W_GEN(lhsSuffix) \ +static inline IData VL_REDAND_W_##lhsSuffix(int lbits, WDataInP lwp) VL_PURE { \ + const int words = VL_WORDS_I(lbits); \ + lwp = lwp + VL_GET_TYPE_OFFSET(lhsSuffix); \ + EData combine = *lwp; \ + for (int i = 1; i < words - 1; ++i) { \ + lwp = lwp + VL_GET_TYPE_JUMP(lhsSuffix); \ + combine &= *lwp; \ + } \ + lwp = lwp + VL_GET_TYPE_JUMP(lhsSuffix); \ + combine &= ~VL_MASK_E(lbits) | *lwp; \ + /* cppcheck-suppress knownConditionTrueFalse */ \ + return ((~combine) == 0); \ + } +// clang-format on +VL_GEN_HELPER_ONE_ARG(VL_REDAND_W_GEN) +#undef VL_REDAND_W_GEN // EMIT_RULE: VL_REDOR: oclean=clean; lclean==clean; obits=1; -#define VL_REDOR_I(lhs) ((lhs) != 0) -#define VL_REDOR_Q(lhs) ((lhs) != 0) -static inline IData VL_REDOR_W(int words, WDataInP const lwp) VL_PURE { - EData equal = 0; - for (int i = 0; i < words; ++i) equal |= lwp[i]; - return (equal != 0); -} +#define VL_REDOR_I_T(lhs) ((lhs) != 0) +#define VL_REDOR_Q_T(lhs) ((lhs) != 0) + +// clang-format off +#define VL_REDOR_W_GEN(lhsSuffix) \ +static inline IData VL_REDOR_W_##lhsSuffix(int words, WDataInP lwp) VL_PURE { \ + EData equal = 0; \ + lwp = lwp + VL_GET_TYPE_OFFSET(lhsSuffix); \ + for (int i = 0; i < words; ++i) { \ + equal |= *lwp; \ + lwp = lwp + VL_GET_TYPE_JUMP(lhsSuffix); \ + } \ + return (equal != 0); \ + } +// clang-format on +VL_GEN_HELPER_ONE_ARG(VL_REDOR_W_GEN) +#undef VL_REDOR_W_GEN // EMIT_RULE: VL_REDXOR: oclean=dirty; obits=1; static inline IData VL_REDXOR_2(IData r) VL_PURE { @@ -785,11 +1042,21 @@ static inline IData VL_REDXOR_64(QData r) VL_PURE { return static_cast(r); #endif } -static inline IData VL_REDXOR_W(int words, WDataInP const lwp) VL_PURE { - EData r = lwp[0]; - for (int i = 1; i < words; ++i) r ^= lwp[i]; - return VL_REDXOR_32(r); -} + +// clang-format off +#define VL_REDXOR_W_GEN(lhsSuffix) \ +static inline IData VL_REDXOR_W_##lhsSuffix(int words, WDataInP lwp) VL_PURE { \ + lwp = lwp + VL_GET_TYPE_OFFSET(lhsSuffix); \ + EData r = *lwp; \ + for (int i = 1; i < words; ++i) { \ + lwp = lwp + VL_GET_TYPE_JUMP(lhsSuffix); \ + r ^= *lwp; \ + } \ + return VL_REDXOR_32(r); \ + } +// clang-format on +VL_GEN_HELPER_ONE_ARG(VL_REDXOR_W_GEN) +#undef VL_REDXOR_W_GEN // EMIT_RULE: VL_COUNTONES_II: oclean = false; lhs clean static inline IData VL_COUNTONES_I(IData lhs) VL_PURE { @@ -903,7 +1170,7 @@ static inline IData VL_CLOG2_W(int words, WDataInP const lwp) VL_PURE { return 0; } -static inline IData VL_MOSTSETBITP1_I(IData lhs) VL_PURE { +static inline IData VL_MOSTSETBITP1_I_T(IData lhs) VL_PURE { if (VL_UNLIKELY(!lhs)) return 0; // __builtin_clz is undefined for 0 #if defined(__GNUC__) && (__GNUC__ >= 4) && !defined(VL_NO_BUILTINS) return VL_EDATASIZE - __builtin_clz(lhs); @@ -914,56 +1181,100 @@ static inline IData VL_MOSTSETBITP1_I(IData lhs) VL_PURE { return 0; // LCOV_EXCL_LINE // Can't get here - one bit must be set #endif } -static inline IData VL_MOSTSETBITP1_Q(QData lhs) VL_PURE { +static inline IData VL_MOSTSETBITP1_Q_T(QData lhs) VL_PURE { if (VL_UNLIKELY(!lhs)) return 0; #if defined(__GNUC__) && (__GNUC__ >= 4) && !defined(VL_NO_BUILTINS) return 64 - __builtin_clzll(static_cast(lhs)); #else const IData hi = static_cast(lhs >> 32ULL); - return hi ? (VL_EDATASIZE + VL_MOSTSETBITP1_I(hi)) - : VL_MOSTSETBITP1_I(static_cast(lhs)); + return hi ? (VL_EDATASIZE + VL_MOSTSETBITP1_I_T(hi)) + : VL_MOSTSETBITP1_I_T(static_cast(lhs)); #endif } -static inline IData VL_MOSTSETBITP1_W(int words, WDataInP const lwp) VL_PURE { - for (int i = words - 1; i >= 0; --i) { - // Shorter worst case if predict not taken - if (VL_UNLIKELY(lwp[i])) return i * VL_EDATASIZE + VL_MOSTSETBITP1_I(lwp[i]); + +// clang-format off +#define VL_MOSTSETBITP1_W_GEN(suffix) \ +static inline IData VL_MOSTSETBITP1_W_##suffix(int words, WDataInP lwp) VL_PURE { \ + lwp = lwp + VL_GET_TYPE_OFFSET(suffix) + ((words << ((VL_GET_TYPE_JUMP(suffix)) - 1)) - (VL_GET_TYPE_JUMP(suffix))); \ + /* MSB set bit plus one; similar to FLS. 0=value is zero */ \ + for (int i = words - 1; i >= 0; --i) { \ + /* Shorter worst case if predict not taken */ \ + if (VL_UNLIKELY(*lwp)) return i * VL_EDATASIZE + VL_MOSTSETBITP1_I_T(*lwp); \ + lwp = lwp - (VL_GET_TYPE_JUMP(suffix)); \ + } \ + return 0; \ } - return 0; -} +// clang-format on +VL_GEN_HELPER_ONE_ARG(VL_MOSTSETBITP1_W_GEN) +#undef VL_MOSTSETBITP1_W_GEN //=================================================================== // SIMPLE LOGICAL OPERATORS +// clang-format off +#define VL_BIOP_GEN(name, op, outputSuffix, lhsSuffix, rhsSuffix) \ +static inline WDataOutP VL_##name##_W_##outputSuffix##lhsSuffix##rhsSuffix(int words, WDataOutP owp, WDataInP lwp, \ + WDataInP rwp) VL_MT_SAFE { \ + const WDataOutP result = owp; \ + owp += VL_GET_TYPE_OFFSET(outputSuffix); \ + lwp += VL_GET_TYPE_OFFSET(lhsSuffix); \ + rwp += VL_GET_TYPE_OFFSET(rhsSuffix); \ + for (int i = 0; (i < words); ++i) { \ + *owp = (*lwp op * rwp); \ + owp += VL_GET_TYPE_JUMP(outputSuffix); \ + lwp += VL_GET_TYPE_JUMP(lhsSuffix); \ + rwp += VL_GET_TYPE_JUMP(rhsSuffix); \ + } \ + return result; \ +} +// clang-format on + // EMIT_RULE: VL_AND: oclean=lclean||rclean; obits=lbits; lbits==rbits; -static inline WDataOutP VL_AND_W(int words, WDataOutP owp, WDataInP const lwp, - WDataInP const rwp) VL_MT_SAFE { - for (int i = 0; (i < words); ++i) owp[i] = (lwp[i] & rwp[i]); - return owp; -} +#define VL_AND_GEN(outputSuffix, lhsSuffix, rhsSuffix) \ + VL_BIOP_GEN(AND, &, outputSuffix, lhsSuffix, rhsSuffix) +VL_GEN_HELPER_THREE_ARG(VL_AND_GEN) +#undef VL_AND_GEN // EMIT_RULE: VL_OR: oclean=lclean&&rclean; obits=lbits; lbits==rbits; -static inline WDataOutP VL_OR_W(int words, WDataOutP owp, WDataInP const lwp, - WDataInP const rwp) VL_MT_SAFE { - for (int i = 0; (i < words); ++i) owp[i] = (lwp[i] | rwp[i]); - return owp; -} +#define VL_OR_GEN(outputSuffix, lhsSuffix, rhsSuffix) \ + VL_BIOP_GEN(OR, |, outputSuffix, lhsSuffix, rhsSuffix) +VL_GEN_HELPER_THREE_ARG(VL_OR_GEN) +#undef VL_OR_GEN +// EMIT_RULE: VL_XOR: oclean=lclean&&rclean; obits=lbits; lbits==rbits; +#define VL_XOR_GEN(outputSuffix, lhsSuffix, rhsSuffix) \ + VL_BIOP_GEN(XOR, ^, outputSuffix, lhsSuffix, rhsSuffix) +VL_GEN_HELPER_THREE_ARG(VL_XOR_GEN) +#undef VL_XOR_GEN + +#undef VL_BIOP_GEN + // EMIT_RULE: VL_CHANGEXOR: oclean=1; obits=32; lbits==rbits; static inline IData VL_CHANGEXOR_W(int words, WDataInP const lwp, WDataInP const rwp) VL_PURE { IData od = 0; for (int i = 0; (i < words); ++i) od |= (lwp[i] ^ rwp[i]); return od; } -// EMIT_RULE: VL_XOR: oclean=lclean&&rclean; obits=lbits; lbits==rbits; -static inline WDataOutP VL_XOR_W(int words, WDataOutP owp, WDataInP const lwp, - WDataInP const rwp) VL_MT_SAFE { - for (int i = 0; (i < words); ++i) owp[i] = (lwp[i] ^ rwp[i]); - return owp; -} // EMIT_RULE: VL_NOT: oclean=dirty; obits=lbits; -static inline WDataOutP VL_NOT_W(int words, WDataOutP owp, WDataInP const lwp) VL_MT_SAFE { - for (int i = 0; i < words; ++i) owp[i] = ~(lwp[i]); - return owp; -} + +// clang-format off + +#define VL_NOT_GEN(outputSuffix, lhsSuffix) \ +static inline WDataOutP VL_NOT_W_##outputSuffix##lhsSuffix(int words, WDataOutP owp, WDataInP lwp) \ + VL_MT_SAFE { \ + const WDataOutP result = owp; \ + owp += VL_GET_TYPE_OFFSET(outputSuffix); \ + lwp += VL_GET_TYPE_OFFSET(lhsSuffix); \ + for (int i = 0; i < words; ++i) { \ + *owp = ~(*lwp); \ + owp += VL_GET_TYPE_JUMP(outputSuffix); \ + lwp += VL_GET_TYPE_JUMP(lhsSuffix); \ + } \ + return result; \ + } + +// clang-format on + +VL_GEN_HELPER_TWO_ARG(VL_NOT_GEN) +#undef VL_NOT_GEN //========================================================================= // Logical comparisons @@ -974,357 +1285,873 @@ static inline WDataOutP VL_NOT_W(int words, WDataOutP owp, WDataInP const lwp) V // EMIT_RULE: VL_GT: oclean=clean; lclean==clean; rclean==clean; obits=1; lbits==rbits; // EMIT_RULE: VL_GTE: oclean=clean; lclean==clean; rclean==clean; obits=1; lbits==rbits; // EMIT_RULE: VL_LTE: oclean=clean; lclean==clean; rclean==clean; obits=1; lbits==rbits; -#define VL_NEQ_W(words, lwp, rwp) (!VL_EQ_W(words, lwp, rwp)) -#define VL_NEQ_R(words, q, rwp) (!VL_EQ_R(words, q, rwp)) -#define VL_LT_W(words, lwp, rwp) (_vl_cmp_w(words, lwp, rwp) < 0) -#define VL_LTE_W(words, lwp, rwp) (_vl_cmp_w(words, lwp, rwp) <= 0) -#define VL_GT_W(words, lwp, rwp) (_vl_cmp_w(words, lwp, rwp) > 0) -#define VL_GTE_W(words, lwp, rwp) (_vl_cmp_w(words, lwp, rwp) >= 0) +#define VL_LT_W_TT(words, lwp, rwp) (_vl_cmp_w_TT(words, lwp, rwp) < 0) +#define VL_LT_W_TV(words, lwp, rwp) (_vl_cmp_w_TV(words, lwp, rwp) < 0) +#define VL_LT_W_TX(words, lwp, rwp) (_vl_cmp_w_TX(words, lwp, rwp) < 0) +#define VL_LT_W_VT(words, lwp, rwp) (_vl_cmp_w_VT(words, lwp, rwp) < 0) +#define VL_LT_W_VV(words, lwp, rwp) (_vl_cmp_w_VV(words, lwp, rwp) < 0) +#define VL_LT_W_VX(words, lwp, rwp) (_vl_cmp_w_VX(words, lwp, rwp) < 0) +#define VL_LT_W_XT(words, lwp, rwp) (_vl_cmp_w_XT(words, lwp, rwp) < 0) +#define VL_LT_W_XV(words, lwp, rwp) (_vl_cmp_w_XV(words, lwp, rwp) < 0) +#define VL_LT_W_XX(words, lwp, rwp) (_vl_cmp_w_XX(words, lwp, rwp) < 0) +#define VL_LT_W_TT(words, lwp, rwp) (_vl_cmp_w_TT(words, lwp, rwp) < 0) +#define VL_LT_W_TV(words, lwp, rwp) (_vl_cmp_w_TV(words, lwp, rwp) < 0) +#define VL_LT_W_TX(words, lwp, rwp) (_vl_cmp_w_TX(words, lwp, rwp) < 0) +#define VL_LT_W_VT(words, lwp, rwp) (_vl_cmp_w_VT(words, lwp, rwp) < 0) +#define VL_LT_W_VV(words, lwp, rwp) (_vl_cmp_w_VV(words, lwp, rwp) < 0) +#define VL_LT_W_VX(words, lwp, rwp) (_vl_cmp_w_VX(words, lwp, rwp) < 0) +#define VL_LT_W_XT(words, lwp, rwp) (_vl_cmp_w_XT(words, lwp, rwp) < 0) +#define VL_LT_W_XV(words, lwp, rwp) (_vl_cmp_w_XV(words, lwp, rwp) < 0) +#define VL_LT_W_XX(words, lwp, rwp) (_vl_cmp_w_XX(words, lwp, rwp) < 0) +#define VL_LTE_W_TT(words, lwp, rwp) (_vl_cmp_w_TT(words, lwp, rwp) <= 0) +#define VL_LTE_W_TV(words, lwp, rwp) (_vl_cmp_w_TV(words, lwp, rwp) <= 0) +#define VL_LTE_W_TX(words, lwp, rwp) (_vl_cmp_w_TX(words, lwp, rwp) <= 0) +#define VL_LTE_W_VT(words, lwp, rwp) (_vl_cmp_w_VT(words, lwp, rwp) <= 0) +#define VL_LTE_W_VV(words, lwp, rwp) (_vl_cmp_w_VV(words, lwp, rwp) <= 0) +#define VL_LTE_W_VX(words, lwp, rwp) (_vl_cmp_w_VX(words, lwp, rwp) <= 0) +#define VL_LTE_W_XT(words, lwp, rwp) (_vl_cmp_w_XT(words, lwp, rwp) <= 0) +#define VL_LTE_W_XV(words, lwp, rwp) (_vl_cmp_w_XV(words, lwp, rwp) <= 0) +#define VL_LTE_W_XX(words, lwp, rwp) (_vl_cmp_w_XX(words, lwp, rwp) <= 0) +#define VL_LTE_W_TT(words, lwp, rwp) (_vl_cmp_w_TT(words, lwp, rwp) <= 0) +#define VL_LTE_W_TV(words, lwp, rwp) (_vl_cmp_w_TV(words, lwp, rwp) <= 0) +#define VL_LTE_W_TX(words, lwp, rwp) (_vl_cmp_w_TX(words, lwp, rwp) <= 0) +#define VL_LTE_W_VT(words, lwp, rwp) (_vl_cmp_w_VT(words, lwp, rwp) <= 0) +#define VL_LTE_W_VV(words, lwp, rwp) (_vl_cmp_w_VV(words, lwp, rwp) <= 0) +#define VL_LTE_W_VX(words, lwp, rwp) (_vl_cmp_w_VX(words, lwp, rwp) <= 0) +#define VL_LTE_W_XT(words, lwp, rwp) (_vl_cmp_w_XT(words, lwp, rwp) <= 0) +#define VL_LTE_W_XV(words, lwp, rwp) (_vl_cmp_w_XV(words, lwp, rwp) <= 0) +#define VL_LTE_W_XX(words, lwp, rwp) (_vl_cmp_w_XX(words, lwp, rwp) <= 0) +#define VL_GT_W_TT(words, lwp, rwp) (_vl_cmp_w_TT(words, lwp, rwp) > 0) +#define VL_GT_W_TV(words, lwp, rwp) (_vl_cmp_w_TV(words, lwp, rwp) > 0) +#define VL_GT_W_TX(words, lwp, rwp) (_vl_cmp_w_TX(words, lwp, rwp) > 0) +#define VL_GT_W_VT(words, lwp, rwp) (_vl_cmp_w_VT(words, lwp, rwp) > 0) +#define VL_GT_W_VV(words, lwp, rwp) (_vl_cmp_w_VV(words, lwp, rwp) > 0) +#define VL_GT_W_VX(words, lwp, rwp) (_vl_cmp_w_VX(words, lwp, rwp) > 0) +#define VL_GT_W_XT(words, lwp, rwp) (_vl_cmp_w_XT(words, lwp, rwp) > 0) +#define VL_GT_W_XV(words, lwp, rwp) (_vl_cmp_w_XV(words, lwp, rwp) > 0) +#define VL_GT_W_XX(words, lwp, rwp) (_vl_cmp_w_XX(words, lwp, rwp) > 0) +#define VL_GT_W_TT(words, lwp, rwp) (_vl_cmp_w_TT(words, lwp, rwp) > 0) +#define VL_GT_W_TV(words, lwp, rwp) (_vl_cmp_w_TV(words, lwp, rwp) > 0) +#define VL_GT_W_TX(words, lwp, rwp) (_vl_cmp_w_TX(words, lwp, rwp) > 0) +#define VL_GT_W_VT(words, lwp, rwp) (_vl_cmp_w_VT(words, lwp, rwp) > 0) +#define VL_GT_W_VV(words, lwp, rwp) (_vl_cmp_w_VV(words, lwp, rwp) > 0) +#define VL_GT_W_VX(words, lwp, rwp) (_vl_cmp_w_VX(words, lwp, rwp) > 0) +#define VL_GT_W_XT(words, lwp, rwp) (_vl_cmp_w_XT(words, lwp, rwp) > 0) +#define VL_GT_W_XV(words, lwp, rwp) (_vl_cmp_w_XV(words, lwp, rwp) > 0) +#define VL_GT_W_XX(words, lwp, rwp) (_vl_cmp_w_XX(words, lwp, rwp) > 0) +#define VL_GTE_W_TT(words, lwp, rwp) (_vl_cmp_w_TT(words, lwp, rwp) >= 0) +#define VL_GTE_W_TV(words, lwp, rwp) (_vl_cmp_w_TV(words, lwp, rwp) >= 0) +#define VL_GTE_W_TX(words, lwp, rwp) (_vl_cmp_w_TX(words, lwp, rwp) >= 0) +#define VL_GTE_W_VT(words, lwp, rwp) (_vl_cmp_w_VT(words, lwp, rwp) >= 0) +#define VL_GTE_W_VV(words, lwp, rwp) (_vl_cmp_w_VV(words, lwp, rwp) >= 0) +#define VL_GTE_W_VX(words, lwp, rwp) (_vl_cmp_w_VX(words, lwp, rwp) >= 0) +#define VL_GTE_W_XT(words, lwp, rwp) (_vl_cmp_w_XT(words, lwp, rwp) >= 0) +#define VL_GTE_W_XV(words, lwp, rwp) (_vl_cmp_w_XV(words, lwp, rwp) >= 0) +#define VL_GTE_W_XX(words, lwp, rwp) (_vl_cmp_w_XX(words, lwp, rwp) >= 0) +#define VL_GTE_W_TT(words, lwp, rwp) (_vl_cmp_w_TT(words, lwp, rwp) >= 0) +#define VL_GTE_W_TV(words, lwp, rwp) (_vl_cmp_w_TV(words, lwp, rwp) >= 0) +#define VL_GTE_W_TX(words, lwp, rwp) (_vl_cmp_w_TX(words, lwp, rwp) >= 0) +#define VL_GTE_W_VT(words, lwp, rwp) (_vl_cmp_w_VT(words, lwp, rwp) >= 0) +#define VL_GTE_W_VV(words, lwp, rwp) (_vl_cmp_w_VV(words, lwp, rwp) >= 0) +#define VL_GTE_W_VX(words, lwp, rwp) (_vl_cmp_w_VX(words, lwp, rwp) >= 0) +#define VL_GTE_W_XT(words, lwp, rwp) (_vl_cmp_w_XT(words, lwp, rwp) >= 0) +#define VL_GTE_W_XV(words, lwp, rwp) (_vl_cmp_w_XV(words, lwp, rwp) >= 0) +#define VL_GTE_W_XX(words, lwp, rwp) (_vl_cmp_w_XX(words, lwp, rwp) >= 0) +// clang-format off // Output clean, AND MUST BE CLEAN -static inline IData VL_EQ_W(int words, WDataInP const lwp, WDataInP const rwp) VL_PURE { - EData nequal = 0; - for (int i = 0; (i < words); ++i) nequal |= (lwp[i] ^ rwp[i]); - return (nequal == 0); -} - -template -static inline IData VL_EQ_W(int words, WDataInP const rwp, - const VlQueue>& q) VL_PURE { - return VL_EQ_R(words, q, rwp); -} - -template -static inline IData VL_EQ_W(int words, WDataInP const rwp, VlQueue q) VL_PURE { - return VL_EQ_R(words, q, rwp); -} - -template -static inline IData VL_EQ_R(int words, VlQueue q, WDataInP const rwp) VL_PURE { - EData nequal = 0; - const int wordsInQ = q.size() * sizeof(T) / sizeof(IData) - 1; - if (wordsInQ + 1 != words) return false; - if (sizeof(T) == 1) { - IData temp = 0; - for (int i = 0; (i < wordsInQ + 1); ++i) { - temp |= static_cast(q.at((wordsInQ - i) * sizeof(IData) + 3)); - temp |= static_cast(q.at((wordsInQ - i) * sizeof(IData) + 2)) << 8; - temp |= static_cast(q.at((wordsInQ - i) * sizeof(IData) + 1)) << 16; - temp |= static_cast(q.at((wordsInQ - i) * sizeof(IData))) << 24; - nequal |= (temp ^ rwp[i]); - temp = 0; - } - } else if (sizeof(T) == 2) { - IData temp = 0; - for (int i = 0; (i < wordsInQ + 1); ++i) { - temp |= q.at((wordsInQ - i) * sizeof(SData) + 1); - temp |= q.at((wordsInQ - i) * sizeof(SData)) << 16; - nequal |= (temp ^ rwp[i]); - temp = 0; - } - } else if (sizeof(T) == 4) { - for (int i = 0; (i < wordsInQ + 1); ++i) { nequal |= (q.at(wordsInQ - i) ^ rwp[i]); } - } else if (sizeof(T) == 8) { - QData temp = 0; - int qSize = q.size() - 1; - for (int i = 0; (i < qSize); i += 2) { - temp = q.at(qSize - i); - nequal |= (static_cast(q.at(qSize - i)) >> 32 ^ rwp[i + 1]); - temp = rwp[i + 1]; - nequal |= (static_cast(q.at(qSize - i)) ^ rwp[i]); - temp = rwp[i]; - } +#define VL_EQ_W_GEN(lhsSuffix, rhsSuffix) \ +static inline IData VL_EQ_W_##lhsSuffix##rhsSuffix(int words, WDataInP lwp, WDataInP rwp) VL_PURE { \ + lwp = lwp + VL_GET_TYPE_OFFSET(lhsSuffix); \ + rwp = rwp + VL_GET_TYPE_OFFSET(rhsSuffix); \ + EData nequal = 0; \ + for (int i = 0; (i < words); ++i) { \ + nequal |= (*lwp ^ *rwp); \ + lwp = lwp + VL_GET_TYPE_JUMP(lhsSuffix); \ + rwp = rwp + VL_GET_TYPE_JUMP(rhsSuffix); \ + } \ + return (nequal == 0); \ } - return (nequal == 0); -} +// clang-format on +VL_GEN_HELPER_TWO_ARG(VL_EQ_W_GEN) +#undef VL_EQ_W_GEN -template -static inline IData VL_EQ_R(int words, const VlQueue>& q, - WDataInP const rwp) VL_PURE { - EData nequal = 0; - const int wordsInQ = q.size() * N_Words; - if ((q.size() * N_Words) != words) { return false; } - int count = 0; - for (int qIndex = q.size() - 1; qIndex >= 0; qIndex--) { - for (int wordInElement = 0; wordInElement < N_Words; wordInElement++) { - nequal |= (q.at(qIndex).at(wordInElement) ^ rwp[count]); - count++; - } +#define VL_NEQ_R_TT(words, q, rwp) (!VL_EQ_R_TT(words, q, rwp)) +#define VL_NEQ_W_TT(words, lwp, rwp) (!VL_EQ_W_TT(words, lwp, rwp)) +#define VL_NEQ_W_TV(words, lwp, rwp) (!VL_EQ_W_TV(words, lwp, rwp)) +#define VL_NEQ_W_TX(words, lwp, rwp) (!VL_EQ_W_TX(words, lwp, rwp)) +#define VL_NEQ_W_VT(words, lwp, rwp) (!VL_EQ_W_VT(words, lwp, rwp)) +#define VL_NEQ_W_VV(words, lwp, rwp) (!VL_EQ_W_VV(words, lwp, rwp)) +#define VL_NEQ_W_VX(words, lwp, rwp) (!VL_EQ_W_VX(words, lwp, rwp)) +#define VL_NEQ_W_XT(words, lwp, rwp) (!VL_EQ_W_XT(words, lwp, rwp)) +#define VL_NEQ_W_XV(words, lwp, rwp) (!VL_EQ_W_XV(words, lwp, rwp)) +#define VL_NEQ_W_XX(words, lwp, rwp) (!VL_EQ_W_XX(words, lwp, rwp)) +#define VL_NEQ_W_TT(words, lwp, rwp) (!VL_EQ_W_TT(words, lwp, rwp)) +#define VL_NEQ_W_TV(words, lwp, rwp) (!VL_EQ_W_TV(words, lwp, rwp)) +#define VL_NEQ_W_TX(words, lwp, rwp) (!VL_EQ_W_TX(words, lwp, rwp)) +#define VL_NEQ_W_VT(words, lwp, rwp) (!VL_EQ_W_VT(words, lwp, rwp)) +#define VL_NEQ_W_VV(words, lwp, rwp) (!VL_EQ_W_VV(words, lwp, rwp)) +#define VL_NEQ_W_VX(words, lwp, rwp) (!VL_EQ_W_VX(words, lwp, rwp)) +#define VL_NEQ_W_XT(words, lwp, rwp) (!VL_EQ_W_XT(words, lwp, rwp)) +#define VL_NEQ_W_XV(words, lwp, rwp) (!VL_EQ_W_XV(words, lwp, rwp)) +#define VL_NEQ_W_XX(words, lwp, rwp) (!VL_EQ_W_XX(words, lwp, rwp)) + +// clang-format off +#define VL_EQ_R_GEN(rhsSuffix) \ +template \ +static inline IData VL_EQ_W_##rhsSuffix##T(int words, WDataInP const rwp, \ + const VlQueue>& q) VL_PURE { \ + return VL_EQ_R_T##rhsSuffix(words, q, rwp); \ + } \ +template \ +static inline IData VL_EQ_W_##rhsSuffix##T(int words, WDataInP const rwp, VlQueue q) \ + VL_PURE { \ + return VL_EQ_R_T##rhsSuffix(words, q, rwp); \ + } \ +template \ +static inline IData VL_EQ_R_T##rhsSuffix(int words, VlQueue q, WDataInP rwp) VL_PURE { \ + EData nequal = 0; \ + const int wordsInQ = q.size() * sizeof(T) / sizeof(IData) - 1; \ + if (wordsInQ + 1 != words) return false; \ + rwp += VL_GET_TYPE_OFFSET(rhsSuffix); \ + if VL_CONSTEXPR_CXX17 (sizeof(T) == 1) { \ + IData temp = 0; \ + for (int i = 0; (i < wordsInQ + 1); ++i) { \ + temp |= static_cast(q.at((wordsInQ - i) * sizeof(IData) + 3)); \ + temp |= static_cast(q.at((wordsInQ - i) * sizeof(IData) + 2)) << 8; \ + temp |= static_cast(q.at((wordsInQ - i) * sizeof(IData) + 1)) << 16; \ + temp |= static_cast(q.at((wordsInQ - i) * sizeof(IData))) << 24; \ + nequal |= (temp ^ *rwp); \ + temp = 0; \ + rwp += VL_GET_TYPE_JUMP(rhsSuffix); \ + } \ + } else if VL_CONSTEXPR_CXX17 (sizeof(T) == 2) { \ + IData temp = 0; \ + for (int i = 0; (i < wordsInQ + 1); ++i) { \ + temp |= q.at((wordsInQ - i) * sizeof(SData) + 1); \ + temp |= q.at((wordsInQ - i) * sizeof(SData)) << 16; \ + nequal |= (temp ^ *rwp); \ + temp = 0; \ + rwp += VL_GET_TYPE_JUMP(rhsSuffix); \ + } \ + } else if VL_CONSTEXPR_CXX17 (sizeof(T) == 4) { \ + for (int i = 0; (i < wordsInQ + 1); ++i) { nequal |= (q.at(wordsInQ - i) ^ rwp[i]); } \ + } else if VL_CONSTEXPR_CXX17 (sizeof(T) == 8) { \ + int qSize = q.size() - 1; \ + for (int i = 0; (i < qSize); i += 2) { \ + nequal |= (static_cast(q.at(qSize - i)) ^ *rwp); \ + rwp += VL_GET_TYPE_JUMP(rhsSuffix); \ + nequal |= (static_cast(q.at(qSize - i)) >> 32 ^ *rwp); \ + rwp += VL_GET_TYPE_JUMP(rhsSuffix); \ + } \ + } \ + return (nequal == 0); \ + } \ +template \ +static inline IData VL_EQ_R_T##rhsSuffix(int words, const VlQueue>& q, \ + WDataInP rwp) VL_PURE { \ + EData nequal = 0; \ + const int wordsInQ = q.size() * N_Words; \ + if ((q.size() * N_Words) != words) { return false; } \ + rwp += VL_GET_TYPE_OFFSET(rhsSuffix); \ + for (int qIndex = q.size() - 1; qIndex >= 0; qIndex--) { \ + for (int wordInElement = 0; wordInElement < N_Words; wordInElement++) { \ + nequal |= (q.at(qIndex).at(wordInElement) ^ *rwp); \ + rwp += VL_GET_TYPE_JUMP(rhsSuffix); \ + } \ + } \ + return (nequal == 0); \ } - - return (nequal == 0); -} +// clang-format on +VL_GEN_HELPER_ONE_ARG(VL_EQ_R_GEN) +#undef VL_EQ_R_GEN // Internal usage -static inline int _vl_cmp_w(int words, WDataInP const lwp, WDataInP const rwp) VL_PURE { - for (int i = words - 1; i >= 0; --i) { - if (lwp[i] > rwp[i]) return 1; - if (lwp[i] < rwp[i]) return -1; +// clang-format off +#define _vl_cmp_w_GEN(lhsSuffix, rhsSuffix) \ +static inline int _vl_cmp_w_##lhsSuffix##rhsSuffix(int words, WDataInP lwp, WDataInP rwp) VL_PURE { \ + int i = words - 1; \ + lwp = lwp + VL_GET_TYPE_OFFSET(lhsSuffix) + (i * VL_GET_TYPE_JUMP(lhsSuffix)); \ + rwp = rwp + VL_GET_TYPE_OFFSET(rhsSuffix) + (i * VL_GET_TYPE_JUMP(rhsSuffix)); \ + for (; i >= 0; --i) { \ + if (*lwp > *rwp) return 1; \ + if (*lwp < *rwp) return -1; \ + lwp = lwp - VL_GET_TYPE_JUMP(lhsSuffix); \ + rwp = rwp - VL_GET_TYPE_JUMP(rhsSuffix); \ + } \ + return 0; /* == */ \ } - return 0; // == -} +// clang-format on +VL_GEN_HELPER_TWO_ARG(_vl_cmp_w_GEN) +#undef _vl_cmp_w_GEN -#define VL_LTS_IWW(lbits, lwp, rwp) (_vl_cmps_w(lbits, lwp, rwp) < 0) -#define VL_LTES_IWW(lbits, lwp, rwp) (_vl_cmps_w(lbits, lwp, rwp) <= 0) -#define VL_GTS_IWW(lbits, lwp, rwp) (_vl_cmps_w(lbits, lwp, rwp) > 0) -#define VL_GTES_IWW(lbits, lwp, rwp) (_vl_cmps_w(lbits, lwp, rwp) >= 0) +#define VL_LTS_IWW_TT(lbits, lwp, rwp) (_vl_cmps_w_TT(lbits, lwp, rwp) < 0) +#define VL_LTS_IWW_TV(lbits, lwp, rwp) (_vl_cmps_w_TV(lbits, lwp, rwp) < 0) +#define VL_LTS_IWW_TX(lbits, lwp, rwp) (_vl_cmps_w_TX(lbits, lwp, rwp) < 0) +#define VL_LTS_IWW_VT(lbits, lwp, rwp) (_vl_cmps_w_VT(lbits, lwp, rwp) < 0) +#define VL_LTS_IWW_VV(lbits, lwp, rwp) (_vl_cmps_w_VV(lbits, lwp, rwp) < 0) +#define VL_LTS_IWW_VX(lbits, lwp, rwp) (_vl_cmps_w_VX(lbits, lwp, rwp) < 0) +#define VL_LTS_IWW_XT(lbits, lwp, rwp) (_vl_cmps_w_XT(lbits, lwp, rwp) < 0) +#define VL_LTS_IWW_XV(lbits, lwp, rwp) (_vl_cmps_w_XV(lbits, lwp, rwp) < 0) +#define VL_LTS_IWW_XX(lbits, lwp, rwp) (_vl_cmps_w_XX(lbits, lwp, rwp) < 0) +#define VL_LTS_IWW_TT(lbits, lwp, rwp) (_vl_cmps_w_TT(lbits, lwp, rwp) < 0) +#define VL_LTS_IWW_TV(lbits, lwp, rwp) (_vl_cmps_w_TV(lbits, lwp, rwp) < 0) +#define VL_LTS_IWW_TX(lbits, lwp, rwp) (_vl_cmps_w_TX(lbits, lwp, rwp) < 0) +#define VL_LTS_IWW_VT(lbits, lwp, rwp) (_vl_cmps_w_VT(lbits, lwp, rwp) < 0) +#define VL_LTS_IWW_VV(lbits, lwp, rwp) (_vl_cmps_w_VV(lbits, lwp, rwp) < 0) +#define VL_LTS_IWW_VX(lbits, lwp, rwp) (_vl_cmps_w_VX(lbits, lwp, rwp) < 0) +#define VL_LTS_IWW_XT(lbits, lwp, rwp) (_vl_cmps_w_XT(lbits, lwp, rwp) < 0) +#define VL_LTS_IWW_XV(lbits, lwp, rwp) (_vl_cmps_w_XV(lbits, lwp, rwp) < 0) +#define VL_LTS_IWW_XX(lbits, lwp, rwp) (_vl_cmps_w_XX(lbits, lwp, rwp) < 0) +#define VL_LTES_IWW_TT(lbits, lwp, rwp) (_vl_cmps_w_TT(lbits, lwp, rwp) <= 0) +#define VL_LTES_IWW_TV(lbits, lwp, rwp) (_vl_cmps_w_TV(lbits, lwp, rwp) <= 0) +#define VL_LTES_IWW_TX(lbits, lwp, rwp) (_vl_cmps_w_TX(lbits, lwp, rwp) <= 0) +#define VL_LTES_IWW_VT(lbits, lwp, rwp) (_vl_cmps_w_VT(lbits, lwp, rwp) <= 0) +#define VL_LTES_IWW_VV(lbits, lwp, rwp) (_vl_cmps_w_VV(lbits, lwp, rwp) <= 0) +#define VL_LTES_IWW_VX(lbits, lwp, rwp) (_vl_cmps_w_VX(lbits, lwp, rwp) <= 0) +#define VL_LTES_IWW_XT(lbits, lwp, rwp) (_vl_cmps_w_XT(lbits, lwp, rwp) <= 0) +#define VL_LTES_IWW_XV(lbits, lwp, rwp) (_vl_cmps_w_XV(lbits, lwp, rwp) <= 0) +#define VL_LTES_IWW_XX(lbits, lwp, rwp) (_vl_cmps_w_XX(lbits, lwp, rwp) <= 0) +#define VL_LTES_IWW_TT(lbits, lwp, rwp) (_vl_cmps_w_TT(lbits, lwp, rwp) <= 0) +#define VL_LTES_IWW_TV(lbits, lwp, rwp) (_vl_cmps_w_TV(lbits, lwp, rwp) <= 0) +#define VL_LTES_IWW_TX(lbits, lwp, rwp) (_vl_cmps_w_TX(lbits, lwp, rwp) <= 0) +#define VL_LTES_IWW_VT(lbits, lwp, rwp) (_vl_cmps_w_VT(lbits, lwp, rwp) <= 0) +#define VL_LTES_IWW_VV(lbits, lwp, rwp) (_vl_cmps_w_VV(lbits, lwp, rwp) <= 0) +#define VL_LTES_IWW_VX(lbits, lwp, rwp) (_vl_cmps_w_VX(lbits, lwp, rwp) <= 0) +#define VL_LTES_IWW_XT(lbits, lwp, rwp) (_vl_cmps_w_XT(lbits, lwp, rwp) <= 0) +#define VL_LTES_IWW_XV(lbits, lwp, rwp) (_vl_cmps_w_XV(lbits, lwp, rwp) <= 0) +#define VL_LTES_IWW_XX(lbits, lwp, rwp) (_vl_cmps_w_XX(lbits, lwp, rwp) <= 0) +#define VL_GTS_IWW_TT(lbits, lwp, rwp) (_vl_cmps_w_TT(lbits, lwp, rwp) > 0) +#define VL_GTS_IWW_TV(lbits, lwp, rwp) (_vl_cmps_w_TV(lbits, lwp, rwp) > 0) +#define VL_GTS_IWW_TX(lbits, lwp, rwp) (_vl_cmps_w_TX(lbits, lwp, rwp) > 0) +#define VL_GTS_IWW_VT(lbits, lwp, rwp) (_vl_cmps_w_VT(lbits, lwp, rwp) > 0) +#define VL_GTS_IWW_VV(lbits, lwp, rwp) (_vl_cmps_w_VV(lbits, lwp, rwp) > 0) +#define VL_GTS_IWW_VX(lbits, lwp, rwp) (_vl_cmps_w_VX(lbits, lwp, rwp) > 0) +#define VL_GTS_IWW_XT(lbits, lwp, rwp) (_vl_cmps_w_XT(lbits, lwp, rwp) > 0) +#define VL_GTS_IWW_XV(lbits, lwp, rwp) (_vl_cmps_w_XV(lbits, lwp, rwp) > 0) +#define VL_GTS_IWW_XX(lbits, lwp, rwp) (_vl_cmps_w_XX(lbits, lwp, rwp) > 0) +#define VL_GTS_IWW_TT(lbits, lwp, rwp) (_vl_cmps_w_TT(lbits, lwp, rwp) > 0) +#define VL_GTS_IWW_TV(lbits, lwp, rwp) (_vl_cmps_w_TV(lbits, lwp, rwp) > 0) +#define VL_GTS_IWW_TX(lbits, lwp, rwp) (_vl_cmps_w_TX(lbits, lwp, rwp) > 0) +#define VL_GTS_IWW_VT(lbits, lwp, rwp) (_vl_cmps_w_VT(lbits, lwp, rwp) > 0) +#define VL_GTS_IWW_VV(lbits, lwp, rwp) (_vl_cmps_w_VV(lbits, lwp, rwp) > 0) +#define VL_GTS_IWW_VX(lbits, lwp, rwp) (_vl_cmps_w_VX(lbits, lwp, rwp) > 0) +#define VL_GTS_IWW_XT(lbits, lwp, rwp) (_vl_cmps_w_XT(lbits, lwp, rwp) > 0) +#define VL_GTS_IWW_XV(lbits, lwp, rwp) (_vl_cmps_w_XV(lbits, lwp, rwp) > 0) +#define VL_GTS_IWW_XX(lbits, lwp, rwp) (_vl_cmps_w_XX(lbits, lwp, rwp) > 0) +#define VL_GTES_IWW_TT(lbits, lwp, rwp) (_vl_cmps_w_TT(lbits, lwp, rwp) >= 0) +#define VL_GTES_IWW_TV(lbits, lwp, rwp) (_vl_cmps_w_TV(lbits, lwp, rwp) >= 0) +#define VL_GTES_IWW_TX(lbits, lwp, rwp) (_vl_cmps_w_TX(lbits, lwp, rwp) >= 0) +#define VL_GTES_IWW_VT(lbits, lwp, rwp) (_vl_cmps_w_VT(lbits, lwp, rwp) >= 0) +#define VL_GTES_IWW_VV(lbits, lwp, rwp) (_vl_cmps_w_VV(lbits, lwp, rwp) >= 0) +#define VL_GTES_IWW_VX(lbits, lwp, rwp) (_vl_cmps_w_VX(lbits, lwp, rwp) >= 0) +#define VL_GTES_IWW_XT(lbits, lwp, rwp) (_vl_cmps_w_XT(lbits, lwp, rwp) >= 0) +#define VL_GTES_IWW_XV(lbits, lwp, rwp) (_vl_cmps_w_XV(lbits, lwp, rwp) >= 0) +#define VL_GTES_IWW_XX(lbits, lwp, rwp) (_vl_cmps_w_XX(lbits, lwp, rwp) >= 0) +#define VL_GTES_IWW_TT(lbits, lwp, rwp) (_vl_cmps_w_TT(lbits, lwp, rwp) >= 0) +#define VL_GTES_IWW_TV(lbits, lwp, rwp) (_vl_cmps_w_TV(lbits, lwp, rwp) >= 0) +#define VL_GTES_IWW_TX(lbits, lwp, rwp) (_vl_cmps_w_TX(lbits, lwp, rwp) >= 0) +#define VL_GTES_IWW_VT(lbits, lwp, rwp) (_vl_cmps_w_VT(lbits, lwp, rwp) >= 0) +#define VL_GTES_IWW_VV(lbits, lwp, rwp) (_vl_cmps_w_VV(lbits, lwp, rwp) >= 0) +#define VL_GTES_IWW_VX(lbits, lwp, rwp) (_vl_cmps_w_VX(lbits, lwp, rwp) >= 0) +#define VL_GTES_IWW_XT(lbits, lwp, rwp) (_vl_cmps_w_XT(lbits, lwp, rwp) >= 0) +#define VL_GTES_IWW_XV(lbits, lwp, rwp) (_vl_cmps_w_XV(lbits, lwp, rwp) >= 0) +#define VL_GTES_IWW_XX(lbits, lwp, rwp) (_vl_cmps_w_XX(lbits, lwp, rwp) >= 0) -static inline IData VL_GTS_III(int lbits, IData lhs, IData rhs) VL_PURE { +static inline IData VL_GTS_III_TT(int lbits, IData lhs, IData rhs) VL_PURE { // For lbits==32, this becomes just a single instruction, otherwise ~5. // GCC 3.3.4 sign extension bugs on AMD64 architecture force us to use quad logic - const int64_t lhs_signed = VL_EXTENDS_QQ(64, lbits, lhs); // Q for gcc - const int64_t rhs_signed = VL_EXTENDS_QQ(64, lbits, rhs); // Q for gcc + const int64_t lhs_signed = VL_EXTENDS_QQ_TT(64, lbits, lhs); // Q for gcc + const int64_t rhs_signed = VL_EXTENDS_QQ_TT(64, lbits, rhs); // Q for gcc return lhs_signed > rhs_signed; } -static inline IData VL_GTS_IQQ(int lbits, QData lhs, QData rhs) VL_PURE { - const int64_t lhs_signed = VL_EXTENDS_QQ(64, lbits, lhs); - const int64_t rhs_signed = VL_EXTENDS_QQ(64, lbits, rhs); +static inline IData VL_GTS_IQQ_TT(int lbits, QData lhs, QData rhs) VL_PURE { + const int64_t lhs_signed = VL_EXTENDS_QQ_TT(64, lbits, lhs); + const int64_t rhs_signed = VL_EXTENDS_QQ_TT(64, lbits, rhs); return lhs_signed > rhs_signed; } -static inline IData VL_GTES_III(int lbits, IData lhs, IData rhs) VL_PURE { - const int64_t lhs_signed = VL_EXTENDS_QQ(64, lbits, lhs); // Q for gcc - const int64_t rhs_signed = VL_EXTENDS_QQ(64, lbits, rhs); // Q for gcc +static inline IData VL_GTES_III_TT(int lbits, IData lhs, IData rhs) VL_PURE { + const int64_t lhs_signed = VL_EXTENDS_QQ_TT(64, lbits, lhs); // Q for gcc + const int64_t rhs_signed = VL_EXTENDS_QQ_TT(64, lbits, rhs); // Q for gcc return lhs_signed >= rhs_signed; } -static inline IData VL_GTES_IQQ(int lbits, QData lhs, QData rhs) VL_PURE { - const int64_t lhs_signed = VL_EXTENDS_QQ(64, lbits, lhs); - const int64_t rhs_signed = VL_EXTENDS_QQ(64, lbits, rhs); +static inline IData VL_GTES_IQQ_TT(int lbits, QData lhs, QData rhs) VL_PURE { + const int64_t lhs_signed = VL_EXTENDS_QQ_TT(64, lbits, lhs); + const int64_t rhs_signed = VL_EXTENDS_QQ_TT(64, lbits, rhs); return lhs_signed >= rhs_signed; } -static inline IData VL_LTS_III(int lbits, IData lhs, IData rhs) VL_PURE { - const int64_t lhs_signed = VL_EXTENDS_QQ(64, lbits, lhs); // Q for gcc - const int64_t rhs_signed = VL_EXTENDS_QQ(64, lbits, rhs); // Q for gcc +static inline IData VL_LTS_III_TT(int lbits, IData lhs, IData rhs) VL_PURE { + const int64_t lhs_signed = VL_EXTENDS_QQ_TT(64, lbits, lhs); // Q for gcc + const int64_t rhs_signed = VL_EXTENDS_QQ_TT(64, lbits, rhs); // Q for gcc return lhs_signed < rhs_signed; } -static inline IData VL_LTS_IQQ(int lbits, QData lhs, QData rhs) VL_PURE { - const int64_t lhs_signed = VL_EXTENDS_QQ(64, lbits, lhs); - const int64_t rhs_signed = VL_EXTENDS_QQ(64, lbits, rhs); +static inline IData VL_LTS_IQQ_TT(int lbits, QData lhs, QData rhs) VL_PURE { + const int64_t lhs_signed = VL_EXTENDS_QQ_TT(64, lbits, lhs); + const int64_t rhs_signed = VL_EXTENDS_QQ_TT(64, lbits, rhs); return lhs_signed < rhs_signed; } -static inline IData VL_LTES_III(int lbits, IData lhs, IData rhs) VL_PURE { - const int64_t lhs_signed = VL_EXTENDS_QQ(64, lbits, lhs); // Q for gcc - const int64_t rhs_signed = VL_EXTENDS_QQ(64, lbits, rhs); // Q for gcc +static inline IData VL_LTES_III_TT(int lbits, IData lhs, IData rhs) VL_PURE { + const int64_t lhs_signed = VL_EXTENDS_QQ_TT(64, lbits, lhs); // Q for gcc + const int64_t rhs_signed = VL_EXTENDS_QQ_TT(64, lbits, rhs); // Q for gcc return lhs_signed <= rhs_signed; } -static inline IData VL_LTES_IQQ(int lbits, QData lhs, QData rhs) VL_PURE { - const int64_t lhs_signed = VL_EXTENDS_QQ(64, lbits, lhs); - const int64_t rhs_signed = VL_EXTENDS_QQ(64, lbits, rhs); +static inline IData VL_LTES_IQQ_TT(int lbits, QData lhs, QData rhs) VL_PURE { + const int64_t lhs_signed = VL_EXTENDS_QQ_TT(64, lbits, lhs); + const int64_t rhs_signed = VL_EXTENDS_QQ_TT(64, lbits, rhs); return lhs_signed <= rhs_signed; } -static inline int _vl_cmps_w(int lbits, WDataInP const lwp, WDataInP const rwp) VL_PURE { - const int words = VL_WORDS_I(lbits); - int i = words - 1; - // We need to flip sense if negative comparison - const EData lsign = VL_SIGN_E(lbits, lwp[i]); - const EData rsign = VL_SIGN_E(lbits, rwp[i]); - if (!lsign && rsign) return 1; // + > - - if (lsign && !rsign) return -1; // - < + - for (; i >= 0; --i) { - if (lwp[i] > rwp[i]) return 1; - if (lwp[i] < rwp[i]) return -1; +// clang-format off +#define _vl_cmps_w_GEN(lhsSuffix, rhsSuffix) \ +static inline int _vl_cmps_w_##lhsSuffix##rhsSuffix(int lbits, WDataInP lwp, WDataInP rwp) VL_PURE { \ + const int words = VL_WORDS_I(lbits); \ + int i = words - 1; \ + lwp = lwp + VL_GET_TYPE_OFFSET(lhsSuffix) + (i * VL_GET_TYPE_JUMP(lhsSuffix)); \ + rwp = rwp + VL_GET_TYPE_OFFSET(rhsSuffix) + (i * VL_GET_TYPE_JUMP(rhsSuffix)); \ + /* We need to flip sense if negative comparison */ \ + const EData lsign = VL_SIGN_E_T(lbits, *lwp); \ + const EData rsign = VL_SIGN_E_T(lbits, *rwp); \ + if (!lsign && rsign) return 1; /* + > - */ \ + if (lsign && !rsign) return -1; /* - < + */ \ + for (; i >= 0; --i) { \ + if (*lwp > *rwp) return 1; \ + if (*lwp < *rwp) return -1; \ + lwp = lwp - VL_GET_TYPE_JUMP(lhsSuffix); \ + rwp = rwp - VL_GET_TYPE_JUMP(rhsSuffix); \ + } \ + return 0; /* == */ \ } - return 0; // == -} +// clang-format on +VL_GEN_HELPER_TWO_ARG(_vl_cmps_w_GEN) +#undef _vl_cmps_w_GEN //========================================================================= // Expressions // Output NOT clean -static inline WDataOutP VL_NEGATE_W(int words, WDataOutP owp, WDataInP const lwp) VL_MT_SAFE { - EData carry = 1; - for (int i = 0; i < words; ++i) { - owp[i] = ~lwp[i] + carry; - carry = (owp[i] < ~lwp[i]); +// clang-format off +#define VL_NEGATE_W_GEN(outputSuffix, lhsSuffix) \ +static inline WDataOutP VL_NEGATE_W_##outputSuffix##lhsSuffix(int words, WDataOutP owp, WDataInP lwp) VL_MT_SAFE { \ + const WDataOutP resultp = owp; \ + owp += VL_GET_TYPE_OFFSET(outputSuffix); \ + lwp += VL_GET_TYPE_OFFSET(lhsSuffix); \ + EData carry = 1; \ + for (int i = 0; i < words; ++i) { \ + *owp = ~(*lwp) + carry; \ + carry = (*owp < ~(*lwp)); \ + owp += VL_GET_TYPE_JUMP(outputSuffix); \ + lwp += VL_GET_TYPE_JUMP(lhsSuffix); \ + } \ + return resultp; \ } - return owp; -} -static inline void VL_NEGATE_INPLACE_W(int words, WDataOutP owp_lwp) VL_MT_SAFE { - EData carry = 1; - for (int i = 0; i < words; ++i) { - const EData word = ~owp_lwp[i] + carry; - carry = (word < ~owp_lwp[i]); - owp_lwp[i] = word; +// clang-format on +VL_GEN_HELPER_TWO_ARG(VL_NEGATE_W_GEN) +#undef VL_NEGATE_W_GEN + +// clang-format off +#define VL_NEGATE_INPLACE_W_GEN(suffix) \ +static inline void VL_NEGATE_INPLACE_W_##suffix(int words, WDataOutP owp_lwp) VL_MT_SAFE { \ + owp_lwp += VL_GET_TYPE_OFFSET(suffix); \ + EData carry = 1; \ + for (int i = 0; i < words; ++i) { \ + const EData word = ~(*owp_lwp) + carry; \ + carry = (word < ~(*owp_lwp)); \ + (*owp_lwp) = word; \ + owp_lwp += VL_GET_TYPE_JUMP(suffix); \ + } \ } -} +// clang-format on + +VL_GEN_HELPER_ONE_ARG(VL_NEGATE_INPLACE_W_GEN) +#undef VL_NEGATE_INPLACE_W_GEN // EMIT_RULE: VL_MUL: oclean=dirty; lclean==clean; rclean==clean; // EMIT_RULE: VL_DIV: oclean=dirty; lclean==clean; rclean==clean; // EMIT_RULE: VL_MODDIV: oclean=dirty; lclean==clean; rclean==clean; -static inline IData VL_DIV_III(int /*lbits*/, IData lhs, IData rhs) { +static inline IData VL_DIV_III_TTT(int /*lbits*/, IData lhs, IData rhs) { return (rhs == 0) ? 0 : lhs / rhs; } -static inline QData VL_DIV_QQQ(int /*lbits*/, QData lhs, QData rhs) { +static inline QData VL_DIV_QQQ_TTT(int /*lbits*/, QData lhs, QData rhs) { return (rhs == 0) ? 0 : lhs / rhs; } -#define VL_DIV_WWW(lbits, owp, lwp, rwp) (_vl_moddiv_w(lbits, owp, lwp, rwp, 0)) -static inline IData VL_MODDIV_III(int /*lbits*/, IData lhs, IData rhs) { +#define VL_DIV_WWW_TTT(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 0, VL_GET_TYPE_OFFSET(T), VL_GET_TYPE_JUMP(T), \ + VL_GET_TYPE_OFFSET(T), VL_GET_TYPE_JUMP(T), VL_GET_TYPE_OFFSET(T), \ + VL_GET_TYPE_JUMP(T))) +#define VL_DIV_WWW_TTV(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 0, VL_GET_TYPE_OFFSET(T), VL_GET_TYPE_JUMP(T), \ + VL_GET_TYPE_OFFSET(T), VL_GET_TYPE_JUMP(T), VL_GET_TYPE_OFFSET(V), \ + VL_GET_TYPE_JUMP(V))) +#define VL_DIV_WWW_TTX(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 0, VL_GET_TYPE_OFFSET(T), VL_GET_TYPE_JUMP(T), \ + VL_GET_TYPE_OFFSET(T), VL_GET_TYPE_JUMP(T), VL_GET_TYPE_OFFSET(X), \ + VL_GET_TYPE_JUMP(X))) +#define VL_DIV_WWW_TVT(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 0, VL_GET_TYPE_OFFSET(T), VL_GET_TYPE_JUMP(T), \ + VL_GET_TYPE_OFFSET(V), VL_GET_TYPE_JUMP(V), VL_GET_TYPE_OFFSET(T), \ + VL_GET_TYPE_JUMP(T))) +#define VL_DIV_WWW_TVV(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 0, VL_GET_TYPE_OFFSET(T), VL_GET_TYPE_JUMP(T), \ + VL_GET_TYPE_OFFSET(V), VL_GET_TYPE_JUMP(V), VL_GET_TYPE_OFFSET(V), \ + VL_GET_TYPE_JUMP(V))) +#define VL_DIV_WWW_TVX(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 0, VL_GET_TYPE_OFFSET(T), VL_GET_TYPE_JUMP(T), \ + VL_GET_TYPE_OFFSET(V), VL_GET_TYPE_JUMP(V), VL_GET_TYPE_OFFSET(X), \ + VL_GET_TYPE_JUMP(X))) +#define VL_DIV_WWW_TXT(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 0, VL_GET_TYPE_OFFSET(T), VL_GET_TYPE_JUMP(T), \ + VL_GET_TYPE_OFFSET(X), VL_GET_TYPE_JUMP(X), VL_GET_TYPE_OFFSET(T), \ + VL_GET_TYPE_JUMP(T))) +#define VL_DIV_WWW_TXV(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 0, VL_GET_TYPE_OFFSET(T), VL_GET_TYPE_JUMP(T), \ + VL_GET_TYPE_OFFSET(X), VL_GET_TYPE_JUMP(X), VL_GET_TYPE_OFFSET(V), \ + VL_GET_TYPE_JUMP(V))) +#define VL_DIV_WWW_TXX(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 0, VL_GET_TYPE_OFFSET(T), VL_GET_TYPE_JUMP(T), \ + VL_GET_TYPE_OFFSET(X), VL_GET_TYPE_JUMP(X), VL_GET_TYPE_OFFSET(X), \ + VL_GET_TYPE_JUMP(X))) +#define VL_DIV_WWW_VTT(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 0, VL_GET_TYPE_OFFSET(V), VL_GET_TYPE_JUMP(V), \ + VL_GET_TYPE_OFFSET(T), VL_GET_TYPE_JUMP(T), VL_GET_TYPE_OFFSET(T), \ + VL_GET_TYPE_JUMP(T))) +#define VL_DIV_WWW_VTV(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 0, VL_GET_TYPE_OFFSET(V), VL_GET_TYPE_JUMP(V), \ + VL_GET_TYPE_OFFSET(T), VL_GET_TYPE_JUMP(T), VL_GET_TYPE_OFFSET(V), \ + VL_GET_TYPE_JUMP(V))) +#define VL_DIV_WWW_VTX(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 0, VL_GET_TYPE_OFFSET(V), VL_GET_TYPE_JUMP(V), \ + VL_GET_TYPE_OFFSET(T), VL_GET_TYPE_JUMP(T), VL_GET_TYPE_OFFSET(X), \ + VL_GET_TYPE_JUMP(X))) +#define VL_DIV_WWW_VVT(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 0, VL_GET_TYPE_OFFSET(V), VL_GET_TYPE_JUMP(V), \ + VL_GET_TYPE_OFFSET(V), VL_GET_TYPE_JUMP(V), VL_GET_TYPE_OFFSET(T), \ + VL_GET_TYPE_JUMP(T))) +#define VL_DIV_WWW_VVV(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 0, VL_GET_TYPE_OFFSET(V), VL_GET_TYPE_JUMP(V), \ + VL_GET_TYPE_OFFSET(V), VL_GET_TYPE_JUMP(V), VL_GET_TYPE_OFFSET(V), \ + VL_GET_TYPE_JUMP(V))) +#define VL_DIV_WWW_VVX(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 0, VL_GET_TYPE_OFFSET(V), VL_GET_TYPE_JUMP(V), \ + VL_GET_TYPE_OFFSET(V), VL_GET_TYPE_JUMP(V), VL_GET_TYPE_OFFSET(X), \ + VL_GET_TYPE_JUMP(X))) +#define VL_DIV_WWW_VXT(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 0, VL_GET_TYPE_OFFSET(V), VL_GET_TYPE_JUMP(V), \ + VL_GET_TYPE_OFFSET(X), VL_GET_TYPE_JUMP(X), VL_GET_TYPE_OFFSET(T), \ + VL_GET_TYPE_JUMP(T))) +#define VL_DIV_WWW_VXV(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 0, VL_GET_TYPE_OFFSET(V), VL_GET_TYPE_JUMP(V), \ + VL_GET_TYPE_OFFSET(X), VL_GET_TYPE_JUMP(X), VL_GET_TYPE_OFFSET(V), \ + VL_GET_TYPE_JUMP(V))) +#define VL_DIV_WWW_VXX(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 0, VL_GET_TYPE_OFFSET(V), VL_GET_TYPE_JUMP(V), \ + VL_GET_TYPE_OFFSET(X), VL_GET_TYPE_JUMP(X), VL_GET_TYPE_OFFSET(X), \ + VL_GET_TYPE_JUMP(X))) +#define VL_DIV_WWW_XTT(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 0, VL_GET_TYPE_OFFSET(X), VL_GET_TYPE_JUMP(X), \ + VL_GET_TYPE_OFFSET(T), VL_GET_TYPE_JUMP(T), VL_GET_TYPE_OFFSET(T), \ + VL_GET_TYPE_JUMP(T))) +#define VL_DIV_WWW_XTV(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 0, VL_GET_TYPE_OFFSET(X), VL_GET_TYPE_JUMP(X), \ + VL_GET_TYPE_OFFSET(T), VL_GET_TYPE_JUMP(T), VL_GET_TYPE_OFFSET(V), \ + VL_GET_TYPE_JUMP(V))) +#define VL_DIV_WWW_XTX(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 0, VL_GET_TYPE_OFFSET(X), VL_GET_TYPE_JUMP(X), \ + VL_GET_TYPE_OFFSET(T), VL_GET_TYPE_JUMP(T), VL_GET_TYPE_OFFSET(X), \ + VL_GET_TYPE_JUMP(X))) +#define VL_DIV_WWW_XVT(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 0, VL_GET_TYPE_OFFSET(X), VL_GET_TYPE_JUMP(X), \ + VL_GET_TYPE_OFFSET(V), VL_GET_TYPE_JUMP(V), VL_GET_TYPE_OFFSET(T), \ + VL_GET_TYPE_JUMP(T))) +#define VL_DIV_WWW_XVV(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 0, VL_GET_TYPE_OFFSET(X), VL_GET_TYPE_JUMP(X), \ + VL_GET_TYPE_OFFSET(V), VL_GET_TYPE_JUMP(V), VL_GET_TYPE_OFFSET(V), \ + VL_GET_TYPE_JUMP(V))) +#define VL_DIV_WWW_XVX(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 0, VL_GET_TYPE_OFFSET(X), VL_GET_TYPE_JUMP(X), \ + VL_GET_TYPE_OFFSET(V), VL_GET_TYPE_JUMP(V), VL_GET_TYPE_OFFSET(X), \ + VL_GET_TYPE_JUMP(X))) +#define VL_DIV_WWW_XXT(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 0, VL_GET_TYPE_OFFSET(X), VL_GET_TYPE_JUMP(X), \ + VL_GET_TYPE_OFFSET(X), VL_GET_TYPE_JUMP(X), VL_GET_TYPE_OFFSET(T), \ + VL_GET_TYPE_JUMP(T))) +#define VL_DIV_WWW_XXV(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 0, VL_GET_TYPE_OFFSET(X), VL_GET_TYPE_JUMP(X), \ + VL_GET_TYPE_OFFSET(X), VL_GET_TYPE_JUMP(X), VL_GET_TYPE_OFFSET(V), \ + VL_GET_TYPE_JUMP(V))) +#define VL_DIV_WWW_XXX(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 0, VL_GET_TYPE_OFFSET(X), VL_GET_TYPE_JUMP(X), \ + VL_GET_TYPE_OFFSET(X), VL_GET_TYPE_JUMP(X), VL_GET_TYPE_OFFSET(X), \ + VL_GET_TYPE_JUMP(X))) + +static inline IData VL_MODDIV_III_TTT(int /*lbits*/, IData lhs, IData rhs) { return (rhs == 0) ? 0 : lhs % rhs; } -static inline QData VL_MODDIV_QQQ(int /*lbits*/, QData lhs, QData rhs) { +static inline QData VL_MODDIV_QQQ_TTT(int /*lbits*/, QData lhs, QData rhs) { return (rhs == 0) ? 0 : lhs % rhs; } -#define VL_MODDIV_WWW(lbits, owp, lwp, rwp) (_vl_moddiv_w(lbits, owp, lwp, rwp, 1)) +#define VL_MODDIV_WWW_TTT(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 1, VL_GET_TYPE_OFFSET(T), VL_GET_TYPE_JUMP(T), \ + VL_GET_TYPE_OFFSET(T), VL_GET_TYPE_JUMP(T), VL_GET_TYPE_OFFSET(T), \ + VL_GET_TYPE_JUMP(T))) +#define VL_MODDIV_WWW_TTV(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 1, VL_GET_TYPE_OFFSET(T), VL_GET_TYPE_JUMP(T), \ + VL_GET_TYPE_OFFSET(T), VL_GET_TYPE_JUMP(T), VL_GET_TYPE_OFFSET(V), \ + VL_GET_TYPE_JUMP(V))) +#define VL_MODDIV_WWW_TTX(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 1, VL_GET_TYPE_OFFSET(T), VL_GET_TYPE_JUMP(T), \ + VL_GET_TYPE_OFFSET(T), VL_GET_TYPE_JUMP(T), VL_GET_TYPE_OFFSET(X), \ + VL_GET_TYPE_JUMP(X))) +#define VL_MODDIV_WWW_TVT(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 1, VL_GET_TYPE_OFFSET(T), VL_GET_TYPE_JUMP(T), \ + VL_GET_TYPE_OFFSET(V), VL_GET_TYPE_JUMP(V), VL_GET_TYPE_OFFSET(T), \ + VL_GET_TYPE_JUMP(T))) +#define VL_MODDIV_WWW_TVV(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 1, VL_GET_TYPE_OFFSET(T), VL_GET_TYPE_JUMP(T), \ + VL_GET_TYPE_OFFSET(V), VL_GET_TYPE_JUMP(V), VL_GET_TYPE_OFFSET(V), \ + VL_GET_TYPE_JUMP(V))) +#define VL_MODDIV_WWW_TVX(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 1, VL_GET_TYPE_OFFSET(T), VL_GET_TYPE_JUMP(T), \ + VL_GET_TYPE_OFFSET(V), VL_GET_TYPE_JUMP(V), VL_GET_TYPE_OFFSET(X), \ + VL_GET_TYPE_JUMP(X))) +#define VL_MODDIV_WWW_TXT(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 1, VL_GET_TYPE_OFFSET(T), VL_GET_TYPE_JUMP(T), \ + VL_GET_TYPE_OFFSET(X), VL_GET_TYPE_JUMP(X), VL_GET_TYPE_OFFSET(T), \ + VL_GET_TYPE_JUMP(T))) +#define VL_MODDIV_WWW_TXV(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 1, VL_GET_TYPE_OFFSET(T), VL_GET_TYPE_JUMP(T), \ + VL_GET_TYPE_OFFSET(X), VL_GET_TYPE_JUMP(X), VL_GET_TYPE_OFFSET(V), \ + VL_GET_TYPE_JUMP(V))) +#define VL_MODDIV_WWW_TXX(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 1, VL_GET_TYPE_OFFSET(T), VL_GET_TYPE_JUMP(T), \ + VL_GET_TYPE_OFFSET(X), VL_GET_TYPE_JUMP(X), VL_GET_TYPE_OFFSET(X), \ + VL_GET_TYPE_JUMP(X))) +#define VL_MODDIV_WWW_VTT(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 1, VL_GET_TYPE_OFFSET(V), VL_GET_TYPE_JUMP(V), \ + VL_GET_TYPE_OFFSET(T), VL_GET_TYPE_JUMP(T), VL_GET_TYPE_OFFSET(T), \ + VL_GET_TYPE_JUMP(T))) +#define VL_MODDIV_WWW_VTV(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 1, VL_GET_TYPE_OFFSET(V), VL_GET_TYPE_JUMP(V), \ + VL_GET_TYPE_OFFSET(T), VL_GET_TYPE_JUMP(T), VL_GET_TYPE_OFFSET(V), \ + VL_GET_TYPE_JUMP(V))) +#define VL_MODDIV_WWW_VTX(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 1, VL_GET_TYPE_OFFSET(V), VL_GET_TYPE_JUMP(V), \ + VL_GET_TYPE_OFFSET(T), VL_GET_TYPE_JUMP(T), VL_GET_TYPE_OFFSET(X), \ + VL_GET_TYPE_JUMP(X))) +#define VL_MODDIV_WWW_VVT(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 1, VL_GET_TYPE_OFFSET(V), VL_GET_TYPE_JUMP(V), \ + VL_GET_TYPE_OFFSET(V), VL_GET_TYPE_JUMP(V), VL_GET_TYPE_OFFSET(T), \ + VL_GET_TYPE_JUMP(T))) +#define VL_MODDIV_WWW_VVV(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 1, VL_GET_TYPE_OFFSET(V), VL_GET_TYPE_JUMP(V), \ + VL_GET_TYPE_OFFSET(V), VL_GET_TYPE_JUMP(V), VL_GET_TYPE_OFFSET(V), \ + VL_GET_TYPE_JUMP(V))) +#define VL_MODDIV_WWW_VVX(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 1, VL_GET_TYPE_OFFSET(V), VL_GET_TYPE_JUMP(V), \ + VL_GET_TYPE_OFFSET(V), VL_GET_TYPE_JUMP(V), VL_GET_TYPE_OFFSET(X), \ + VL_GET_TYPE_JUMP(X))) +#define VL_MODDIV_WWW_VXT(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 1, VL_GET_TYPE_OFFSET(V), VL_GET_TYPE_JUMP(V), \ + VL_GET_TYPE_OFFSET(X), VL_GET_TYPE_JUMP(X), VL_GET_TYPE_OFFSET(T), \ + VL_GET_TYPE_JUMP(T))) +#define VL_MODDIV_WWW_VXV(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 1, VL_GET_TYPE_OFFSET(V), VL_GET_TYPE_JUMP(V), \ + VL_GET_TYPE_OFFSET(X), VL_GET_TYPE_JUMP(X), VL_GET_TYPE_OFFSET(V), \ + VL_GET_TYPE_JUMP(V))) +#define VL_MODDIV_WWW_VXX(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 1, VL_GET_TYPE_OFFSET(V), VL_GET_TYPE_JUMP(V), \ + VL_GET_TYPE_OFFSET(X), VL_GET_TYPE_JUMP(X), VL_GET_TYPE_OFFSET(X), \ + VL_GET_TYPE_JUMP(X))) +#define VL_MODDIV_WWW_XTT(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 1, VL_GET_TYPE_OFFSET(X), VL_GET_TYPE_JUMP(X), \ + VL_GET_TYPE_OFFSET(T), VL_GET_TYPE_JUMP(T), VL_GET_TYPE_OFFSET(T), \ + VL_GET_TYPE_JUMP(T))) +#define VL_MODDIV_WWW_XTV(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 1, VL_GET_TYPE_OFFSET(X), VL_GET_TYPE_JUMP(X), \ + VL_GET_TYPE_OFFSET(T), VL_GET_TYPE_JUMP(T), VL_GET_TYPE_OFFSET(V), \ + VL_GET_TYPE_JUMP(V))) +#define VL_MODDIV_WWW_XTX(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 1, VL_GET_TYPE_OFFSET(X), VL_GET_TYPE_JUMP(X), \ + VL_GET_TYPE_OFFSET(T), VL_GET_TYPE_JUMP(T), VL_GET_TYPE_OFFSET(X), \ + VL_GET_TYPE_JUMP(X))) +#define VL_MODDIV_WWW_XVT(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 1, VL_GET_TYPE_OFFSET(X), VL_GET_TYPE_JUMP(X), \ + VL_GET_TYPE_OFFSET(V), VL_GET_TYPE_JUMP(V), VL_GET_TYPE_OFFSET(T), \ + VL_GET_TYPE_JUMP(T))) +#define VL_MODDIV_WWW_XVV(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 1, VL_GET_TYPE_OFFSET(X), VL_GET_TYPE_JUMP(X), \ + VL_GET_TYPE_OFFSET(V), VL_GET_TYPE_JUMP(V), VL_GET_TYPE_OFFSET(V), \ + VL_GET_TYPE_JUMP(V))) +#define VL_MODDIV_WWW_XVX(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 1, VL_GET_TYPE_OFFSET(X), VL_GET_TYPE_JUMP(X), \ + VL_GET_TYPE_OFFSET(V), VL_GET_TYPE_JUMP(V), VL_GET_TYPE_OFFSET(X), \ + VL_GET_TYPE_JUMP(X))) +#define VL_MODDIV_WWW_XXT(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 1, VL_GET_TYPE_OFFSET(X), VL_GET_TYPE_JUMP(X), \ + VL_GET_TYPE_OFFSET(X), VL_GET_TYPE_JUMP(X), VL_GET_TYPE_OFFSET(T), \ + VL_GET_TYPE_JUMP(T))) +#define VL_MODDIV_WWW_XXV(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 1, VL_GET_TYPE_OFFSET(X), VL_GET_TYPE_JUMP(X), \ + VL_GET_TYPE_OFFSET(X), VL_GET_TYPE_JUMP(X), VL_GET_TYPE_OFFSET(V), \ + VL_GET_TYPE_JUMP(V))) +#define VL_MODDIV_WWW_XXX(lbits, owp, lwp, rwp) \ + (_vl_moddiv_w(lbits, owp, lwp, rwp, 1, VL_GET_TYPE_OFFSET(X), VL_GET_TYPE_JUMP(X), \ + VL_GET_TYPE_OFFSET(X), VL_GET_TYPE_JUMP(X), VL_GET_TYPE_OFFSET(X), \ + VL_GET_TYPE_JUMP(X))) -static inline WDataOutP VL_ADD_W(int words, WDataOutP owp, WDataInP const lwp, - WDataInP const rwp) VL_MT_SAFE { - QData carry = 0; - for (int i = 0; i < words; ++i) { - carry = carry + static_cast(lwp[i]) + static_cast(rwp[i]); - owp[i] = (carry & 0xffffffffULL); - carry = (carry >> 32ULL) & 0xffffffffULL; - } - // Last output word is dirty - return owp; +// clang-format off +#define VL_ADD_GEN(outputSuffix, lhsSuffix, rhsSuffix) \ +static inline WDataOutP VL_ADD_W_##outputSuffix##lhsSuffix##rhsSuffix(int words, WDataOutP owp, WDataInP lwp, \ + WDataInP rwp) VL_MT_SAFE { \ + const WDataOutP result = owp; \ + owp += VL_GET_TYPE_OFFSET(outputSuffix); \ + lwp += VL_GET_TYPE_OFFSET(lhsSuffix); \ + rwp += VL_GET_TYPE_OFFSET(rhsSuffix); \ + QData carry = 0; \ + for (int i = 0; i < words; ++i) { \ + carry = carry + static_cast(*lwp) + static_cast(*rwp); \ + *owp = (carry & 0xffffffffULL); \ + carry = (carry >> 32ULL) & 0xffffffffULL; \ + owp += VL_GET_TYPE_JUMP(outputSuffix); \ + lwp += VL_GET_TYPE_JUMP(lhsSuffix); \ + rwp += VL_GET_TYPE_JUMP(rhsSuffix); \ + } \ + /* Last output word is dirty */ \ + return result; \ } +// clang-format on +VL_GEN_HELPER_THREE_ARG(VL_ADD_GEN) +#undef VL_ADD_GEN -static inline WDataOutP VL_SUB_W(int words, WDataOutP owp, WDataInP const lwp, - WDataInP const rwp) VL_MT_SAFE { - QData carry = 0; - for (int i = 0; i < words; ++i) { - carry = (carry + static_cast(lwp[i]) - + static_cast(static_cast(~rwp[i]))); - if (i == 0) ++carry; // Negation of rwp - owp[i] = (carry & 0xffffffffULL); - carry = (carry >> 32ULL) & 0xffffffffULL; - } - // Last output word is dirty - return owp; +// clang-format off +#define VL_SUB_GEN(outputSuffix, lhsSuffix, rhsSuffix) \ +static inline WDataOutP VL_SUB_W_##outputSuffix##lhsSuffix##rhsSuffix(int words, WDataOutP owp, WDataInP lwp, \ + WDataInP rwp) VL_MT_SAFE { \ + const WDataOutP result = owp; \ + owp += VL_GET_TYPE_OFFSET(outputSuffix); \ + lwp += VL_GET_TYPE_OFFSET(lhsSuffix); \ + rwp += VL_GET_TYPE_OFFSET(rhsSuffix); \ + QData carry = 0; \ + for (int i = 0; i < words; ++i) { \ + carry = (carry + static_cast(*lwp) \ + + static_cast(static_cast(~*rwp))); \ + if (i == 0) ++carry; /* Negation of rwp */ \ + *owp = (carry & 0xffffffffULL); \ + carry = (carry >> 32ULL) & 0xffffffffULL; \ + owp += VL_GET_TYPE_JUMP(outputSuffix); \ + lwp += VL_GET_TYPE_JUMP(lhsSuffix); \ + rwp += VL_GET_TYPE_JUMP(rhsSuffix); \ + } \ + /* Last output word is dirty */ \ + return result; \ } +// clang-format on +VL_GEN_HELPER_THREE_ARG(VL_SUB_GEN) +#undef VL_SUB_GEN -static inline WDataOutP VL_MUL_W(int words, WDataOutP owp, WDataInP const lwp, - WDataInP const rwp) VL_MT_SAFE { - for (int i = 0; i < words; ++i) owp[i] = 0; - for (int lword = 0; lword < words; ++lword) { - for (int rword = 0; rword < words; ++rword) { - QData mul = static_cast(lwp[lword]) * static_cast(rwp[rword]); - for (int qword = lword + rword; qword < words; ++qword) { - mul += static_cast(owp[qword]); - owp[qword] = (mul & 0xffffffffULL); - mul = (mul >> 32ULL) & 0xffffffffULL; - } - } - } - // Last output word is dirty - return owp; +// clang-format off +#define VL_MUL_GEN(outputSuffix, lhsSuffix, rhsSuffix) \ +static inline WDataOutP VL_MUL_W_##outputSuffix##lhsSuffix##rhsSuffix(int words, WDataOutP owp, WDataInP lwp, \ + WDataInP rwp) VL_MT_SAFE { \ + const WDataOutP result = owp; \ + owp += VL_GET_TYPE_OFFSET(outputSuffix); \ + lwp += VL_GET_TYPE_OFFSET(lhsSuffix); \ + rwp += VL_GET_TYPE_OFFSET(rhsSuffix); \ + for (int i = 0; i < words; ++i) { \ + *owp = 0; \ + owp += VL_GET_TYPE_JUMP(outputSuffix); \ + } \ + for (int lword = 0; lword < words; ++lword) { \ + WDataInP currentRwp = rwp; \ + for (int rword = 0; rword < words; ++rword) { \ + QData mul = static_cast(*lwp) * static_cast(*currentRwp); \ + int qword = lword + rword; \ + owp = result + VL_GET_TYPE_OFFSET(outputSuffix) + qword * VL_GET_TYPE_JUMP(outputSuffix); \ + for (; qword < words; ++qword) { \ + mul += static_cast(*owp); \ + *owp = (mul & 0xffffffffULL); \ + mul = (mul >> 32ULL) & 0xffffffffULL; \ + owp += VL_GET_TYPE_JUMP(outputSuffix); \ + } \ + currentRwp += VL_GET_TYPE_JUMP(rhsSuffix); \ + } \ + lwp += VL_GET_TYPE_JUMP(lhsSuffix); \ + } \ + /* Last output word is dirty */ \ + return result; \ } +// clang-format on +VL_GEN_HELPER_THREE_ARG(VL_MUL_GEN) +#undef VL_MUL_GEN -static inline IData VL_MULS_III(int lbits, IData lhs, IData rhs) VL_PURE { - const int32_t lhs_signed = VL_EXTENDS_II(32, lbits, lhs); - const int32_t rhs_signed = VL_EXTENDS_II(32, lbits, rhs); +static inline IData VL_MULS_III_TTT(int lbits, IData lhs, IData rhs) VL_PURE { + const int32_t lhs_signed = VL_EXTENDS_II_TT(32, lbits, lhs); + const int32_t rhs_signed = VL_EXTENDS_II_TT(32, lbits, rhs); return lhs_signed * rhs_signed; } -static inline QData VL_MULS_QQQ(int lbits, QData lhs, QData rhs) VL_PURE { - const int64_t lhs_signed = VL_EXTENDS_QQ(64, lbits, lhs); - const int64_t rhs_signed = VL_EXTENDS_QQ(64, lbits, rhs); +static inline QData VL_MULS_QQQ_TTT(int lbits, QData lhs, QData rhs) VL_PURE { + const int64_t lhs_signed = VL_EXTENDS_QQ_TT(64, lbits, lhs); + const int64_t rhs_signed = VL_EXTENDS_QQ_TT(64, lbits, rhs); return lhs_signed * rhs_signed; } -static inline WDataOutP VL_MULS_WWW(int lbits, WDataOutP owp, WDataInP lwp, - WDataInP rwp) VL_MT_SAFE { - const int words = VL_WORDS_I(lbits); - VL_DEBUG_IFDEF(assert(words <= VL_MULS_MAX_WORDS);); - VlWide lwstore; - VlWide rwstore; - const EData lneg = VL_SIGN_E(lbits, lwp[words - 1]); - if (lneg) { // Negate lhs - VL_NEGATE_W(words, lwstore, lwp); - lwstore[words - 1] &= VL_MASK_E(lbits); // Clean it - lwp = lwstore; +// clang-format off +#define VL_MULS_WWW_GEN(outputSuffix, lhsSuffix, rhsSuffix) \ +static inline WDataOutP VL_MULS_WWW_##outputSuffix##lhsSuffix##rhsSuffix( \ + int lbits, WDataOutP owp, WDataInP const lwp, WDataInP const rwp) VL_MT_SAFE { \ + const WDataOutP resultp = owp; \ + const int words = VL_WORDS_I(lbits); \ + VL_DEBUG_IFDEF(assert(words <= VL_MULS_MAX_WORDS);); \ + /* cppcheck-suppress variableScope */ \ + VlWide lwstore; /* Fixed size, as MSVC++ doesn't allow [words] here */ \ + /* cppcheck-suppress variableScope */ \ + VlWide rwstore; \ + WDataInP lwusp = lwp; \ + WDataInP rwusp = rwp; \ + const EData lneg = VL_SIGN_E_T(lbits, *VL_GET_ELEM(lhsSuffix, lwp, words - 1)); \ + if (lneg) { /* Negate lhs */ \ + lwusp = lwstore; \ + VL_NEGATE_W_T##lhsSuffix(words, lwstore, lwp); \ + lwstore[words - 1] &= VL_MASK_E(lbits); /* Clean it */ \ + } \ + const EData rneg = VL_SIGN_E_T(lbits, *VL_GET_ELEM(rhsSuffix, rwp, words - 1)); \ + if (rneg) { /* Negate rhs */ \ + rwusp = rwstore; \ + VL_NEGATE_W_T##rhsSuffix(words, rwstore, rwp); \ + rwstore[words - 1] &= VL_MASK_E(lbits); /* Clean it */ \ + } \ + if (rneg) { \ + if (lneg) { \ + VL_MUL_W_##outputSuffix##TT(words, owp, lwusp, rwusp); \ + } else { \ + VL_MUL_W_##outputSuffix##lhsSuffix##T(words, owp, lwusp, rwusp); \ + } \ + } else { \ + if (lneg) { \ + VL_MUL_W_##outputSuffix##T##rhsSuffix(words, owp, lwusp, rwusp); \ + } else { \ + VL_MUL_W_##outputSuffix##lhsSuffix##rhsSuffix(words, owp, lwusp, rwusp); \ + } \ + } \ + *VL_GET_ELEM(outputSuffix, owp, words - 1) &= VL_MASK_E( \ + lbits); /* Clean. Note it's ok for the multiply to overflow into the sign bit */ \ + if ((lneg ^ rneg) & 1) { /* Negate output (not using NEGATE, as owp==lwp) */ \ + QData carry = 0; \ + owp += VL_GET_TYPE_OFFSET(outputSuffix); \ + for (int i = 0; i < words; ++i) { \ + carry = carry + static_cast(static_cast(~*owp)); \ + if (i == 0) ++carry; /* Negation of temp2 */ \ + *owp = (carry & 0xffffffffULL); \ + carry = (carry >> 32ULL) & 0xffffffffULL; \ + owp += VL_GET_TYPE_JUMP(outputSuffix); \ + } \ + /* Not needed: owp[words-1] |= 1<(static_cast(~owp[i])); - if (i == 0) ++carry; // Negation of temp2 - owp[i] = (carry & 0xffffffffULL); - carry = (carry >> 32ULL) & 0xffffffffULL; - } - // Not needed: owp[words-1] |= 1< lwstore; - VlWide rwstore; - if (lsign) lwp = _vl_clean_inplace_w(lbits, VL_NEGATE_W(lwords, lwstore, lwp)); - if (rsign) rwp = _vl_clean_inplace_w(lbits, VL_NEGATE_W(lwords, rwstore, rwp)); - if ((lsign && !rsign) || (!lsign && rsign)) { - VlWide qNoSign; - VL_DIV_WWW(lbits, qNoSign, lwp, rwp); - _vl_clean_inplace_w(lbits, VL_NEGATE_W(lwords, owp, qNoSign)); - return owp; +// clang-format off +#define VL_DIVS_WWW_GEN(outputSuffix, lhsSuffix, rhsSuffix) \ +static inline WDataOutP VL_DIVS_WWW_##outputSuffix##lhsSuffix##rhsSuffix( \ + int lbits, WDataOutP owp, WDataInP const lwp, WDataInP const rwp) VL_MT_SAFE { \ + const int lwords = VL_WORDS_I(lbits); \ + const EData lsign = VL_SIGN_E_T(lbits, *VL_GET_ELEM(lhsSuffix, lwp, lwords - 1)); \ + const EData rsign = VL_SIGN_E_T(lbits, *VL_GET_ELEM(rhsSuffix, rwp, lwords - 1)); \ + VL_DEBUG_IFDEF(assert(lwords <= VL_MULS_MAX_WORDS);); \ + /* cppcheck-suppress variableScope */ \ + VlWide lwstore; /* Fixed size, as MSVC++ doesn't allow [words] here */ \ + /* cppcheck-suppress variableScope */ \ + VlWide rwstore; \ + WDataInP ltup = lwp; \ + WDataInP rtup = rwp; \ + if (lsign) ltup = _vl_clean_inplace_w_T(lbits, VL_NEGATE_W_T##lhsSuffix(lwords, lwstore, lwp)); \ + if (rsign) rtup = _vl_clean_inplace_w_T(lbits, VL_NEGATE_W_T##rhsSuffix(lwords, rwstore, rwp)); \ + if ((lsign && !rsign) || (!lsign && rsign)) { \ + VlWide qNoSign; \ + if (lsign && !rsign) { \ + VL_DIV_WWW_TT##rhsSuffix(lbits, qNoSign, ltup, rtup); \ + } else { \ + VL_DIV_WWW_T##lhsSuffix##T(lbits, qNoSign, ltup, rtup); \ + } \ + _vl_clean_inplace_w_##outputSuffix(lbits, VL_NEGATE_W_##outputSuffix##T(lwords, owp, qNoSign)); \ + return owp; \ + } \ + if (lsign /*&& rsign*/) return VL_DIV_WWW_##outputSuffix##TT(lbits, owp, ltup, rtup); \ + return VL_DIV_WWW_##outputSuffix##lhsSuffix##rhsSuffix(lbits, owp, ltup, rtup); \ } - return VL_DIV_WWW(lbits, owp, lwp, rwp); -} -static inline WDataOutP VL_MODDIVS_WWW(int lbits, WDataOutP owp, WDataInP lwp, - WDataInP rwp) VL_MT_SAFE { - const int lwords = VL_WORDS_I(lbits); - const EData lsign = VL_SIGN_E(lbits, lwp[lwords - 1]); - const EData rsign = VL_SIGN_E(lbits, rwp[lwords - 1]); - VL_DEBUG_IFDEF(assert(lwords <= VL_MULS_MAX_WORDS);); - VlWide lwstore; - VlWide rwstore; - if (lsign) lwp = _vl_clean_inplace_w(lbits, VL_NEGATE_W(lwords, lwstore, lwp)); - if (rsign) rwp = _vl_clean_inplace_w(lbits, VL_NEGATE_W(lwords, rwstore, rwp)); - if (lsign) { // Only dividend sign matters for modulus - VlWide qNoSign; - VL_MODDIV_WWW(lbits, qNoSign, lwp, rwp); - _vl_clean_inplace_w(lbits, VL_NEGATE_W(lwords, owp, qNoSign)); - return owp; +// clang-format on +VL_GEN_HELPER_THREE_ARG(VL_DIVS_WWW_GEN) +#undef VL_DIVS_WWW_GEN + +// clang-format off +#define VL_MODDIVS_WWW_GEN(outputSuffix, lhsSuffix, rhsSuffix) \ +static inline WDataOutP VL_MODDIVS_WWW_##outputSuffix##lhsSuffix##rhsSuffix( \ + int lbits, WDataOutP owp, WDataInP const lwp, WDataInP const rwp) VL_MT_SAFE { \ + const int lwords = VL_WORDS_I(lbits); \ + const EData lsign = VL_SIGN_E_T(lbits, *VL_GET_ELEM(lhsSuffix, lwp, lwords - 1)); \ + const EData rsign = VL_SIGN_E_T(lbits, *VL_GET_ELEM(rhsSuffix, rwp, lwords - 1)); \ + VL_DEBUG_IFDEF(assert(lwords <= VL_MULS_MAX_WORDS);); \ + /* cppcheck-suppress variableScope */ \ + VlWide lwstore; /* Fixed size, as MSVC++ doesn't allow [words] here */ \ + /* cppcheck-suppress variableScope */ \ + VlWide rwstore; \ + WDataInP ltup = lwp; \ + WDataInP rtup = rwp; \ + if (lsign) ltup = _vl_clean_inplace_w_T(lbits, VL_NEGATE_W_T##lhsSuffix(lwords, lwstore, lwp)); \ + if (rsign) rtup = _vl_clean_inplace_w_T(lbits, VL_NEGATE_W_T##rhsSuffix(lwords, rwstore, rwp)); \ + if (lsign) { /* Only dividend sign matters for modulus */ \ + VlWide qNoSign; \ + if (rsign) { \ + VL_MODDIV_WWW_TTT(lbits, qNoSign, ltup, rtup); \ + } else { \ + VL_MODDIV_WWW_TT##rhsSuffix(lbits, qNoSign, ltup, rtup); \ + } \ + _vl_clean_inplace_w_##outputSuffix(lbits, VL_NEGATE_W_##outputSuffix##T(lwords, owp, qNoSign)); \ + return owp; \ + } \ + if (rsign) return VL_MODDIV_WWW_##outputSuffix##lhsSuffix##T(lbits, owp, ltup, rtup); \ + return VL_MODDIV_WWW_##outputSuffix##lhsSuffix##rhsSuffix(lbits, owp, ltup, rtup); \ } - return VL_MODDIV_WWW(lbits, owp, lwp, rwp); -} +// clang-format on +VL_GEN_HELPER_THREE_ARG(VL_MODDIVS_WWW_GEN) +#undef VL_MODDIVS_WWW_GEN #define VL_POW_IIQ(obits, lbits, rbits, lhs, rhs) VL_POW_QQQ(obits, lbits, rbits, lhs, rhs) #define VL_POW_IIW(obits, lbits, rbits, lhs, rwp) VL_POW_QQW(obits, lbits, rbits, lhs, rwp) @@ -1374,7 +2201,7 @@ QData VL_POW_QQW(int obits, int, int rbits, QData lhs, WDataInP const rwp) VL_MT static inline IData VL_POWSS_III(int obits, int, int rbits, IData lhs, IData rhs, bool lsign, bool rsign) VL_MT_SAFE { if (VL_UNLIKELY(rhs == 0)) return 1; - if (rsign && VL_SIGN_I(rbits, rhs)) { + if (rsign && VL_SIGN_I_T(rbits, rhs)) { if (lhs == 0) { return 0; // "X" } @@ -1390,7 +2217,7 @@ static inline IData VL_POWSS_III(int obits, int, int rbits, IData lhs, IData rhs static inline QData VL_POWSS_QQQ(int obits, int, int rbits, QData lhs, QData rhs, bool lsign, bool rsign) VL_MT_SAFE { if (VL_UNLIKELY(rhs == 0)) return 1; - if (rsign && VL_SIGN_Q(rbits, rhs)) { + if (rsign && VL_SIGN_Q_T(rbits, rhs)) { if (lhs == 0) return 0; // "X" if (lhs == 1) return 1; @@ -1434,133 +2261,160 @@ static inline void _vl_insert_QQ(QData& lhsr, QData ld, int hbit, int lbit, int const QData insmask = (VL_MASK_Q(hbit - lbit + 1)) << lbit; lhsr = (lhsr & ~insmask) | ((ld << lbit) & (insmask & cleanmask)); } -static inline void _vl_insert_WI(WDataOutP iowp, IData ld, int hbit, int lbit, - int rbits = 0) VL_MT_SAFE { - // Insert value ld into iowp at bit slice [hbit:lbit]. iowp is rbits wide. - const int hoffset = VL_BITBIT_E(hbit); - const int loffset = VL_BITBIT_E(lbit); - const int roffset = VL_BITBIT_E(rbits); - const int hword = VL_BITWORD_E(hbit); - const int lword = VL_BITWORD_E(lbit); - const int rword = VL_BITWORD_E(rbits); - const EData cleanmask = hword == rword ? VL_MASK_E(roffset) : VL_MASK_E(0); - - if (hoffset == VL_SIZEBITS_E && loffset == 0) { - // Fast and common case, word based insertion - iowp[lword] = ld & cleanmask; - } else { - const EData lde = static_cast(ld); - if (hword == lword) { // know < EData bits because above checks it - // Assignment is contained within one word of destination - const EData insmask = (VL_MASK_E(hoffset - loffset + 1)) << loffset; - iowp[lword] = (iowp[lword] & ~insmask) | ((lde << loffset) & (insmask & cleanmask)); - } else { - // Assignment crosses a word boundary in destination - const EData hinsmask = (VL_MASK_E(hoffset - 0 + 1)) << 0; - const EData linsmask = (VL_MASK_E((VL_EDATASIZE - 1) - loffset + 1)) << loffset; - const int nbitsonright = VL_EDATASIZE - loffset; // bits that end up in lword - iowp[lword] = (iowp[lword] & ~linsmask) | ((lde << loffset) & linsmask); - // Prevent unsafe write where lword was final writable location and hword is - // out-of-bounds. - if (VL_LIKELY(!(hword == rword && roffset == 0))) { - iowp[hword] - = (iowp[hword] & ~hinsmask) | ((lde >> nbitsonright) & (hinsmask & cleanmask)); - } - } +// clang-format off +#define _vl_insert_WI_GEN(outputSuffix) \ +static inline void _vl_insert_WI_##outputSuffix(WDataOutP iowp, IData ld, int hbit, int lbit, \ + int rbits = 0) VL_MT_SAFE { \ + /* Insert value ld into iowp at bit slice [hbit:lbit]. iowp is rbits wide. */ \ + const int hoffset = VL_BITBIT_E(hbit); \ + const int loffset = VL_BITBIT_E(lbit); \ + const int roffset = VL_BITBIT_E(rbits); \ + const int hword = VL_BITWORD_E(hbit); \ + const int lword = VL_BITWORD_E(lbit); \ + const int rword = VL_BITWORD_E(rbits); \ + const EData cleanmask = hword == rword ? VL_MASK_E(roffset) : VL_MASK_E(0); \ + if (hoffset == VL_SIZEBITS_E && loffset == 0) { \ + /* Fast and common case, word based insertion */ \ + *VL_GET_ELEM(outputSuffix, iowp, lword) = ld & cleanmask; \ + } else { \ + const EData lde = static_cast(ld); \ + if (hword == lword) { /* know < EData bits because above checks it */ \ + /* Assignment is contained within one word of destination */ \ + const EData insmask = (VL_MASK_E(hoffset - loffset + 1)) << loffset; \ + iowp = VL_GET_ELEM(outputSuffix, iowp, lword); \ + *iowp = (*iowp & ~insmask) | ((lde << loffset) & (insmask & cleanmask)); \ + } else { \ + /* Assignment crosses a word boundary in destination */ \ + const EData hinsmask = (VL_MASK_E(hoffset - 0 + 1)) << 0; \ + const EData linsmask = (VL_MASK_E((VL_EDATASIZE - 1) - loffset + 1)) << loffset; \ + const int nbitsonright = VL_EDATASIZE - loffset; /* bits that end up in lword */ \ + *VL_GET_ELEM(outputSuffix, iowp, lword) \ + = (*VL_GET_ELEM(outputSuffix, iowp, lword) & ~linsmask) \ + | ((lde << loffset) & linsmask); \ + /* Prevent unsafe write where lword was final writable location and hword is \ + out-of-bounds. */ \ + if (VL_LIKELY(!(hword == rword && roffset == 0))) { \ + iowp = VL_GET_ELEM(outputSuffix, iowp, hword); \ + *iowp \ + = (*iowp & ~hinsmask) | ((lde >> nbitsonright) & (hinsmask & cleanmask)); \ + } \ + } \ + } \ } -} +// clang-format on +VL_GEN_HELPER_ONE_ARG(_vl_insert_WI_GEN) +#undef _vl_insert_WI_GEN // Copy bits from lwp[hbit:lbit] to low bits of lhsr. rbits is real width of lshr -static inline void _vl_insert_IW(IData& lhsr, WDataInP const lwp, int hbit, int lbit, - int rbits = 0) VL_MT_SAFE { - const int hoffset = VL_BITBIT_E(hbit); - const int loffset = VL_BITBIT_E(lbit); - const int hword = VL_BITWORD_E(hbit); - const int lword = VL_BITWORD_E(lbit); - const IData cleanmask = VL_MASK_I(rbits); - if (hword == lword) { - const IData insmask = (VL_MASK_I(hoffset - loffset + 1)); - lhsr = (lhsr & ~insmask) | ((lwp[lword] >> loffset) & (insmask & cleanmask)); - } else { - const int nbitsonright = VL_IDATASIZE - loffset; // bits that filled by lword - const IData hinsmask = (VL_MASK_E(hoffset - 0 + 1)) << nbitsonright; - const IData linsmask = VL_MASK_E(VL_EDATASIZE - loffset); - lhsr = (lhsr & ~linsmask) | ((lwp[lword] >> loffset) & (linsmask & cleanmask)); - lhsr = (lhsr & ~hinsmask) | ((lwp[hword] << nbitsonright) & (hinsmask & cleanmask)); +// clang-format off +#define _vl_insert_IW_GEN(rhsSuffix) \ +static inline void _vl_insert_IW_T##rhsSuffix(IData& lhsr, WDataInP const lwp, int hbit, \ + int lbit, int rbits = 0) VL_MT_SAFE { \ + const int hoffset = VL_BITBIT_E(hbit); \ + const int loffset = VL_BITBIT_E(lbit); \ + const int hword = VL_BITWORD_E(hbit); \ + const int lword = VL_BITWORD_E(lbit); \ + const IData cleanmask = VL_MASK_I(rbits); \ + if (hword == lword) { \ + const IData insmask = (VL_MASK_I(hoffset - loffset + 1)); \ + lhsr = (lhsr & ~insmask) \ + | ((*VL_GET_ELEM(rhsSuffix, lwp, lword) >> loffset) & (insmask & cleanmask)); \ + } else { \ + const int nbitsonright = VL_IDATASIZE - loffset; /* bits that filled by lword */ \ + const IData hinsmask = (VL_MASK_E(hoffset - 0 + 1)) << nbitsonright; \ + const IData linsmask = VL_MASK_E(VL_EDATASIZE - loffset); \ + lhsr = (lhsr & ~linsmask) \ + | ((*VL_GET_ELEM(rhsSuffix, lwp, lword) >> loffset) & (linsmask & cleanmask)); \ + lhsr = (lhsr & ~hinsmask) \ + | ((*VL_GET_ELEM(rhsSuffix, lwp, hword) << nbitsonright) \ + & (hinsmask & cleanmask)); \ + } \ } -} +// clang-format on +VL_GEN_HELPER_ONE_ARG(_vl_insert_IW_GEN) +#undef _vl_insert_IW_GEN +// clang-format off // INTERNAL: Stuff large LHS bit 0++ into OUTPUT at specified offset // lwp may be "dirty" -static inline void _vl_insert_WW(WDataOutP iowp, WDataInP const lwp, int hbit, int lbit, - int rbits = 0) VL_MT_SAFE { - const int hoffset = VL_BITBIT_E(hbit); - const int loffset = VL_BITBIT_E(lbit); - const int roffset = VL_BITBIT_E(rbits); - const int lword = VL_BITWORD_E(lbit); - const int hword = VL_BITWORD_E(hbit); - const int rword = VL_BITWORD_E(rbits); - const int words = VL_WORDS_I(hbit - lbit + 1); - // Cleaning mask, only applied to top word of the assignment. Is a no-op - // if we don't assign to the top word of the destination. - const EData cleanmask = hword == rword ? VL_MASK_E(roffset) : VL_MASK_E(0); - - if (hoffset == VL_SIZEBITS_E && loffset == 0) { - // Fast and common case, word based insertion - for (int i = 0; i < (words - 1); ++i) iowp[lword + i] = lwp[i]; - iowp[hword] = lwp[words - 1] & cleanmask; - } else if (loffset == 0) { - // Non-32bit, but nicely aligned, so stuff all but the last word - for (int i = 0; i < (words - 1); ++i) iowp[lword + i] = lwp[i]; - // Know it's not a full word as above fast case handled it - const EData hinsmask = (VL_MASK_E(hoffset - 0 + 1)); - iowp[hword] = (iowp[hword] & ~hinsmask) | (lwp[words - 1] & (hinsmask & cleanmask)); - } else { - const EData hinsmask = (VL_MASK_E(hoffset - 0 + 1)) << 0; - const EData linsmask = (VL_MASK_E((VL_EDATASIZE - 1) - loffset + 1)) << loffset; - const int nbitsonright - = VL_EDATASIZE - loffset; // bits that end up in lword (know loffset!=0) - // Middle words - for (int i = 0; i < words; ++i) { - { // Lower word - const int oword = lword + i; - const EData d = lwp[i] << loffset; - const EData od = (iowp[oword] & ~linsmask) | (d & linsmask); - if (oword == hword) { - iowp[oword] = (iowp[oword] & ~hinsmask) | (od & (hinsmask & cleanmask)); - } else { - iowp[oword] = od; - } - } - { // Upper word - const int oword = lword + i + 1; - if (oword <= hword) { - const EData d = lwp[i] >> nbitsonright; - const EData od = (d & ~linsmask) | (iowp[oword] & linsmask); - if (oword == hword) { - iowp[oword] = (iowp[oword] & ~hinsmask) | (od & (hinsmask & cleanmask)); - } else { - iowp[oword] = od; - } - } - } - } +#define _vl_insert_WW_GEN(outputSuffix, lhsSuffix) \ +static inline void _vl_insert_WW_##outputSuffix##lhsSuffix(WDataOutP iowp, WDataInP const lwp, int hbit, int lbit, \ + int rbits = 0) VL_MT_SAFE { \ + const int hoffset = VL_BITBIT_E(hbit); \ + const int loffset = VL_BITBIT_E(lbit); \ + const int roffset = VL_BITBIT_E(rbits); \ + const int lword = VL_BITWORD_E(lbit); \ + const int hword = VL_BITWORD_E(hbit); \ + const int rword = VL_BITWORD_E(rbits); \ + const int words = VL_WORDS_I(hbit - lbit + 1); \ + /* Cleaning mask, only applied to top word of the assignment. Is a no-op \ + if we don't assign to the top word of the destination. */ \ + const EData cleanmask = hword == rword ? VL_MASK_E(roffset) : VL_MASK_E(0); \ +\ + if (hoffset == VL_SIZEBITS_E && loffset == 0) { \ + /* Fast and common case, word based insertion */ \ + for (int i = 0; i < (words - 1); ++i) *VL_GET_ELEM(outputSuffix, iowp, lword + i) = *VL_GET_ELEM(lhsSuffix, lwp, i); \ + *VL_GET_ELEM(outputSuffix, iowp, hword) = *VL_GET_ELEM(lhsSuffix, lwp, words - 1) & cleanmask; \ + } else if (loffset == 0) { \ + /* Non-32bit, but nicely aligned, so stuff all but the last word */ \ + for (int i = 0; i < (words - 1); ++i) *VL_GET_ELEM(outputSuffix, iowp, lword + i) = *VL_GET_ELEM(lhsSuffix, lwp, i); \ + /* Know it's not a full word as above fast case handled it */ \ + const EData hinsmask = (VL_MASK_E(hoffset - 0 + 1)); \ + *VL_GET_ELEM(outputSuffix, iowp, hword) = (*VL_GET_ELEM(outputSuffix, iowp, hword) & ~hinsmask) | (*VL_GET_ELEM(lhsSuffix, lwp, words - 1) & (hinsmask & cleanmask)); \ + } else { \ + const EData hinsmask = (VL_MASK_E(hoffset - 0 + 1)) << 0; \ + const EData linsmask = (VL_MASK_E((VL_EDATASIZE - 1) - loffset + 1)) << loffset; \ + const int nbitsonright \ + = VL_EDATASIZE - loffset; /* bits that end up in lword (know loffset!=0) */ \ + /* Middle words */ \ + for (int i = 0; i < words; ++i) { \ + { /* Lower word */ \ + const int oword = lword + i; \ + const EData d = *VL_GET_ELEM(lhsSuffix, lwp, i) << loffset; \ + const EData od = (*VL_GET_ELEM(outputSuffix, iowp, oword) & ~linsmask) | (d & linsmask); \ + if (oword == hword) { \ + *VL_GET_ELEM(outputSuffix, iowp, oword) = (*VL_GET_ELEM(outputSuffix, iowp, oword) & ~hinsmask) | (od & (hinsmask & cleanmask)); \ + } else { \ + *VL_GET_ELEM(outputSuffix, iowp, oword) = od; \ + } \ + } \ + { /* Upper word */ \ + const int oword = lword + i + 1; \ + if (oword <= hword) { \ + const EData d = *VL_GET_ELEM(lhsSuffix, lwp, i) >> nbitsonright; \ + const EData od = (d & ~linsmask) | (*VL_GET_ELEM(outputSuffix, iowp, oword) & linsmask); \ + if (oword == hword) { \ + *VL_GET_ELEM(outputSuffix, iowp, oword) \ + = (*VL_GET_ELEM(outputSuffix, iowp, oword) & ~hinsmask) | (od & (hinsmask & cleanmask)); \ + } else { \ + *VL_GET_ELEM(outputSuffix, iowp, oword) = od; \ + } \ + } \ + } \ + } \ + } \ } -} +// clang-format on +VL_GEN_HELPER_TWO_ARG(_vl_insert_WW_GEN) -static inline void _vl_insert_WQ(WDataOutP iowp, QData ld, int hbit, int lbit, - int rbits = 0) VL_MT_SAFE { - VlWide lwp; - VL_SET_WQ(lwp, ld); - _vl_insert_WW(iowp, lwp, hbit, lbit, rbits); -} +// clang-format off +#define _vl_insert_WQ_GEN(suffix) \ +static inline void _vl_insert_WQ_##suffix(WDataOutP iowp, QData ld, int hbit, int lbit, \ + int rbits = 0) VL_MT_SAFE { \ + VlWide lwp; \ + VL_SET_WQ_T(lwp, ld); \ + _vl_insert_WW_##suffix##T(iowp, lwp, hbit, lbit, rbits); \ + } +// clang-format on +VL_GEN_HELPER_ONE_ARG(_vl_insert_WQ_GEN) +#undef _vl_insert_WQ_GEN // EMIT_RULE: VL_REPLICATE: oclean=clean>width32, dirty<=width32; lclean=clean; rclean==clean; // RHS MUST BE CLEAN CONSTANT. #define VL_REPLICATE_IOI(lbits, ld, rep) (-(ld)) // Iff lbits==1 #define VL_REPLICATE_QOI(lbits, ld, rep) (-(static_cast(ld))) // Iff lbits==1 -static inline IData VL_REPLICATE_III(int lbits, IData ld, IData rep) VL_PURE { +static inline IData VL_REPLICATE_III_TTT(int lbits, IData ld, IData rep) VL_PURE { IData returndata = ld; for (unsigned i = 1; i < rep; ++i) { returndata = returndata << lbits; @@ -1568,7 +2422,7 @@ static inline IData VL_REPLICATE_III(int lbits, IData ld, IData rep) VL_PURE { } return returndata; } -static inline QData VL_REPLICATE_QII(int lbits, IData ld, IData rep) VL_PURE { +static inline QData VL_REPLICATE_QII_TTT(int lbits, IData ld, IData rep) VL_PURE { QData returndata = ld; for (unsigned i = 1; i < rep; ++i) { returndata = returndata << lbits; @@ -1576,41 +2430,73 @@ static inline QData VL_REPLICATE_QII(int lbits, IData ld, IData rep) VL_PURE { } return returndata; } -static inline WDataOutP VL_REPLICATE_WII(int lbits, WDataOutP owp, IData ld, - IData rep) VL_MT_SAFE { - owp[0] = ld; - // Zeroing all words isn't strictly needed but allows compiler to know - // it does not need to preserve data in word(s) not being written - for (unsigned i = 1; i < VL_WORDS_I(static_cast(lbits) * rep); ++i) owp[i] = 0; - for (unsigned i = 1; i < rep; ++i) { - _vl_insert_WI(owp, ld, i * lbits + lbits - 1, i * lbits); + +// clang-format off +#define VL_REPLICATE_WII_GEN(outputSuffix) \ +static inline WDataOutP VL_REPLICATE_WII_##outputSuffix##TT(int lbits, WDataOutP owp, \ + IData ld, IData rep) VL_MT_SAFE { \ + const WDataOutP resultp = owp; \ + owp += VL_GET_TYPE_OFFSET(outputSuffix); \ + *owp = ld; \ + /* Zeroing all words isn't strictly needed but allows compiler to know \ + it does not need to preserve data in word(s) not being written */ \ + for (unsigned i = 1; i < VL_WORDS_I(static_cast(lbits) * rep); ++i) { \ + owp += VL_GET_TYPE_JUMP(outputSuffix); \ + *owp = 0; \ + } \ + for (unsigned i = 1; i < rep; ++i) { \ + _vl_insert_WI_##outputSuffix(resultp, ld, i* lbits + lbits - 1, i * lbits); \ + } \ + return resultp; \ } - return owp; -} -static inline WDataOutP VL_REPLICATE_WQI(int lbits, WDataOutP owp, QData ld, - IData rep) VL_MT_SAFE { - VL_SET_WQ(owp, ld); - // Zeroing all words isn't strictly needed but allows compiler to know - // it does not need to preserve data in word(s) not being written - for (unsigned i = 2; i < VL_WORDS_I(static_cast(lbits) * rep); ++i) owp[i] = 0; - for (unsigned i = 1; i < rep; ++i) { - _vl_insert_WQ(owp, ld, i * lbits + lbits - 1, i * lbits); +// clang-format on +VL_GEN_HELPER_ONE_ARG(VL_REPLICATE_WII_GEN) +#undef VL_REPLICATE_WII_GEN + +// clang-format off +#define VL_REPLICATE_WQI_GEN(outputSuffix) \ +static inline WDataOutP VL_REPLICATE_WQI_##outputSuffix##TT(int lbits, WDataOutP owp, \ + QData ld, IData rep) VL_MT_SAFE { \ + const WDataOutP resultp = owp; \ + VL_SET_WQ_##outputSuffix(owp, ld); \ + /* Zeroing all words isn't strictly needed but allows compiler to know \ + it does not need to preserve data in word(s) not being written */ \ + owp += VL_GET_TYPE_OFFSET(outputSuffix) + VL_GET_TYPE_JUMP(outputSuffix); \ + for (unsigned i = 2; i < VL_WORDS_I(static_cast(lbits) * rep); ++i) { \ + owp += VL_GET_TYPE_JUMP(outputSuffix); \ + *owp = 0; \ + } \ + for (unsigned i = 1; i < rep; ++i) { \ + _vl_insert_WQ_##outputSuffix(resultp, ld, i* lbits + lbits - 1, i * lbits); \ + } \ + return resultp; \ } - return owp; -} -static inline WDataOutP VL_REPLICATE_WWI(int lbits, WDataOutP owp, WDataInP const lwp, - IData rep) VL_MT_SAFE { - for (unsigned i = 0; i < VL_WORDS_I(static_cast(lbits)); ++i) owp[i] = lwp[i]; - // Zeroing all words isn't strictly needed but allows compiler to know - // it does not need to preserve data in word(s) not being written - for (unsigned i = VL_WORDS_I(static_cast(lbits)); - i < VL_WORDS_I(static_cast(lbits * rep)); ++i) - owp[i] = 0; - for (unsigned i = 1; i < rep; ++i) { - _vl_insert_WW(owp, lwp, i * lbits + lbits - 1, i * lbits); +// clang-format on +VL_GEN_HELPER_ONE_ARG(VL_REPLICATE_WQI_GEN) +#undef VL_REPLICATE_WQI_GEN + +// clang-format off +#define VL_REPLICATE_WWI_GEN(outputSuffix, lhsSuffix) \ +static inline WDataOutP VL_REPLICATE_WWI_##outputSuffix##lhsSuffix##T( \ + int lbits, WDataOutP owp, WDataInP const lwp, IData rep) VL_MT_SAFE { \ + const WDataOutP resultp = owp; \ + VL_ASSIGN_W_##outputSuffix##lhsSuffix(lbits, owp, lwp); \ + /* Zeroing all words isn't strictly needed but allows compiler to know \ + it does not need to preserve data in word(s) not being written */ \ + int i = VL_WORDS_I(lbits); \ + owp += VL_GET_TYPE_OFFSET(outputSuffix) + i * VL_GET_TYPE_JUMP(outputSuffix); \ + for (; i < VL_WORDS_I(lbits * rep); ++i) { \ + *owp = 0; \ + owp += VL_GET_TYPE_JUMP(outputSuffix); \ + } \ + for (unsigned i = 1; i < rep; ++i) { \ + _vl_insert_WW_TT(resultp, lwp, i* lbits + lbits - 1, i * lbits); \ + } \ + return resultp; \ } - return owp; -} +// clang-format on +VL_GEN_HELPER_TWO_ARG(VL_REPLICATE_WWI_GEN) +#undef VL_REPLICATE_WWI_GEN // Left stream operator. Output will always be clean. LHS and RHS must be clean. // Special "fast" versions for slice sizes that are a power of 2. These use @@ -1812,7 +2698,7 @@ static inline void VL_STREAMR_RQI(int lbits, VlQueue>& q, QData IData rd_log2) VL_PURE { q.clear(); // Empty the queue first VlWide value; - VL_SET_WQ(value, ld); + VL_SET_WQ_T(value, ld); q.push_back(value); } @@ -1823,11 +2709,11 @@ static inline void VL_STREAMR_RWI(int lbits, VlQueue& q, WDataInP const lwp, const int numWords = VL_BITWORD_E(lbits); QData qdataValue = 0; for (int word = numWords - 1; word >= 0; word--) { - VL_CONSTEXPR_CXX17 int valueSize = sizeof(T); + constexpr int valueSize = sizeof(T); if VL_CONSTEXPR_CXX17 (valueSize < 4) { - VL_CONSTEXPR_CXX17 int mask = VL_MASK_I(valueSize * 8); + constexpr int mask = VL_MASK_I(valueSize * 8); // Push all bytes of the 32-bit integer, MSB first (Big-Endian) - VL_CONSTEXPR_CXX17 int qElementsPerWord = 4 / valueSize; + constexpr int qElementsPerWord = 4 / valueSize; for (int i = 0; i < qElementsPerWord; i++) { q.push_back(static_cast( ((lwp[word] >> (qElementsPerWord - i - 1) * 8 * valueSize)) & mask)); @@ -2112,7 +2998,7 @@ static inline QData VL_STREAML_QQI(int lbits, QData ld, IData rd) VL_PURE { static inline WDataOutP VL_STREAML_WWI(int lbits, WDataOutP owp, WDataInP const lwp, IData rd) VL_MT_SAFE { - VL_ZERO_W(lbits, owp); + VL_ZERO_W_T(lbits, owp); // Slice size should never exceed the lhs width const int ssize = (rd < static_cast(lbits)) ? rd : (static_cast(lbits)); for (int istart = 0; istart < lbits; istart += rd) { @@ -2324,8 +3210,8 @@ static inline WDataOutP VL_PACK_W_RI(int obits, int lbits, WDataOutP owp, if (VL_UNLIKELY(obits < q.size() * lbits)) return owp; // Though is illegal for q to be larger const int offset = obits - q.size() * lbits; for (size_t i = 0; i < q.size(); ++i) - _vl_insert_WI(owp, q.at(q.size() - i - 1), i * lbits + lbits - 1 + offset, - i * lbits + offset); + _vl_insert_WI_T(owp, q.at(q.size() - i - 1), i * lbits + lbits - 1 + offset, + i * lbits + offset); return owp; } @@ -2335,8 +3221,8 @@ static inline WDataOutP VL_PACK_W_RI(int obits, int lbits, WDataOutP owp, if (VL_UNLIKELY(obits < q.size() * lbits)) return owp; // Though is illegal for q to be larger const int offset = obits - q.size() * lbits; for (size_t i = 0; i < q.size(); ++i) - _vl_insert_WI(owp, q.at(q.size() - i - 1), i * lbits + lbits - 1 + offset, - i * lbits + offset); + _vl_insert_WI_T(owp, q.at(q.size() - i - 1), i * lbits + lbits - 1 + offset, + i * lbits + offset); return owp; } @@ -2346,8 +3232,8 @@ static inline WDataOutP VL_PACK_W_RI(int obits, int lbits, WDataOutP owp, if (VL_UNLIKELY(obits < q.size() * lbits)) return owp; // Though is illegal for q to be larger const int offset = obits - q.size() * lbits; for (size_t i = 0; i < q.size(); ++i) - _vl_insert_WI(owp, q.at(q.size() - 1 - i), i * lbits + lbits - 1 + offset, - i * lbits + offset); + _vl_insert_WI_T(owp, q.at(q.size() - 1 - i), i * lbits + lbits - 1 + offset, + i * lbits + offset); return owp; } @@ -2356,7 +3242,7 @@ static inline WDataOutP VL_PACK_W_UI(int obits, int lbits, WDataOutP owp, const VlUnpacked& q) { VL_MEMSET_ZERO_W(owp + 1, VL_WORDS_I(obits) - 1); for (size_t i = 0; i < N_Depth; ++i) - _vl_insert_WI(owp, q[N_Depth - 1 - i], i * lbits + lbits - 1, i * lbits); + _vl_insert_WI_T(owp, q[N_Depth - 1 - i], i * lbits + lbits - 1, i * lbits); return owp; } @@ -2365,7 +3251,7 @@ static inline WDataOutP VL_PACK_W_UI(int obits, int lbits, WDataOutP owp, const VlUnpacked& q) { VL_MEMSET_ZERO_W(owp + 1, VL_WORDS_I(obits) - 1); for (size_t i = 0; i < N_Depth; ++i) - _vl_insert_WI(owp, q[N_Depth - 1 - i], i * lbits + lbits - 1, i * lbits); + _vl_insert_WI_T(owp, q[N_Depth - 1 - i], i * lbits + lbits - 1, i * lbits); return owp; } @@ -2374,7 +3260,7 @@ static inline WDataOutP VL_PACK_W_UI(int obits, int lbits, WDataOutP owp, const VlUnpacked& q) { VL_MEMSET_ZERO_W(owp + 1, VL_WORDS_I(obits) - 1); for (size_t i = 0; i < N_Depth; ++i) - _vl_insert_WI(owp, q[N_Depth - 1 - i], i * lbits + lbits - 1, i * lbits); + _vl_insert_WI_T(owp, q[N_Depth - 1 - i], i * lbits + lbits - 1, i * lbits); return owp; } @@ -2384,8 +3270,8 @@ static inline WDataOutP VL_PACK_W_RQ(int obits, int lbits, WDataOutP owp, if (VL_UNLIKELY(obits < q.size() * lbits)) return owp; // Though is illegal for q to be larger const int offset = obits - q.size() * lbits; for (size_t i = 0; i < q.size(); ++i) - _vl_insert_WQ(owp, q.at(q.size() - 1 - i), i * lbits + lbits - 1 + offset, - i * lbits + offset); + _vl_insert_WQ_T(owp, q.at(q.size() - 1 - i), i * lbits + lbits - 1 + offset, + i * lbits + offset); return owp; } @@ -2394,7 +3280,7 @@ static inline WDataOutP VL_PACK_W_UQ(int obits, int lbits, WDataOutP owp, const VlUnpacked& q) { VL_MEMSET_ZERO_W(owp + 1, VL_WORDS_I(obits) - 1); for (size_t i = 0; i < N_Depth; ++i) - _vl_insert_WQ(owp, q[N_Depth - 1 - i], i * lbits + lbits - 1, i * lbits); + _vl_insert_WQ_T(owp, q[N_Depth - 1 - i], i * lbits + lbits - 1, i * lbits); return owp; } @@ -2405,8 +3291,8 @@ static inline WDataOutP VL_PACK_W_RW(int obits, int lbits, WDataOutP owp, if (VL_UNLIKELY(obits < q.size() * lbits)) return owp; // Though is illegal for q to be larger const int offset = obits - q.size() * lbits; for (size_t i = 0; i < q.size(); ++i) - _vl_insert_WW(owp, q.at(q.size() - 1 - i), i * lbits + lbits - 1 + offset, - i * lbits + offset); + _vl_insert_WW_TT(owp, q.at(q.size() - 1 - i), i * lbits + lbits - 1 + offset, + i * lbits + offset); return owp; } @@ -2417,7 +3303,8 @@ static inline WDataOutP VL_PACK_W_UW(int obits, int lbits, WDataOutP owp, if (VL_UNLIKELY(obits < q.size() * lbits)) return owp; // Though is illegal for q to be larger const int offset = obits - q.size() * lbits; for (size_t i = 0; i < N_Depth; ++i) - _vl_insert_WW(owp, q[N_Depth - 1 - i], i * lbits + lbits - 1 + offset, i * lbits + offset); + _vl_insert_WW_TT(owp, q[N_Depth - 1 - i], i * lbits + lbits - 1 + offset, + i * lbits + offset); return owp; } @@ -2425,84 +3312,143 @@ static inline WDataOutP VL_PACK_W_UW(int obits, int lbits, WDataOutP owp, // Thus we specify inputs must be clean, so we don't need to clean the output. // Note the bit shifts are always constants, so the adds in these constify out. // Casts required, as args may be 8 bit entities, and need to shift to appropriate output size -#define VL_CONCAT_III(obits, lbits, rbits, ld, rd) \ +#define VL_CONCAT_III_TTT(obits, lbits, rbits, ld, rd) \ (static_cast(ld) << (rbits) | static_cast(rd)) -#define VL_CONCAT_QII(obits, lbits, rbits, ld, rd) \ +#define VL_CONCAT_QII_TTT(obits, lbits, rbits, ld, rd) \ (static_cast(ld) << (rbits) | static_cast(rd)) -#define VL_CONCAT_QIQ(obits, lbits, rbits, ld, rd) \ +#define VL_CONCAT_QIQ_TTT(obits, lbits, rbits, ld, rd) \ (static_cast(ld) << (rbits) | static_cast(rd)) -#define VL_CONCAT_QQI(obits, lbits, rbits, ld, rd) \ +#define VL_CONCAT_QQI_TTT(obits, lbits, rbits, ld, rd) \ (static_cast(ld) << (rbits) | static_cast(rd)) -#define VL_CONCAT_QQQ(obits, lbits, rbits, ld, rd) \ +#define VL_CONCAT_QQQ_TTT(obits, lbits, rbits, ld, rd) \ (static_cast(ld) << (rbits) | static_cast(rd)) -static inline WDataOutP VL_CONCAT_WII(int obits, int lbits, int rbits, WDataOutP owp, IData ld, - IData rd) VL_MT_SAFE { - owp[0] = rd; - VL_MEMSET_ZERO_W(owp + 1, VL_WORDS_I(obits) - 1); - _vl_insert_WI(owp, ld, rbits + lbits - 1, rbits); - return owp; -} -static inline WDataOutP VL_CONCAT_WWI(int obits, int lbits, int rbits, WDataOutP owp, - WDataInP const lwp, IData rd) VL_MT_SAFE { - owp[0] = rd; - VL_MEMSET_ZERO_W(owp + 1, VL_WORDS_I(obits) - 1); - _vl_insert_WW(owp, lwp, rbits + lbits - 1, rbits); - return owp; -} +// clang-format off +#define VL_CONCAT_WII_GEN(outputSuffix) \ +static inline WDataOutP VL_CONCAT_WII_##outputSuffix##TT( \ + int obits, int lbits, int rbits, WDataOutP const owp, IData ld, IData rd) VL_MT_SAFE { \ + *VL_GET_ELEM(outputSuffix, owp, 0) = rd; \ + VL_ZERO_OFFSET_W_##outputSuffix(obits - VL_EDATASIZE, VL_GET_ELEM(outputSuffix, owp, 1)); \ + _vl_insert_WI_##outputSuffix(owp, ld, rbits + lbits - 1, rbits); \ + return owp; \ + } +// clang-format on +VL_GEN_HELPER_ONE_ARG(VL_CONCAT_WII_GEN) +#undef VL_CONCAT_WII_GEN -static inline WDataOutP VL_CONCAT_WIW(int obits, int lbits, int rbits, WDataOutP owp, IData ld, - WDataInP const rwp) VL_MT_SAFE { - const int rwords = VL_WORDS_I(rbits); - VL_MEMCPY_W(owp, rwp, rwords); - VL_MEMSET_ZERO_W(owp + rwords, VL_WORDS_I(obits) - rwords); - _vl_insert_WI(owp, ld, rbits + lbits - 1, rbits); - return owp; -} -static inline WDataOutP VL_CONCAT_WIQ(int obits, int lbits, int rbits, WDataOutP owp, IData ld, - QData rd) VL_MT_SAFE { - VL_SET_WQ(owp, rd); - VL_MEMSET_ZERO_W(owp + VL_WQ_WORDS_E, VL_WORDS_I(obits) - VL_WQ_WORDS_E); - _vl_insert_WI(owp, ld, rbits + lbits - 1, rbits); - return owp; -} -static inline WDataOutP VL_CONCAT_WQI(int obits, int lbits, int rbits, WDataOutP owp, QData ld, - IData rd) VL_MT_SAFE { - owp[0] = rd; - VL_MEMSET_ZERO_W(owp + 1, VL_WORDS_I(obits) - 1); - _vl_insert_WQ(owp, ld, rbits + lbits - 1, rbits); - return owp; -} -static inline WDataOutP VL_CONCAT_WQQ(int obits, int lbits, int rbits, WDataOutP owp, QData ld, - QData rd) VL_MT_SAFE { - VL_SET_WQ(owp, rd); - VL_MEMSET_ZERO_W(owp + VL_WQ_WORDS_E, VL_WORDS_I(obits) - VL_WQ_WORDS_E); - _vl_insert_WQ(owp, ld, rbits + lbits - 1, rbits); - return owp; -} -static inline WDataOutP VL_CONCAT_WWQ(int obits, int lbits, int rbits, WDataOutP owp, - WDataInP const lwp, QData rd) VL_MT_SAFE { - VL_SET_WQ(owp, rd); - VL_MEMSET_ZERO_W(owp + VL_WQ_WORDS_E, VL_WORDS_I(obits) - VL_WQ_WORDS_E); - _vl_insert_WW(owp, lwp, rbits + lbits - 1, rbits); - return owp; -} -static inline WDataOutP VL_CONCAT_WQW(int obits, int lbits, int rbits, WDataOutP owp, QData ld, - WDataInP const rwp) VL_MT_SAFE { - const int rwords = VL_WORDS_I(rbits); - VL_MEMCPY_W(owp, rwp, rwords); - VL_MEMSET_ZERO_W(owp + rwords, VL_WORDS_I(obits) - rwords); - _vl_insert_WQ(owp, ld, rbits + lbits - 1, rbits); - return owp; -} -static inline WDataOutP VL_CONCAT_WWW(int obits, int lbits, int rbits, WDataOutP owp, - WDataInP const lwp, WDataInP const rwp) VL_MT_SAFE { - const int rwords = VL_WORDS_I(rbits); - VL_MEMCPY_W(owp, rwp, rwords); - VL_MEMSET_ZERO_W(owp + rwords, VL_WORDS_I(obits) - rwords); - _vl_insert_WW(owp, lwp, rbits + lbits - 1, rbits); - return owp; +// clang-format off +#define VL_CONCAT_WWI_GEN(outputSuffix, lhsSuffix) \ +static inline WDataOutP VL_CONCAT_WWI_##outputSuffix##lhsSuffix##T( \ + int obits, int lbits, int rbits, WDataOutP owp, WDataInP const lwp, IData rd) \ + VL_MT_SAFE { \ + *VL_GET_ELEM(outputSuffix, owp, 0) = rd; \ + VL_ZERO_OFFSET_W_##outputSuffix(obits - VL_EDATASIZE, VL_GET_ELEM(outputSuffix, owp, 1)); \ + _vl_insert_WW_##outputSuffix##lhsSuffix(owp, lwp, rbits + lbits - 1, rbits); \ + return owp; \ + } +// clang-format on +VL_GEN_HELPER_TWO_ARG(VL_CONCAT_WWI_GEN) +#undef VL_CONCAT_WWI_GEN + +// clang-format off +#define VL_CONCAT_WIW_GEN(outputSuffix, rhsSuffix) \ +static inline WDataOutP VL_CONCAT_WIW##outputSuffix##T##rhsSuffix( \ + int obits, int lbits, int rbits, WDataOutP owp, IData ld, WDataInP const rwp) \ + VL_MT_SAFE { \ + const int rwords = VL_WORDS_I(rbits); \ + VL_ASSIGN_W_##outputSuffix##rhsSuffix(rbits, owp, rwp); \ + VL_ZERO_OFFSET_W_##outputSuffix(obits - rbits, VL_GET_ELEM(outputSuffix, owp, rwords)); \ + _vl_insert_WI_##outputSuffix(owp, ld, rbits + lbits - 1, rbits); \ + return owp; \ + } +// clang-format on +VL_GEN_HELPER_TWO_ARG(VL_CONCAT_WIW_GEN) +#undef VL_CONCAT_WIW_GEN + +// clang-format off +#define VL_CONCAT_WIQ_GEN(outputSuffix) \ +static inline WDataOutP VL_CONCAT_WIQ_##outputSuffix##TT( \ + int obits, int lbits, int rbits, WDataOutP owp, IData ld, QData rd) VL_MT_SAFE { \ + VL_SET_WQ_##outputSuffix(owp, rd); \ + VL_ZERO_OFFSET_W_##outputSuffix(obits - VL_QUADSIZE, \ + VL_GET_ELEM(outputSuffix, owp, VL_WQ_WORDS_E)); \ + _vl_insert_WI_##outputSuffix(owp, ld, rbits + lbits - 1, rbits); \ + return owp; \ + } +// clang-format on +VL_GEN_HELPER_ONE_ARG(VL_CONCAT_WIQ_GEN) +#undef VL_CONCAT_WIQ_GEN + +// clang-format off +#define VL_CONCAT_WQI_GEN(outputSuffix) \ +static inline WDataOutP VL_CONCAT_WQI_##outputSuffix##TT( \ + int obits, int lbits, int rbits, WDataOutP owp, QData ld, IData rd) VL_MT_SAFE { \ + *VL_GET_ELEM(outputSuffix, owp, 0) = rd; \ + VL_ZERO_OFFSET_W_##outputSuffix(obits - VL_EDATASIZE, VL_GET_ELEM(outputSuffix, owp, 1)); \ + _vl_insert_WQ_##outputSuffix(owp, ld, rbits + lbits - 1, rbits); \ + return owp; \ + } +// clang-format on +VL_GEN_HELPER_ONE_ARG(VL_CONCAT_WQI_GEN) +#undef VL_CONCAT_WQI_GEN + +// clang-format off +#define VL_CONCAT_WQQ_GEN(outputSuffix) \ +static inline WDataOutP VL_CONCAT_WQQ_##outputSuffix##TT( \ + int obits, int lbits, int rbits, WDataOutP owp, QData ld, QData rd) VL_MT_SAFE { \ + VL_SET_WQ_##outputSuffix(owp, rd); \ + VL_ZERO_OFFSET_W_##outputSuffix(obits - VL_QUADSIZE, \ + VL_GET_ELEM(outputSuffix, owp, VL_WQ_WORDS_E)); \ + _vl_insert_WQ_##outputSuffix(owp, ld, rbits + lbits - 1, rbits); \ + return owp; \ + } +// clang-format on +VL_GEN_HELPER_ONE_ARG(VL_CONCAT_WQQ_GEN) +#undef VL_CONCAT_WQQ_GEN + +// clang-format off +#define VL_CONCAT_WWQ_GEN(outputSuffix, lhsSuffix) \ +static inline WDataOutP VL_CONCAT_WWQ_##outputSuffix##lhsSuffix##T( \ + int obits, int lbits, int rbits, WDataOutP owp, WDataInP const lwp, QData rd) \ + VL_MT_SAFE { \ + VL_SET_WQ_##outputSuffix(owp, rd); \ + VL_ZERO_OFFSET_W_##outputSuffix(obits - VL_QUADSIZE, \ + VL_GET_ELEM(outputSuffix, owp, VL_WQ_WORDS_E)); \ + _vl_insert_WW_##outputSuffix##lhsSuffix(owp, lwp, rbits + lbits - 1, rbits); \ + return owp; \ + } +// clang-format on +VL_GEN_HELPER_TWO_ARG(VL_CONCAT_WWQ_GEN) +#undef VL_CONCAT_WWQ_GEN + +// clang-format off +#define VL_CONCAT_WQW_GEN(outputSuffix, rhsSuffix) \ +static inline WDataOutP VL_CONCAT_WQW_##outputSuffix##T##rhsSuffix(int obits, int lbits, int rbits, WDataOutP owp, QData ld, \ + WDataInP const rwp) VL_MT_SAFE { \ + const int rwords = VL_WORDS_I(rbits); \ + VL_ASSIGN_W_##outputSuffix##rhsSuffix(rbits, owp, rwp); \ + VL_ZERO_OFFSET_W_##outputSuffix(obits - rbits, VL_GET_ELEM(outputSuffix, owp, rwords)); \ + _vl_insert_WQ_##outputSuffix(owp, ld, rbits + lbits - 1, rbits); \ + return owp; \ } +// clang-format on +VL_GEN_HELPER_TWO_ARG(VL_CONCAT_WQW_GEN) +#undef VL_CONCAT_WQW_GEN + +// clang-format off +#define VL_CONCAT_WWW_GEN(outputSuffix, lhsSuffix, rhsSuffix) \ +static inline WDataOutP VL_CONCAT_WWW_##outputSuffix##lhsSuffix##rhsSuffix( \ + int obits, int lbits, int rbits, WDataOutP owp, WDataInP const lwp, WDataInP const rwp) \ + VL_MT_SAFE { \ + const int rwords = VL_WORDS_I(rbits); \ + VL_ASSIGN_W_##outputSuffix##rhsSuffix(rbits, owp, rwp); \ + VL_ZERO_OFFSET_W_##outputSuffix(obits - rbits, VL_GET_ELEM(outputSuffix, owp, rwords)); \ + _vl_insert_WW_##outputSuffix##lhsSuffix(owp, lwp, rbits + lbits - 1, rbits); \ + return owp; \ + } +// clang-format on +VL_GEN_HELPER_THREE_ARG(VL_CONCAT_WWW_GEN) +#undef VL_CONCAT_WWW_GEN //=================================================================== // Shifts @@ -2526,148 +3472,266 @@ static inline void _vl_shiftl_inplace_w(int obits, WDataOutP iowp, // expression. Thus consider this when optimizing. (And perhaps have 2 funcs?) // If RHS (rd/rwp) is larger than the output, zeros (or all ones for >>>) must be returned // (This corresponds to AstShift*Ovr Ast nodes) -static inline IData VL_SHIFTL_III(int /*obits*/, int, int, IData lhs, IData rhs) VL_MT_SAFE { +static inline IData VL_SHIFTL_III_TTT(int /*obits*/, int, int, IData lhs, IData rhs) VL_MT_SAFE { if (VL_UNLIKELY(rhs >= VL_IDATASIZE)) return 0; return lhs << rhs; // Small is common so not clean return } -static inline IData VL_SHIFTL_IIQ(int obits, int, int, IData lhs, QData rhs) VL_MT_SAFE { +static inline IData VL_SHIFTL_IIQ_TTT(int obits, int, int, IData lhs, QData rhs) VL_MT_SAFE { if (VL_UNLIKELY(rhs >= VL_IDATASIZE)) return 0; return VL_CLEAN_II(obits, obits, lhs << rhs); } -static inline QData VL_SHIFTL_QQI(int /*obits*/, int, int, QData lhs, IData rhs) VL_MT_SAFE { +static inline QData VL_SHIFTL_QQI_TTT(int /*obits*/, int, int, QData lhs, IData rhs) VL_MT_SAFE { if (VL_UNLIKELY(rhs >= VL_QUADSIZE)) return 0; return lhs << rhs; // Small is common so not clean return } -static inline QData VL_SHIFTL_QQQ(int obits, int, int, QData lhs, QData rhs) VL_MT_SAFE { +static inline QData VL_SHIFTL_QQQ_TTT(int obits, int, int, QData lhs, QData rhs) VL_MT_SAFE { if (VL_UNLIKELY(rhs >= VL_QUADSIZE)) return 0; return VL_CLEAN_QQ(obits, obits, lhs << rhs); } -static inline WDataOutP VL_SHIFTL_WWI(int obits, int, int, WDataOutP owp, WDataInP const lwp, - IData rd) VL_MT_SAFE { - const int word_shift = VL_BITWORD_E(rd); - const int bit_shift = VL_BITBIT_E(rd); - if (rd >= static_cast(obits)) { // rd may be huge with MSB set - for (int i = 0; i < VL_WORDS_I(obits); ++i) owp[i] = 0; - } else if (bit_shift == 0) { // Aligned word shift (<<0,<<32,<<64 etc) - for (int i = 0; i < word_shift; ++i) owp[i] = 0; - for (int i = word_shift; i < VL_WORDS_I(obits); ++i) owp[i] = lwp[i - word_shift]; - } else { - for (int i = 0; i < VL_WORDS_I(obits); ++i) owp[i] = 0; - _vl_insert_WW(owp, lwp, obits - 1, rd); + +// clang-format off +#define VL_SHIFTL_WWI_GEN(outputSuffix, lhsSuffix) \ +static inline WDataOutP VL_SHIFTL_WWI_##outputSuffix##lhsSuffix##T( \ + int obits, int, int, WDataOutP owp, WDataInP lwp, IData rd) VL_MT_SAFE { \ + const WDataOutP resultp = owp; \ + owp += VL_GET_TYPE_OFFSET(outputSuffix); \ + const int word_shift = VL_BITWORD_E(rd); \ + const int bit_shift = VL_BITBIT_E(rd); \ + if (rd >= static_cast(obits)) { /* rd may be huge with MSB set */ \ + for (int i = 0; i < VL_WORDS_I(obits); ++i) { \ + *owp = 0; \ + owp += VL_GET_TYPE_JUMP(outputSuffix); \ + } \ + } else if (bit_shift == 0) { /* Aligned word shift (<<0,<<32,<<64 etc) */ \ + for (int i = 0; i < word_shift; ++i) { \ + *owp = 0; \ + owp += VL_GET_TYPE_JUMP(outputSuffix); \ + } \ + lwp += VL_GET_TYPE_OFFSET(lhsSuffix); \ + for (int i = word_shift; i < VL_WORDS_I(obits); ++i) { \ + *owp = *lwp; \ + owp += VL_GET_TYPE_JUMP(outputSuffix); \ + lwp += VL_GET_TYPE_JUMP(lhsSuffix); \ + } \ + } else { \ + for (int i = 0; i < VL_WORDS_I(obits); ++i) { \ + *owp = 0; \ + owp += VL_GET_TYPE_JUMP(outputSuffix); \ + } \ + _vl_insert_WW_##outputSuffix##lhsSuffix(resultp, lwp, obits - 1, rd); \ + } \ + return resultp; \ } - return owp; -} -static inline WDataOutP VL_SHIFTL_WWW(int obits, int lbits, int rbits, WDataOutP owp, - WDataInP const lwp, WDataInP const rwp) VL_MT_SAFE { - for (int i = 1; i < VL_WORDS_I(rbits); ++i) { - if (VL_UNLIKELY(rwp[i])) { // Huge shift 1>>32 or more - return VL_ZERO_W(obits, owp); - } +// clang-format on +VL_GEN_HELPER_TWO_ARG(VL_SHIFTL_WWI_GEN) +#undef VL_SHIFTL_WWI_GEN + +// clang-format off +#define VL_SHIFTL_WWW_GEN(outputSuffix, lhsSuffix, rhsSuffix) \ +static inline WDataOutP VL_SHIFTL_WWW_##outputSuffix##lhsSuffix##rhsSuffix(int obits, int lbits, int rbits, WDataOutP owp, \ + WDataInP const lwp, WDataInP rwp) VL_MT_SAFE { \ + rwp += VL_GET_TYPE_OFFSET(rhsSuffix); \ + const EData rwp0 = *rwp; \ + rwp += VL_GET_TYPE_JUMP(rhsSuffix); \ + for (int i = 1; i < VL_WORDS_I(rbits); ++i) { \ + if (VL_UNLIKELY(*rwp)) { /* Huge shift 1>>32 or more */ \ + return VL_ZERO_W_##outputSuffix(obits, owp); \ + } \ + rwp += VL_GET_TYPE_JUMP(rhsSuffix); \ + } \ + return VL_SHIFTL_WWI_##outputSuffix##lhsSuffix##T(obits, lbits, 32, owp, lwp, rwp0); \ } - return VL_SHIFTL_WWI(obits, lbits, 32, owp, lwp, rwp[0]); -} -static inline WDataOutP VL_SHIFTL_WWQ(int obits, int lbits, int rbits, WDataOutP owp, - WDataInP const lwp, QData rd) VL_MT_SAFE { - VlWide rwp; - VL_SET_WQ(rwp, rd); - return VL_SHIFTL_WWW(obits, lbits, rbits, owp, lwp, rwp); -} -static inline IData VL_SHIFTL_IIW(int obits, int, int rbits, IData lhs, - WDataInP const rwp) VL_MT_SAFE { - for (int i = 1; i < VL_WORDS_I(rbits); ++i) { - if (VL_UNLIKELY(rwp[i])) { // Huge shift 1>>32 or more - return 0; - } +// clang-format on +VL_GEN_HELPER_THREE_ARG(VL_SHIFTL_WWW_GEN) +#undef VL_SHIFTL_WWW_GEN + +// clang-format off +#define VL_SHIFTL_WWQ_GEN(outputSuffix, lhsSuffix) \ +static inline WDataOutP VL_SHIFTL_WWQ_##outputSuffix##lhsSuffix##T(int obits, int lbits, int rbits, WDataOutP owp, \ + WDataInP const lwp, QData rd) VL_MT_SAFE { \ + if (VL_UNLIKELY(rd >> VL_IDATASIZE)) return VL_ZERO_W_##outputSuffix(obits, owp); \ + return VL_SHIFTL_WWI_##outputSuffix##lhsSuffix##T(obits, lbits, 32, owp, lwp, static_cast(rd)); \ } - return VL_SHIFTL_III(obits, obits, 32, lhs, rwp[0]); -} -static inline QData VL_SHIFTL_QQW(int obits, int, int rbits, QData lhs, - WDataInP const rwp) VL_MT_SAFE { - for (int i = 1; i < VL_WORDS_I(rbits); ++i) { - if (VL_UNLIKELY(rwp[i])) { // Huge shift 1>>32 or more - return 0; - } +// clang-format on +VL_GEN_HELPER_TWO_ARG(VL_SHIFTL_WWQ_GEN) +#undef VL_SHIFTL_WWQ_GEN + +// clang-format off +#define VL_SHIFTL_IIW_GEN(rhsSuffix) \ +static inline IData VL_SHIFTL_IIW_TT##rhsSuffix(int obits, int, int rbits, IData lhs, WDataInP rwp) \ + VL_MT_SAFE { \ + rwp += VL_GET_TYPE_OFFSET(rhsSuffix); \ + const EData rwp0 = *rwp; \ + rwp += VL_GET_TYPE_JUMP(rhsSuffix); \ + for (int i = 1; i < VL_WORDS_I(rbits); ++i) { \ + if (VL_UNLIKELY(*rwp)) { /* Huge shift 1>>32 or more */ \ + return 0; \ + } \ + rwp += VL_GET_TYPE_JUMP(rhsSuffix); \ + } \ + return VL_SHIFTL_III_TTT(obits, obits, 32, lhs, rwp0); \ } - // Above checks rwp[1]==0 so not needed in below shift - return VL_SHIFTL_QQI(obits, obits, 32, lhs, rwp[0]); -} +// clang-format on +VL_GEN_HELPER_ONE_ARG(VL_SHIFTL_IIW_GEN) +#undef VL_SHIFTL_IIW_GEN + +// clang-format off +#define VL_SHIFTL_QQW_GEN(rhsSuffix) \ +static inline QData VL_SHIFTL_QQW_TT##rhsSuffix(int obits, int, int rbits, QData lhs, WDataInP rwp) \ + VL_MT_SAFE { \ + rwp += VL_GET_TYPE_OFFSET(rhsSuffix); \ + const EData rwp0 = *rwp; \ + rwp += VL_GET_TYPE_JUMP(rhsSuffix); \ + for (int i = 1; i < VL_WORDS_I(rbits); ++i) { \ + if (VL_UNLIKELY(*rwp)) { /* Huge shift 1>>32 or more */ \ + return 0; \ + } \ + rwp += VL_GET_TYPE_JUMP(rhsSuffix); \ + } \ + /* Above checks rwp[1]==0 so not needed in below shift */ \ + return VL_SHIFTL_QQI_TTT(obits, obits, 32, lhs, rwp0); \ + } +// clang-format on +VL_GEN_HELPER_ONE_ARG(VL_SHIFTL_QQW_GEN) +#undef VL_SHIFTL_QQW_GEN // EMIT_RULE: VL_SHIFTR: oclean=lclean; rclean==clean; // Important: Unlike most other funcs, the shift might well be a computed // expression. Thus consider this when optimizing. (And perhaps have 2 funcs?) -static inline IData VL_SHIFTR_III(int /*obits*/, int, int, IData lhs, IData rhs) VL_PURE { +static inline IData VL_SHIFTR_III_TTT(int /*obits*/, int, int, IData lhs, IData rhs) VL_PURE { if (VL_UNLIKELY(rhs >= VL_IDATASIZE)) return 0; return lhs >> rhs; } -static inline IData VL_SHIFTR_IIQ(int /*obits*/, int, int, IData lhs, QData rhs) VL_PURE { +static inline IData VL_SHIFTR_IIQ_TTT(int /*obits*/, int, int, IData lhs, QData rhs) VL_PURE { if (VL_UNLIKELY(rhs >= VL_IDATASIZE)) return 0; return lhs >> rhs; } -static inline QData VL_SHIFTR_QQI(int /*obits*/, int, int, QData lhs, IData rhs) VL_PURE { +static inline QData VL_SHIFTR_QQI_TTT(int /*obits*/, int, int, QData lhs, IData rhs) VL_PURE { if (VL_UNLIKELY(rhs >= VL_QUADSIZE)) return 0; return lhs >> rhs; } -static inline QData VL_SHIFTR_QQQ(int /*obits*/, int, int, QData lhs, QData rhs) VL_PURE { +static inline QData VL_SHIFTR_QQQ_TTT(int /*obits*/, int, int, QData lhs, QData rhs) VL_PURE { if (VL_UNLIKELY(rhs >= VL_QUADSIZE)) return 0; return lhs >> rhs; } -static inline WDataOutP VL_SHIFTR_WWI(int obits, int, int, WDataOutP owp, WDataInP const lwp, - IData rd) VL_MT_SAFE { - const int word_shift = VL_BITWORD_E(rd); // Maybe 0 - const int bit_shift = VL_BITBIT_E(rd); - if (rd >= static_cast(obits)) { // rd may be huge with MSB set - for (int i = 0; i < VL_WORDS_I(obits); ++i) owp[i] = 0; - } else if (bit_shift == 0) { // Aligned word shift (>>0,>>32,>>64 etc) - const int copy_words = (VL_WORDS_I(obits) - word_shift); - for (int i = 0; i < copy_words; ++i) owp[i] = lwp[i + word_shift]; - for (int i = copy_words; i < VL_WORDS_I(obits); ++i) owp[i] = 0; - } else { - const int loffset = rd & VL_SIZEBITS_E; - const int nbitsonright = VL_EDATASIZE - loffset; // bits that end up in lword (know - // loffset!=0) Middle words - const int words = VL_WORDS_I(obits - rd); - for (int i = 0; i < words; ++i) { - owp[i] = lwp[i + word_shift] >> loffset; - const int upperword = i + word_shift + 1; - if (upperword < VL_WORDS_I(obits)) owp[i] |= lwp[upperword] << nbitsonright; - } - for (int i = words; i < VL_WORDS_I(obits); ++i) owp[i] = 0; - } - return owp; -} -static inline WDataOutP VL_SHIFTR_WWW(int obits, int lbits, int rbits, WDataOutP owp, - WDataInP const lwp, WDataInP const rwp) VL_MT_SAFE { - for (int i = 1; i < VL_WORDS_I(rbits); ++i) { - if (VL_UNLIKELY(rwp[i])) { // Huge shift 1>>32 or more - return VL_ZERO_W(obits, owp); - } - } - return VL_SHIFTR_WWI(obits, lbits, 32, owp, lwp, rwp[0]); -} -static inline WDataOutP VL_SHIFTR_WWQ(int obits, int lbits, int rbits, WDataOutP owp, - WDataInP const lwp, QData rd) VL_MT_SAFE { - VlWide rwp; - VL_SET_WQ(rwp, rd); - return VL_SHIFTR_WWW(obits, lbits, rbits, owp, lwp, rwp); -} -static inline IData VL_SHIFTR_IIW(int obits, int, int rbits, IData lhs, - WDataInP const rwp) VL_PURE { - for (int i = 1; i < VL_WORDS_I(rbits); ++i) { - if (VL_UNLIKELY(rwp[i])) return 0; // Huge shift 1>>32 or more +// clang-format off +#define VL_SHIFTR_WWI_GEN(outputSuffix, lhsSuffix) \ +static inline WDataOutP VL_SHIFTR_WWI_##outputSuffix##lhsSuffix##T( \ + int obits, int, int, WDataOutP owp, WDataInP lwp, IData rd) VL_MT_SAFE { \ + const WDataOutP resultp = owp; \ + owp += VL_GET_TYPE_OFFSET(outputSuffix); \ + const int word_shift = VL_BITWORD_E(rd); /* Maybe 0 */ \ + const int bit_shift = VL_BITBIT_E(rd); \ + if (rd >= static_cast(obits)) { /* rd may be huge with MSB set */ \ + for (int i = 0; i < VL_WORDS_I(obits); ++i) { \ + *owp = 0; \ + owp += VL_GET_TYPE_JUMP(outputSuffix); \ + } \ + } else if (bit_shift == 0) { /* Aligned word shift (>>0,>>32,>>64 etc) */ \ + const int copy_words = (VL_WORDS_I(obits) - word_shift); \ + lwp += VL_GET_TYPE_OFFSET(lhsSuffix) + (word_shift * VL_GET_TYPE_JUMP(lhsSuffix)); \ + for (int i = 0; i < copy_words; ++i) { \ + *owp = *lwp; \ + owp += VL_GET_TYPE_JUMP(outputSuffix); \ + lwp += VL_GET_TYPE_JUMP(lhsSuffix); \ + } \ + for (int i = copy_words; i < VL_WORDS_I(obits); ++i) { \ + *owp = 0; \ + owp += VL_GET_TYPE_JUMP(outputSuffix); \ + } \ + } else { \ + const int loffset = rd & VL_SIZEBITS_E; \ + /* bits that end up in lword (know loffset!=0) Middle words */ \ + const int nbitsonright = VL_EDATASIZE - loffset; \ + const int words = VL_WORDS_I(obits - rd); \ + lwp += VL_GET_TYPE_OFFSET(lhsSuffix) + (word_shift * VL_GET_TYPE_JUMP(lhsSuffix)); \ + for (int i = 0; i < words; ++i) { \ + *owp = *lwp >> loffset; \ + const int upperword = i + word_shift + 1; \ + lwp += VL_GET_TYPE_JUMP(lhsSuffix); \ + if (upperword < VL_WORDS_I(obits)) *owp |= *lwp << nbitsonright; \ + owp += VL_GET_TYPE_JUMP(outputSuffix); \ + } \ + for (int i = words; i < VL_WORDS_I(obits); ++i) { \ + *owp = 0; \ + owp += VL_GET_TYPE_JUMP(outputSuffix); \ + } \ + } \ + return resultp; \ } - return VL_SHIFTR_III(obits, obits, 32, lhs, rwp[0]); -} -static inline QData VL_SHIFTR_QQW(int obits, int, int rbits, QData lhs, - WDataInP const rwp) VL_PURE { - for (int i = 1; i < VL_WORDS_I(rbits); ++i) { - if (VL_UNLIKELY(rwp[i])) return 0; // Huge shift 1>>32 or more +// clang-format on +VL_GEN_HELPER_TWO_ARG(VL_SHIFTR_WWI_GEN) +#undef VL_SHIFTR_WWI_GEN + +// clang-format off +#define VL_SHIFTR_WWW_GEN(outputSuffix, lhsSuffix, rhsSuffix) \ +static inline WDataOutP VL_SHIFTR_WWW_##outputSuffix##lhsSuffix##rhsSuffix( \ + int obits, int lbits, int rbits, WDataOutP owp, WDataInP const lwp, WDataInP rwp) \ + VL_MT_SAFE { \ + rwp += VL_GET_TYPE_OFFSET(rhsSuffix); \ + const EData rwp0 = *rwp; \ + rwp += VL_GET_TYPE_JUMP(rhsSuffix); \ + for (int i = 1; i < VL_WORDS_I(rbits); ++i) { \ + if (VL_UNLIKELY(*rwp)) { /* Huge shift 1>>32 or more */ \ + return VL_ZERO_W_##outputSuffix(obits, owp); \ + } \ + rwp += VL_GET_TYPE_JUMP(rhsSuffix); \ + } \ + return VL_SHIFTR_WWI_##outputSuffix##lhsSuffix##T(obits, lbits, 32, owp, lwp, rwp0); \ } - return VL_SHIFTR_QQI(obits, obits, 32, lhs, rwp[0]); -} +// clang-format on +VL_GEN_HELPER_THREE_ARG(VL_SHIFTR_WWW_GEN) +#undef VL_SHIFTR_WWW_GEN + +// clang-format off +#define VL_SHIFTR_WWQ_GEN(outputSuffix, lhsSuffix) \ +static inline WDataOutP VL_SHIFTR_WWQ_##outputSuffix##lhsSuffix##T( \ + int obits, int lbits, int rbits, WDataOutP owp, WDataInP const lwp, QData rd) \ + VL_MT_SAFE { \ + if (VL_UNLIKELY(rd >> VL_IDATASIZE)) return VL_ZERO_W_##outputSuffix(obits, owp); \ + return VL_SHIFTR_WWI_##outputSuffix##lhsSuffix##T(obits, lbits, rbits, owp, lwp, static_cast(rd)); \ + } +// clang-format on +VL_GEN_HELPER_TWO_ARG(VL_SHIFTR_WWQ_GEN) +#undef VL_SHIFTR_WWQ_GEN + +// clang-format off +#define VL_SHIFTR_IIW_GEN(rhsSuffix) \ +static inline IData VL_SHIFTR_IIW_TT##rhsSuffix(int obits, int, int rbits, IData lhs, \ + WDataInP rwp) VL_PURE { \ + rwp = rwp + VL_GET_TYPE_OFFSET(rhsSuffix); \ + const EData rwp0 = *rwp; \ + rwp = rwp + VL_GET_TYPE_JUMP(rhsSuffix); \ + for (int i = 1; i < VL_WORDS_I(rbits); ++i) { \ + if (VL_UNLIKELY(*rwp)) return 0; /* Huge shift 1>>32 or more */ \ + rwp = rwp + VL_GET_TYPE_JUMP(rhsSuffix); \ + } \ + return VL_SHIFTR_III_TTT(obits, obits, 32, lhs, rwp0); \ + } +// clang-format on +VL_GEN_HELPER_ONE_ARG(VL_SHIFTR_IIW_GEN) +#undef VL_SHIFTR_IIW_GEN + +// clang-format off +#define VL_SHIFTR_QQW_GEN(rhsSuffix) \ +static inline QData VL_SHIFTR_QQW_TT##rhsSuffix(int obits, int, int rbits, QData lhs, \ + WDataInP rwp) VL_PURE { \ + rwp = rwp + VL_GET_TYPE_OFFSET(rhsSuffix); \ + const EData rwp0 = *rwp; \ + rwp = rwp + VL_GET_TYPE_JUMP(rhsSuffix); \ + for (int i = 1; i < VL_WORDS_I(rbits); ++i) { \ + if (VL_UNLIKELY(*rwp)) return 0; /* Huge shift 1>>32 or more */ \ + rwp = rwp + VL_GET_TYPE_JUMP(rhsSuffix); \ + } \ + return VL_SHIFTR_QQI_TTT(obits, obits, 32, lhs, rwp0); \ + } +// clang-format on +VL_GEN_HELPER_ONE_ARG(VL_SHIFTR_QQW_GEN) +#undef VL_SHIFTR_QQW_GEN // EMIT_RULE: VL_SHIFTRS: oclean=false; lclean=clean, rclean==clean; -static inline IData VL_SHIFTRS_III(int obits, int lbits, int, IData lhs, IData rhs) VL_PURE { +static inline IData VL_SHIFTRS_III_TTT(int obits, int lbits, int, IData lhs, IData rhs) VL_PURE { // Note the C standard does not specify the >> operator as a arithmetic shift! // IEEE says signed if output signed, but bit position from lbits; // must use lbits for sign; lbits might != obits, @@ -2677,128 +3741,200 @@ static inline IData VL_SHIFTRS_III(int obits, int lbits, int, IData lhs, IData r const IData signext = ~(VL_MASK_I(lbits) >> rhs); // One with bits where we've shifted "past" return (lhs >> rhs) | (sign & VL_CLEAN_II(obits, obits, signext)); } -static inline QData VL_SHIFTRS_QQI(int obits, int lbits, int, QData lhs, IData rhs) VL_PURE { +static inline QData VL_SHIFTRS_QQI_TTT(int obits, int lbits, int, QData lhs, IData rhs) VL_PURE { const QData sign = -(lhs >> (lbits - 1)); if (VL_UNLIKELY(rhs >= VL_QUADSIZE)) return sign & VL_MASK_Q(obits); const QData signext = ~(VL_MASK_Q(lbits) >> rhs); return (lhs >> rhs) | (sign & VL_CLEAN_QQ(obits, obits, signext)); } -static inline IData VL_SHIFTRS_IQI(int obits, int lbits, int rbits, QData lhs, IData rhs) VL_PURE { - return static_cast(VL_SHIFTRS_QQI(obits, lbits, rbits, lhs, rhs)); +static inline IData VL_SHIFTRS_IQI_TTT(int obits, int lbits, int rbits, QData lhs, + IData rhs) VL_PURE { + return static_cast(VL_SHIFTRS_QQI_TTT(obits, lbits, rbits, lhs, rhs)); } -static inline WDataOutP VL_SHIFTRS_WWI(int obits, int lbits, int, WDataOutP owp, - WDataInP const lwp, IData rd) VL_MT_SAFE { - const int word_shift = VL_BITWORD_E(rd); - const int bit_shift = VL_BITBIT_E(rd); - const int lmsw = VL_WORDS_I(obits) - 1; - const EData sign = VL_SIGNONES_E(lbits, lwp[lmsw]); - if (rd >= static_cast(obits)) { // Shifting past end, sign in all of lbits - for (int i = 0; i <= lmsw; ++i) owp[i] = sign; - owp[lmsw] &= VL_MASK_E(lbits); - } else if (bit_shift == 0) { // Aligned word shift (>>0,>>32,>>64 etc) - const int copy_words = (VL_WORDS_I(obits) - word_shift); - for (int i = 0; i < copy_words; ++i) owp[i] = lwp[i + word_shift]; - if (copy_words >= 0) owp[copy_words - 1] |= ~VL_MASK_E(obits) & sign; - for (int i = copy_words; i < VL_WORDS_I(obits); ++i) owp[i] = sign; - owp[lmsw] &= VL_MASK_E(lbits); - } else { - const int loffset = rd & VL_SIZEBITS_E; - const int nbitsonright - = VL_EDATASIZE - loffset; // bits that end up in lword (know loffset!=0) - // Middle words - const int words = VL_WORDS_I(obits - rd); - for (int i = 0; i < words; ++i) { - owp[i] = lwp[i + word_shift] >> loffset; - const int upperword = i + word_shift + 1; - if (upperword < VL_WORDS_I(obits)) owp[i] |= lwp[upperword] << nbitsonright; - } - if (words) owp[words - 1] |= sign & ~VL_MASK_E(obits - loffset); - for (int i = words; i < VL_WORDS_I(obits); ++i) owp[i] = sign; - owp[lmsw] &= VL_MASK_E(lbits); + +// clang-format off +#define VL_SHIFTRS_WWI_GEN(outputSuffix, lhsSuffix) \ +static inline WDataOutP VL_SHIFTRS_WWI_##outputSuffix##lhsSuffix##T( \ + int obits, int lbits, int, WDataOutP owp, WDataInP lwp, IData rd) VL_MT_SAFE { \ + const int word_shift = VL_BITWORD_E(rd); \ + const int bit_shift = VL_BITBIT_E(rd); \ + const int lmsw = VL_WORDS_I(obits) - 1; \ + const EData sign = VL_SIGNONES_E(lbits, *VL_GET_ELEM(lhsSuffix, lwp, lmsw)); \ + const WDataOutP resultp = owp; \ + owp += VL_GET_TYPE_OFFSET(outputSuffix); \ + if (rd >= static_cast(obits)) { /* Shifting past end, sign in all of lbits */ \ + for (int i = 0; i < lmsw; ++i) { \ + *owp = sign; \ + owp += VL_GET_TYPE_JUMP(outputSuffix); \ + } \ + *owp = sign & VL_MASK_E(lbits); \ + } else if (bit_shift == 0) { /* Aligned word shift (>>0,>>32,>>64 etc) */ \ + const int copy_words = (VL_WORDS_I(obits) - word_shift); \ + lwp += VL_GET_TYPE_OFFSET(lhsSuffix) + (word_shift * VL_GET_TYPE_JUMP(lhsSuffix)); \ + for (int i = 0; i < copy_words; ++i) { \ + *owp = *lwp; \ + owp += VL_GET_TYPE_JUMP(outputSuffix); \ + lwp += VL_GET_TYPE_JUMP(lhsSuffix); \ + } \ + if (copy_words >= 0) *(owp - VL_GET_TYPE_JUMP(outputSuffix)) |= ~VL_MASK_E(obits) & sign; \ + for (int i = copy_words; i < VL_WORDS_I(obits); ++i) { \ + *owp = sign; \ + owp += VL_GET_TYPE_JUMP(outputSuffix); \ + } \ + *(owp - VL_GET_TYPE_JUMP(outputSuffix)) &= VL_MASK_E(lbits); \ + } else { \ + const int loffset = rd & VL_SIZEBITS_E; \ + const int nbitsonright \ + = VL_EDATASIZE - loffset; /* bits that end up in lword (know loffset!=0) */ \ + /* Middle words */ \ + const int words = VL_WORDS_I(obits - rd); \ + lwp += VL_GET_TYPE_OFFSET(lhsSuffix) + (word_shift * VL_GET_TYPE_JUMP(lhsSuffix)); \ + for (int i = 0; i < words; ++i) { \ + *owp = *lwp >> loffset; \ + const int upperword = i + word_shift + 1; \ + lwp += VL_GET_TYPE_JUMP(lhsSuffix); \ + if (upperword < VL_WORDS_I(obits)) *owp |= *lwp << nbitsonright; \ + owp += VL_GET_TYPE_JUMP(outputSuffix); \ + } \ + if (words) *(owp - VL_GET_TYPE_JUMP(outputSuffix)) |= sign & ~VL_MASK_E(obits - loffset); \ + for (int i = words; i < VL_WORDS_I(obits); ++i) { \ + *owp = sign; \ + owp += VL_GET_TYPE_JUMP(outputSuffix); \ + } \ + *(owp - VL_GET_TYPE_JUMP(outputSuffix)) &= VL_MASK_E(lbits); \ + } \ + return resultp; \ } - return owp; -} -static inline WDataOutP VL_SHIFTRS_WWW(int obits, int lbits, int rbits, WDataOutP owp, - WDataInP const lwp, WDataInP const rwp) VL_MT_SAFE { - EData overshift = 0; // Huge shift 1>>32 or more - for (int i = 1; i < VL_WORDS_I(rbits); ++i) overshift |= rwp[i]; - if (VL_UNLIKELY(overshift || rwp[0] >= static_cast(obits))) { - const int owords = VL_WORDS_I(obits); - if (VL_SIGN_E(lbits, lwp[owords - 1])) { - VL_MEMSET_ONES_W(owp, owords); - owp[owords - 1] &= VL_MASK_E(lbits); - } else { - VL_MEMSET_ZERO_W(owp, owords); - } - return owp; +// clang-format on +VL_GEN_HELPER_TWO_ARG(VL_SHIFTRS_WWI_GEN) +#undef VL_SHIFTRS_WWI_GEN + +// clang-format off +#define VL_SHIFTRS_WWW_GEN(outputSuffix, lhsSuffix, rhsSuffix) \ +static inline WDataOutP VL_SHIFTRS_WWW_##outputSuffix##lhsSuffix##rhsSuffix( \ + int obits, int lbits, int rbits, WDataOutP owp, WDataInP const lwp, WDataInP rwp) \ + VL_MT_SAFE { \ + rwp += VL_GET_TYPE_OFFSET(rhsSuffix); \ + const EData rwp0 = *rwp; \ + rwp += VL_GET_TYPE_JUMP(rhsSuffix); \ + EData overshift = 0; /* Huge shift 1>>32 or more */ \ + for (int i = 1; i < VL_WORDS_I(rbits); ++i) { \ + overshift |= *rwp; \ + rwp += VL_GET_TYPE_JUMP(rhsSuffix); \ + } \ + if (VL_UNLIKELY(overshift || rwp0 >= static_cast(obits))) { \ + const int owords = VL_WORDS_I(obits); \ + if (VL_SIGN_E_T(lbits, *VL_GET_ELEM(lhsSuffix, lwp, owords - 1))) { \ + VL_MEMSET_ONES_W(owp, owords); \ + *VL_GET_ELEM(outputSuffix, owp, owords - 1) &= VL_MASK_E(lbits); \ + } else { \ + VL_MEMSET_ZERO_W(owp, owords); \ + } \ + return owp; \ + } \ + return VL_SHIFTRS_WWI_##outputSuffix##lhsSuffix##T(obits, lbits, 32, owp, lwp, rwp0); \ } - return VL_SHIFTRS_WWI(obits, lbits, 32, owp, lwp, rwp[0]); -} -static inline WDataOutP VL_SHIFTRS_WWQ(int obits, int lbits, int rbits, WDataOutP owp, - WDataInP const lwp, QData rd) VL_MT_SAFE { +// clang-format on +VL_GEN_HELPER_THREE_ARG(VL_SHIFTRS_WWW_GEN) +#undef VL_SHIFTRS_WWW_GEN + +// clang-format off +#define VL_SHIFTRS_WWQ_GEN(outputSuffix, lhsSuffix) \ +static inline WDataOutP VL_SHIFTRS_WWQ_##outputSuffix##lhsSuffix##T( \ + int obits, int lbits, int rbits, WDataOutP owp, WDataInP const lwp, QData rd) \ + VL_MT_SAFE { \ + VlWide rwp; \ + VL_SET_WQ_T(rwp, rd); \ + return VL_SHIFTRS_WWW_##outputSuffix##lhsSuffix##T(obits, lbits, rbits, owp, lwp, rwp); \ + } +// clang-format on +VL_GEN_HELPER_TWO_ARG(VL_SHIFTRS_WWQ_GEN) +#undef VL_SHIFTRS_WWQ_GEN + +// clang-format off +#define VL_SHIFTRS_IIW_GEN(rhsSuffix) \ +static inline IData VL_SHIFTRS_IIW_TT##rhsSuffix(int obits, int lbits, int rbits, IData lhs, \ + WDataInP const rwp) VL_PURE { \ + EData overshift = 0; /* Huge shift 1>>32 or more */ \ + for (int i = 1; i < VL_WORDS_I(rbits); ++i) overshift |= rwp[i]; \ + if (VL_UNLIKELY(overshift || rwp[0] >= static_cast(obits))) { \ + const IData sign = -(lhs >> (lbits - 1)); /* ffff_ffff if negative */ \ + return VL_CLEAN_II(obits, obits, sign); \ + } \ + return VL_SHIFTRS_III_TTT(obits, lbits, 32, lhs, rwp[0]); \ + } +// clang-format on +VL_GEN_HELPER_ONE_ARG(VL_SHIFTRS_IIW_GEN) +#undef VL_SHIFTRS_IIW_GEN + +// clang-format off +#define VL_SHIFTRS_QQW_GEN(rhsSuffix) \ +static inline QData VL_SHIFTRS_QQW_TT##rhsSuffix(int obits, int lbits, int rbits, QData lhs, \ + WDataInP const rwp) VL_PURE { \ + EData overshift = 0; /* Huge shift 1>>32 or more */ \ + for (int i = 1; i < VL_WORDS_I(rbits); ++i) overshift |= rwp[i]; \ + if (VL_UNLIKELY(overshift || rwp[0] >= static_cast(obits))) { \ + const QData sign = -(lhs >> (lbits - 1)); /* ffff_ffff if negative */ \ + return VL_CLEAN_QQ(obits, obits, sign); \ + } \ + return VL_SHIFTRS_QQI_TTT(obits, lbits, 32, lhs, rwp[0]); \ + } +// clang-format on +VL_GEN_HELPER_ONE_ARG(VL_SHIFTRS_QQW_GEN) +#undef VL_SHIFTRS_QQW_GEN + +static inline IData VL_SHIFTRS_IIQ_TTT(int obits, int lbits, int rbits, IData lhs, + QData rhs) VL_PURE { VlWide rwp; - VL_SET_WQ(rwp, rd); - return VL_SHIFTRS_WWW(obits, lbits, rbits, owp, lwp, rwp); + VL_SET_WQ_T(rwp, rhs); + return VL_SHIFTRS_IIW_TTT(obits, lbits, rbits, lhs, rwp); } -static inline IData VL_SHIFTRS_IIW(int obits, int lbits, int rbits, IData lhs, - WDataInP const rwp) VL_PURE { - EData overshift = 0; // Huge shift 1>>32 or more - for (int i = 1; i < VL_WORDS_I(rbits); ++i) overshift |= rwp[i]; - if (VL_UNLIKELY(overshift || rwp[0] >= static_cast(obits))) { - const IData sign = -(lhs >> (lbits - 1)); // ffff_ffff if negative - return VL_CLEAN_II(obits, obits, sign); - } - return VL_SHIFTRS_III(obits, lbits, 32, lhs, rwp[0]); -} -static inline QData VL_SHIFTRS_QQW(int obits, int lbits, int rbits, QData lhs, - WDataInP const rwp) VL_PURE { - EData overshift = 0; // Huge shift 1>>32 or more - for (int i = 1; i < VL_WORDS_I(rbits); ++i) overshift |= rwp[i]; - if (VL_UNLIKELY(overshift || rwp[0] >= static_cast(obits))) { - const QData sign = -(lhs >> (lbits - 1)); // ffff_ffff if negative - return VL_CLEAN_QQ(obits, obits, sign); - } - return VL_SHIFTRS_QQI(obits, lbits, 32, lhs, rwp[0]); -} -static inline IData VL_SHIFTRS_IIQ(int obits, int lbits, int rbits, IData lhs, QData rhs) VL_PURE { +static inline QData VL_SHIFTRS_QQQ_TTT(int obits, int lbits, int rbits, QData lhs, + QData rhs) VL_PURE { VlWide rwp; - VL_SET_WQ(rwp, rhs); - return VL_SHIFTRS_IIW(obits, lbits, rbits, lhs, rwp); -} -static inline QData VL_SHIFTRS_QQQ(int obits, int lbits, int rbits, QData lhs, QData rhs) VL_PURE { - VlWide rwp; - VL_SET_WQ(rwp, rhs); - return VL_SHIFTRS_QQW(obits, lbits, rbits, lhs, rwp); + VL_SET_WQ_T(rwp, rhs); + return VL_SHIFTRS_QQW_TTT(obits, lbits, rbits, lhs, rwp); } //=================================================================== // Bit selection // EMIT_RULE: VL_BITSEL: oclean=dirty; rclean==clean; -#define VL_BITSEL_IIII(lbits, lhs, rhs) ((lhs) >> (rhs)) -#define VL_BITSEL_QIII(lbits, lhs, rhs) ((lhs) >> (rhs)) -#define VL_BITSEL_QQII(lbits, lhs, rhs) ((lhs) >> (rhs)) -#define VL_BITSEL_IQII(lbits, lhs, rhs) (static_cast((lhs) >> (rhs))) +#define VL_BITSEL_IIII_TTTT(lbits, lhs, rhs) ((lhs) >> (rhs)) +#define VL_BITSEL_QIII_TTTT(lbits, lhs, rhs) ((lhs) >> (rhs)) +#define VL_BITSEL_QQII_TTTT(lbits, lhs, rhs) ((lhs) >> (rhs)) +#define VL_BITSEL_IQII_TTTT(lbits, lhs, rhs) (static_cast((lhs) >> (rhs))) -static inline IData VL_BITSEL_IWII(int lbits, WDataInP const lwp, IData rd) VL_MT_SAFE { - const int word = VL_BITWORD_E(rd); - if (VL_UNLIKELY(rd > static_cast(lbits))) { - return ~0; // Spec says you can go outside the range of a array. Don't coredump if so. - // We return all 1's as that's more likely to find bugs (?) than 0's. +// clang-format off +#define VL_BITSEL_IWII_GEN(lhsSuffix) \ +static inline IData VL_BITSEL_IWII_T##lhsSuffix##TT(int lbits, WDataInP const lwp, IData rd) \ + VL_MT_SAFE { \ + const int word = VL_BITWORD_E(rd); \ + if (VL_UNLIKELY(rd >= static_cast(lbits))) { \ + VL_IF_VX(lhsSuffix, \ + VL_FATAL_MT(__FILE__, __LINE__, "", \ + "Tried to access index out of range - Verilator shall handle " \ + "index ranges at compile time");); \ + VL_IF_T(lhsSuffix, return ~0;); /* Spec says you can go outside the range of a array. \ + Don't coredump if so. */ \ + /* We return all 1's as that's more likely to find bugs (?) than 0's. */ \ + } \ + return (*VL_GET_ELEM(lhsSuffix, lwp, word) >> VL_BITBIT_E(rd)); \ } - return (lwp[word] >> VL_BITBIT_E(rd)); -} +// clang-format on +VL_GEN_HELPER_ONE_ARG(VL_BITSEL_IWII_GEN) +#undef VL_BITSEL_IWII_GEN // EMIT_RULE: VL_RANGE: oclean=lclean; out=dirty // & MUST BE CLEAN (currently constant) -#define VL_SEL_IIII(lbits, lhs, lsb, width) ((lhs) >> (lsb)) -#define VL_SEL_QQII(lbits, lhs, lsb, width) ((lhs) >> (lsb)) -#define VL_SEL_IQII(lbits, lhs, lsb, width) (static_cast((lhs) >> (lsb))) +#define VL_SEL_IIII_TTTT(lbits, lhs, lsb, width) ((lhs) >> (lsb)) +#define VL_SEL_QQII_TTTT(lbits, lhs, lsb, width) ((lhs) >> (lsb)) +#define VL_SEL_IQII_TTTT(lbits, lhs, lsb, width) (static_cast((lhs) >> (lsb))) // #define VL_SEL_IRII(lbits, lhs, lsb, width) ((lhs) >> (lsb)) template -static inline IData VL_SEL_IRII(int lbits, const VlQueue& lhs, IData lsb, - IData width) VL_MT_SAFE { +static inline IData VL_SEL_IRII_TTTT(int lbits, const VlQueue& lhs, IData lsb, + IData width) VL_MT_SAFE { IData val = 0; if (sizeof(T) == 8) { const int offset = lhs.size() * sizeof(T) / sizeof(IData) - VL_BITWORD_E(lsb) - 1; @@ -2819,8 +3955,8 @@ static inline IData VL_SEL_IRII(int lbits, const VlQueue& lhs, IData lsb, } template -static inline IData VL_SEL_IRII(int lbits, const VlQueue>& lhs, IData lsb, - IData width) VL_MT_SAFE { +static inline IData VL_SEL_IRII_TTTT(int lbits, const VlQueue>& lhs, IData lsb, + IData width) VL_MT_SAFE { IData val = 0; const int offset = lhs.size() * N_Words - VL_BITWORD_E(lsb) - 1; @@ -2832,68 +3968,107 @@ static inline IData VL_SEL_IRII(int lbits, const VlQueue>& lhs, return val; } -static inline IData VL_SEL_IWII(int lbits, WDataInP const lwp, IData lsb, IData width) VL_MT_SAFE { - const int msb = lsb + width - 1; - if (VL_UNLIKELY(msb >= lbits)) { - return ~0; // Spec says you can go outside the range of a array. Don't coredump if so. +// clang-format off +#define VL_SEL_IWII_GEN(lhsSuffix) \ +static inline IData VL_SEL_IWII_T##lhsSuffix##TT(int lbits, WDataInP const lwp, IData lsb, \ + IData width) VL_MT_SAFE { \ + const int msb = lsb + width - 1; \ + if (VL_UNLIKELY(msb >= lbits)) { \ + VL_IF_VX(lhsSuffix, \ + VL_FATAL_MT(__FILE__, __LINE__, "", \ + "Tried to access index out of range - Verilator shall handle " \ + "index ranges at compile time");); \ + VL_IF_T(lhsSuffix, return ~0;); /* Spec says you can go outside the range of a array. \ + Don't coredump if so. */ \ + } \ + const int lsbWord = VL_BITWORD_E(lsb); \ + const IData lo = *VL_GET_ELEM(lhsSuffix, lwp, lsbWord) >> VL_BITBIT_E(lsb); \ + if (VL_BITWORD_E(msb) == lsbWord) return lo; \ + /* 32 bit extraction may span two words */ \ + const int nbitsfromlow \ + = VL_EDATASIZE - VL_BITBIT_E(lsb); /* bits that come from low word */ \ + return (*VL_GET_ELEM(lhsSuffix, lwp, VL_BITWORD_E(msb)) << nbitsfromlow) | lo; \ } - if (VL_BITWORD_E(msb) == VL_BITWORD_E(static_cast(lsb))) { - return VL_BITRSHIFT_W(lwp, lsb); - } - // 32 bit extraction may span two words - const int nbitsfromlow = VL_EDATASIZE - VL_BITBIT_E(lsb); // bits that come from low word - return ((lwp[VL_BITWORD_E(msb)] << nbitsfromlow) | VL_BITRSHIFT_W(lwp, lsb)); -} +// clang-format on +VL_GEN_HELPER_ONE_ARG(VL_SEL_IWII_GEN) +#undef VL_SEL_IWII_GEN -static inline QData VL_SEL_QWII(int lbits, WDataInP const lwp, IData lsb, IData width) VL_MT_SAFE { - const int msb = lsb + width - 1; - if (VL_UNLIKELY(msb > lbits)) { - return ~0; // Spec says you can go outside the range of a array. Don't coredump if so. +// clang-format off +#define VL_SEL_QWII_GEN(lhsSuffix) \ +static inline QData VL_SEL_QWII_T##lhsSuffix##TT(int lbits, WDataInP const lwp, IData lsb, \ + IData width) VL_MT_SAFE { \ + const int msb = lsb + width - 1; \ + if (VL_UNLIKELY(msb >= lbits)) { \ + VL_IF_VX(lhsSuffix, \ + VL_FATAL_MT(__FILE__, __LINE__, "", \ + "Tried to access index out of range - Verilator shall handle " \ + "index ranges at compile time");); \ + VL_IF_T(lhsSuffix, return ~0;); /* Spec says you can go outside the range of a array. \ + Don't coredump if so. */ \ + } \ + const int lsbWord = VL_BITWORD_E(lsb); \ + const IData lo = *VL_GET_ELEM(lhsSuffix, lwp, lsbWord) >> VL_BITBIT_E(lsb); \ + if (VL_BITWORD_E(msb) == lsbWord) return lo; \ + const int nbitsfromlow = VL_EDATASIZE - VL_BITBIT_E(lsb); \ + const QData hi = *VL_GET_ELEM(lhsSuffix, lwp, VL_BITWORD_E(msb)); \ + if (VL_BITWORD_E(msb) == 1 + lsbWord) return (hi << nbitsfromlow) | lo; \ + /* 64 bit extraction may span three words */ \ + const QData mid = *VL_GET_ELEM(lhsSuffix, lwp, VL_BITWORD_E(lsb) + 1); \ + return (hi << (nbitsfromlow + VL_EDATASIZE)) | (mid << nbitsfromlow) | lo; \ } - if (VL_BITWORD_E(msb) == VL_BITWORD_E(static_cast(lsb))) { - return VL_BITRSHIFT_W(lwp, lsb); - } - if (VL_BITWORD_E(msb) == 1 + VL_BITWORD_E(static_cast(lsb))) { - const int nbitsfromlow = VL_EDATASIZE - VL_BITBIT_E(lsb); - const QData hi = (lwp[VL_BITWORD_E(msb)]); - const QData lo = VL_BITRSHIFT_W(lwp, lsb); - return (hi << nbitsfromlow) | lo; - } - // 64 bit extraction may span three words - const int nbitsfromlow = VL_EDATASIZE - VL_BITBIT_E(lsb); - const QData hi = (lwp[VL_BITWORD_E(msb)]); - const QData mid = (lwp[VL_BITWORD_E(lsb) + 1]); - const QData lo = VL_BITRSHIFT_W(lwp, lsb); - return (hi << (nbitsfromlow + VL_EDATASIZE)) | (mid << nbitsfromlow) | lo; -} +// clang-format on +VL_GEN_HELPER_ONE_ARG(VL_SEL_QWII_GEN) +#undef VL_SEL_QWII_GEN -static inline WDataOutP VL_SEL_WWII(int obits, int lbits, WDataOutP owp, WDataInP const lwp, - IData lsb, IData width) VL_MT_SAFE { - const int msb = lsb + width - 1; - const int word_shift = VL_BITWORD_E(lsb); - if (VL_UNLIKELY(msb > lbits)) { // Outside bounds, - for (int i = 0; i < VL_WORDS_I(obits) - 1; ++i) owp[i] = ~0; - owp[VL_WORDS_I(obits) - 1] = VL_MASK_E(obits); - } else if (VL_BITBIT_E(lsb) == 0) { - // Just a word extract - for (int i = 0; i < VL_WORDS_I(obits); ++i) owp[i] = lwp[i + word_shift]; - } else { - // Not a _vl_insert because the bits come from any bit number and goto bit 0 - const int loffset = lsb & VL_SIZEBITS_E; - const int nbitsfromlow = VL_EDATASIZE - loffset; // bits that end up in lword (know - // loffset!=0) Middle words - const int words = VL_WORDS_I(msb - lsb + 1); - for (int i = 0; i < words; ++i) { - owp[i] = lwp[i + word_shift] >> loffset; - const int upperword = i + word_shift + 1; - if (upperword <= static_cast(VL_BITWORD_E(msb))) { - owp[i] |= lwp[upperword] << nbitsfromlow; - } - } - for (int i = words; i < VL_WORDS_I(obits); ++i) owp[i] = 0; +// clang-format off +#define VL_SEL_WWII_GEN(outputSuffix, lhsSuffix) \ +static inline WDataOutP VL_SEL_WWII_##outputSuffix##lhsSuffix##TT( \ + int obits, int lbits, WDataOutP owp, WDataInP lwp, IData lsb, IData width) VL_MT_SAFE { \ + const int msb = lsb + width - 1; \ + const int word_shift = VL_BITWORD_E(lsb); \ + const WDataOutP resultp = owp; \ + if (VL_UNLIKELY(msb >= lbits)) { /* Outside bounds, */ \ + VL_IF_VX(lhsSuffix, \ + VL_FATAL_MT(__FILE__, __LINE__, "", \ + "Tried to access index out of range - Verilator shall handle " \ + "index ranges at compile time");); \ + VL_IF_T(lhsSuffix, VL_ALLONES_W_##outputSuffix(obits, owp);); \ + } else if (VL_BITBIT_E(lsb) == 0) { \ + /* Just a word extract */ \ + owp += VL_GET_TYPE_OFFSET(outputSuffix); \ + lwp += VL_GET_TYPE_OFFSET(lhsSuffix) + (word_shift * VL_GET_TYPE_JUMP(lhsSuffix)); \ + for (int i = 0; i < VL_WORDS_I(obits); ++i) { \ + *owp = *lwp; \ + owp += VL_GET_TYPE_JUMP(outputSuffix); \ + lwp += VL_GET_TYPE_JUMP(lhsSuffix); \ + } \ + } else { \ + /* Not a _vl_insert because the bits come from any bit number and goto bit 0 */ \ + const int loffset = lsb & VL_SIZEBITS_E; \ + const int nbitsfromlow = VL_EDATASIZE - loffset; /* bits that end up in lword (know \ + loffset!=0) Middle words */ \ + const int words = VL_WORDS_I(msb - lsb + 1); \ + owp += VL_GET_TYPE_OFFSET(outputSuffix); \ + lwp += VL_GET_TYPE_OFFSET(lhsSuffix) + (word_shift * VL_GET_TYPE_JUMP(lhsSuffix)); \ + for (int i = 0; i < words; ++i) { \ + *owp = *lwp >> loffset; \ + const int upperword = i + word_shift + 1; \ + lwp += VL_GET_TYPE_JUMP(lhsSuffix); \ + if (upperword <= static_cast(VL_BITWORD_E(msb))) { \ + *owp |= *lwp << nbitsfromlow; \ + } \ + owp += VL_GET_TYPE_JUMP(outputSuffix); \ + } \ + for (int i = words; i < VL_WORDS_I(obits); ++i) { \ + *owp = 0; \ + owp += VL_GET_TYPE_JUMP(outputSuffix); \ + } \ + } \ + return resultp; \ } - return owp; -} +// clang-format on +VL_GEN_HELPER_TWO_ARG(VL_SEL_WWII_GEN) +#undef VL_SEL_WWII_GEN template static inline VlQueue VL_CLONE_Q(const VlQueue& from, int lbits, int srcElementBits, @@ -3157,7 +4332,7 @@ static inline void VL_UNPACK_RI_W(int lbits, int rbits, VlQueue& q, WData const int bitPos = rbits - (i + 1) * lbits; const int actualBitPos = (bitPos < 0) ? 0 : bitPos; const int actualWidth = (bitPos < 0) ? (lbits + bitPos) : lbits; - q.atWrite(i) = VL_SEL_IWII(rbits, rwp, actualBitPos, actualWidth) & mask; + q.atWrite(i) = VL_SEL_IWII_TTTT(rbits, rwp, actualBitPos, actualWidth) & mask; } } @@ -3170,7 +4345,7 @@ static inline void VL_UNPACK_RI_W(int lbits, int rbits, VlQueue& q, WData const int bitPos = rbits - (i + 1) * lbits; const int actualBitPos = (bitPos < 0) ? 0 : bitPos; const int actualWidth = (bitPos < 0) ? (lbits + bitPos) : lbits; - q.atWrite(i) = VL_SEL_IWII(rbits, rwp, actualBitPos, actualWidth) & mask; + q.atWrite(i) = VL_SEL_IWII_TTTT(rbits, rwp, actualBitPos, actualWidth) & mask; } } @@ -3183,7 +4358,7 @@ static inline void VL_UNPACK_RI_W(int lbits, int rbits, VlQueue& q, WData const int bitPos = rbits - (i + 1) * lbits; const int actualBitPos = (bitPos < 0) ? 0 : bitPos; const int actualWidth = (bitPos < 0) ? (lbits + bitPos) : lbits; - q.atWrite(i) = VL_SEL_IWII(rbits, rwp, actualBitPos, actualWidth) & mask; + q.atWrite(i) = VL_SEL_IWII_TTTT(rbits, rwp, actualBitPos, actualWidth) & mask; } } @@ -3196,7 +4371,7 @@ static inline void VL_UNPACK_RQ_W(int lbits, int rbits, VlQueue& q, WData const int bitPos = rbits - (i + 1) * lbits; const int actualBitPos = (bitPos < 0) ? 0 : bitPos; const int actualWidth = (bitPos < 0) ? (lbits + bitPos) : lbits; - q.atWrite(i) = VL_SEL_QWII(rbits, rwp, actualBitPos, actualWidth) & mask; + q.atWrite(i) = VL_SEL_QWII_TTTT(rbits, rwp, actualBitPos, actualWidth) & mask; } } @@ -3210,7 +4385,7 @@ static inline void VL_UNPACK_RW_W(int lbits, int rbits, VlQueue> const int bitPos = rbits - (i + 1) * lbits; const int actualBitPos = (bitPos < 0) ? 0 : bitPos; const int actualWidth = (bitPos < 0) ? (lbits + bitPos) : lbits; - VL_SEL_WWII(actualWidth, rbits, q.atWrite(i), rwp, actualBitPos, actualWidth); + VL_SEL_WWII_TTTT(actualWidth, rbits, q.atWrite(i), rwp, actualBitPos, actualWidth); } } @@ -3320,7 +4495,7 @@ static inline void VL_UNPACK_UI_W(int lbits, int rbits, VlUnpacked @@ -3328,7 +4503,7 @@ static inline void VL_UNPACK_UI_W(int lbits, int rbits, VlUnpacked @@ -3336,7 +4511,7 @@ static inline void VL_UNPACK_UI_W(int lbits, int rbits, VlUnpacked @@ -3344,14 +4519,14 @@ static inline void VL_UNPACK_UQ_W(int lbits, int rbits, VlUnpacked static inline void VL_UNPACK_UW_W(int lbits, int rbits, VlUnpacked, N_Depth>& q, WDataInP rwp, const int bit_offset = 0) { for (size_t i = 0; i < N_Depth; ++i) - VL_SEL_WWII(lbits, rbits, q[i], rwp, bit_offset + (N_Depth - 1 - i) * lbits, lbits); + VL_SEL_WWII_TTTT(lbits, rbits, q[i], rwp, bit_offset + (N_Depth - 1 - i) * lbits, lbits); } // Return QData from double (numeric) @@ -3380,17 +4555,17 @@ static inline WDataOutP VL_RTOIROUND_W_D(int obits, WDataOutP owp, double lhs) V // IEEE format: [63]=sign [62:52]=exp+1023 [51:0]=mantissa // This does not need to support subnormals as they are sub-integral lhs = VL_ROUND(lhs); - VL_ZERO_W(obits, owp); + VL_ZERO_W_T(obits, owp); if (lhs == 0.0) return owp; const QData q = VL_CVT_Q_D(lhs); const int lsb = static_cast((q >> 52ULL) & VL_MASK_Q(11)) - 1023 - 52; const uint64_t mantissa = (q & VL_MASK_Q(52)) | (1ULL << 52); if (lsb < 0) { - VL_SET_WQ(owp, mantissa >> -lsb); + VL_SET_WQ_T(owp, mantissa >> -lsb); } else if (lsb < obits) { - _vl_insert_WQ(owp, mantissa, lsb + 52, lsb); + _vl_insert_WQ_T(owp, mantissa, lsb + 52, lsb); } - if (lhs < 0) VL_NEGATE_INPLACE_W(VL_WORDS_I(obits), owp); + if (lhs < 0) VL_NEGATE_INPLACE_W_T(VL_WORDS_I(obits), owp); return owp; } @@ -3398,264 +4573,279 @@ static inline WDataOutP VL_RTOIROUND_W_D(int obits, WDataOutP owp, double lhs) V // Range assignments // EMIT_RULE: VL_ASSIGNRANGE: rclean=dirty; -static inline void VL_ASSIGNSEL_II(int rbits, int obits, int lsb, CData& lhsr, IData rhs) VL_PURE { +static inline void VL_ASSIGNSEL_II_TT(int rbits, int obits, int lsb, CData& lhsr, + IData rhs) VL_PURE { _vl_insert_II(lhsr, rhs, lsb + obits - 1, lsb, rbits); } -static inline void VL_ASSIGNSEL_II(int rbits, int obits, int lsb, SData& lhsr, IData rhs) VL_PURE { +static inline void VL_ASSIGNSEL_II_TT(int rbits, int obits, int lsb, SData& lhsr, + IData rhs) VL_PURE { _vl_insert_II(lhsr, rhs, lsb + obits - 1, lsb, rbits); } -static inline void VL_ASSIGNSEL_II(int rbits, int obits, int lsb, IData& lhsr, IData rhs) VL_PURE { +static inline void VL_ASSIGNSEL_II_TT(int rbits, int obits, int lsb, IData& lhsr, + IData rhs) VL_PURE { _vl_insert_II(lhsr, rhs, lsb + obits - 1, lsb, rbits); } -static inline void VL_ASSIGNSEL_QI(int rbits, int obits, int lsb, QData& lhsr, IData rhs) VL_PURE { +static inline void VL_ASSIGNSEL_QI_TT(int rbits, int obits, int lsb, QData& lhsr, + IData rhs) VL_PURE { _vl_insert_QQ(lhsr, rhs, lsb + obits - 1, lsb, rbits); } -static inline void VL_ASSIGNSEL_QQ(int rbits, int obits, int lsb, QData& lhsr, QData rhs) VL_PURE { +static inline void VL_ASSIGNSEL_QQ_TT(int rbits, int obits, int lsb, QData& lhsr, + QData rhs) VL_PURE { _vl_insert_QQ(lhsr, rhs, lsb + obits - 1, lsb, rbits); } // static inline void VL_ASSIGNSEL_IIIW(int obits, int lsb, IData& lhsr, WDataInP const rwp) // VL_MT_SAFE { Illegal, as lhs width >= rhs width -static inline void VL_ASSIGNSEL_WI(int rbits, int obits, int lsb, WDataOutP iowp, - IData rhs) VL_MT_SAFE { - _vl_insert_WI(iowp, rhs, lsb + obits - 1, lsb, rbits); -} -static inline void VL_ASSIGNSEL_WQ(int rbits, int obits, int lsb, WDataOutP iowp, - QData rhs) VL_MT_SAFE { - _vl_insert_WQ(iowp, rhs, lsb + obits - 1, lsb, rbits); -} -static inline void VL_ASSIGNSEL_WW(int rbits, int obits, int lsb, WDataOutP iowp, - WDataInP const rwp) VL_MT_SAFE { - _vl_insert_WW(iowp, rwp, lsb + obits - 1, lsb, rbits); -} + +// clang-format off +#define VL_ASSIGNSEL_WI_GEN(lhsSuffix) \ +static inline void VL_ASSIGNSEL_WI_##lhsSuffix##T(int rbits, int obits, int lsb, WDataOutP iowp, IData rhs) \ + VL_MT_SAFE { \ + _vl_insert_WI_##lhsSuffix(iowp, rhs, lsb + obits - 1, lsb, rbits); \ + } +// clang-format on +VL_GEN_HELPER_ONE_ARG(VL_ASSIGNSEL_WI_GEN) +#undef VL_ASSIGNSEL_WI_GEN + +// clang-format off +#define VL_ASSIGNSEL_WQ_GEN(lhsSuffix) \ +static inline void VL_ASSIGNSEL_WQ_##lhsSuffix##T(int rbits, int obits, int lsb, \ + WDataOutP iowp, QData rhs) VL_MT_SAFE { \ + _vl_insert_WQ_##lhsSuffix(iowp, rhs, lsb + obits - 1, lsb, rbits); \ + } +// clang-format on +VL_GEN_HELPER_ONE_ARG(VL_ASSIGNSEL_WQ_GEN) +#undef VL_ASSIGNSEL_WQ_GEN + +// clang-format off +#define VL_ASSIGNSEL_WW_GEN(lhsSuffix, rhsSuffix) \ +static inline void VL_ASSIGNSEL_WW_##lhsSuffix##rhsSuffix( \ + int rbits, int obits, int lsb, WDataOutP iowp, WDataInP const rwp) VL_MT_SAFE { \ + _vl_insert_WW_##lhsSuffix##rhsSuffix(iowp, rwp, lsb + obits - 1, lsb, rbits); \ + } +// clang-format on +VL_GEN_HELPER_TWO_ARG(VL_ASSIGNSEL_WW_GEN) +#undef VL_ASSIGNSEL_WI_GEN //==================================================== // Range assignments // These additional functions copy bits range [obis+roffset-1:roffset] from rhs to lower bits // of lhs(select before assigning). Rhs should always be wider than lhs. -static inline void VL_SELASSIGN_II(int rbits, int obits, CData& lhsr, IData rhs, - int roffset) VL_PURE { +static inline void VL_SELASSIGN_II_TT(int rbits, int obits, CData& lhsr, IData rhs, + int roffset) VL_PURE { _vl_insert_II(lhsr, rhs >> roffset, obits - 1, 0, rbits); } -static inline void VL_SELASSIGN_II(int rbits, int obits, SData& lhsr, IData rhs, - int roffset) VL_PURE { +static inline void VL_SELASSIGN_II_TT(int rbits, int obits, SData& lhsr, IData rhs, + int roffset) VL_PURE { _vl_insert_II(lhsr, rhs >> roffset, obits - 1, 0, rbits); } -static inline void VL_SELASSIGN_II(int rbits, int obits, IData& lhsr, IData rhs, - int roffset) VL_PURE { +static inline void VL_SELASSIGN_II_TT(int rbits, int obits, IData& lhsr, IData rhs, + int roffset) VL_PURE { _vl_insert_II(lhsr, rhs >> roffset, obits - 1, 0, rbits); } -static inline void VL_SELASSIGN_IQ(int rbits, int obits, CData& lhsr, QData rhs, - int roffset) VL_PURE { +static inline void VL_SELASSIGN_IQ_TT(int rbits, int obits, CData& lhsr, QData rhs, + int roffset) VL_PURE { // it will be truncated to right CData mask const CData cleanmask = VL_MASK_I(rbits); const CData insmask = VL_MASK_I(obits); lhsr = (lhsr & ~insmask) | (static_cast(rhs >> roffset) & (insmask & cleanmask)); } -static inline void VL_SELASSIGN_IQ(int rbits, int obits, SData& lhsr, QData rhs, - int roffset) VL_PURE { +static inline void VL_SELASSIGN_IQ_TT(int rbits, int obits, SData& lhsr, QData rhs, + int roffset) VL_PURE { // it will be truncated to right CData mask const SData cleanmask = VL_MASK_I(rbits); const SData insmask = VL_MASK_I(obits); lhsr = (lhsr & ~insmask) | (static_cast(rhs >> roffset) & (insmask & cleanmask)); } -static inline void VL_SELASSIGN_IQ(int rbits, int obits, IData& lhsr, QData rhs, - int roffset) VL_PURE { +static inline void VL_SELASSIGN_IQ_TT(int rbits, int obits, IData& lhsr, QData rhs, + int roffset) VL_PURE { const IData cleanmask = VL_MASK_I(rbits); const IData insmask = VL_MASK_I(obits); lhsr = (lhsr & ~insmask) | (static_cast(rhs >> roffset) & (insmask & cleanmask)); } -static inline void VL_SELASSIGN_QQ(int rbits, int obits, QData& lhsr, QData rhs, - int roffset) VL_PURE { +static inline void VL_SELASSIGN_QQ_TT(int rbits, int obits, QData& lhsr, QData rhs, + int roffset) VL_PURE { _vl_insert_QQ(lhsr, rhs >> roffset, obits - 1, 0, rbits); } -static inline void VL_SELASSIGN_IW(int rbits, int obits, CData& lhsr, WDataInP const rhs, - int roffset) VL_MT_SAFE { - IData l = static_cast(lhsr); - _vl_insert_IW(l, rhs, roffset + obits - 1, roffset, rbits); - lhsr = static_cast(l); -} -static inline void VL_SELASSIGN_IW(int rbits, int obits, SData& lhsr, WDataInP const rhs, - int roffset) VL_MT_SAFE { - IData l = static_cast(lhsr); - _vl_insert_IW(l, rhs, roffset + obits - 1, roffset, rbits); - lhsr = static_cast(l); -} -static inline void VL_SELASSIGN_IW(int rbits, int obits, IData& lhsr, WDataInP const rhs, - int roffset) VL_MT_SAFE { - _vl_insert_IW(lhsr, rhs, roffset + obits - 1, roffset, rbits); -} -static inline void VL_SELASSIGN_QW(int rbits, int obits, QData& lhsr, WDataInP const rhs, - int roffset) VL_MT_SAFE { - // assert VL_QDATASIZE >= rbits > VL_IDATASIZE; - IData low = static_cast(lhsr); - IData high = static_cast(lhsr >> VL_IDATASIZE); - if (obits <= VL_IDATASIZE) { - _vl_insert_IW(low, rhs, obits + roffset - 1, roffset, VL_IDATASIZE); - } else { - _vl_insert_IW(low, rhs, roffset + VL_IDATASIZE - 1, roffset, VL_IDATASIZE); - _vl_insert_IW(high, rhs, roffset + obits - 1, roffset + VL_IDATASIZE, - rbits - VL_IDATASIZE); +// clang-format off +#define VL_SELASSIGN_IW_GEN(rhsSuffix) \ +static inline void VL_SELASSIGN_IW_T##rhsSuffix(int rbits, int obits, CData& lhsr, \ + WDataInP const rhs, int roffset) VL_MT_SAFE { \ + IData l = static_cast(lhsr); \ + _vl_insert_IW_T##rhsSuffix(l, rhs, roffset + obits - 1, roffset, rbits); \ + lhsr = static_cast(l); \ } - lhsr = (static_cast(high) << VL_IDATASIZE) | low; -} +// clang-format on +VL_GEN_HELPER_ONE_ARG(VL_SELASSIGN_IW_GEN) +#undef VL_SELASSIGN_IW_GEN -static inline void VL_SELASSIGN_WW(int rbits, int obits, WDataOutP iowp, WDataInP const rwp, - int roffset) VL_MT_SAFE { - // assert rbits > VL_QDATASIZE - const int wordoff = roffset / VL_EDATASIZE; - const int lsb = roffset & VL_SIZEBITS_E; - const int upperbits = lsb == 0 ? 0 : VL_EDATASIZE - lsb; - // If roffset is not aligned, we copy some bits to align it. - if (lsb != 0) { - const int w = obits < upperbits ? obits : upperbits; - const int insmask = VL_MASK_E(w); - iowp[0] = (iowp[0] & ~insmask) | ((rwp[wordoff] >> lsb) & insmask); - // cppcheck-suppress knownConditionTrueFalse - if (w == obits) return; - obits -= w; +// clang-format off +#define VL_SELASSIGN_IW_GEN(rhsSuffix) \ +static inline void VL_SELASSIGN_IW_T##rhsSuffix(int rbits, int obits, SData& lhsr, \ + WDataInP const rhs, int roffset) VL_MT_SAFE { \ + IData l = static_cast(lhsr); \ + _vl_insert_IW_T##rhsSuffix(l, rhs, roffset + obits - 1, roffset, rbits); \ + lhsr = static_cast(l); \ } - _vl_insert_WW(iowp, rwp + static_cast(wordoff + (lsb != 0)), upperbits + obits - 1, - upperbits, rbits); -} +// clang-format on +VL_GEN_HELPER_ONE_ARG(VL_SELASSIGN_IW_GEN) +#undef VL_SELASSIGN_IW_GEN + +// clang-format off +#define VL_SELASSIGN_IW_GEN(rhsSuffix) \ +static inline void VL_SELASSIGN_IW_T##rhsSuffix(int rbits, int obits, IData& lhsr, \ + WDataInP const rhs, int roffset) VL_MT_SAFE { \ + _vl_insert_IW_T##rhsSuffix(lhsr, rhs, roffset + obits - 1, roffset, rbits); \ + } +// clang-format on +VL_GEN_HELPER_ONE_ARG(VL_SELASSIGN_IW_GEN) +#undef VL_SELASSIGN_IW_GEN + +// clang-format off +#define VL_SELASSIGN_QW_GEN(rhsSuffix) \ +static inline void VL_SELASSIGN_QW_T##rhsSuffix(int rbits, int obits, QData& lhsr, \ + WDataInP const rhs, int roffset) VL_MT_SAFE { \ + /* assert VL_QDATASIZE >= rbits > VL_IDATASIZE; */ \ + IData low = static_cast(lhsr); \ + IData high = static_cast(lhsr >> VL_IDATASIZE); \ + if (obits <= VL_IDATASIZE) { \ + _vl_insert_IW_T##rhsSuffix(low, rhs, obits + roffset - 1, roffset, VL_IDATASIZE); \ + } else { \ + _vl_insert_IW_T##rhsSuffix(low, rhs, roffset + VL_IDATASIZE - 1, roffset, \ + VL_IDATASIZE); \ + _vl_insert_IW_T##rhsSuffix(high, rhs, roffset + obits - 1, roffset + VL_IDATASIZE, \ + rbits - VL_IDATASIZE); \ + } \ + lhsr = (static_cast(high) << VL_IDATASIZE) | low; \ + } +// clang-format on +VL_GEN_HELPER_ONE_ARG(VL_SELASSIGN_QW_GEN) +#undef VL_SELASSIGN_QW_GEN + +// clang-format off +#define VL_SELASSIGN_WW_GEN(lhsSuffix, rhsSuffix) \ +static inline void VL_SELASSIGN_WW_##lhsSuffix##rhsSuffix( \ + int rbits, int obits, WDataOutP iowp, WDataInP rwp, int roffset) VL_MT_SAFE { \ + /* assert rbits > VL_QDATASIZE */ \ + const int wordoff = roffset / VL_EDATASIZE; \ + const int lsb = roffset & VL_SIZEBITS_E; \ + const int upperbits = lsb == 0 ? 0 : VL_EDATASIZE - lsb; \ + /* If roffset is not aligned, we copy some bits to align it. */ \ + if (lsb != 0) { \ + const int w = obits < upperbits ? obits : upperbits; \ + const int insmask = VL_MASK_E(w); \ + const WDataOutP iowp0 = VL_GET_ELEM(lhsSuffix, iowp, 0); \ + *iowp0 = (*iowp0 & ~insmask) \ + | ((*VL_GET_ELEM(rhsSuffix, rwp, wordoff) >> lsb) & insmask); \ + /* cppcheck-suppress knownConditionTrueFalse */ \ + if (w == obits) return; \ + obits -= w; \ + } \ + rwp = VL_GET_ELEM(rhsSuffix, rwp, wordoff + (lsb != 0)) - VL_GET_TYPE_OFFSET(rhsSuffix); \ + /* ^ the '- VL_GET_TYPE_OFFSET(rhsSuffix)' is here to pretend that this is not a middle \ + * of some wide - we need this since _vl_insert_WW_** will add offset */ \ + _vl_insert_WW_##lhsSuffix##rhsSuffix(iowp, rwp, upperbits + obits - 1, upperbits, rbits); \ + } +// clang-format on +VL_GEN_HELPER_TWO_ARG(VL_SELASSIGN_WW_GEN) +#undef VL_SELASSIGN_WW_GEN //====================================================================== // Triops // This must be a macro in order for short-circuiting of the values to work. -#define VL_COND_WIWW(obits, owp, cond, w1p, w2p) \ - VL_MEMCPY_W(owp, (cond) ? (w1p) : (w2p), VL_WORDS_I(obits)) +#define VL_COND_WIWW_TTTT(obits, owp, cond, w1p, w2p) \ + VL_ASSIGN_W_TT(obits, owp, (cond) ? (w1p) : (w2p)) +#define VL_COND_WIWW_TTVV(obits, owp, cond, w1p, w2p) \ + VL_ASSIGN_W_TV(obits, owp, (cond) ? (w1p) : (w2p)) +#define VL_COND_WIWW_TTXX(obits, owp, cond, w1p, w2p) \ + VL_ASSIGN_W_TX(obits, owp, (cond) ? (w1p) : (w2p)) +#define VL_COND_WIWW_VTTT(obits, owp, cond, w1p, w2p) \ + VL_ASSIGN_W_VT(obits, owp, (cond) ? (w1p) : (w2p)) +#define VL_COND_WIWW_VTVV(obits, owp, cond, w1p, w2p) \ + VL_ASSIGN_W_VV(obits, owp, (cond) ? (w1p) : (w2p)) +#define VL_COND_WIWW_VTXX(obits, owp, cond, w1p, w2p) \ + VL_ASSIGN_W_VX(obits, owp, (cond) ? (w1p) : (w2p)) +#define VL_COND_WIWW_XTTT(obits, owp, cond, w1p, w2p) \ + VL_ASSIGN_W_XT(obits, owp, (cond) ? (w1p) : (w2p)) +#define VL_COND_WIWW_XTVV(obits, owp, cond, w1p, w2p) \ + VL_ASSIGN_W_XV(obits, owp, (cond) ? (w1p) : (w2p)) +#define VL_COND_WIWW_XTXX(obits, owp, cond, w1p, w2p) \ + VL_ASSIGN_W_XX(obits, owp, (cond) ? (w1p) : (w2p)) +#define VL_COND_WIWW_TTTV(obits, owp, cond, w1p, w2p) \ + ((cond) ? VL_ASSIGN_W_TT(obits, owp, w1p) : VL_ASSIGN_W_TV(obits, owp, w2p)) +#define VL_COND_WIWW_TTTX(obits, owp, cond, w1p, w2p) \ + ((cond) ? VL_ASSIGN_W_TT(obits, owp, w1p) : VL_ASSIGN_W_TX(obits, owp, w2p)) +#define VL_COND_WIWW_TTVT(obits, owp, cond, w1p, w2p) \ + ((cond) ? VL_ASSIGN_W_TV(obits, owp, w1p) : VL_ASSIGN_W_TT(obits, owp, w2p)) +#define VL_COND_WIWW_TTVX(obits, owp, cond, w1p, w2p) \ + ((cond) ? VL_ASSIGN_W_TV(obits, owp, w1p) : VL_ASSIGN_W_TX(obits, owp, w2p)) +#define VL_COND_WIWW_TTXT(obits, owp, cond, w1p, w2p) \ + ((cond) ? VL_ASSIGN_W_TX(obits, owp, w1p) : VL_ASSIGN_W_TT(obits, owp, w2p)) +#define VL_COND_WIWW_TTXV(obits, owp, cond, w1p, w2p) \ + ((cond) ? VL_ASSIGN_W_TX(obits, owp, w1p) : VL_ASSIGN_W_TV(obits, owp, w2p)) +#define VL_COND_WIWW_VTTV(obits, owp, cond, w1p, w2p) \ + ((cond) ? VL_ASSIGN_W_VT(obits, owp, w1p) : VL_ASSIGN_W_VV(obits, owp, w2p)) +#define VL_COND_WIWW_VTTX(obits, owp, cond, w1p, w2p) \ + ((cond) ? VL_ASSIGN_W_VT(obits, owp, w1p) : VL_ASSIGN_W_VX(obits, owp, w2p)) +#define VL_COND_WIWW_VTVT(obits, owp, cond, w1p, w2p) \ + ((cond) ? VL_ASSIGN_W_VV(obits, owp, w1p) : VL_ASSIGN_W_VT(obits, owp, w2p)) +#define VL_COND_WIWW_VTVX(obits, owp, cond, w1p, w2p) \ + ((cond) ? VL_ASSIGN_W_VV(obits, owp, w1p) : VL_ASSIGN_W_VX(obits, owp, w2p)) +#define VL_COND_WIWW_VTXT(obits, owp, cond, w1p, w2p) \ + ((cond) ? VL_ASSIGN_W_VX(obits, owp, w1p) : VL_ASSIGN_W_VT(obits, owp, w2p)) +#define VL_COND_WIWW_VTXV(obits, owp, cond, w1p, w2p) \ + ((cond) ? VL_ASSIGN_W_VX(obits, owp, w1p) : VL_ASSIGN_W_VV(obits, owp, w2p)) +#define VL_COND_WIWW_XTTV(obits, owp, cond, w1p, w2p) \ + ((cond) ? VL_ASSIGN_W_XT(obits, owp, w1p) : VL_ASSIGN_W_XV(obits, owp, w2p)) +#define VL_COND_WIWW_XTTX(obits, owp, cond, w1p, w2p) \ + ((cond) ? VL_ASSIGN_W_XT(obits, owp, w1p) : VL_ASSIGN_W_XX(obits, owp, w2p)) +#define VL_COND_WIWW_XTVT(obits, owp, cond, w1p, w2p) \ + ((cond) ? VL_ASSIGN_W_XV(obits, owp, w1p) : VL_ASSIGN_W_XT(obits, owp, w2p)) +#define VL_COND_WIWW_XTVX(obits, owp, cond, w1p, w2p) \ + ((cond) ? VL_ASSIGN_W_XV(obits, owp, w1p) : VL_ASSIGN_W_XX(obits, owp, w2p)) +#define VL_COND_WIWW_XTXT(obits, owp, cond, w1p, w2p) \ + ((cond) ? VL_ASSIGN_W_XX(obits, owp, w1p) : VL_ASSIGN_W_XT(obits, owp, w2p)) +#define VL_COND_WIWW_XTXV(obits, owp, cond, w1p, w2p) \ + ((cond) ? VL_ASSIGN_W_XX(obits, owp, w1p) : VL_ASSIGN_W_XV(obits, owp, w2p)) //====================================================================== // Constification -// VL_CONST_W_#X(int obits, WDataOutP owp, IData data0, .... IData data(#-1)) +// VL_CONST_W_#T/V/X(int obits, WDataOutP owp, {IData data0, .... IData data(#-1)}) // Sets wide vector words to specified constant words. // These macros are used when o might represent more words then are given as constants, // hence all upper words must be zeroed. -// If changing the number of functions here, also change EMITCINLINES_NUM_CONSTW #define VL_C_END_(obits, wordsSet) \ VL_MEMSET_ZERO_W(o + (wordsSet), VL_WORDS_I(obits) - (wordsSet)); \ return o +static inline WDataOutP VL_CONST_W_T(const int obits, WDataOutP const o, + std::initializer_list values) VL_MT_SAFE { + VL_MEMCPY_W(o, WDataInP::external(values.begin()), values.size()); + VL_C_END_(obits, values.size()); +} + // clang-format off -static inline WDataOutP VL_CONST_W_1X(int obits, WDataOutP o, EData d0) VL_MT_SAFE { - o[0] = d0; - VL_C_END_(obits, 1); -} -static inline WDataOutP VL_CONST_W_2X(int obits, WDataOutP o, EData d1, EData d0) VL_MT_SAFE { - o[0] = d0; o[1] = d1; - VL_C_END_(obits, 2); -} -static inline WDataOutP VL_CONST_W_3X(int obits, WDataOutP o, EData d2, EData d1, - EData d0) VL_MT_SAFE { - o[0] = d0; o[1] = d1; o[2] = d2; - VL_C_END_(obits, 3); -} -static inline WDataOutP VL_CONST_W_4X(int obits, WDataOutP o, - EData d3, EData d2, EData d1, EData d0) VL_MT_SAFE { - o[0] = d0; o[1] = d1; o[2] = d2; o[3] = d3; - VL_C_END_(obits, 4); -} -static inline WDataOutP VL_CONST_W_5X(int obits, WDataOutP o, - EData d4, - EData d3, EData d2, EData d1, EData d0) VL_MT_SAFE { - o[0] = d0; o[1] = d1; o[2] = d2; o[3] = d3; - o[4] = d4; - VL_C_END_(obits, 5); -} -static inline WDataOutP VL_CONST_W_6X(int obits, WDataOutP o, - EData d5, EData d4, - EData d3, EData d2, EData d1, EData d0) VL_MT_SAFE { - o[0] = d0; o[1] = d1; o[2] = d2; o[3] = d3; - o[4] = d4; o[5] = d5; - VL_C_END_(obits, 6); -} -static inline WDataOutP VL_CONST_W_7X(int obits, WDataOutP o, - EData d6, EData d5, EData d4, - EData d3, EData d2, EData d1, EData d0) VL_MT_SAFE { - o[0] = d0; o[1] = d1; o[2] = d2; o[3] = d3; - o[4] = d4; o[5] = d5; o[6] = d6; - VL_C_END_(obits, 7); -} -static inline WDataOutP VL_CONST_W_8X(int obits, WDataOutP o, - EData d7, EData d6, EData d5, EData d4, - EData d3, EData d2, EData d1, EData d0) VL_MT_SAFE { - o[0] = d0; o[1] = d1; o[2] = d2; o[3] = d3; - o[4] = d4; o[5] = d5; o[6] = d6; o[7] = d7; - VL_C_END_(obits, 8); -} -// -static inline WDataOutP VL_CONSTHI_W_1X(int obits, int lsb, WDataOutP o, - EData d0) VL_MT_SAFE { - WDataOutP ohi = o + VL_WORDS_I(lsb); - ohi[0] = d0; - VL_C_END_(obits, VL_WORDS_I(lsb) + 1); -} -static inline WDataOutP VL_CONSTHI_W_2X(int obits, int lsb, WDataOutP o, - EData d1, EData d0) VL_MT_SAFE { - WDataOutP ohi = o + VL_WORDS_I(lsb); - ohi[0] = d0; ohi[1] = d1; - VL_C_END_(obits, VL_WORDS_I(lsb) + 2); -} -static inline WDataOutP VL_CONSTHI_W_3X(int obits, int lsb, WDataOutP o, - EData d2, EData d1, EData d0) VL_MT_SAFE { - WDataOutP ohi = o + VL_WORDS_I(lsb); - ohi[0] = d0; ohi[1] = d1; ohi[2] = d2; - VL_C_END_(obits, VL_WORDS_I(lsb) + 3); -} -static inline WDataOutP VL_CONSTHI_W_4X(int obits, int lsb, WDataOutP o, - EData d3, EData d2, EData d1, EData d0) VL_MT_SAFE { - WDataOutP ohi = o + VL_WORDS_I(lsb); - ohi[0] = d0; ohi[1] = d1; ohi[2] = d2; ohi[3] = d3; - VL_C_END_(obits, VL_WORDS_I(lsb) + 4); -} -static inline WDataOutP VL_CONSTHI_W_5X(int obits, int lsb, WDataOutP o, - EData d4, - EData d3, EData d2, EData d1, EData d0) VL_MT_SAFE { - WDataOutP ohi = o + VL_WORDS_I(lsb); - ohi[0] = d0; ohi[1] = d1; ohi[2] = d2; ohi[3] = d3; - ohi[4] = d4; - VL_C_END_(obits, VL_WORDS_I(lsb) + 5); -} -static inline WDataOutP VL_CONSTHI_W_6X(int obits, int lsb, WDataOutP o, - EData d5, EData d4, - EData d3, EData d2, EData d1, EData d0) VL_MT_SAFE { - WDataOutP ohi = o + VL_WORDS_I(lsb); - ohi[0] = d0; ohi[1] = d1; ohi[2] = d2; ohi[3] = d3; - ohi[4] = d4; ohi[5] = d5; - VL_C_END_(obits, VL_WORDS_I(lsb) + 6); -} -static inline WDataOutP VL_CONSTHI_W_7X(int obits, int lsb, WDataOutP o, - EData d6, EData d5, EData d4, - EData d3, EData d2, EData d1, EData d0) VL_MT_SAFE { - WDataOutP ohi = o + VL_WORDS_I(lsb); - ohi[0] = d0; ohi[1] = d1; ohi[2] = d2; ohi[3] = d3; - ohi[4] = d4; ohi[5] = d5; ohi[6] = d6; - VL_C_END_(obits, VL_WORDS_I(lsb) + 7); -} -static inline WDataOutP VL_CONSTHI_W_8X(int obits, int lsb, WDataOutP o, - EData d7, EData d6, EData d5, EData d4, - EData d3, EData d2, EData d1, EData d0) VL_MT_SAFE { - WDataOutP ohi = o + VL_WORDS_I(lsb); - ohi[0] = d0; ohi[1] = d1; ohi[2] = d2; ohi[3] = d3; - ohi[4] = d4; ohi[5] = d5; ohi[6] = d6; ohi[7] = d7; - VL_C_END_(obits, VL_WORDS_I(lsb) + 8); -} - -#undef VL_C_END_ - -// Partial constant, lower words of vector wider than 8*32, starting at bit number lsb -static inline void VL_CONSTLO_W_8X(int lsb, WDataOutP obase, - EData d7, EData d6, EData d5, EData d4, - EData d3, EData d2, EData d1, EData d0) VL_MT_SAFE { - WDataOutP o = obase + VL_WORDS_I(lsb); - o[0] = d0; o[1] = d1; o[2] = d2; o[3] = d3; o[4] = d4; o[5] = d5; o[6] = d6; o[7] = d7; -} +#define VL_CONST_W_GEN(outputSuffix) \ +static inline WDataOutP VL_CONST_W_##outputSuffix( \ + const int obits, WDataOutP o, std::initializer_list values) VL_MT_SAFE { \ + const WDataOutP resultp = o; \ + o += VL_GET_TYPE_OFFSET(outputSuffix); \ + for (EData v : values) { \ + *o = v; \ + o += VL_GET_TYPE_JUMP(outputSuffix); \ + } \ + VL_ZERO_OFFSET_W_##outputSuffix(obits - (values.size() * VL_EDATASIZE), o); \ + return resultp; \ + } // clang-format on +VL_CONST_W_GEN(V) +VL_CONST_W_GEN(X) +#undef VL_CONST_W_GEN //====================================================================== // Strings @@ -3697,7 +4887,7 @@ extern std::string VL_CVT_PACK_STR_NW(int lwords, const WDataInP lwp) VL_PURE; extern std::string VL_CVT_PACK_STR_ND(const VlQueue& q) VL_PURE; inline std::string VL_CVT_PACK_STR_NQ(QData lhs) VL_PURE { VlWide lw; - VL_SET_WQ(lw, lhs); + VL_SET_WQ_T(lw, lhs); return VL_CVT_PACK_STR_NW(VL_WQ_WORDS_E, lw); } inline std::string VL_CVT_PACK_STR_NN(const std::string& lhs) VL_PURE { return lhs; } @@ -3782,4 +4972,8 @@ uint64_t VL_MURMUR64_HASH(const char* key) VL_PURE; //====================================================================== +#undef VL_GEN_HELPER_THREE_ARG +#undef VL_GEN_HELPER_TWO_ARG +#undef VL_GEN_HELPER_ONE_ARG + #endif // Guard diff --git a/include/verilated_random.cpp b/include/verilated_random.cpp index 71f719722..4da8311f4 100644 --- a/include/verilated_random.cpp +++ b/include/verilated_random.cpp @@ -386,11 +386,11 @@ static bool parseSMTNum(int obits, WDataOutP owp, const std::string& val) { } bool VlRandomVar::set(const std::string& idx, const std::string& val) const { VlWide qowp; - VL_SET_WQ(qowp, 0ULL); + VL_SET_WQ_T(qowp, 0ULL); WDataOutP owp = qowp; const int obits = width(); VlWide qiwp; - VL_SET_WQ(qiwp, 0ULL); + VL_SET_WQ_T(qiwp, 0ULL); if (!idx.empty() && !parseSMTNum(64, qiwp, idx)) return false; const int nidx = qiwp[0]; if (obits > VL_QUADSIZE) owp = WDataOutP::external(reinterpret_cast(datap(nidx))); @@ -409,7 +409,7 @@ bool VlRandomVar::set(const std::string& idx, const std::string& val) const { QData* const p = static_cast(datap(nidx)); *p = VL_CLEAN_QQ(obits, obits, VL_SET_QW(owp)); } else { - _vl_clean_inplace_w(obits, owp); + _vl_clean_inplace_w_T(obits, owp); } return true; } diff --git a/include/verilated_saif_c.cpp b/include/verilated_saif_c.cpp index 18f579ec2..b0568b647 100644 --- a/include/verilated_saif_c.cpp +++ b/include/verilated_saif_c.cpp @@ -65,20 +65,23 @@ class VerilatedSaifActivityBit final { // MEMBERS bool m_lastVal = false; // Last emitted activity bit value + bool m_lastValXZ = false; // Last emitted activity bit value uint64_t m_highTime = 0; // Total time when bit was high size_t m_transitions = 0; // Total number of bit transitions public: // METHODS VL_ATTR_ALWINLINE - void aggregateVal(uint64_t dt, bool newVal) { - m_transitions += newVal != m_lastVal ? 1 : 0; + void aggregateVal(uint64_t dt, bool newVal, bool newValXZ = false) { + m_transitions += (newVal != m_lastVal || m_lastValXZ != newValXZ) ? 1 : 0; m_highTime += m_lastVal ? dt : 0; m_lastVal = newVal; + m_lastValXZ = newValXZ; } // ACCESSORS VL_ATTR_ALWINLINE bool bitValue() const { return m_lastVal; } + VL_ATTR_ALWINLINE bool bitValueXZ() const { return m_lastValXZ; } VL_ATTR_ALWINLINE uint64_t highTime() const { return m_highTime; } VL_ATTR_ALWINLINE uint64_t toggleCount() const { return m_transitions; } }; @@ -104,6 +107,7 @@ public: // METHODS VL_ATTR_ALWINLINE void emitBit(uint64_t time, CData newval); + VL_ATTR_ALWINLINE void emitLogic(uint64_t time, CData newval, CData newvalXZ); template VL_ATTR_ALWINLINE void emitData(uint64_t time, DataType newval, uint32_t bits) { @@ -117,7 +121,23 @@ public: updateLastTime(time); } + template + VL_ATTR_ALWINLINE void emitFourstateData(uint64_t time, DataType newval, DataType newvalXZ, + uint32_t bits) { + static_assert(std::is_integral::value, + "The emitted value must be of integral type"); + + const uint64_t dt = time - m_lastTime; + for (size_t i = 0; i < std::min(m_width, bits); ++i) { + m_bits[i].aggregateVal(dt, newval & 1, newvalXZ & 1); + newval >>= 1; + newvalXZ >>= 1; + } + updateLastTime(time); + } + VL_ATTR_ALWINLINE void emitWData(uint64_t time, WDataInP newval, uint32_t bits); + VL_ATTR_ALWINLINE void emitFourstateWData(uint64_t time, WDataInP newval, uint32_t bits); VL_ATTR_ALWINLINE void updateLastTime(uint64_t val) { m_lastTime = val; } // ACCESSORS @@ -229,7 +249,15 @@ void VerilatedSaifActivityVar::emitBit(const uint64_t time, const CData newval) } VL_ATTR_ALWINLINE -void VerilatedSaifActivityVar::emitWData(const uint64_t time, WDataInP newval, +void VerilatedSaifActivityVar::emitLogic(const uint64_t time, const CData newval, + const CData newvalXZ) { + assert(m_lastTime <= time); + m_bits[0].aggregateVal(time - m_lastTime, newval, newvalXZ); + updateLastTime(time); +} + +VL_ATTR_ALWINLINE +void VerilatedSaifActivityVar::emitWData(const uint64_t time, const WDataInP newval, const uint32_t bits) { assert(m_lastTime <= time); const uint64_t dt = time - m_lastTime; @@ -241,6 +269,20 @@ void VerilatedSaifActivityVar::emitWData(const uint64_t time, WDataInP newval, updateLastTime(time); } +VL_ATTR_ALWINLINE +void VerilatedSaifActivityVar::emitFourstateWData(const uint64_t time, const WDataInP newval, + const uint32_t bits) { + assert(m_lastTime <= time); + const uint64_t dt = time - m_lastTime; + for (std::size_t i = 0; i < std::min(m_width, bits) * 2; i += 2) { + const size_t wordIndex = i / VL_EDATASIZE; + m_bits[i].aggregateVal(dt, (newval[wordIndex] >> VL_BITBIT_E(i)) & 1, + (newval[wordIndex | 1] >> VL_BITBIT_E(i)) & 1); + } + + updateLastTime(time); +} + VerilatedSaifActivityBit& VerilatedSaifActivityVar::bit(const std::size_t index) { assert(index < m_width); return m_bits[index]; @@ -633,6 +675,15 @@ void VerilatedSaifBuffer::emitBit(const uint32_t code, const CData newval) { activity.emitBit(m_owner.currentTime(), newval); } +VL_ATTR_ALWINLINE +void VerilatedSaifBuffer::emitLogic(uint32_t code, CData newval, CData newvalXZ) { + assert(m_owner.m_activityAccumulators.at(m_fidx)->m_activity.count(code) + && "Activity must be declared earlier"); + VerilatedSaifActivityVar& activity + = m_owner.m_activityAccumulators.at(m_fidx)->m_activity.at(code); + activity.emitLogic(m_owner.currentTime(), newval, newvalXZ); +} + VL_ATTR_ALWINLINE void VerilatedSaifBuffer::emitCData(const uint32_t code, const CData newval, const int bits) { assert(m_owner.m_activityAccumulators.at(m_fidx)->m_activity.count(code) @@ -642,6 +693,16 @@ void VerilatedSaifBuffer::emitCData(const uint32_t code, const CData newval, con activity.emitData(m_owner.currentTime(), newval, bits); } +VL_ATTR_ALWINLINE +void VerilatedSaifBuffer::emitFourstateCData(uint32_t code, CData newval, CData newvalXZ, + int bits) { + assert(m_owner.m_activityAccumulators.at(m_fidx)->m_activity.count(code) + && "Activity must be declared earlier"); + VerilatedSaifActivityVar& activity + = m_owner.m_activityAccumulators.at(m_fidx)->m_activity.at(code); + activity.emitFourstateData(m_owner.currentTime(), newval, newvalXZ, bits); +} + VL_ATTR_ALWINLINE void VerilatedSaifBuffer::emitSData(const uint32_t code, const SData newval, const int bits) { assert(m_owner.m_activityAccumulators.at(m_fidx)->m_activity.count(code) @@ -651,6 +712,16 @@ void VerilatedSaifBuffer::emitSData(const uint32_t code, const SData newval, con activity.emitData(m_owner.currentTime(), newval, bits); } +VL_ATTR_ALWINLINE +void VerilatedSaifBuffer::emitFourstateSData(uint32_t code, SData newval, SData newvalXZ, + int bits) { + assert(m_owner.m_activityAccumulators.at(m_fidx)->m_activity.count(code) + && "Activity must be declared earlier"); + VerilatedSaifActivityVar& activity + = m_owner.m_activityAccumulators.at(m_fidx)->m_activity.at(code); + activity.emitFourstateData(m_owner.currentTime(), newval, newvalXZ, bits); +} + VL_ATTR_ALWINLINE void VerilatedSaifBuffer::emitIData(const uint32_t code, const IData newval, const int bits) { assert(m_owner.m_activityAccumulators.at(m_fidx)->m_activity.count(code) @@ -660,6 +731,16 @@ void VerilatedSaifBuffer::emitIData(const uint32_t code, const IData newval, con activity.emitData(m_owner.currentTime(), newval, bits); } +VL_ATTR_ALWINLINE +void VerilatedSaifBuffer::emitFourstateIData(uint32_t code, IData newval, IData newvalXZ, + int bits) { + assert(m_owner.m_activityAccumulators.at(m_fidx)->m_activity.count(code) + && "Activity must be declared earlier"); + VerilatedSaifActivityVar& activity + = m_owner.m_activityAccumulators.at(m_fidx)->m_activity.at(code); + activity.emitFourstateData(m_owner.currentTime(), newval, newvalXZ, bits); +} + VL_ATTR_ALWINLINE void VerilatedSaifBuffer::emitQData(const uint32_t code, const QData newval, const int bits) { assert(m_owner.m_activityAccumulators.at(m_fidx)->m_activity.count(code) @@ -670,7 +751,17 @@ void VerilatedSaifBuffer::emitQData(const uint32_t code, const QData newval, con } VL_ATTR_ALWINLINE -void VerilatedSaifBuffer::emitWData(const uint32_t code, WDataInP newval, const int bits) { +void VerilatedSaifBuffer::emitFourstateQData(uint32_t code, QData newval, QData newvalXZ, + int bits) { + assert(m_owner.m_activityAccumulators.at(m_fidx)->m_activity.count(code) + && "Activity must be declared earlier"); + VerilatedSaifActivityVar& activity + = m_owner.m_activityAccumulators.at(m_fidx)->m_activity.at(code); + activity.emitFourstateData(m_owner.currentTime(), newval, newvalXZ, bits); +} + +VL_ATTR_ALWINLINE +void VerilatedSaifBuffer::emitWData(const uint32_t code, const WDataInP newval, const int bits) { assert(m_owner.m_activityAccumulators.at(m_fidx)->m_activity.count(code) && "Activity must be declared earlier"); VerilatedSaifActivityVar& activity @@ -678,6 +769,16 @@ void VerilatedSaifBuffer::emitWData(const uint32_t code, WDataInP newval, const activity.emitWData(m_owner.currentTime(), newval, bits); } +VL_ATTR_ALWINLINE +void VerilatedSaifBuffer::emitFourstateWData(const uint32_t code, const WDataInP newval, + const int bits) { + assert(m_owner.m_activityAccumulators.at(m_fidx)->m_activity.count(code) + && "Activity must be declared earlier"); + VerilatedSaifActivityVar& activity + = m_owner.m_activityAccumulators.at(m_fidx)->m_activity.at(code); + activity.emitFourstateWData(m_owner.currentTime(), newval, bits); +} + VL_ATTR_ALWINLINE void VerilatedSaifBuffer::emitDouble(const uint32_t code, const double newval) { // NOP diff --git a/include/verilated_saif_c.h b/include/verilated_saif_c.h index 63cc717c0..8fb49221c 100644 --- a/include/verilated_saif_c.h +++ b/include/verilated_saif_c.h @@ -243,11 +243,21 @@ class VerilatedSaifBuffer VL_NOT_FINAL { // called from only one place (the full* methods), so always inline them. VL_ATTR_ALWINLINE void emitEvent(uint32_t code); VL_ATTR_ALWINLINE void emitBit(uint32_t code, CData newval); + VL_ATTR_ALWINLINE void emitLogic(uint32_t code, CData newval, CData newvalXZ); VL_ATTR_ALWINLINE void emitCData(uint32_t code, CData newval, int bits); + VL_ATTR_ALWINLINE void emitFourstateCData(uint32_t code, CData newval, CData newvalXZ, + int bits); VL_ATTR_ALWINLINE void emitSData(uint32_t code, SData newval, int bits); + VL_ATTR_ALWINLINE void emitFourstateSData(uint32_t code, SData newval, SData newvalXZ, + int bits); VL_ATTR_ALWINLINE void emitIData(uint32_t code, IData newval, int bits); + VL_ATTR_ALWINLINE void emitFourstateIData(uint32_t code, IData newval, IData newvalXZ, + int bits); VL_ATTR_ALWINLINE void emitQData(uint32_t code, QData newval, int bits); + VL_ATTR_ALWINLINE void emitFourstateQData(uint32_t code, QData newval, QData newvalXZ, + int bits); VL_ATTR_ALWINLINE void emitWData(uint32_t code, WDataInP newval, int bits); + VL_ATTR_ALWINLINE void emitFourstateWData(uint32_t code, WDataInP newval, int bits); VL_ATTR_ALWINLINE void emitDouble(uint32_t code, double newval); }; diff --git a/include/verilated_trace.h b/include/verilated_trace.h index de8f89946..d10e9a3c2 100644 --- a/include/verilated_trace.h +++ b/include/verilated_trace.h @@ -385,11 +385,17 @@ public: // Write to previous value buffer value and emit trace entry. void fullBit(uint32_t* oldp, CData newval); + void fullLogic(uint32_t* oldp, CData newval, CData newvalXZ); void fullCData(uint32_t* oldp, CData newval, int bits); + void fullFourstateCData(uint32_t* oldp, CData newval, CData newvalXZ, int bits); void fullSData(uint32_t* oldp, SData newval, int bits); + void fullFourstateSData(uint32_t* oldp, SData newval, SData newvalXZ, int bits); void fullIData(uint32_t* oldp, IData newval, int bits); + void fullFourstateIData(uint32_t* oldp, IData newval, IData newvalXZ, int bits); void fullQData(uint32_t* oldp, QData newval, int bits); + void fullFourstateQData(uint32_t* oldp, QData newval, QData newvalXZ, int bits); void fullWData(uint32_t* oldp, WDataInP newval, int bits); + void fullFourstateWData(uint32_t* oldp, WDataInP newval, int bits); void fullDouble(uint32_t* oldp, double newval); void fullEvent(uint32_t* oldp, const VlEventBase* newvalp); void fullEventTriggered(uint32_t* oldp); @@ -399,32 +405,69 @@ public: const uint32_t diff = *oldp ^ newval; if (VL_UNLIKELY(diff)) fullBit(oldp, newval); } + VL_ATTR_ALWINLINE void chgLogic(uint32_t* oldp, CData newval, CData newvalXZ) { + CData* oldcp = reinterpret_cast(oldp); + const uint32_t diff = (oldcp[0] ^ newval) | (oldcp[1] ^ newvalXZ); + if (VL_UNLIKELY(diff)) fullLogic(oldp, newval, newvalXZ); + } VL_ATTR_ALWINLINE void chgCData(uint32_t* oldp, CData newval, int bits) { const uint32_t diff = *oldp ^ newval; if (VL_UNLIKELY(diff)) fullCData(oldp, newval, bits); } + VL_ATTR_ALWINLINE void chgFourstateCData(uint32_t* oldp, CData newval, CData newvalXZ, + int bits) { + CData* oldcp = reinterpret_cast(oldp); + const uint32_t diff = (oldcp[0] ^ newval) | (oldcp[1] ^ newvalXZ); + if (VL_UNLIKELY(diff)) fullFourstateCData(oldp, newval, newvalXZ, bits); + } VL_ATTR_ALWINLINE void chgSData(uint32_t* oldp, SData newval, int bits) { const uint32_t diff = *oldp ^ newval; if (VL_UNLIKELY(diff)) fullSData(oldp, newval, bits); } + VL_ATTR_ALWINLINE void chgFourstateSData(uint32_t* oldp, SData newval, SData newvalXZ, + int bits) { + SData* oldcp = reinterpret_cast(oldp); + const uint32_t diff = (oldcp[0] ^ newval) | (oldcp[1] ^ newvalXZ); + if (VL_UNLIKELY(diff)) fullFourstateSData(oldp, newval, newvalXZ, bits); + } VL_ATTR_ALWINLINE void chgIData(uint32_t* oldp, IData newval, int bits) { const uint32_t diff = *oldp ^ newval; if (VL_UNLIKELY(diff)) fullIData(oldp, newval, bits); } + VL_ATTR_ALWINLINE void chgFourstateIData(uint32_t* oldp, IData newval, IData newvalXZ, + int bits) { + IData* oldcp = reinterpret_cast(oldp); + const uint32_t diff = (oldcp[0] ^ newval) | (oldcp[1] ^ newvalXZ); + if (VL_UNLIKELY(diff)) fullFourstateIData(oldp, newval, newvalXZ, bits); + } VL_ATTR_ALWINLINE void chgQData(uint32_t* oldp, QData newval, int bits) { QData old; std::memcpy(&old, oldp, sizeof(old)); const uint64_t diff = old ^ newval; if (VL_UNLIKELY(diff)) fullQData(oldp, newval, bits); } - VL_ATTR_ALWINLINE void chgWData(uint32_t* oldp, WDataInP newval, int bits) { - for (int i = 0; i < (bits + 31) / 32; ++i) { + VL_ATTR_ALWINLINE void chgFourstateQData(uint32_t* oldp, QData newval, QData newvalXZ, + int bits) { + QData* oldcp = reinterpret_cast(oldp); + const uint32_t diff = (oldcp[0] ^ newval) | (oldcp[1] ^ newvalXZ); + if (VL_UNLIKELY(diff)) fullFourstateQData(oldp, newval, newvalXZ, bits); + } + VL_ATTR_ALWINLINE void chgWData(uint32_t* oldp, const WDataInP newval, int bits) { + for (int i = 0; i < VL_WORDS_I(bits); ++i) { if (VL_UNLIKELY(oldp[i] ^ newval[i])) { fullWData(oldp, newval, bits); return; } } } + VL_ATTR_ALWINLINE void chgFourstateWData(uint32_t* oldp, const WDataInP newval, int bits) { + for (int i = 0; i < VL_WORDS_I(bits); ++i) { + if (VL_UNLIKELY(oldp[i] ^ newval[i])) { + fullFourstateWData(oldp, newval, bits); + return; + } + } + } VL_ATTR_ALWINLINE void chgEvent(uint32_t* oldp, const VlEventBase* newvalp) { if (newvalp->isTriggered()) fullEvent(oldp, newvalp); } diff --git a/include/verilated_trace_imp.h b/include/verilated_trace_imp.h index 0843f1843..7dfd1da78 100644 --- a/include/verilated_trace_imp.h +++ b/include/verilated_trace_imp.h @@ -555,6 +555,16 @@ void VerilatedTraceBuffer::fullBit(uint32_t* oldp, CData newval) { emitBit(code, newval); } +template <> +void VerilatedTraceBuffer::fullLogic(uint32_t* oldp, CData newval, CData newvalXZ) { + const uint32_t code = oldp - m_sigs_oldvalp; + CData* oldcp = reinterpret_cast(oldp); + oldcp[0] = newval; // Still copy even if not tracing so chg doesn't call full + oldcp[1] = newvalXZ; + if (VL_UNLIKELY(m_sigs_enabledp && !(VL_BITISSET_W(m_sigs_enabledp, code)))) return; + emitLogic(code, newval, newvalXZ); +} + template <> void VerilatedTraceBuffer::fullEvent(uint32_t* oldp, const VlEventBase* newvalp) { const uint32_t code = oldp - m_sigs_oldvalp; @@ -577,6 +587,17 @@ void VerilatedTraceBuffer::fullCData(uint32_t* oldp, CData newval, int emitCData(code, newval, bits); } +template <> +void VerilatedTraceBuffer::fullFourstateCData(uint32_t* oldp, CData newval, + CData newvalXZ, int bits) { + const uint32_t code = oldp - m_sigs_oldvalp; + CData* oldcp = reinterpret_cast(oldp); + oldcp[0] = newval; // Still copy even if not tracing so chg doesn't call full + oldcp[1] = newvalXZ; + if (VL_UNLIKELY(m_sigs_enabledp && !(VL_BITISSET_W(m_sigs_enabledp, code)))) return; + emitFourstateCData(code, newval, newvalXZ, bits); +} + template <> void VerilatedTraceBuffer::fullSData(uint32_t* oldp, SData newval, int bits) { const uint32_t code = oldp - m_sigs_oldvalp; @@ -585,6 +606,17 @@ void VerilatedTraceBuffer::fullSData(uint32_t* oldp, SData newval, int emitSData(code, newval, bits); } +template <> +void VerilatedTraceBuffer::fullFourstateSData(uint32_t* oldp, SData newval, + SData newvalXZ, int bits) { + const uint32_t code = oldp - m_sigs_oldvalp; + SData* oldcp = reinterpret_cast(oldp); + oldcp[0] = newval; // Still copy even if not tracing so chg doesn't call full + oldcp[1] = newvalXZ; + if (VL_UNLIKELY(m_sigs_enabledp && !(VL_BITISSET_W(m_sigs_enabledp, code)))) return; + emitFourstateSData(code, newval, newvalXZ, bits); +} + template <> void VerilatedTraceBuffer::fullIData(uint32_t* oldp, IData newval, int bits) { const uint32_t code = oldp - m_sigs_oldvalp; @@ -593,6 +625,17 @@ void VerilatedTraceBuffer::fullIData(uint32_t* oldp, IData newval, int emitIData(code, newval, bits); } +template <> +void VerilatedTraceBuffer::fullFourstateIData(uint32_t* oldp, IData newval, + IData newvalXZ, int bits) { + const uint32_t code = oldp - m_sigs_oldvalp; + IData* oldcp = reinterpret_cast(oldp); + oldcp[0] = newval; // Still copy even if not tracing so chg doesn't call full + oldcp[1] = newvalXZ; + if (VL_UNLIKELY(m_sigs_enabledp && !(VL_BITISSET_W(m_sigs_enabledp, code)))) return; + emitFourstateIData(code, newval, newvalXZ, bits); +} + template <> void VerilatedTraceBuffer::fullQData(uint32_t* oldp, QData newval, int bits) { const uint32_t code = oldp - m_sigs_oldvalp; @@ -602,13 +645,33 @@ void VerilatedTraceBuffer::fullQData(uint32_t* oldp, QData newval, int } template <> -void VerilatedTraceBuffer::fullWData(uint32_t* oldp, WDataInP newval, int bits) { +void VerilatedTraceBuffer::fullFourstateQData(uint32_t* oldp, QData newval, + QData newvalXZ, int bits) { + const uint32_t code = oldp - m_sigs_oldvalp; + QData* oldcp = reinterpret_cast(oldp); + oldcp[0] = newval; // Still copy even if not tracing so chg doesn't call full + oldcp[1] = newvalXZ; + if (VL_UNLIKELY(m_sigs_enabledp && !(VL_BITISSET_W(m_sigs_enabledp, code)))) return; + emitFourstateQData(code, newval, newvalXZ, bits); +} + +template <> +void VerilatedTraceBuffer::fullWData(uint32_t* oldp, const WDataInP newval, int bits) { const uint32_t code = oldp - m_sigs_oldvalp; for (int i = 0; i < VL_WORDS_I(bits); ++i) oldp[i] = newval[i]; if (VL_UNLIKELY(m_sigs_enabledp && !(VL_BITISSET_W(m_sigs_enabledp, code)))) return; emitWData(code, newval, bits); } +template <> +void VerilatedTraceBuffer::fullFourstateWData(uint32_t* oldp, const WDataInP newval, + int bits) { + const uint32_t code = oldp - m_sigs_oldvalp; + for (int i = 0; i < VL_WORDS_I(bits) * 2; ++i) oldp[i] = newval[i]; + if (VL_UNLIKELY(m_sigs_enabledp && !(VL_BITISSET_W(m_sigs_enabledp, code)))) return; + emitFourstateWData(code, newval, bits); +} + template <> void VerilatedTraceBuffer::fullDouble(uint32_t* oldp, double newval) { const uint32_t code = oldp - m_sigs_oldvalp; diff --git a/include/verilated_types.h b/include/verilated_types.h index 40847b65e..baacd6098 100644 --- a/include/verilated_types.h +++ b/include/verilated_types.h @@ -95,37 +95,37 @@ struct VlWide final { return std::memcmp(m_storage, that.m_storage, N_Words * sizeof(EData)) == 0; } bool operator!=(const VlWide& that) const VL_PURE { return !(*this == that); } - EData& operator[](size_t index) VL_MT_SAFE { return m_storage[index]; } - const EData& operator[](size_t index) const VL_MT_SAFE { return m_storage[index]; } + EData& operator[](size_t index) VL_PURE { return m_storage[index]; } + const EData& operator[](size_t index) const VL_PURE { return m_storage[index]; } VlWide& operator&=(const VlWide& rhs) { - VL_AND_W(N_Words, *this, *this, rhs); + VL_AND_W_TTT(N_Words, *this, *this, rhs); return *this; } VlWide& operator|=(const VlWide& rhs) { - VL_OR_W(N_Words, *this, *this, rhs); + VL_OR_W_TTT(N_Words, *this, *this, rhs); return *this; } VlWide& operator^=(const VlWide& rhs) { - VL_XOR_W(N_Words, *this, *this, rhs); + VL_XOR_W_TTT(N_Words, *this, *this, rhs); return *this; } VlWide& operator+=(const VlWide& rhs) { - VL_ADD_W(N_Words, *this, *this, rhs); + VL_ADD_W_TTT(N_Words, *this, *this, rhs); return *this; } VlWide& operator*=(const VlWide& rhs) { VlWide out{}; - VL_MUL_W(N_Words, out, *this, rhs); + VL_MUL_W_TTT(N_Words, out, *this, rhs); for (size_t i = 0; i < N_Words; ++i) m_storage[i] = out.m_storage[i]; return *this; } // METHODS - EData& at(size_t index) VL_MT_SAFE { return m_storage[index]; } - const EData& at(size_t index) const VL_MT_SAFE { return m_storage[index]; } + EData& at(size_t index) VL_MT_SAFE VL_PURE { return m_storage[index]; } + const EData& at(size_t index) const VL_MT_SAFE VL_PURE { return m_storage[index]; } size_t size() const VL_PURE { return N_Words; } - EData* data() VL_MT_SAFE { return &m_storage[0]; } - const EData* data() const VL_MT_SAFE { return &m_storage[0]; } + EData* data() VL_MT_SAFE VL_PURE { return &m_storage[0]; } + const EData* data() const VL_MT_SAFE VL_PURE { return &m_storage[0]; } inline bool operator<(const VlWide& rhs) const VL_PURE; }; @@ -169,9 +169,28 @@ public: // METHODS EData* datap() const VL_PURE { return m_datap; } operator bool() const VL_PURE { return m_datap; } + EData& operator*() const VL_PURE { return *m_datap; } EData& operator[](size_t index) const VL_PURE { return m_datap[index]; } WDataOutP operator+(size_t index) const VL_PURE { return WDataOutP(m_datap + index); } WDataOutP operator+(int index) const VL_PURE { return WDataOutP(m_datap + index); } + WDataOutP& operator+=(size_t index) { + m_datap += index; + return *this; + } + WDataOutP& operator+=(int index) { + m_datap += index; + return *this; + } + WDataOutP operator-(size_t index) const VL_PURE { return WDataOutP(m_datap - index); } + WDataOutP operator-(int index) const VL_PURE { return WDataOutP(m_datap - index); } + WDataOutP& operator-=(size_t index) { + m_datap -= index; + return *this; + } + WDataOutP& operator-=(int index) { + m_datap -= index; + return *this; + } }; static_assert(sizeof(WDataOutP) == sizeof(EData*), "WDataOutP should be a single pointer"); @@ -208,17 +227,36 @@ public: // METHODS const EData* datap() const VL_PURE { return m_datap; } operator bool() const VL_PURE { return m_datap; } + const EData& operator*() const VL_PURE { return *m_datap; } const EData& operator[](size_t index) const VL_PURE { return m_datap[index]; } WDataInP operator+(size_t index) const VL_PURE { return WDataInP(m_datap + index); } WDataInP operator+(int index) const VL_PURE { return WDataInP(m_datap + index); } + WDataInP& operator+=(size_t index) { + m_datap += index; + return *this; + } + WDataInP& operator+=(int index) { + m_datap += index; + return *this; + } + WDataInP operator-(size_t index) const VL_PURE { return WDataInP(m_datap - index); } + WDataInP operator-(int index) const VL_PURE { return WDataInP(m_datap - index); } + WDataInP& operator-=(size_t index) { + m_datap -= index; + return *this; + } + WDataInP& operator-=(int index) { + m_datap -= index; + return *this; + } }; static_assert(sizeof(WDataInP) == sizeof(EData*), "WDataInP should be a single pointer"); -static int _vl_cmp_w(int words, WDataInP const lwp, WDataInP const rwp) VL_PURE; +static int _vl_cmp_w_TT(int words, WDataInP const lwp, WDataInP const rwp) VL_PURE; template bool VlWide::operator<(const VlWide& rhs) const VL_PURE { - return _vl_cmp_w(N_Words, *this, rhs) < 0; + return _vl_cmp_w_TT(N_Words, *this, rhs) < 0; } //=================================================================== diff --git a/include/verilated_vcd_c.cpp b/include/verilated_vcd_c.cpp index c0ca9281b..07cb4ea77 100644 --- a/include/verilated_vcd_c.cpp +++ b/include/verilated_vcd_c.cpp @@ -635,6 +635,18 @@ void VerilatedVcdBuffer::emitBit(uint32_t code, CData newval) { finishLine(code, wp); } +VL_ATTR_ALWINLINE +void VerilatedVcdBuffer::emitLogic(uint32_t code, CData newval, CData newvalXZ) { + // Don't prefetch suffix as it's a bit too late; + char* wp = m_writep; + if (newval) { + *wp++ = newvalXZ ? 'x' : '1'; + } else { + *wp++ = newvalXZ ? 'z' : '0'; + } + finishLine(code, wp); +} + VL_ATTR_ALWINLINE void VerilatedVcdBuffer::emitCData(uint32_t code, CData newval, int bits) { char* wp = m_writep; @@ -643,6 +655,19 @@ void VerilatedVcdBuffer::emitCData(uint32_t code, CData newval, int bits) { finishLine(code, wp + bits); } +VL_ATTR_ALWINLINE +void VerilatedVcdBuffer::emitFourstateCData(uint32_t code, CData newval, CData newvalXZ, + int bits) { + char* wp = m_writep; + *wp++ = 'b'; + for (int i = bits - 1; i >= 0; --i) { + const CData mask = 1 << i; + *wp++ = (newvalXZ & mask) ? (newval & mask ? 'x' : 'z') + : ('0' | (static_cast(newval >> i) & 1)); + } + finishLine(code, wp); +} + VL_ATTR_ALWINLINE void VerilatedVcdBuffer::emitSData(uint32_t code, SData newval, int bits) { char* wp = m_writep; @@ -651,6 +676,19 @@ void VerilatedVcdBuffer::emitSData(uint32_t code, SData newval, int bits) { finishLine(code, wp + bits); } +VL_ATTR_ALWINLINE +void VerilatedVcdBuffer::emitFourstateSData(uint32_t code, SData newval, SData newvalXZ, + int bits) { + char* wp = m_writep; + *wp++ = 'b'; + for (int i = bits - 1; i >= 0; --i) { + const SData mask = 1 << i; + *wp++ = (newvalXZ & mask) ? (newval & mask ? 'x' : 'z') + : ('0' | (static_cast(newval >> i) & 1)); + } + finishLine(code, wp); +} + VL_ATTR_ALWINLINE void VerilatedVcdBuffer::emitIData(uint32_t code, IData newval, int bits) { char* wp = m_writep; @@ -659,6 +697,19 @@ void VerilatedVcdBuffer::emitIData(uint32_t code, IData newval, int bits) { finishLine(code, wp + bits); } +VL_ATTR_ALWINLINE +void VerilatedVcdBuffer::emitFourstateIData(uint32_t code, IData newval, IData newvalXZ, + int bits) { + char* wp = m_writep; + *wp++ = 'b'; + for (int i = bits - 1; i >= 0; --i) { + const IData mask = 1 << i; + *wp++ = (newvalXZ & mask) ? (newval & mask ? 'x' : 'z') + : ('0' | (static_cast(newval >> i) & 1)); + } + finishLine(code, wp); +} + VL_ATTR_ALWINLINE void VerilatedVcdBuffer::emitQData(uint32_t code, QData newval, int bits) { char* wp = m_writep; @@ -668,7 +719,20 @@ void VerilatedVcdBuffer::emitQData(uint32_t code, QData newval, int bits) { } VL_ATTR_ALWINLINE -void VerilatedVcdBuffer::emitWData(uint32_t code, WDataInP newval, int bits) { +void VerilatedVcdBuffer::emitFourstateQData(uint32_t code, QData newval, QData newvalXZ, + int bits) { + char* wp = m_writep; + *wp++ = 'b'; + for (int i = bits - 1; i >= 0; --i) { + const QData mask = 1 << i; + *wp++ = (newvalXZ & mask) ? (newval & mask ? 'x' : 'z') + : ('0' | (static_cast(newval >> i) & 1)); + } + finishLine(code, wp); +} + +VL_ATTR_ALWINLINE +void VerilatedVcdBuffer::emitWData(uint32_t code, const WDataInP newval, int bits) { int words = VL_WORDS_I(bits); char* wp = m_writep; *wp++ = 'b'; @@ -684,6 +748,32 @@ void VerilatedVcdBuffer::emitWData(uint32_t code, WDataInP newval, int bits) { finishLine(code, wp); } +VL_ATTR_ALWINLINE +void VerilatedVcdBuffer::emitFourstateWData(uint32_t code, const WDataInP newval, int bits) { + char* wp = m_writep; + *wp++ = 'b'; + const int lastIdx = ((bits - 1) / VL_EDATASIZE) << 1; + { + const EData value = newval[lastIdx]; + const EData xz = newval[lastIdx | 1]; + for (int i = (bits - 1) % VL_EDATASIZE; i >= 0; --i) { + const EData mask = 1 << i; + *wp++ = (xz & mask) ? (value & mask ? 'x' : 'z') + : ('0' | (static_cast(value >> i) & 1)); + } + } + for (int w = lastIdx - 2; w >= 0; w -= 2) { + const EData value = newval[w]; + const EData xz = newval[w | 1]; + for (int i = VL_EDATASIZE - 1; i >= 0; --i) { + const EData mask = 1 << i; + *wp++ = (xz & mask) ? (value & mask ? 'x' : 'z') + : ('0' | (static_cast(value >> i) & 1)); + } + } + finishLine(code, wp); +} + VL_ATTR_ALWINLINE void VerilatedVcdBuffer::emitDouble(uint32_t code, double newval) { char* wp = m_writep; diff --git a/include/verilated_vcd_c.h b/include/verilated_vcd_c.h index 931035bed..f98ccd172 100644 --- a/include/verilated_vcd_c.h +++ b/include/verilated_vcd_c.h @@ -247,11 +247,21 @@ class VerilatedVcdBuffer VL_NOT_FINAL { // called from only one place (the full* methods), so always inline them. VL_ATTR_ALWINLINE void emitEvent(uint32_t code); VL_ATTR_ALWINLINE void emitBit(uint32_t code, CData newval); + VL_ATTR_ALWINLINE void emitLogic(uint32_t code, CData newval, CData newvalXZ); VL_ATTR_ALWINLINE void emitCData(uint32_t code, CData newval, int bits); + VL_ATTR_ALWINLINE void emitFourstateCData(uint32_t code, CData newval, CData newvalXZ, + int bits); VL_ATTR_ALWINLINE void emitSData(uint32_t code, SData newval, int bits); + VL_ATTR_ALWINLINE void emitFourstateSData(uint32_t code, SData newval, SData newvalXZ, + int bits); VL_ATTR_ALWINLINE void emitIData(uint32_t code, IData newval, int bits); + VL_ATTR_ALWINLINE void emitFourstateIData(uint32_t code, IData newval, IData newvalXZ, + int bits); VL_ATTR_ALWINLINE void emitQData(uint32_t code, QData newval, int bits); + VL_ATTR_ALWINLINE void emitFourstateQData(uint32_t code, QData newval, QData newvalXZ, + int bits); VL_ATTR_ALWINLINE void emitWData(uint32_t code, WDataInP newval, int bits); + VL_ATTR_ALWINLINE void emitFourstateWData(uint32_t code, WDataInP newval, int bits); VL_ATTR_ALWINLINE void emitDouble(uint32_t code, double newval); }; diff --git a/include/verilated_vpi.cpp b/include/verilated_vpi.cpp index 65afe20f3..d34506092 100644 --- a/include/verilated_vpi.cpp +++ b/include/verilated_vpi.cpp @@ -4466,7 +4466,7 @@ void vpi_get_time(vpiHandle object, p_vpi_time time_p) { if (time_p->type == vpiSimTime) { const QData qtime = VL_TIME_Q(); VlWide<2> itime; - VL_SET_WQ(itime, qtime); + VL_SET_WQ_T(itime, qtime); time_p->low = itime[0]; time_p->high = itime[1]; return; diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index 90a0d3ab4..38401432b 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -104,6 +104,7 @@ set(HEADERS V3Force.h V3FsmDetect.h V3Fork.h + V3Fourstate.h V3FuncOpt.h V3FunctionTraits.h V3Gate.h @@ -280,6 +281,7 @@ set(COMMON_SOURCES V3Force.cpp V3FsmDetect.cpp V3Fork.cpp + V3Fourstate.cpp V3FuncOpt.cpp V3Gate.cpp V3Global.cpp diff --git a/src/Makefile_obj.in b/src/Makefile_obj.in index f5a728063..5053ab171 100644 --- a/src/Makefile_obj.in +++ b/src/Makefile_obj.in @@ -282,6 +282,7 @@ RAW_OBJS_PCH_ASTNOMT = \ V3Force.o \ V3FsmDetect.o \ V3Fork.o \ + V3Fourstate.o \ V3Gate.o \ V3HierBlock.o \ V3Inline.o \ diff --git a/src/V3Ast.cpp b/src/V3Ast.cpp index 8c9d6198e..deffa4101 100644 --- a/src/V3Ast.cpp +++ b/src/V3Ast.cpp @@ -131,6 +131,19 @@ AstNode::AstNode(VNType t, FileLine* fl) editCountInc(); } +int AstNode::widthWords() const { + UASSERT_OBJ(m_dtypep, this, "DType is not set"); + return VL_WORDS_I(width()) * (m_dtypep->isShuffledFourstate() ? 2 : 1); +} +bool AstNode::isQuad() const VL_MT_STABLE { + UASSERT_OBJ(m_dtypep, this, "DType is not set"); + return !m_dtypep->isShuffledFourstate() && (width() > VL_IDATASIZE && width() <= VL_QUADSIZE); +} +bool AstNode::isWide() const VL_MT_STABLE { + UASSERT_OBJ(m_dtypep, this, "DType is not set"); + return m_dtypep->isShuffledFourstate() || (width() > VL_QUADSIZE); +} + AstNode* AstNode::abovep() const { // m_headtailp only valid at beginning or end of list // Avoid supporting at other locations as would require walking @@ -1601,28 +1614,30 @@ void AstNode::dtypeChgWidthSigned(int width, int widthMin, VSigning numeric) { } } -AstNodeDType* AstNode::findBasicDType(VBasicDTypeKwd kwd) const { +AstNodeDType* AstNode::findBasicDType(VBasicDTypeKwd kwd, bool isShuffledFourstate) const { // For 'simple' types we use the global directory. These are all unsized. // More advanced types land under the module/task/etc - return v3Global.rootp()->typeTablep()->findBasicDType(fileline(), kwd); + return v3Global.rootp()->typeTablep()->findBasicDType(fileline(), kwd, isShuffledFourstate); } -AstNodeDType* AstNode::findBitDType(int width, int widthMin, VSigning numeric) const { - return v3Global.rootp()->typeTablep()->findLogicBitDType(fileline(), VBasicDTypeKwd::BIT, - width, widthMin, numeric); +AstNodeDType* AstNode::findBitDType(int width, int widthMin, VSigning numeric, + bool isShuffledFourstate) const { + return v3Global.rootp()->typeTablep()->findLogicBitDType( + fileline(), VBasicDTypeKwd::BIT, width, widthMin, numeric, isShuffledFourstate); } -AstNodeDType* AstNode::findLogicDType(int width, int widthMin, VSigning numeric) const { - return v3Global.rootp()->typeTablep()->findLogicBitDType(fileline(), VBasicDTypeKwd::LOGIC, - width, widthMin, numeric); +AstNodeDType* AstNode::findLogicDType(int width, int widthMin, VSigning numeric, + bool isShuffledFourstate) const { + return v3Global.rootp()->typeTablep()->findLogicBitDType( + fileline(), VBasicDTypeKwd::LOGIC, width, widthMin, numeric, isShuffledFourstate); } -AstNodeDType* AstNode::findLogicRangeDType(const VNumRange& range, int widthMin, - VSigning numeric) const { - return v3Global.rootp()->typeTablep()->findLogicBitDType(fileline(), VBasicDTypeKwd::LOGIC, - range, widthMin, numeric); +AstNodeDType* AstNode::findLogicRangeDType(const VNumRange& range, int widthMin, VSigning numeric, + bool isShuffledFourstate) const { + return v3Global.rootp()->typeTablep()->findLogicBitDType( + fileline(), VBasicDTypeKwd::LOGIC, range, widthMin, numeric, isShuffledFourstate); } -AstNodeDType* AstNode::findBitRangeDType(const VNumRange& range, int widthMin, - VSigning numeric) const { - return v3Global.rootp()->typeTablep()->findLogicBitDType(fileline(), VBasicDTypeKwd::BIT, - range, widthMin, numeric); +AstNodeDType* AstNode::findBitRangeDType(const VNumRange& range, int widthMin, VSigning numeric, + bool isShuffledFourstate) const { + return v3Global.rootp()->typeTablep()->findLogicBitDType( + fileline(), VBasicDTypeKwd::BIT, range, widthMin, numeric, isShuffledFourstate); } AstBasicDType* AstNode::findInsertSameDType(AstBasicDType* nodep) { return v3Global.rootp()->typeTablep()->findInsertSameDType(nodep); diff --git a/src/V3Ast.h b/src/V3Ast.h index 2963987f2..29b22bba2 100644 --- a/src/V3Ast.h +++ b/src/V3Ast.h @@ -644,9 +644,9 @@ public: int widthMinV() const { return v3Global.widthMinUsage() == VWidthMinUsage::VERILOG_WIDTH ? widthMin() : width(); } - int widthWords() const { return VL_WORDS_I(width()); } - bool isQuad() const VL_MT_STABLE { return (width() > VL_IDATASIZE && width() <= VL_QUADSIZE); } - bool isWide() const VL_MT_STABLE { return (width() > VL_QUADSIZE); } + int widthWords() const; + bool isQuad() const VL_MT_STABLE; + bool isWide() const VL_MT_STABLE; inline bool isCHandle() const VL_MT_STABLE; inline bool isDouble() const VL_MT_STABLE; inline bool isSigned() const VL_MT_STABLE; @@ -793,18 +793,20 @@ public: AstNodeDType* findQueueIndexDType() const; AstNodeDType* findStreamDType() const; AstNodeDType* findVoidDType() const; - AstNodeDType* findBitDType(int width, int widthMin, VSigning numeric) const; - AstNodeDType* findLogicDType(int width, int widthMin, VSigning numeric) const; + AstNodeDType* findBitDType(int width, int widthMin, VSigning numeric, + bool isShuffledFourstate = false) const; + AstNodeDType* findLogicDType(int width, int widthMin, VSigning numeric, + bool isShuffledFourstate = false) const; AstNodeDType* findBitOrLogicDType(int width, int widthMin, VSigning numeric, bool isFourstate) const { return isFourstate ? findLogicDType(width, widthMin, numeric) : findBitDType(width, widthMin, numeric); } - AstNodeDType* findLogicRangeDType(const VNumRange& range, int widthMin, - VSigning numeric) const VL_MT_STABLE; - AstNodeDType* findBitRangeDType(const VNumRange& range, int widthMin, - VSigning numeric) const VL_MT_STABLE; - AstNodeDType* findBasicDType(VBasicDTypeKwd kwd) const; + AstNodeDType* findLogicRangeDType(const VNumRange& range, int widthMin, VSigning numeric, + bool isShuffledFourstate = false) const VL_MT_STABLE; + AstNodeDType* findBitRangeDType(const VNumRange& range, int widthMin, VSigning numeric, + bool isShuffledFourstate = false) const VL_MT_STABLE; + AstNodeDType* findBasicDType(VBasicDTypeKwd kwd, bool isShuffledFourstate = false) const; static AstBasicDType* findInsertSameDType(AstBasicDType* nodep); static VCastable computeCastable(const AstNodeDType* toDtp, const AstNodeDType* fromDtp, diff --git a/src/V3AstAttr.h b/src/V3AstAttr.h index afca1bcc2..23198d766 100644 --- a/src/V3AstAttr.h +++ b/src/V3AstAttr.h @@ -2172,9 +2172,11 @@ public: const VNumRange m_nrange; // From AstBasicDType: Numeric msb/lsb (if non-opaque keyword) const VSigning m_numeric; // From AstNodeDType: Node is signed const VBasicDTypeKwd m_keyword; // From AstBasicDType: What keyword created basic type + const bool m_isShuffledFourstate; // Whether it is a shuffled fourstate bool operator==(const VBasicTypeKey& rhs) const { return m_width == rhs.m_width && m_widthMin == rhs.m_widthMin && m_numeric == rhs.m_numeric - && m_keyword == rhs.m_keyword && m_nrange == rhs.m_nrange; + && m_keyword == rhs.m_keyword && m_nrange == rhs.m_nrange + && m_isShuffledFourstate == rhs.m_isShuffledFourstate; } bool operator<(const VBasicTypeKey& rhs) const { if ((m_width < rhs.m_width)) return true; @@ -2187,15 +2189,17 @@ public: if (!(m_keyword == rhs.m_keyword)) return false; // lhs > rhs if ((m_nrange < rhs.m_nrange)) return true; if (!(m_nrange == rhs.m_nrange)) return false; // lhs > rhs + if (!m_isShuffledFourstate && rhs.m_isShuffledFourstate) return true; return false; } VBasicTypeKey(int width, int widthMin, VSigning numeric, VBasicDTypeKwd kwd, - const VNumRange& nrange) + const VNumRange& nrange, bool isShuffledFourstate) : m_width{width} , m_widthMin{widthMin} , m_nrange{nrange} , m_numeric{numeric} - , m_keyword{kwd} {} + , m_keyword{kwd} + , m_isShuffledFourstate{isShuffledFourstate} {} ~VBasicTypeKey() = default; }; diff --git a/src/V3AstNodeDType.h b/src/V3AstNodeDType.h index fcb2183ba..c75dda179 100644 --- a/src/V3AstNodeDType.h +++ b/src/V3AstNodeDType.h @@ -158,7 +158,9 @@ public: bool isSigned() const VL_MT_STABLE { return m_numeric.isSigned(); } bool isNosign() const VL_MT_SAFE { return m_numeric.isNosign(); } VSigning numeric() const VL_MT_STABLE { return m_numeric; } - int widthWords() const VL_MT_STABLE { return VL_WORDS_I(width()); } + int widthWords() const VL_MT_STABLE { + return VL_WORDS_I(width()) * (isShuffledFourstate() ? 2 : 1); + } int widthMin() const VL_MT_STABLE { // If sized, the size, // if unsized the min digits to represent it return m_widthMin ? m_widthMin : m_width; @@ -183,6 +185,7 @@ public: // Represents a C++ LiteralType? (can be constexpr) bool isLiteralType() const VL_MT_STABLE; virtual bool isDynamicallySized() const { return false; } + virtual bool isShuffledFourstate() const VL_MT_STABLE { return false; } private: class CTypeRecursed; @@ -407,37 +410,47 @@ class AstBasicDType final : public AstNodeDType { struct Members final { VBasicDTypeKwd m_keyword; // (also in VBasicTypeKey) What keyword created basic type VNumRange m_nrange; // (also in VBasicTypeKey) Numeric msb/lsb (if non-opaque keyword) + bool m_isShuffledFourstate; // (also in VBasicTypeKey) whether it is a shuffled four-state + // value (forty shuffled bits will be represented as 80bits in + // 128 bits VlWide) - shuffled implies wide that stores values + // as described in: + // IEEE 1800-2023 38. VPI routine definitions + // Figure 38-8 - s_vpi_vecval structure definition bool operator==(const Members& rhs) const { - return rhs.m_keyword == m_keyword && rhs.m_nrange == m_nrange; + return rhs.m_keyword == m_keyword && rhs.m_nrange == m_nrange + && rhs.m_isShuffledFourstate == m_isShuffledFourstate; } } m; // See also in AstNodeDType: m_width, m_widthMin, m_numeric(issigned) public: - AstBasicDType(FileLine* fl, VBasicDTypeKwd kwd, const VSigning& signst = VSigning::NOSIGN) + AstBasicDType(FileLine* fl, VBasicDTypeKwd kwd, const VSigning& signst = VSigning::NOSIGN, + bool isShuffledFourstate = false) : ASTGEN_SUPER_BasicDType(fl) { - init(kwd, signst, 0, -1, nullptr); + init(kwd, signst, 0, -1, nullptr, isShuffledFourstate); } - AstBasicDType(FileLine* fl, VFlagLogicPacked, int wantwidth) + AstBasicDType(FileLine* fl, VFlagLogicPacked, int wantwidth, bool isShuffledFourstate = false) : ASTGEN_SUPER_BasicDType(fl) { - init(VBasicDTypeKwd::LOGIC, VSigning::NOSIGN, wantwidth, -1, nullptr); + init(VBasicDTypeKwd::LOGIC, VSigning::NOSIGN, wantwidth, -1, nullptr, isShuffledFourstate); } - AstBasicDType(FileLine* fl, VFlagBitPacked, int wantwidth) + AstBasicDType(FileLine* fl, VFlagBitPacked, int wantwidth, bool isShuffledFourstate = false) : ASTGEN_SUPER_BasicDType(fl) { - init(VBasicDTypeKwd::BIT, VSigning::NOSIGN, wantwidth, -1, nullptr); + init(VBasicDTypeKwd::BIT, VSigning::NOSIGN, wantwidth, -1, nullptr, isShuffledFourstate); } - AstBasicDType(FileLine* fl, VBasicDTypeKwd kwd, VSigning numer, int wantwidth, int widthmin) + AstBasicDType(FileLine* fl, VBasicDTypeKwd kwd, VSigning numer, int wantwidth, int widthmin, + bool isShuffledFourstate = false) : ASTGEN_SUPER_BasicDType(fl) { - init(kwd, numer, wantwidth, widthmin, nullptr); + init(kwd, numer, wantwidth, widthmin, nullptr, isShuffledFourstate); } - AstBasicDType(FileLine* fl, VBasicDTypeKwd kwd, VSigning numer, VNumRange range, int widthmin) + AstBasicDType(FileLine* fl, VBasicDTypeKwd kwd, VSigning numer, VNumRange range, int widthmin, + bool isShuffledFourstate = false) : ASTGEN_SUPER_BasicDType(fl) { - init(kwd, numer, range.elements(), widthmin, nullptr); + init(kwd, numer, range.elements(), widthmin, nullptr, isShuffledFourstate); m.m_nrange = range; // as init() presumes lsb==0, but range.lsb() might not be } // See also addRange in verilog.y private: void init(VBasicDTypeKwd kwd, VSigning numer, int wantwidth, int wantwidthmin, - AstRange* rangep); + AstRange* rangep, bool isShuffledFourstate); public: ASTGEN_MEMBERS_AstBasicDType; @@ -521,6 +534,7 @@ public: void cvtRangeConst(); // Convert to smaller representation bool isCompound() const override { return isString(); } bool isIntegralOrPacked() const override { return keyword().isIntNumeric(); } + bool isShuffledFourstate() const VL_MT_STABLE override { return m.m_isShuffledFourstate; } }; class AstBracketArrayDType final : public AstNodeDType { // Associative/Queue/Normal array data type, ie "[dtype_or_expr]" diff --git a/src/V3AstNodeExpr.h b/src/V3AstNodeExpr.h index e8f065861..9c64dfb04 100644 --- a/src/V3AstNodeExpr.h +++ b/src/V3AstNodeExpr.h @@ -487,6 +487,8 @@ private: VSelfPointerText m_selfPointer = VSelfPointerText{VSelfPointerText::Empty()}; // Output code object // pointer (e.g.: 'this') + bool m_fourstateXZPart : 1; // If references four-state shuffled var true for XZ part and + // false for value part protected: AstNodeVarRef(VNType t, FileLine* fl, AstVar* varp, const VAccess& access) : AstNodeExpr{t, fl} @@ -516,6 +518,8 @@ public: AstNodeModule* classOrPackagep() const { return m_classOrPackagep; } void classOrPackagep(AstNodeModule* nodep) { m_classOrPackagep = nodep; } static AstNodeVarRef* varRefLValueRecurse(AstNode* nodep); + void fourstateXZPart(bool xz) { m_fourstateXZPart = xz; } + bool fourstateXZPart() const { return m_fourstateXZPart; } }; // === Concrete node types ===================================================== @@ -1675,6 +1679,27 @@ public: bool sameNode(const AstNode* /*samep*/) const override { return true; } bool isSystemFunc() const override { return true; } }; +class AstFourstateExpr final : public AstNodeExpr { + // When AstNode wants a value as an child and that value is a splitted four-state value (so, it + // has value and xz part) this node shall be used to put them both there + // @astgen op1 := valuep : AstNodeExpr // value part of a four-state expression + // @astgen op2 := xzp : AstNodeExpr // xz part of a four-state expression +public: + AstFourstateExpr(FileLine* fl, AstNodeExpr* const valuePartp, AstNodeExpr* const xzPartp) + : ASTGEN_SUPER_FourstateExpr(fl) { + UASSERT_OBJ(valuePartp->width() == xzPartp->width(), this, + "Value and XZ part shall have same width but they have: " + << valuePartp->width() << " and " << xzPartp->width()); + valuep(valuePartp); + xzp(xzPartp); + dtypeSetLogicUnsized(valuePartp->width(), valuePartp->dtypep()->widthMin(), + valuePartp->dtypep()->numeric()); + } + ASTGEN_MEMBERS_AstFourstateExpr; + string emitVerilog() override { V3ERROR_NA_RETURN(""); } + string emitC() override { V3ERROR_NA_RETURN(""); } + bool cleanOut() const override { return true; } +}; class AstFuture final : public AstNodeExpr { // Verilog $future_gclk // @astgen op1 := exprp : AstNodeExpr @@ -3101,7 +3126,7 @@ public: void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override { out.opConcat(lhs, rhs); } - string emitC() override { return "VL_CONCAT_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri)"; } + string emitC() override { return "VL_CONCAT_%nq%lq%rq_%nf%lf%rf(%nw,%lw,%rw, %P, %li, %ri)"; } string emitSMT() const override { return "(concat %l %r)"; } bool cleanOut() const override { return true; } bool cleanLhs() const override { return true; } @@ -3143,7 +3168,7 @@ public: out.opDiv(lhs, rhs); } string emitVerilog() override { return "%k(%l %f/ %r)"; } - string emitC() override { return "VL_DIV_%nq%lq%rq(%lw, %P, %li, %ri)"; } + string emitC() override { return "VL_DIV_%nq%lq%rq_%nf%lf%rf(%lw, %P, %li, %ri)"; } string emitSMT() const override { return "(bvudiv %l %r)"; } bool emitCheckMaxWords() override { return true; } bool cleanOut() const override { return false; } @@ -3186,7 +3211,7 @@ public: out.opDivS(lhs, rhs); } string emitVerilog() override { return "%k(%l %f/ %r)"; } - string emitC() override { return "VL_DIVS_%nq%lq%rq(%lw, %P, %li, %ri)"; } + string emitC() override { return "VL_DIVS_%nq%lq%rq_%nf%lf%rf(%lw, %P, %li, %ri)"; } string emitSMT() const override { return "(bvsdiv %l %r)"; } bool emitCheckMaxWords() override { return true; } bool cleanOut() const override { return false; } @@ -3221,7 +3246,7 @@ public: if (v3Global.opt.fourstate()) { V3ERROR_NA_RETURN(""); } else { - return "VL_EQ_%lq(%lW, %P, %li, %ri)"; + return "VL_EQ_%lq_%lf%rf(%lW, %P, %li, %ri)"; } } string emitSMT() const override { return "(__Vbv (= %l %r))"; } @@ -3334,7 +3359,7 @@ public: out.opGt(lhs, rhs); } string emitVerilog() override { return "%k(%l %f> %r)"; } - string emitC() override { return "VL_GT_%lq(%lW, %P, %li, %ri)"; } + string emitC() override { return "VL_GT_%lq_%lf%rf(%lW, %P, %li, %ri)"; } string emitSMT() const override { return "(__Vbv (bvugt %l %r))"; } string emitSimpleOperator() override { return ">"; } bool cleanOut() const override { return true; } @@ -3397,7 +3422,7 @@ public: out.opGtS(lhs, rhs); } string emitVerilog() override { return "%k(%l %f> %r)"; } - string emitC() override { return "VL_GTS_%nq%lq%rq(%lw, %P, %li, %ri)"; } + string emitC() override { return "VL_GTS_%nq%lq%rq_%lf%rf(%lw, %P, %li, %ri)"; } string emitSMT() const override { return "(__Vbv (bvsgt %l %r))"; } string emitSimpleOperator() override { return ""; } bool cleanOut() const override { return true; } @@ -3419,7 +3444,7 @@ public: out.opGte(lhs, rhs); } string emitVerilog() override { return "%k(%l %f>= %r)"; } - string emitC() override { return "VL_GTE_%lq(%lW, %P, %li, %ri)"; } + string emitC() override { return "VL_GTE_%lq_%lf%rf(%lW, %P, %li, %ri)"; } string emitSMT() const override { return "(__Vbv (bvuge %l %r))"; } string emitSimpleOperator() override { return ">="; } bool cleanOut() const override { return true; } @@ -3482,7 +3507,7 @@ public: out.opGteS(lhs, rhs); } string emitVerilog() override { return "%k(%l %f>= %r)"; } - string emitC() override { return "VL_GTES_%nq%lq%rq(%lw, %P, %li, %ri)"; } + string emitC() override { return "VL_GTES_%nq%lq%rq_%lf%rf(%lw, %P, %li, %ri)"; } string emitSMT() const override { return "(__Vbv (bvsge %l %r))"; } string emitSimpleOperator() override { return ""; } bool cleanOut() const override { return true; } @@ -3504,7 +3529,7 @@ public: out.opLogAnd(lhs, rhs); } string emitVerilog() override { return "%k(%l %f&& %r)"; } - string emitC() override { return "VL_LOGAND_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri)"; } + string emitC() override { V3ERROR_NA_RETURN(""); } string emitSMT() const override { return "(bvand %l %r)"; } string emitSimpleOperator() override { return "&&"; } bool cleanOut() const override { return true; } @@ -3526,7 +3551,7 @@ public: out.opLogIf(lhs, rhs); } string emitVerilog() override { return "%k(%l %f-> %r)"; } - string emitC() override { return "VL_LOGIF_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri)"; } + string emitC() override { V3ERROR_NA_RETURN(""); } string emitSMT() const override { return "(__Vbv (=> (__Vbool %l) (__Vbool %r)))"; } string emitSimpleOperator() override { return "->"; } bool cleanOut() const override { return true; } @@ -3548,7 +3573,7 @@ public: out.opLogOr(lhs, rhs); } string emitVerilog() override { return "%k(%l %f|| %r)"; } - string emitC() override { return "VL_LOGOR_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri)"; } + string emitC() override { V3ERROR_NA_RETURN(""); } string emitSMT() const override { return "(bvor %l %r)"; } string emitSimpleOperator() override { return "||"; } bool cleanOut() const override { return true; } @@ -3570,7 +3595,7 @@ public: out.opLt(lhs, rhs); } string emitVerilog() override { return "%k(%l %f< %r)"; } - string emitC() override { return "VL_LT_%lq(%lW, %P, %li, %ri)"; } + string emitC() override { return "VL_LT_%lq_%lf%rf(%lW, %P, %li, %ri)"; } string emitSMT() const override { return "(__Vbv (bvult %l %r))"; } string emitSimpleOperator() override { return "<"; } bool cleanOut() const override { return true; } @@ -3633,7 +3658,7 @@ public: out.opLtS(lhs, rhs); } string emitVerilog() override { return "%k(%l %f< %r)"; } - string emitC() override { return "VL_LTS_%nq%lq%rq(%lw, %P, %li, %ri)"; } + string emitC() override { return "VL_LTS_%nq%lq%rq_%lf%rf(%lw, %P, %li, %ri)"; } string emitSMT() const override { return "(__Vbv (bvslt %l %r))"; } string emitSimpleOperator() override { return ""; } bool cleanOut() const override { return true; } @@ -3655,7 +3680,7 @@ public: out.opLte(lhs, rhs); } string emitVerilog() override { return "%k(%l %f<= %r)"; } - string emitC() override { return "VL_LTE_%lq(%lW, %P, %li, %ri)"; } + string emitC() override { return "VL_LTE_%lq_%lf%rf(%lW, %P, %li, %ri)"; } string emitSMT() const override { return "(__Vbv (bvule %l %r))"; } string emitSimpleOperator() override { return "<="; } bool cleanOut() const override { return true; } @@ -3718,7 +3743,7 @@ public: out.opLteS(lhs, rhs); } string emitVerilog() override { return "%k(%l %f<= %r)"; } - string emitC() override { return "VL_LTES_%nq%lq%rq(%lw, %P, %li, %ri)"; } + string emitC() override { return "VL_LTES_%nq%lq%rq_%lf%rf(%lw, %P, %li, %ri)"; } string emitSMT() const override { return "(__Vbv (bvsle %l %r))"; } string emitSimpleOperator() override { return ""; } bool cleanOut() const override { return true; } @@ -3740,7 +3765,7 @@ public: out.opModDiv(lhs, rhs); } string emitVerilog() override { return "%k(%l %f%% %r)"; } - string emitC() override { return "VL_MODDIV_%nq%lq%rq(%lw, %P, %li, %ri)"; } + string emitC() override { return "VL_MODDIV_%nq%lq%rq_%nf%lf%rf(%lw, %P, %li, %ri)"; } string emitSMT() const override { return "(bvurem %l %r)"; } bool emitCheckMaxWords() override { return true; } bool cleanOut() const override { return false; } @@ -3762,7 +3787,7 @@ public: out.opModDivS(lhs, rhs); } string emitVerilog() override { return "%k(%l %f%% %r)"; } - string emitC() override { return "VL_MODDIVS_%nq%lq%rq(%lw, %P, %li, %ri)"; } + string emitC() override { return "VL_MODDIVS_%nq%lq%rq_%nf%lf%rf(%lw, %P, %li, %ri)"; } string emitSMT() const override { return "(bvsmod %l %r)"; } bool emitCheckMaxWords() override { return true; } bool cleanOut() const override { return false; } @@ -3794,7 +3819,7 @@ public: if (v3Global.opt.fourstate()) { V3ERROR_NA_RETURN(""); } else { - return "VL_NEQ_%lq(%lW, %P, %li, %ri)"; + return "VL_NEQ_%lq_%lf%rf(%lW, %P, %li, %ri)"; } } string emitSimpleOperator() override { @@ -3929,9 +3954,17 @@ public: if (const AstConst* const constp = VN_CAST(rhsp, Const)) { if (constp->num().isFourState() || (constp->dtypep()->isSigned() && constp->num().isNegative())) { - dtypeSetLogicSized(lhsp->width(), VSigning::UNSIGNED); // V3Width warns + if (lhsp->dtypep() && !lhsp->dtypep()->isFourstate()) { + dtypeSetBitSized(lhsp->width(), VSigning::UNSIGNED); // V3Width warns + } else { + dtypeSetLogicSized(lhsp->width(), VSigning::UNSIGNED); // V3Width warns + } } else { - dtypeSetLogicSized(lhsp->width() * constp->toSInt(), VSigning::UNSIGNED); + if (lhsp->dtypep() && !lhsp->dtypep()->isFourstate()) { + dtypeSetBitSized(lhsp->width() * constp->toSInt(), VSigning::UNSIGNED); + } else { + dtypeSetLogicSized(lhsp->width() * constp->toSInt(), VSigning::UNSIGNED); + } } } } @@ -3943,7 +3976,7 @@ public: out.opRepl(lhs, rhs); } string emitVerilog() override { return "%f{%r{%k%l}}"; } - string emitC() override { return "VL_REPLICATE_%nq%lq%rq(%lw, %P, %li, %ri)"; } + string emitC() override { return "VL_REPLICATE_%nq%lq%rq_%nf%lf%rf(%lw, %P, %li, %ri)"; } string emitSMT() const override { return "((_ repeat " + cvtToStr(width() / lhsp()->width()) + ") %l)"; } @@ -4106,7 +4139,15 @@ public: : ASTGEN_SUPER_Sel(fl, fromp, lsbp) , m_declElWidth{1} , m_widthConst{bitwidth} { - dtypeSetLogicSized(bitwidth, VSigning::UNSIGNED); + if (const AstNodeDType* const dtypep = fromp->dtypep()) { + if (dtypep->isFourstate()) { + dtypeSetLogicSized(bitwidth, VSigning::UNSIGNED); + } else { + dtypeSetBitSized(bitwidth, VSigning::UNSIGNED); + } + } else { + dtypeSetLogicSized(bitwidth, VSigning::UNSIGNED); + } } AstSel(FileLine* fl, AstNodeExpr* fromp, int lsb, int bitwidth) : ASTGEN_SUPER_Sel(fl, fromp, new AstConst(fl, lsb)) // Need () constructor @@ -4122,9 +4163,9 @@ public: } string emitVerilog() override { V3ERROR_NA_RETURN(""); } string emitC() override { - return widthConst() == 1 ? "VL_BITSEL_%nq%lq%rqI(%lw, %P, %li, %ri)" - : isWide() ? "VL_SEL_%nq%lq%rqI(%nw, %lw, %P, %li, %ri, %nw)" - : "VL_SEL_%nq%lq%rqI(%lw, %P, %li, %ri, %nw)"; + return widthConst() == 1 ? "VL_BITSEL_%nq%lq%rqI_%nf%lf%rfT(%lw, %P, %li, %ri)" + : isWide() ? "VL_SEL_%nq%lq%rqI_%nf%lf%rfT(%nw, %lw, %P, %li, %ri, %nw)" + : "VL_SEL_%nq%lq%rqI_%nf%lf%rfT(%lw, %P, %li, %ri, %nw)"; } string emitSMT() const override { return "((_ extract %t %r) %l)"; } bool cleanOut() const override { return false; } @@ -4171,7 +4212,7 @@ public: out.opShiftL(lhs, rhs); } string emitVerilog() override { return "%k(%l %f<< %r)"; } - string emitC() override { return "VL_SHIFTL_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri)"; } + string emitC() override { return "VL_SHIFTL_%nq%lq%rq_%nf%lf%rf(%nw,%lw,%rw, %P, %li, %ri)"; } string emitSMT() const override { return "(bvshl %l %r)"; } string emitSimpleOperator() override { return (rhsp()->isWide() || rhsp()->isQuad()) ? "" : "<<"; @@ -4188,14 +4229,25 @@ class AstShiftLOvr final : public AstNodeBiop { public: AstShiftLOvr(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp, int setwidth = 0) : ASTGEN_SUPER_ShiftLOvr(fl, lhsp, rhsp) { - if (setwidth) dtypeSetLogicSized(setwidth, VSigning::UNSIGNED); + if (lhsp->dtypep() && rhsp->dtypep() && !lhsp->dtypep()->isFourstate() + && !rhsp->dtypep()->isFourstate()) { + dtypeSetBitUnsized(setwidth ? setwidth : lhsp->width(), + setwidth ? 0 : lhsp->dtypep()->widthMin(), + lhsp->dtypep()->numeric()); + } else if (lhsp->dtypep()) { + dtypeSetLogicUnsized(setwidth ? setwidth : lhsp->width(), + setwidth ? 0 : lhsp->dtypep()->widthMin(), + lhsp->dtypep()->numeric()); + } else { + dtypeSetLogicSized(setwidth, VSigning::UNSIGNED); + } } ASTGEN_MEMBERS_AstShiftLOvr; void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override { out.opShiftL(lhs, rhs); } string emitVerilog() override { return "%k(%l %f<< %r)"; } - string emitC() override { return "VL_SHIFTL_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri)"; } + string emitC() override { return "VL_SHIFTL_%nq%lq%rq_%nf%lf%rf(%nw,%lw,%rw, %P, %li, %ri)"; } string emitSimpleOperator() override { return ""; } bool cleanOut() const override { return false; } bool cleanLhs() const override { return false; } @@ -4226,7 +4278,7 @@ public: out.opShiftR(lhs, rhs); } string emitVerilog() override { return "%k(%l %f>> %r)"; } - string emitC() override { return "VL_SHIFTR_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri)"; } + string emitC() override { return "VL_SHIFTR_%nq%lq%rq_%nf%lf%rf(%nw,%lw,%rw, %P, %li, %ri)"; } string emitSMT() const override { return "(bvlshr %l %r)"; } string emitSimpleOperator() override { return (rhsp()->isWide() || rhsp()->isQuad()) ? "" : ">>"; @@ -4244,14 +4296,25 @@ class AstShiftROvr final : public AstNodeBiop { public: AstShiftROvr(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp, int setwidth = 0) : ASTGEN_SUPER_ShiftROvr(fl, lhsp, rhsp) { - if (setwidth) dtypeSetLogicSized(setwidth, VSigning::UNSIGNED); + if (lhsp->dtypep() && rhsp->dtypep() && !lhsp->dtypep()->isFourstate() + && !rhsp->dtypep()->isFourstate()) { + dtypeSetBitUnsized(setwidth ? setwidth : lhsp->width(), + setwidth ? 0 : lhsp->dtypep()->widthMin(), + lhsp->dtypep()->numeric()); + } else if (lhsp->dtypep()) { + dtypeSetLogicUnsized(setwidth ? setwidth : lhsp->width(), + setwidth ? 0 : lhsp->dtypep()->widthMin(), + lhsp->dtypep()->numeric()); + } else { + dtypeSetLogicSized(setwidth, VSigning::UNSIGNED); + } } ASTGEN_MEMBERS_AstShiftROvr; void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override { out.opShiftR(lhs, rhs); } string emitVerilog() override { return "%k(%l %f>> %r)"; } - string emitC() override { return "VL_SHIFTR_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri)"; } + string emitC() override { return "VL_SHIFTR_%nq%lq%rq_%nf%lf%rf(%nw,%lw,%rw, %P, %li, %ri)"; } string emitSimpleOperator() override { return ""; } bool cleanOut() const override { return true; } bool cleanLhs() const override { return true; } @@ -4268,7 +4331,18 @@ public: AstShiftRS(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp, int setwidth = 0) : ASTGEN_SUPER_ShiftRS(fl, lhsp, rhsp) { // Important that widthMin be correct, as opExtend requires it after V3Expand - if (setwidth) dtypeSetLogicSized(setwidth, VSigning::SIGNED); + if (lhsp->dtypep() && rhsp->dtypep() && !lhsp->dtypep()->isFourstate() + && !rhsp->dtypep()->isFourstate()) { + dtypeSetBitUnsized(setwidth ? setwidth : lhsp->width(), + setwidth ? 0 : lhsp->dtypep()->widthMin(), + lhsp->dtypep()->numeric()); + } else if (lhsp->dtypep()) { + dtypeSetLogicUnsized(setwidth ? setwidth : lhsp->width(), + setwidth ? 0 : lhsp->dtypep()->widthMin(), + lhsp->dtypep()->numeric()); + } else { + dtypeSetLogicSized(setwidth, VSigning::UNSIGNED); + } } ASTGEN_MEMBERS_AstShiftRS; void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override { @@ -4276,7 +4350,7 @@ public: } string emitVerilog() override { return "%k(%l %f>>> %r)"; } string emitSMT() const override { return "(bvashr %l %r)"; } - string emitC() override { return "VL_SHIFTRS_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri)"; } + string emitC() override { return "VL_SHIFTRS_%nq%lq%rq_%nf%lf%rf(%nw,%lw,%rw, %P, %li, %ri)"; } string emitSimpleOperator() override { return ""; } bool cleanOut() const override { return false; } bool cleanLhs() const override { return true; } @@ -4293,14 +4367,25 @@ public: AstShiftRSOvr(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp, int setwidth = 0) : ASTGEN_SUPER_ShiftRSOvr(fl, lhsp, rhsp) { // Important that widthMin be correct, as opExtend requires it after V3Expand - if (setwidth) dtypeSetLogicSized(setwidth, VSigning::SIGNED); + if (lhsp->dtypep() && rhsp->dtypep() && !lhsp->dtypep()->isFourstate() + && !rhsp->dtypep()->isFourstate()) { + dtypeSetBitUnsized(setwidth ? setwidth : lhsp->width(), + setwidth ? 0 : lhsp->dtypep()->widthMin(), + lhsp->dtypep()->numeric()); + } else if (lhsp->dtypep()) { + dtypeSetLogicUnsized(setwidth ? setwidth : lhsp->width(), + setwidth ? 0 : lhsp->dtypep()->widthMin(), + lhsp->dtypep()->numeric()); + } else { + dtypeSetLogicSized(setwidth, VSigning::UNSIGNED); + } } ASTGEN_MEMBERS_AstShiftRSOvr; void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override { out.opShiftRS(lhs, rhs, lhsp()->widthMinV()); } string emitVerilog() override { return "%k(%l %f>>> %r)"; } - string emitC() override { return "VL_SHIFTRS_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri)"; } + string emitC() override { return "VL_SHIFTRS_%nq%lq%rq_%nf%lf%rf(%nw,%lw,%rw, %P, %li, %ri)"; } string emitSimpleOperator() override { return ""; } bool cleanOut() const override { return false; } bool cleanLhs() const override { return true; } @@ -4321,7 +4406,7 @@ public: out.opSub(lhs, rhs); } string emitVerilog() override { return "%k(%l %f- %r)"; } - string emitC() override { return "VL_SUB_%lq(%lW, %P, %li, %ri)"; } + string emitC() override { return "VL_SUB_%lq_%nf%lf%rf(%lW, %P, %li, %ri)"; } string emitSMT() const override { return "(bvsub %l %r)"; } string emitSimpleOperator() override { return "-"; } bool cleanOut() const override { return false; } @@ -4394,7 +4479,7 @@ public: out.opEq(lhs, rhs); } string emitVerilog() override { return "%k(%l %f== %r)"; } - string emitC() override { return "VL_EQ_%lq(%lW, %P, %li, %ri)"; } + string emitC() override { return "VL_EQ_%lq_%lf%rf(%lW, %P, %li, %ri)"; } string emitSMT() const override { return "(__Vbv (= %l %r))"; } string emitSimpleOperator() override { return "=="; } bool cleanOut() const override { return true; } @@ -4415,7 +4500,7 @@ public: out.opCaseEq(lhs, rhs); } string emitVerilog() override { return "%k(%l %f=== %r)"; } - string emitC() override { return "VL_EQ_%lq(%lW, %P, %li, %ri)"; } + string emitC() override { return "VL_EQ_%lq_%lf%rf(%lW, %P, %li, %ri)"; } string emitSimpleOperator() override { return "=="; } bool cleanOut() const override { return true; } bool cleanLhs() const override { return true; } @@ -4496,7 +4581,7 @@ public: out.opLogEq(lhs, rhs); } string emitVerilog() override { return "%k(%l %f<-> %r)"; } - string emitC() override { return "VL_LOGEQ_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri)"; } + string emitC() override { V3ERROR_NA_RETURN(""); } string emitSMT() const override { return "(bvxnor %l %r)"; } string emitSimpleOperator() override { return "<->"; } bool cleanOut() const override { return true; } @@ -4524,7 +4609,7 @@ public: out.opNeq(lhs, rhs); } string emitVerilog() override { return "%k(%l %f!= %r)"; } - string emitC() override { return "VL_NEQ_%lq(%lW, %P, %li, %ri)"; } + string emitC() override { return "VL_NEQ_%lq_%lf%rf(%lW, %P, %li, %ri)"; } string emitSimpleOperator() override { return "!="; } string emitSMT() const override { return "(__Vbv (not (= %l %r)))"; } bool cleanOut() const override { return true; } @@ -4545,7 +4630,7 @@ public: out.opCaseNeq(lhs, rhs); } string emitVerilog() override { return "%k(%l %f!== %r)"; } - string emitC() override { return "VL_NEQ_%lq(%lW, %P, %li, %ri)"; } + string emitC() override { return "VL_NEQ_%lq_%lf%rf(%lW, %P, %li, %ri)"; } string emitSimpleOperator() override { return "!="; } bool cleanOut() const override { return true; } bool cleanLhs() const override { return true; } @@ -4628,7 +4713,7 @@ public: out.opAdd(lhs, rhs); } string emitVerilog() override { return "%k(%l %f+ %r)"; } - string emitC() override { return "VL_ADD_%lq(%lW, %P, %li, %ri)"; } + string emitC() override { return "VL_ADD_%lq_%nf%lf%rf(%lW, %P, %li, %ri)"; } string emitSMT() const override { return "(bvadd %l %r)"; } string emitSimpleOperator() override { return "+"; } bool cleanOut() const override { return false; } @@ -4670,7 +4755,7 @@ public: out.opAnd(lhs, rhs); } string emitVerilog() override { return "%k(%l %f& %r)"; } - string emitC() override { return "VL_AND_%lq(%lW, %P, %li, %ri)"; } + string emitC() override { return "VL_AND_%lq_%nf%lf%rf(%lW, %P, %li, %ri)"; } string emitSMT() const override { return "(bvand %l %r)"; } string emitSimpleOperator() override { return "&"; } bool cleanOut() const override { V3ERROR_NA_RETURN(false); } @@ -4692,7 +4777,7 @@ public: out.opMul(lhs, rhs); } string emitVerilog() override { return "%k(%l %f* %r)"; } - string emitC() override { return "VL_MUL_%lq(%lW, %P, %li, %ri)"; } + string emitC() override { return "VL_MUL_%lq_%nf%lf%rf(%lW, %P, %li, %ri)"; } string emitSMT() const override { return "(bvmul %l %r)"; } string emitSimpleOperator() override { return "*"; } bool cleanOut() const override { return false; } @@ -4735,7 +4820,7 @@ public: out.opMulS(lhs, rhs); } string emitVerilog() override { return "%k(%l %f* %r)"; } - string emitC() override { return "VL_MULS_%nq%lq%rq(%lw, %P, %li, %ri)"; } + string emitC() override { return "VL_MULS_%nq%lq%rq_%nf%lf%rf(%lw, %P, %li, %ri)"; } string emitSMT() const override { return "(bvmul %l %r)"; } string emitSimpleOperator() override { return ""; } bool emitCheckMaxWords() override { return true; } @@ -4759,7 +4844,7 @@ public: out.opOr(lhs, rhs); } string emitVerilog() override { return "%k(%l %f| %r)"; } - string emitC() override { return "VL_OR_%lq(%lW, %P, %li, %ri)"; } + string emitC() override { return "VL_OR_%lq_%nf%lf%rf(%lW, %P, %li, %ri)"; } string emitSMT() const override { return "(bvor %l %r)"; } string emitSimpleOperator() override { return "|"; } bool cleanOut() const override { V3ERROR_NA_RETURN(false); } @@ -4781,7 +4866,7 @@ public: out.opXor(lhs, rhs); } string emitVerilog() override { return "%k(%l %f^ %r)"; } - string emitC() override { return "VL_XOR_%lq(%lW, %P, %li, %ri)"; } + string emitC() override { return "VL_XOR_%lq_%nf%lf%rf(%lW, %P, %li, %ri)"; } string emitSMT() const override { return "(bvxor %l %r)"; } string emitSimpleOperator() override { return "^"; } bool cleanOut() const override { return false; } // Lclean && Rclean @@ -4969,7 +5054,7 @@ public: void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override { out.opAssign(lhs); } - string emitC() override { return isWide() ? "VL_ASSIGN_W(%nw, %P, %li)" : "%li"; } + string emitC() override { return isWide() ? "VL_ASSIGN_W_%lf%rf(%nw, %P, %li)" : "%li"; } bool cleanOut() const override { return false; } bool cleanLhs() const override { return false; } bool cleanRhs() const override { return false; } @@ -5198,7 +5283,7 @@ class AstInferredDisable final : public AstNodeTermop { public: explicit AstInferredDisable(FileLine* fl) : ASTGEN_SUPER_InferredDisable(fl) { - dtypeSetLogicSized(1, VSigning::UNSIGNED); + dtypeSetBitSized(1, VSigning::UNSIGNED); } ASTGEN_MEMBERS_AstInferredDisable; string emitVerilog() override { return "%f$inferred_disable"; } @@ -5267,7 +5352,7 @@ public: out.opAssign(lhs.isNeqZero() ? rhs : ths); } string emitVerilog() override { return "%k(%l %f? %r %k: %t)"; } - string emitC() override { return "VL_COND_%nq%lq%rq%tq(%nw, %P, %li, %ri, %ti)"; } + string emitC() override { return "VL_COND_%nq%lq%rq%tq_%nf%lf%rf%tf(%nw, %P, %li, %ri, %ti)"; } string emitSMT() const override { return "(ite (__Vbool %l) %r %t)"; } bool cleanOut() const override { return false; } // clean if e1 & e2 clean bool cleanLhs() const override { return true; } @@ -5504,6 +5589,7 @@ public: void numberOperate(V3Number& out, const V3Number& lhs) override { out.opAssign(lhs); } string emitVerilog() override { return "(%l)"; } string emitC() override { V3ERROR_NA_RETURN(""); } + string emitSMT() const override { return "%l"; } bool cleanOut() const override { return false; } bool cleanLhs() const override { return false; } bool sizeMattersLhs() const override { return false; } @@ -5549,12 +5635,20 @@ public: : ASTGEN_SUPER_Extend(fl, lhsp) {} AstExtend(FileLine* fl, AstNodeExpr* lhsp, int width) : ASTGEN_SUPER_Extend(fl, lhsp) { - dtypeSetLogicSized(width, VSigning::UNSIGNED); + if (const AstNodeDType* const dtypep = lhsp->dtypep()) { + if (dtypep->isFourstate()) { + dtypeSetLogicSized(width, VSigning::UNSIGNED); + } else { + dtypeSetBitSized(width, VSigning::UNSIGNED); + } + } else { + dtypeSetLogicSized(width, VSigning::UNSIGNED); + } } ASTGEN_MEMBERS_AstExtend; void numberOperate(V3Number& out, const V3Number& lhs) override { out.opAssign(lhs); } string emitVerilog() override { return "%l"; } - string emitC() override { return "VL_EXTEND_%nq%lq(%nw,%lw, %P, %li)"; } + string emitC() override { return "VL_EXTEND_%nq%lq_%nf%lf(%nw,%lw, %P, %li)"; } string emitSMT() const override { return "((_ zero_extend " + cvtToStr(width() - lhsp()->width()) + ") %l)"; } @@ -5574,14 +5668,22 @@ public: AstExtendS(FileLine* fl, AstNodeExpr* lhsp, int width) // Important that widthMin be correct, as opExtend requires it after V3Expand : ASTGEN_SUPER_ExtendS(fl, lhsp) { - dtypeSetLogicSized(width, VSigning::UNSIGNED); + if (const AstNodeDType* const dtypep = lhsp->dtypep()) { + if (dtypep->isFourstate()) { + dtypeSetLogicSized(width, VSigning::UNSIGNED); + } else { + dtypeSetBitSized(width, VSigning::UNSIGNED); + } + } else { + dtypeSetLogicSized(width, VSigning::UNSIGNED); + } } ASTGEN_MEMBERS_AstExtendS; void numberOperate(V3Number& out, const V3Number& lhs) override { out.opExtendS(lhs, lhsp()->widthMinV()); } string emitVerilog() override { return "%l"; } - string emitC() override { return "VL_EXTENDS_%nq%lq(%nw,%lw, %P, %li)"; } + string emitC() override { return "VL_EXTENDS_%nq%lq_%nf%lf(%nw,%lw, %P, %li)"; } string emitSMT() const override { return "((_ sign_extend " + cvtToStr(width() - lhsp()->width()) + ") %l)"; } @@ -5727,7 +5829,7 @@ public: ASTGEN_MEMBERS_AstLogNot; void numberOperate(V3Number& out, const V3Number& lhs) override { out.opLogNot(lhs); } string emitVerilog() override { return "%f(! %l)"; } - string emitC() override { return "VL_LOGNOT_%nq%lq(%nw,%lw, %P, %li)"; } + string emitC() override { V3ERROR_NA_RETURN(""); } string emitSMT() const override { return "(__Vbv (not (__Vbool %l)))"; } string emitSimpleOperator() override { return "!"; } bool cleanOut() const override { return true; } @@ -5747,7 +5849,7 @@ public: ASTGEN_MEMBERS_AstMostSetBitP1; void numberOperate(V3Number& out, const V3Number& lhs) override { out.opMostSetBitP1(lhs); } string emitVerilog() override { return "%f$mostsetbitp1(%l)"; } - string emitC() override { return "VL_MOSTSETBITP1_%lq(%lW, %P, %li)"; } + string emitC() override { return "VL_MOSTSETBITP1_%lq_%lf(%lW, %P, %li)"; } bool cleanOut() const override { return true; } bool cleanLhs() const override { return true; } bool sizeMattersLhs() const override { return false; } @@ -5778,7 +5880,7 @@ public: ASTGEN_MEMBERS_AstNegate; void numberOperate(V3Number& out, const V3Number& lhs) override { out.opNegate(lhs); } string emitVerilog() override { return "%f(- %l)"; } - string emitC() override { return "VL_NEGATE_%lq(%lW, %P, %li)"; } + string emitC() override { return "VL_NEGATE_%lq_%nf%lf(%lW, %P, %li)"; } string emitSMT() const override { return "(bvneg %l)"; } string emitSimpleOperator() override { return "-"; } bool cleanOut() const override { return false; } @@ -5812,7 +5914,7 @@ public: ASTGEN_MEMBERS_AstNot; void numberOperate(V3Number& out, const V3Number& lhs) override { out.opNot(lhs); } string emitVerilog() override { return "%f(~ %l)"; } - string emitC() override { return "VL_NOT_%lq(%lW, %P, %li)"; } + string emitC() override { return "VL_NOT_%lq_%nf%lf(%lW, %P, %li)"; } string emitSMT() const override { return "(bvnot %l)"; } string emitSimpleOperator() override { return "~"; } bool cleanOut() const override { return false; } @@ -6004,7 +6106,7 @@ public: ASTGEN_MEMBERS_AstRedAnd; void numberOperate(V3Number& out, const V3Number& lhs) override { out.opRedAnd(lhs); } string emitVerilog() override { return "%f(& %l)"; } - string emitC() override { return "VL_REDAND_%nq%lq(%lw, %P, %li)"; } + string emitC() override { return "VL_REDAND_%lq_%lf(%lw, %P, %li)"; } bool cleanOut() const override { return true; } bool cleanLhs() const override { return true; } bool sizeMattersLhs() const override { return false; } @@ -6019,7 +6121,7 @@ public: ASTGEN_MEMBERS_AstRedOr; void numberOperate(V3Number& out, const V3Number& lhs) override { out.opRedOr(lhs); } string emitVerilog() override { return "%f(| %l)"; } - string emitC() override { return "VL_REDOR_%lq(%lW, %P, %li)"; } + string emitC() override { return "VL_REDOR_%lq_%lf(%lW, %P, %li)"; } bool cleanOut() const override { return true; } bool cleanLhs() const override { return true; } bool sizeMattersLhs() const override { return false; } @@ -6034,7 +6136,7 @@ public: ASTGEN_MEMBERS_AstRedXor; void numberOperate(V3Number& out, const V3Number& lhs) override { out.opRedXor(lhs); } string emitVerilog() override { return "%f(^ %l)"; } - string emitC() override { return "VL_REDXOR_%lq(%lW, %P, %li)"; } + string emitC() override { return "VL_REDXOR_%lq_%lf(%lW, %P, %li)"; } bool cleanOut() const override { return false; } bool cleanLhs() const override { const int w = lhsp()->width(); diff --git a/src/V3AstNodeOther.h b/src/V3AstNodeOther.h index 3c25a9992..e0c02de47 100644 --- a/src/V3AstNodeOther.h +++ b/src/V3AstNodeOther.h @@ -1960,11 +1960,12 @@ public: ASTGEN_MEMBERS_AstTypeTable; bool maybePointedTo() const override VL_MT_SAFE { return true; } void cloneRelink() override { V3ERROR_NA; } // Not cloneable - AstBasicDType* findBasicDType(FileLine* fl, VBasicDTypeKwd kwd); + AstBasicDType* findBasicDType(FileLine* fl, VBasicDTypeKwd kwd, + bool isShuffledFourstate = false); AstBasicDType* findLogicBitDType(FileLine* fl, VBasicDTypeKwd kwd, int width, int widthMin, - VSigning numeric); + VSigning numeric, bool isShuffledFourstate); AstBasicDType* findLogicBitDType(FileLine* fl, VBasicDTypeKwd kwd, const VNumRange& range, - int widthMin, VSigning numeric); + int widthMin, VSigning numeric, bool isShuffledFourstate); AstBasicDType* findCreateSameDType(AstBasicDType& node); AstBasicDType* findInsertSameDType(AstBasicDType* nodep); AstConstraintRefDType* findConstraintRefDType(FileLine* fl); @@ -2117,6 +2118,8 @@ class AstVar final : public AstNode { // @astgen op4 := attrsp : List[AstNode] // Attributes during early parse // @astgen ptr := m_sensIfacep : Optional[AstIface] // Interface type to which reads from this // var are sensitive + // @astgen ptr := m_fourstateComplementp : Optional[AstVar] // Set in four-state value part - + // points to an xz part string m_name; // Name of variable string m_origName; // Original name before dot addition @@ -2126,6 +2129,8 @@ class AstVar final : public AstNode { VDirection m_declDirection; // Declared direction input/output etc VLifetime m_lifetime; // Lifetime VRandAttr m_rand; // Randomizability of this variable (rand, randc, etc) + VBasicDTypeKwd + m_fourstateOriginalDTypeKwd; // Original dtype of a four-state var - before splitting int m_pinNum = 0; // For JSON, if non-zero the connection pin number bool m_ansi : 1; // Params or pins declared in the module header, rather than the body bool m_declTyped : 1; // Declared as type (for dedup check) @@ -2190,7 +2195,10 @@ class AstVar final : public AstNode { bool m_isStdRandomizeArg : 1; // Argument variable created for std::randomize (__Varg*) bool m_processQueue : 1; // Process queue variable bool m_mtaskCacheLineAlign : 1; // Start MTask affinity group on a cache line + bool m_isFourstateComplement : 1; // Set in four-state xz part + bool m_isTopLevelPort : 1; // Whether this variable used to be a top level input void init() { + m_fourstateOriginalDTypeKwd = VBasicDTypeKwd::UNKNOWN; m_ansi = false; m_declTyped = false; m_tristate = false; @@ -2254,6 +2262,8 @@ class AstVar final : public AstNode { m_isStdRandomizeArg = false; m_processQueue = false; m_mtaskCacheLineAlign = false; + m_isFourstateComplement = false; + m_isTopLevelPort = false; } public: @@ -2356,6 +2366,36 @@ public: void ansi(bool flag) { m_ansi = flag; } void declTyped(bool flag) { m_declTyped = flag; } void sensIfacep(AstIface* nodep) { m_sensIfacep = nodep; } + void fourstateComplementp(AstVar* const varp) { + UASSERT_OBJ(!isFourstateComplement(), this, + "The variable is a four-state complement itself"); + UASSERT_OBJ(!m_fourstateComplementp, this, "Four-state complement is already added"); + UASSERT_OBJ(!varp->isFourstateComplement(), varp, + "Varp is already a four-state complement"); + UASSERT_OBJ(!varp->fourstateComplementp(), varp, + "Varp has a complement - it can't can be a complement at the same time"); + varp->m_isFourstateComplement = true; + m_fourstateComplementp = varp; + } + AstVar* cloneWithFourstateComplementp() { + UASSERT_OBJ(fourstateComplementp(), this, "Variable has no complement"); + AstVar* const newp = cloneTree(false); + newp->m_fourstateComplementp = fourstateComplementp()->cloneTree(false); + return newp; + } + AstVar* fourstateComplementp() const { return m_fourstateComplementp; } + VBasicDTypeKwd fourstateOriginalDTypeKwd() const { return m_fourstateOriginalDTypeKwd; } + void fourstateOriginalDTypeKwd(const VBasicDTypeKwd dtypeKwd) { + m_fourstateOriginalDTypeKwd = dtypeKwd; + } + bool isFourstateComplement() const { return m_isFourstateComplement; } + void unsetIsFourstateComplement() { m_isFourstateComplement = false; } + bool isFourstateConstruct() const { + return m_isFourstateComplement || dtypep()->isShuffledFourstate() + || fourstateComplementp(); + } + bool isTopLevelPort() const { return m_isTopLevelPort; } + void setIsTopLevelPort() { m_isTopLevelPort = true; } void attrFileDescr(bool flag) { m_fileDescr = flag; } void attrScBv(bool flag) { m_attrScBv = flag; } void attrScBigUint(bool flag) { m_attrScBigUint = flag; } @@ -2565,6 +2605,7 @@ public: && !noCReset() && !(basicp() && basicp()->isEvent()); } static AstVar* scVarRecurse(AstNode* nodep); + const char* broken() const override; }; class AstVarScope final : public AstNode { // A particular scoped usage of a variable diff --git a/src/V3AstNodeStmt.h b/src/V3AstNodeStmt.h index 25de3ad08..e7b2fd60b 100644 --- a/src/V3AstNodeStmt.h +++ b/src/V3AstNodeStmt.h @@ -1297,8 +1297,10 @@ class AstTraceDecl final : public AstNodeStmt { const VNumRange m_arrayRange; // Property of var the trace details const VVarType m_varType; // Type of variable (for localparam vs. param) const VDirection m_declDirection; // Declared direction input/output etc + const VBasicDTypeKwd m_dtypeKwd; // dtype keyword of traced signal const bool m_inDtypeFunc; // Trace decl inside type init function int m_codeInc{0}; // Code increment for type + public: AstTraceDecl(FileLine* fl, const string& showname, AstVar* varp, // For input/output state etc @@ -1310,6 +1312,7 @@ public: , m_arrayRange{arrayRange} , m_varType{varp->varType()} , m_declDirection{varp->declDirection()} + , m_dtypeKwd{varp->fourstateOriginalDTypeKwd()} , m_inDtypeFunc{inDtypeFunc} { dtypeFrom(valuep); this->valuep(valuep); @@ -1335,12 +1338,15 @@ public: if (m_codeInc) { return m_codeInc; } return (m_arrayRange.ranged() ? m_arrayRange.elements() : 1) * valuep()->dtypep()->widthWords() + * (1 + VN_IS(valuep(), FourstateExpr)) // Fourstate variables take twice + // as much space as they are wide * (VL_EDATASIZE / 32); // A code is always 32-bits } const VNumRange& bitRange() const { return m_bitRange; } const VNumRange& arrayRange() const { return m_arrayRange; } VVarType varType() const { return m_varType; } VDirection declDirection() const { return m_declDirection; } + VBasicDTypeKwd dtypeKwd() const { return m_dtypeKwd; } AstCCall* dtypeCallp() const { return m_dtypeCallp; } void dtypeCallp(AstCCall* const callp) { m_dtypeCallp = callp; } AstTraceDecl* dtypeDeclp() const { return m_dtypeDeclp; } diff --git a/src/V3AstNodes.cpp b/src/V3AstNodes.cpp index aba8a9d0f..f9235d1b3 100644 --- a/src/V3AstNodes.cpp +++ b/src/V3AstNodes.cpp @@ -199,11 +199,12 @@ void AstAddrOfCFunc::dump(std::ostream& str) const { } void AstBasicDType::init(VBasicDTypeKwd kwd, VSigning numer, int wantwidth, int wantwidthmin, - AstRange* rangep) { + AstRange* rangep, bool isShuffledFourstate) { // wantwidth=0 means figure it out, but if a widthmin is >=0 // we allow width 0 so that {{0{x}},y} works properly // wantwidthmin=-1: default, use wantwidth if it is non-zero m.m_keyword = kwd; + m.m_isShuffledFourstate = isShuffledFourstate; // Implicitness: // "parameter X" is implicit and sized from initial // value, "parameter reg x" not if (keyword() == VBasicDTypeKwd::LOGIC_IMPLICIT) { @@ -1026,6 +1027,15 @@ AstVar* AstVar::scVarRecurse(AstNode* nodep) { return nullptr; } +const char* AstVar::broken() const { + BROKEN_RTN(v3Global.fourstateHandled() && dtypep()->isFourstate()); + BROKEN_RTN(v3Global.fourstateShuffled() && dtypep()->isWide() + && (isFourstateComplement() + || name().rfind("__Vxz") // TODO: make this not a hard coded value + != std::string::npos)); + return nullptr; +} + const AstNodeDType* AstNodeDType::skipRefIterp(bool skipConst, bool skipEnum, bool assertOn) const VL_MT_STABLE { static constexpr int MAX_TYPEDEF_DEPTH = 1000; @@ -1221,7 +1231,8 @@ AstNodeDType::CTypeRecursed AstNodeDType::cTypeRecurse(bool compound, bool packe // We don't print msb()/lsb() as multidim packed would require recursion, // and may confuse users as C++ data is stored always with bit 0 used const string bitvec = (!bdtypep->isOpaque() && !v3Global.opt.protectIds()) - ? "/*" + cvtToStr(dtypep->width() - 1) + ":0*/" + ? "/*" + cvtToStr(dtypep->width() - 1) + ":0" + + (isShuffledFourstate() ? " 4-state" : "") + "*/" : ""; if (bdtypep->keyword() == VBasicDTypeKwd::CHARPTR) { info.m_type = "const char*"; @@ -1249,6 +1260,8 @@ AstNodeDType::CTypeRecursed AstNodeDType::cTypeRecurse(bool compound, bool packe info.m_type = "VlStdRandomizer"; } else if (bdtypep->isEvent()) { info.m_type = v3Global.assignsEvents() ? "VlAssignableEvent" : "VlEvent"; + } else if (dtypep->isWide()) { + info.m_type = "VlWide<" + cvtToStr(dtypep->widthWords()) + ">" + bitvec; } else if (dtypep->widthMin() <= 8) { // Handle unpacked arrays; not bdtypep->width info.m_type = "CData" + bitvec; } else if (dtypep->widthMin() <= 16) { @@ -1257,8 +1270,6 @@ AstNodeDType::CTypeRecursed AstNodeDType::cTypeRecurse(bool compound, bool packe info.m_type = "IData" + bitvec; } else if (dtypep->isQuad()) { info.m_type = "QData" + bitvec; - } else if (dtypep->isWide()) { - info.m_type = "VlWide<" + cvtToStr(dtypep->widthWords()) + ">" + bitvec; } // CData, SData, IData, QData or VlWide are packed type. const bool packedType = VString::startsWith(info.m_type, "CData") @@ -1604,32 +1615,34 @@ AstVoidDType* AstTypeTable::findVoidDType(FileLine* fl) { return m_voidp; } -AstBasicDType* AstTypeTable::findBasicDType(FileLine* fl, VBasicDTypeKwd kwd) { +AstBasicDType* AstTypeTable::findBasicDType(FileLine* fl, VBasicDTypeKwd kwd, + bool isShuffledFourstate) { // Because the detailed map doesn't update m_basicps, check the detailed // map for this same node. Also adds this new node to the detailed map if (!m_basicps[kwd]) { - AstBasicDType basic{fl, kwd}; + AstBasicDType basic{fl, kwd, VSigning::NOSIGN, isShuffledFourstate}; m_basicps[kwd] = findCreateSameDType(basic); } return m_basicps[kwd]; } AstBasicDType* AstTypeTable::findLogicBitDType(FileLine* fl, VBasicDTypeKwd kwd, int width, - int widthMin, VSigning numeric) { - AstBasicDType basic{fl, kwd, numeric, width, widthMin}; + int widthMin, VSigning numeric, + bool isShuffledFourstate) { + AstBasicDType basic{fl, kwd, numeric, width, widthMin, isShuffledFourstate}; return findCreateSameDType(basic); } AstBasicDType* AstTypeTable::findLogicBitDType(FileLine* fl, VBasicDTypeKwd kwd, const VNumRange& range, int widthMin, - VSigning numeric) { - AstBasicDType basic{fl, kwd, numeric, range, widthMin}; + VSigning numeric, bool isShuffledFourstate) { + AstBasicDType basic{fl, kwd, numeric, range, widthMin, isShuffledFourstate}; return findCreateSameDType(basic); } AstBasicDType* AstTypeTable::findCreateSameDType(AstBasicDType& node) { - const VBasicTypeKey key{node.width(), node.widthMin(), node.numeric(), node.keyword(), - node.nrange()}; + const VBasicTypeKey key{node.width(), node.widthMin(), node.numeric(), + node.keyword(), node.nrange(), node.isShuffledFourstate()}; AstBasicDType*& entryr = m_detailedMap[key]; if (!entryr) { entryr = node.cloneTree(false); @@ -1641,8 +1654,8 @@ AstBasicDType* AstTypeTable::findCreateSameDType(AstBasicDType& node) { // cppcheck-suppress duplInheritedMember AstBasicDType* AstTypeTable::findInsertSameDType(AstBasicDType* nodep) { - const VBasicTypeKey key{nodep->width(), nodep->widthMin(), nodep->numeric(), nodep->keyword(), - nodep->nrange()}; + const VBasicTypeKey key{nodep->width(), nodep->widthMin(), nodep->numeric(), + nodep->keyword(), nodep->nrange(), nodep->isShuffledFourstate()}; auto pair = m_detailedMap.emplace(key, nodep); if (pair.second) nodep->generic(true); // No addTypesp; the upper function that called new() is responsible for adding @@ -1956,6 +1969,7 @@ void AstAttrOf::dumpJson(std::ostream& str) const { void AstBasicDType::dump(std::ostream& str) const { this->AstNodeDType::dump(str); str << " kwd=" << keyword().ascii(); + if (isShuffledFourstate()) str << " [SHUFFLED4STATE]"; if (isRanged() && !rangep()) str << " range=[" << left() << ":" << right() << "]"; } void AstBasicDType::dumpJson(std::ostream& str) const { @@ -3285,6 +3299,10 @@ void AstVar::dump(std::ostream& str) const { } else if (isFuncLocal()) { str << " [FUNC]"; } + if (const AstVar* const varp = fourstateComplementp()) { + str << " [COMPL=" << nodeAddr(varp) << "]"; + } + if (isFourstateComplement()) str << " [4STATECOMPL]"; if (hasUserInit()) str << " [UINIT]"; if (icoMaybeWritten()) str << " [ICOMAYBEWRITTEN]"; if (isDpiOpenArray()) str << " [DPIOPENA]"; diff --git a/src/V3Const.cpp b/src/V3Const.cpp index 203fef45a..1a537379b 100644 --- a/src/V3Const.cpp +++ b/src/V3Const.cpp @@ -3709,6 +3709,16 @@ class ConstVisitor final : public VNVisitor { if (!m_doNConst) return; const AstBasicDType* const bdtypep = VN_CAST(nodep->dtypep()->skipRefp(), BasicDType); if (!bdtypep) return; + { + const AstNodeExpr* const lhsp = VN_AS(nodep->abovep(), NodeAssign)->lhsp(); + const AstVar* varp; + if (const AstMemberSel* memberSel = VN_CAST(lhsp, MemberSel)) { + varp = memberSel->varp(); + } else { + varp = VN_AS(lhsp, NodeVarRef)->varp(); + } + if (varp->isFourstateConstruct()) return; + } if (!bdtypep->isZeroInit()) return; AstConst* const newp = new AstConst{nodep->fileline(), V3Number{nodep, bdtypep}}; UINFO(9, "CRESET(0) => CONST(0) " << nodep); @@ -3846,8 +3856,9 @@ class ConstVisitor final : public VNVisitor { nodep->condp(new AstLogNot{condp->fileline(), condp}); // LogNot, as C++ optimization also possible nodep->addThensp(elsesp); - } else if (((VN_IS(nodep->condp(), Not) && nodep->condp()->width() == 1) - || VN_IS(nodep->condp(), LogNot)) + } else if ((!v3Global.opt.fourstate() || v3Global.fourstateHandled()) + && ((VN_IS(nodep->condp(), Not) && nodep->condp()->width() == 1) + || VN_IS(nodep->condp(), LogNot)) && nodep->thensp() && nodep->elsesp()) { UINFO(4, "IF(NOT {x}) => IF(x) swapped if/else" << nodep); AstNodeExpr* const condp @@ -3859,7 +3870,8 @@ class ConstVisitor final : public VNVisitor { ifp->branchPred(nodep->branchPred().invert()); nodep->replaceWith(ifp); VL_DO_DANGLING(pushDeletep(nodep), nodep); - } else if (ifSameAssign(nodep)) { + } else if ((!v3Global.opt.fourstate() || v3Global.fourstateHandled()) + && ifSameAssign(nodep)) { UINFO(4, "IF({a}) ASSIGN({b},{c}) else ASSIGN({b},{d}) => ASSIGN({b}, {a}?{c}:{d})"); AstNodeAssign* const thensp = VN_AS(nodep->thensp(), NodeAssign); diff --git a/src/V3Dead.cpp b/src/V3Dead.cpp index 411ec57eb..f88020d43 100644 --- a/src/V3Dead.cpp +++ b/src/V3Dead.cpp @@ -489,8 +489,12 @@ class DeadVisitor final : public VNVisitor { retry = false; for (std::vector::iterator it = m_varsp.begin(); it != m_varsp.end(); ++it) { AstVar* const varp = *it; - if (!varp) continue; + if (!varp || varp->isFourstateComplement()) continue; if (varp->user1() == 0) { + if (AstVar* const varComplementp = varp->fourstateComplementp()) { + if (varComplementp->user1() != 0) continue; + deleting(varComplementp); + } UINFO(4, " Dead " << varp); if (varp->dtypep()) varp->dtypep()->user1Inc(-1); deleting(varp); diff --git a/src/V3Delayed.cpp b/src/V3Delayed.cpp index f2ed71ebc..978ade1e5 100644 --- a/src/V3Delayed.cpp +++ b/src/V3Delayed.cpp @@ -489,6 +489,76 @@ class DelayedVisitor final : public VNVisitor { return varscp; } + AstVarScope* getFourstateComplementScope(const AstVarScope* const vscp) { + const AstVar* const varp = vscp->varp()->fourstateComplementp(); + UASSERT_OBJ(varp, vscp, "Non four-state won't have a complement"); + AstVarScope* resultp = VN_AS(vscp->nextp(), VarScope); + do { + // In most (if not in all) cases the complement VarScope is right after main part + if (resultp->varp() == varp) return resultp; + resultp = VN_AS(resultp->nextp(), VarScope); + } while (resultp); + // Fallback to looking elsewhere + resultp = vscp->scopep()->varsp(); + while (resultp != vscp) { + // In most (if not in all) cases the complement VarScope is right after main part + if (resultp->varp() == varp) return resultp; + resultp = VN_AS(resultp->nextp(), VarScope); + } + return nullptr; + } + + AstVarScope* createTemp(const std::string& prefix, AstVarScope* vscp, AstNodeDType* dtypep, + VarScopeInfo* vscpInfo = nullptr) { + const AstVar* const varp = vscp->varp(); + AstScope* const scopep = vscp->scopep(); + auto getName + = [this, &prefix, scopep](const AstVarScope* const vscp, VarScopeInfo* vscpInfo) { + return prefix + + (vscpInfo ? uniqueTmpName(scopep, vscp, *vscpInfo) + : vscp->varp()->shortName()); + }; + FileLine* const flp = vscp->fileline(); + + AstNodeModule* const modp = scopep->modp(); + // Get/create the corresponding AstVar + AstVar*& newVarp = m_varMap(modp)[getName(vscp, vscpInfo)]; + bool newlyCreated = false; + if (!newVarp) { + newVarp = new AstVar{flp, VVarType::BLOCKTEMP, getName(vscp, vscpInfo), dtypep}; + modp->addStmtsp(newVarp); + newlyCreated = true; + } + + if (varp->fourstateComplementp()) { + if (AstVarScope* const complementVscp = getFourstateComplementScope(vscp)) { + std::string name + = getName(complementVscp, vscpInfo ? &m_vscpInfo(complementVscp) : nullptr); + AstVar*& newComplementVarp = m_varMap(modp)[name]; + if (!newComplementVarp) { + newComplementVarp = new AstVar{flp, VVarType::BLOCKTEMP, name, dtypep}; + modp->addStmtsp(newComplementVarp); + } + if (newlyCreated) newVarp->fourstateComplementp(newComplementVarp); + } + } + + // We should be able to assert this here, but unfortuantely + // 'isAssignmentCompatible' does not exist as of right now. + // UASSERT_OBJ(isAssignmentCompatible(varp->dtypep(), dtypep), flp, "Invalid temporary"); + + // Create the AstVarScope + AstVarScope* const varscp = new AstVarScope{flp, scopep, newVarp}; + scopep->addVarsp(varscp); + return varscp; + } + + AstVarScope* createTemp(const std::string& prefix, AstVarScope* vscp, int width, + VarScopeInfo* vscpInfo = nullptr) { + return createTemp(prefix, vscp, vscp->findBitDType(width, width, VSigning::UNSIGNED), + vscpInfo); + } + // Same as above but create a 2-state scalar of the given 'width' AstVarScope* createTemp(FileLine* flp, AstScope* scopep, const std::string& name, int width) { AstNodeDType* const dtypep = scopep->findBitDType(width, width, VSigning::UNSIGNED); @@ -591,8 +661,7 @@ class DelayedVisitor final : public VNVisitor { FileLine* const flp = vscp->fileline(); AstScope* const scopep = vscp->scopep(); // Create the shadow variable - const std::string name = "__Vdly__" + vscp->varp()->shortName(); - AstVarScope* const shadowVscp = createTemp(flp, scopep, name, vscp->dtypep()); + AstVarScope* const shadowVscp = createTemp("__Vdly__", vscp, vscp->dtypep()); vscpInfo.shadowVariableKit().vscp = shadowVscp; // Mark both for V3LifePsot vscp->optimizeLifePost(true); @@ -631,12 +700,10 @@ class DelayedVisitor final : public VNVisitor { FileLine* const flp = vscp->fileline(); AstScope* const scopep = vscp->scopep(); // Create the shadow variable - const std::string shadowName = "__Vdly__" + vscp->varp()->shortName(); - AstVarScope* const shadowVscp = createTemp(flp, scopep, shadowName, vscp->dtypep()); + AstVarScope* const shadowVscp = createTemp("__Vdly__", vscp, vscp->dtypep()); vscpInfo.shadowVarMaskedKit().vscp = shadowVscp; // Create the makk variable - const std::string maskName = "__VdlyMask__" + vscp->varp()->shortName(); - AstVarScope* const maskVscp = createTemp(flp, scopep, maskName, vscp->dtypep()); + AstVarScope* const maskVscp = createTemp("__VdlyMask__", vscp, vscp->dtypep()); maskVscp->varp()->setIgnorePostWrite(); vscpInfo.shadowVarMaskedKit().maskp = maskVscp; // Create the AstActive for the Post logic @@ -742,7 +809,7 @@ class DelayedVisitor final : public VNVisitor { if (!reuseTheFlag) { // Create new flag - AstVarScope* const flagVscp = createTemp(flp, scopep, "__VdlySet" + baseName, 1); + AstVarScope* const flagVscp = createTemp("__VdlySet", vscp, 1, &vscpInfo); // Set the flag at the original NBA nodep->addHereThisAsNext( // new AstAssign{flp, new AstVarRef{flp, flagVscp, VAccess::WRITE}, @@ -818,7 +885,7 @@ class DelayedVisitor final : public VNVisitor { = captureLhs(scopep, nodep, nodep->lhsp()->unlinkFrBack(), baseName); // Create new flag - AstVarScope* const flagVscp = createTemp(flp, scopep, "__VdlySet" + baseName, 1); + AstVarScope* const flagVscp = createTemp("__VdlySet", vscp, 1, &vscpInfo); flagVscp->varp()->setIgnorePostWrite(); // Set the flag at the original NBA nodep->addHereThisAsNext( // @@ -850,8 +917,7 @@ class DelayedVisitor final : public VNVisitor { auto* const cqDTypep = new AstNBACommitQueueDType{flp, vscp->dtypep()->skipRefp(), N_Partial}; v3Global.rootp()->typeTablep()->addTypesp(cqDTypep); - const std::string name = "__VdlyCommitQueue" + vscp->varp()->shortName(); - AstVarScope* const queueVscp = createTemp(flp, scopep, name, cqDTypep); + AstVarScope* const queueVscp = createTemp("__VdlyCommitQueue", vscp, cqDTypep); queueVscp->varp()->noReset(true); queueVscp->varp()->setIgnorePostWrite(); vscpInfo.valueQueueKit().vscp = queueVscp; @@ -1198,9 +1264,7 @@ class DelayedVisitor final : public VNVisitor { AstNode* newp = cstmtp; if (nodep->isDelayed()) { const AstVarRef* const vrefp = VN_AS(eventp, VarRef); - const std::string newvarname = "__Vdly__" + vrefp->varp()->shortName(); - AstVarScope* const dlyvscp - = createTemp(flp, vrefp->varScopep()->scopep(), newvarname, 1); + AstVarScope* const dlyvscp = createTemp("__Vdly__", vrefp->varScopep(), 1); const auto dlyRef = [=](VAccess access) { // return new AstVarRef{flp, dlyvscp, access}; diff --git a/src/V3DfgDataType.h b/src/V3DfgDataType.h index 3011d254f..092129066 100644 --- a/src/V3DfgDataType.h +++ b/src/V3DfgDataType.h @@ -77,7 +77,7 @@ class DfgDataType final { // METHODS static AstNodeDType* canonicalPackedDType(uint32_t width) { - return v3Global.rootp()->typeTablep()->findLogicDType(width, width, VSigning::UNSIGNED); + return v3Global.rootp()->typeTablep()->findBitDType(width, width, VSigning::UNSIGNED); } static AstNodeDType* canonicalArrayDType(uint32_t size, const DfgDataType& elemType) { AstNodeDType* const elemDTypep = elemType.m_astDtypep; diff --git a/src/V3DfgDfgToAst.cpp b/src/V3DfgDfgToAst.cpp index b2af96461..16822e999 100644 --- a/src/V3DfgDfgToAst.cpp +++ b/src/V3DfgDfgToAst.cpp @@ -54,7 +54,7 @@ template <> AstCountOnes* makeNode( // const DfgCountOnes* vtxp, AstNodeExpr* op1) { AstCountOnes* const nodep = new AstCountOnes{vtxp->fileline(), op1}; - nodep->dtypeSetLogicSized(vtxp->width(), VSigning::UNSIGNED); + nodep->dtypeSetBitSized(vtxp->width(), VSigning::UNSIGNED); return nodep; } diff --git a/src/V3EmitCConstInit.h b/src/V3EmitCConstInit.h index b18a43e46..d210f5b85 100644 --- a/src/V3EmitCConstInit.h +++ b/src/V3EmitCConstInit.h @@ -41,6 +41,16 @@ class EmitCConstInit VL_NOT_FINAL : public EmitCBaseVisitorConst { } protected: + void emitTVX(const AstNode* const nodep) { + const AstVarRef* const varRefp = VN_CAST(nodep, VarRef); + if (varRefp && varRefp->varp()->dtypep()->isShuffledFourstate()) { + UASSERT_OBJ(v3Global.opt.fourstate(), nodep, + "Tried to use four-state function in two state mode"); + puts(varRefp->fourstateXZPart() ? "X" : "V"); + } else { + puts("T"); + } + } // VISITORS void visit(AstInitArray* nodep) override { VL_RESTORER(m_unpackedWord); diff --git a/src/V3EmitCFunc.cpp b/src/V3EmitCFunc.cpp index 11f2ac14a..0c56a3f1c 100644 --- a/src/V3EmitCFunc.cpp +++ b/src/V3EmitCFunc.cpp @@ -42,6 +42,7 @@ void EmitCFunc::emitOpName(AstNode* nodep, const string& format, AstNode* lhsp, // and write out appropriate text. // %n* node // %nq emitIQW on the [node] + // %nf data format T/V/X // %nw width in bits // %nW width in words // %ni iterate @@ -50,6 +51,7 @@ void EmitCFunc::emitOpName(AstNode* nodep, const string& format, AstNode* lhsp, // %t* thsp - if appropriate, then second char as above // %k Potential line break // %P Wide temporary name + // %p* Wide temporary - if appropriate, then second char as above // , Commas suppressed if the previous field is suppressed string out; putnbs(nodep, ""); @@ -128,6 +130,16 @@ void EmitCFunc::emitOpName(AstNode* nodep, const string& format, AstNode* lhsp, needComma = true; } + break; + case 'p': + if (nodep->isWide()) { + UASSERT_OBJ(m_wideTempRefp, nodep, + "Wide Op w/ no temp, perhaps missing op in V3EmitC?"); + detail = true; + detailp = m_wideTempRefp; + } else { + ++pos; + } break; default: nodep->v3fatalSrc("Unknown emitOperator format code: %" << pos[0]); break; } @@ -149,15 +161,22 @@ void EmitCFunc::emitOpName(AstNode* nodep, const string& format, AstNode* lhsp, emitIQW(detailp); } break; + case 'f': + putOut(); + emitTVX(detailp); + break; case 'w': commaOut(); out += cvtToStr(detailp->widthMin()); needComma = true; break; case 'W': - if (lhsp->isWide()) { + if (detailp->isWide()) { commaOut(); - out += cvtToStr(lhsp->widthWords()); + out += cvtToStr(VL_WORDS_I( + detailp->width())); // Even if signal is shuffled we want to emit + // width that does not take into account the fact + // that 4-states takes 2 bits needComma = true; } else if (VN_IS(lhsp, StreamR)) { commaOut(); @@ -521,6 +540,15 @@ void EmitCFunc::emitVarReset(const string& prefix, AstVar* varp, bool constructi } } +bool isModulePort(const AstVar* const varp) { + if (varp->varType() == VVarType::PORT) { + const AstNode* iter = varp; + while (!iter->firstAbovep()) iter = iter->backp(); + if (VN_IS(iter->firstAbovep(), Module)) return true; + } + return false; +} + string EmitCFunc::emitVarResetRecurse(const AstVar* varp, bool constructing, const string& varNameProtected, AstNodeDType* dtypep, int depth, const string& suffix, const AstNode* valuep) { @@ -617,8 +645,47 @@ string EmitCFunc::emitVarResetRecurse(const AstVar* varp, bool constructing, out += varNameProtected + suffix + "[" + cvtToStr(w) + "] = "; out += cvtToStr(constp->num().edataWord(w)) + "U;\n"; } + } else if (v3Global.opt.fourstate() && dtypep->isShuffledFourstate()) { + const std::string& reset = slow ? "RESET_" : ""; + if (v3Global.opt.zeroTopPorts().isTrue() && varp->isTopLevelPort()) { + // Instead of using VL_ZERO_RESET_W V and X we just use T and pretend the + // signal is twice as wide. this way we resets whole thing and sets to zero at + // once. We can do that because of the four-state internal representation + out += "VL_ZERO_" + reset + "W_T("; + out += cvtToStr(dtypep->widthMin() * 2); + out += ", " + varNameProtected + suffix; + out += ");\n"; + } else if (varp->varType().isNet() || isModulePort(varp)) { + out += "VL_ZERO_" + reset + "W_V("; + out += cvtToStr(dtypep->widthMin()); + out += ", " + varNameProtected + suffix; + out += ");\n"; + out += "VL_ALLONES_" + reset + "W_X("; + out += cvtToStr(dtypep->widthMin()); + out += ", " + varNameProtected + suffix; + out += ");\n"; + } else { + // The same as above we can do a trick and use the internal representation to + // set everything up in one go but this time it is important to clear the + // result + out += "VL_ALLONES_" + reset + "W_T("; + out += cvtToStr(dtypep->widthWords() * VL_EDATASIZE); + out += ", " + varNameProtected + suffix; + out += ");\n"; + if ((dtypep->widthMin() & VL_SIZEBITS_E) != 0) { + // Need cleaning + out += "_vl_clean_inplace_w_V("; + out += cvtToStr(dtypep->widthMin()); + out += ", " + varNameProtected + suffix; + out += ");\n"; + out += "_vl_clean_inplace_w_X("; + out += cvtToStr(dtypep->widthMin()); + out += ", " + varNameProtected + suffix; + out += ");\n"; + } + } } else { - out += zeroit ? (slow ? "VL_ZERO_RESET_W(" : "VL_ZERO_W(") + out += zeroit ? (slow ? "VL_ZERO_RESET_W_T(" : "VL_ZERO_W_T(") : (varp->isXTemp() ? "VL_SCOPED_RAND_RESET_ASSIGN_W(" : "VL_SCOPED_RAND_RESET_W("); out += cvtToStr(dtypep->widthMin()); @@ -645,6 +712,16 @@ string EmitCFunc::emitVarResetRecurse(const AstVar* varp, bool constructing, UASSERT_OBJ(constp, varp, "non-const initializer for variable"); out += cvtToStr(constp->num().edataWord(0)) + "U;\n"; out += ";\n"; + } else if (v3Global.opt.fourstate() && varp->isFourstateConstruct()) { + V3Number xNum{varp->fileline(), varp->width(), 0}; + if (!(v3Global.opt.zeroTopPorts().isTrue() && varp->isTopLevelPort()) + && (varp->isFourstateComplement() + || !(varp->varType().isNet() || isModulePort(varp)))) { + xNum.setAllBits1(); + } + out += " = "; + out += xNum.emitC(); + out += ";\n"; } else if (zeroit) { out += " = 0;\n"; } else { diff --git a/src/V3EmitCFunc.h b/src/V3EmitCFunc.h index 5e527870c..7c1b5850d 100644 --- a/src/V3EmitCFunc.h +++ b/src/V3EmitCFunc.h @@ -30,9 +30,6 @@ #include #include -// Number of VL_CONST_W_*X's in verilated.h (IE VL_CONST_W_8X is last) -constexpr int EMITC_NUM_CONSTW = 8; - //###################################################################### // Emit lazy forward declarations @@ -299,58 +296,23 @@ public: return; } - int upWidth = nodep->num().widthToFit(); - int chunks = 0; - if (upWidth > EMITC_NUM_CONSTW * VL_EDATASIZE) { - // Output e.g. 8 words in groups of e.g. 8 - chunks = (upWidth - 1) / (EMITC_NUM_CONSTW * VL_EDATASIZE); - upWidth %= (EMITC_NUM_CONSTW * VL_EDATASIZE); - if (upWidth == 0) upWidth = (EMITC_NUM_CONSTW * VL_EDATASIZE); + const int width = nodep->num().widthToFit(); + putnbs(nodep, "VL_CONST_W_"); + emitTVX(assigntop); + puts("("); + puts(cvtToStr(assigntop->width())); + puts(","); + if (!assigntop->selfPointer().isEmpty()) { + emitDereference(assigntop, assigntop->selfPointerProtect(m_useSelfForThis)); } - { // Upper e.g. 8 words - if (chunks) { - putnbs(nodep, "VL_CONSTHI_W_"); - puts(cvtToStr(VL_WORDS_I(upWidth))); - puts("X("); - puts(cvtToStr(nodep->widthMin())); - puts(","); - puts(cvtToStr(chunks * EMITC_NUM_CONSTW * VL_EDATASIZE)); - } else { - putnbs(nodep, "VL_CONST_W_"); - puts(cvtToStr(VL_WORDS_I(upWidth))); - puts("X("); - puts(cvtToStr(nodep->widthMin())); - } - puts(","); - if (!assigntop->selfPointer().isEmpty()) { - emitDereference(assigntop, assigntop->selfPointerProtect(m_useSelfForThis)); - } - puts(assigntop->varp()->nameProtect()); - for (int word = VL_WORDS_I(upWidth) - 1; word >= 0; word--) { - // Only 32 bits - llx + long long here just to appease CPP format warning - ofp()->printf(",0x%08" PRIx64, static_cast(nodep->num().edataWord( - word + chunks * EMITC_NUM_CONSTW))); - } - puts(")"); - } - for (chunks--; chunks >= 0; chunks--) { - puts(";\n"); - putbs("VL_CONSTLO_W_"); - puts(cvtToStr(EMITC_NUM_CONSTW)); - puts("X("); - puts(cvtToStr(chunks * EMITC_NUM_CONSTW * VL_EDATASIZE)); - puts(","); - if (!assigntop->selfPointer().isEmpty()) { - emitDereference(assigntop, assigntop->selfPointerProtect(m_useSelfForThis)); - } - puts(assigntop->varp()->nameProtect()); - for (int word = EMITC_NUM_CONSTW - 1; word >= 0; word--) { - // Only 32 bits - llx + long long here just to appease CPP format warning - ofp()->printf(",0x%08" PRIx64, static_cast(nodep->num().edataWord( - word + chunks * EMITC_NUM_CONSTW))); - } - puts(")"); + puts(assigntop->varp()->nameProtect()); + puts(", {"); + for (int word = 0; word < VL_WORDS_I(width); ++word) { + // Only 32 bits - llx + long long here just to appease CPP format warning + if (word) puts(","); + ofp()->printf("0x%08" PRIx64, static_cast(nodep->num().edataWord(word))); } + puts("})"); } void emitNodesWithText(AstNode* nodesp, bool useSelfForThis, bool tracking, @@ -609,6 +571,9 @@ public: putnbs(nodep, "VL_ASSIGNSEL_"); emitIQW(selp->fromp()); emitIQW(nodep->rhsp()); + puts("_"); + emitTVX(selp->fromp()); + emitTVX(nodep->rhsp()); puts("("); putns(selp->fromp(), cvtToStr(selp->fromp()->widthMin()) + ", "); puts(cvtToStr(nodep->widthMin()) + ", "); @@ -694,8 +659,10 @@ public: m_wideTempRefp = VN_AS(nodep->lhsp(), VarRef); paren = false; } else if (nodep->isWide() && !unpackDtp && !VN_IS(nodep->rhsp(), Const)) { - putnbs(nodep, "VL_ASSIGN_W("); - puts(cvtToStr(nodep->widthMin()) + ", "); + putnbs(nodep, "VL_ASSIGN_W_"); + emitTVX(nodep->lhsp()); + emitTVX(nodep->rhsp()); + puts("(" + cvtToStr(nodep->widthMin()) + ", "); iterateAndNextConstNull(nodep->lhsp()); puts(", "); } else if (VN_IS(nodep->lhsp()->dtypep()->skipRefp(), QueueDType) @@ -1792,7 +1759,6 @@ public: } void visit(AstConst* nodep) override { // if (m_wideTempRefp && nodep->isWide()) { - UASSERT_OBJ(m_wideTempRefp, nodep, "Wide Constant w/ no temp"); emitConstantW(nodep, m_wideTempRefp); m_wideTempRefp = nullptr; // We used it, fail if set it a second time } else { diff --git a/src/V3EmitCHeaders.cpp b/src/V3EmitCHeaders.cpp index 8b2f2add0..04c4b8823 100644 --- a/src/V3EmitCHeaders.cpp +++ b/src/V3EmitCHeaders.cpp @@ -442,7 +442,9 @@ class EmitCHeader final : public EmitCConstInit { puts(getfunc ? "VL_ASSIGNSEL_" : "VL_SELASSIGN_"); puts(lhstype->charIQWN()); puts(rhstype->charIQWN()); - puts("(" + std::to_string(lhstype->width()) + ", "); // LHS width + UASSERT_OBJ(!v3Global.opt.fourstate(), lhstype, + "Four-state currently do not support structs and unions"); + puts("_TT(" + std::to_string(lhstype->width()) + ", "); // LHS width if (getfunc) { puts(std::to_string(rhstype->width()) + ", "); // Number of copy bits puts(off + ", "); // LHS offset diff --git a/src/V3EmitCImp.cpp b/src/V3EmitCImp.cpp index 0f968d486..c781ecc7f 100644 --- a/src/V3EmitCImp.cpp +++ b/src/V3EmitCImp.cpp @@ -740,8 +740,9 @@ class EmitCTrace final : public EmitCFunc { void emitTraceChangeOne(AstTraceInc* nodep, int arrayindex) { // Note: Both VTraceType::CHANGE and VTraceType::FULL use the 'full' methods - const std::string func = nodep->traceType() == VTraceType::CHANGE ? "chg" : "full"; + std::string func = nodep->traceType() == VTraceType::CHANGE ? "chg" : "full"; bool emitWidth = true; + const bool isFourstate = VN_IS(nodep->valuep(), FourstateExpr); string stype; if (nodep->dtypep()->basicp()->isDouble()) { stype = "Double"; @@ -759,10 +760,14 @@ class EmitCTrace final : public EmitCFunc { } else if (nodep->dtypep()->basicp()->isEvent()) { stype = "Event"; emitWidth = false; + } else if (isFourstate) { + stype = "Logic"; + emitWidth = false; } else { stype = "Bit"; emitWidth = false; } + if (isFourstate && stype != "Logic") func += "Fourstate"; putns(nodep, "bufp->" + func + stype); const uint32_t offset = (arrayindex < 0) ? 0 : (arrayindex * nodep->declp()->widthWords()); @@ -781,8 +786,8 @@ class EmitCTrace final : public EmitCFunc { } void emitTraceValue(const AstTraceInc* nodep, int arrayindex) { - if (AstVarRef* const varrefp = VN_CAST(nodep->valuep(), VarRef)) { - const AstVar* const varp = varrefp->varp(); + auto putVarRef = [this, nodep, arrayindex](AstVarRef* const varrefp) { + AstVar* const varp = varrefp->varp(); if (varp->isEvent()) puts("&"); puts("("); if (emitTraceIsScBigUint(nodep)) { @@ -801,12 +806,39 @@ class EmitCTrace final : public EmitCFunc { puts(")"); } puts(")"); + }; + puts("("); + if (AstFourstateExpr* const exprp = VN_CAST(nodep->valuep(), FourstateExpr)) { + AstVarRef* const valueVarrefp = VN_CAST(exprp->valuep(), VarRef); + AstVarRef* const xzVarrefp = VN_CAST(exprp->xzp(), VarRef); + if (valueVarrefp && xzVarrefp && valueVarrefp->varp() == xzVarrefp->varp()) { + UASSERT_OBJ(valueVarrefp->isWide() + && valueVarrefp->varp()->dtypep()->isShuffledFourstate(), + nodep, + "This shall only happen with wide shuffled four-state variables"); + putVarRef(valueVarrefp); + } else { + if (!valueVarrefp) { + iterateConst(exprp->valuep()); + } else { + putVarRef(valueVarrefp); + } + puts("), ("); + if (!xzVarrefp) { + iterateConst(exprp->xzp()); + } else { + putVarRef(xzVarrefp); + } + } + } else if (AstVarRef* const varrefp = VN_CAST(nodep->valuep(), VarRef)) { + putVarRef(varrefp); } else { puts("("); iterateConst(nodep->valuep()); emitTraceIndex(nodep, arrayindex); puts(")"); } + puts(")"); } void emitTraceIndex(const AstTraceInc* const nodep, int arrayindex) { diff --git a/src/V3EmitV.cpp b/src/V3EmitV.cpp index db0798e38..7a412aac4 100644 --- a/src/V3EmitV.cpp +++ b/src/V3EmitV.cpp @@ -639,6 +639,13 @@ class EmitVBaseVisitorConst VL_NOT_FINAL : public VNVisitorConst { iterateConst(nodep->exprp()); puts(";\n"); } + void visit(AstFourstateExpr* const nodep) override { + puts("Four-state expression: (Value part: "); + iterateConst(nodep->valuep()); + puts(", XZ part:"); + iterateConst(nodep->xzp()); + puts(")"); + } // Nodes involing AstText void visit(AstText* nodep) override { diff --git a/src/V3Error.h b/src/V3Error.h index 01e7d6447..2fcdcf207 100644 --- a/src/V3Error.h +++ b/src/V3Error.h @@ -90,6 +90,7 @@ public: CASEWITHX, // Case with X values CASEX, // Casex CASTCONST, // Cast is constant + CASTFOURSTATE, // Implicit logic (between 2/4 state logic) CDCRSTLOGIC, // Logic in async reset path. Historical, never issued. CLKDATA, // Clock used as data. Historical, never issued. CMPCONST, // Comparison is constant due to limited range @@ -226,24 +227,24 @@ public: " EC_FIRST_WARN", "ALWCOMBORDER", "ALWNEVER", "ASCRANGE", "ASSIGNDLY", "ASSIGNEQEXPR", "ASSIGNIN", "BADSTDPRAGMA", "BADVLTPRAGMA", "BLKANDNBLK", "BLKLOOPINIT", "BLKSEQ", "BSSPACE", "CASEINCOMPLETE", "CASEOVERLAP", "CASEWITHX", "CASEX", "CASTCONST", - "CDCRSTLOGIC", "CLKDATA", "CMPCONST", "COLONPLUS", "COMBDLY", "CONSTRAINTIGN", - "CONTASSREG", "COVERIGN", "DECLFILENAME", "DEFOVERRIDE", "DEFPARAM", "DEPRECATED", - "ENCAPSULATED", "ENDLABEL", "ENUMITEMWIDTH", "ENUMVALUE", "EOFNEWLINE", "FINALDLY", - "FSMMULTI", "FUNCTIMECTL", "FUTURE", "GENCLK", "GENUNNAMED", "HIERBLOCK", "HIERPARAM", - "IEEEMAYDEPRECATE", "IFDEPTH", "IGNOREDRETURN", "IMPERFECTSCH", "IMPLICIT", - "IMPLICITSTATIC", "IMPORTSTAR", "IMPURE", "INCABSPATH", "INFINITELOOP", "INITIALDLY", - "INSECURE", "INSIDETRUE", "LATCH", "LITENDIAN", "MINTYPMAXDLY", "MISINDENT", "MODDUP", - "MODMISSING", "MULTIDRIVEN", "MULTITOP", "NEWERSTD", "NOEFFECT", "NOLATCH", "NONSTD", - "NORETURN", "NOTREDOP", "NULLPORT", "PARAMNODEFAULT", "PINCONNECTEMPTY", "PINMISSING", - "PINNOCONNECT", "PINNOTFOUND", "PKGNODECL", "PREPROCZERO", "PROCASSINIT", - "PROCASSWIRE", "PROFOUTOFDATE", "PROTECTED", "PROTOTYPEMIS", "RANDC", "REALCVT", - "REDEFMACRO", "RISEFALLDLY", "SELRANGE", "SHORTREAL", "SIDEEFFECT", "SPECIFYIGN", - "SPLITVAR", "STATICVAR", "STMTDLY", "SUPERNFIRST", "SYMRSVDWORD", "SYNCASYNCNET", - "TICKCOUNT", "TIMESCALEMOD", "UNDRIVEN", "UNOPT", "UNOPTFLAT", "UNOPTTHREADS", - "UNPACKED", "UNSATCONSTR", "UNSIGNED", "UNUSED", "UNUSEDGENVAR", "UNUSEDLOOP", - "UNUSEDPARAM", "UNUSEDSIGNAL", "USERERROR", "USERFATAL", "USERINFO", "USERWARN", - "VARHIDDEN", "WAITCONST", "WIDTH", "WIDTHCONCAT", "WIDTHEXPAND", "WIDTHTRUNC", - "WIDTHXZEXPAND", "ZERODLY", "ZEROREPL", " MAX"}; + "CASTFOURSTATE", "CDCRSTLOGIC", "CLKDATA", "CMPCONST", "COLONPLUS", "COMBDLY", + "CONSTRAINTIGN", "CONTASSREG", "COVERIGN", "DECLFILENAME", "DEFOVERRIDE", "DEFPARAM", + "DEPRECATED", "ENCAPSULATED", "ENDLABEL", "ENUMITEMWIDTH", "ENUMVALUE", "EOFNEWLINE", + "FINALDLY", "FSMMULTI", "FUNCTIMECTL", "FUTURE", "GENCLK", "GENUNNAMED", "HIERBLOCK", + "HIERPARAM", "IEEEMAYDEPRECATE", "IFDEPTH", "IGNOREDRETURN", "IMPERFECTSCH", + "IMPLICIT", "IMPLICITSTATIC", "IMPORTSTAR", "IMPURE", "INCABSPATH", "INFINITELOOP", + "INITIALDLY", "INSECURE", "INSIDETRUE", "LATCH", "LITENDIAN", "MINTYPMAXDLY", + "MISINDENT", "MODDUP", "MODMISSING", "MULTIDRIVEN", "MULTITOP", "NEWERSTD", "NOEFFECT", + "NOLATCH", "NONSTD", "NORETURN", "NOTREDOP", "NULLPORT", "PARAMNODEFAULT", + "PINCONNECTEMPTY", "PINMISSING", "PINNOCONNECT", "PINNOTFOUND", "PKGNODECL", + "PREPROCZERO", "PROCASSINIT", "PROCASSWIRE", "PROFOUTOFDATE", "PROTECTED", + "PROTOTYPEMIS", "RANDC", "REALCVT", "REDEFMACRO", "RISEFALLDLY", "SELRANGE", + "SHORTREAL", "SIDEEFFECT", "SPECIFYIGN", "SPLITVAR", "STATICVAR", "STMTDLY", + "SUPERNFIRST", "SYMRSVDWORD", "SYNCASYNCNET", "TICKCOUNT", "TIMESCALEMOD", "UNDRIVEN", + "UNOPT", "UNOPTFLAT", "UNOPTTHREADS", "UNPACKED", "UNSATCONSTR", "UNSIGNED", "UNUSED", + "UNUSEDGENVAR", "UNUSEDLOOP", "UNUSEDPARAM", "UNUSEDSIGNAL", "USERERROR", "USERFATAL", + "USERINFO", "USERWARN", "VARHIDDEN", "WAITCONST", "WIDTH", "WIDTHCONCAT", + "WIDTHEXPAND", "WIDTHTRUNC", "WIDTHXZEXPAND", "ZERODLY", "ZEROREPL", " MAX"}; return names[m_e]; } // Warnings that default to off diff --git a/src/V3Expand.cpp b/src/V3Expand.cpp index f58474273..9b7cddd8b 100644 --- a/src/V3Expand.cpp +++ b/src/V3Expand.cpp @@ -937,7 +937,7 @@ class ExpandVisitor final : public VNVisitor { if (lhswidth == 1) { newp = new AstNegate{fl, lhsp->cloneTreePure(true)}; // Replicate always unsigned - newp->dtypeSetLogicSized(VL_EDATASIZE, VSigning::UNSIGNED); + newp->dtypeSetBitSized(VL_EDATASIZE, VSigning::UNSIGNED); } else { newp = newAstWordSelClone(lhsp, w); FileLine* const rfl = rhsp->fileline(); diff --git a/src/V3Fourstate.cpp b/src/V3Fourstate.cpp new file mode 100644 index 000000000..c92bad79a --- /dev/null +++ b/src/V3Fourstate.cpp @@ -0,0 +1,2529 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +//************************************************************************* +// DESCRIPTION: Verilator: Four-state logic handler +// +// Code available from: https://verilator.org +// +//************************************************************************* +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +//************************************************************************* +// +// - Splits four-state variables into two two-state variables +// - Handles wire conflicts +// +//************************************************************************* + +#include "V3PchAstNoMT.h" + +#include "V3Fourstate.h" + +#include "V3Const.h" +#include "V3Stats.h" +#include "V3UniqueNames.h" + +#include +#include +#include +#include + +VL_DEFINE_DEBUG_FUNCTIONS; + +/* TODOs: + * - Rest of operators + * - Statements - cases etc. + * - split asswignw into multiple statements + * - four-states printing + */ +namespace { +struct FourstatePair final { + AstNodeExpr* valuep; + AstNodeExpr* xzp; +}; + +enum LogicType : char { + UNINITIALIZED = 0, // Logic type has not been evaluated + TWO_STATE, // Two-state expression + TWO_STATE_HARD, // Expression is guaranteed by user that it won't be a four-state + // (propagator may not change it) + TWO_STATE_WITH_FOUR_STATE_IN_SUBTREE, // Two-state expression with four-state expression + // in its subtree - this is necessary since some + // AstNodes (e.g.: AstCastWrap or AstSel) may + // contain four-state expression as a child but + // itself be a two-state. When this occurs we need + // to know that for the sake of short-circuiting + // (because we use precalculation statements we need + // to know that we cannot put them before current + // expression unconditionally) + FOUR_STATE, // Four-state expression +}; + +static void setLogicType(AstNodeExpr* const exprp, const LogicType logic) { + exprp->user4(static_cast(logic)); +} + +static LogicType getLogicType(const AstNodeExpr* const exprp) { + return static_cast(exprp->user4()); +} + +static bool isTwostateHard(const AstNodeExpr* const exprp) { + return getLogicType(exprp) == TWO_STATE_HARD; +} + +static void setTwostate(AstNodeExpr* const exprp, bool hard = true) { + setLogicType(exprp, hard ? TWO_STATE_HARD : TWO_STATE); +} + +static void setFourstate(AstNodeExpr* const exprp, bool fourstate = true, + bool fourstateInSubTree = false) { + if (isTwostateHard(exprp)) return; + setLogicType(exprp, fourstate ? FOUR_STATE + : (fourstateInSubTree ? TWO_STATE_WITH_FOUR_STATE_IN_SUBTREE + : TWO_STATE)); +} + +static bool isFourstate(const AstNodeExpr* const exprp) { + const LogicType logic = getLogicType(exprp); + UASSERT_OBJ(logic != UNINITIALIZED, exprp, + "Logic type of expression: " << exprp->typeName() << " is unevaluated"); + return logic == FOUR_STATE; +} + +// Return true when the expression is two-state and has four-state expression in sub-tree +static bool hasFourstateInSubtree(const AstNodeExpr* const exprp) { + return getLogicType(exprp) == TWO_STATE_WITH_FOUR_STATE_IN_SUBTREE; +} + +template +struct ReducerTrait final : std::false_type {}; +template +struct ReducerTrait< + T, std::enable_if_t()(std::declval(), + std::declval())), + FourstatePair>::value>> + final : std::true_type {}; + +static bool isStaticallyGte(const V3Number& msb, const AstNodeExpr* const exprp) { + FileLine* const flp = exprp->fileline(); + const int exprpWidth = exprp->width(); + if (V3Number{flp, 1, 0} + .opGte(msb, V3Number{flp, exprpWidth, 0}.opSub( + V3Number{flp, exprpWidth, 0}.opShiftL( + V3Number{flp, exprpWidth, 1}, + V3Number{flp, exprpWidth, static_cast(exprpWidth)}), + V3Number{flp, exprpWidth, 1})) + .isEqOne()) { + return true; + } + if (const AstConst* const constp = VN_CAST(exprp, Const)) { + if (V3Number{flp, 1, 0}.opGte(msb, constp->num()).isEqOne()) return true; + } + return false; +} +static bool isStaticallyNGte(const V3Number& msb, const AstNodeExpr* const exprp) { + FileLine* const flp = exprp->fileline(); + if (const AstConst* const constp = VN_CAST(exprp, Const)) { + return constp->num().isAnyXZ() || V3Number{flp, 1, 0}.opLt(msb, constp->num()).isNeqZero(); + } + return false; +} +static bool needsSplitting(const AstNodeDType* const dtypep) { + if (const AstBasicDType* const basicp = VN_CAST(dtypep->skipRefp(), BasicDType)) { + return basicp->isFourstate(); + } + return false; +} + +class FTaskPortsHelper final { + std::vector + m_currentFTaskRefPortps; // Ports of FTask in order so we can connect AstArgs to them + std::map + m_currentFTaskRefPortpsNamesToVarps; // Ports names to their Vars so we can handle + // named arguments + +public: + explicit FTaskPortsHelper(const AstNodeFTask* const ftaskp) { + // TODO: Add caching + UASSERT_OBJ(m_currentFTaskRefPortps.empty(), ftaskp, + "Tried to build a port map while another exists"); + UASSERT_OBJ(m_currentFTaskRefPortpsNamesToVarps.empty(), ftaskp, + "Tried to build a port map while another exists"); + for (AstNode* stmtp = ftaskp->stmtsp(); stmtp; stmtp = stmtp->nextp()) { + if (AstVar* const varp = VN_CAST(stmtp, Var)) { + if (varp->direction().isAny() && !varp->isFourstateConstruct()) { + m_currentFTaskRefPortps.push_back(varp); + m_currentFTaskRefPortpsNamesToVarps[varp->name()] = varp; + } + } + } + } + + AstVar* getArgPortVar(const std::string& name, const size_t idx) const { + return name.empty() ? m_currentFTaskRefPortps.at(idx) + : m_currentFTaskRefPortpsNamesToVarps.at(name); + } + AstVar* lastp() const { + return m_currentFTaskRefPortps.empty() ? nullptr : m_currentFTaskRefPortps.back(); + } +}; +} // namespace + +// Propagates the logic type (two or four-state) on AstNodeExpr +// Needed as V3Width not always gives a correct logic type +class FourstateLogicTypePropagator final : public VNVisitor { + bool m_fourstateInSubtree + = false; // Whether a four-state expression is present in a sub-tree of an expression + + void iterateChildrenSeparately(AstNode* const nodep) { + auto foreach = [this](AstNode* nodep) { + bool fourstateInSubtree = false; + for (; nodep; nodep = nodep->nextp()) { + m_fourstateInSubtree = false; + iterate(nodep); + fourstateInSubtree |= m_fourstateInSubtree; + } + return fourstateInSubtree; + }; + // Cast to char so, there is no warnings + m_fourstateInSubtree = static_cast(static_cast(foreach(nodep->op1p())) + | static_cast(foreach(nodep->op2p())) + | static_cast(foreach(nodep->op3p())) + | static_cast(foreach(nodep->op4p()))); + } + + void visit(AstConst* const nodep) override { + iterateChildrenSeparately(nodep); + setFourstate(nodep, nodep->num().isAnyXZ(), m_fourstateInSubtree); + m_fourstateInSubtree |= isFourstate(nodep); + } + + void visit(AstNodeVarRef* const nodep) override { + setFourstate(nodep, needsSplitting(nodep->varp()->dtypep()), m_fourstateInSubtree); + m_fourstateInSubtree |= isFourstate(nodep); + } + + void visit(AstNodeFTaskRef* const nodep) override { + iterateChildrenSeparately(nodep); + setFourstate(nodep, + nodep->taskp()->fvarp() && needsSplitting(nodep->taskp()->fvarp()->dtypep()), + m_fourstateInSubtree); + m_fourstateInSubtree |= isFourstate(nodep); + } + + void visit(AstNodeUniop* const nodep) override { + iterateChildrenSeparately(nodep); + setFourstate(nodep, isFourstate(nodep->lhsp()), m_fourstateInSubtree); + } + + void visit(AstCastWrap* const nodep) override { + iterateChildrenSeparately(nodep); + setFourstate(nodep, needsSplitting(nodep->dtypep()), m_fourstateInSubtree); + m_fourstateInSubtree |= isFourstate(nodep); + } + + void visit(AstNodeBiop* const nodep) override { + iterateChildrenSeparately(nodep); + setFourstate(nodep, isFourstate(nodep->lhsp()) || isFourstate(nodep->rhsp()), + m_fourstateInSubtree); + } + + void visit(AstEqCase* const nodep) override { + iterateChildrenSeparately(nodep); + setFourstate(nodep, false, m_fourstateInSubtree); + } + + void visit(AstNeqCase* const nodep) override { + iterateChildrenSeparately(nodep); + setFourstate(nodep, false, m_fourstateInSubtree); + } + + void visit(AstDiv* nodep) override { + iterateChildrenSeparately(nodep); + if (AstConst* const constp = VN_CAST(nodep->rhsp(), Const)) { + setFourstate(nodep, + isFourstate(nodep->lhsp()) || constp->num().isEqZero() + || constp->num().isAnyXZ(), + m_fourstateInSubtree); + } else { + setFourstate(nodep, true, m_fourstateInSubtree); + } + m_fourstateInSubtree |= isFourstate(nodep); + } + + void visit(AstNodeTriop* const nodep) override { + iterateChildrenSeparately(nodep); + setFourstate(nodep, + isFourstate(nodep->lhsp()) || isFourstate(nodep->rhsp()) + || isFourstate(nodep->thsp()), + m_fourstateInSubtree); + } + + void visit(AstCReset* const nodep) override { + iterateChildrenSeparately(nodep); + setFourstate(nodep, false, m_fourstateInSubtree); + } + + void visit(AstSFormatArg* const nodep) override { + iterateChildrenSeparately(nodep); + setFourstate(nodep, isFourstate(nodep->exprp()), m_fourstateInSubtree); + } + + void visit(AstSel* const nodep) override { + iterateChildrenSeparately(nodep); + setFourstate(nodep, isFourstate(nodep->fromp()), m_fourstateInSubtree); + } + + void visit(AstCExprUser* const nodep) override { + iterateChildrenSeparately(nodep); + setFourstate(nodep, false, m_fourstateInSubtree); + } + + void visit(AstRedOr* const nodep) override { + iterateChildrenSeparately(nodep); + setFourstate(nodep, isFourstate(nodep->lhsp()), m_fourstateInSubtree); + } + + void visit(AstTime* const nodep) override { + iterateChildrenSeparately(nodep); + // Time is actually a fourstate but we never put `x` or `z` there + setFourstate(nodep, false, m_fourstateInSubtree); + } + + void visit(AstScopeName* const nodep) override { + iterateChildrenSeparately(nodep); + setFourstate(nodep, false, m_fourstateInSubtree); + } + + void visit(AstClassOrPackageRef* const nodep) override { + iterateChildrenSeparately(nodep); + setFourstate(nodep, false, m_fourstateInSubtree); + } + + // void visit(AstCMethodHard* const nodep) override { + // iterateChildrenSeparately(nodep); + // setFourstate(nodep, false, m_fourstateInSubtree); + // } + + void visit(AstCExpr* const nodep) override { + iterateChildrenSeparately(nodep); + setFourstate(nodep, false, m_fourstateInSubtree); + } + + void visit(AstRand* const nodep) override { + iterateChildrenSeparately(nodep); + setFourstate(nodep, false, m_fourstateInSubtree); + } + + // void visit(AstRandRNG* const nodep) override { + // iterateChildrenSeparately(nodep); + // setFourstate(nodep, false, m_fourstateInSubtree); + // } + + void visit(AstMemberSel* const nodep) override { + iterateChildrenSeparately(nodep); + setFourstate(nodep, needsSplitting(nodep->varp()->dtypep()), m_fourstateInSubtree); + } + + void visit(AstSFormatF* const nodep) override { + iterateChildrenSeparately(nodep); + setFourstate(nodep, false, m_fourstateInSubtree); + } + + void visit(AstStructSel* const nodep) override { + iterateChildrenSeparately(nodep); + setFourstate(nodep, isFourstate(nodep->fromp()), m_fourstateInSubtree); + } + + // void visit(AstExprStmt* const nodep) override { + // iterateChildrenSeparately(nodep); + // setFourstate(nodep, isFourstate(nodep->resultp()), m_fourstateInSubtree); + // } + + // void visit(AstConsPackMember* const nodep) override { + // iterateChildrenSeparately(nodep); + // setFourstate(nodep, isFourstate(nodep->rhsp()), m_fourstateInSubtree); + // } + + void visit(AstFOpen* const nodep) override { + iterateChildrenSeparately(nodep); + setFourstate(nodep, false, m_fourstateInSubtree); + } + + // void visit(AstFOpenMcd* const nodep) override { + // iterateChildrenSeparately(nodep); + // setFourstate(nodep, false, m_fourstateInSubtree); + // } + + // void visit(AstLambdaArgRef* const nodep) override { + // iterateChildrenSeparately(nodep); + // setFourstate(nodep, needsSplitting(nodep->dtypep()), m_fourstateInSubtree); + // } + + // void visit(AstTestPlusArgs* const nodep) override { + // iterateChildrenSeparately(nodep); + // setFourstate(nodep, false, m_fourstateInSubtree); + // } + + // void visit(AstValuePlusArgs* const nodep) override { + // iterateChildrenSeparately(nodep); + // setFourstate(nodep, false, m_fourstateInSubtree); + // } + + // void visit(AstCvtArrayToPacked* const nodep) override { + // iterateChildrenSeparately(nodep); + // setFourstate(nodep, needsSplitting(nodep->fromp()->dtypep()), m_fourstateInSubtree); + // } + + void visit(AstSScanF* const nodep) override { + iterateChildrenSeparately(nodep); + setFourstate(nodep, false, m_fourstateInSubtree); + } + + // void visit(AstFScanF* const nodep) override { // We want to get UNSUPPORTED error right now + // iterateChildrenSeparately(nodep); + // setFourstate(nodep, false, m_fourstateInSubtree); + // } + + void visit(AstFourstateExpr* const nodep) override { + iterateChildrenSeparately(nodep); + // The `false` is a lie but this visitor is here just for debug purposes so, after + // FourstateVisitor we can check whether any four-state expression has not been handled. + // This lie is safe since before V3Fourstate no AstFourstateExpr exists + setFourstate(nodep, false, m_fourstateInSubtree); + } + + void visit(AstNodeExpr* const nodep) override { + iterateChildrenSeparately(nodep); + if (AstBasicDType* const basicp = VN_CAST(nodep->dtypep()->skipRefOrNullp(), BasicDType)) { + if (basicp->keyword().isIntNumeric()) { + nodep->v3warn(E_UNSUPPORTED, "Unsupported: Operator " + << nodep->typeName() + << " not supported in the four-state mode"); + } + } + setFourstate(nodep, false, m_fourstateInSubtree); // Set an arbitrary logic type + } + + void visit(AstNode* nodep) override { + VL_RESTORER(m_fourstateInSubtree); + iterateChildrenSeparately(nodep); + } + +public: + FourstateLogicTypePropagator(AstNode* const nodep) { iterate(nodep); } + ~FourstateLogicTypePropagator() override = default; +}; + +// Splits AstVar of four-state type into two two-states +// Transforms four-state logic expressions into two-states +// Handles AssignW conflict resolution +class FourstateVisitor final : public VNVisitor { + const VNUser1InUse m_user1InUse; + const VNUser2InUse m_user2InUse; + const VNUser3InUse m_user3InUse; + const VNUser4InUse m_user4InUse; + // Node status + // AstVar::user1p -> AstVar*. Where is value part of splitted variable - xz + // AstNodeExpr::user1p -> AstNodeExpr*. Expression evaluating value component + // AstNodeExpr::user2p -> AstNodeExpr*. Expression evaluating xz component + // AstSel::user3 -> bool. Whether it has been handled + // AstNodeFTaskRef::user3 -> bool. Whether it has been handled + // AstNodeExpr::user4 -> LogicType. Expression logic type (whether it is four + // or two state) + + static void setValuePartVarp(AstVar* const varp, AstVar* const valuep) { + varp->user1p(valuep); + } + static AstVar* getValuePartVarp(AstVar* const varp) { return VN_AS(varp->user1p(), Var); } + static void setSelpHandled(AstSel* const selp) { selp->user3(1); } + static bool isSelpHandled(AstSel* const selp) { return selp->user3(); } + static void setFTaskRefHandled(AstNodeFTaskRef* const ftaskRefp) { ftaskRefp->user3(1); } + static bool isFTaskRefHandled(AstNodeFTaskRef* const ftaskRefp) { return ftaskRefp->user3(); } + static void setExprValuep(AstNodeExpr* const fourstateExprp, AstNode* const valuep) { + fourstateExprp->user1p(valuep); + } + static AstNodeExpr* getExprValuep(const AstNodeExpr* const fourstateExprp) { + return VN_AS(fourstateExprp->user1p(), NodeExpr); + } + static void setExprXZp(AstNodeExpr* const fourstateExprp, AstNode* const xzp) { + fourstateExprp->user2p(xzp); + } + static AstNodeExpr* getExprXZp(const AstNodeExpr* const fourstateExprp) { + return VN_AS(fourstateExprp->user2p(), NodeExpr); + } + + V3UniqueNames m_tmpNames; // Unique names generator for temporary variables + + AstNode* m_currentTmpSpotp = nullptr; // Node after which put AstVar* for temporary variable + bool m_tmpFuncLocal + = false; // Whether temporary variables shall be created as function locals + AstNodeStmt* m_currentStmtp = nullptr; // Current statement + std::vector m_varpsToRemove; // Vars to unlink and remove in destructor + + std::vector m_ftaskPortHelpers; // Cache of FTaskPortsHelpers + + // array - whether numeric + // map - width + std::array>, 2> + m_tmpUnusedVarps; // Existing not in use temporary variables + std::vector m_tmpVarpsInUse; // Temporary variables that are being currently used + + // Original AstVar* and pair of assignments + using NetToAssignwps + = std::map>>; + NetToAssignwps m_assignWToTrior; // Map from variables to their AssingWs + NetToAssignwps m_assignWToTriand; // Map from variables to their AssingWs + NetToAssignwps m_assignWToWire; // Map from variables to their AssingWs + + static FourstatePair triReducer(const FourstatePair& a, const FourstatePair& b) { + FileLine* const flp = a.valuep->fileline(); + FourstatePair result; + { + // a.value | b.value + result.valuep = new AstOr{flp, a.valuep, b.valuep}; + } + { + // (a.value & a.xz) | (b.value & b.xz) | (a.xz & b.xz) | (a.value & ~b.value & ~b.xz) | + // (b.value & ~a.value & ~a.xz) + result.xzp = new AstOr{ + flp, + new AstOr{flp, + new AstOr{flp, new AstAnd{flp, a.valuep->cloneTree(false), a.xzp}, + new AstAnd{flp, b.valuep->cloneTree(false), b.xzp}}, + new AstAnd{flp, a.xzp->cloneTree(false), b.xzp->cloneTree(false)}}, + new AstOr{flp, + new AstAnd{flp, + new AstAnd{flp, a.valuep->cloneTree(false), + new AstNot{flp, b.valuep->cloneTree(false)}}, + new AstNot{flp, b.xzp->cloneTree(false)}}, + new AstAnd{flp, + new AstAnd{flp, b.valuep->cloneTree(false), + new AstNot{flp, a.valuep->cloneTree(false)}}, + new AstNot{flp, a.xzp->cloneTree(false)}}}}; + } + return result; + } + static FourstatePair triandReducer(const FourstatePair& a, const FourstatePair& b) { + FileLine* const flp = a.valuep->fileline(); + FourstatePair result; + { + // (a.value & b.xz) | (b.value & a.xz) | (a.value & b.value) + result.valuep = new AstOr{ + flp, + new AstOr{flp, new AstAnd{flp, a.valuep, b.xzp}, new AstAnd{flp, b.valuep, a.xzp}}, + new AstAnd{flp, a.valuep->cloneTree(false), b.valuep->cloneTree(false)}}; + } + { + // (a.xz & b.xz) | (a.value & b.value & a.xz) | (a.value & b.value & b.xz) + result.xzp = new AstOr{ + flp, + new AstOr{flp, new AstAnd{flp, a.xzp->cloneTree(false), b.xzp->cloneTree(false)}, + new AstAnd{flp, + new AstAnd{flp, a.valuep->cloneTree(false), + b.valuep->cloneTree(false)}, + b.xzp->cloneTree(false)}}, + new AstAnd{flp, + new AstAnd{flp, a.valuep->cloneTree(false), b.valuep->cloneTree(false)}, + b.xzp->cloneTree(false)}}; + } + return result; + } + static FourstatePair triorReducer(const FourstatePair& a, const FourstatePair& b) { + FileLine* const flp = a.valuep->fileline(); + FourstatePair result; + { + // a.value | b.value + result.valuep = new AstOr{flp, a.valuep, b.valuep}; + } + { + // (a.value | b.xz) & (b.value | a.xz) & (a.xz | ~a.value) & (b.xz | ~b.value) + result.xzp + = new AstAnd{flp, + new AstAnd{flp, new AstOr{flp, a.valuep->cloneTree(false), b.xzp}, + new AstOr{flp, b.valuep->cloneTree(false), a.xzp}}, + new AstAnd{flp, + new AstOr{flp, a.xzp->cloneTree(false), + new AstNot{flp, a.valuep->cloneTree(false)}}, + new AstOr{flp, b.xzp->cloneTree(false), + new AstNot{flp, b.valuep->cloneTree(false)}}}}; + } + return result; + } + + template + static FourstatePair buildTree(std::vector exprps, Reducer_T&& reducer) { + static_assert(ReducerTrait::value, "Reducer_T shall fullfill reducer trait"); + while (exprps.size() > 1) { + const size_t halfSize = exprps.size() / 2; + for (size_t i = 0; i < halfSize; ++i) { + exprps[i] = reducer(exprps[i], exprps.back()); + exprps.pop_back(); + } + } + return exprps[0]; + } + + template + static void triorTriandReduce(const NetToAssignwps& assignWs, Reducer_T&& reducer) { + for (const auto& pair : assignWs) { + const auto& assignps = pair.second; + if (assignps.size() < 2) continue; + std::vector exprps; + exprps.reserve(assignps.size()); + for (const auto& assignp : assignps) { + exprps.push_back({assignp.first->rhsp()->unlinkFrBack(), + assignp.second->rhsp()->unlinkFrBack()}); + const AstVarXRef* xarefp = nullptr; + if (exprps.back().valuep->exists([&xarefp](const AstVarXRef* const refp) { + xarefp = refp; + return true; + })) { + // The issue is when hierarchical reference is being moved to another module. + // Then it shall be fixed + xarefp->v3warn( + E_UNSUPPORTED, + "Hierarchical references are unsupported in assigns with --fourstate"); + } + } + FourstatePair result = buildTree(std::move(exprps), reducer); + assignps[0].first->rhsp(result.valuep); + assignps[0].second->rhsp(result.xzp); + for (size_t i = 1; i < assignps.size(); ++i) { + assignps[i].first->unlinkFrBack()->deleteTree(); + assignps[i].second->unlinkFrBack()->deleteTree(); + } + } + } + + static AstConst* createZeroOrOnesp(const AstNodeExpr* const exprp, const bool ones = false) { + AstConst* const resultp + = new AstConst{exprp->fileline(), AstConst::WidthedValue{}, exprp->width(), 0}; + resultp->dtypeSetBitUnsized(exprp->width(), exprp->widthMin(), exprp->dtypep()->numeric()); + if (ones) resultp->num().setAllBits1(); + setFourstate(resultp, false); + return resultp; + } + + // {whether supported, whether four state} - second is needed for the recursion + static std::pair isDTypepSupported(const AstNodeDType* const dtypep) { + if (const AstBasicDType* const basicp = VN_CAST(dtypep, BasicDType)) { + return {true, basicp->isFourstate()}; + } + if (const AstNodeUOrStructDType* const containerDTypep + = VN_CAST(dtypep, NodeUOrStructDType)) { + return {!containerDTypep->isFourstate(), containerDTypep->isFourstate()}; + } + if (const AstSampleQueueDType* const containerDTypep = VN_CAST(dtypep, SampleQueueDType)) { + std::pair subDtype + = isDTypepSupported(containerDTypep->subDTypep()->skipRefp()); + return {subDtype.first && !subDtype.second, false}; + } + if (const AstQueueDType* const containerDTypep = VN_CAST(dtypep, QueueDType)) { + std::pair subDtype + = isDTypepSupported(containerDTypep->subDTypep()->skipRefp()); + return {subDtype.first && !subDtype.second, false}; + } + if (const AstAssocArrayDType* const containerDTypep = VN_CAST(dtypep, AssocArrayDType)) { + std::pair subDtype + = isDTypepSupported(containerDTypep->subDTypep()->skipRefp()); + return {subDtype.first && !subDtype.second, false}; + } + if (const AstUnpackArrayDType* const containerDTypep = VN_CAST(dtypep, UnpackArrayDType)) { + std::pair subDtype + = isDTypepSupported(containerDTypep->subDTypep()->skipRefp()); + return {subDtype.first && !subDtype.second, false}; + } + if (const AstPackArrayDType* const containerDTypep = VN_CAST(dtypep, PackArrayDType)) { + std::pair subDtype + = isDTypepSupported(containerDTypep->subDTypep()->skipRefp()); + return {subDtype.first && !subDtype.second, false}; + } + return {true, false}; + } + + void assignWConflictResolution(AstVar* const varp, AstAssignW* const assignwValuep, + AstAssignW* const assignwXzp) { + // Assignments to different things are unsupported + switch (varp->varType()) { + case VVarType::TRIOR: + m_assignWToTrior[varp].emplace_back(assignwValuep, assignwXzp); + break; + case VVarType::TRIAND: + m_assignWToTriand[varp].emplace_back(assignwValuep, assignwXzp); + break; + case VVarType::VAR: + case VVarType::TRIWIRE: + case VVarType::PORT: // The issue with ports is that we lose information about the wire + // type (tri/triand/trior) + case VVarType::WIRE: m_assignWToWire[varp].emplace_back(assignwValuep, assignwXzp); break; + case VVarType::SUPPLY0: + case VVarType::SUPPLY1: + case VVarType::TRI0: + case VVarType::TRI1: + varp->v3warn(E_UNSUPPORTED, + "supply0/tri0 and supply1/tri1 are not supported with --fourstate"); + break; + default: // LCOV_EXCL_LINE + assignwValuep->v3fatalSrc( + "Unexpected variable type on lhs of assign: " << varp->varType().ascii()); + break; + } + } + + class StatementPlaceHolder final { + FourstateVisitor& m_visitor; + AstNodeStmt* const m_prevStmtp; + AstNodeStmt* const m_stmtp; + + public: + explicit StatementPlaceHolder(FourstateVisitor& visitor, FileLine* const flp) + : m_visitor{visitor} + , m_prevStmtp{m_visitor.m_currentStmtp} + , m_stmtp{new AstStmtExpr{flp, new AstConst{flp, 0}}} { + m_visitor.m_currentStmtp = m_stmtp; + } + ~StatementPlaceHolder() { + UASSERT_OBJ(m_stmtp->backp(), m_stmtp, + "Placeholder statement never used - maybe it is unnecessary?"); + m_stmtp->unlinkFrBack()->deleteTree(); + m_visitor.m_currentStmtp = m_prevStmtp; + } + AstNodeStmt* stmtp() const { return m_stmtp; } + }; + + struct TmpVarsReleaser final { + FourstateVisitor& m_visitor; + const size_t m_tmpVarpsInUseLen; + explicit TmpVarsReleaser(FourstateVisitor& visitor) + : m_visitor{visitor} + , m_tmpVarpsInUseLen{m_visitor.m_tmpVarpsInUse.size()} {} + ~TmpVarsReleaser() { + UASSERT(m_tmpVarpsInUseLen <= m_visitor.m_tmpVarpsInUse.size(), + "There is less used tmp variables than before"); + for (size_t i = m_tmpVarpsInUseLen; i < m_visitor.m_tmpVarpsInUse.size(); ++i) { + AstVar* const varp = m_visitor.m_tmpVarpsInUse[i]; + m_visitor + .m_tmpUnusedVarps[varp->dtypep()->numeric().isSigned() ? 1 : 0][varp->width()] + .push_back(varp); + } + m_visitor.m_tmpVarpsInUse.resize(m_tmpVarpsInUseLen); + } + }; + + // Takes expression or AstVar and creates a new temporary variable + AstVar* createTmp(AstNode* const nodep) { + UASSERT_OBJ( + VN_IS(nodep, NodeExpr) || VN_IS(nodep, Var), nodep, + "This function shall only be called on expressions or variables, but was called on: " + << nodep); + UASSERT_OBJ(m_currentTmpSpotp, nodep, "No where to place tmp variable"); + AstNodeDType* const dtypep = nodep->dtypep(); + auto& pool = m_tmpUnusedVarps[dtypep->numeric().isSigned() ? 1 : 0]; + if (!pool[dtypep->width()].empty()) { + AstVar* varp = pool[dtypep->width()].back(); + pool[dtypep->width()].pop_back(); + return varp; + } + AstVar* const varp = new AstVar{nodep->fileline(), VVarType::STMTTEMP, + m_tmpNames.get(nodep), VFlagBitPacked{}, nodep->width()}; + m_currentTmpSpotp->addHereThisAsNext(varp); + varp->funcLocal(m_tmpFuncLocal); + varp->noSubst(true); + m_tmpVarpsInUse.push_back(varp); + return varp; + } + + void splitVar(AstVar* const varp) { + UASSERT_OBJ(needsSplitting(varp->dtypep()), varp, + "Split shall be called only on four-state variables"); + if (getValuePartVarp(varp)) return; + m_varpsToRemove.push_back(varp); + if (AstNodeFTask* const ftaskp = VN_CAST(varp->backp(), NodeFTask)) { + if (ftaskp->fvarp() == varp) { + AstVar* const portEndp = getFTaskPortHelper(ftaskp).lastp(); + AstVar* const returnValuep + = new AstVar{varp->fileline(), VVarType::PORT, varp->name() + VALUE_SUFFIX, + VFlagBitPacked{}, varp->width()}; + AstVar* const returnXzp + = new AstVar{varp->fileline(), VVarType::PORT, varp->name() + XZ_SUFFIX, + VFlagBitPacked{}, varp->width()}; + returnValuep->direction(VDirection::OUTPUT); + returnXzp->direction(VDirection::OUTPUT); + returnValuep->funcLocal(true); + returnXzp->funcLocal(true); + returnValuep->lifetime(VLifetime::AUTOMATIC_IMPLICIT); + returnXzp->lifetime(VLifetime::AUTOMATIC_IMPLICIT); + returnValuep->trace(varp->isTrace()); + returnValuep->fourstateOriginalDTypeKwd(varp->dtypep()->basicp()->keyword()); + returnXzp->fourstateOriginalDTypeKwd(varp->dtypep()->basicp()->keyword()); + FileLine* const flp = varp->fileline(); + // CReset is not used because V3Task may inline function call and then CReset will + // be assigned to tmp variable - which does not contain information whether it is + // uased as an complement or what + AstConst* const constp + = new AstConst{flp, AstConst::DTyped{}, returnXzp->dtypep()}; + constp->num().setAllBits1(); + AstAssign* const valueResetp + = new AstAssign{flp, new AstVarRef{flp, returnValuep, VAccess::WRITE}, + constp->cloneTree(false)}; + AstAssign* const xzResetp + = new AstAssign{flp, new AstVarRef{flp, returnXzp, VAccess::WRITE}, constp}; + if (portEndp) { + portEndp->addNextHere(xzResetp); + portEndp->addNextHere(valueResetp); + portEndp->addNextHere(returnXzp); + portEndp->addNextHere(returnValuep); + } else if (AstNode* const stmtp = ftaskp->stmtsp()) { + stmtp->addHereThisAsNext(returnValuep); + stmtp->addHereThisAsNext(returnXzp); + stmtp->addHereThisAsNext(valueResetp); + stmtp->addHereThisAsNext(xzResetp); + } else { + ftaskp->addStmtsp(returnValuep); + ftaskp->addStmtsp(returnXzp); + ftaskp->addStmtsp(valueResetp); + ftaskp->addStmtsp(xzResetp); + } + FourstateLogicTypePropagator{ftaskp}; + setValuePartVarp(varp, returnValuep); + returnValuep->fourstateComplementp(returnXzp); + ftaskp->dtypeSetVoid(); + return; + } + } + AstVar* const newXzp = varp->cloneTree(false); + newXzp->name(newXzp->name() + XZ_SUFFIX); + newXzp->fourstateOriginalDTypeKwd(varp->dtypep()->basicp()->keyword()); + newXzp->dtypeSetBitUnsized(varp->width(), varp->widthMin(), varp->dtypep()->numeric()); + if (AstNodeExpr* const valuep = VN_CAST(newXzp->valuep(), NodeExpr)) { + valuep->unlinkFrBack(); + newXzp->valuep(getFourstateExpressionXZ(valuep)); + valuep->deleteTree(); + } + varp->addNextHere(newXzp); + AstVar* const newValuep = varp->cloneTree(false); + newValuep->name(newValuep->name() + VALUE_SUFFIX); + newValuep->trace(varp->isTrace()); + newValuep->fourstateOriginalDTypeKwd(varp->dtypep()->basicp()->keyword()); + newValuep->dtypeSetBitUnsized(varp->width(), varp->widthMin(), varp->dtypep()->numeric()); + if (AstNodeExpr* const valuep = VN_CAST(newValuep->valuep(), NodeExpr)) { + valuep->unlinkFrBack(); + newValuep->valuep(getFourstateExpressionValue(valuep)); + valuep->deleteTree(); + } + newValuep->fourstateComplementp(newXzp); + varp->addNextHere(newValuep); + setValuePartVarp(varp, newValuep); + } + + static AstVar* getSplittedValue(AstVar* const varp) { + UASSERT_OBJ(needsSplitting(varp->dtypep()), varp, + "Split shall be called only on four-state variables"); + AstVar* const result = getValuePartVarp(varp); + UASSERT_OBJ(result, varp, "Variable shall be split first"); + return result; + } + + static AstVar* getSplittedXZ(AstVar* const varp) { + return getSplittedValue(varp)->fourstateComplementp(); + } + + const FTaskPortsHelper& getFTaskPortHelper(AstNodeFTask* const ftaskp) { + if (ftaskp->user1()) return m_ftaskPortHelpers[ftaskp->user1() - 1]; + ftaskp->user1(m_ftaskPortHelpers.size() + 1); + m_ftaskPortHelpers.emplace_back(static_cast(ftaskp)); + return m_ftaskPortHelpers.back(); + } + + void addPrecalculation(AstNodeStmt* const nodep) { + FourstateLogicTypePropagator{nodep}; + m_currentStmtp->addHereThisAsNext(nodep); + } + + AstNodeExpr* getFourstateExpressionSelHandler(AstSel* const selp, + AstNodeExpr* const valueExprp, + const bool defaultsToZero) { + FileLine* const flp = selp->fileline(); + AstNodeExpr* lsbp = selp->lsbp(); + V3Number maxmsb{flp, 32, static_cast(selp->fromp()->dtypep()->width() - 1)}; + if (isStaticallyNGte(maxmsb, lsbp)) { + if (!selp->fromp()->isPure()) { + addPrecalculation(new AstStmtExpr{flp, valueExprp}); + // No precalculation of lsbp because right now: + // isStaticallyNGte(lsbp) => VN_IS(lsbp, Const) + } else { + valueExprp->deleteTree(); + } + return createZeroOrOnesp(selp, !defaultsToZero); + } + AstSel* const newp = [selp] { + AstNodeExpr* const fromp = selp->fromp()->unlinkFrBack(); + AstNodeExpr* const lsbp = selp->lsbp()->unlinkFrBack(); + AstSel* const newp = selp->cloneTree(false); + selp->fromp(fromp); + selp->lsbp(lsbp); + return newp; + }(); + setSelpHandled(newp); + newp->fromp(valueExprp); + const bool isStaticallyInRange = isStaticallyGte(maxmsb, lsbp); + const bool isLsbpFourstete = isFourstate(lsbp); + if (isStaticallyInRange && !isLsbpFourstete) { + newp->lsbp(lsbp->cloneTree(false)); + return newp; + } + AstNodeExpr* conditionp; + if (isLsbpFourstete) { + conditionp = getFourstateExpressionXZ(lsbp, isFourstate(selp)); + if (!isStaticallyInRange) { + conditionp = new AstOr{flp, conditionp, + new AstLt{flp, new AstConst{flp, maxmsb}, + getFourstateExpressionValue(lsbp, true)}}; + } + lsbp = getFourstateExpressionValue(lsbp, true); + } else { + if (!VN_IS(lsbp, + NodeVarRef) /*&& !VN_IS(lsbp, Const)*/) { // Not being a Cosnt is + // guarateed by logic above - if + // lsbp is a AstConst then it is + // either statically inside or + // outside range + AstVar* const lsbTmpp = createTmp(lsbp); + addPrecalculation(new AstAssign{flp, new AstVarRef{flp, lsbTmpp, VAccess::WRITE}, + lsbp->cloneTree(false)}); + lsbp = new AstVarRef{flp, lsbTmpp, VAccess::READ}; + } else { + lsbp = lsbp->cloneTree(false); + } + conditionp = new AstLt{flp, new AstConst{flp, maxmsb}, lsbp->cloneTree(false)}; + } + newp->lsbp(lsbp); + return new AstCond{flp, conditionp, createZeroOrOnesp(selp, !defaultsToZero), newp}; + } + + // Base visitor for Value and XZ visitor, contains some common functionalities + class FourstateExpressionVisitor VL_NOT_FINAL : public VNVisitor { + protected: + FourstateVisitor& m_fourstateVisitor; + AstNodeExpr* m_resultp = nullptr; + + private: + bool m_noTmp = false; + bool m_enforceTmp = false; + + virtual AstNodeExpr* getCache(const AstNodeExpr* keyp) = 0; + virtual void setCache(AstNodeExpr* keyp, AstNodeExpr* valuep) = 0; + + protected: + void noTmp() { m_noTmp = true; } + void enforceTmp() { m_enforceTmp = true; } + + void addPrecalculation(AstNodeStmt* const nodep) { + FourstateLogicTypePropagator{nodep}; + m_fourstateVisitor.m_currentStmtp->addHereThisAsNext(nodep); + } + + void fourstateExpressionFuncRefHandler(AstNodeFTaskRef* const funcRefp) { + // Its ok to use this instead of output since we only need width which is the same + AstVar* const functionReturnVarp = VN_AS(VN_AS(funcRefp->taskp(), Func)->fvarp(), Var); + AstVar* const resultValuep = m_fourstateVisitor.createTmp(functionReturnVarp); + AstVar* const resultXzp = m_fourstateVisitor.createTmp(functionReturnVarp); + AstNodeFTaskRef* const newCallp = funcRefp->cloneTree(false); + UASSERT_OBJ(!isFTaskRefHandled(newCallp), funcRefp, + "Trying to handle already handled four-state function call"); + setFTaskRefHandled(newCallp); + if (newCallp->argsp()) newCallp->argsp()->unlinkFrBackWithNext()->deleteTree(); + FileLine* const flp = funcRefp->fileline(); + { + size_t argIdx = 0; + const FTaskPortsHelper& ftaskPortsHelper + = m_fourstateVisitor.getFTaskPortHelper(funcRefp->taskp()); + for (AstArg* argp = funcRefp->argsp(); argp; argp = VN_AS(argp->nextp(), Arg)) { + const AstVar* const varp + = ftaskPortsHelper.getArgPortVar(argp->name(), argIdx); + ++argIdx; + if (needsSplitting(varp->dtypep())) { + newCallp->addArgsp(new AstArg{ + flp, "", getFourstateExpressionValue(argp->exprp(), false)}); + newCallp->addArgsp( + new AstArg{flp, "", getFourstateExpressionXZ(argp->exprp(), false)}); + } else if (isFourstate(argp->exprp())) { + newCallp->addArgsp(new AstArg{ + flp, "", m_fourstateVisitor.getTwoStateCast(argp->exprp())}); + } else { + newCallp->addArgsp(argp->cloneTree(false)); + } + } + } + AstVarRef* const resultValueRefp = new AstVarRef{flp, resultValuep, VAccess::WRITE}; + AstVarRef* const resultXzRefp = new AstVarRef{flp, resultXzp, VAccess::WRITE}; + setFourstate(resultValueRefp, false); + setFourstate(resultXzRefp, false); + { + std::string resultName = funcRefp->taskp()->fvarp()->name(); + AstArg* const resultValueArgp + = new AstArg{flp, resultName + VALUE_SUFFIX, resultValueRefp}; + AstArg* const resultXZArgp + = new AstArg{flp, std::move(resultName) + XZ_SUFFIX, resultXzRefp}; + newCallp->addArgsp(resultValueArgp); + newCallp->addArgsp(resultXZArgp); + } + AstStmtExpr* const newStmtExprp = new AstStmtExpr{flp, newCallp}; + addPrecalculation(newStmtExprp); + AstVarRef* const varRefValuep = new AstVarRef{flp, resultValuep, VAccess::READ}; + AstVarRef* const varRefXzp = new AstVarRef{flp, resultXzp, VAccess::READ}; + pushDeletep(varRefValuep); + pushDeletep(varRefXzp); + setExprValuep(funcRefp, varRefValuep); + setExprXZp(funcRefp, varRefXzp); + } + + void fourstateExpressionCondHandler(AstCond* const condp) { + FileLine* const flp = condp->fileline(); + AstVar* const resultValueTmpVarp = m_fourstateVisitor.createTmp(condp->thenp()); + AstVar* const resultXZTmpVarp = m_fourstateVisitor.createTmp(condp->thenp()); + AstIf* ifp = new AstIf{flp, isFourstate(condp->condp()) + ? getFourstateExpressionXZ(condp->condp()) + : condp->condp()->cloneTree(false)}; + // Those must be here so expr is always evaluated fully in the right place + AstIf* twoStateIfp = ifp; + if (isFourstate(condp->condp())) { + // Condition is X/Z + AstNodeExpr* conditionValuep = getFourstateExpressionValue(condp->condp()); + AstNodeExpr* const thenCopyp = condp->thenp()->cloneTree(false); + AstNodeExpr* const elseCopyp = condp->elsep()->cloneTree(false); + StatementPlaceHolder thenPlaceholder{m_fourstateVisitor, flp}; + ifp->addThensp(thenPlaceholder.stmtp()); + TmpVarsReleaser tmpVarsReleaser{m_fourstateVisitor}; + addPrecalculation( + new AstAssign{flp, new AstVarRef{flp, resultValueTmpVarp, VAccess::WRITE}, + getFourstateExpressionValue(thenCopyp, false)}); + addPrecalculation( + new AstAssign{flp, new AstVarRef{flp, resultXZTmpVarp, VAccess::WRITE}, + getFourstateExpressionXZ(thenCopyp, false)}); + AstIf* const thenifp = new AstIf{ + flp, new AstOr{ + flp, + new AstXor{flp, new AstVarRef{flp, resultValueTmpVarp, VAccess::READ}, + getFourstateExpressionValue(elseCopyp, false)}, + new AstXor{flp, new AstVarRef{flp, resultXZTmpVarp, VAccess::READ}, + getFourstateExpressionXZ(elseCopyp, false)}}}; + ifp->addThensp(thenifp); + thenifp->addThensp( + new AstAssign{flp, new AstVarRef{flp, resultValueTmpVarp, VAccess::WRITE}, + createZeroOrOnesp(thenCopyp, true)}); + thenifp->addThensp( + new AstAssign{flp, new AstVarRef{flp, resultXZTmpVarp, VAccess::WRITE}, + createZeroOrOnesp(thenCopyp, true)}); + thenCopyp->deleteTree(); + elseCopyp->deleteTree(); + twoStateIfp = new AstIf{flp, conditionValuep}; + ifp->addElsesp(twoStateIfp); + } + { + // Condition is 1/0 + { + // Condition is 1 + StatementPlaceHolder thenPlaceholder{m_fourstateVisitor, flp}; + twoStateIfp->addThensp(thenPlaceholder.stmtp()); + TmpVarsReleaser tmpVarsReleaser{m_fourstateVisitor}; + addPrecalculation( + new AstAssign{flp, new AstVarRef{flp, resultValueTmpVarp, VAccess::WRITE}, + getFourstateExpressionValue(condp->thenp(), false)}); + addPrecalculation( + new AstAssign{flp, new AstVarRef{flp, resultXZTmpVarp, VAccess::WRITE}, + getFourstateExpressionXZ(condp->thenp(), false)}); + } + { + // Condition is 0 + StatementPlaceHolder elsePlaceholder{m_fourstateVisitor, flp}; + twoStateIfp->addElsesp(elsePlaceholder.stmtp()); + TmpVarsReleaser tmpVarsReleaser{m_fourstateVisitor}; + addPrecalculation( + new AstAssign{flp, new AstVarRef{flp, resultValueTmpVarp, VAccess::WRITE}, + getFourstateExpressionValue(condp->elsep(), false)}); + addPrecalculation( + new AstAssign{flp, new AstVarRef{flp, resultXZTmpVarp, VAccess::WRITE}, + getFourstateExpressionXZ(condp->elsep(), false)}); + } + } + addPrecalculation(ifp); + AstVarRef* const resultValueTmpVarRefp + = new AstVarRef{flp, resultValueTmpVarp, VAccess::READ}; + AstVarRef* const resultXZTmpVarRefp + = new AstVarRef{flp, resultXZTmpVarp, VAccess::READ}; + pushDeletep(resultValueTmpVarRefp); + pushDeletep(resultXZTmpVarRefp); + setExprValuep(condp, resultValueTmpVarRefp); + setExprXZp(condp, resultXZTmpVarRefp); + } + + void fourstateExpressionLogAndHandler(AstLogAnd* const logAndp) { + FileLine* const flp = logAndp->fileline(); + AstVar* const resultValueTmpVarp = m_fourstateVisitor.createTmp(logAndp); + AstVar* const resultXZTmpVarp = m_fourstateVisitor.createTmp(logAndp); + addPrecalculation(new AstAssign{flp, + new AstVarRef{flp, resultXZTmpVarp, VAccess::WRITE}, + getFourstateExpressionXZ(logAndp->lhsp(), false)}); + addPrecalculation( + new AstAssign{flp, new AstVarRef{flp, resultValueTmpVarp, VAccess::WRITE}, + new AstOr{flp, new AstVarRef{flp, resultXZTmpVarp, VAccess::READ}, + getFourstateExpressionValue(logAndp->lhsp(), false)}}); + AstIf* const ifp + = new AstIf{flp, new AstVarRef{flp, resultValueTmpVarp, VAccess::READ}}; + addPrecalculation(ifp); + { + // Lhs is non zero + StatementPlaceHolder placeholderStmt{m_fourstateVisitor, flp}; + ifp->addThensp(placeholderStmt.stmtp()); + TmpVarsReleaser{m_fourstateVisitor}; + addPrecalculation(new AstAssign{ + flp, new AstVarRef{flp, resultValueTmpVarp, VAccess::WRITE}, + new AstOr{flp, getFourstateExpressionValue(logAndp->rhsp(), false), + getFourstateExpressionXZ(logAndp->rhsp())}}); + addPrecalculation(new AstAssign{ + flp, new AstVarRef{flp, resultXZTmpVarp, VAccess::WRITE}, + new AstLogAnd{flp, new AstVarRef{flp, resultValueTmpVarp, VAccess::READ}, + new AstOr{flp, + new AstVarRef{flp, resultXZTmpVarp, VAccess::READ}, + getFourstateExpressionXZ(logAndp->rhsp())}}}); + } + AstVarRef* const resultValueTmpVarRefp + = new AstVarRef{flp, resultValueTmpVarp, VAccess::READ}; + AstVarRef* const resultXZTmpVarRefp + = new AstVarRef{flp, resultXZTmpVarp, VAccess::READ}; + pushDeletep(resultValueTmpVarRefp); + pushDeletep(resultXZTmpVarRefp); + setExprValuep(logAndp, resultValueTmpVarRefp); + setExprXZp(logAndp, resultXZTmpVarRefp); + } + + void fourstateExpressionLogOrHandler(AstLogOr* const logOrp) { + FileLine* const flp = logOrp->fileline(); + AstVar* const resultValueTmpVarp = m_fourstateVisitor.createTmp(logOrp); + AstVar* const resultXZTmpVarp = m_fourstateVisitor.createTmp(logOrp); + addPrecalculation(new AstAssign{flp, + new AstVarRef{flp, resultXZTmpVarp, VAccess::WRITE}, + getFourstateExpressionXZ(logOrp->lhsp(), false)}); + addPrecalculation(new AstAssign{flp, + new AstVarRef{flp, resultValueTmpVarp, VAccess::WRITE}, + getFourstateExpressionValue(logOrp->lhsp(), false)}); + AstIf* const ifp = new AstIf{ + flp, + new AstOr{flp, + new AstNot{flp, new AstVarRef{flp, resultValueTmpVarp, VAccess::READ}}, + new AstVarRef{flp, resultXZTmpVarp, VAccess::READ}}}; + addPrecalculation(ifp); + { + // Lhs is non one + StatementPlaceHolder placeholderStmt{m_fourstateVisitor, flp}; + ifp->addThensp(placeholderStmt.stmtp()); + TmpVarsReleaser{m_fourstateVisitor}; + addPrecalculation(new AstAssign{ + flp, new AstVarRef{flp, resultValueTmpVarp, VAccess::WRITE}, + new AstOr{flp, getFourstateExpressionValue(logOrp->rhsp()), + new AstOr{flp, getFourstateExpressionXZ(logOrp->rhsp()), + new AstVarRef{flp, resultXZTmpVarp, VAccess::READ}}}}); + addPrecalculation(new AstAssign{ + flp, new AstVarRef{flp, resultXZTmpVarp, VAccess::WRITE}, + new AstLogAnd{ + flp, new AstVarRef{flp, resultValueTmpVarp, VAccess::READ}, + new AstOr{flp, + new AstNot{flp, getFourstateExpressionValue(logOrp->rhsp())}, + getFourstateExpressionXZ(logOrp->rhsp())}}}); + } + AstVarRef* const resultValueTmpVarRefp + = new AstVarRef{flp, resultValueTmpVarp, VAccess::READ}; + AstVarRef* const resultXZTmpVarRefp + = new AstVarRef{flp, resultXZTmpVarp, VAccess::READ}; + pushDeletep(resultValueTmpVarRefp); + pushDeletep(resultXZTmpVarRefp); + setExprValuep(logOrp, resultValueTmpVarRefp); + setExprXZp(logOrp, resultXZTmpVarRefp); + } + + AstNodeExpr* get(AstNodeExpr* const exprp, bool putIntoTmp = true) { + if (AstNodeExpr* result = getCache(exprp)) return result->cloneTree(false); + m_resultp = nullptr; + VL_RESTORER(m_noTmp); + VL_RESTORER(m_enforceTmp); + m_noTmp = false; + m_enforceTmp = false; + iterate(exprp); + UASSERT_OBJ(m_resultp, exprp, + "Result shall always be returned - even if it is just a place holder"); + UASSERT_OBJ(!(m_noTmp && m_enforceTmp), exprp, + "Expression may not enforce and omit tmp variable at the same time"); + if (m_enforceTmp || (putIntoTmp && !m_noTmp)) { + FileLine* const flp = exprp->fileline(); + AstVar* const varp = m_fourstateVisitor.createTmp(exprp); + AstVarRef* const varRefp = new AstVarRef{flp, varp, VAccess::WRITE}; + AstAssign* const assignp = new AstAssign{flp, varRefp, m_resultp}; + addPrecalculation(assignp); + m_resultp = new AstVarRef{flp, varp, VAccess::READ}; + setFourstate(m_resultp, false); + } + setCache(exprp, m_resultp); + return m_resultp; + } + + public: + explicit FourstateExpressionVisitor(FourstateVisitor& fourstateVisitor) + : m_fourstateVisitor{fourstateVisitor} {} + ~FourstateExpressionVisitor() override = default; + + virtual AstNodeExpr* getFourstateExpressionValue(AstNodeExpr* const exprp, + bool putIntoTmp = true) { + return m_fourstateVisitor.m_fourstateGeneratorValueVisitor.getFourstateExpressionValue( + exprp, putIntoTmp); + } + + virtual AstNodeExpr* getFourstateExpressionXZ(AstNodeExpr* const exprp, + const bool putIntoTmp = true) { + return m_fourstateVisitor.m_fourstateGeneratorXZVisitor.getFourstateExpressionXZ( + exprp, putIntoTmp); + } + }; + + // Visitor used to get an expression with a value of a value part of a four-state expression + // This can be thought as a function - but a Visitor was used to be able to use vtable, create + // some enclosing namespace and benefit from inheritance + class FourstateExpressionValueVisitor final : public FourstateExpressionVisitor { + + void visit(AstAnd* const andp) override { + // (a.value | a.xz) & (b.value | b.xz) + FileLine* const flp = andp->fileline(); + m_resultp = new AstAnd{flp, + new AstOr{flp, getFourstateExpressionValue(andp->lhsp()), + getFourstateExpressionXZ(andp->lhsp())}, + new AstOr{flp, getFourstateExpressionValue(andp->rhsp()), + getFourstateExpressionXZ(andp->rhsp())}}; + } + + void visit(AstOr* const orp) override { + // a.value | b.value | a.xz | b.xz + FileLine* const flp = orp->fileline(); + m_resultp = new AstOr{flp, + new AstOr{flp, getFourstateExpressionValue(orp->lhsp()), + getFourstateExpressionValue(orp->rhsp())}, + new AstOr{flp, getFourstateExpressionXZ(orp->lhsp()), + getFourstateExpressionXZ(orp->rhsp())}}; + } + + void visit(AstXor* const xorp) override { + // (a.value ^ b.value) | a.xz | b.xz + FileLine* const flp = xorp->fileline(); + m_resultp = new AstOr{flp, + new AstXor{flp, getFourstateExpressionValue(xorp->lhsp(), false), + getFourstateExpressionValue(xorp->rhsp(), false)}, + getFourstateExpressionXZ(xorp)}; + } + + void visit(AstNot* const notp) override { + // ~a.value | a.xz + FileLine* const flp = notp->fileline(); + m_resultp = new AstOr{flp, new AstNot{flp, getFourstateExpressionValue(notp->lhsp())}, + getFourstateExpressionXZ(notp->lhsp())}; + } + + template + void visitCompare(CompoarisonOp_T* const cmpp) { + // |(a.xz | b.xz) | (a.value op b.value) + FileLine* const flp = cmpp->fileline(); + m_resultp + = new AstOr{flp, getFourstateExpressionXZ(cmpp), + new CompoarisonOp_T{flp, getFourstateExpressionValue(cmpp->lhsp()), + getFourstateExpressionValue(cmpp->rhsp())}}; + } + + void visit(AstEq* const eqp) override { visitCompare(eqp); } + void visit(AstNeq* const neqp) override { visitCompare(neqp); } + void visit(AstGt* const gtp) override { visitCompare(gtp); } + void visit(AstGte* const gtep) override { visitCompare(gtep); } + void visit(AstLt* const ltp) override { visitCompare(ltp); } + void visit(AstLte* const ltep) override { visitCompare(ltep); } + + void visit(AstGtS* const gtp) override { visitCompare(gtp); } + void visit(AstGteS* const gtep) override { visitCompare(gtep); } + void visit(AstLtS* const ltp) override { visitCompare(ltp); } + void visit(AstLteS* const ltep) override { visitCompare(ltep); } + + void visit(AstEqWild* const eqWildp) override { + // ((a.value | b.xz) == (b.value | b.xz)) | |(a.xz & ~b.xz) + FileLine* const flp = eqWildp->fileline(); + m_resultp = new AstOr{ + flp, + new AstEq{flp, + new AstOr{flp, getFourstateExpressionValue(eqWildp->lhsp(), false), + getFourstateExpressionXZ(eqWildp->rhsp())}, + new AstOr{flp, getFourstateExpressionValue(eqWildp->rhsp(), false), + getFourstateExpressionXZ(eqWildp->rhsp())}}, + getFourstateExpressionXZ(eqWildp)}; + } + + void visit(AstNeqWild* const neqWildp) override { + // ((a.value | b.xz) != (b.value | b.xz)) | |(a.xz & ~b.xz) + FileLine* const flp = neqWildp->fileline(); + m_resultp = new AstOr{ + flp, + new AstNeq{flp, + new AstOr{flp, getFourstateExpressionValue(neqWildp->lhsp(), false), + getFourstateExpressionXZ(neqWildp->rhsp())}, + new AstOr{flp, getFourstateExpressionValue(neqWildp->rhsp(), false), + getFourstateExpressionXZ(neqWildp->rhsp())}}, + getFourstateExpressionXZ(neqWildp)}; + } + + void visit(AstShiftL* const shiftlp) override { + // |b.xz ? '1 : (a.value << b.value) + FileLine* const flp = shiftlp->fileline(); + m_resultp = new AstCond{ + flp, new AstRedOr{flp, getFourstateExpressionXZ(shiftlp->rhsp())}, + createZeroOrOnesp(shiftlp->lhsp(), true), + new AstShiftL{ + flp, + getFourstateExpressionValue( + shiftlp->lhsp(), true /*must be in tmp so it always gets evaluated*/), + getFourstateExpressionValue(shiftlp->rhsp())}}; + } + + void visit(AstShiftR* const shiftrp) override { + // |b.xz ? '1 : (a.value >> b.value) + FileLine* const flp = shiftrp->fileline(); + m_resultp = new AstCond{ + flp, new AstRedOr{flp, getFourstateExpressionXZ(shiftrp->rhsp())}, + createZeroOrOnesp(shiftrp->lhsp(), true), + new AstShiftR{ + flp, + getFourstateExpressionValue( + shiftrp->lhsp(), true /*must be in tmp so it always gets evaluated*/), + getFourstateExpressionValue(shiftrp->rhsp())}}; + } + + void visit(AstExtend* const extendp) override { + FileLine* const flp = extendp->fileline(); + m_resultp = new AstExtend{flp, getFourstateExpressionValue(extendp->lhsp(), false), + extendp->width()}; + } + + void visit(AstExtendS* const extendsp) override { + FileLine* const flp = extendsp->fileline(); + m_resultp = new AstExtendS{flp, getFourstateExpressionValue(extendsp->lhsp(), false), + extendsp->width()}; + } + + void visit(AstCReset* const cresetp) override { // LCOV_EXCL_LINE + cresetp->v3fatalSrc("This shall never be reached - CReset shall never be under " + "anything but AstNodeAssign"); + } + + void visit(AstConst* const constp) override { + noTmp(); + AstConst* const newp = constp->cloneTree(false); + newp->num().opBitsOneX(constp->num()); + newp->dtypeSetBitUnsized(newp->width(), newp->dtypep()->widthMin(), + newp->dtypep()->numeric()); + m_resultp = newp; + } + + void visit(AstNodeFTaskRef* const funcp) override { + fourstateExpressionFuncRefHandler(funcp); + noTmp(); + m_resultp = getExprValuep(funcp)->cloneTree(false); + } + + void visit(AstCond* const condp) override { + fourstateExpressionCondHandler(condp); + noTmp(); + m_resultp = getExprValuep(condp)->cloneTree(false); + } + + void visit(AstLogAnd* const logAndp) override { + fourstateExpressionLogAndHandler(logAndp); + noTmp(); + m_resultp = getExprValuep(logAndp)->cloneTree(false); + } + + void visit(AstLogOr* const logOrp) override { + fourstateExpressionLogOrHandler(logOrp); + noTmp(); + m_resultp = getExprValuep(logOrp)->cloneTree(false); + } + + void visit(AstSel* const selp) override { + m_resultp = m_fourstateVisitor.getFourstateExpressionSelHandler( + selp, getFourstateExpressionValue(selp->fromp(), false), false); + } + + void visit(AstRedAnd* const redAndp) override { + // &(a.value | a.xz) + enforceTmp(); + FileLine* const flp = redAndp->fileline(); + m_resultp = new AstRedAnd{ + flp, new AstOr{flp, getFourstateExpressionValue(redAndp->lhsp(), false), + getFourstateExpressionXZ(redAndp->lhsp())}}; + } + + void visit(AstRedOr* const redOrp) override { + // |(a.value | a.xz) + FileLine* const flp = redOrp->fileline(); + m_resultp + = new AstRedOr{flp, new AstOr{flp, getFourstateExpressionValue(redOrp->lhsp()), + getFourstateExpressionXZ(redOrp->lhsp())}}; + } + + void visit(AstRedXor* const redXorp) override { + // |a.xz | ^a.value + FileLine* const flp = redXorp->fileline(); + m_resultp = new AstOr{ + flp, new AstRedOr{flp, getFourstateExpressionXZ(redXorp->lhsp())}, + new AstRedXor{flp, getFourstateExpressionValue(redXorp->lhsp(), false)}}; + } + + template + void getFourstateExpressionArithmeticValue(ComparisonOp_T* const biop) { + // |(a.xz | b.xz) ? '1 : (a op b) + FileLine* const flp = biop->fileline(); + m_resultp = new AstCond{ + flp, + new AstRedOr{flp, new AstOr{flp, getFourstateExpressionXZ(biop->lhsp()), + getFourstateExpressionXZ(biop->rhsp())}}, + createZeroOrOnesp(biop, true), + new ComparisonOp_T{ + flp, + getFourstateExpressionValue( + biop->lhsp(), true /*must be in tmp so it always gets evaluated*/), + getFourstateExpressionValue( + biop->rhsp(), true /*must be in tmp so it always gets evaluated*/)}}; + } + + void visit(AstAdd* const addp) override { getFourstateExpressionArithmeticValue(addp); } + void visit(AstSub* const subp) override { getFourstateExpressionArithmeticValue(subp); } + void visit(AstMul* const mulp) override { getFourstateExpressionArithmeticValue(mulp); } + void visit(AstMulS* const mulsp) override { getFourstateExpressionArithmeticValue(mulsp); } + + template + void getFourstateExpressionDivValue(ModDivOp_T* const biop) { + // |(a.xz | b.xz) | ~|b.value ? '1 : (a op b) + FileLine* const flp = biop->fileline(); + ModDivOp_T* const resultp = new ModDivOp_T{ + flp, + getFourstateExpressionValue(biop->lhsp(), + true /*must be in tmp so it always gets evaluated*/), + getFourstateExpressionValue(biop->rhsp(), + true /*must be in tmp so it always gets evaluated*/)}; + setTwostate(resultp); + m_resultp = new AstCond{ + flp, + new AstOr{ + flp, + new AstRedOr{flp, new AstOr{flp, getFourstateExpressionXZ(biop->lhsp()), + getFourstateExpressionXZ(biop->rhsp())}}, + new AstNot{flp, new AstRedOr{flp, getFourstateExpressionValue(biop->rhsp())}}}, + createZeroOrOnesp(biop, true), resultp}; + } + + void visit(AstDiv* const divp) override { getFourstateExpressionDivValue(divp); } + void visit(AstDivS* const divsp) override { getFourstateExpressionDivValue(divsp); } + void visit(AstModDiv* const moddivp) override { getFourstateExpressionDivValue(moddivp); } + void visit(AstModDivS* const moddivsp) override { + getFourstateExpressionDivValue(moddivsp); + } + + void visit(AstConcat* const concatp) override { + // {a.value, b.value} + m_resultp = new AstConcat{concatp->fileline(), + getFourstateExpressionValue(concatp->lhsp(), false), + getFourstateExpressionValue(concatp->rhsp(), false)}; + } + + void visit(AstReplicate* const replicatep) override { + // {count{src.value}} + // IEEE 1800-2023 11.4.12.1 Replication operator: + // 'A replication operator (also called a multiple concatenation) is expressed by a + // concatenation preceded by a non-negative, non-x, and non-z constant expression, + // called a multiplier'... + // Because of that `replicatep->countp()` is just cloned + m_resultp = new AstReplicate{replicatep->fileline(), + getFourstateExpressionValue(replicatep->srcp(), false), + replicatep->countp()->cloneTree(false)}; + m_resultp->dtypeSetBitUnsized(replicatep->width(), replicatep->dtypep()->widthMin(), + replicatep->dtypep()->numeric()); + } + + void visit(AstCastWrap* const castWrapp) override { + // Cast to anything to fourstate + m_resultp = getFourstateExpressionValue(castWrapp->lhsp(), false); + } + + void visit(AstNodeVarRef* const varRefp) override { + noTmp(); + m_fourstateVisitor.splitVar(varRefp->varp()); + AstNodeVarRef* const newp = varRefp->cloneTree(false); + if (!newp->name().empty()) newp->name(newp->name() + VALUE_SUFFIX); + newp->varp(getSplittedValue(varRefp->varp())); + newp->dtypeSetBitSized(varRefp->varp()->width(), varRefp->varp()->dtypep()->numeric()); + m_resultp = newp; + } + + void visit(AstNodeExpr* const nodep) override { + nodep->v3warn(E_UNSUPPORTED, "Unsupported: Operator " + << nodep->typeName() + << " not supported in the four-state mode"); + // Workaround to avoid Internal errors + m_resultp = new AstConst{nodep->fileline(), AstConst::BitFalse{}}; + } + + void visit(AstNode* const nodep) override { // LCOV_EXCL_LINE + nodep->v3fatalSrc("This node shall be unreachable in this visitor"); + } + + AstNodeExpr* getCache(const AstNodeExpr* const keyp) override { + return getExprValuep(keyp); + } + void setCache(AstNodeExpr* keyp, AstNodeExpr* const valuep) override { + setExprValuep(keyp, valuep); + } + + public: + using FourstateExpressionVisitor::FourstateExpressionVisitor; + ~FourstateExpressionValueVisitor() override = default; + + AstNodeExpr* getFourstateExpressionValue(AstNodeExpr* const exprp, + bool putIntoTmp = true) override { + if (!isFourstate(exprp)) { + AstStmtExpr* const holderp + = new AstStmtExpr{exprp->fileline(), exprp->cloneTree(false)}; + m_fourstateVisitor.iterateChildren(holderp); + AstNodeExpr* const resultp = holderp->exprp()->unlinkFrBack(); + holderp->deleteTree(); + return resultp; + } + return get(exprp, putIntoTmp); + } + }; + + // Visitor used to get an expression with a value of an xz part of a four-state expression + // This can be thought as a function - but a Visitor was used to be able to use vtable, create + // some enclosing namespace and benefit from inheritance + class FourstateExpressionXZVisitor final : public FourstateExpressionVisitor { + + void visit(AstAnd* const andp) override { + // (a.value & b.xz) | (b.value & a.xz) | (a.xz & b.xz) + FileLine* const flp = andp->fileline(); + m_resultp + = new AstOr{flp, + new AstOr{flp, + new AstAnd{flp, getFourstateExpressionValue(andp->lhsp()), + getFourstateExpressionXZ(andp->rhsp())}, + new AstAnd{flp, getFourstateExpressionValue(andp->rhsp()), + getFourstateExpressionXZ(andp->lhsp())}}, + new AstAnd{flp, getFourstateExpressionXZ(andp->lhsp()), + getFourstateExpressionXZ(andp->rhsp())}}; + } + + void visit(AstOr* const orp) override { + // (a.xz & b.xz) | (a.xz & ~b.value) | (b.xz & ~a.value) + FileLine* const flp = orp->fileline(); + m_resultp = new AstOr{ + flp, + new AstOr{flp, + new AstAnd{flp, getFourstateExpressionXZ(orp->lhsp()), + getFourstateExpressionXZ(orp->rhsp())}, + new AstAnd{flp, getFourstateExpressionXZ(orp->lhsp()), + new AstNot{flp, getFourstateExpressionValue(orp->rhsp())}}}, + new AstAnd{flp, getFourstateExpressionXZ(orp->rhsp()), + new AstNot{flp, getFourstateExpressionValue(orp->lhsp())}}}; + } + + void visit(AstXor* const xorp) override { + // a.xz | b.xz + FileLine* const flp = xorp->fileline(); + m_resultp = new AstOr{flp, getFourstateExpressionXZ(xorp->lhsp()), + getFourstateExpressionXZ(xorp->rhsp())}; + } + + void visit(AstNot* const notp) override { + // a.xz + m_resultp = getFourstateExpressionXZ(notp->lhsp()); + } + + void visitCompare(AstNodeBiop* const cmpp) { + // |(a.xz | b.xz) + enforceTmp(); + FileLine* const flp = cmpp->fileline(); + m_resultp = new AstRedOr{flp, new AstOr{flp, getFourstateExpressionXZ(cmpp->lhsp()), + getFourstateExpressionXZ(cmpp->rhsp())}}; + } + + void visit(AstEq* const eqp) override { visitCompare(eqp); } + void visit(AstNeq* const neqp) override { visitCompare(neqp); } + void visit(AstGt* const gtp) override { visitCompare(gtp); } + void visit(AstGte* const gtep) override { visitCompare(gtep); } + void visit(AstLt* const ltp) override { visitCompare(ltp); } + void visit(AstLte* const ltep) override { visitCompare(ltep); } + + void visit(AstGtS* const gtp) override { visitCompare(gtp); } + void visit(AstGteS* const gtep) override { visitCompare(gtep); } + void visit(AstLtS* const ltp) override { visitCompare(ltp); } + void visit(AstLteS* const ltep) override { visitCompare(ltep); } + + void visit(AstEqWild* const eqWildp) override { + // |(a.xz & ~b.xz) + enforceTmp(); + FileLine* const flp = eqWildp->fileline(); + m_resultp = new AstRedOr{ + flp, new AstAnd{flp, getFourstateExpressionXZ(eqWildp->lhsp(), false), + new AstNot{flp, getFourstateExpressionXZ(eqWildp->rhsp())}}}; + } + + void visit(AstNeqWild* const neqWildp) override { + // |(a.xz & ~b.xz) + enforceTmp(); + FileLine* const flp = neqWildp->fileline(); + m_resultp = new AstRedOr{ + flp, new AstAnd{flp, getFourstateExpressionXZ(neqWildp->lhsp(), false), + new AstNot{flp, getFourstateExpressionXZ(neqWildp->rhsp())}}}; + } + + void visit(AstShiftL* const shiftlp) override { + // |b.xz ? '1 : (a.xz << b.value) + FileLine* const flp = shiftlp->fileline(); + m_resultp + = new AstCond{flp, new AstRedOr{flp, getFourstateExpressionXZ(shiftlp->rhsp())}, + createZeroOrOnesp(shiftlp->lhsp(), true), + new AstShiftL{flp, getFourstateExpressionXZ(shiftlp->lhsp(), false), + getFourstateExpressionValue(shiftlp->rhsp())}}; + } + + void visit(AstShiftR* const shiftrp) override { + // |b.xz ? '1 : (a.xz >> b.value) + FileLine* const flp = shiftrp->fileline(); + m_resultp + = new AstCond{flp, new AstRedOr{flp, getFourstateExpressionXZ(shiftrp->rhsp())}, + createZeroOrOnesp(shiftrp->lhsp(), true), + new AstShiftR{flp, getFourstateExpressionXZ(shiftrp->lhsp(), false), + getFourstateExpressionValue(shiftrp->rhsp())}}; + } + + void visit(AstExtend* const extendp) override { + FileLine* const flp = extendp->fileline(); + m_resultp = new AstExtend{flp, getFourstateExpressionXZ(extendp->lhsp(), false), + extendp->width()}; + } + + void visit(AstExtendS* const extendsp) override { + FileLine* const flp = extendsp->fileline(); + m_resultp = new AstExtendS{flp, getFourstateExpressionXZ(extendsp->lhsp(), false), + extendsp->width()}; + } + + void visit(AstCReset* const cresetp) override { // LCOV_EXCL_LINE + cresetp->v3fatalSrc("This shall never be reached - CReset shall never be under " + "anything but AstNodeAssign"); + } + + void visit(AstConst* const constp) override { + noTmp(); + AstConst* const newp = constp->cloneTree(false); + newp->num().opBitsXZ(constp->num()); + newp->dtypeSetBitSized(newp->width(), newp->dtypep()->numeric()); + m_resultp = newp; + } + + void visit(AstRedAnd* const redAndp) override { + // &(a.value | a.xz) & |a.xz + FileLine* const flp = redAndp->fileline(); + m_resultp = new AstAnd{flp, getFourstateExpressionValue(redAndp), + new AstRedOr{flp, getFourstateExpressionXZ(redAndp->lhsp())}}; + } + + void visit(AstRedOr* const redOrp) override { + // |a.xz & ~|(a.value & ~a.xz) + FileLine* const flp = redOrp->fileline(); + m_resultp = new AstAnd{ + flp, new AstRedOr{flp, getFourstateExpressionXZ(redOrp->lhsp())}, + new AstNot{ + flp, + new AstRedOr{flp, new AstAnd{flp, getFourstateExpressionValue(redOrp->lhsp()), + new AstNot{flp, getFourstateExpressionXZ( + redOrp->lhsp())}}}}}; + } + + void visit(AstRedXor* const redXorp) override { + // |a.xz + m_resultp + = new AstRedOr{redXorp->fileline(), getFourstateExpressionXZ(redXorp->lhsp())}; + } + + void getFourstateExpressionArithmeticXZ(AstNodeBiop* const biop) { + // |(a.xz | b.xz) ? '1 : '0 + FileLine* const flp = biop->fileline(); + m_resultp = new AstCond{ + flp, + new AstRedOr{flp, new AstOr{flp, getFourstateExpressionXZ(biop->lhsp()), + getFourstateExpressionXZ(biop->rhsp())}}, + createZeroOrOnesp(biop, true), createZeroOrOnesp(biop)}; + } + + void visit(AstAdd* const addp) override { getFourstateExpressionArithmeticXZ(addp); } + void visit(AstSub* const subp) override { getFourstateExpressionArithmeticXZ(subp); } + void visit(AstMul* const mulp) override { getFourstateExpressionArithmeticXZ(mulp); } + void visit(AstMulS* const mulsp) override { getFourstateExpressionArithmeticXZ(mulsp); } + + void getFourstateExpressionDivValue(AstNodeBiop* const biop) { + // |(a.xz | b.xz) | ~|b.value ? '1 : '0 + FileLine* const flp = biop->fileline(); + m_resultp = new AstCond{ + flp, + new AstOr{ + flp, + new AstRedOr{flp, new AstOr{flp, getFourstateExpressionXZ(biop->lhsp()), + getFourstateExpressionXZ(biop->rhsp())}}, + new AstNot{flp, new AstRedOr{flp, getFourstateExpressionValue(biop->rhsp())}}}, + createZeroOrOnesp(biop, true), createZeroOrOnesp(biop, false)}; + } + + void visit(AstDiv* const divp) override { getFourstateExpressionDivValue(divp); } + void visit(AstDivS* const divsp) override { getFourstateExpressionDivValue(divsp); } + void visit(AstModDiv* const moddivp) override { getFourstateExpressionDivValue(moddivp); } + void visit(AstModDivS* const moddivsp) override { + getFourstateExpressionDivValue(moddivsp); + } + + void visit(AstConcat* const concatp) override { + // {a.xz, b.xz} + m_resultp = new AstConcat{concatp->fileline(), + getFourstateExpressionXZ(concatp->lhsp(), false), + getFourstateExpressionXZ(concatp->rhsp(), false)}; + } + + void visit(AstReplicate* const replicatep) override { + // {count{src.value}} + // IEEE 1800-2023 11.4.12.1 Replication operator: + // 'A replication operator (also called a multiple concatenation) is expressed by a + // concatenation preceded by a non-negative, non-x, and non-z constant expression, + // called a multiplier'... + // Because of that `replicatep->countp()` is just cloned + m_resultp = new AstReplicate{replicatep->fileline(), + getFourstateExpressionXZ(replicatep->srcp(), false), + replicatep->countp()->cloneTree(false)}; + m_resultp->dtypeSetBitUnsized(replicatep->width(), replicatep->dtypep()->widthMin(), + replicatep->dtypep()->numeric()); + } + + void visit(AstCastWrap* const castWrapp) override { + // Cast to anything to fourstate + m_resultp = getFourstateExpressionXZ(castWrapp->lhsp(), false); + } + + void visit(AstNodeFTaskRef* const funcp) override { + fourstateExpressionFuncRefHandler(funcp); + noTmp(); + m_resultp = getExprXZp(funcp)->cloneTree(false); + } + + void visit(AstCond* const condp) override { + fourstateExpressionCondHandler(condp); + noTmp(); + m_resultp = getExprXZp(condp)->cloneTree(false); + } + + void visit(AstLogAnd* const logAndp) override { + fourstateExpressionLogAndHandler(logAndp); + noTmp(); + m_resultp = getExprXZp(logAndp)->cloneTree(false); + } + + void visit(AstLogOr* const logOrp) override { + fourstateExpressionLogOrHandler(logOrp); + noTmp(); + m_resultp = getExprXZp(logOrp)->cloneTree(false); + } + + void visit(AstSel* const selp) override { + m_resultp = m_fourstateVisitor.getFourstateExpressionSelHandler( + selp, getFourstateExpressionXZ(selp->fromp(), false), false); + } + + void visit(AstNodeVarRef* const varRefp) override { + noTmp(); + m_fourstateVisitor.splitVar(varRefp->varp()); + AstNodeVarRef* const newp = varRefp->cloneTree(false); + if (!newp->name().empty()) newp->name(newp->name() + XZ_SUFFIX); + newp->varp(getSplittedXZ(varRefp->varp())); + newp->dtypeSetBitSized(varRefp->varp()->width(), varRefp->varp()->dtypep()->numeric()); + m_resultp = newp; + } + + void visit(AstNodeExpr* const nodep) override { + nodep->v3warn(E_UNSUPPORTED, "Unsupported: Operator " + << nodep->typeName() + << " not supported in the four-state mode"); + // Workaround to avoid Internal errors + m_resultp = new AstConst{nodep->fileline(), AstConst::BitFalse{}}; + } + + void visit(AstNode* const nodep) override { // LCOV_EXCL_LINE + nodep->v3fatalSrc("This node shall be unreachable in this visitor"); + } + + AstNodeExpr* getCache(const AstNodeExpr* const keyp) override { return getExprXZp(keyp); } + void setCache(AstNodeExpr* keyp, AstNodeExpr* const valuep) override { + setExprXZp(keyp, valuep); + } + + public: + using FourstateExpressionVisitor::FourstateExpressionVisitor; + ~FourstateExpressionXZVisitor() override = default; + + AstNodeExpr* getFourstateExpressionXZ(AstNodeExpr* const exprp, + bool putIntoTmp = true) override { + if (!isFourstate(exprp)) return createZeroOrOnesp(exprp); + return get(exprp, putIntoTmp); + } + }; + + FourstateExpressionValueVisitor + m_fourstateGeneratorValueVisitor; // Generator of four-state expressions (value part) + FourstateExpressionXZVisitor + m_fourstateGeneratorXZVisitor; // Generator of four-state expressions (xz part) + + AstNodeExpr* getFourstateExpressionValue(AstNodeExpr* const exprp, bool putIntoTmp = false) { + if (AstCReset* const cresetp = VN_CAST(exprp, CReset)) { + // This is here instead in the visitor because CReset shall never be nested into + // the expression and also it is a very special case + return cresetp->cloneTree(false); + } + AstNodeExpr* const result + = m_fourstateGeneratorValueVisitor.getFourstateExpressionValue(exprp, putIntoTmp); + FourstateLogicTypePropagator{result}; + return result; + } + + AstNodeExpr* getFourstateExpressionXZ(AstNodeExpr* const exprp, bool putIntoTmp = false) { + if (AstCReset* const cresetp = VN_CAST(exprp, CReset)) { + // This is here instead in the visitor because CReset shall never be nested into + // the expression and also it is a very special case + return cresetp->cloneTree(false); + } + AstNodeExpr* const result + = m_fourstateGeneratorXZVisitor.getFourstateExpressionXZ(exprp, putIntoTmp); + FourstateLogicTypePropagator{result}; + return result; + } + + AstNodeExpr* getTruthExpr(AstNodeExpr* const exprp) { + UASSERT_OBJ(isFourstate(exprp), exprp, + "This function is ment to be called on four-state expressions"); + // a.value && !a.xz + FileLine* const flp = exprp->fileline(); + AstLogAnd* const result + = new AstLogAnd{flp, getFourstateExpressionValue(exprp), + new AstLogNot{flp, getFourstateExpressionXZ(exprp)}}; + setFourstate(result, false); + setFourstate(result->rhsp(), false); + return result; + } + + AstNodeExpr* getTwoStateCast(AstNodeExpr* const exprp) { + UASSERT_OBJ(isFourstate(exprp), exprp, + "This function is ment to be called on four-state expressions"); + // (a.value & (~a.xz)) + FileLine* const flp = exprp->fileline(); + AstAnd* const result = new AstAnd{flp, getFourstateExpressionValue(exprp), + new AstNot{flp, getFourstateExpressionXZ(exprp)}}; + setFourstate(result, false); + setFourstate(result->rhsp(), false); + return result; + } + + void visit(AstNodeAssign* const nodep) override { + VL_RESTORER(m_currentStmtp); + m_currentStmtp = nodep; + TmpVarsReleaser tmpVarsReleaser{*this}; + if (isFourstate(nodep->lhsp())) { + AstNodeVarRef* const lhsVarRefp = VN_CAST(nodep->lhsp(), NodeVarRef); + if (VL_UNLIKELY(!lhsVarRefp)) { + nodep->v3warn( + E_UNSUPPORTED, + "Fourstate LHS other than a simple variable reference is not supported"); + return; + } + AstNodeAssign* const assignXZp = nodep->cloneTree(false); + { + assignXZp->lhsp()->unlinkFrBack()->deleteTree(); + assignXZp->rhsp()->unlinkFrBack()->deleteTree(); + AstNodeExpr* const newLhsp = getFourstateExpressionXZ(lhsVarRefp); + assignXZp->lhsp(newLhsp); + assignXZp->rhsp(getFourstateExpressionXZ(nodep->rhsp())); + assignXZp->dtypeFrom(newLhsp); + nodep->addNextHere(assignXZp); + } + { + AstNodeExpr* const newRhsp = getFourstateExpressionValue(nodep->rhsp()); + AstNodeExpr* const newLhsp = getFourstateExpressionValue(lhsVarRefp); + pushDeletep(nodep->lhsp()->unlinkFrBack()); + pushDeletep(nodep->rhsp()->unlinkFrBack()); + nodep->lhsp(newLhsp); + nodep->rhsp(newRhsp); + nodep->dtypeFrom(newLhsp); + } + if (AstAssignW* const assignWValuep = VN_CAST(nodep, AssignW)) { + assignWConflictResolution(lhsVarRefp->varp(), assignWValuep, + VN_AS(assignXZp, AssignW)); + if (const AstNode* const timingControlp = assignWValuep->timingControlp()) { + timingControlp->v3warn( + E_UNSUPPORTED, + "Continuous assignment delays are unsupported with --fourstate"); + } + } + } else if (isFourstate(nodep->rhsp())) { + AstNodeExpr* const newRhsp = getTwoStateCast(nodep->rhsp()); + pushDeletep(nodep->rhsp()->unlinkFrBack()); + nodep->rhsp(newRhsp); + } + iterateChildren(nodep); + } + + void visit(AstStmtExpr* const nodep) override { + VL_RESTORER(m_currentStmtp); + m_currentStmtp = nodep; + TmpVarsReleaser tmpVarsReleaser{*this}; + auto isFourState = [nodep]() -> bool { + if (AstNodeFTaskRef* const taskRefp = VN_CAST(nodep->exprp(), NodeFTaskRef)) { + return isFourstate(taskRefp) && !isFTaskRefHandled(taskRefp); + } + return isFourstate(nodep->exprp()); + }; + if (isFourState()) { + AstNodeExpr* const exprp = nodep->exprp()->unlinkFrBack(); + nodep->exprp(getFourstateExpressionValue(exprp)); + AstNodeExpr* const newXzp = getFourstateExpressionXZ(exprp); + iterateChildren(newXzp); + AstStmtExpr* const newStmtExprp = new AstStmtExpr{nodep->fileline(), newXzp}; + nodep->addNextHere(newStmtExprp); + exprp->deleteTree(); + } + iterateChildren(nodep); + } + + void visit(AstLoopTest* const nodep) override { + VL_RESTORER(m_currentStmtp); + m_currentStmtp = nodep; + TmpVarsReleaser tmpVarsReleaser{*this}; + if (isFourstate(nodep->condp())) { + AstNodeExpr* const condp = nodep->condp()->unlinkFrBack(); + nodep->condp(getTruthExpr(condp)); + condp->deleteTree(); + } + iterateChildren(nodep); + } + + void visit(AstNodeIf* const nodep) override { + VL_RESTORER(m_currentStmtp); + m_currentStmtp = nodep; + if (isFourstate(nodep->condp())) { + AstNodeExpr* const condp = nodep->condp()->unlinkFrBack(); + nodep->condp(getTruthExpr(condp)); + condp->deleteTree(); + } + { + TmpVarsReleaser tmpVarsReleaser{*this}; + iterateAndNextNull(nodep->condp()); + } + iterateAndNextNull(nodep->thensp()); + iterateAndNextNull(nodep->elsesp()); + } + + void visit(AstCase* const nodep) override { + VL_RESTORER(m_currentStmtp); + m_currentStmtp = nodep; + if (isFourstate(nodep->exprp())) { + nodep->v3warn(E_UNSUPPORTED, "All case statements with four-state value as an " + "expression are unsupported with --fourstate"); + } else { + iterate(nodep->exprp()); + } + iterateAndNextNull(nodep->itemsp()); + iterateAndNextNull(nodep->notParallelp()); + } + + void visit(AstCaseItem* const nodep) override { + for (AstNodeExpr* condp = nodep->condsp(); condp; + condp = VN_AS(condp->nextp(), NodeExpr)) { + if (isFourstate(condp)) { + nodep->v3warn(E_UNSUPPORTED, + "Four-state case items values are unsupported with --fourstate"); + } else { + iterate(condp); + } + } + iterateAndNextNull(nodep->stmtsp()); + } + + void visit(AstSenItem* const nodep) override { + if (!VN_IS(nodep->sensp(), FourstateExpr) && isFourstate(nodep->sensp())) { + AstNodeExpr* const sensp = nodep->sensp()->unlinkFrBack(); + nodep->sensp(new AstFourstateExpr{nodep->fileline(), + getFourstateExpressionValue(sensp), + getFourstateExpressionXZ(sensp)}); + sensp->deleteTree(); + } + iterateChildren(nodep); + } + + void visit(AstDisplay* const nodep) override { + VL_RESTORER(m_currentStmtp); + m_currentStmtp = nodep; + if (nodep->filep() && isFourstate(nodep->filep())) { + nodep->filep()->v3warn( + CASTFOURSTATE, + "Some features are not supported with four-state values - cast it to two-state " + "logic or suppress this warning and it will be done implicitly"); + AstNodeExpr* const newp = getTwoStateCast(nodep->filep()); + nodep->filep()->unlinkFrBack()->deleteTree(); + nodep->filep(newp); + } + iterateChildren(nodep); + } + + void visit(AstFClose* const nodep) override { + VL_RESTORER(m_currentStmtp); + m_currentStmtp = nodep; + if (isFourstate(nodep->filep())) { + nodep->filep()->v3warn( + CASTFOURSTATE, + "Some features are not supported with four-state values - cast it to two-state " + "logic or suppress this warning and it will be done implicitly"); + AstNodeExpr* const newp = getTwoStateCast(nodep->filep()); + nodep->filep()->unlinkFrBack()->deleteTree(); + nodep->filep(newp); + } + iterateChildren(nodep); + } + + void visit(AstFFlush* const nodep) override { + VL_RESTORER(m_currentStmtp); + m_currentStmtp = nodep; + if (nodep->filep() && isFourstate(nodep->filep())) { + nodep->filep()->v3warn( + CASTFOURSTATE, + "Some features are not supported with four-state values - cast it to two-state " + "logic or suppress this warning and it will be done implicitly"); + AstNodeExpr* const newp = getTwoStateCast(nodep->filep()); + nodep->filep()->unlinkFrBack()->deleteTree(); + nodep->filep(newp); + } + iterateChildren(nodep); + } + + void cArgsHandler(AstNode* nodep) { + for (; nodep; nodep = nodep->nextp()) { + if (AstNodeExpr* const exprp = VN_CAST(nodep, NodeExpr)) { + if (isFourstate(exprp)) { + exprp->v3warn( + CASTFOURSTATE, + "Some features are not supported with four-state values - cast it to " + "two-state " + "logic or suppress this warning and it will be done implicitly"); + AstNodeExpr* const newp = getTwoStateCast(exprp); + exprp->replaceWith(newp); + exprp->deleteTree(); + nodep = newp; + } + } + } + } + + void visit(AstCStmtUser* const nodep) override { + VL_RESTORER(m_currentStmtp); + m_currentStmtp = nodep; + cArgsHandler(nodep->nodesp()); + } + + void visit(AstCExprUser* const nodep) override { cArgsHandler(nodep->nodesp()); } + void visit(AstCExpr* const nodep) override { cArgsHandler(nodep->nodesp()); } + + void visit(AstSFormatF* const nodep) override { + for (AstNodeExpr* exprp = nodep->exprsp(); exprp; + exprp = VN_AS(exprp->nextp(), NodeExpr)) { + if (isFourstate(exprp)) { + exprp->v3warn( + CASTFOURSTATE, + "Some features are not supported with four-state values - cast it to " + "two-state logic or suppress this warning and it will be done implicitly"); + if (AstSFormatArg* const sformatArgp = VN_CAST(exprp, SFormatArg)) { + AstNodeExpr* const currentExprp = sformatArgp->exprp(); + currentExprp->replaceWith(getTwoStateCast(currentExprp)); + currentExprp->deleteTree(); + setFourstate(exprp, isFourstate(sformatArgp->exprp())); + } else { + AstNodeExpr* const newp = getTwoStateCast(exprp); + exprp->replaceWith(newp); + exprp->deleteTree(); + exprp = newp; + } + } + } + iterateChildren(nodep); + } + + void visit(AstPin* const nodep) override { + AstVar* const varp = nodep->modVarp(); + if (!varp->isFourstateConstruct()) { + if (AstNodeExpr* const exprp = VN_CAST(nodep->exprp(), NodeExpr)) { + if (VL_UNLIKELY(!(VN_IS(exprp, NodeVarRef) || VN_IS(exprp, Const)))) { + // The issue lays in need for precalculations, potential side effects and lack + // of arguments order evaluation guarantees. The idea to support it is to do + // something like: + // Pin(foo()) + // will turn into: + // wire tmp; + // always assign tmp = foo; // <-- AstNodeAssign visitor will handle this + // Pin(tmp, tmp__Vxz) + exprp->v3warn(E_UNSUPPORTED, + "Cells with pins that are not a variable reference or a " + "constant are not supported with --fourstate"); + return; + } + if (needsSplitting(varp->dtypep())) { + AstPin* const newp + = new AstPin{nodep->fileline(), nodep->pinNum(), + nodep->name().empty() ? "" : nodep->name() + XZ_SUFFIX, + getFourstateExpressionXZ(exprp)}; + nodep->addNextHere(newp); + AstNodeExpr* const oldp = exprp->unlinkFrBack(); + nodep->exprp(getFourstateExpressionValue(oldp)); + oldp->deleteTree(); + splitVar(varp); // Ensure that variable is splitted + nodep->modVarp(getSplittedValue(varp)); + newp->modVarp(getSplittedXZ(varp)); + } else if (isFourstate(exprp)) { + AstNodeExpr* const oldp = exprp->unlinkFrBack(); + nodep->exprp(getTwoStateCast(oldp)); + oldp->deleteTree(); + } + } else if (!nodep->exprp() && needsSplitting(varp->dtypep())) { + AstPin* const newp + = new AstPin{nodep->fileline(), nodep->pinNum(), + nodep->name().empty() ? "" : nodep->name() + XZ_SUFFIX, nullptr}; + nodep->addNextHere(newp); + splitVar(varp); // Ensure that variable is splitted + nodep->modVarp(getSplittedValue(varp)); + newp->modVarp(getSplittedXZ(varp)); + } + } + iterateChildren(nodep); + } + + void visit(AstNodeFTaskRef* const nodep) override { + if (!isFTaskRefHandled(nodep)) { + setFTaskRefHandled(nodep); + size_t currentArgIdx = 0; + const FTaskPortsHelper& fTaskPortsHelper = getFTaskPortHelper(nodep->taskp()); + for (AstArg* argp = nodep->argsp(); argp; argp = VN_AS(argp->nextp(), Arg)) { + AstVar* const varp = fTaskPortsHelper.getArgPortVar(argp->name(), currentArgIdx); + ++currentArgIdx; + if (needsSplitting(varp->dtypep())) { + AstArg* const newp = new AstArg{ + argp->fileline(), argp->name().empty() ? "" : (varp->name() + XZ_SUFFIX), + getFourstateExpressionXZ(argp->exprp())}; + argp->addNextHere(newp); + AstNodeExpr* const oldp = argp->exprp()->unlinkFrBack(); + argp->exprp(getFourstateExpressionValue(oldp)); + oldp->deleteTree(); + if (!argp->name().empty()) argp->name(argp->name() + VALUE_SUFFIX); + argp = VN_AS(argp->nextp(), Arg); + } else if (isFourstate(argp->exprp())) { + AstNodeExpr* const oldp = argp->exprp()->unlinkFrBack(); + argp->exprp(getTwoStateCast(oldp)); + oldp->deleteTree(); + } + } + } + iterateChildren(nodep); + } + + void visit(AstCastWrap* const nodep) override { + if (!isFourstate(nodep) && isFourstate(nodep->lhsp())) { + AstNodeExpr* const lhsp = nodep->lhsp()->unlinkFrBack(); + nodep->lhsp(getTwoStateCast(lhsp)); + lhsp->deleteTree(); + } + iterateChildren(nodep); + } + + void visit(AstEqCase* const nodep) override { + FileLine* const flp = nodep->fileline(); + AstNodeExpr* newp; + if (isFourstate(nodep->lhsp()) && isFourstate(nodep->rhsp())) { + newp = new AstAnd{flp, + new AstEq{flp, getFourstateExpressionXZ(nodep->lhsp()), + getFourstateExpressionXZ(nodep->rhsp())}, + new AstEq{flp, getFourstateExpressionValue(nodep->lhsp()), + getFourstateExpressionValue(nodep->rhsp())}}; + } else if (isFourstate(nodep->lhsp()) || isFourstate(nodep->rhsp())) { + AstNodeExpr* const fourstateHsp + = isFourstate(nodep->lhsp()) ? nodep->lhsp() : nodep->rhsp(); + AstNodeExpr* const twostateHsp = isFourstate(nodep->lhsp()) + ? nodep->rhsp()->unlinkFrBack() + : nodep->lhsp()->unlinkFrBack(); + newp = new AstAnd{ + flp, new AstNot{flp, getFourstateExpressionXZ(fourstateHsp)}, + new AstEq{flp, getFourstateExpressionValue(fourstateHsp), twostateHsp}}; + } else { + newp = new AstEq{flp, nodep->lhsp()->unlinkFrBack(), nodep->rhsp()->unlinkFrBack()}; + } + { FourstateLogicTypePropagator{newp}; } + VNRelinker relinker; + nodep->unlinkFrBack(&relinker); + relinker.relink(newp); + nodep->deleteTree(); + } + + void visit(AstNeqCase* const nodep) override { + FileLine* const flp = nodep->fileline(); + AstNodeExpr* newp; + if (isFourstate(nodep->lhsp()) && isFourstate(nodep->rhsp())) { + newp = new AstRedOr{ + flp, new AstOr{flp, + new AstXor{flp, getFourstateExpressionValue(nodep->lhsp()), + getFourstateExpressionValue(nodep->rhsp())}, + new AstXor{flp, getFourstateExpressionXZ(nodep->lhsp()), + getFourstateExpressionXZ(nodep->rhsp())}}}; + } else if (isFourstate(nodep->lhsp()) || isFourstate(nodep->rhsp())) { + AstNodeExpr* const fourstateHsp + = isFourstate(nodep->lhsp()) ? nodep->lhsp() : nodep->rhsp(); + AstNodeExpr* const twostateHsp = isFourstate(nodep->lhsp()) + ? nodep->rhsp()->unlinkFrBack() + : nodep->lhsp()->unlinkFrBack(); + newp = new AstRedOr{ + flp, new AstOr{ + flp, getFourstateExpressionXZ(fourstateHsp), + new AstXor{flp, getFourstateExpressionValue(fourstateHsp), twostateHsp}}}; + } else { + newp = new AstNeq{flp, nodep->lhsp()->unlinkFrBack(), nodep->rhsp()->unlinkFrBack()}; + } + { FourstateLogicTypePropagator{newp}; } + VNRelinker relinker; + nodep->unlinkFrBack(&relinker); + relinker.relink(newp); + nodep->deleteTree(); + } + + void visit(AstSel* const nodep) override { + UASSERT_OBJ(!isFourstate(nodep), nodep, + "This visitor shall never be reached for four-state AstSel"); + if (!isSelpHandled(nodep)) { + setSelpHandled(nodep); + AstNodeExpr* const newp + = getFourstateExpressionSelHandler(nodep, nodep->fromp()->cloneTree(false), true); + { FourstateLogicTypePropagator{newp}; } + VNRelinker relinker; + nodep->unlinkFrBack(&relinker); + relinker.relink(newp); + nodep->deleteTree(); + } else { + iterateChildren(nodep); + } + } + + void visit(AstLogOr* const nodep) override { + if (!hasFourstateInSubtree(nodep->rhsp())) { + iterateChildren(nodep); + return; + } + UASSERT_OBJ(!isFourstate(nodep), nodep, + "This shall be reached only by two-state expressions"); + FileLine* const flp = nodep->fileline(); + AstVar* resultVarp = createTmp(nodep); + addPrecalculation(new AstAssign{flp, new AstVarRef{flp, resultVarp, VAccess::WRITE}, + new AstRedOr{flp, nodep->lhsp()->unlinkFrBack()}}); + addPrecalculation( + new AstIf{flp, new AstNot{flp, new AstVarRef{flp, resultVarp, VAccess::READ}}, + new AstAssign{flp, new AstVarRef{flp, resultVarp, VAccess::WRITE}, + new AstRedOr{flp, nodep->rhsp()->unlinkFrBack()}}}); + AstVarRef* const newp = new AstVarRef{flp, resultVarp, VAccess::READ}; + setFourstate(newp, false); + VNRelinker relinker; + nodep->unlinkFrBack(&relinker); + relinker.relink(newp); + nodep->deleteTree(); + } + + void visit(AstLogAnd* const nodep) override { + if (!hasFourstateInSubtree(nodep->rhsp())) { + iterateChildren(nodep); + return; + } + UASSERT_OBJ(!isFourstate(nodep), nodep, + "This shall be reached only by two-state expressions"); + FileLine* const flp = nodep->fileline(); + AstVar* resultVarp = createTmp(nodep); + addPrecalculation(new AstAssign{flp, new AstVarRef{flp, resultVarp, VAccess::WRITE}, + new AstRedOr{flp, nodep->lhsp()->unlinkFrBack()}}); + addPrecalculation( + new AstIf{flp, new AstVarRef{flp, resultVarp, VAccess::READ}, + new AstAssign{flp, new AstVarRef{flp, resultVarp, VAccess::WRITE}, + new AstRedOr{flp, nodep->rhsp()->unlinkFrBack()}}}); + AstVarRef* const newp = new AstVarRef{flp, resultVarp, VAccess::READ}; + setFourstate(newp, false); + VNRelinker relinker; + nodep->unlinkFrBack(&relinker); + relinker.relink(newp); + nodep->deleteTree(); + } + + void visit(AstCond* const nodep) override { + UASSERT_OBJ(!isFourstate(nodep), nodep, + "This shall be reached only by two-state expressions"); + if (!hasFourstateInSubtree(nodep->thenp()) && !hasFourstateInSubtree(nodep->elsep())) { + iterateChildren(nodep); + return; + } + FileLine* const flp = nodep->fileline(); + AstVar* resultVarp = createTmp(nodep); + addPrecalculation( + new AstIf{flp, nodep->condp()->unlinkFrBack(), + new AstAssign{flp, new AstVarRef{flp, resultVarp, VAccess::WRITE}, + nodep->thenp()->unlinkFrBack()}, + new AstAssign{flp, new AstVarRef{flp, resultVarp, VAccess::WRITE}, + nodep->elsep()->unlinkFrBack()}}); + AstVarRef* const newp = new AstVarRef{flp, resultVarp, VAccess::READ}; + setFourstate(newp, false); + VNRelinker relinker; + nodep->unlinkFrBack(&relinker); + relinker.relink(newp); + nodep->deleteTree(); + } + + void visit(AstCvtPackedToArray* const) override { + // Skip this tree since this expr is not supported anyway + } + void visit(AstTestPlusArgs* const) override { + // Skip this tree since this expr is not supported anyway + } + void visit(AstValuePlusArgs* const) override { + // Skip this tree since this expr is not supported anyway + } + void visit(AstFOpenMcd* const) override { + // Skip this tree since this expr is not supported anyway + } + void visit(AstCMethodHard* const) override { + // Skip this tree since this expr is not supported anyway + } + void visit(AstConsPackUOrStruct* const) override { + // Skip this tree since this expr is not supported anyway + } + + void visit(AstNodeFTask* const nodep) override { + VL_RESTORER(m_currentTmpSpotp); + VL_RESTORER(m_tmpUnusedVarps); + VL_RESTORER(m_tmpFuncLocal); + m_tmpFuncLocal = true; + m_currentTmpSpotp = nodep->stmtsp(); + TmpVarsReleaser releaser{*this}; + // Make sure FTasks use only local variables - prevents using tmp + // which may be used by a caller + for (auto& it : m_tmpUnusedVarps) it.clear(); + iterateChildren(nodep); + } + + void visit(AstVar* const nodep) override { + if (VL_UNLIKELY(!isDTypepSupported(nodep->dtypep()->skipRefp()).first)) { + nodep->v3warn(E_UNSUPPORTED, + "Variables of type: " << nodep->dtypep()->prettyDTypeNameQ() + << " are unsupported with --fourstate"); + } else if (needsSplitting(nodep->dtypep())) { + splitVar(nodep); + } + iterateChildren(nodep); + } + + void visit(AstPull* const nodep) override { + nodep->v3warn(E_UNSUPPORTED, "Pullups and pulldowns are unsupported with --fourstate"); + } + + void visit(AstModportVarRef* const nodep) override { + if ((nodep->exprp() && isFourstate(nodep->exprp())) + || (nodep->varp() && needsSplitting(nodep->varp()->dtypep()))) { + nodep->v3warn(E_UNSUPPORTED, "modports are not supported with --fourstate"); + } else { + iterateChildren(nodep); + } + } + + void visit(AstNodeModule* const nodep) override { + VL_RESTORER(m_currentTmpSpotp); + VL_RESTORER(m_tmpUnusedVarps); + m_currentTmpSpotp = nodep->stmtsp(); + iterateChildren(nodep); + } + + void visit(AstNodeStmt* const nodep) override { + VL_RESTORER(m_currentStmtp); + TmpVarsReleaser tmpVarsReleaser{*this}; + m_currentStmtp = nodep; + iterateChildren(nodep); + } + + void visit(AstNode* const nodep) override { iterateChildren(nodep); } + +public: + explicit FourstateVisitor(AstNetlist* const netlistp) + : m_tmpNames{"__VfourstateTmp"} + , m_fourstateGeneratorValueVisitor{*this} + , m_fourstateGeneratorXZVisitor{*this} { + { FourstateLogicTypePropagator{netlistp}; } + iterate(netlistp); + triorTriandReduce(m_assignWToTriand, triandReducer); + triorTriandReduce(m_assignWToTrior, triorReducer); + triorTriandReduce(m_assignWToWire, triReducer); + V3Error::abortIfErrors(); + { FourstateLogicTypePropagator{netlistp}; } + netlistp->foreach([](AstNodeExpr* const nodep) { + if (VN_IS(nodep, NodeFTaskRef)) { + // Changing it in type propagador is unnecessary since those will be 100% handled + return; + } + if (isFourstate(nodep)) { + nodep->v3warn(E_UNSUPPORTED, "This four-state expression has not been handled"); + } + if (nodep->dtypep()->isFourstate()) { + // If it is not a fourstate expression according to the + // `FourstateLogicTypePropagator` lets set the bit + nodep->dtypeSetBitUnsized(nodep->width(), nodep->widthMin(), + nodep->dtypep()->numeric()); + } + }); + V3Error::abortIfErrors(); + for (AstVar* const varp : m_varpsToRemove) varp->unlinkFrBack()->deleteTree(); + } + ~FourstateVisitor() override = default; +}; + +// Creates one wide shuffled variable from two wide signals that together create a four-state +// From: +// VlWide<128> a_value; +// VlWide<128> a_xz; +// creates a: +// VlWide<256> a; // keeps [value1, xz1, value2, xz2,...] +class FourstateShuffleVisitor final : public VNVisitor { + const VNUser1InUse m_user1InUse; + + // Node status + // AstVar*::user1p -> AstVar*. Four-state wide complemetary (xz part) variable keeps here + // a pointer to a newly created wide four-state shuffled + // signal + + VDouble0 m_shuffledVars; + + static bool needsShuffle(const AstVar* const varp) { + return varp->isWide() && (varp->fourstateComplementp() || varp->isFourstateComplement()); + } + + AstVar* getCreateShuffledVariantp(AstVar* varp) { + UASSERT_OBJ( + varp->fourstateComplementp() || varp->isFourstateComplement(), varp, + "This function is ment to be called on variables which create a four-state value"); + UASSERT_OBJ(varp->isWide(), varp, + "This function is only ment to be called on wide wariables"); + if (AstVar* newp = varp->fourstateComplementp()) varp = newp; + const size_t pos = varp->name().rfind(XZ_SUFFIX); + UASSERT_OBJ(pos != std::string::npos, varp, + "Four-state complementary value (xz part) shall have '" + << XZ_SUFFIX << "', but it is named: " << varp->name()); + if (AstVar* resultp = VN_AS(varp->user1p(), Var)) return resultp; + UINFO(4, "SHUFFLED4STATE: " << varp); + ++m_shuffledVars; + AstVar* const resultp = varp->cloneTree(false); + resultp->unsetIsFourstateComplement(); + resultp->name(resultp->name().erase(pos, sizeof(XZ_SUFFIX))); + resultp->dtypep(resultp->findBitDType(resultp->width(), resultp->dtypep()->widthMin(), + varp->dtypep()->numeric(), true)); + varp->addNextHere(resultp); + varp->user1p(resultp); + return resultp; + } + + void visit(AstNodeCCall* const nodep) override { + iterateChildren(nodep); + if (nodep->funcp()->dpiImportPrototype()) return; + AstNodeExpr* exprp = nodep->argsp(); + for (AstVar* varp = nodep->funcp()->argsp(); varp; varp = VN_AS(varp->nextp(), Var)) { + UASSERT_OBJ(exprp, varp, "Too little arguments"); + if (needsShuffle(varp)) { + UASSERT_OBJ(!varp->isFourstateComplement(), varp, + "This loop shall never reach four-state complement"); + if (AstVar* const complement = varp->fourstateComplementp()) { + getCreateShuffledVariantp(complement); + UASSERT_OBJ( + VN_IS(exprp, NodeVarRef) && VN_IS(exprp->nextp(), NodeVarRef), exprp, + "Wide four-state signals shall be passed only as lvalue references"); + exprp->nextp()->unlinkFrBack()->deleteTree(); + varp = VN_AS(varp->nextp()->nextp(), Var); + } + } + exprp = VN_AS(exprp->nextp(), NodeExpr); + } + UASSERT_OBJ(!exprp, exprp, "Too many arguments"); + } + + void visit(AstVar* const nodep) override { + iterateChildren(nodep); + if (needsShuffle(nodep)) { + getCreateShuffledVariantp(nodep); + pushDeletep(nodep->unlinkFrBack()); + } + } + + void visit(AstNodeVarRef* const nodep) override { + iterateChildren(nodep); + if (!needsShuffle(nodep->varp())) return; + AstVar* const varp = getCreateShuffledVariantp(nodep->varp()); + FileLine* const flp = nodep->fileline(); + if (AstVarScope* const oldVscp = nodep->varScopep()) { + AstVarScope* const vscp = new AstVarScope{flp, oldVscp->scopep(), varp}; + vscp->trace(oldVscp->isTrace()); + vscp->optimizeLifePost(oldVscp->optimizeLifePost()); + nodep->varScopep(vscp); + } + nodep->fourstateXZPart(nodep->varp()->isFourstateComplement()); + nodep->varp(varp); + if (AstWordSel* const wselp = VN_CAST(nodep->firstAbovep(), WordSel)) { + AstNodeExpr* idxp + = new AstMul{flp, wselp->bitp()->unlinkFrBack(), new AstConst{flp, 2}}; + if (nodep->fourstateXZPart()) idxp = new AstAdd{flp, idxp, new AstConst{flp, 1}}; + idxp = V3Const::constifyEdit(idxp); + wselp->bitp(idxp); + } + } + + void visit(AstNode* const nodep) override { iterateChildren(nodep); } + +public: + explicit FourstateShuffleVisitor(AstNetlist* const netlistp) { iterate(netlistp); } + ~FourstateShuffleVisitor() override { + V3Stats::addStat("Shuffled fourstate variables", m_shuffledVars); + } +}; + +void V3Fourstate::fourstateAll(AstNetlist* const netlistp) { + UINFO(2, __FUNCTION__ << ":"); + { FourstateVisitor{netlistp}; } + v3Global.setFourstateHandled(); + V3Global::dumpCheckGlobalTree("fourstate", 0, dumpTreeEitherLevel() >= 6); +} + +void V3Fourstate::fourstateShuffleAll(AstNetlist* const netlistp) { + UINFO(2, __FUNCTION__ << ":"); + { FourstateShuffleVisitor{netlistp}; } + v3Global.setFourstateShuffled(); + V3Global::dumpCheckGlobalTree("fourstateShuffle", 0, dumpTreeEitherLevel() >= 6); +} diff --git a/src/V3Fourstate.h b/src/V3Fourstate.h new file mode 100644 index 000000000..26e679d7d --- /dev/null +++ b/src/V3Fourstate.h @@ -0,0 +1,36 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +//************************************************************************* +// DESCRIPTION: Verilator: Four-state logic handler +// +// Code available from: https://verilator.org +// +//************************************************************************* +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +//************************************************************************* + +#ifndef VERILATOR_V3FOURSTATE_METHOD_H_ +#define VERILATOR_V3FOURSTATE_METHOD_H_ + +#include "config_build.h" +#include "verilatedos.h" + +class AstNetlist; + +//============================================================================ + +#define VALUE_SUFFIX "" // Needs to be empty so C++ api won't change +#define XZ_SUFFIX "__Vxz" + +class V3Fourstate final { +public: + static void fourstateAll(AstNetlist* nodep) VL_MT_DISABLED; + static void fourstateShuffleAll(AstNetlist* nodep) VL_MT_DISABLED; +}; + +#endif // Guard diff --git a/src/V3Global.h b/src/V3Global.h index 4825a540a..5668ebc95 100644 --- a/src/V3Global.h +++ b/src/V3Global.h @@ -135,6 +135,8 @@ class V3Global final { bool m_useCovergroup = false; // Has covergroup declarations bool m_useRandomizeMethods = false; // Need to define randomize() class methods bool m_hasPrintedObjects = false; // Design has format args printed with to_string() + bool m_fourstateHandled = false; // There should be no more fourstate values + bool m_fourstateShuffled = false; // There should be no more fourstate values uint64_t m_currentHierBlockCost = 0; // Total cost of this hier block, used for scheduling // Memory address to short string mapping (for debug) @@ -224,6 +226,10 @@ public: bool useCovergroup() const { return m_useCovergroup; } void useCovergroup(bool flag) { m_useCovergroup = flag; } bool useRandomizeMethods() const { return m_useRandomizeMethods; } + void setFourstateHandled() { m_fourstateHandled = true; } + bool fourstateHandled() const { return m_fourstateHandled; } + void setFourstateShuffled() { m_fourstateShuffled = true; } + bool fourstateShuffled() const { return m_fourstateShuffled; } void useRandomizeMethods(bool flag) { m_useRandomizeMethods = flag; } bool hasPrintedObjects() const { return m_hasPrintedObjects; } void hasPrintedObjects(bool flag) { m_hasPrintedObjects = flag; } diff --git a/src/V3InlineCFuncs.cpp b/src/V3InlineCFuncs.cpp index cdfc24062..953417d98 100644 --- a/src/V3InlineCFuncs.cpp +++ b/src/V3InlineCFuncs.cpp @@ -222,10 +222,19 @@ class InlineCFuncsVisitor final : public VNVisitor { // Clone local variables, add them to the local scope for (AstVar* varp = calleep->varsp(); varp; varp = VN_AS(varp->nextp(), Var)) { - AstVar* const newVarp = varp->cloneTree(false); + if (varp->isFourstateComplement()) continue; + AstVar* const complementp = varp->fourstateComplementp(); + AstVar* const newVarp + = complementp ? varp->cloneWithFourstateComplementp() : varp->cloneTree(false); newVarp->name(varPrefix + varp->name()); lscopep->addStmtsp(newVarp); varp->user2p(newVarp); + if (complementp) { + AstVar* const newComplementp = newVarp->fourstateComplementp(); + newComplementp->name(varPrefix + complementp->name()); + lscopep->addStmtsp(newComplementp); + complementp->user2p(newComplementp); + } } // Clone the function body diff --git a/src/V3Localize.cpp b/src/V3Localize.cpp index 17e069708..2e90e12e3 100644 --- a/src/V3Localize.cpp +++ b/src/V3Localize.cpp @@ -111,16 +111,30 @@ class LocalizeVisitor final : public VNVisitor { AstVar* const oldVarp = nodep->varp(); for (AstCFunc* const funcp : funcps) { // Create the new local variable. - const string newName + string newName = nodep->scopep() == funcp->scopep() ? oldVarp->name() : nodep->scopep()->nameDotless() + "__DOT__" + oldVarp->name(); - AstVar* const newVarp - = new AstVar{oldVarp->fileline(), oldVarp->varType(), newName, oldVarp}; + AstVar* const newVarp = new AstVar{oldVarp->fileline(), oldVarp->varType(), + std::move(newName), oldVarp}; newVarp->funcLocal(true); newVarp->noReset(oldVarp->noReset()); newVarp->noSubst(oldVarp->noSubst()); funcp->addVarsp(newVarp); + if (AstVar* complementp = oldVarp->fourstateComplementp()) { + string newName + = nodep->scopep() == funcp->scopep() + ? complementp->name() + : nodep->scopep()->nameDotless() + "__DOT__" + complementp->name(); + AstVar* const newVarXZp + = new AstVar{complementp->fileline(), complementp->varType(), + std::move(newName), complementp}; + newVarXZp->funcLocal(true); + newVarXZp->noReset(complementp->noReset()); + newVarXZp->noSubst(complementp->noSubst()); + funcp->addVarsp(newVarXZp); + newVarp->fourstateComplementp(newVarXZp); + } // Fix up all the references within this function const auto er = m_references(funcp).equal_range(nodep); @@ -192,6 +206,8 @@ class LocalizeVisitor final : public VNVisitor { && !nodep->varp()->sensIfacep() // Not sensitive to an interface && !nodep->varp()->isVirtIface() // Not interface pointer && !nodep->varp()->valuep() // Does not have an initializer + && !nodep->varp()->isFourstateComplement() // Don't optimize complements just optimize + // a value part ) { UINFO(4, "Consider for localization: " << nodep); m_varScopeps.push_back(nodep); diff --git a/src/V3Number.cpp b/src/V3Number.cpp index d97e4ed50..e46ee9948 100644 --- a/src/V3Number.cpp +++ b/src/V3Number.cpp @@ -522,6 +522,13 @@ V3Number& V3Number::setValue1() { return *this; } +V3Number& V3Number::setXZFromXZComplement(const V3Number& other) { + UASSERT(words() == other.words(), "Width mismatch"); + UASSERT(!other.isAnyXZ(), "XZ in xz part"); + for (int i = 1; i < words(); ++i) m_data.num()[i].m_valueX = other.m_data.num()[i].m_value; + return *this; +} + void V3Number::setBitX0(int bit) { // Selection beyond bounds after V3Premit needs to have 0s // in upper bits. Contrast to setAllBitsXRemoved which honors xAssign @@ -1167,6 +1174,20 @@ bool V3Number::isAllX() const VL_MT_SAFE { } return true; } +bool V3Number::isAll0() const VL_MT_SAFE { + if (isDouble() || isString()) return false; + for (int i = 0; i < width(); ++i) { + if (!bitIs0(i)) return false; + } + return true; +} +bool V3Number::isAll1() const VL_MT_SAFE { + if (isDouble() || isString()) return false; + for (int i = 0; i < width(); ++i) { + if (!bitIs1(i)) return false; + } + return true; +} bool V3Number::isEqZero() const VL_MT_SAFE { if (isString()) return m_data.str().empty(); for (int i = 0; i < words(); ++i) { @@ -1339,6 +1360,16 @@ V3Number& V3Number::opBitsOne(const V3Number& lhs) { // 1->1, 0/X/Z->0 } return *this; } +V3Number& V3Number::opBitsOneX(const V3Number& lhs) { + // op i, L(lhs) bit return + NUM_ASSERT_OP_ARGS1(lhs); + NUM_ASSERT_LOGIC_ARGS1(lhs); + setZero(); + for (int bit = 0; bit < width(); ++bit) { + if (lhs.bitIs1(bit) || lhs.bitIsX(bit)) setBit(bit, 1); + } + return *this; +} V3Number& V3Number::opBitsXZ(const V3Number& lhs) { // 0/1->1, X/Z->0 // op i, L(lhs) bit return NUM_ASSERT_OP_ARGS1(lhs); diff --git a/src/V3Number.h b/src/V3Number.h index d81e32d72..3969264eb 100644 --- a/src/V3Number.h +++ b/src/V3Number.h @@ -640,6 +640,7 @@ public: V3Number& setAllBits0(); V3Number& setAllBits1(); V3Number& setValue1(); + V3Number& setXZFromXZComplement(const V3Number&); // IE if nbits=1, then 0b1, if 2->0b11, if 3->0b111 etc V3Number& setMask(int nbits, int lsb = 0); @@ -697,6 +698,8 @@ public: } bool isAllZ() const VL_MT_SAFE; bool isAllX() const VL_MT_SAFE; + bool isAll0() const VL_MT_SAFE; + bool isAll1() const VL_MT_SAFE; bool isEqZero() const VL_MT_SAFE; bool isNeqZero() const; bool isBitsZero(int msb, int lsb) const; @@ -744,6 +747,7 @@ public: // "this" is the output, as we need the output width before some computations V3Number& opBitsNonXZ(const V3Number& lhs); // 0/1->1, X/Z->0 V3Number& opBitsOne(const V3Number& lhs); // 1->1, 0/X/Z->0 + V3Number& opBitsOneX(const V3Number& lhs); // 1/X->1, 0/Z->0 V3Number& opBitsXZ(const V3Number& lhs); // 0/1->0, X/Z->1 V3Number& opBitsZ(const V3Number& lhs); // Z->1, 0/1/X->0 // diff --git a/src/V3Options.cpp b/src/V3Options.cpp index 7a85c848d..d1a76d94f 100644 --- a/src/V3Options.cpp +++ b/src/V3Options.cpp @@ -1054,6 +1054,15 @@ void V3Options::notify() VL_MT_DISABLED { cmdfl->v3warn(E_UNSUPPORTED, "--fourstate is not supported with hierarchical Verilation"); } + if (traceEnabledFst()) { + cmdfl->v3warn(E_UNSUPPORTED, "--fourstate is not supported with fst trace"); + } + if (systemC()) cmdfl->v3warn(E_UNSUPPORTED, "--fourstate is not supported with --sc"); + if (!m_xInitialDefault) cmdfl->v3error("--x-initial has no sense with --fourstate"); + if (!m_xAssignDefault) cmdfl->v3error("--x-assign has no sense with --fourstate"); + } else if (!m_zero_top_ports.isDefault()) { + cmdfl->v3error( + "--zero-top-ports and --no-zero-top-ports shall be used only with --fourstate"); } if (coverage() && savable()) { @@ -1942,6 +1951,7 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, DECL_OPTION("-waiver-output", Set, &m_waiverOutput); DECL_OPTION("-x-assign", CbVal, [this, fl](const char* valp) { + m_xAssignDefault = false; if (!std::strcmp(valp, "0")) { m_xAssign = "0"; } else if (!std::strcmp(valp, "1")) { @@ -1957,6 +1967,7 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, } }); DECL_OPTION("-x-initial", CbVal, [this, fl](const char* valp) { + m_xInitialDefault = false; if (!std::strcmp(valp, "0")) { m_xInitial = "0"; } else if (!std::strcmp(valp, "fast")) { @@ -1975,6 +1986,8 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, addIncDirUser(parseFileArg(optdir, string{valp})); }).notForRerun(); + DECL_OPTION("-zero-top-ports", OnOff, &m_zero_top_ports).undocumented(); + parser.finalize(); for (int i = 0; i < argc;) { diff --git a/src/V3Options.h b/src/V3Options.h index 182379fe9..f82267f3c 100644 --- a/src/V3Options.h +++ b/src/V3Options.h @@ -311,6 +311,7 @@ private: bool m_vpi = false; // main switch: --vpi bool m_waiverMultiline = false; // main switch: --waiver-multiline bool m_xInitialEdge = false; // main switch: --x-initial-edge + VOptionBool m_zero_top_ports{VOptionBool::OPT_DEFAULT_TRUE}; // main switch --zero-top-ports int m_assertUnrollLimit = 1024; // main switch: --assert-unroll-limit int m_buildJobs = -1; // main switch: --build-jobs, -j @@ -384,6 +385,8 @@ private: string m_work = "work"; // main switch: --work {libname} string m_xAssign; // main switch: --x-assign string m_xInitial; // main switch: --x-initial + bool m_xAssignDefault = true; // whether the value is default of explicitly provided by user + bool m_xInitialDefault = true; // whether the value is default of explicitly provided by user // Language is now held in FileLine, on a per-node basis. However we still // have a concept of the default language at a global level. @@ -708,6 +711,7 @@ public: bool isWaiverOutput() const { return !m_waiverOutput.empty(); } string xAssign() const { return m_xAssign; } string xInitial() const { return m_xInitial; } + VOptionBool zeroTopPorts() const { return m_zero_top_ports; } const VStringSet& cppFiles() const { return m_cppFiles; } const VStringList& cFlags() const { return m_cFlags; } diff --git a/src/V3Premit.cpp b/src/V3Premit.cpp index c5a9fa9d1..077ffb448 100644 --- a/src/V3Premit.cpp +++ b/src/V3Premit.cpp @@ -28,6 +28,7 @@ #include "V3Premit.h" +#include "V3Fourstate.h" #include "V3Stats.h" #include "V3UniqueNames.h" @@ -308,6 +309,42 @@ class PremitVisitor final : public VNVisitor { iterateChildren(nodep); checkNode(nodep); } + void visit(AstFourstateExpr* nodep) override { + iterateChildren(nodep); + // Consider adding a temp for this expression. + if (!m_stmtp) return; // Not under a statement + if (nodep->user1SetOnce()) return; // Already processed + if (!nodep->valuep()->isWide()) return; // Not wide + if (m_assignLhs) return; // This is an lvalue! + UASSERT_OBJ(!VN_IS(nodep->firstAbovep(), ArraySel), nodep, "Should have been ignored"); + // Keep as local temporary. + std::string name = "__Vtemp_" + std::to_string(m_tmpVarCnt); + std::string nameXz = "__Vtemp_" + std::to_string(++m_tmpVarCnt) + XZ_SUFFIX; + FileLine* const flp = nodep->fileline(); + AstVar* const valueVarp + = new AstVar{flp, VVarType::STMTTEMP, std::move(name), nodep->valuep()->dtypep()}; + AstVar* xzVarp + = new AstVar{flp, VVarType::STMTTEMP, std::move(nameXz), nodep->xzp()->dtypep()}; + valueVarp->fourstateComplementp(xzVarp); + valueVarp->funcLocal(true); + xzVarp->funcLocal(true); + valueVarp->noReset(true); + xzVarp->noReset(true); + m_cfuncp->addVarsp(valueVarp); + m_cfuncp->addVarsp(xzVarp); + ++m_temporaryVarsCreated; + + // Assignment to put before the referencing statement + AstAssign* const assignValuep = new AstAssign{ + flp, new AstVarRef{flp, valueVarp, VAccess::WRITE}, nodep->valuep()->unlinkFrBack()}; + AstAssign* const assignXZp = new AstAssign{flp, new AstVarRef{flp, xzVarp, VAccess::WRITE}, + nodep->xzp()->unlinkFrBack()}; + // Insert before the statement + m_stmtp->addHereThisAsNext(assignValuep); + m_stmtp->addHereThisAsNext(assignXZp); + nodep->valuep(new AstVarRef{flp, valueVarp, VAccess::READ}); + nodep->xzp(new AstVarRef{flp, xzVarp, VAccess::READ}); + } void visit(AstRand* nodep) override { iterateChildren(nodep); checkNode(nodep); diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp index 2786ea305..3c84c2998 100644 --- a/src/V3Randomize.cpp +++ b/src/V3Randomize.cpp @@ -1011,12 +1011,20 @@ class ConstraintExprVisitor final : public VNVisitor { if (targetWidth > exprWidth) { // Extend to match target width AstNodeExpr* const result = new AstExtend{fl, exprp, targetWidth}; - result->dtypeSetLogicSized(targetWidth, targetSigning); + if (exprp->dtypep()->isFourstate()) { + result->dtypeSetLogicSized(targetWidth, targetSigning); + } else { + result->dtypeSetBitSized(targetWidth, targetSigning); + } return result; } else if (targetWidth < exprWidth) { // Truncate to match target width AstNodeExpr* const result = new AstSel{fl, exprp, 0, targetWidth}; - result->dtypeSetLogicSized(targetWidth, targetSigning); + if (exprp->dtypep()->isFourstate()) { + result->dtypeSetLogicSized(targetWidth, targetSigning); + } else { + result->dtypeSetBitSized(targetWidth, targetSigning); + } return result; } else { // Width already matches @@ -1964,7 +1972,6 @@ class ConstraintExprVisitor final : public VNVisitor { AstNodeExpr* indexp = nodep->bitp()->unlinkFrBack(&handle); if (indexp->width() < 32) { AstExtend* const extendp = new AstExtend{fl, indexp, 32}; - extendp->dtypeSetLogicSized(32, VSigning::UNSIGNED); extendp->user1(true); indexp = extendp; } diff --git a/src/V3Reloop.cpp b/src/V3Reloop.cpp index 8870e2ab6..f939a360c 100644 --- a/src/V3Reloop.cpp +++ b/src/V3Reloop.cpp @@ -66,8 +66,7 @@ class ReloopVisitor final : public VNVisitor { static AstVar* createVarTemp(FileLine* fl, AstCFunc* cfuncp) { UASSERT_OBJ(cfuncp, fl, "Assignment not under a function"); const string newvarname{"__Vilp" + std::to_string(cfuncp->user1Inc() + 1)}; - AstVar* const varp - = new AstVar{fl, VVarType::STMTTEMP, newvarname, VFlagLogicPacked{}, 32}; + AstVar* const varp = new AstVar{fl, VVarType::STMTTEMP, newvarname, VFlagBitPacked{}, 32}; cfuncp->addVarsp(varp); return varp; } diff --git a/src/V3SenExprBuilder.h b/src/V3SenExprBuilder.h index ac9abf196..8d9dff56a 100644 --- a/src/V3SenExprBuilder.h +++ b/src/V3SenExprBuilder.h @@ -246,10 +246,40 @@ private: = [this, flp, senp]() { return new AstVarRef{flp, getPrev(senp), VAccess::READ}; }; const auto lsb = [=](AstNodeExpr* opp) { return new AstSel{flp, opp, 0, 1}; }; + // Four-state expression handlers + AstFourstateExpr* const fourstateExpr = VN_CAST(senp, FourstateExpr); + auto currValp = [this, fourstateExpr]() { return getCurr(fourstateExpr->valuep()); }; + auto currXZp = [this, fourstateExpr]() { return getCurr(fourstateExpr->xzp()); }; + auto prevValp = [this, fourstateExpr, flp]() { + return new AstVarRef{flp, getPrev(fourstateExpr->valuep()), VAccess::READ}; + }; + auto prevXZp = [this, fourstateExpr, flp]() { + return new AstVarRef{flp, getPrev(fourstateExpr->xzp()), VAccess::READ}; + }; + // All event signals should be 1-bit at this point switch (senItemp->edgeType()) { case VEdgeType::ET_CHANGED: case VEdgeType::ET_HYBRID: // + if (fourstateExpr) { + if (VN_IS(senp->dtypep()->skipRefp(), UnpackArrayDType)) { + AstCMethodHard* const resultValp + = new AstCMethodHard{flp, prevp(), VCMethod::UNPACKED_NEQ, currValp()}; + AstCMethodHard* const resultXZp + = new AstCMethodHard{flp, prevp(), VCMethod::UNPACKED_NEQ, currXZp()}; + resultValp->dtypeSetBit(); + resultXZp->dtypeSetBit(); + return {wrapExprWithNullCheck(flp, new AstOr{flp, resultValp, resultXZp}, + baseClassRefp), + true}; + } + return {wrapExprWithNullCheck( + flp, + lsb(new AstOr{flp, new AstXor{flp, prevValp(), currValp()}, + new AstXor{flp, prevXZp(), currXZp()}}), + baseClassRefp), + true}; + } if (VN_IS(senp->dtypep()->skipRefp(), UnpackArrayDType)) { // operand order reversed to avoid calling neq() method on non-VlUnpacked type, see // issue #5125 @@ -261,15 +291,46 @@ private: return {wrapExprWithNullCheck(flp, new AstNeq{flp, currp(), prevp()}, baseClassRefp), true}; case VEdgeType::ET_BOTHEDGE: // + if (fourstateExpr) { + return {wrapExprWithNullCheck( + flp, + lsb(new AstOr{flp, new AstXor{flp, currXZp(), prevXZp()}, + new AstAnd{flp, new AstNot{flp, prevXZp()}, + new AstXor{flp, currValp(), prevValp()}}}), + baseClassRefp), + false}; + } return { wrapExprWithNullCheck(flp, lsb(new AstXor{flp, currp(), prevp()}), baseClassRefp), false}; case VEdgeType::ET_POSEDGE: // + if (fourstateExpr) { + return {wrapExprWithNullCheck( + flp, + lsb(new AstAnd{ + flp, + new AstAnd{flp, new AstOr{flp, currValp(), currXZp()}, + new AstOr{flp, prevXZp(), new AstNot{flp, prevValp()}}}, + new AstNot{flp, new AstAnd{flp, prevXZp(), currXZp()}}}), + baseClassRefp), + false}; + } return {wrapExprWithNullCheck(flp, lsb(new AstAnd{flp, currp(), new AstNot{flp, prevp()}}), baseClassRefp), false}; case VEdgeType::ET_NEGEDGE: // + if (fourstateExpr) { + return {wrapExprWithNullCheck( + flp, + lsb(new AstAnd{ + flp, + new AstAnd{flp, new AstOr{flp, prevValp(), prevXZp()}, + new AstOr{flp, currXZp(), new AstNot{flp, currValp()}}}, + new AstNot{flp, new AstAnd{flp, prevXZp(), currXZp()}}}), + baseClassRefp), + false}; + } return {wrapExprWithNullCheck(flp, lsb(new AstAnd{flp, new AstNot{flp, currp()}, prevp()}), baseClassRefp), @@ -293,6 +354,9 @@ private: return {wrapExprWithNullCheck(flp, callp, baseClassRefp), false}; } case VEdgeType::ET_TRUE: // + if (fourstateExpr) { + return {lsb(new AstAnd{flp, currValp(), new AstNot{flp, currXZp()}}), false}; + } return {currp(), false}; case VEdgeType::ET_INITIAL_NBA: // return {new AstConst{flp, AstConst::BitFalse{}}, true}; diff --git a/src/V3Task.cpp b/src/V3Task.cpp index 0db8d04d3..423f50f7a 100644 --- a/src/V3Task.cpp +++ b/src/V3Task.cpp @@ -553,8 +553,9 @@ class TaskVisitor final : public VNVisitor { } } - void connectPort(AstVar* portp, AstArg* argp, const string& namePrefix, AstNode* beginp, - bool inlineTask) { + AstVarScope* connectPort(AstVar* portp, AstArg* argp, const string& namePrefix, + AstNode* beginp, bool inlineTask) { + AstVarScope* newvscp = nullptr; AstNodeExpr* pinp = argp->exprp(); if (inlineTask) { portp->unlinkFrBack(); @@ -575,7 +576,7 @@ class TaskVisitor final : public VNVisitor { + std::to_string(m_unconVarNum++), portp->dtypep()}; m_modp->addStmtsp(varp); - AstVarScope* const newvscp = new AstVarScope{pinp->fileline(), m_scopep, varp}; + newvscp = new AstVarScope{pinp->fileline(), m_scopep, varp}; m_scopep->addVarsp(newvscp); AstVarRef* const repp = new AstVarRef{pinp->fileline(), newvscp, VAccess::WRITE}; pinp->replaceWith(repp); @@ -620,8 +621,7 @@ class TaskVisitor final : public VNVisitor { } else if (portp->isInout()) { // UINFOTREE(9, pinp, "", "pinrsize-"); - AstVarScope* const newvscp - = createVarScope(portp, namePrefix + "__" + portp->shortName()); + newvscp = createVarScope(portp, namePrefix + "__" + portp->shortName()); portp->user2p(newvscp); if (!inlineTask) { pinp->replaceWith( @@ -642,8 +642,7 @@ class TaskVisitor final : public VNVisitor { } else if (portp->isWritable()) { // Even if it's referencing a varref, we still make a temporary // Else task(x,x,x) might produce incorrect results - AstVarScope* const newvscp - = createVarScope(portp, namePrefix + "__" + portp->shortName()); + newvscp = createVarScope(portp, namePrefix + "__" + portp->shortName()); portp->user2p(newvscp); if (!inlineTask) { pinp->replaceWith(new AstVarRef{newvscp->fileline(), newvscp, VAccess::WRITE}); @@ -654,8 +653,7 @@ class TaskVisitor final : public VNVisitor { beginp->addNext(postassp); } else if (inlineTask && portp->isNonOutput()) { // Make input variable - AstVarScope* const newvscp - = createVarScope(portp, namePrefix + "__" + portp->shortName()); + newvscp = createVarScope(portp, namePrefix + "__" + portp->shortName()); portp->user2p(newvscp); AstAssign* const preassp = connectPortMakeInAssign(pinp, newvscp, false); // Put assignment in FRONT of all other statements @@ -666,6 +664,7 @@ class TaskVisitor final : public VNVisitor { beginp->addNext(preassp); } } + return newvscp; } bool hasRefArgument(AstNodeFTask* nodep) { @@ -692,10 +691,25 @@ class TaskVisitor final : public VNVisitor { AstNode::user2ClearTree(); { const V3TaskConnects tconnects = V3Task::taskConnects(refp, beginp); + AstVar* prevFourstateVarp = nullptr; for (const auto& itr : tconnects) { AstVar* const portp = itr.first; AstArg* const argp = itr.second; - connectPort(portp, argp, namePrefix, beginp, true); + AstVar* varp = nullptr; + if (const AstVarScope* const vscp + = connectPort(portp, argp, namePrefix, beginp, true)) { + varp = vscp->varp(); + } + UASSERT_OBJ( + itr.first->isFourstateComplement() == (prevFourstateVarp != nullptr), varp, + "Fourstate complements shall be predecessed with fourstate value part"); + if (itr.first->fourstateComplementp()) { + UASSERT_OBJ(varp, itr.first, "Port not needed?"); + prevFourstateVarp = varp; + } else if (prevFourstateVarp) { + prevFourstateVarp->fourstateComplementp(varp); + prevFourstateVarp = nullptr; + } } } UASSERT_OBJ(!refp->argsp(), refp, "Arg wasn't removed by above loop"); diff --git a/src/V3TraceDecl.cpp b/src/V3TraceDecl.cpp index 1a1ad6b89..44bef9df4 100644 --- a/src/V3TraceDecl.cpp +++ b/src/V3TraceDecl.cpp @@ -230,8 +230,11 @@ class TraceDeclVisitor final : public VNVisitor { FileLine& fileline() const { return m_vscp ? *m_vscp->fileline() : *m_cellp->fileline(); } }; std::vector m_entries; // Trace entries under current scope + std::map + m_varxzToVscp; // Map from variable with xz part to its variable scope AstVarScope* m_traVscp = nullptr; // Current AstVarScope we are constructing AstTraceDecls for AstNodeExpr* m_traValuep = nullptr; // Value expression for current signal + AstNodeExpr* m_traValueXZp = nullptr; // ValueXZ expression for current signal string m_traName; // Name component for current signal VDouble0 m_statSigs; // Statistic tracking @@ -334,6 +337,10 @@ class TraceDeclVisitor final : public VNVisitor { } FileLine* const flp = m_traVscp->fileline(); AstNodeExpr* valuep = m_traValuep->cloneTree(false); + if (m_traValueXZp) { + valuep = new AstFourstateExpr{m_traVscp->fileline(), valuep, + m_traValueXZp->cloneTree(false)}; + } const bool validOffset = m_offset != std::numeric_limits::max(); AstTraceDecl* const newp = new AstTraceDecl{flp, m_traName, m_traVscp->varp(), valuep, @@ -685,6 +692,12 @@ class TraceDeclVisitor final : public VNVisitor { // traversal. m_traValuep = new AstVarRef{m_traVscp->fileline(), m_traVscp, VAccess::READ}; + if (AstVar* const complementp + = m_traVscp->varp()->fourstateComplementp()) { + m_traValueXZp + = new AstVarRef{m_traVscp->fileline(), + m_varxzToVscp.at(complementp), VAccess::READ}; + } // Recurse into data type of the signal. The visit methods will add // AstTraceDecls. iterate(m_traVscp->varp()->dtypep()->skipRefToEnump()); @@ -694,6 +707,10 @@ class TraceDeclVisitor final : public VNVisitor { // Note: Sometimes VL_DANGLING is a no-op, but we have assertions // on m_traValuep being nullptr, so make sure it is. m_traValuep = nullptr; + if (m_traValueXZp) { + VL_DO_DANGLING(m_traValueXZp->deleteTree(), m_traValueXZp); + m_traValueXZp = nullptr; + } } } } else { @@ -795,8 +812,12 @@ class TraceDeclVisitor final : public VNVisitor { if (nodep->varp()->isParam() && VN_IS(nodep->scopep()->modp(), Package)) return; } - // Add to traced signal list - m_entries.emplace_back(m_currScopep, nodep); + if (nodep->varp()->isFourstateComplement()) { + m_varxzToVscp.emplace(nodep->varp(), nodep); + } else { + // Add to traced signal list + m_entries.emplace_back(m_currScopep, nodep); + } } // VISITORS - Data types when tracing diff --git a/src/V3Unknown.cpp b/src/V3Unknown.cpp index 57e12e478..3ae20054f 100644 --- a/src/V3Unknown.cpp +++ b/src/V3Unknown.cpp @@ -207,7 +207,11 @@ class UnknownVisitor final : public VNVisitor { } void visit(AstVar* nodep) override { VL_RESTORER(m_allowXUnique); - if (nodep->isParam()) m_allowXUnique = false; + if (nodep->isParam()) { + m_allowXUnique = false; + } else if (m_modp && m_modp->isTop() && nodep->varType() == VVarType::PORT) { + nodep->setIsTopLevelPort(); + } iterateChildren(nodep); } void visitEqNeqCase(AstNodeBiop* nodep) { @@ -394,7 +398,7 @@ class UnknownVisitor final : public VNVisitor { void visit(AstSel* nodep) override { iterateChildren(nodep); - if (!nodep->user1SetOnce()) { + if (!v3Global.opt.fourstate() && !nodep->user1SetOnce()) { // Guard against reading/writing past end of bit vector array const AstNode* const basefromp = AstArraySel::baseFromp(nodep, true); bool lvalue = false; @@ -551,7 +555,8 @@ public: // CONSTRUCTORS explicit UnknownVisitor(AstNetlist* nodep) : m_lvboundNames{"__Vlvbound"} - , m_xrandNames{std::make_unique(s_xrandPrefix)} { + , m_xrandNames{std::make_unique(s_xrandPrefix)} + , m_allowXUnique{!v3Global.opt.fourstate()} { iterate(nodep); } ~UnknownVisitor() override { // diff --git a/src/V3Width.cpp b/src/V3Width.cpp index 86d688cc7..a49ff4593 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -1071,7 +1071,8 @@ class WidthVisitor final : public VNVisitor { const bool inParameterizedTemplate = m_modep && (m_modep->dead() || m_modep->parameterizedTemplate()); - if (VN_IS(nodep->lsbp(), Const) && nodep->msbConst() < nodep->lsbConst()) { + if (!v3Global.opt.fourstate() && VN_IS(nodep->lsbp(), Const) + && nodep->msbConst() < nodep->lsbConst()) { // Likely impossible given above width check nodep->v3warn(E_UNSUPPORTED, "Unsupported: left < right of bit extract: " // LCOV_EXCL_LINE @@ -1145,22 +1146,24 @@ class WidthVisitor final : public VNVisitor { UINFO(1, " Related node: " << nodep); } if (lrefp) UINFO(9, " Select extend lrefp " << lrefp); - if (lrefp && lrefp->access().isWriteOrRW()) { - // lvarref[X] = ..., the expression assigned is too wide - // WTF to do - // Don't change the width of this lhsp, instead propagate up - // to upper assign/expression the correct width - AstNodeDType* const subDTypep - = nodep->findLogicDType(width, width, nodep->fromp()->dtypep()->numeric()); - widthCheckSized(nodep, "errorless...", nodep->fromp(), subDTypep, EXTEND_EXP, - false /*noerror*/); - } else { - // Extend it - const int extendTo = nodep->msbConst() + 1; - AstNodeDType* const subDTypep = nodep->findLogicDType( - extendTo, extendTo, nodep->fromp()->dtypep()->numeric()); - widthCheckSized(nodep, "errorless...", nodep->fromp(), subDTypep, EXTEND_EXP, - false /*noerror*/); + if (!v3Global.opt.fourstate()) { + if (lrefp && lrefp->access().isWriteOrRW()) { + // lvarref[X] = ..., the expression assigned is too wide + // WTF to do + // Don't change the width of this lhsp, instead propagate up + // to upper assign/expression the correct width + AstNodeDType* const subDTypep = nodep->findLogicDType( + width, width, nodep->fromp()->dtypep()->numeric()); + widthCheckSized(nodep, "errorless...", nodep->fromp(), subDTypep, + EXTEND_EXP, false /*noerror*/); + } else { + // Extend it + const int extendTo = nodep->msbConst() + 1; + AstNodeDType* const subDTypep = nodep->findLogicDType( + extendTo, extendTo, nodep->fromp()->dtypep()->numeric()); + widthCheckSized(nodep, "errorless...", nodep->fromp(), subDTypep, + EXTEND_EXP, false /*noerror*/); + } } } // iterate FINAL is two blocks above @@ -1168,7 +1171,7 @@ class WidthVisitor final : public VNVisitor { // If we have a width problem with GENERATE etc, this will reduce // it down and mask it, so we have no chance of finding a real // error in the future. So don't do this for them. - if (!m_doGenerate) { + if (!v3Global.opt.fourstate() && !m_doGenerate) { // lsbp() must be self-determined, however for performance // we want the select to be truncated to fit within the // maximum select range, e.g. turn Xs outside of the select @@ -1908,13 +1911,15 @@ class WidthVisitor final : public VNVisitor { void visit(AstCExprUser* nodep) override { // Give it the size the user wants. if (m_vup && m_vup->prelim()) { - nodep->dtypeSetLogicUnsized(32, 1, VSigning::UNSIGNED); // We don't care + nodep->dtypeSetBitUnsized(32, 1, VSigning::UNSIGNED); // We don't care // All arguments seek their natural sizes userIterateChildren(nodep, WidthVP{SELF, BOTH}.p()); } if (m_vup->final()) { AstNodeDType* const expDTypep = m_vup->dtypeOverridep(nodep->dtypep()); - nodep->dtypep(expDTypep); // Assume user knows the rules; go with the flow + nodep->dtypeSetBitUnsized( + expDTypep->width(), expDTypep->widthMin(), + expDTypep->numeric()); // Assume user knows the rules; go with the flow if (nodep->width() > 64) { nodep->v3warn(E_UNSUPPORTED, "Unsupported: $c can't generate wider than 64 bits"); } @@ -2046,7 +2051,7 @@ class WidthVisitor final : public VNVisitor { iterateCheckSizedSelf(nodep, "FHS", nodep->fhsp(), SELF, BOTH); // For widthMin, if a 32 bit number, we need a 6 bit number as we need to return '32'. const int widthMin = V3Number::log2b(nodep->lhsp()->width()) + 1; - nodep->dtypeSetLogicUnsized(32, widthMin, VSigning::SIGNED); + nodep->dtypeSetBitUnsized(32, widthMin, VSigning::SIGNED); } } void visit(AstCountOnes* nodep) override { @@ -2054,7 +2059,7 @@ class WidthVisitor final : public VNVisitor { iterateCheckSizedSelf(nodep, "LHS", nodep->lhsp(), SELF, BOTH); // For widthMin, if a 32 bit number, we need a 6 bit number as we need to return '32'. const int widthMin = V3Number::log2b(nodep->lhsp()->width()) + 1; - nodep->dtypeSetLogicUnsized(32, widthMin, VSigning::SIGNED); + nodep->dtypeSetBitUnsized(32, widthMin, VSigning::SIGNED); } } void visit(AstCvtPackString* nodep) override { diff --git a/src/V3WidthCommit.cpp b/src/V3WidthCommit.cpp index 651bff963..acfbc60fa 100644 --- a/src/V3WidthCommit.cpp +++ b/src/V3WidthCommit.cpp @@ -278,9 +278,6 @@ private: void visit(AstCastWrap* nodep) override { iterateChildren(nodep); editDType(nodep); - UINFO(6, " Replace " << nodep << " w/ " << nodep->lhsp()); - nodep->replaceWith(nodep->lhsp()->unlinkFrBack()); - VL_DO_DANGLING(pushDeletep(nodep), nodep); } void visit(AstConstraint* nodep) override { iterateChildren(nodep); @@ -557,3 +554,19 @@ void V3WidthCommit::widthCommit(AstNetlist* nodep) { { WidthCommitVisitor{nodep}; } // Destruct before checking V3Global::dumpCheckGlobalTree("widthcommit", 0, dumpTreeEitherLevel() >= 6); } + +void V3WidthCommit::widthCommitClean(AstNetlist* nodep) { + UINFO(2, __FUNCTION__ << ":"); + { + std::vector castWrapsToDelete; + v3Global.rootp()->foreach([&castWrapsToDelete](AstCastWrap* nodep) { + UINFO(6, " Replace " << nodep << " w/ " << nodep->lhsp()); + castWrapsToDelete.push_back(nodep); + }); + for (AstCastWrap* const nodep : castWrapsToDelete) { + nodep->replaceWith(nodep->lhsp()->unlinkFrBack()); + VL_DO_DANGLING(nodep->deleteTree(), nodep); + } + } + V3Global::dumpCheckGlobalTree("widthcommit_clean", 0, dumpTreeEitherLevel() >= 6); +} diff --git a/src/V3WidthCommit.h b/src/V3WidthCommit.h index 03b18d23d..218d0c086 100644 --- a/src/V3WidthCommit.h +++ b/src/V3WidthCommit.h @@ -42,6 +42,7 @@ public: // Final step... Mark all widths as equal static void widthCommit(AstNetlist* nodep) VL_MT_DISABLED; + static void widthCommitClean(AstNetlist* nodep) VL_MT_DISABLED; }; //###################################################################### diff --git a/src/V3WidthSel.cpp b/src/V3WidthSel.cpp index 055755842..804f7a7ad 100644 --- a/src/V3WidthSel.cpp +++ b/src/V3WidthSel.cpp @@ -174,8 +174,15 @@ class WidthSelVisitor final : public VNVisitor { } else { extendp = new AstExtend{fl, indexp}; } - extendp->dtypeSetLogicUnsized( - 32, std::max(V3Number::log2b(elwidth) + 1, indexp->widthMin()), VSigning::UNSIGNED); + if (indexp->dtypep()->isFourstate()) { + extendp->dtypeSetLogicUnsized( + 32, std::max(V3Number::log2b(elwidth) + 1, indexp->widthMin()), + VSigning::UNSIGNED); + } else { + extendp->dtypeSetBitUnsized(32, + std::max(V3Number::log2b(elwidth) + 1, indexp->widthMin()), + VSigning::UNSIGNED); + } AstNodeExpr* const mulp = new AstMul{fl, new AstConst{fl, AstConst::Unsized32{}, elwidth}, // Extend needed as index might be e.g. 3 bits but constant e.g. 5 bits diff --git a/src/Verilator.cpp b/src/Verilator.cpp index b1f0a9af0..2b19001e5 100644 --- a/src/Verilator.cpp +++ b/src/Verilator.cpp @@ -57,6 +57,7 @@ #include "V3File.h" #include "V3Force.h" #include "V3Fork.h" +#include "V3Fourstate.h" #include "V3FsmDetect.h" #include "V3FuncOpt.h" #include "V3Gate.h" @@ -301,6 +302,8 @@ static void process() { // No more AstGenBlocks after this V3Begin::debeginAll(v3Global.rootp()); // Flatten cell names, before inliner + if (v3Global.opt.fourstate()) V3Fourstate::fourstateAll(v3Global.rootp()); + V3WidthCommit::widthCommitClean(v3Global.rootp()); // Expand inouts, stage 2 // Also simplify pin connections to always be AssignWs in prep for V3Unknown V3Tristate::tristateAll(v3Global.rootp()); @@ -561,6 +564,11 @@ static void process() { V3Expand::expandAll(v3Global.rootp()); } + if (!v3Global.opt.lintOnly() && !v3Global.opt.serializeOnly() + && v3Global.opt.fourstate()) { + V3Fourstate::fourstateShuffleAll(v3Global.rootp()); + } + // Propagate constants across WORDSEL arrayed temporaries if (!v3Global.opt.serializeOnly() && v3Global.opt.fSubst()) { // Constant folding of expanded stuff diff --git a/test_regress/Makefile b/test_regress/Makefile index fdf66a181..42e74203a 100644 --- a/test_regress/Makefile +++ b/test_regress/Makefile @@ -43,7 +43,7 @@ endif ###################################################################### -SCENARIOS ?= --vlt --vltmt --dist +SCENARIOS ?= --vlt --vltmt --dist --vlt4 --vltmt4 DRIVER_HASHSET ?= .PHONY: test diff --git a/test_regress/driver.py b/test_regress/driver.py index 0aaca7c16..b589a637c 100755 --- a/test_regress/driver.py +++ b/test_regress/driver.py @@ -44,7 +44,9 @@ All_Scenarios = { 'xrun': ['linter', 'simulator', 'simulator_st', 'xrun'], 'xsim': ['linter', 'simulator', 'simulator_st', 'xsim'], 'vlt': ['linter', 'simulator', 'simulator_st', 'vlt_all', 'vlt'], + 'vlt4': ['linter', 'simulator', 'simulator_st', 'vlt_all', 'vlt'], 'vltmt': ['simulator', 'vlt_all', 'vltmt'], + 'vltmt4': ['simulator', 'vlt_all', 'vltmt'], # yapf: enable } @@ -731,11 +733,13 @@ class VlTest: # Make e.g. self.vlt, self.vltmt etc self.vlt = False # Set below also self.vltmt = False # Set below also + self.vlt4 = False # Set below also + self.vltmt4 = False # Set below also self.xsim = False # Set below also for ascenario in All_Scenarios: self.__dict__[ascenario] = False self.__dict__[scenario] = True - self.vlt_all = self.vlt or self.vltmt # Any Verilator scenario + self.vlt_all = self.vlt or self.vltmt or self.vlt4 or self.vltmt4 # Any Verilator scenario (self.py_filename, self.t_dir) = Runner._py_filename_adjust(self.py_filename, ".") for tdir in Args.test_dirs: # pylint: disable=redefined-outer-name @@ -895,6 +899,9 @@ class VlTest: self.top_filename = re.sub(r'\.py$', '', self.py_filename) + '.' + self.v_suffix self.pli_filename = re.sub(r'\.py$', '', self.py_filename) + '.cpp' self.top_shell_filename = self.obj_dir + "/" + self.vm_prefix + "__top.v" + self.twostate_capable = True + self.fourstate_capable = True + self.fourstate_nowarn = True # This is only a temporary workaround def _define_opt_calc(self) -> str: return "--define " if self.xsim else "+define+" @@ -1150,9 +1157,10 @@ class VlTest: verilator_flags += ["--trace-vcd"] if Args.gdbsim or Args.rrsim: verilator_flags += ["-CFLAGS -ggdb -LDFLAGS -ggdb"] - verilator_flags += ["--x-assign unique"] # More likely to be buggy + if not (param['vlt4'] or param['vltmt4']): + verilator_flags += ["--x-assign unique"] # More likely to be buggy - if param['vltmt']: + if param['vltmt'] or param['vltmt4']: verilator_flags += ["--debug-partition"] if param['threads'] >= 0: verilator_flags += ["--threads", str(param['threads'])] @@ -1160,6 +1168,10 @@ class VlTest: verilator_flags += ["--exe"] if param['make_main'] and param['verilator_make_gmake']: verilator_flags += ["../" + self.main_filename] + if param['vlt4'] or param['vltmt4']: + verilator_flags += ["--fourstate"] + if self.fourstate_nowarn: + verilator_flags += ["-Wno-FUTURE", "-Wno-CASTFOURSTATE"] cmdargs = [ "--prefix", @@ -1216,7 +1228,7 @@ class VlTest: if re.search(r'(^|\s)-?-threads\s', checkflags): self.error("Specify threads via 'threads=' argument, not as a command line option") - if param['threads'] < 0 and param['vltmt']: + if param['threads'] < 0 and (param['vltmt'] or param['vltmt4']): param['threads'] = calc_threads(Vltmt_Threads) if not param['context_threads']: param['context_threads'] = param['threads'] if (param['threads'] >= 1) else 1 @@ -1358,6 +1370,15 @@ class VlTest: self.skip("Test requires Coroutines; ignore error since not available\n") return + if not self.twostate_capable and (param['vlt'] or param['vltmt']): + self.skip("Test is not twostate capable") + return + + if not self.fourstate_capable and (param['vlt4'] or param['vltmt4']): + self.skip("Test is not fourstate capable - maybe verilator does not" + "support all used features") + return + if self.timing and self.sc and re.search(r'Ubuntu 24.04', distro.name( pretty=True)) and re.search(r'clang', self.cxx_version): self.skip( @@ -1869,6 +1890,11 @@ class VlTest: tee=True, verilator_run=False) -> bool: # Move gcov data to parallel area + if not self.fourstate_capable and (self.vlt4 or self.vltmt4): + self.skip("Test is not fourstate capable - maybe verilator does not" + "support all used features") + return False + try: command = ' '.join(cmd) except TypeError: diff --git a/test_regress/t/t_a2_first_sc.py b/test_regress/t/t_a2_first_sc.py index 16ed8d0c0..ba9bd88bd 100755 --- a/test_regress/t/t_a2_first_sc.py +++ b/test_regress/t/t_a2_first_sc.py @@ -15,6 +15,7 @@ import vltest_bootstrap test.priority(100) test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_a1_first_cc.v" test.leak_check_disable() diff --git a/test_regress/t/t_alias_force.py b/test_regress/t/t_alias_force.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_alias_force.py +++ b/test_regress/t/t_alias_force.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_alias_ports_unsup.py b/test_regress/t/t_alias_ports_unsup.py index 1952b53a1..873d22c46 100755 --- a/test_regress/t/t_alias_ports_unsup.py +++ b/test_regress/t/t_alias_ports_unsup.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_alias_simple.py b/test_regress/t/t_alias_simple.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_alias_simple.py +++ b/test_regress/t/t_alias_simple.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_alias_sub_select.py b/test_regress/t/t_alias_sub_select.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_alias_sub_select.py +++ b/test_regress/t/t_alias_sub_select.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_alias_transitive.py b/test_regress/t/t_alias_transitive.py index 84b274f68..17424b42f 100755 --- a/test_regress/t/t_alias_transitive.py +++ b/test_regress/t/t_alias_transitive.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_alias_tristate_unsup.py b/test_regress/t/t_alias_tristate_unsup.py index 1952b53a1..873d22c46 100755 --- a/test_regress/t/t_alias_tristate_unsup.py +++ b/test_regress/t/t_alias_tristate_unsup.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_altera_lpm_add_sub.py b/test_regress/t/t_altera_lpm_add_sub.py index f26c3d861..62d0f361f 100755 --- a/test_regress/t/t_altera_lpm_add_sub.py +++ b/test_regress/t/t_altera_lpm_add_sub.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) diff --git a/test_regress/t/t_altera_lpm_and.py b/test_regress/t/t_altera_lpm_and.py index f26c3d861..62d0f361f 100755 --- a/test_regress/t/t_altera_lpm_and.py +++ b/test_regress/t/t_altera_lpm_and.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) diff --git a/test_regress/t/t_altera_lpm_clshift.py b/test_regress/t/t_altera_lpm_clshift.py index f26c3d861..62d0f361f 100755 --- a/test_regress/t/t_altera_lpm_clshift.py +++ b/test_regress/t/t_altera_lpm_clshift.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) diff --git a/test_regress/t/t_altera_lpm_compare.py b/test_regress/t/t_altera_lpm_compare.py index f26c3d861..62d0f361f 100755 --- a/test_regress/t/t_altera_lpm_compare.py +++ b/test_regress/t/t_altera_lpm_compare.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) diff --git a/test_regress/t/t_altera_lpm_counter.py b/test_regress/t/t_altera_lpm_counter.py index 971d7ce7b..5434d8c59 100755 --- a/test_regress/t/t_altera_lpm_counter.py +++ b/test_regress/t/t_altera_lpm_counter.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) diff --git a/test_regress/t/t_altera_lpm_decode.py b/test_regress/t/t_altera_lpm_decode.py index f26c3d861..62d0f361f 100755 --- a/test_regress/t/t_altera_lpm_decode.py +++ b/test_regress/t/t_altera_lpm_decode.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) diff --git a/test_regress/t/t_altera_lpm_divide.py b/test_regress/t/t_altera_lpm_divide.py index f26c3d861..62d0f361f 100755 --- a/test_regress/t/t_altera_lpm_divide.py +++ b/test_regress/t/t_altera_lpm_divide.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) diff --git a/test_regress/t/t_altera_lpm_fifo.py b/test_regress/t/t_altera_lpm_fifo.py index f26c3d861..62d0f361f 100755 --- a/test_regress/t/t_altera_lpm_fifo.py +++ b/test_regress/t/t_altera_lpm_fifo.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) diff --git a/test_regress/t/t_altera_lpm_fifo_dc.py b/test_regress/t/t_altera_lpm_fifo_dc.py index f26c3d861..62d0f361f 100755 --- a/test_regress/t/t_altera_lpm_fifo_dc.py +++ b/test_regress/t/t_altera_lpm_fifo_dc.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) diff --git a/test_regress/t/t_altera_lpm_mult.py b/test_regress/t/t_altera_lpm_mult.py index f26c3d861..62d0f361f 100755 --- a/test_regress/t/t_altera_lpm_mult.py +++ b/test_regress/t/t_altera_lpm_mult.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) diff --git a/test_regress/t/t_altera_lpm_mult_noinl.py b/test_regress/t/t_altera_lpm_mult_noinl.py index ed460d248..4c8a994f0 100755 --- a/test_regress/t/t_altera_lpm_mult_noinl.py +++ b/test_regress/t/t_altera_lpm_mult_noinl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) module = re.sub(r'_noinl', '', module) diff --git a/test_regress/t/t_altera_lpm_mux.py b/test_regress/t/t_altera_lpm_mux.py index f26c3d861..62d0f361f 100755 --- a/test_regress/t/t_altera_lpm_mux.py +++ b/test_regress/t/t_altera_lpm_mux.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) diff --git a/test_regress/t/t_altera_lpm_or.py b/test_regress/t/t_altera_lpm_or.py index f26c3d861..62d0f361f 100755 --- a/test_regress/t/t_altera_lpm_or.py +++ b/test_regress/t/t_altera_lpm_or.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) diff --git a/test_regress/t/t_altera_lpm_ram_dp.py b/test_regress/t/t_altera_lpm_ram_dp.py index f26c3d861..62d0f361f 100755 --- a/test_regress/t/t_altera_lpm_ram_dp.py +++ b/test_regress/t/t_altera_lpm_ram_dp.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) diff --git a/test_regress/t/t_altera_lpm_ram_dq.py b/test_regress/t/t_altera_lpm_ram_dq.py index f26c3d861..62d0f361f 100755 --- a/test_regress/t/t_altera_lpm_ram_dq.py +++ b/test_regress/t/t_altera_lpm_ram_dq.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) diff --git a/test_regress/t/t_altera_lpm_ram_io.py b/test_regress/t/t_altera_lpm_ram_io.py index f26c3d861..62d0f361f 100755 --- a/test_regress/t/t_altera_lpm_ram_io.py +++ b/test_regress/t/t_altera_lpm_ram_io.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) diff --git a/test_regress/t/t_altera_lpm_rom.py b/test_regress/t/t_altera_lpm_rom.py index f26c3d861..62d0f361f 100755 --- a/test_regress/t/t_altera_lpm_rom.py +++ b/test_regress/t/t_altera_lpm_rom.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) diff --git a/test_regress/t/t_altera_lpm_xor.py b/test_regress/t/t_altera_lpm_xor.py index f26c3d861..62d0f361f 100755 --- a/test_regress/t/t_altera_lpm_xor.py +++ b/test_regress/t/t_altera_lpm_xor.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) diff --git a/test_regress/t/t_always_nosplit.py b/test_regress/t/t_always_nosplit.py index d33d40f72..beba77d87 100755 --- a/test_regress/t/t_always_nosplit.py +++ b/test_regress/t/t_always_nosplit.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--stats"]) diff --git a/test_regress/t/t_always_reorder_inlined_func.py b/test_regress/t/t_always_reorder_inlined_func.py index 692e056be..7df8d0daa 100755 --- a/test_regress/t/t_always_reorder_inlined_func.py +++ b/test_regress/t/t_always_reorder_inlined_func.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_always_split.py b/test_regress/t/t_always_split.py index f5ececdbb..54bbec7c0 100755 --- a/test_regress/t/t_always_split.py +++ b/test_regress/t/t_always_split.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--stats"]) diff --git a/test_regress/t/t_always_split_rst.py b/test_regress/t/t_always_split_rst.py index 5afd83272..fd125caa5 100755 --- a/test_regress/t/t_always_split_rst.py +++ b/test_regress/t/t_always_split_rst.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--stats", test.wno_unopthreads_for_few_cores]) diff --git a/test_regress/t/t_always_splitord.py b/test_regress/t/t_always_splitord.py index d133a773e..e8149422c 100755 --- a/test_regress/t/t_always_splitord.py +++ b/test_regress/t/t_always_splitord.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--stats"]) diff --git a/test_regress/t/t_array_compare.py b/test_regress/t/t_array_compare.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_array_compare.py +++ b/test_regress/t/t_array_compare.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_array_in_struct.py b/test_regress/t/t_array_in_struct.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_array_in_struct.py +++ b/test_regress/t/t_array_in_struct.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_array_mda.py b/test_regress/t/t_array_mda.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_array_mda.py +++ b/test_regress/t/t_array_mda.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_array_method.py b/test_regress/t/t_array_method.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_array_method.py +++ b/test_regress/t/t_array_method.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_array_non_blocking_loop.py b/test_regress/t/t_array_non_blocking_loop.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_array_non_blocking_loop.py +++ b/test_regress/t/t_array_non_blocking_loop.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_array_packed_endian.py b/test_regress/t/t_array_packed_endian.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_array_packed_endian.py +++ b/test_regress/t/t_array_packed_endian.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_array_packed_sign.py b/test_regress/t/t_array_packed_sign.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_array_packed_sign.py +++ b/test_regress/t/t_array_packed_sign.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_array_packed_sysfunct.py b/test_regress/t/t_array_packed_sysfunct.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_array_packed_sysfunct.py +++ b/test_regress/t/t_array_packed_sysfunct.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_array_packed_write_read.py b/test_regress/t/t_array_packed_write_read.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_array_packed_write_read.py +++ b/test_regress/t/t_array_packed_write_read.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_array_pattern_2d.py b/test_regress/t/t_array_pattern_2d.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_array_pattern_2d.py +++ b/test_regress/t/t_array_pattern_2d.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_array_pattern_concat.py b/test_regress/t/t_array_pattern_concat.py index 8a938befd..a10e2547d 100755 --- a/test_regress/t/t_array_pattern_concat.py +++ b/test_regress/t/t_array_pattern_concat.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_array_pattern_packed.py b/test_regress/t/t_array_pattern_packed.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_array_pattern_packed.py +++ b/test_regress/t/t_array_pattern_packed.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_array_pattern_side_effect.py b/test_regress/t/t_array_pattern_side_effect.py index 8a938befd..a10e2547d 100755 --- a/test_regress/t/t_array_pattern_side_effect.py +++ b/test_regress/t/t_array_pattern_side_effect.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_array_pattern_unpacked.py b/test_regress/t/t_array_pattern_unpacked.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_array_pattern_unpacked.py +++ b/test_regress/t/t_array_pattern_unpacked.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_array_query.py b/test_regress/t/t_array_query.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_array_query.py +++ b/test_regress/t/t_array_query.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_array_query_with.py b/test_regress/t/t_array_query_with.py index 690ae1cbf..6dc1eb6bb 100755 --- a/test_regress/t/t_array_query_with.py +++ b/test_regress/t/t_array_query_with.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--assert']) diff --git a/test_regress/t/t_array_rev.py b/test_regress/t/t_array_rev.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_array_rev.py +++ b/test_regress/t/t_array_rev.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_array_sel_short.py b/test_regress/t/t_array_sel_short.py index f7f552639..fdb979698 100755 --- a/test_regress/t/t_array_sel_short.py +++ b/test_regress/t/t_array_sel_short.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios("simulator") +test.fourstate_capable = False test.compile(verilator_flags2=["--dump-tree"]) diff --git a/test_regress/t/t_array_sel_wide.py b/test_regress/t/t_array_sel_wide.py index 66009b455..52533feae 100755 --- a/test_regress/t/t_array_sel_wide.py +++ b/test_regress/t/t_array_sel_wide.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_array_type_methods.py b/test_regress/t/t_array_type_methods.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_array_type_methods.py +++ b/test_regress/t/t_array_type_methods.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_array_unpacked_public.py b/test_regress/t/t_array_unpacked_public.py index 96cc687b0..a7d1a28e4 100755 --- a/test_regress/t/t_array_unpacked_public.py +++ b/test_regress/t/t_array_unpacked_public.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--public-flat-rw"]) diff --git a/test_regress/t/t_assert_always_unbounded.py b/test_regress/t/t_assert_always_unbounded.py index 2351d6963..4de85e908 100755 --- a/test_regress/t/t_assert_always_unbounded.py +++ b/test_regress/t/t_assert_always_unbounded.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_assert_assert.py b/test_regress/t/t_assert_assert.py index 84b274f68..17424b42f 100755 --- a/test_regress/t/t_assert_assert.py +++ b/test_regress/t/t_assert_assert.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_assert_bang_in_seq.py b/test_regress/t/t_assert_bang_in_seq.py index 032a880d7..e5603321a 100755 --- a/test_regress/t/t_assert_bang_in_seq.py +++ b/test_regress/t/t_assert_bang_in_seq.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--assert', '--timing']) diff --git a/test_regress/t/t_assert_basic.py b/test_regress/t/t_assert_basic.py index cae36a498..f79d4bbfe 100755 --- a/test_regress/t/t_assert_basic.py +++ b/test_regress/t/t_assert_basic.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--assert'], nc_flags2=['+assert']) diff --git a/test_regress/t/t_assert_basic_cover.py b/test_regress/t/t_assert_basic_cover.py index 48c7114a7..b50b01789 100755 --- a/test_regress/t/t_assert_basic_cover.py +++ b/test_regress/t/t_assert_basic_cover.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_assert_basic.v" test.compile(verilator_flags2=['--assert --cc --coverage-user']) diff --git a/test_regress/t/t_assert_basic_fail.py b/test_regress/t/t_assert_basic_fail.py index b967c0080..bfd5fc3ae 100755 --- a/test_regress/t/t_assert_basic_fail.py +++ b/test_regress/t/t_assert_basic_fail.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_assert_basic.v" test.compile(v_flags2=[ diff --git a/test_regress/t/t_assert_basic_off.py b/test_regress/t/t_assert_basic_off.py index ece9748ce..72b66d2ae 100755 --- a/test_regress/t/t_assert_basic_off.py +++ b/test_regress/t/t_assert_basic_off.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_assert_basic.v" test.compile(v_flags2=[]) diff --git a/test_regress/t/t_assert_casez.py b/test_regress/t/t_assert_casez.py index 690ae1cbf..6dc1eb6bb 100755 --- a/test_regress/t/t_assert_casez.py +++ b/test_regress/t/t_assert_casez.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--assert']) diff --git a/test_regress/t/t_assert_clock_event_unsup.py b/test_regress/t/t_assert_clock_event_unsup.py index b5718946c..3b6e0ee4f 100755 --- a/test_regress/t/t_assert_clock_event_unsup.py +++ b/test_regress/t/t_assert_clock_event_unsup.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert'], fails=True) diff --git a/test_regress/t/t_assert_consec_rep.py b/test_regress/t/t_assert_consec_rep.py index 8c22ba5dd..c87bc1954 100755 --- a/test_regress/t/t_assert_consec_rep.py +++ b/test_regress/t/t_assert_consec_rep.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') # UNOPTTHREADS in vltmt due to many small assertion states +test.fourstate_capable = False test.compile(verilator_flags2=['--assert', '--timing']) diff --git a/test_regress/t/t_assert_consec_rep_large.py b/test_regress/t/t_assert_consec_rep_large.py index 23f04b54c..06ba763e5 100755 --- a/test_regress/t/t_assert_consec_rep_large.py +++ b/test_regress/t/t_assert_consec_rep_large.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(verilator_flags2=['--assert', '--timing']) diff --git a/test_regress/t/t_assert_cover.py b/test_regress/t/t_assert_cover.py index 175cad18a..e4aaf22ae 100755 --- a/test_regress/t/t_assert_cover.py +++ b/test_regress/t/t_assert_cover.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_assert_cover.v" test.compile(verilator_flags2=['--assert --cc --coverage-user'], diff --git a/test_regress/t/t_assert_ctl_arg.py b/test_regress/t/t_assert_ctl_arg.py index 573f5c1b5..6477ba350 100755 --- a/test_regress/t/t_assert_ctl_arg.py +++ b/test_regress/t/t_assert_ctl_arg.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile( make_top_shell=False, diff --git a/test_regress/t/t_assert_ctl_arg_noinl.py b/test_regress/t/t_assert_ctl_arg_noinl.py index 1ea437d1f..b7b9fa160 100755 --- a/test_regress/t/t_assert_ctl_arg_noinl.py +++ b/test_regress/t/t_assert_ctl_arg_noinl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t_assert_ctl_arg.v" test.pli_filename = "t/t_assert_ctl_arg.cpp" diff --git a/test_regress/t/t_assert_ctl_concurrent.py b/test_regress/t/t_assert_ctl_concurrent.py index 5f3b89cca..e00d8868f 100755 --- a/test_regress/t/t_assert_ctl_concurrent.py +++ b/test_regress/t/t_assert_ctl_concurrent.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary --assert"]) diff --git a/test_regress/t/t_assert_ctl_concurrent_noinl.py b/test_regress/t/t_assert_ctl_concurrent_noinl.py index 1e71be98c..e720452f1 100755 --- a/test_regress/t/t_assert_ctl_concurrent_noinl.py +++ b/test_regress/t/t_assert_ctl_concurrent_noinl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t_assert_ctl_concurrent.v" test.compile(verilator_flags2=["--binary --assert --fno-inline"]) diff --git a/test_regress/t/t_assert_ctl_immediate_noinl.py b/test_regress/t/t_assert_ctl_immediate_noinl.py index 1a57006dc..a0557437f 100755 --- a/test_regress/t/t_assert_ctl_immediate_noinl.py +++ b/test_regress/t/t_assert_ctl_immediate_noinl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t_assert_ctl_immediate.v" test.golden_filename = "t/t_assert_ctl_immediate.out" diff --git a/test_regress/t/t_assert_ctl_lock.py b/test_regress/t/t_assert_ctl_lock.py index fdd1c0d4d..e648f37b3 100755 --- a/test_regress/t/t_assert_ctl_lock.py +++ b/test_regress/t/t_assert_ctl_lock.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary --assert"]) diff --git a/test_regress/t/t_assert_ctl_lock_noinl.py b/test_regress/t/t_assert_ctl_lock_noinl.py index 83440d018..9f3e88e68 100755 --- a/test_regress/t/t_assert_ctl_lock_noinl.py +++ b/test_regress/t/t_assert_ctl_lock_noinl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t_assert_ctl_lock.v" test.compile(verilator_flags2=["--binary --assert --fno-inline"]) diff --git a/test_regress/t/t_assert_ctl_pass_actions.py b/test_regress/t/t_assert_ctl_pass_actions.py index fdd1c0d4d..e648f37b3 100755 --- a/test_regress/t/t_assert_ctl_pass_actions.py +++ b/test_regress/t/t_assert_ctl_pass_actions.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary --assert"]) diff --git a/test_regress/t/t_assert_disable_bad.py b/test_regress/t/t_assert_disable_bad.py index b5718946c..3b6e0ee4f 100755 --- a/test_regress/t/t_assert_disable_bad.py +++ b/test_regress/t/t_assert_disable_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert'], fails=True) diff --git a/test_regress/t/t_assert_disable_count.py b/test_regress/t/t_assert_disable_count.py index 690ae1cbf..6dc1eb6bb 100755 --- a/test_regress/t/t_assert_disable_count.py +++ b/test_regress/t/t_assert_disable_count.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--assert']) diff --git a/test_regress/t/t_assert_disable_iff.py b/test_regress/t/t_assert_disable_iff.py index 6832b1356..4eca473d5 100755 --- a/test_regress/t/t_assert_disable_iff.py +++ b/test_regress/t/t_assert_disable_iff.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--assert --cc --coverage-user']) diff --git a/test_regress/t/t_assert_elab_p.py b/test_regress/t/t_assert_elab_p.py index 8443b98f6..cca537c7d 100755 --- a/test_regress/t/t_assert_elab_p.py +++ b/test_regress/t/t_assert_elab_p.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator_st') +test.fourstate_capable = False test.compile(verilator_flags2=['--no-skip-identical'], expect_filename=test.golden_filename) diff --git a/test_regress/t/t_assert_future.py b/test_regress/t/t_assert_future.py index a9ba85b06..ae85fce1d 100755 --- a/test_regress/t/t_assert_future.py +++ b/test_regress/t/t_assert_future.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--assert']) diff --git a/test_regress/t/t_assert_future_unsup.py b/test_regress/t/t_assert_future_unsup.py index f3bbcad9d..f38b02634 100755 --- a/test_regress/t/t_assert_future_unsup.py +++ b/test_regress/t/t_assert_future_unsup.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_assert_goto_rep.py b/test_regress/t/t_assert_goto_rep.py index b92324a60..9e52f845a 100755 --- a/test_regress/t/t_assert_goto_rep.py +++ b/test_regress/t/t_assert_goto_rep.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--timing', '--assert']) diff --git a/test_regress/t/t_assert_iff.py b/test_regress/t/t_assert_iff.py index 6832b1356..4eca473d5 100755 --- a/test_regress/t/t_assert_iff.py +++ b/test_regress/t/t_assert_iff.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--assert --cc --coverage-user']) diff --git a/test_regress/t/t_assert_iff_bad1.py b/test_regress/t/t_assert_iff_bad1.py index 1eded5b63..7e413af12 100755 --- a/test_regress/t/t_assert_iff_bad1.py +++ b/test_regress/t/t_assert_iff_bad1.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = 't_assert_iff.v' test.compile(verilator_flags2=['--assert --cc --coverage-user -DFAIL1']) diff --git a/test_regress/t/t_assert_iff_bad2.py b/test_regress/t/t_assert_iff_bad2.py index 528ac5a33..2494ed0f7 100755 --- a/test_regress/t/t_assert_iff_bad2.py +++ b/test_regress/t/t_assert_iff_bad2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = 't_assert_iff.v' test.compile(verilator_flags2=['--assert --cc --coverage-user -DFAIL2']) diff --git a/test_regress/t/t_assert_iff_clk.py b/test_regress/t/t_assert_iff_clk.py index 35e44000c..84d6e744b 100755 --- a/test_regress/t/t_assert_iff_clk.py +++ b/test_regress/t/t_assert_iff_clk.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=['--assert', '--timing']) diff --git a/test_regress/t/t_assert_implication.py b/test_regress/t/t_assert_implication.py index 3c390daaf..9b307b320 100755 --- a/test_regress/t/t_assert_implication.py +++ b/test_regress/t/t_assert_implication.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--assert --cc']) diff --git a/test_regress/t/t_assert_implication_bad.py b/test_regress/t/t_assert_implication_bad.py index c6162d8aa..68cbeca1a 100755 --- a/test_regress/t/t_assert_implication_bad.py +++ b/test_regress/t/t_assert_implication_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_assert_implication.v" test.compile(v_flags2=['+define+FAIL_ASSERT_1'], verilator_flags2=['--assert --cc']) diff --git a/test_regress/t/t_assert_implication_coverage.py b/test_regress/t/t_assert_implication_coverage.py index b375cb363..cb6dbf6f1 100755 --- a/test_regress/t/t_assert_implication_coverage.py +++ b/test_regress/t/t_assert_implication_coverage.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--assert --cc --coverage']) diff --git a/test_regress/t/t_assert_inside_cond.py b/test_regress/t/t_assert_inside_cond.py index 5ae697d72..20c131146 100755 --- a/test_regress/t/t_assert_inside_cond.py +++ b/test_regress/t/t_assert_inside_cond.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["-x-assign 0 --assert +define+T_ASSERT_INSIDE_COND"]) diff --git a/test_regress/t/t_assert_inside_cond_bad.py b/test_regress/t/t_assert_inside_cond_bad.py index 382f607ed..95fd1f1a6 100755 --- a/test_regress/t/t_assert_inside_cond_bad.py +++ b/test_regress/t/t_assert_inside_cond_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_assert_inside_cond.v" test.compile(verilator_flags2=["-x-assign 0 --assert +define+T_ASSERT_INSIDE_COND_BAD"]) diff --git a/test_regress/t/t_assert_nonconsec_rep.py b/test_regress/t/t_assert_nonconsec_rep.py index b92324a60..9e52f845a 100755 --- a/test_regress/t/t_assert_nonconsec_rep.py +++ b/test_regress/t/t_assert_nonconsec_rep.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--timing', '--assert']) diff --git a/test_regress/t/t_assert_past.py b/test_regress/t/t_assert_past.py index 690ae1cbf..6dc1eb6bb 100755 --- a/test_regress/t/t_assert_past.py +++ b/test_regress/t/t_assert_past.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--assert']) diff --git a/test_regress/t/t_assert_pre.py b/test_regress/t/t_assert_pre.py index 84b274f68..17424b42f 100755 --- a/test_regress/t/t_assert_pre.py +++ b/test_regress/t/t_assert_pre.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_assert_preponed_nba.py b/test_regress/t/t_assert_preponed_nba.py index 46d1fe4c0..bd6ade23d 100755 --- a/test_regress/t/t_assert_preponed_nba.py +++ b/test_regress/t/t_assert_preponed_nba.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary']) diff --git a/test_regress/t/t_assert_procedural.py b/test_regress/t/t_assert_procedural.py index 8a938befd..a10e2547d 100755 --- a/test_regress/t/t_assert_procedural.py +++ b/test_regress/t/t_assert_procedural.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_assert_procedural_clk_bad.py b/test_regress/t/t_assert_procedural_clk_bad.py index 695572bb1..d72ea051d 100755 --- a/test_regress/t/t_assert_procedural_clk_bad.py +++ b/test_regress/t/t_assert_procedural_clk_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(expect_filename=test.golden_filename, fails=True) diff --git a/test_regress/t/t_assert_procedural_gated.py b/test_regress/t/t_assert_procedural_gated.py index 8a938befd..a10e2547d 100755 --- a/test_regress/t/t_assert_procedural_gated.py +++ b/test_regress/t/t_assert_procedural_gated.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_assert_property_stop_bad.py b/test_regress/t/t_assert_property_stop_bad.py index 20a9b4950..f7e7bf730 100755 --- a/test_regress/t/t_assert_property_stop_bad.py +++ b/test_regress/t/t_assert_property_stop_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary']) diff --git a/test_regress/t/t_assert_question.py b/test_regress/t/t_assert_question.py index 690ae1cbf..6dc1eb6bb 100755 --- a/test_regress/t/t_assert_question.py +++ b/test_regress/t/t_assert_question.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--assert']) diff --git a/test_regress/t/t_assert_rep_range_unsup.py b/test_regress/t/t_assert_rep_range_unsup.py index 74c8e2367..47042ce5c 100755 --- a/test_regress/t/t_assert_rep_range_unsup.py +++ b/test_regress/t/t_assert_rep_range_unsup.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert'], fails=True) diff --git a/test_regress/t/t_assert_sampled.py b/test_regress/t/t_assert_sampled.py index 690ae1cbf..6dc1eb6bb 100755 --- a/test_regress/t/t_assert_sampled.py +++ b/test_regress/t/t_assert_sampled.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--assert']) diff --git a/test_regress/t/t_assert_seq_clocking.py b/test_regress/t/t_assert_seq_clocking.py index 23f04b54c..06ba763e5 100755 --- a/test_regress/t/t_assert_seq_clocking.py +++ b/test_regress/t/t_assert_seq_clocking.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(verilator_flags2=['--assert', '--timing']) diff --git a/test_regress/t/t_assert_synth.py b/test_regress/t/t_assert_synth.py index cae36a498..f79d4bbfe 100755 --- a/test_regress/t/t_assert_synth.py +++ b/test_regress/t/t_assert_synth.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--assert'], nc_flags2=['+assert']) diff --git a/test_regress/t/t_assert_synth_full.py b/test_regress/t/t_assert_synth_full.py index 51a4b04ab..593979d3e 100755 --- a/test_regress/t/t_assert_synth_full.py +++ b/test_regress/t/t_assert_synth_full.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_assert_synth.v" test.compile(v_flags2=['+define+FAILING_FULL +define+ATTRIBUTES'], diff --git a/test_regress/t/t_assert_synth_full_vlt.py b/test_regress/t/t_assert_synth_full_vlt.py index ddb365b89..e98e0648b 100755 --- a/test_regress/t/t_assert_synth_full_vlt.py +++ b/test_regress/t/t_assert_synth_full_vlt.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_assert_synth.v" test.compile(v_flags2=['+define+FAILING_FULL', "t/t_assert_synth_full.vlt"], diff --git a/test_regress/t/t_assert_synth_off.py b/test_regress/t/t_assert_synth_off.py index a3749ba4e..a82c0781b 100755 --- a/test_regress/t/t_assert_synth_off.py +++ b/test_regress/t/t_assert_synth_off.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_assert_synth.v" test.compile(v_flags2=[ diff --git a/test_regress/t/t_assert_synth_parallel.py b/test_regress/t/t_assert_synth_parallel.py index ebc736037..32351a13b 100755 --- a/test_regress/t/t_assert_synth_parallel.py +++ b/test_regress/t/t_assert_synth_parallel.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_assert_synth.v" test.compile(v_flags2=['+define+FAILING_PARALLEL', '+define+ATTRIBUTES'], diff --git a/test_regress/t/t_assert_synth_parallel_vlt.py b/test_regress/t/t_assert_synth_parallel_vlt.py index 583578775..b36695243 100755 --- a/test_regress/t/t_assert_synth_parallel_vlt.py +++ b/test_regress/t/t_assert_synth_parallel_vlt.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_assert_synth.v" test.compile(v_flags2=['+define+FAILING_PARALLEL', "t/t_assert_synth_parallel.vlt"], diff --git a/test_regress/t/t_assert_unclocked_bad.py b/test_regress/t/t_assert_unclocked_bad.py index 77a0ac64b..b8c5d4bde 100755 --- a/test_regress/t/t_assert_unclocked_bad.py +++ b/test_regress/t/t_assert_unclocked_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(expect_filename=test.golden_filename, fails=True) diff --git a/test_regress/t/t_assert_unique_case.py b/test_regress/t/t_assert_unique_case.py index d51be7bb2..8541e9676 100755 --- a/test_regress/t/t_assert_unique_case.py +++ b/test_regress/t/t_assert_unique_case.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_assert_unique_case_bad.v" test.compile(verilator_flags2=["-x-assign 0 --assert-case --no-stop-fail +define+NO_STOP_FAIL"]) diff --git a/test_regress/t/t_assert_unique_case_bad.py b/test_regress/t/t_assert_unique_case_bad.py index 4286be915..67b789bb1 100755 --- a/test_regress/t/t_assert_unique_case_bad.py +++ b/test_regress/t/t_assert_unique_case_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["-x-assign 0 --assert"]) diff --git a/test_regress/t/t_assign_automatic_bad.py b/test_regress/t/t_assign_automatic_bad.py index 1d5ccb8f4..c1876edec 100755 --- a/test_regress/t/t_assign_automatic_bad.py +++ b/test_regress/t/t_assign_automatic_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_assign_deassign_concat.py b/test_regress/t/t_assign_deassign_concat.py index b7d7b425d..9676468a2 100755 --- a/test_regress/t/t_assign_deassign_concat.py +++ b/test_regress/t/t_assign_deassign_concat.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary --timing", "-Wno-IEEEMAYDEPRECATE"]) diff --git a/test_regress/t/t_assign_dff.py b/test_regress/t/t_assign_dff.py index 10f1e0290..cc58ae7a7 100755 --- a/test_regress/t/t_assign_dff.py +++ b/test_regress/t/t_assign_dff.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["-Wno-IEEEMAYDEPRECATE"]) diff --git a/test_regress/t/t_assign_expr.py b/test_regress/t/t_assign_expr.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_assign_expr.py +++ b/test_regress/t/t_assign_expr.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_assign_func.py b/test_regress/t/t_assign_func.py index 8a938befd..a10e2547d 100755 --- a/test_regress/t/t_assign_func.py +++ b/test_regress/t/t_assign_func.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_assign_inline.py b/test_regress/t/t_assign_inline.py index 54903fd3d..15da8bd6d 100755 --- a/test_regress/t/t_assign_inline.py +++ b/test_regress/t/t_assign_inline.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["-O0 -fgate"]) diff --git a/test_regress/t/t_assign_pattern_cmp.py b/test_regress/t/t_assign_pattern_cmp.py index 8a938befd..a10e2547d 100755 --- a/test_regress/t/t_assign_pattern_cmp.py +++ b/test_regress/t/t_assign_pattern_cmp.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_assign_slice_overflow.py b/test_regress/t/t_assign_slice_overflow.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_assign_slice_overflow.py +++ b/test_regress/t/t_assign_slice_overflow.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_assign_slice_overflow_ox.py b/test_regress/t/t_assign_slice_overflow_ox.py index d28c9d7e7..5ac09d865 100755 --- a/test_regress/t/t_assign_slice_overflow_ox.py +++ b/test_regress/t/t_assign_slice_overflow_ox.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t_assign_slice_overflow.v" test.compile(verilator_flags2=["-fno-expand"]) diff --git a/test_regress/t/t_assigndly_deep_ref.py b/test_regress/t/t_assigndly_deep_ref.py index 05f4c1c48..48796f962 100755 --- a/test_regress/t/t_assigndly_deep_ref.py +++ b/test_regress/t/t_assigndly_deep_ref.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=['--timing']) diff --git a/test_regress/t/t_assigndly_deep_ref_array.py b/test_regress/t/t_assigndly_deep_ref_array.py index 05f4c1c48..48796f962 100755 --- a/test_regress/t/t_assigndly_deep_ref_array.py +++ b/test_regress/t/t_assigndly_deep_ref_array.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=['--timing']) diff --git a/test_regress/t/t_assigndly_dynamic_nofork.py b/test_regress/t/t_assigndly_dynamic_nofork.py index 12f9972d3..a4abb6bf9 100755 --- a/test_regress/t/t_assigndly_dynamic_nofork.py +++ b/test_regress/t/t_assigndly_dynamic_nofork.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_assigndly_task.v" test.compile(verilator_flags2=["--timing"]) diff --git a/test_regress/t/t_assigndly_task.py b/test_regress/t/t_assigndly_task.py index 66009b455..52533feae 100755 --- a/test_regress/t/t_assigndly_task.py +++ b/test_regress/t/t_assigndly_task.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_assoc.py b/test_regress/t/t_assoc.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_assoc.py +++ b/test_regress/t/t_assoc.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_assoc2.py b/test_regress/t/t_assoc2.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_assoc2.py +++ b/test_regress/t/t_assoc2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_assoc_method.py b/test_regress/t/t_assoc_method.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_assoc_method.py +++ b/test_regress/t/t_assoc_method.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_assoc_wildcard.py b/test_regress/t/t_assoc_wildcard.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_assoc_wildcard.py +++ b/test_regress/t/t_assoc_wildcard.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_assoc_wildcard_method.py b/test_regress/t/t_assoc_wildcard_method.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_assoc_wildcard_method.py +++ b/test_regress/t/t_assoc_wildcard_method.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_ast_dump_patterns.py b/test_regress/t/t_ast_dump_patterns.py index d1bf14b33..27effe117 100755 --- a/test_regress/t/t_ast_dump_patterns.py +++ b/test_regress/t/t_ast_dump_patterns.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(verilator_flags2=["--dump-ast-patterns", "--no-skip-identical"]) diff --git a/test_regress/t/t_benchmark_mux4k.py b/test_regress/t/t_benchmark_mux4k.py index 61180d55a..315eeae75 100755 --- a/test_regress/t/t_benchmark_mux4k.py +++ b/test_regress/t/t_benchmark_mux4k.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(v_flags2=["--stats", test.wno_unopthreads_for_few_cores]) diff --git a/test_regress/t/t_benchmark_mux4k_onecpu.py b/test_regress/t/t_benchmark_mux4k_onecpu.py index fc138f8da..929354d3a 100755 --- a/test_regress/t/t_benchmark_mux4k_onecpu.py +++ b/test_regress/t/t_benchmark_mux4k_onecpu.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_benchmark_mux4k.v" test.compile(v_flags2=["--stats", test.wno_unopthreads_for_few_cores]) diff --git a/test_regress/t/t_benchmark_sim.py b/test_regress/t/t_benchmark_sim.py index 559d15b40..a7e37e849 100755 --- a/test_regress/t/t_benchmark_sim.py +++ b/test_regress/t/t_benchmark_sim.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_gen_alw.v" # Use any top file # As an example, compile and simulate the top file with varying optimization level diff --git a/test_regress/t/t_bit_scan_loops.py b/test_regress/t/t_bit_scan_loops.py index 07b7818b1..c92cb5c1c 100755 --- a/test_regress/t/t_bit_scan_loops.py +++ b/test_regress/t/t_bit_scan_loops.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False # --unroll-count 0 so the loops are recognized without relying on unrolling. test.compile(verilator_flags2=['--stats', '--unroll-count', '0']) diff --git a/test_regress/t/t_bit_scan_loops_off.py b/test_regress/t/t_bit_scan_loops_off.py index cdf34ea55..e6f3e1fb5 100755 --- a/test_regress/t/t_bit_scan_loops_off.py +++ b/test_regress/t/t_bit_scan_loops_off.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False # Reuse the same design; only the optimization switch differs. test.top_filename = "t/t_bit_scan_loops.v" diff --git a/test_regress/t/t_bit_scan_loops_xassign0.py b/test_regress/t/t_bit_scan_loops_xassign0.py index b44c2cdf7..9946a17fc 100755 --- a/test_regress/t/t_bit_scan_loops_xassign0.py +++ b/test_regress/t/t_bit_scan_loops_xassign0.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False # Reuse the same design. '--x-assign 0' makes the auto-inserted out-of-range guard on a # non-power-of-two bit-select a plain '(idx <= W-1) && vec[idx]' (AstLogAnd), rather than diff --git a/test_regress/t/t_bitsel_2d_slice.py b/test_regress/t/t_bitsel_2d_slice.py index 903201f15..03b00189e 100755 --- a/test_regress/t/t_bitsel_2d_slice.py +++ b/test_regress/t/t_bitsel_2d_slice.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios("simulator") +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_bitsel_concat.py b/test_regress/t/t_bitsel_concat.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_bitsel_concat.py +++ b/test_regress/t/t_bitsel_concat.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_bitsel_lvalue.py b/test_regress/t/t_bitsel_lvalue.py index 0379f0dd0..945124978 100755 --- a/test_regress/t/t_bitsel_lvalue.py +++ b/test_regress/t/t_bitsel_lvalue.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_bitsel_over32.py b/test_regress/t/t_bitsel_over32.py index b24c8b500..0a47a00f0 100755 --- a/test_regress/t/t_bitsel_over32.py +++ b/test_regress/t/t_bitsel_over32.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--trace-vcd']) diff --git a/test_regress/t/t_bitsel_slice.py b/test_regress/t/t_bitsel_slice.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_bitsel_slice.py +++ b/test_regress/t/t_bitsel_slice.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_bitsel_struct.py b/test_regress/t/t_bitsel_struct.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_bitsel_struct.py +++ b/test_regress/t/t_bitsel_struct.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_bitsel_struct2.py b/test_regress/t/t_bitsel_struct2.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_bitsel_struct2.py +++ b/test_regress/t/t_bitsel_struct2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_bitsel_struct3.py b/test_regress/t/t_bitsel_struct3.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_bitsel_struct3.py +++ b/test_regress/t/t_bitsel_struct3.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_bitsel_wire_array_bad.py b/test_regress/t/t_bitsel_wire_array_bad.py index 3c74ad70b..26ee06500 100755 --- a/test_regress/t/t_bitsel_wire_array_bad.py +++ b/test_regress/t/t_bitsel_wire_array_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False # Compile time only test diff --git a/test_regress/t/t_blocking.py b/test_regress/t/t_blocking.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_blocking.py +++ b/test_regress/t/t_blocking.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_case_66bits.py b/test_regress/t/t_case_66bits.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_case_66bits.py +++ b/test_regress/t/t_case_66bits.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_case_66bits_no_const_eager.py b/test_regress/t/t_case_66bits_no_const_eager.py index 6809ac70f..cc4a5cc83 100755 --- a/test_regress/t/t_case_66bits_no_const_eager.py +++ b/test_regress/t/t_case_66bits_no_const_eager.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_case_66bits.v" test.compile(verilator_flags2=['-fno-const-eager']) diff --git a/test_regress/t/t_case_66bits_noexpand.py b/test_regress/t/t_case_66bits_noexpand.py index 8674d7ee6..fbb7e413a 100755 --- a/test_regress/t/t_case_66bits_noexpand.py +++ b/test_regress/t/t_case_66bits_noexpand.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_case_66bits.v" test.compile(verilator_flags2=['-fno-expand']) diff --git a/test_regress/t/t_case_auto1.py b/test_regress/t/t_case_auto1.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_case_auto1.py +++ b/test_regress/t/t_case_auto1.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_case_call_count.py b/test_regress/t/t_case_call_count.py index df91d0e3c..120f647ff 100755 --- a/test_regress/t/t_case_call_count.py +++ b/test_regress/t/t_case_call_count.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--stats']) diff --git a/test_regress/t/t_case_decoder.py b/test_regress/t/t_case_decoder.py index 4265c138b..f1a9090a8 100755 --- a/test_regress/t/t_case_decoder.py +++ b/test_regress/t/t_case_decoder.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary', '--stats']) diff --git a/test_regress/t/t_case_decoder_off.py b/test_regress/t/t_case_decoder_off.py index abc61d879..2cff986a2 100755 --- a/test_regress/t/t_case_decoder_off.py +++ b/test_regress/t/t_case_decoder_off.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_case_decoder.v" diff --git a/test_regress/t/t_case_deep.py b/test_regress/t/t_case_deep.py index bfd4b3039..cb80aad20 100755 --- a/test_regress/t/t_case_deep.py +++ b/test_regress/t/t_case_deep.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile( # We have deep expressions we want to test diff --git a/test_regress/t/t_case_default_bad.py b/test_regress/t/t_case_default_bad.py index c7d9b21a5..692e6eeb1 100755 --- a/test_regress/t/t_case_default_bad.py +++ b/test_regress/t/t_case_default_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_case_dupitems.py b/test_regress/t/t_case_dupitems.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_case_dupitems.py +++ b/test_regress/t/t_case_dupitems.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_case_enum_complete.py b/test_regress/t/t_case_enum_complete.py index 0930535c5..351ed96be 100755 --- a/test_regress/t/t_case_enum_complete.py +++ b/test_regress/t/t_case_enum_complete.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(verilator_flags2=["-Wwarn-CASEINCOMPLETE"]) diff --git a/test_regress/t/t_case_enum_complete_wildcard.py b/test_regress/t/t_case_enum_complete_wildcard.py index 0930535c5..351ed96be 100755 --- a/test_regress/t/t_case_enum_complete_wildcard.py +++ b/test_regress/t/t_case_enum_complete_wildcard.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(verilator_flags2=["-Wwarn-CASEINCOMPLETE"]) diff --git a/test_regress/t/t_case_enum_emptyish.py b/test_regress/t/t_case_enum_emptyish.py index 84c09a3bb..73c8707f4 100755 --- a/test_regress/t/t_case_enum_emptyish.py +++ b/test_regress/t/t_case_enum_emptyish.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile( # We have deep expressions we want to test) diff --git a/test_regress/t/t_case_enum_incomplete_bad.py b/test_regress/t/t_case_enum_incomplete_bad.py index da00b062f..9c7c6999d 100755 --- a/test_regress/t/t_case_enum_incomplete_bad.py +++ b/test_regress/t/t_case_enum_incomplete_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(verilator_flags2=['--assert'], fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_case_enum_incomplete_wildcard_bad.py b/test_regress/t/t_case_enum_incomplete_wildcard_bad.py index da00b062f..9c7c6999d 100755 --- a/test_regress/t/t_case_enum_incomplete_wildcard_bad.py +++ b/test_regress/t/t_case_enum_incomplete_wildcard_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(verilator_flags2=['--assert'], fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_case_group.py b/test_regress/t/t_case_group.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_case_group.py +++ b/test_regress/t/t_case_group.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_case_huge.py b/test_regress/t/t_case_huge.py index 57891d35b..3853005ef 100755 --- a/test_regress/t/t_case_huge.py +++ b/test_regress/t/t_case_huge.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False # This tests combining CFuncs, but Dfg would inline the submodule, disabling test.compile(verilator_flags2=["--stats", "-fno-dfg"]) diff --git a/test_regress/t/t_case_huge_nocase.py b/test_regress/t/t_case_huge_nocase.py index 011bbdc67..ee3ca35cb 100755 --- a/test_regress/t/t_case_huge_nocase.py +++ b/test_regress/t/t_case_huge_nocase.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator_st') +test.fourstate_capable = False test.top_filename = 't/t_case_huge.v' test.compile(verilator_flags2=["--stats -fno-case"]) diff --git a/test_regress/t/t_case_huge_nocase_tree.py b/test_regress/t/t_case_huge_nocase_tree.py index 2083db119..26488e892 100755 --- a/test_regress/t/t_case_huge_nocase_tree.py +++ b/test_regress/t/t_case_huge_nocase_tree.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator_st') +test.fourstate_capable = False test.top_filename = 't/t_case_huge.v' test.compile(verilator_flags2=["--stats -fno-case-tree"]) diff --git a/test_regress/t/t_case_huge_noopt.py b/test_regress/t/t_case_huge_noopt.py index 5835918b6..81cbdd399 100755 --- a/test_regress/t/t_case_huge_noopt.py +++ b/test_regress/t/t_case_huge_noopt.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator_st') +test.fourstate_capable = False test.top_filename = 't/t_case_huge.v' test.compile(verilator_flags2=["--stats -fno-combine"]) diff --git a/test_regress/t/t_case_incrdecr.py b/test_regress/t/t_case_incrdecr.py index 7a37c1259..69e778e9e 100755 --- a/test_regress/t/t_case_incrdecr.py +++ b/test_regress/t/t_case_incrdecr.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--trace-vcd --fno-split -x-assign 0"]) diff --git a/test_regress/t/t_case_inside.py b/test_regress/t/t_case_inside.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_case_inside.py +++ b/test_regress/t/t_case_inside.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_case_inside_call_count.py b/test_regress/t/t_case_inside_call_count.py index df91d0e3c..120f647ff 100755 --- a/test_regress/t/t_case_inside_call_count.py +++ b/test_regress/t/t_case_inside_call_count.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--stats']) diff --git a/test_regress/t/t_case_inside_with_x.py b/test_regress/t/t_case_inside_with_x.py index 46d1fe4c0..bd6ade23d 100755 --- a/test_regress/t/t_case_inside_with_x.py +++ b/test_regress/t/t_case_inside_with_x.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary']) diff --git a/test_regress/t/t_case_itemwidth.py b/test_regress/t/t_case_itemwidth.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_case_itemwidth.py +++ b/test_regress/t/t_case_itemwidth.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_case_nest.py b/test_regress/t/t_case_nest.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_case_nest.py +++ b/test_regress/t/t_case_nest.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_case_onehot.py b/test_regress/t/t_case_onehot.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_case_onehot.py +++ b/test_regress/t/t_case_onehot.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_case_orig.py b/test_regress/t/t_case_orig.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_case_orig.py +++ b/test_regress/t/t_case_orig.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_case_overlap_bad.py b/test_regress/t/t_case_overlap_bad.py index c7d9b21a5..692e6eeb1 100755 --- a/test_regress/t/t_case_overlap_bad.py +++ b/test_regress/t/t_case_overlap_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_case_priority_overlap.py b/test_regress/t/t_case_priority_overlap.py index 46d1fe4c0..bd6ade23d 100755 --- a/test_regress/t/t_case_priority_overlap.py +++ b/test_regress/t/t_case_priority_overlap.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary']) diff --git a/test_regress/t/t_case_reducer.py b/test_regress/t/t_case_reducer.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_case_reducer.py +++ b/test_regress/t/t_case_reducer.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_case_string.py b/test_regress/t/t_case_string.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_case_string.py +++ b/test_regress/t/t_case_string.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_case_table_normal.py b/test_regress/t/t_case_table_normal.py index 25746e901..99191987b 100755 --- a/test_regress/t/t_case_table_normal.py +++ b/test_regress/t/t_case_table_normal.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary', '--stats']) diff --git a/test_regress/t/t_case_table_normal_off.py b/test_regress/t/t_case_table_normal_off.py index 7497fbc92..d3d35119e 100755 --- a/test_regress/t/t_case_table_normal_off.py +++ b/test_regress/t/t_case_table_normal_off.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_case_table_normal.v" diff --git a/test_regress/t/t_case_table_tiny.py b/test_regress/t/t_case_table_tiny.py index 55d103058..8963e0ff5 100755 --- a/test_regress/t/t_case_table_tiny.py +++ b/test_regress/t/t_case_table_tiny.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary', '--stats']) diff --git a/test_regress/t/t_case_table_tiny_off.py b/test_regress/t/t_case_table_tiny_off.py index 8890dcd07..9f86d9591 100755 --- a/test_regress/t/t_case_table_tiny_off.py +++ b/test_regress/t/t_case_table_tiny_off.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_case_table_tiny.v" diff --git a/test_regress/t/t_case_unique_many.py b/test_regress/t/t_case_unique_many.py index d4a6141c1..bf5a9eb1d 100755 --- a/test_regress/t/t_case_unique_many.py +++ b/test_regress/t/t_case_unique_many.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--assert"]) diff --git a/test_regress/t/t_case_unique_overlap.py b/test_regress/t/t_case_unique_overlap.py index f3945fcdd..880f87d97 100755 --- a/test_regress/t/t_case_unique_overlap.py +++ b/test_regress/t/t_case_unique_overlap.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--stats']) diff --git a/test_regress/t/t_case_wild.py b/test_regress/t/t_case_wild.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_case_wild.py +++ b/test_regress/t/t_case_wild.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_case_write1.py b/test_regress/t/t_case_write1.py index 99c78dafa..a2a3ca5fd 100755 --- a/test_regress/t/t_case_write1.py +++ b/test_regress/t/t_case_write1.py @@ -11,6 +11,7 @@ import vltest_bootstrap test.priority(50) test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--stats -O3 -x-assign fast"]) diff --git a/test_regress/t/t_case_write1_noexpand.py b/test_regress/t/t_case_write1_noexpand.py index 1375ace89..388b28008 100755 --- a/test_regress/t/t_case_write1_noexpand.py +++ b/test_regress/t/t_case_write1_noexpand.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_case_write1.v" test.compile(verilator_flags2=['-fno-expand']) diff --git a/test_regress/t/t_case_write2.py b/test_regress/t/t_case_write2.py index 99c78dafa..a2a3ca5fd 100755 --- a/test_regress/t/t_case_write2.py +++ b/test_regress/t/t_case_write2.py @@ -11,6 +11,7 @@ import vltest_bootstrap test.priority(50) test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--stats -O3 -x-assign fast"]) diff --git a/test_regress/t/t_case_x.py b/test_regress/t/t_case_x.py index 793e4f0a3..9366fc26b 100755 --- a/test_regress/t/t_case_x.py +++ b/test_regress/t/t_case_x.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--x-assign 0"]) diff --git a/test_regress/t/t_case_x_bad.py b/test_regress/t/t_case_x_bad.py index c7d9b21a5..692e6eeb1 100755 --- a/test_regress/t/t_case_x_bad.py +++ b/test_regress/t/t_case_x_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_case_zx_bad.py b/test_regress/t/t_case_zx_bad.py index c7d9b21a5..692e6eeb1 100755 --- a/test_regress/t/t_case_zx_bad.py +++ b/test_regress/t/t_case_zx_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_cast.py b/test_regress/t/t_cast.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_cast.py +++ b/test_regress/t/t_cast.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_cast_param_logic.py b/test_regress/t/t_cast_param_logic.py index 67b896515..8a1a7b033 100755 --- a/test_regress/t/t_cast_param_logic.py +++ b/test_regress/t/t_cast_param_logic.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint() diff --git a/test_regress/t/t_cast_string.py b/test_regress/t/t_cast_string.py index 8a938befd..a10e2547d 100755 --- a/test_regress/t/t_cast_string.py +++ b/test_regress/t/t_cast_string.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_cast_types.py b/test_regress/t/t_cast_types.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_cast_types.py +++ b/test_regress/t/t_cast_types.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_castdyn.py b/test_regress/t/t_castdyn.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_castdyn.py +++ b/test_regress/t/t_castdyn.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_castdyn_castconst_bad.py b/test_regress/t/t_castdyn_castconst_bad.py index c7d9b21a5..692e6eeb1 100755 --- a/test_regress/t/t_castdyn_castconst_bad.py +++ b/test_regress/t/t_castdyn_castconst_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_castdyn_enum.py b/test_regress/t/t_castdyn_enum.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_castdyn_enum.py +++ b/test_regress/t/t_castdyn_enum.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_checker.py b/test_regress/t/t_checker.py index d4a6141c1..bf5a9eb1d 100755 --- a/test_regress/t/t_checker.py +++ b/test_regress/t/t_checker.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--assert"]) diff --git a/test_regress/t/t_checker_top.py b/test_regress/t/t_checker_top.py index fedddbcdd..16efd6c24 100755 --- a/test_regress/t/t_checker_top.py +++ b/test_regress/t/t_checker_top.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(verilator_flags2=["--assert"]) diff --git a/test_regress/t/t_class_class_extends.py b/test_regress/t/t_class_class_extends.py index 4ee7f9e14..64d4ecb78 100755 --- a/test_regress/t/t_class_class_extends.py +++ b/test_regress/t/t_class_class_extends.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary']) diff --git a/test_regress/t/t_class_default_type_param.py b/test_regress/t/t_class_default_type_param.py index 31b1f0e53..9da272f7d 100755 --- a/test_regress/t/t_class_default_type_param.py +++ b/test_regress/t/t_class_default_type_param.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_class_enum.py b/test_regress/t/t_class_enum.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_class_enum.py +++ b/test_regress/t/t_class_enum.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_class_link_delay2.py b/test_regress/t/t_class_link_delay2.py index 10ad7f0de..89d778552 100755 --- a/test_regress/t/t_class_link_delay2.py +++ b/test_regress/t/t_class_link_delay2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_class_member_shadow_type.py b/test_regress/t/t_class_member_shadow_type.py index 8a938befd..a10e2547d 100755 --- a/test_regress/t/t_class_member_shadow_type.py +++ b/test_regress/t/t_class_member_shadow_type.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_class_method_struct.py b/test_regress/t/t_class_method_struct.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_class_method_struct.py +++ b/test_regress/t/t_class_method_struct.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_class_null_struct.py b/test_regress/t/t_class_null_struct.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_class_null_struct.py +++ b/test_regress/t/t_class_null_struct.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_class_packed.py b/test_regress/t/t_class_packed.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_class_packed.py +++ b/test_regress/t/t_class_packed.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_class_param.py b/test_regress/t/t_class_param.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_class_param.py +++ b/test_regress/t/t_class_param.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_class_param_mailbox.py b/test_regress/t/t_class_param_mailbox.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_class_param_mailbox.py +++ b/test_regress/t/t_class_param_mailbox.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_class_param_nested_typedef.py b/test_regress/t/t_class_param_nested_typedef.py index c87a1e49f..ba29bf27d 100755 --- a/test_regress/t/t_class_param_nested_typedef.py +++ b/test_regress/t/t_class_param_nested_typedef.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_class_param_static.py b/test_regress/t/t_class_param_static.py index 84b274f68..17424b42f 100755 --- a/test_regress/t/t_class_param_static.py +++ b/test_regress/t/t_class_param_static.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_class_param_typedef5.py b/test_regress/t/t_class_param_typedef5.py index 7ded63f3a..d210ebd50 100755 --- a/test_regress/t/t_class_param_typedef5.py +++ b/test_regress/t/t_class_param_typedef5.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_class_param_typedef8.py b/test_regress/t/t_class_param_typedef8.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_class_param_typedef8.py +++ b/test_regress/t/t_class_param_typedef8.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_class_static_after_cg.py b/test_regress/t/t_class_static_after_cg.py index 26440f70f..001f9d311 100755 --- a/test_regress/t/t_class_static_after_cg.py +++ b/test_regress/t/t_class_static_after_cg.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.lint() diff --git a/test_regress/t/t_class_static_default_arg.py b/test_regress/t/t_class_static_default_arg.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_class_static_default_arg.py +++ b/test_regress/t/t_class_static_default_arg.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_class_trigger_null.py b/test_regress/t/t_class_trigger_null.py index 4ee7f9e14..64d4ecb78 100755 --- a/test_regress/t/t_class_trigger_null.py +++ b/test_regress/t/t_class_trigger_null.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary']) diff --git a/test_regress/t/t_class_typedef.py b/test_regress/t/t_class_typedef.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_class_typedef.py +++ b/test_regress/t/t_class_typedef.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_class_uses_this.py b/test_regress/t/t_class_uses_this.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_class_uses_this.py +++ b/test_regress/t/t_class_uses_this.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_clk_concat.py b/test_regress/t/t_clk_concat.py index fb2c945b4..d21e18d15 100755 --- a/test_regress/t/t_clk_concat.py +++ b/test_regress/t/t_clk_concat.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False out_filename = test.obj_dir + "/V" + test.name + ".tree.json" diff --git a/test_regress/t/t_clk_concat2.py b/test_regress/t/t_clk_concat2.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_clk_concat2.py +++ b/test_regress/t/t_clk_concat2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_clk_concat3.py b/test_regress/t/t_clk_concat3.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_clk_concat3.py +++ b/test_regress/t/t_clk_concat3.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_clk_concat4.py b/test_regress/t/t_clk_concat4.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_clk_concat4.py +++ b/test_regress/t/t_clk_concat4.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_clk_concat5.py b/test_regress/t/t_clk_concat5.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_clk_concat5.py +++ b/test_regress/t/t_clk_concat5.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_clk_concat6.py b/test_regress/t/t_clk_concat6.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_clk_concat6.py +++ b/test_regress/t/t_clk_concat6.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_clk_concat_vlt.py b/test_regress/t/t_clk_concat_vlt.py index a9dcc2716..fc021ec0e 100755 --- a/test_regress/t/t_clk_concat_vlt.py +++ b/test_regress/t/t_clk_concat_vlt.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_clk_concat.v" out_filename = test.obj_dir + "/V" + test.name + ".tree.json" diff --git a/test_regress/t/t_clk_condflop.py b/test_regress/t/t_clk_condflop.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_clk_condflop.py +++ b/test_regress/t/t_clk_condflop.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_clk_dsp.py b/test_regress/t/t_clk_dsp.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_clk_dsp.py +++ b/test_regress/t/t_clk_dsp.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_clk_inp_init.py b/test_regress/t/t_clk_inp_init.py index e561a74aa..ae80da618 100755 --- a/test_regress/t/t_clk_inp_init.py +++ b/test_regress/t/t_clk_inp_init.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.compile(make_main=False, verilator_flags2=["--exe", test.pli_filename]) diff --git a/test_regress/t/t_clk_latch.py b/test_regress/t/t_clk_latch.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_clk_latch.py +++ b/test_regress/t/t_clk_latch.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_clk_latch_edgestyle.py b/test_regress/t/t_clk_latch_edgestyle.py index 886d943e2..b77f9d0dd 100755 --- a/test_regress/t/t_clk_latch_edgestyle.py +++ b/test_regress/t/t_clk_latch_edgestyle.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_clk_latch.v" test.compile(v_flags2=['+define+EDGE_DETECT_STYLE']) diff --git a/test_regress/t/t_clk_latchgate.py b/test_regress/t/t_clk_latchgate.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_clk_latchgate.py +++ b/test_regress/t/t_clk_latchgate.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_clk_powerdn.py b/test_regress/t/t_clk_powerdn.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_clk_powerdn.py +++ b/test_regress/t/t_clk_powerdn.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_clk_scope_bad.py b/test_regress/t/t_clk_scope_bad.py index 67b896515..8a1a7b033 100755 --- a/test_regress/t/t_clk_scope_bad.py +++ b/test_regress/t/t_clk_scope_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint() diff --git a/test_regress/t/t_clk_vecgen1.py b/test_regress/t/t_clk_vecgen1.py index b341eb3c4..a65805982 100755 --- a/test_regress/t/t_clk_vecgen1.py +++ b/test_regress/t/t_clk_vecgen1.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_clk_vecgen1.v" test.compile(v_flags2=['+define+T_TEST1']) diff --git a/test_regress/t/t_clk_vecgen2.py b/test_regress/t/t_clk_vecgen2.py index 75eed1071..0c0e3fbdd 100755 --- a/test_regress/t/t_clk_vecgen2.py +++ b/test_regress/t/t_clk_vecgen2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_clk_vecgen1.v" test.compile(v_flags2=['+define+T_TEST2']) diff --git a/test_regress/t/t_clk_vecgen3.py b/test_regress/t/t_clk_vecgen3.py index c3f505618..6bff51320 100755 --- a/test_regress/t/t_clk_vecgen3.py +++ b/test_regress/t/t_clk_vecgen3.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_clk_vecgen1.v" test.compile(v_flags2=['+define+T_TEST3']) diff --git a/test_regress/t/t_clocked_release_combo.py b/test_regress/t/t_clocked_release_combo.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_clocked_release_combo.py +++ b/test_regress/t/t_clocked_release_combo.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_clocking_bad4.py b/test_regress/t/t_clocking_bad4.py index c7d9b21a5..692e6eeb1 100755 --- a/test_regress/t/t_clocking_bad4.py +++ b/test_regress/t/t_clocking_bad4.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_clocking_concat.py b/test_regress/t/t_clocking_concat.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_clocking_concat.py +++ b/test_regress/t/t_clocking_concat.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_clocking_empty_block.py b/test_regress/t/t_clocking_empty_block.py index 7ded63f3a..d210ebd50 100755 --- a/test_regress/t/t_clocking_empty_block.py +++ b/test_regress/t/t_clocking_empty_block.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_clocking_inout.py b/test_regress/t/t_clocking_inout.py index bb3cf3bf1..ad429a977 100755 --- a/test_regress/t/t_clocking_inout.py +++ b/test_regress/t/t_clocking_inout.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"], make_main=False) diff --git a/test_regress/t/t_clocking_input_default.py b/test_regress/t/t_clocking_input_default.py index f498514dd..1f50802e3 100755 --- a/test_regress/t/t_clocking_input_default.py +++ b/test_regress/t/t_clocking_input_default.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"], make_main=False) diff --git a/test_regress/t/t_clocking_out_on_change.py b/test_regress/t/t_clocking_out_on_change.py index 7ded63f3a..d210ebd50 100755 --- a/test_regress/t/t_clocking_out_on_change.py +++ b/test_regress/t/t_clocking_out_on_change.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_clocking_react.py b/test_regress/t/t_clocking_react.py index 7ded63f3a..d210ebd50 100755 --- a/test_regress/t/t_clocking_react.py +++ b/test_regress/t/t_clocking_react.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_clocking_sampled_unpacked.py b/test_regress/t/t_clocking_sampled_unpacked.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_clocking_sampled_unpacked.py +++ b/test_regress/t/t_clocking_sampled_unpacked.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_clocking_sched.py b/test_regress/t/t_clocking_sched.py index c03eaf086..40b9c248c 100755 --- a/test_regress/t/t_clocking_sched.py +++ b/test_regress/t/t_clocking_sched.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_clocking_sched_timing.py b/test_regress/t/t_clocking_sched_timing.py index 81c152f91..821e33607 100755 --- a/test_regress/t/t_clocking_sched_timing.py +++ b/test_regress/t/t_clocking_sched_timing.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_clocking_sched.v" test.compile(timing_loop=True, verilator_flags2=["--timing"]) diff --git a/test_regress/t/t_clocking_sched_timing_forkproc.py b/test_regress/t/t_clocking_sched_timing_forkproc.py index eef7522eb..babf10902 100755 --- a/test_regress/t/t_clocking_sched_timing_forkproc.py +++ b/test_regress/t/t_clocking_sched_timing_forkproc.py @@ -9,6 +9,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_clocking_sched.v" test.compile(timing_loop=True, verilator_flags2=["--timing"]) diff --git a/test_regress/t/t_clocking_timing1.py b/test_regress/t/t_clocking_timing1.py index 449fd97df..0e3acc961 100755 --- a/test_regress/t/t_clocking_timing1.py +++ b/test_regress/t/t_clocking_timing1.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_clocking_timing.v" test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_clocking_timing2.py b/test_regress/t/t_clocking_timing2.py index 64fbfad5e..47679f0fb 100755 --- a/test_regress/t/t_clocking_timing2.py +++ b/test_regress/t/t_clocking_timing2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_clocking_timing.v" test.compile(verilator_flags2=["--binary -DTEST_INPUT_SKEW=12 -DTEST_OUTPUT_SKEW=16"]) diff --git a/test_regress/t/t_clocking_unsup2.py b/test_regress/t/t_clocking_unsup2.py index 67b896515..8a1a7b033 100755 --- a/test_regress/t/t_clocking_unsup2.py +++ b/test_regress/t/t_clocking_unsup2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint() diff --git a/test_regress/t/t_clocking_virtual.py b/test_regress/t/t_clocking_virtual.py index 7ded63f3a..d210ebd50 100755 --- a/test_regress/t/t_clocking_virtual.py +++ b/test_regress/t/t_clocking_virtual.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_clocking_zero_delay.py b/test_regress/t/t_clocking_zero_delay.py index f2d7f08fa..5790553c6 100755 --- a/test_regress/t/t_clocking_zero_delay.py +++ b/test_regress/t/t_clocking_zero_delay.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary', '--timing']) diff --git a/test_regress/t/t_comb_do_not_convert_to.py b/test_regress/t/t_comb_do_not_convert_to.py index b3e1bba47..148554386 100755 --- a/test_regress/t/t_comb_do_not_convert_to.py +++ b/test_regress/t/t_comb_do_not_convert_to.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.compile(verilator_flags2=["--stats"]) diff --git a/test_regress/t/t_comb_loop_through_unpacked_array.py b/test_regress/t/t_comb_loop_through_unpacked_array.py index 9ecd0205a..4b4d999e5 100755 --- a/test_regress/t/t_comb_loop_through_unpacked_array.py +++ b/test_regress/t/t_comb_loop_through_unpacked_array.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.compile(verilator_flags2=["-Wno-UNOPTFLAT", "-fno-dfg"]) diff --git a/test_regress/t/t_concat_casts.py b/test_regress/t/t_concat_casts.py index 903201f15..03b00189e 100755 --- a/test_regress/t/t_concat_casts.py +++ b/test_regress/t/t_concat_casts.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios("simulator") +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_concat_unpack.py b/test_regress/t/t_concat_unpack.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_concat_unpack.py +++ b/test_regress/t/t_concat_unpack.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_const_bitoptree_bug3096.py b/test_regress/t/t_const_bitoptree_bug3096.py index ab913e2a1..6196bad31 100755 --- a/test_regress/t/t_const_bitoptree_bug3096.py +++ b/test_regress/t/t_const_bitoptree_bug3096.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.compile(make_top_shell=False, make_main=False, v_flags2=["--exe", test.pli_filename]) diff --git a/test_regress/t/t_const_sel_sel_extend.py b/test_regress/t/t_const_sel_sel_extend.py index 46f459325..5ac68e5d3 100755 --- a/test_regress/t/t_const_sel_sel_extend.py +++ b/test_regress/t/t_const_sel_sel_extend.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_constraint_array_index.py b/test_regress/t/t_constraint_array_index.py index ab048b5e8..0521af235 100755 --- a/test_regress/t/t_constraint_array_index.py +++ b/test_regress/t/t_constraint_array_index.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_constraint_array_index_simple.py b/test_regress/t/t_constraint_array_index_simple.py index db1adb3f9..b19f4bf03 100755 --- a/test_regress/t/t_constraint_array_index_simple.py +++ b/test_regress/t/t_constraint_array_index_simple.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_constraint_array_limit.py b/test_regress/t/t_constraint_array_limit.py index fac064bd4..7f9e188d5 100755 --- a/test_regress/t/t_constraint_array_limit.py +++ b/test_regress/t/t_constraint_array_limit.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_constraint_array_reduction_inherit.py b/test_regress/t/t_constraint_array_reduction_inherit.py index db1adb3f9..b19f4bf03 100755 --- a/test_regress/t/t_constraint_array_reduction_inherit.py +++ b/test_regress/t/t_constraint_array_reduction_inherit.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_constraint_array_sum_with.py b/test_regress/t/t_constraint_array_sum_with.py index db1adb3f9..b19f4bf03 100755 --- a/test_regress/t/t_constraint_array_sum_with.py +++ b/test_regress/t/t_constraint_array_sum_with.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_constraint_assoc_arr_bad.py b/test_regress/t/t_constraint_assoc_arr_bad.py index c7d9b21a5..692e6eeb1 100755 --- a/test_regress/t/t_constraint_assoc_arr_bad.py +++ b/test_regress/t/t_constraint_assoc_arr_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_constraint_assoc_arr_basic.py b/test_regress/t/t_constraint_assoc_arr_basic.py index ab048b5e8..0521af235 100755 --- a/test_regress/t/t_constraint_assoc_arr_basic.py +++ b/test_regress/t/t_constraint_assoc_arr_basic.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_constraint_assoc_arr_others.py b/test_regress/t/t_constraint_assoc_arr_others.py index ab048b5e8..0521af235 100755 --- a/test_regress/t/t_constraint_assoc_arr_others.py +++ b/test_regress/t/t_constraint_assoc_arr_others.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_constraint_cls_arr_member.py b/test_regress/t/t_constraint_cls_arr_member.py index db1adb3f9..b19f4bf03 100755 --- a/test_regress/t/t_constraint_cls_arr_member.py +++ b/test_regress/t/t_constraint_cls_arr_member.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_constraint_countbits_unsup.py b/test_regress/t/t_constraint_countbits_unsup.py index b7449248c..5f4a1b488 100755 --- a/test_regress/t/t_constraint_countbits_unsup.py +++ b/test_regress/t/t_constraint_countbits_unsup.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_constraint_dist.py b/test_regress/t/t_constraint_dist.py index 87b346af1..4524e278f 100755 --- a/test_regress/t/t_constraint_dist.py +++ b/test_regress/t/t_constraint_dist.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_constraint_dist_weight.py b/test_regress/t/t_constraint_dist_weight.py index db1adb3f9..b19f4bf03 100755 --- a/test_regress/t/t_constraint_dist_weight.py +++ b/test_regress/t/t_constraint_dist_weight.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_constraint_dyn_array_reduction.py b/test_regress/t/t_constraint_dyn_array_reduction.py index db1adb3f9..b19f4bf03 100755 --- a/test_regress/t/t_constraint_dyn_array_reduction.py +++ b/test_regress/t/t_constraint_dyn_array_reduction.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_constraint_dyn_queue_basic.py b/test_regress/t/t_constraint_dyn_queue_basic.py index ab048b5e8..0521af235 100755 --- a/test_regress/t/t_constraint_dyn_queue_basic.py +++ b/test_regress/t/t_constraint_dyn_queue_basic.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_constraint_dyn_size_inline.py b/test_regress/t/t_constraint_dyn_size_inline.py index db1adb3f9..b19f4bf03 100755 --- a/test_regress/t/t_constraint_dyn_size_inline.py +++ b/test_regress/t/t_constraint_dyn_size_inline.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_constraint_foreach.py b/test_regress/t/t_constraint_foreach.py index ab048b5e8..0521af235 100755 --- a/test_regress/t/t_constraint_foreach.py +++ b/test_regress/t/t_constraint_foreach.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_constraint_foreach_classref.py b/test_regress/t/t_constraint_foreach_classref.py index db1adb3f9..b19f4bf03 100755 --- a/test_regress/t/t_constraint_foreach_classref.py +++ b/test_regress/t/t_constraint_foreach_classref.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_constraint_func_call_unsup.py b/test_regress/t/t_constraint_func_call_unsup.py index 18ef27714..d1c8fa5b1 100755 --- a/test_regress/t/t_constraint_func_call_unsup.py +++ b/test_regress/t/t_constraint_func_call_unsup.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_constraint_global_arr_unsup.py b/test_regress/t/t_constraint_global_arr_unsup.py index 4cebd5d8e..e6bb34c89 100755 --- a/test_regress/t/t_constraint_global_arr_unsup.py +++ b/test_regress/t/t_constraint_global_arr_unsup.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_constraint_global_cls_arr.py b/test_regress/t/t_constraint_global_cls_arr.py index 8862c2c31..50fdc5f6d 100755 --- a/test_regress/t/t_constraint_global_cls_arr.py +++ b/test_regress/t/t_constraint_global_cls_arr.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_constraint_global_cls_arr_2d_unsup.py b/test_regress/t/t_constraint_global_cls_arr_2d_unsup.py index 4cebd5d8e..e6bb34c89 100755 --- a/test_regress/t/t_constraint_global_cls_arr_2d_unsup.py +++ b/test_regress/t/t_constraint_global_cls_arr_2d_unsup.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_constraint_global_nested_member.py b/test_regress/t/t_constraint_global_nested_member.py index 8862c2c31..50fdc5f6d 100755 --- a/test_regress/t/t_constraint_global_nested_member.py +++ b/test_regress/t/t_constraint_global_nested_member.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_constraint_global_nested_randmode.py b/test_regress/t/t_constraint_global_nested_randmode.py index db1adb3f9..b19f4bf03 100755 --- a/test_regress/t/t_constraint_global_nested_randmode.py +++ b/test_regress/t/t_constraint_global_nested_randmode.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_constraint_global_randMode.py b/test_regress/t/t_constraint_global_randMode.py index 8862c2c31..50fdc5f6d 100755 --- a/test_regress/t/t_constraint_global_randMode.py +++ b/test_regress/t/t_constraint_global_randMode.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_constraint_global_randmode_subobj.py b/test_regress/t/t_constraint_global_randmode_subobj.py index db1adb3f9..b19f4bf03 100755 --- a/test_regress/t/t_constraint_global_randmode_subobj.py +++ b/test_regress/t/t_constraint_global_randmode_subobj.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_constraint_global_random_simple.py b/test_regress/t/t_constraint_global_random_simple.py index 8862c2c31..50fdc5f6d 100755 --- a/test_regress/t/t_constraint_global_random_simple.py +++ b/test_regress/t/t_constraint_global_random_simple.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_constraint_global_subobj.py b/test_regress/t/t_constraint_global_subobj.py index db1adb3f9..b19f4bf03 100755 --- a/test_regress/t/t_constraint_global_subobj.py +++ b/test_regress/t/t_constraint_global_subobj.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_constraint_implication_set.py b/test_regress/t/t_constraint_implication_set.py index db1adb3f9..b19f4bf03 100755 --- a/test_regress/t/t_constraint_implication_set.py +++ b/test_regress/t/t_constraint_implication_set.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_constraint_inheritance_with.py b/test_regress/t/t_constraint_inheritance_with.py index ab048b5e8..0521af235 100755 --- a/test_regress/t/t_constraint_inheritance_with.py +++ b/test_regress/t/t_constraint_inheritance_with.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_constraint_inside_typedef_array.py b/test_regress/t/t_constraint_inside_typedef_array.py index db1adb3f9..b19f4bf03 100755 --- a/test_regress/t/t_constraint_inside_typedef_array.py +++ b/test_regress/t/t_constraint_inside_typedef_array.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_constraint_json_only.out b/test_regress/t/t_constraint_json_only.out index c18d8a989..323a32f19 100644 --- a/test_regress/t/t_constraint_json_only.out +++ b/test_regress/t/t_constraint_json_only.out @@ -2,7 +2,7 @@ "modulesp": [ {"type":"MODULE","name":"t","addr":"(F)","loc":"d,67:8,67:9","origName":"t","verilogName":"t","level":1,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"p","addr":"(G)","loc":"d,69:10,69:11","dtypep":"(H)","origName":"p","verilogName":"p","direction":"NONE","lifetime":"VSTATICI","varType":"VAR","dtypeName":"Packet","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"p","addr":"(G)","loc":"d,69:10,69:11","dtypep":"(H)","origName":"p","verilogName":"p","direction":"NONE","lifetime":"VSTATICI","varType":"VAR","dtypeName":"Packet","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"INITIAL","name":"","addr":"(I)","loc":"d,71:3,71:10", "stmtsp": [ {"type":"BEGIN","name":"","addr":"(J)","loc":"d,71:11,71:16","unnamed":true,"declsp": [], @@ -19,21 +19,21 @@ "stmtsp": [ {"type":"CLASS","name":"Packet","addr":"(O)","loc":"d,7:1,7:6","origName":"Packet","verilogName":"Packet","level":3,"timeunit":"1ps","classOrPackagep":"UNLINKED","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"header","addr":"(P)","loc":"d,8:12,8:18","dtypep":"(Q)","origName":"header","verilogName":"header","direction":"NONE","lifetime":"VAUTOMI","varType":"MEMBER","dtypeName":"int","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"length","addr":"(R)","loc":"d,9:12,9:18","dtypep":"(Q)","origName":"length","verilogName":"length","direction":"NONE","lifetime":"VAUTOMI","varType":"MEMBER","dtypeName":"int","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"sublength","addr":"(S)","loc":"d,10:12,10:21","dtypep":"(Q)","origName":"sublength","verilogName":"sublength","direction":"NONE","lifetime":"VAUTOMI","varType":"MEMBER","dtypeName":"int","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"if_4","addr":"(T)","loc":"d,11:12,11:16","dtypep":"(U)","origName":"if_4","verilogName":"if_4","direction":"NONE","lifetime":"VAUTOMI","varType":"MEMBER","dtypeName":"bit","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"iff_5_6","addr":"(V)","loc":"d,12:12,12:19","dtypep":"(U)","origName":"iff_5_6","verilogName":"iff_5_6","direction":"NONE","lifetime":"VAUTOMI","varType":"MEMBER","dtypeName":"bit","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"if_state_ok","addr":"(W)","loc":"d,13:12,13:23","dtypep":"(U)","origName":"if_state_ok","verilogName":"if_state_ok","direction":"NONE","lifetime":"VAUTOMI","varType":"MEMBER","dtypeName":"bit","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"array","addr":"(X)","loc":"d,15:12,15:17","dtypep":"(Y)","origName":"array","verilogName":"array","direction":"NONE","lifetime":"VAUTOMI","varType":"MEMBER","dtypeName":"","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"state","addr":"(Z)","loc":"d,17:10,17:15","dtypep":"(M)","origName":"state","verilogName":"state","direction":"NONE","lifetime":"VAUTOMI","varType":"MEMBER","dtypeName":"string","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"header","addr":"(P)","loc":"d,8:12,8:18","dtypep":"(Q)","origName":"header","verilogName":"header","direction":"NONE","lifetime":"VAUTOMI","varType":"MEMBER","dtypeName":"int","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"length","addr":"(R)","loc":"d,9:12,9:18","dtypep":"(Q)","origName":"length","verilogName":"length","direction":"NONE","lifetime":"VAUTOMI","varType":"MEMBER","dtypeName":"int","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"sublength","addr":"(S)","loc":"d,10:12,10:21","dtypep":"(Q)","origName":"sublength","verilogName":"sublength","direction":"NONE","lifetime":"VAUTOMI","varType":"MEMBER","dtypeName":"int","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"if_4","addr":"(T)","loc":"d,11:12,11:16","dtypep":"(U)","origName":"if_4","verilogName":"if_4","direction":"NONE","lifetime":"VAUTOMI","varType":"MEMBER","dtypeName":"bit","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"iff_5_6","addr":"(V)","loc":"d,12:12,12:19","dtypep":"(U)","origName":"iff_5_6","verilogName":"iff_5_6","direction":"NONE","lifetime":"VAUTOMI","varType":"MEMBER","dtypeName":"bit","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"if_state_ok","addr":"(W)","loc":"d,13:12,13:23","dtypep":"(U)","origName":"if_state_ok","verilogName":"if_state_ok","direction":"NONE","lifetime":"VAUTOMI","varType":"MEMBER","dtypeName":"bit","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"array","addr":"(X)","loc":"d,15:12,15:17","dtypep":"(Y)","origName":"array","verilogName":"array","direction":"NONE","lifetime":"VAUTOMI","varType":"MEMBER","dtypeName":"","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"state","addr":"(Z)","loc":"d,17:10,17:15","dtypep":"(M)","origName":"state","verilogName":"state","direction":"NONE","lifetime":"VAUTOMI","varType":"MEMBER","dtypeName":"string","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"FUNC","name":"strings_equal","addr":"(AB)","loc":"d,61:16,61:29","dtypep":"(U)","method":true,"cname":"strings_equal", "fvarp": [ - {"type":"VAR","name":"strings_equal","addr":"(BB)","loc":"d,61:16,61:29","dtypep":"(U)","origName":"strings_equal","verilogName":"strings_equal","direction":"OUTPUT","noCReset":true,"icoMaybeWritten":true,"isFuncReturn":true,"isFuncLocal":true,"lifetime":"VAUTOM","varType":"VAR","dtypeName":"bit","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} + {"type":"VAR","name":"strings_equal","addr":"(BB)","loc":"d,61:16,61:29","dtypep":"(U)","origName":"strings_equal","verilogName":"strings_equal","direction":"OUTPUT","noCReset":true,"icoMaybeWritten":true,"isFuncReturn":true,"isFuncLocal":true,"lifetime":"VAUTOM","varType":"VAR","dtypeName":"bit","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ],"classOrPackagep": [], "stmtsp": [ - {"type":"VAR","name":"a","addr":"(CB)","loc":"d,61:37,61:38","dtypep":"(M)","origName":"a","verilogName":"a","direction":"INPUT","isFuncLocal":true,"lifetime":"VAUTOMI","varType":"PORT","dtypeName":"string","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"b","addr":"(DB)","loc":"d,61:47,61:48","dtypep":"(M)","origName":"b","verilogName":"b","direction":"INPUT","isFuncLocal":true,"lifetime":"VAUTOMI","varType":"PORT","dtypeName":"string","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"a","addr":"(CB)","loc":"d,61:37,61:38","dtypep":"(M)","origName":"a","verilogName":"a","direction":"INPUT","isFuncLocal":true,"lifetime":"VAUTOMI","varType":"PORT","dtypeName":"string","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"b","addr":"(DB)","loc":"d,61:47,61:48","dtypep":"(M)","origName":"b","verilogName":"b","direction":"INPUT","isFuncLocal":true,"lifetime":"VAUTOMI","varType":"PORT","dtypeName":"string","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"ASSIGN","name":"","addr":"(EB)","loc":"d,61:16,61:29","dtypep":"(U)", "rhsp": [ {"type":"CONST","name":"1'h0","addr":"(FB)","loc":"d,61:16,61:29","dtypep":"(U)"} @@ -56,7 +56,7 @@ ],"timingControlp": []} ],"scopeNamep": []}, {"type":"FUNC","name":"new","addr":"(MB)","loc":"d,7:1,7:6","dtypep":"(NB)","method":true,"cname":"new","fvarp": [],"classOrPackagep": [],"stmtsp": [],"scopeNamep": []}, - {"type":"VAR","name":"constraint","addr":"(OB)","loc":"d,7:1,7:6","dtypep":"(PB)","origName":"constraint","verilogName":"constraint","direction":"NONE","lifetime":"NONE","varType":"MEMBER","dtypeName":"VlRandomizer","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} + {"type":"VAR","name":"constraint","addr":"(OB)","loc":"d,7:1,7:6","dtypep":"(PB)","origName":"constraint","verilogName":"constraint","direction":"NONE","lifetime":"NONE","varType":"MEMBER","dtypeName":"VlRandomizer","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ],"extendsp": []} ]} ],"filesp": [], diff --git a/test_regress/t/t_constraint_mode.py b/test_regress/t/t_constraint_mode.py index ab048b5e8..0521af235 100755 --- a/test_regress/t/t_constraint_mode.py +++ b/test_regress/t/t_constraint_mode.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_constraint_mode_ctor.py b/test_regress/t/t_constraint_mode_ctor.py index db1adb3f9..b19f4bf03 100755 --- a/test_regress/t/t_constraint_mode_ctor.py +++ b/test_regress/t/t_constraint_mode_ctor.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_constraint_mode_static.py b/test_regress/t/t_constraint_mode_static.py index db1adb3f9..b19f4bf03 100755 --- a/test_regress/t/t_constraint_mode_static.py +++ b/test_regress/t/t_constraint_mode_static.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_constraint_non_base2_pow_unsup.py b/test_regress/t/t_constraint_non_base2_pow_unsup.py index 344a4e20a..a88bd50c8 100755 --- a/test_regress/t/t_constraint_non_base2_pow_unsup.py +++ b/test_regress/t/t_constraint_non_base2_pow_unsup.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_constraint_non_const_exp_pow_unsup.py b/test_regress/t/t_constraint_non_const_exp_pow_unsup.py index 3160d0589..763d0b4d6 100755 --- a/test_regress/t/t_constraint_non_const_exp_pow_unsup.py +++ b/test_regress/t/t_constraint_non_const_exp_pow_unsup.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_constraint_shift_width.py b/test_regress/t/t_constraint_shift_width.py index 0b0c140af..e5c306670 100755 --- a/test_regress/t/t_constraint_shift_width.py +++ b/test_regress/t/t_constraint_shift_width.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_constraint_struct.py b/test_regress/t/t_constraint_struct.py index ab048b5e8..0521af235 100755 --- a/test_regress/t/t_constraint_struct.py +++ b/test_regress/t/t_constraint_struct.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_constraint_struct_complex.py b/test_regress/t/t_constraint_struct_complex.py index 8862c2c31..50fdc5f6d 100755 --- a/test_regress/t/t_constraint_struct_complex.py +++ b/test_regress/t/t_constraint_struct_complex.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_constraint_sysfunc.py b/test_regress/t/t_constraint_sysfunc.py index db1adb3f9..b19f4bf03 100755 --- a/test_regress/t/t_constraint_sysfunc.py +++ b/test_regress/t/t_constraint_sysfunc.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_constraint_unq_arr_derived.py b/test_regress/t/t_constraint_unq_arr_derived.py index db1adb3f9..b19f4bf03 100755 --- a/test_regress/t/t_constraint_unq_arr_derived.py +++ b/test_regress/t/t_constraint_unq_arr_derived.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_constraint_unq_arr_derived_inline_unsup.py b/test_regress/t/t_constraint_unq_arr_derived_inline_unsup.py index 18ef27714..d1c8fa5b1 100755 --- a/test_regress/t/t_constraint_unq_arr_derived_inline_unsup.py +++ b/test_regress/t/t_constraint_unq_arr_derived_inline_unsup.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_constraint_unsup.py b/test_regress/t/t_constraint_unsup.py index b7449248c..5f4a1b488 100755 --- a/test_regress/t/t_constraint_unsup.py +++ b/test_regress/t/t_constraint_unsup.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_constraint_unsup_unq_arr.py b/test_regress/t/t_constraint_unsup_unq_arr.py index b7449248c..5f4a1b488 100755 --- a/test_regress/t/t_constraint_unsup_unq_arr.py +++ b/test_regress/t/t_constraint_unsup_unq_arr.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_coroutine_lambda.py b/test_regress/t/t_coroutine_lambda.py index a4be4c39b..66f41be97 100755 --- a/test_regress/t/t_coroutine_lambda.py +++ b/test_regress/t/t_coroutine_lambda.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=[ "--binary", diff --git a/test_regress/t/t_cover_assert.py b/test_regress/t/t_cover_assert.py index 167d3f0b5..4fd8b5a7d 100755 --- a/test_regress/t/t_cover_assert.py +++ b/test_regress/t/t_cover_assert.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(verilator_flags2=["-Wall -Wno-DECLFILENAME --coverage"]) diff --git a/test_regress/t/t_cover_expr.py b/test_regress/t/t_cover_expr.py index 413e34601..d000b2c3f 100755 --- a/test_regress/t/t_cover_expr.py +++ b/test_regress/t/t_cover_expr.py @@ -11,6 +11,7 @@ import vltest_bootstrap from pathlib import Path test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--cc', '--coverage-expr']) diff --git a/test_regress/t/t_cover_expr_fork.py b/test_regress/t/t_cover_expr_fork.py index 57b6e30b1..377d5be43 100755 --- a/test_regress/t/t_cover_expr_fork.py +++ b/test_regress/t/t_cover_expr_fork.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--coverage-expr --binary']) diff --git a/test_regress/t/t_cover_expr_max.py b/test_regress/t/t_cover_expr_max.py index 9647dcec2..dde1c750e 100755 --- a/test_regress/t/t_cover_expr_max.py +++ b/test_regress/t/t_cover_expr_max.py @@ -11,6 +11,7 @@ import vltest_bootstrap from pathlib import Path test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_cover_expr.v" test.compile(verilator_flags2=['--cc', '--coverage-expr', '--coverage-expr-max', '128']) diff --git a/test_regress/t/t_cover_expr_queue_class.py b/test_regress/t/t_cover_expr_queue_class.py index ef0f2bae6..887562b46 100755 --- a/test_regress/t/t_cover_expr_queue_class.py +++ b/test_regress/t/t_cover_expr_queue_class.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--coverage-expr']) diff --git a/test_regress/t/t_cover_expr_trace.py b/test_regress/t/t_cover_expr_trace.py index a2177bd02..8deb58338 100755 --- a/test_regress/t/t_cover_expr_trace.py +++ b/test_regress/t/t_cover_expr_trace.py @@ -11,6 +11,7 @@ import vltest_bootstrap from pathlib import Path test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_cover_expr.v" test.compile(verilator_flags2=['--cc', '--coverage-expr', '--trace-vcd']) diff --git a/test_regress/t/t_cover_fsm_basic.py b/test_regress/t/t_cover_fsm_basic.py index 628914b4f..b0410eb23 100755 --- a/test_regress/t/t_cover_fsm_basic.py +++ b/test_regress/t/t_cover_fsm_basic.py @@ -12,6 +12,7 @@ import os import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--cc --coverage-fsm']) diff --git a/test_regress/t/t_cover_fsm_beginif.py b/test_regress/t/t_cover_fsm_beginif.py index 46a0e0d22..d266d6b7b 100755 --- a/test_regress/t/t_cover_fsm_beginif.py +++ b/test_regress/t/t_cover_fsm_beginif.py @@ -12,6 +12,7 @@ import os import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--cc --coverage-fsm']) test.execute() diff --git a/test_regress/t/t_cover_fsm_case_next_ok_multi.py b/test_regress/t/t_cover_fsm_case_next_ok_multi.py index a95c8efad..d2c95bdd1 100755 --- a/test_regress/t/t_cover_fsm_case_next_ok_multi.py +++ b/test_regress/t/t_cover_fsm_case_next_ok_multi.py @@ -12,6 +12,7 @@ import os import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--cc --coverage-fsm']) diff --git a/test_regress/t/t_cover_fsm_combo_same_warn_bad.py b/test_regress/t/t_cover_fsm_combo_same_warn_bad.py index 46cc6db99..2f7de05e9 100755 --- a/test_regress/t/t_cover_fsm_combo_same_warn_bad.py +++ b/test_regress/t/t_cover_fsm_combo_same_warn_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False # Two supported case statements in the same combinational always block for the # same FSM are legal RTL, but Phase 1 only instruments the first and warns on diff --git a/test_regress/t/t_cover_fsm_concat_unsup.py b/test_regress/t/t_cover_fsm_concat_unsup.py index 4a63bc600..5eb108e86 100755 --- a/test_regress/t/t_cover_fsm_concat_unsup.py +++ b/test_regress/t/t_cover_fsm_concat_unsup.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename, verilator_flags2=['--coverage']) diff --git a/test_regress/t/t_cover_fsm_decldump.py b/test_regress/t/t_cover_fsm_decldump.py index 66c75caa2..bf60e4185 100755 --- a/test_regress/t/t_cover_fsm_decldump.py +++ b/test_regress/t/t_cover_fsm_decldump.py @@ -12,6 +12,7 @@ from pathlib import Path import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_cover_fsm_policy_accept_multi.v" # Dump the lowered AST so AstCoverOtherDecl::dump() sees FSM metadata-bearing diff --git a/test_regress/t/t_cover_fsm_flag_off.py b/test_regress/t/t_cover_fsm_flag_off.py index e3fdca440..3f1582099 100755 --- a/test_regress/t/t_cover_fsm_flag_off.py +++ b/test_regress/t/t_cover_fsm_flag_off.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--cc --coverage-line']) diff --git a/test_regress/t/t_cover_fsm_graphdump.py b/test_regress/t/t_cover_fsm_graphdump.py index 9742f2aaf..13939d998 100755 --- a/test_regress/t/t_cover_fsm_graphdump.py +++ b/test_regress/t/t_cover_fsm_graphdump.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vltmt') +test.fourstate_capable = False test.top_filename = "t/t_cover_fsm_policy_accept_multi.v" test.compile(v_flags2=["--coverage-fsm", "--dumpi-graph", "6"], threads=2) diff --git a/test_regress/t/t_cover_fsm_if_unknown_enum_multi_bad.py b/test_regress/t/t_cover_fsm_if_unknown_enum_multi_bad.py index 936ca5648..56681667d 100755 --- a/test_regress/t/t_cover_fsm_if_unknown_enum_multi_bad.py +++ b/test_regress/t/t_cover_fsm_if_unknown_enum_multi_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(verilator_flags2=["--coverage-fsm"], fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_cover_fsm_negative_extract.py b/test_regress/t/t_cover_fsm_negative_extract.py index de42b16de..e5dc9135e 100755 --- a/test_regress/t/t_cover_fsm_negative_extract.py +++ b/test_regress/t/t_cover_fsm_negative_extract.py @@ -12,6 +12,7 @@ import os import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False # This test is intentionally "half supported": one case item is a simple # direct state assignment, while the others use shapes the extractor should diff --git a/test_regress/t/t_cover_fsm_nextstate_overwrite_warn.py b/test_regress/t/t_cover_fsm_nextstate_overwrite_warn.py index 40fb48177..ddb3f5312 100755 --- a/test_regress/t/t_cover_fsm_nextstate_overwrite_warn.py +++ b/test_regress/t/t_cover_fsm_nextstate_overwrite_warn.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False # A canonical `state_d = state_q` default followed by another top-level write # to `state_d` before `case (state_d)` is legal RTL, but it is not the narrow diff --git a/test_regress/t/t_cover_fsm_nonenum_literal.py b/test_regress/t/t_cover_fsm_nonenum_literal.py index 17eea3dc9..23865aee6 100755 --- a/test_regress/t/t_cover_fsm_nonenum_literal.py +++ b/test_regress/t/t_cover_fsm_nonenum_literal.py @@ -12,6 +12,7 @@ from pathlib import Path import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(v_flags=["--coverage-fsm", "--dump-tree"]) diff --git a/test_regress/t/t_cover_fsm_nonenum_unsupported_bad.py b/test_regress/t/t_cover_fsm_nonenum_unsupported_bad.py index 25a99f0c5..61a439c44 100755 --- a/test_regress/t/t_cover_fsm_nonenum_unsupported_bad.py +++ b/test_regress/t/t_cover_fsm_nonenum_unsupported_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(verilator_flags2=["--coverage-fsm"], fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_cover_fsm_noreset.py b/test_regress/t/t_cover_fsm_noreset.py index 2f70ddb14..1b148500d 100755 --- a/test_regress/t/t_cover_fsm_noreset.py +++ b/test_regress/t/t_cover_fsm_noreset.py @@ -12,6 +12,7 @@ import os import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False # This test deliberately uses a clocked FSM with no outer reset branch. It # keeps coverage extraction in the supported subset, but forces lowering down diff --git a/test_regress/t/t_cover_fsm_plain_always_ignore_multi.py b/test_regress/t/t_cover_fsm_plain_always_ignore_multi.py index 1b2d7e17a..f4d11fe47 100755 --- a/test_regress/t/t_cover_fsm_plain_always_ignore_multi.py +++ b/test_regress/t/t_cover_fsm_plain_always_ignore_multi.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--cc --coverage-fsm', '-Werror-COVERIGN']) diff --git a/test_regress/t/t_cover_fsm_plain_always_warn_multi_bad.py b/test_regress/t/t_cover_fsm_plain_always_warn_multi_bad.py index 57716476b..b2d69f8eb 100755 --- a/test_regress/t/t_cover_fsm_plain_always_warn_multi_bad.py +++ b/test_regress/t/t_cover_fsm_plain_always_warn_multi_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(verilator_flags2=['--cc --coverage-fsm'], fails=True, diff --git a/test_regress/t/t_cover_fsm_plain_always_zerohit_multi.py b/test_regress/t/t_cover_fsm_plain_always_zerohit_multi.py index 163436db8..19a4c5140 100755 --- a/test_regress/t/t_cover_fsm_plain_always_zerohit_multi.py +++ b/test_regress/t/t_cover_fsm_plain_always_zerohit_multi.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--cc --coverage-fsm', '-Werror-COVERIGN']) diff --git a/test_regress/t/t_cover_fsm_policy_accept_multi.py b/test_regress/t/t_cover_fsm_policy_accept_multi.py index 1b075a66f..b752dccce 100755 --- a/test_regress/t/t_cover_fsm_policy_accept_multi.py +++ b/test_regress/t/t_cover_fsm_policy_accept_multi.py @@ -12,6 +12,7 @@ import os import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--cc --coverage-fsm']) diff --git a/test_regress/t/t_cover_fsm_reset.py b/test_regress/t/t_cover_fsm_reset.py index 13a780eaa..53d8e4194 100755 --- a/test_regress/t/t_cover_fsm_reset.py +++ b/test_regress/t/t_cover_fsm_reset.py @@ -12,6 +12,7 @@ import os import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--cc --coverage-fsm']) diff --git a/test_regress/t/t_cover_fsm_reset_multi.py b/test_regress/t/t_cover_fsm_reset_multi.py index 6689f3ab2..15818bf21 100755 --- a/test_regress/t/t_cover_fsm_reset_multi.py +++ b/test_regress/t/t_cover_fsm_reset_multi.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False # Multiple reset assignments to the same FSM state variable are legal RTL but # not a realistic reset style to model as distinct reset arcs. Warn and ignore diff --git a/test_regress/t/t_cover_fsm_sel.py b/test_regress/t/t_cover_fsm_sel.py index 9d066e89e..9af30364e 100755 --- a/test_regress/t/t_cover_fsm_sel.py +++ b/test_regress/t/t_cover_fsm_sel.py @@ -12,6 +12,7 @@ import os import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--coverage"]) diff --git a/test_regress/t/t_cover_fsm_sel_assign.py b/test_regress/t/t_cover_fsm_sel_assign.py index 728658c89..15e488970 100755 --- a/test_regress/t/t_cover_fsm_sel_assign.py +++ b/test_regress/t/t_cover_fsm_sel_assign.py @@ -12,6 +12,7 @@ import os import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--coverage"]) diff --git a/test_regress/t/t_cover_fsm_sel_togglevar_unsup.py b/test_regress/t/t_cover_fsm_sel_togglevar_unsup.py index 59e566c59..4be6bdece 100755 --- a/test_regress/t/t_cover_fsm_sel_togglevar_unsup.py +++ b/test_regress/t/t_cover_fsm_sel_togglevar_unsup.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename, verilator_flags2=['--coverage']) diff --git a/test_regress/t/t_cover_fsm_transition_shapes_multi.py b/test_regress/t/t_cover_fsm_transition_shapes_multi.py index 46c209f35..66019ec3c 100755 --- a/test_regress/t/t_cover_fsm_transition_shapes_multi.py +++ b/test_regress/t/t_cover_fsm_transition_shapes_multi.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--cc --coverage-fsm']) diff --git a/test_regress/t/t_cover_fsm_two_proc_multi.py b/test_regress/t/t_cover_fsm_two_proc_multi.py index 0768245c3..08e47ffe9 100755 --- a/test_regress/t/t_cover_fsm_two_proc_multi.py +++ b/test_regress/t/t_cover_fsm_two_proc_multi.py @@ -12,6 +12,7 @@ import os import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--cc --coverage']) diff --git a/test_regress/t/t_cover_fsm_wide_sparse.py b/test_regress/t/t_cover_fsm_wide_sparse.py index 8df28da15..e8d276b8c 100755 --- a/test_regress/t/t_cover_fsm_wide_sparse.py +++ b/test_regress/t/t_cover_fsm_wide_sparse.py @@ -12,6 +12,7 @@ import os import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--cc --coverage-fsm']) diff --git a/test_regress/t/t_cover_hier_inline.py b/test_regress/t/t_cover_hier_inline.py index 7bc7313df..945a6f58a 100755 --- a/test_regress/t/t_cover_hier_inline.py +++ b/test_regress/t/t_cover_hier_inline.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False # Keep this paired with t_cover_hier_noinline.py: both tests use the same # source and golden so inline and no-inline coverage are checked for parity. diff --git a/test_regress/t/t_cover_hier_noinline.py b/test_regress/t/t_cover_hier_noinline.py index d0f1c44df..0f391e688 100755 --- a/test_regress/t/t_cover_hier_noinline.py +++ b/test_regress/t/t_cover_hier_noinline.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False # Exercise both user and generated coverage in duplicated hierarchy instances; # the shared golden verifies inline and no-inline modules report the same diff --git a/test_regress/t/t_cover_line_cc.py b/test_regress/t/t_cover_line_cc.py index 132c62394..0a2acda5a 100755 --- a/test_regress/t/t_cover_line_cc.py +++ b/test_regress/t/t_cover_line_cc.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_cover_line.v" test.golden_filename = "t/t_cover_line.out" diff --git a/test_regress/t/t_cover_line_cc_vlt.py b/test_regress/t/t_cover_line_cc_vlt.py index 1d700d328..2cd332d49 100755 --- a/test_regress/t/t_cover_line_cc_vlt.py +++ b/test_regress/t/t_cover_line_cc_vlt.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_cover_line.v" test.golden_filename = "t/t_cover_line.out" diff --git a/test_regress/t/t_cover_line_expr_cc.py b/test_regress/t/t_cover_line_expr_cc.py index 2139f2018..e1cf182d9 100755 --- a/test_regress/t/t_cover_line_expr_cc.py +++ b/test_regress/t/t_cover_line_expr_cc.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_cover_expr.v" test.golden_filename = "t/t_cover_line_expr.out" diff --git a/test_regress/t/t_cover_line_sc.py b/test_regress/t/t_cover_line_sc.py index 2654687b3..62ca31d14 100755 --- a/test_regress/t/t_cover_line_sc.py +++ b/test_regress/t/t_cover_line_sc.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_cover_line.v" test.compile(verilator_flags2=['--sc --coverage-line +define+ATTRIBUTE']) diff --git a/test_regress/t/t_cover_line_trace.py b/test_regress/t/t_cover_line_trace.py index 8fec71ba8..49c987a8d 100755 --- a/test_regress/t/t_cover_line_trace.py +++ b/test_regress/t/t_cover_line_trace.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_cover_line.v" test.compile( diff --git a/test_regress/t/t_cover_line_tri_gate_cond.py b/test_regress/t/t_cover_line_tri_gate_cond.py index 17563e6f0..f0e8b5a96 100755 --- a/test_regress/t/t_cover_line_tri_gate_cond.py +++ b/test_regress/t/t_cover_line_tri_gate_cond.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.pli_filename = "t/t_tri_gate.cpp" test.top_filename = "t/t_tri_gate.v" diff --git a/test_regress/t/t_cover_line_wide_ternary.py b/test_regress/t/t_cover_line_wide_ternary.py index 055ae3d8e..edf491ec1 100755 --- a/test_regress/t/t_cover_line_wide_ternary.py +++ b/test_regress/t/t_cover_line_wide_ternary.py @@ -11,6 +11,7 @@ import vltest_bootstrap from pathlib import Path test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--cc', '--coverage-line']) diff --git a/test_regress/t/t_cover_otherdecl_dump.py b/test_regress/t/t_cover_otherdecl_dump.py index a82316eea..087f3a7c9 100755 --- a/test_regress/t/t_cover_otherdecl_dump.py +++ b/test_regress/t/t_cover_otherdecl_dump.py @@ -12,6 +12,7 @@ from pathlib import Path import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_cover_fsm_policy_accept_multi.v" # Dump generic COVEROTHERDECL nodes so AstCoverOtherDecl::dump() also sees diff --git a/test_regress/t/t_cover_per_instance_inline.py b/test_regress/t/t_cover_per_instance_inline.py index 33176a521..df148ed97 100755 --- a/test_regress/t/t_cover_per_instance_inline.py +++ b/test_regress/t/t_cover_per_instance_inline.py @@ -12,6 +12,7 @@ import os import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(top_filename="t/t_cover_per_instance.v", v_flags2=["+define+INLINE_CHILD"], diff --git a/test_regress/t/t_cover_per_instance_noinline.py b/test_regress/t/t_cover_per_instance_noinline.py index 4193ac5e8..408aa6f52 100755 --- a/test_regress/t/t_cover_per_instance_noinline.py +++ b/test_regress/t/t_cover_per_instance_noinline.py @@ -12,6 +12,7 @@ import os import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(top_filename="t/t_cover_per_instance.v", verilator_flags2=[ diff --git a/test_regress/t/t_cover_per_instance_user.py b/test_regress/t/t_cover_per_instance_user.py index 33d93bc19..02cdee5c6 100755 --- a/test_regress/t/t_cover_per_instance_user.py +++ b/test_regress/t/t_cover_per_instance_user.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=[ '--binary', diff --git a/test_regress/t/t_cover_property.py b/test_regress/t/t_cover_property.py index ef1f5c1ed..84386529c 100755 --- a/test_regress/t/t_cover_property.py +++ b/test_regress/t/t_cover_property.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(verilator_flags2=['--coverage', '--assert', '--timing']) diff --git a/test_regress/t/t_cover_sequence.py b/test_regress/t/t_cover_sequence.py index 23e13d99b..286d4a886 100755 --- a/test_regress/t/t_cover_sequence.py +++ b/test_regress/t/t_cover_sequence.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=['--assert', '--timing', '--coverage-user']) diff --git a/test_regress/t/t_cover_sequence_unsup.py b/test_regress/t/t_cover_sequence_unsup.py index 56c514bc5..50cd9a52a 100755 --- a/test_regress/t/t_cover_sequence_unsup.py +++ b/test_regress/t/t_cover_sequence_unsup.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert --error-limit 1000'], diff --git a/test_regress/t/t_cover_sva_notflat.py b/test_regress/t/t_cover_sva_notflat.py index 6d9931532..dd4d0717a 100755 --- a/test_regress/t/t_cover_sva_notflat.py +++ b/test_regress/t/t_cover_sva_notflat.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--assert --cc --coverage-user']) diff --git a/test_regress/t/t_cover_sva_trace.py b/test_regress/t/t_cover_sva_trace.py index 5a27d61d4..fb0408022 100755 --- a/test_regress/t/t_cover_sva_trace.py +++ b/test_regress/t/t_cover_sva_trace.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_cover_sva_notflat.v" test.compile(verilator_flags2=['--assert --cc --coverage-user --trace-vcd --trace-coverage']) diff --git a/test_regress/t/t_cover_sys_line_expr.py b/test_regress/t/t_cover_sys_line_expr.py index 763e18bc3..350ec9f5e 100755 --- a/test_regress/t/t_cover_sys_line_expr.py +++ b/test_regress/t/t_cover_sys_line_expr.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios("simulator") +test.fourstate_capable = False test.compile(verilator_flags2=["--cc --coverage-line --coverage-expr"]) diff --git a/test_regress/t/t_cover_toggle.py b/test_regress/t/t_cover_toggle.py index e15a9a488..b9b28953b 100755 --- a/test_regress/t/t_cover_toggle.py +++ b/test_regress/t/t_cover_toggle.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--cc --coverage-toggle --stats']) diff --git a/test_regress/t/t_cover_toggle_min.py b/test_regress/t/t_cover_toggle_min.py index 9c454c71c..7b2a213cf 100755 --- a/test_regress/t/t_cover_toggle_min.py +++ b/test_regress/t/t_cover_toggle_min.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary', '--coverage-toggle']) diff --git a/test_regress/t/t_cover_toggle_underscore.py b/test_regress/t/t_cover_toggle_underscore.py index 0c7eb2ed7..776c7bfbe 100755 --- a/test_regress/t/t_cover_toggle_underscore.py +++ b/test_regress/t/t_cover_toggle_underscore.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = 't/t_cover_toggle.v' test.compile(verilator_flags2=['--cc --coverage-toggle --coverage-underscore']) diff --git a/test_regress/t/t_cover_toggle_width.py b/test_regress/t/t_cover_toggle_width.py index 68185902b..d7595d074 100755 --- a/test_regress/t/t_cover_toggle_width.py +++ b/test_regress/t/t_cover_toggle_width.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_cover_toggle.v" test.compile(verilator_flags2=['--cc --coverage-toggle --coverage-max-width 1025']) diff --git a/test_regress/t/t_cover_trace_always.py b/test_regress/t/t_cover_trace_always.py index 05c05a4b2..7c820e31d 100755 --- a/test_regress/t/t_cover_trace_always.py +++ b/test_regress/t/t_cover_trace_always.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary --coverage --trace-coverage --trace-vcd']) diff --git a/test_regress/t/t_cover_unused_bad.py b/test_regress/t/t_cover_unused_bad.py index cc0bb1049..54758ac35 100755 --- a/test_regress/t/t_cover_unused_bad.py +++ b/test_regress/t/t_cover_unused_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(verilator_flags2=["-Wall -Wno-DECLFILENAME --coverage"], fails=True, diff --git a/test_regress/t/t_covergroup_args.py b/test_regress/t/t_covergroup_args.py index 20a45138f..6fb3d6f6d 100755 --- a/test_regress/t/t_covergroup_args.py +++ b/test_regress/t/t_covergroup_args.py @@ -12,5 +12,6 @@ import vltest_bootstrap import coverage_covergroup_common test.scenarios('vlt') +test.fourstate_capable = False coverage_covergroup_common.run(test) diff --git a/test_regress/t/t_covergroup_auto_bin_max.py b/test_regress/t/t_covergroup_auto_bin_max.py index 4c22a684c..c74cd4faa 100755 --- a/test_regress/t/t_covergroup_auto_bin_max.py +++ b/test_regress/t/t_covergroup_auto_bin_max.py @@ -11,5 +11,6 @@ import vltest_bootstrap import coverage_covergroup_common test.scenarios('vlt') +test.fourstate_capable = False coverage_covergroup_common.run(test) diff --git a/test_regress/t/t_covergroup_auto_bin_max_bad.py b/test_regress/t/t_covergroup_auto_bin_max_bad.py index ecc1e3c96..261da8e46 100755 --- a/test_regress/t/t_covergroup_auto_bin_max_bad.py +++ b/test_regress/t/t_covergroup_auto_bin_max_bad.py @@ -9,6 +9,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(expect_filename=test.golden_filename, fails=True) diff --git a/test_regress/t/t_covergroup_auto_bins.py b/test_regress/t/t_covergroup_auto_bins.py index 9f6b5465d..9c3727141 100755 --- a/test_regress/t/t_covergroup_auto_bins.py +++ b/test_regress/t/t_covergroup_auto_bins.py @@ -11,5 +11,6 @@ import vltest_bootstrap import coverage_covergroup_common test.scenarios('vlt_all') +test.fourstate_capable = False coverage_covergroup_common.run(test) diff --git a/test_regress/t/t_covergroup_auto_sample_timing.py b/test_regress/t/t_covergroup_auto_sample_timing.py index 2a533c364..df8fb096f 100755 --- a/test_regress/t/t_covergroup_auto_sample_timing.py +++ b/test_regress/t/t_covergroup_auto_sample_timing.py @@ -11,6 +11,7 @@ import vltest_bootstrap import coverage_covergroup_common test.scenarios('vlt') +test.fourstate_capable = False # Use the same .v file as the non-timing test test.top_filename = "t/t_covergroup_clocked_sample.v" diff --git a/test_regress/t/t_covergroup_autobins_bad.py b/test_regress/t/t_covergroup_autobins_bad.py index ef7407f24..8d57b32a2 100755 --- a/test_regress/t/t_covergroup_autobins_bad.py +++ b/test_regress/t/t_covergroup_autobins_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(expect_filename=test.golden_filename, fails=True) diff --git a/test_regress/t/t_covergroup_bin_counts.py b/test_regress/t/t_covergroup_bin_counts.py index b25c6b6b5..3640a7050 100755 --- a/test_regress/t/t_covergroup_bin_counts.py +++ b/test_regress/t/t_covergroup_bin_counts.py @@ -11,6 +11,7 @@ import vltest_bootstrap import coverage_covergroup_common test.scenarios('vlt') +test.fourstate_capable = False coverage_covergroup_common.run(test) diff --git a/test_regress/t/t_covergroup_clocked_sample.py b/test_regress/t/t_covergroup_clocked_sample.py index be9b453d3..d0d581ccf 100755 --- a/test_regress/t/t_covergroup_clocked_sample.py +++ b/test_regress/t/t_covergroup_clocked_sample.py @@ -12,5 +12,6 @@ import coverage_covergroup_common # Issue #7779 unstable with --vltmt test.scenarios('vlt') +test.fourstate_capable = False coverage_covergroup_common.run(test) diff --git a/test_regress/t/t_covergroup_cross.py b/test_regress/t/t_covergroup_cross.py index ca81cf2c1..1578be409 100755 --- a/test_regress/t/t_covergroup_cross.py +++ b/test_regress/t/t_covergroup_cross.py @@ -11,5 +11,6 @@ import vltest_bootstrap import coverage_covergroup_common test.scenarios('vlt_all') +test.fourstate_capable = False coverage_covergroup_common.run(test, verilator_flags2=['--Wno-COVERIGN']) diff --git a/test_regress/t/t_covergroup_cross_opt_unsup.py b/test_regress/t/t_covergroup_cross_opt_unsup.py index ecc1e3c96..261da8e46 100755 --- a/test_regress/t/t_covergroup_cross_opt_unsup.py +++ b/test_regress/t/t_covergroup_cross_opt_unsup.py @@ -9,6 +9,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(expect_filename=test.golden_filename, fails=True) diff --git a/test_regress/t/t_covergroup_default_bins.py b/test_regress/t/t_covergroup_default_bins.py index 6b0f1a9e4..7fab8bca5 100755 --- a/test_regress/t/t_covergroup_default_bins.py +++ b/test_regress/t/t_covergroup_default_bins.py @@ -11,5 +11,6 @@ import vltest_bootstrap import coverage_covergroup_common test.scenarios('vlt') +test.fourstate_capable = False coverage_covergroup_common.run(test) diff --git a/test_regress/t/t_covergroup_embedded_unsup.py b/test_regress/t/t_covergroup_embedded_unsup.py index 77a0ac64b..b8c5d4bde 100755 --- a/test_regress/t/t_covergroup_embedded_unsup.py +++ b/test_regress/t/t_covergroup_embedded_unsup.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(expect_filename=test.golden_filename, fails=True) diff --git a/test_regress/t/t_covergroup_iff.py b/test_regress/t/t_covergroup_iff.py index 6b0f1a9e4..7fab8bca5 100755 --- a/test_regress/t/t_covergroup_iff.py +++ b/test_regress/t/t_covergroup_iff.py @@ -11,5 +11,6 @@ import vltest_bootstrap import coverage_covergroup_common test.scenarios('vlt') +test.fourstate_capable = False coverage_covergroup_common.run(test) diff --git a/test_regress/t/t_covergroup_ignore_bins.py b/test_regress/t/t_covergroup_ignore_bins.py index 6b0f1a9e4..7fab8bca5 100755 --- a/test_regress/t/t_covergroup_ignore_bins.py +++ b/test_regress/t/t_covergroup_ignore_bins.py @@ -11,5 +11,6 @@ import vltest_bootstrap import coverage_covergroup_common test.scenarios('vlt') +test.fourstate_capable = False coverage_covergroup_common.run(test) diff --git a/test_regress/t/t_covergroup_illegal_bins.py b/test_regress/t/t_covergroup_illegal_bins.py index 6b0f1a9e4..7fab8bca5 100755 --- a/test_regress/t/t_covergroup_illegal_bins.py +++ b/test_regress/t/t_covergroup_illegal_bins.py @@ -11,5 +11,6 @@ import vltest_bootstrap import coverage_covergroup_common test.scenarios('vlt') +test.fourstate_capable = False coverage_covergroup_common.run(test) diff --git a/test_regress/t/t_covergroup_member_event_unsup.py b/test_regress/t/t_covergroup_member_event_unsup.py index 695572bb1..d72ea051d 100755 --- a/test_regress/t/t_covergroup_member_event_unsup.py +++ b/test_regress/t/t_covergroup_member_event_unsup.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(expect_filename=test.golden_filename, fails=True) diff --git a/test_regress/t/t_covergroup_negative_ranges.py b/test_regress/t/t_covergroup_negative_ranges.py index ab1d96563..0e46e4cf0 100755 --- a/test_regress/t/t_covergroup_negative_ranges.py +++ b/test_regress/t/t_covergroup_negative_ranges.py @@ -8,5 +8,6 @@ import vltest_bootstrap import coverage_covergroup_common test.scenarios('vlt') +test.fourstate_capable = False coverage_covergroup_common.run(test) diff --git a/test_regress/t/t_covergroup_option.py b/test_regress/t/t_covergroup_option.py index c1bdd3d22..cfb44c977 100755 --- a/test_regress/t/t_covergroup_option.py +++ b/test_regress/t/t_covergroup_option.py @@ -11,5 +11,6 @@ import vltest_bootstrap import coverage_covergroup_common test.scenarios('vlt') +test.fourstate_capable = False coverage_covergroup_common.run(test, verilator_flags2=['--Wno-COVERIGN']) diff --git a/test_regress/t/t_covergroup_option_unsup.py b/test_regress/t/t_covergroup_option_unsup.py index ef7407f24..8d57b32a2 100755 --- a/test_regress/t/t_covergroup_option_unsup.py +++ b/test_regress/t/t_covergroup_option_unsup.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(expect_filename=test.golden_filename, fails=True) diff --git a/test_regress/t/t_covergroup_param_bins.py b/test_regress/t/t_covergroup_param_bins.py index ab1d96563..0e46e4cf0 100755 --- a/test_regress/t/t_covergroup_param_bins.py +++ b/test_regress/t/t_covergroup_param_bins.py @@ -8,5 +8,6 @@ import vltest_bootstrap import coverage_covergroup_common test.scenarios('vlt') +test.fourstate_capable = False coverage_covergroup_common.run(test) diff --git a/test_regress/t/t_covergroup_trans.py b/test_regress/t/t_covergroup_trans.py index ca81cf2c1..1578be409 100755 --- a/test_regress/t/t_covergroup_trans.py +++ b/test_regress/t/t_covergroup_trans.py @@ -11,5 +11,6 @@ import vltest_bootstrap import coverage_covergroup_common test.scenarios('vlt_all') +test.fourstate_capable = False coverage_covergroup_common.run(test, verilator_flags2=['--Wno-COVERIGN']) diff --git a/test_regress/t/t_covergroup_trans_errors_bad.py b/test_regress/t/t_covergroup_trans_errors_bad.py index ef7407f24..8d57b32a2 100755 --- a/test_regress/t/t_covergroup_trans_errors_bad.py +++ b/test_regress/t/t_covergroup_trans_errors_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(expect_filename=test.golden_filename, fails=True) diff --git a/test_regress/t/t_covergroup_trans_restart.py b/test_regress/t/t_covergroup_trans_restart.py index 6b0f1a9e4..7fab8bca5 100755 --- a/test_regress/t/t_covergroup_trans_restart.py +++ b/test_regress/t/t_covergroup_trans_restart.py @@ -11,5 +11,6 @@ import vltest_bootstrap import coverage_covergroup_common test.scenarios('vlt') +test.fourstate_capable = False coverage_covergroup_common.run(test) diff --git a/test_regress/t/t_covergroup_undef_field_bad.py b/test_regress/t/t_covergroup_undef_field_bad.py index 695572bb1..d72ea051d 100755 --- a/test_regress/t/t_covergroup_undef_field_bad.py +++ b/test_regress/t/t_covergroup_undef_field_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(expect_filename=test.golden_filename, fails=True) diff --git a/test_regress/t/t_covergroup_unsup.py b/test_regress/t/t_covergroup_unsup.py index 695572bb1..d72ea051d 100755 --- a/test_regress/t/t_covergroup_unsup.py +++ b/test_regress/t/t_covergroup_unsup.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(expect_filename=test.golden_filename, fails=True) diff --git a/test_regress/t/t_covergroup_unsup_ign.py b/test_regress/t/t_covergroup_unsup_ign.py index 4fe9db965..94ffdacf7 100755 --- a/test_regress/t/t_covergroup_unsup_ign.py +++ b/test_regress/t/t_covergroup_unsup_ign.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_covergroup_unsup.v" test.lint(verilator_flags2=['--assert --coverage --Wno-COVERIGN +define+T_COVERGROUP_UNSUP_IGN'], diff --git a/test_regress/t/t_covergroup_unsup_ign2.py b/test_regress/t/t_covergroup_unsup_ign2.py index 9ea990866..783bad4b3 100755 --- a/test_regress/t/t_covergroup_unsup_ign2.py +++ b/test_regress/t/t_covergroup_unsup_ign2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_covergroup_unsup.v" test.lint(verilator_flags2=[ diff --git a/test_regress/t/t_debug_emitv.py b/test_regress/t/t_debug_emitv.py index 29c864976..0913aaf42 100755 --- a/test_regress/t/t_debug_emitv.py +++ b/test_regress/t/t_debug_emitv.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios("vlt") +test.fourstate_capable = False test.lint( # We also have dump-tree turned on, so hit a lot of AstNode*::dump() functions diff --git a/test_regress/t/t_debug_emitv_addrids.py b/test_regress/t/t_debug_emitv_addrids.py index dec2a3a47..54f4cb6c2 100755 --- a/test_regress/t/t_debug_emitv_addrids.py +++ b/test_regress/t/t_debug_emitv_addrids.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_debug_emitv.v" test.lint( diff --git a/test_regress/t/t_debug_width.py b/test_regress/t/t_debug_width.py index 45a700fcb..03726f9a6 100755 --- a/test_regress/t/t_debug_width.py +++ b/test_regress/t/t_debug_width.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_opt_const.v" test.lint(verilator_flags2=["--debug-width"], fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_default_disable_iff_scope.py b/test_regress/t/t_default_disable_iff_scope.py index 35e44000c..84d6e744b 100755 --- a/test_regress/t/t_default_disable_iff_scope.py +++ b/test_regress/t/t_default_disable_iff_scope.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=['--assert', '--timing']) diff --git a/test_regress/t/t_delay_timing.py b/test_regress/t/t_delay_timing.py index 6018fde16..ce82130d9 100755 --- a/test_regress/t/t_delay_timing.py +++ b/test_regress/t/t_delay_timing.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_delay.v" test.compile(verilator_flags2=['--binary -Wno-ZERODLY']) diff --git a/test_regress/t/t_delay_var.py b/test_regress/t/t_delay_var.py index 9b8d8f041..b122eaac4 100755 --- a/test_regress/t/t_delay_var.py +++ b/test_regress/t/t_delay_var.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_depth_flop.py b/test_regress/t/t_depth_flop.py index 0c191b8c9..de6e6308a 100755 --- a/test_regress/t/t_depth_flop.py +++ b/test_regress/t/t_depth_flop.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vltmt') # Note issue shows up with --threads +test.fourstate_capable = False test.compile(verilator_flags2=['--compiler clang -Wno-UNOPTTHREADS'], threads=2) diff --git a/test_regress/t/t_detectarray_1.py b/test_regress/t/t_detectarray_1.py index 0bed5b40c..54100b4eb 100755 --- a/test_regress/t/t_detectarray_1.py +++ b/test_regress/t/t_detectarray_1.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["-Wno-UNOPTFLAT", "-fno-dfg"]) diff --git a/test_regress/t/t_detectarray_2.py b/test_regress/t/t_detectarray_2.py index 0bed5b40c..54100b4eb 100755 --- a/test_regress/t/t_detectarray_2.py +++ b/test_regress/t/t_detectarray_2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["-Wno-UNOPTFLAT", "-fno-dfg"]) diff --git a/test_regress/t/t_detectarray_3.py b/test_regress/t/t_detectarray_3.py index c4cba146d..317aa35d5 100755 --- a/test_regress/t/t_detectarray_3.py +++ b/test_regress/t/t_detectarray_3.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["-Wno-UNOPTFLAT", "-Wno-WIDTH", "-fno-dfg"]) diff --git a/test_regress/t/t_dfg_3676.py b/test_regress/t/t_dfg_3676.py index 46f459325..5ac68e5d3 100755 --- a/test_regress/t/t_dfg_3676.py +++ b/test_regress/t/t_dfg_3676.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_dfg_4943.py b/test_regress/t/t_dfg_4943.py index 46f459325..5ac68e5d3 100755 --- a/test_regress/t/t_dfg_4943.py +++ b/test_regress/t/t_dfg_4943.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_dfg_astrefs.py b/test_regress/t/t_dfg_astrefs.py index fe7150491..1c2876612 100755 --- a/test_regress/t/t_dfg_astrefs.py +++ b/test_regress/t/t_dfg_astrefs.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_dfg_bin_to_one_hot.py b/test_regress/t/t_dfg_bin_to_one_hot.py index acd1c67c8..4117d617f 100755 --- a/test_regress/t/t_dfg_bin_to_one_hot.py +++ b/test_regress/t/t_dfg_bin_to_one_hot.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(verilator_flags2=["--stats", "-fno-table", "-fno-inline"]) diff --git a/test_regress/t/t_dfg_break_cycles.py b/test_regress/t/t_dfg_break_cycles.py index ec6c6b339..32c7a9f84 100755 --- a/test_regress/t/t_dfg_break_cycles.py +++ b/test_regress/t/t_dfg_break_cycles.py @@ -12,6 +12,7 @@ import vltest_bootstrap import os test.scenarios('vlt_all') +test.fourstate_capable = False test.sim_time = 2000000 if not os.path.exists(test.root + "/.git"): diff --git a/test_regress/t/t_dfg_circular_merged_scc.py b/test_regress/t/t_dfg_circular_merged_scc.py index 10ad7f0de..89d778552 100755 --- a/test_regress/t/t_dfg_circular_merged_scc.py +++ b/test_regress/t/t_dfg_circular_merged_scc.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_dfg_constpool_unused.py b/test_regress/t/t_dfg_constpool_unused.py index d8194a13e..5282d2bb4 100755 --- a/test_regress/t/t_dfg_constpool_unused.py +++ b/test_regress/t/t_dfg_constpool_unused.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary', '--stats']) diff --git a/test_regress/t/t_dfg_dump_patterns.py b/test_regress/t/t_dfg_dump_patterns.py index d0f557d1d..ec0bd8858 100755 --- a/test_regress/t/t_dfg_dump_patterns.py +++ b/test_regress/t/t_dfg_dump_patterns.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(verilator_flags2=["--dump-dfg-patterns --no-skip-identical"]) diff --git a/test_regress/t/t_dfg_inline_forced.py b/test_regress/t/t_dfg_inline_forced.py index 46f459325..5ac68e5d3 100755 --- a/test_regress/t/t_dfg_inline_forced.py +++ b/test_regress/t/t_dfg_inline_forced.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_dfg_multidriver_dfg_bad.py b/test_regress/t/t_dfg_multidriver_dfg_bad.py index 2b3ca29ee..6eac3db9c 100755 --- a/test_regress/t/t_dfg_multidriver_dfg_bad.py +++ b/test_regress/t/t_dfg_multidriver_dfg_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(verilator_flags2=["-fdfg-synthesize-all", "-fno-const-before-dfg"], fails=True, diff --git a/test_regress/t/t_dfg_oob_sel_rvalue.py b/test_regress/t/t_dfg_oob_sel_rvalue.py index 76205c3f9..d00ed2a97 100755 --- a/test_regress/t/t_dfg_oob_sel_rvalue.py +++ b/test_regress/t/t_dfg_oob_sel_rvalue.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(verilator_flags2=["--stats"]) diff --git a/test_regress/t/t_dfg_peephole.py b/test_regress/t/t_dfg_peephole.py index 593b11b10..2832d4acf 100755 --- a/test_regress/t/t_dfg_peephole.py +++ b/test_regress/t/t_dfg_peephole.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.sim_time = 2000000 test.top_filename = "t/t_dfg_peephole.v" diff --git a/test_regress/t/t_dfg_peephole_off_all.py b/test_regress/t/t_dfg_peephole_off_all.py index 61d349322..ebfb24309 100755 --- a/test_regress/t/t_dfg_peephole_off_all.py +++ b/test_regress/t/t_dfg_peephole_off_all.py @@ -12,5 +12,6 @@ import vltest_bootstrap import runpy test.scenarios('vlt_all') +test.fourstate_capable = False runpy.run_path("t/t_dfg_peephole.py", globals()) diff --git a/test_regress/t/t_dfg_peephole_off_each.py b/test_regress/t/t_dfg_peephole_off_each.py index 61d349322..ebfb24309 100755 --- a/test_regress/t/t_dfg_peephole_off_each.py +++ b/test_regress/t/t_dfg_peephole_off_each.py @@ -12,5 +12,6 @@ import vltest_bootstrap import runpy test.scenarios('vlt_all') +test.fourstate_capable = False runpy.run_path("t/t_dfg_peephole.py", globals()) diff --git a/test_regress/t/t_dfg_regularize_circular.py b/test_regress/t/t_dfg_regularize_circular.py index 46f459325..5ac68e5d3 100755 --- a/test_regress/t/t_dfg_regularize_circular.py +++ b/test_regress/t/t_dfg_regularize_circular.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_dfg_regularize_clk.py b/test_regress/t/t_dfg_regularize_clk.py index 63315cbc5..cbdd466d7 100755 --- a/test_regress/t/t_dfg_regularize_clk.py +++ b/test_regress/t/t_dfg_regularize_clk.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(verilator_flags2=["--hierarchical", "--trace"]) diff --git a/test_regress/t/t_dfg_regularize_driver_of_sc_var.py b/test_regress/t/t_dfg_regularize_driver_of_sc_var.py index 1175ee8cc..e97f76f8a 100755 --- a/test_regress/t/t_dfg_regularize_driver_of_sc_var.py +++ b/test_regress/t/t_dfg_regularize_driver_of_sc_var.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(verilator_flags2=["--sc"]) diff --git a/test_regress/t/t_dfg_result_var_ext_write.py b/test_regress/t/t_dfg_result_var_ext_write.py index 3c6aa8922..0a6d6f6fe 100755 --- a/test_regress/t/t_dfg_result_var_ext_write.py +++ b/test_regress/t/t_dfg_result_var_ext_write.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_dfg_synthesis.py b/test_regress/t/t_dfg_synthesis.py index bad50c846..5cd216836 100755 --- a/test_regress/t/t_dfg_synthesis.py +++ b/test_regress/t/t_dfg_synthesis.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.sim_time = 2000000 if not os.path.exists(test.root + "/.git"): diff --git a/test_regress/t/t_dfg_true_cycle_bad.py b/test_regress/t/t_dfg_true_cycle_bad.py index f3bbcad9d..f38b02634 100755 --- a/test_regress/t/t_dfg_true_cycle_bad.py +++ b/test_regress/t/t_dfg_true_cycle_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_disable.py b/test_regress/t/t_disable.py index 276645160..8824db0e5 100755 --- a/test_regress/t/t_disable.py +++ b/test_regress/t/t_disable.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=["--timing"]) diff --git a/test_regress/t/t_disable_empty.py b/test_regress/t/t_disable_empty.py index 7ded63f3a..d210ebd50 100755 --- a/test_regress/t/t_disable_empty.py +++ b/test_regress/t/t_disable_empty.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_disable_empty_outside.py b/test_regress/t/t_disable_empty_outside.py index 276645160..8824db0e5 100755 --- a/test_regress/t/t_disable_empty_outside.py +++ b/test_regress/t/t_disable_empty_outside.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=["--timing"]) diff --git a/test_regress/t/t_disable_fork_nested.py b/test_regress/t/t_disable_fork_nested.py index b716266af..1506db89d 100755 --- a/test_regress/t/t_disable_fork_nested.py +++ b/test_regress/t/t_disable_fork_nested.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary", "-Wno-ZERODLY"]) diff --git a/test_regress/t/t_disable_genfor2.py b/test_regress/t/t_disable_genfor2.py index 7ded63f3a..d210ebd50 100755 --- a/test_regress/t/t_disable_genfor2.py +++ b/test_regress/t/t_disable_genfor2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_disable_inside.py b/test_regress/t/t_disable_inside.py index 276645160..8824db0e5 100755 --- a/test_regress/t/t_disable_inside.py +++ b/test_regress/t/t_disable_inside.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=["--timing"]) diff --git a/test_regress/t/t_disable_outside.py b/test_regress/t/t_disable_outside.py index 276645160..8824db0e5 100755 --- a/test_regress/t/t_disable_outside.py +++ b/test_regress/t/t_disable_outside.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=["--timing"]) diff --git a/test_regress/t/t_disable_outside2.py b/test_regress/t/t_disable_outside2.py index 276645160..8824db0e5 100755 --- a/test_regress/t/t_disable_outside2.py +++ b/test_regress/t/t_disable_outside2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=["--timing"]) diff --git a/test_regress/t/t_disable_outside3.py b/test_regress/t/t_disable_outside3.py index 276645160..8824db0e5 100755 --- a/test_regress/t/t_disable_outside3.py +++ b/test_regress/t/t_disable_outside3.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=["--timing"]) diff --git a/test_regress/t/t_disable_outside4.py b/test_regress/t/t_disable_outside4.py index 276645160..8824db0e5 100755 --- a/test_regress/t/t_disable_outside4.py +++ b/test_regress/t/t_disable_outside4.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=["--timing"]) diff --git a/test_regress/t/t_disable_task_by_name.py b/test_regress/t/t_disable_task_by_name.py index 390bba1b8..51c729a6e 100755 --- a/test_regress/t/t_disable_task_by_name.py +++ b/test_regress/t/t_disable_task_by_name.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=["--timing"]) diff --git a/test_regress/t/t_disable_task_join.py b/test_regress/t/t_disable_task_join.py index 55da782f9..b41fd0ce7 100755 --- a/test_regress/t/t_disable_task_join.py +++ b/test_regress/t/t_disable_task_join.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=["--timing"]) diff --git a/test_regress/t/t_disable_task_simple.py b/test_regress/t/t_disable_task_simple.py index 276645160..8824db0e5 100755 --- a/test_regress/t/t_disable_task_simple.py +++ b/test_regress/t/t_disable_task_simple.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=["--timing"]) diff --git a/test_regress/t/t_display.py b/test_regress/t/t_display.py index ed8db10e9..8aeecc749 100755 --- a/test_regress/t/t_display.py +++ b/test_regress/t/t_display.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_display_brace.py b/test_regress/t/t_display_brace.py index 84b274f68..17424b42f 100755 --- a/test_regress/t/t_display_brace.py +++ b/test_regress/t/t_display_brace.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_display_enum_format.py b/test_regress/t/t_display_enum_format.py index 8a938befd..a10e2547d 100755 --- a/test_regress/t/t_display_enum_format.py +++ b/test_regress/t/t_display_enum_format.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_display_noopt.py b/test_regress/t/t_display_noopt.py index aa3c4d3d3..dc89cc0d1 100755 --- a/test_regress/t/t_display_noopt.py +++ b/test_regress/t/t_display_noopt.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_display.v" test.golden_filename = "t/t_display.out" diff --git a/test_regress/t/t_display_real.py b/test_regress/t/t_display_real.py index ed8db10e9..8aeecc749 100755 --- a/test_regress/t/t_display_real.py +++ b/test_regress/t/t_display_real.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_display_real_noopt.py b/test_regress/t/t_display_real_noopt.py index fa74c3c9e..9a6d33f03 100755 --- a/test_regress/t/t_display_real_noopt.py +++ b/test_regress/t/t_display_real_noopt.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_display_real.v" test.golden_filename = "t/t_display_real.out" diff --git a/test_regress/t/t_display_recurse.py b/test_regress/t/t_display_recurse.py index ed8db10e9..8aeecc749 100755 --- a/test_regress/t/t_display_recurse.py +++ b/test_regress/t/t_display_recurse.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_display_signed.py b/test_regress/t/t_display_signed.py index ed8db10e9..8aeecc749 100755 --- a/test_regress/t/t_display_signed.py +++ b/test_regress/t/t_display_signed.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_display_signed_noopt.py b/test_regress/t/t_display_signed_noopt.py index 8a54193d2..f5727da29 100755 --- a/test_regress/t/t_display_signed_noopt.py +++ b/test_regress/t/t_display_signed_noopt.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_display_signed.v" test.golden_filename = "t/t_display_signed.out" diff --git a/test_regress/t/t_display_wide.py b/test_regress/t/t_display_wide.py index ed8db10e9..8aeecc749 100755 --- a/test_regress/t/t_display_wide.py +++ b/test_regress/t/t_display_wide.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_dotfiles.py b/test_regress/t/t_dotfiles.py index 3145748f6..7dbd5e63d 100755 --- a/test_regress/t/t_dotfiles.py +++ b/test_regress/t/t_dotfiles.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vltmt') +test.fourstate_capable = False # Use a top file which we are sure to be parallelizable test.top_filename = "t/t_gen_alw.v" diff --git a/test_regress/t/t_dpi_2exparg_bad.py b/test_regress/t/t_dpi_2exparg_bad.py index 1952b53a1..873d22c46 100755 --- a/test_regress/t/t_dpi_2exparg_bad.py +++ b/test_regress/t/t_dpi_2exparg_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_dpi_accessors.py b/test_regress/t/t_dpi_accessors.py index df409b3e6..9bbed7220 100755 --- a/test_regress/t/t_dpi_accessors.py +++ b/test_regress/t/t_dpi_accessors.py @@ -13,6 +13,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(make_top_shell=False, make_main=False, diff --git a/test_regress/t/t_dpi_arg_inout_type.py b/test_regress/t/t_dpi_arg_inout_type.py index 14c3a8b01..e6af73fcf 100755 --- a/test_regress/t/t_dpi_arg_inout_type.py +++ b/test_regress/t/t_dpi_arg_inout_type.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if test.nc: # For NC, compile twice, first just to generate DPI headers diff --git a/test_regress/t/t_dpi_arg_inout_unpack.py b/test_regress/t/t_dpi_arg_inout_unpack.py index 9e5ecc737..b8f53465c 100755 --- a/test_regress/t/t_dpi_arg_inout_unpack.py +++ b/test_regress/t/t_dpi_arg_inout_unpack.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if test.nc: # For NC, compile twice, first just to generate DPI headers diff --git a/test_regress/t/t_dpi_arg_input_type.py b/test_regress/t/t_dpi_arg_input_type.py index 14c3a8b01..e6af73fcf 100755 --- a/test_regress/t/t_dpi_arg_input_type.py +++ b/test_regress/t/t_dpi_arg_input_type.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if test.nc: # For NC, compile twice, first just to generate DPI headers diff --git a/test_regress/t/t_dpi_arg_input_unpack.py b/test_regress/t/t_dpi_arg_input_unpack.py index 9e5ecc737..b8f53465c 100755 --- a/test_regress/t/t_dpi_arg_input_unpack.py +++ b/test_regress/t/t_dpi_arg_input_unpack.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if test.nc: # For NC, compile twice, first just to generate DPI headers diff --git a/test_regress/t/t_dpi_arg_output_type.py b/test_regress/t/t_dpi_arg_output_type.py index 14c3a8b01..e6af73fcf 100755 --- a/test_regress/t/t_dpi_arg_output_type.py +++ b/test_regress/t/t_dpi_arg_output_type.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if test.nc: # For NC, compile twice, first just to generate DPI headers diff --git a/test_regress/t/t_dpi_arg_output_unpack.py b/test_regress/t/t_dpi_arg_output_unpack.py index 9e5ecc737..b8f53465c 100755 --- a/test_regress/t/t_dpi_arg_output_unpack.py +++ b/test_regress/t/t_dpi_arg_output_unpack.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if test.nc: # For NC, compile twice, first just to generate DPI headers diff --git a/test_regress/t/t_dpi_class_param.py b/test_regress/t/t_dpi_class_param.py index e515b2452..7a331cb5e 100755 --- a/test_regress/t/t_dpi_class_param.py +++ b/test_regress/t/t_dpi_class_param.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary', test.pli_filename]) diff --git a/test_regress/t/t_dpi_export.py b/test_regress/t/t_dpi_export.py index ff105941a..97f7c0247 100755 --- a/test_regress/t/t_dpi_export.py +++ b/test_regress/t/t_dpi_export.py @@ -12,6 +12,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(v_flags2=["t/t_dpi_export_c.cpp"], verilator_flags2=["-Wall -Wno-DECLFILENAME -no-l2name"]) diff --git a/test_regress/t/t_dpi_export_noopt.py b/test_regress/t/t_dpi_export_noopt.py index 0919e7c46..1e0804665 100755 --- a/test_regress/t/t_dpi_export_noopt.py +++ b/test_regress/t/t_dpi_export_noopt.py @@ -12,6 +12,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_dpi_export.v" test.compile( diff --git a/test_regress/t/t_dpi_export_unpack.py b/test_regress/t/t_dpi_export_unpack.py index b365ee618..60bc35479 100755 --- a/test_regress/t/t_dpi_export_unpack.py +++ b/test_regress/t/t_dpi_export_unpack.py @@ -12,6 +12,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_dpi_if_cond.py b/test_regress/t/t_dpi_if_cond.py index acc933ae9..dcc4ad885 100755 --- a/test_regress/t/t_dpi_if_cond.py +++ b/test_regress/t/t_dpi_if_cond.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(v_flags2=["t/t_dpi_if_cond_c.cpp"]) diff --git a/test_regress/t/t_dpi_import.py b/test_regress/t/t_dpi_import.py index 04c801021..f87f339a3 100755 --- a/test_regress/t/t_dpi_import.py +++ b/test_regress/t/t_dpi_import.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(v_flags2=["t/t_dpi_import_c.cpp"], verilator_flags2=["-Wall -Wno-DECLFILENAME"]) diff --git a/test_regress/t/t_dpi_import_hdr_only.py b/test_regress/t/t_dpi_import_hdr_only.py index a1a6d32bb..f5e85d72c 100755 --- a/test_regress/t/t_dpi_import_hdr_only.py +++ b/test_regress/t/t_dpi_import_hdr_only.py @@ -11,6 +11,7 @@ import vltest_bootstrap import filecmp test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_dpi_import.v" tmp_dir = test.obj_dir + "/dpi-hdr" diff --git a/test_regress/t/t_dpi_instr_count_large_hier.py b/test_regress/t/t_dpi_instr_count_large_hier.py index 23091d496..36cfb32db 100755 --- a/test_regress/t/t_dpi_instr_count_large_hier.py +++ b/test_regress/t/t_dpi_instr_count_large_hier.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vltmt') +test.fourstate_capable = False test.clean_objs() test.top_filename = "t/t_dpi_instr_count_large.v" diff --git a/test_regress/t/t_dpi_open.py b/test_regress/t/t_dpi_open.py index f5713ec78..dc95c5084 100755 --- a/test_regress/t/t_dpi_open.py +++ b/test_regress/t/t_dpi_open.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(v_flags2=["t/t_dpi_open_c.cpp"], verilator_flags2=["-Wall -Wno-DECLFILENAME -unroll-count 1"]) diff --git a/test_regress/t/t_dpi_open_elem.py b/test_regress/t/t_dpi_open_elem.py index 685e2a7d4..cf46709ab 100755 --- a/test_regress/t/t_dpi_open_elem.py +++ b/test_regress/t/t_dpi_open_elem.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(v_flags2=["t/t_dpi_open_elem_c.cpp"], verilator_flags2=["-Wall -Wno-DECLFILENAME -unroll-count 1"]) diff --git a/test_regress/t/t_dpi_open_vecval.py b/test_regress/t/t_dpi_open_vecval.py index dac21360a..1d7f255c7 100755 --- a/test_regress/t/t_dpi_open_vecval.py +++ b/test_regress/t/t_dpi_open_vecval.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(v_flags2=["t/t_dpi_open_vecval_c.cpp"], verilator_flags2=["-Wall -Wno-DECLFILENAME -unroll-count 1"]) diff --git a/test_regress/t/t_dpi_result_type.py b/test_regress/t/t_dpi_result_type.py index 14c3a8b01..e6af73fcf 100755 --- a/test_regress/t/t_dpi_result_type.py +++ b/test_regress/t/t_dpi_result_type.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if test.nc: # For NC, compile twice, first just to generate DPI headers diff --git a/test_regress/t/t_dpi_result_type_bad.py b/test_regress/t/t_dpi_result_type_bad.py index e4c660f24..411b081df 100755 --- a/test_regress/t/t_dpi_result_type_bad.py +++ b/test_regress/t/t_dpi_result_type_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename, diff --git a/test_regress/t/t_dump_dfg.py b/test_regress/t/t_dump_dfg.py index 052e2b396..e4605880e 100755 --- a/test_regress/t/t_dump_dfg.py +++ b/test_regress/t/t_dump_dfg.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False # For code coverage of graph dumping, so does not matter much what the input is test.top_filename = "t/t_benchmark_mux4k.v" diff --git a/test_regress/t/t_dump_json.py b/test_regress/t/t_dump_json.py index 63fcca771..24eb5c4bb 100755 --- a/test_regress/t/t_dump_json.py +++ b/test_regress/t/t_dump_json.py @@ -11,6 +11,7 @@ import json import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_dump.v" out_filename = test.obj_dir + "/V" + test.name + "_002_cellsort.tree.json" diff --git a/test_regress/t/t_dynarray.py b/test_regress/t/t_dynarray.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_dynarray.py +++ b/test_regress/t/t_dynarray.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_dynarray_init.py b/test_regress/t/t_dynarray_init.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_dynarray_init.py +++ b/test_regress/t/t_dynarray_init.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_dynarray_method.py b/test_regress/t/t_dynarray_method.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_dynarray_method.py +++ b/test_regress/t/t_dynarray_method.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_dynarray_multid.py b/test_regress/t/t_dynarray_multid.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_dynarray_multid.py +++ b/test_regress/t/t_dynarray_multid.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_dynarray_param.py b/test_regress/t/t_dynarray_param.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_dynarray_param.py +++ b/test_regress/t/t_dynarray_param.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_embed1.py b/test_regress/t/t_embed1.py index 6d6bc7cf3..acd6c2236 100755 --- a/test_regress/t/t_embed1.py +++ b/test_regress/t/t_embed1.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False child_dir = test.obj_dir + "_child" test.mkdir_ok(child_dir) diff --git a/test_regress/t/t_emit_constw.py b/test_regress/t/t_emit_constw.py index ce4ff87ca..3aa360ff5 100755 --- a/test_regress/t/t_emit_constw.py +++ b/test_regress/t/t_emit_constw.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--fno-expand']) diff --git a/test_regress/t/t_emit_memb_limit.py b/test_regress/t/t_emit_memb_limit.py index 9fdb63b30..5d5a26dce 100755 --- a/test_regress/t/t_emit_memb_limit.py +++ b/test_regress/t/t_emit_memb_limit.py @@ -11,6 +11,7 @@ import vltest_bootstrap # Very slow on vltmt, and doesn't test much of value there, so disabled test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = test.obj_dir + "/t_emit_memb_limit.v" diff --git a/test_regress/t/t_enum.py b/test_regress/t/t_enum.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_enum.py +++ b/test_regress/t/t_enum.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_enum_const_methods.py b/test_regress/t/t_enum_const_methods.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_enum_const_methods.py +++ b/test_regress/t/t_enum_const_methods.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_enum_huge_methods.py b/test_regress/t/t_enum_huge_methods.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_enum_huge_methods.py +++ b/test_regress/t/t_enum_huge_methods.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_enum_int.py b/test_regress/t/t_enum_int.py index 8edf7f9f6..e167e354b 100755 --- a/test_regress/t/t_enum_int.py +++ b/test_regress/t/t_enum_int.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--debug", "--debugi", "0", "--dumpi-tree", "0"]) diff --git a/test_regress/t/t_enum_name2.py b/test_regress/t/t_enum_name2.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_enum_name2.py +++ b/test_regress/t/t_enum_name2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_enum_name3.py b/test_regress/t/t_enum_name3.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_enum_name3.py +++ b/test_regress/t/t_enum_name3.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_enum_name_sformatf.py b/test_regress/t/t_enum_name_sformatf.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_enum_name_sformatf.py +++ b/test_regress/t/t_enum_name_sformatf.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_enum_public.py b/test_regress/t/t_enum_public.py index f89e20642..af07323ca 100755 --- a/test_regress/t/t_enum_public.py +++ b/test_regress/t/t_enum_public.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if test.vlt_all: test.compile(verilator_flags2=["--exe", test.pli_filename], diff --git a/test_regress/t/t_enum_type_methods.py b/test_regress/t/t_enum_type_methods.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_enum_type_methods.py +++ b/test_regress/t/t_enum_type_methods.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_enum_type_pins.py b/test_regress/t/t_enum_type_pins.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_enum_type_pins.py +++ b/test_regress/t/t_enum_type_pins.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_enumeration.py b/test_regress/t/t_enumeration.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_enumeration.py +++ b/test_regress/t/t_enumeration.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_eq_wild_unsup.py b/test_regress/t/t_eq_wild_unsup.py index 3160d0589..763d0b4d6 100755 --- a/test_regress/t/t_eq_wild_unsup.py +++ b/test_regress/t/t_eq_wild_unsup.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_event.py b/test_regress/t/t_event.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_event.py +++ b/test_regress/t/t_event.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_event_class_fire.py b/test_regress/t/t_event_class_fire.py index 331309e57..2249bee06 100755 --- a/test_regress/t/t_event_class_fire.py +++ b/test_regress/t/t_event_class_fire.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False # Issue #5597 makes this fail test.compile(fails=test.vlt_all, diff --git a/test_regress/t/t_event_control_expr.py b/test_regress/t/t_event_control_expr.py index 9ae6ac710..20b6adfc4 100755 --- a/test_regress/t/t_event_control_expr.py +++ b/test_regress/t/t_event_control_expr.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile( # do not test classes for multithreaded, as V3InstrCount doesn't handle MemberSel diff --git a/test_regress/t/t_event_control_expr_noinl.py b/test_regress/t/t_event_control_expr_noinl.py index cae1d7b22..5aaade11e 100755 --- a/test_regress/t/t_event_control_expr_noinl.py +++ b/test_regress/t/t_event_control_expr_noinl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = 't_event_control_expr.v' test.compile( diff --git a/test_regress/t/t_event_control_prev_name_collision.py b/test_regress/t/t_event_control_prev_name_collision.py index 5d6840eb6..71e9baec2 100755 --- a/test_regress/t/t_event_control_prev_name_collision.py +++ b/test_regress/t/t_event_control_prev_name_collision.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_event_control_scope_var.py b/test_regress/t/t_event_control_scope_var.py index 9f40badfa..a18a77ef4 100755 --- a/test_regress/t/t_event_control_scope_var.py +++ b/test_regress/t/t_event_control_scope_var.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['-fno-inline', '-Wno-WIDTHTRUNC']) diff --git a/test_regress/t/t_event_dynamic_wait.py b/test_regress/t/t_event_dynamic_wait.py index f2d7f08fa..5790553c6 100755 --- a/test_regress/t/t_event_dynamic_wait.py +++ b/test_regress/t/t_event_dynamic_wait.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary', '--timing']) diff --git a/test_regress/t/t_export_packed_struct.py b/test_regress/t/t_export_packed_struct.py index f975b0638..c642c836e 100755 --- a/test_regress/t/t_export_packed_struct.py +++ b/test_regress/t/t_export_packed_struct.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(make_top_shell=False, make_main=False, diff --git a/test_regress/t/t_export_packed_struct2.cpp b/test_regress/t/t_export_packed_struct2.cpp index 94c6a3840..db73e7e48 100644 --- a/test_regress/t/t_export_packed_struct2.cpp +++ b/test_regress/t/t_export_packed_struct2.cpp @@ -78,7 +78,7 @@ int main(int argc, char** argv) { for (int i = 0; i < 3; ++i) { for (int j = 0; j < 3; ++j) { for (int k = 0; k < 3; ++k) { - VL_SET_WQ(in.b[i][j][k].a, 0x1234123412341234UL); + VL_SET_WQ_T(in.b[i][j][k].a, 0x1234123412341234UL); // Set last bit zero and upper bits one in.b[i][j][k].a[2] = 0xfe; } diff --git a/test_regress/t/t_export_packed_struct2.py b/test_regress/t/t_export_packed_struct2.py index 1864fa13a..b434211d8 100755 --- a/test_regress/t/t_export_packed_struct2.py +++ b/test_regress/t/t_export_packed_struct2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) diff --git a/test_regress/t/t_exprstmt_on_lhs_of_nba.py b/test_regress/t/t_exprstmt_on_lhs_of_nba.py index 10ad7f0de..89d778552 100755 --- a/test_regress/t/t_exprstmt_on_lhs_of_nba.py +++ b/test_regress/t/t_exprstmt_on_lhs_of_nba.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_extract_static_const.py b/test_regress/t/t_extract_static_const.py index 307854e91..370e8fd38 100755 --- a/test_regress/t/t_extract_static_const.py +++ b/test_regress/t/t_extract_static_const.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.compile(verilator_flags2=["--stats"]) diff --git a/test_regress/t/t_extract_static_const_no_merge.py b/test_regress/t/t_extract_static_const_no_merge.py index 09f698726..b0a9ba491 100755 --- a/test_regress/t/t_extract_static_const_no_merge.py +++ b/test_regress/t/t_extract_static_const_no_merge.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.top_filename = "t/t_extract_static_const.v" test.golden_filename = "t/t_extract_static_const.out" diff --git a/test_regress/t/t_finish_stops_nonfinal.py b/test_regress/t/t_finish_stops_nonfinal.py index 1365809b3..4a7eb7c49 100755 --- a/test_regress/t/t_finish_stops_nonfinal.py +++ b/test_regress/t/t_finish_stops_nonfinal.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(make_main=False, verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_flag_csplit.py b/test_regress/t/t_flag_csplit.py index 77b68dfd8..b529aff34 100755 --- a/test_regress/t/t_flag_csplit.py +++ b/test_regress/t/t_flag_csplit.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False def check_splits(): diff --git a/test_regress/t/t_flag_csplit_groups.py b/test_regress/t/t_flag_csplit_groups.py index 8210a6dbd..7263190d7 100755 --- a/test_regress/t/t_flag_csplit_groups.py +++ b/test_regress/t/t_flag_csplit_groups.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.top_filename = "t/t_flag_csplit.v" diff --git a/test_regress/t/t_flag_csplit_off.py b/test_regress/t/t_flag_csplit_off.py index b298d4700..9d3773bac 100755 --- a/test_regress/t/t_flag_csplit_off.py +++ b/test_regress/t/t_flag_csplit_off.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.top_filename = "t/t_flag_csplit.v" diff --git a/test_regress/t/t_flag_expand_limit.py b/test_regress/t/t_flag_expand_limit.py index d9b19b528..e96ab1bb4 100755 --- a/test_regress/t/t_flag_expand_limit.py +++ b/test_regress/t/t_flag_expand_limit.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(verilator_flags2=['--expand-limit 1 --stats -fno-dfg']) diff --git a/test_regress/t/t_flag_hier1_bad.py b/test_regress/t/t_flag_hier1_bad.py index d1ddb265d..9c3197d26 100755 --- a/test_regress/t/t_flag_hier1_bad.py +++ b/test_regress/t/t_flag_hier1_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_hier_block.v" test.lint(fails=True, diff --git a/test_regress/t/t_flag_j_hier.py b/test_regress/t/t_flag_j_hier.py index bddf78458..989902a1d 100755 --- a/test_regress/t/t_flag_j_hier.py +++ b/test_regress/t/t_flag_j_hier.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(verilator_flags2=['--hierarchical -j --build-jobs 2']) diff --git a/test_regress/t/t_flag_main_sc_bad.py b/test_regress/t/t_flag_main_sc_bad.py index 8417c5915..e10e622f5 100755 --- a/test_regress/t/t_flag_main_sc_bad.py +++ b/test_regress/t/t_flag_main_sc_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(verilator_flags2=['--exe --build --main --sc'], fails=True, diff --git a/test_regress/t/t_flag_main_vpi_badentry.py b/test_regress/t/t_flag_main_vpi_badentry.py index 15398a3e5..9f211a8b1 100755 --- a/test_regress/t/t_flag_main_vpi_badentry.py +++ b/test_regress/t/t_flag_main_vpi_badentry.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False # A valid library loaded with a : entry that does not exist must # fail with a clear error (the missing-named-bootstrap branch of the loader). diff --git a/test_regress/t/t_flag_main_vpi_badlib.py b/test_regress/t/t_flag_main_vpi_badlib.py index 2ac211d49..ba6f30c77 100755 --- a/test_regress/t/t_flag_main_vpi_badlib.py +++ b/test_regress/t/t_flag_main_vpi_badlib.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False # +verilator+vpi+ pointing at a non-existent library must fail with a clear # error (the dlopen-failure branch of the runtime loader). diff --git a/test_regress/t/t_flag_main_vpi_noarray.py b/test_regress/t/t_flag_main_vpi_noarray.py index 9dd2ac853..4cd1336be 100755 --- a/test_regress/t/t_flag_main_vpi_noarray.py +++ b/test_regress/t/t_flag_main_vpi_noarray.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False # A library loaded with no : entry that lacks vlog_startup_routines # must fail with a clear error (the missing-array branch of the loader). diff --git a/test_regress/t/t_flag_make_cmake_sc.py b/test_regress/t/t_flag_make_cmake_sc.py index 3f9a83e6f..402f27f51 100755 --- a/test_regress/t/t_flag_make_cmake_sc.py +++ b/test_regress/t/t_flag_make_cmake_sc.py @@ -12,6 +12,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_make_gmake=False, verilator_make_cmake=True, verilator_flags2=["-sc"]) diff --git a/test_regress/t/t_flag_output_groups.py b/test_regress/t/t_flag_output_groups.py index 11316ac58..79463b8e0 100755 --- a/test_regress/t/t_flag_output_groups.py +++ b/test_regress/t/t_flag_output_groups.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.compile(verilator_flags2=["--output-groups", "2"]) diff --git a/test_regress/t/t_flag_prefix.py b/test_regress/t/t_flag_prefix.py index 08a786f04..494e4d9d2 100755 --- a/test_regress/t/t_flag_prefix.py +++ b/test_regress/t/t_flag_prefix.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile( verilator_flags2=[ diff --git a/test_regress/t/t_flag_structs_packed.py b/test_regress/t/t_flag_structs_packed.py index 3db2135f9..5297ab6e2 100755 --- a/test_regress/t/t_flag_structs_packed.py +++ b/test_regress/t/t_flag_structs_packed.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.compile(verilator_flags2=['-Wno-fatal', '--structs-packed'], expect_filename=test.golden_filename) diff --git a/test_regress/t/t_flag_x_assign_bad.py b/test_regress/t/t_flag_x_assign_bad.py index 02a6f1414..3e0a0bbfd 100755 --- a/test_regress/t/t_flag_x_assign_bad.py +++ b/test_regress/t/t_flag_x_assign_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(verilator_flags2=["--x-assign bad_one"], fails=True, diff --git a/test_regress/t/t_flag_x_initial_bad.py b/test_regress/t/t_flag_x_initial_bad.py index f5eb5d59f..0a96bc50f 100755 --- a/test_regress/t/t_flag_x_initial_bad.py +++ b/test_regress/t/t_flag_x_initial_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(verilator_flags2=["--x-initial bad_one"], fails=True, diff --git a/test_regress/t/t_flag_xinitial_0.py b/test_regress/t/t_flag_xinitial_0.py index 082f1d0ba..3b2e64aed 100755 --- a/test_regress/t/t_flag_xinitial_0.py +++ b/test_regress/t/t_flag_xinitial_0.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.compile(verilator_flags2=["--x-initial 0"]) diff --git a/test_regress/t/t_flag_xinitial_unique.py b/test_regress/t/t_flag_xinitial_unique.py index b9ca8f3e8..98257eab1 100755 --- a/test_regress/t/t_flag_xinitial_unique.py +++ b/test_regress/t/t_flag_xinitial_unique.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios("vlt_all") +test.fourstate_capable = False test.compile(verilator_flags2=["--x-initial unique"]) diff --git a/test_regress/t/t_for_assign.py b/test_regress/t/t_for_assign.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_for_assign.py +++ b/test_regress/t/t_for_assign.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_for_init_bug.py b/test_regress/t/t_for_init_bug.py index f8083269e..673bbd42b 100755 --- a/test_regress/t/t_for_init_bug.py +++ b/test_regress/t/t_for_init_bug.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_force.py b/test_regress/t/t_force.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_force.py +++ b/test_regress/t/t_force.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_force_assign.py b/test_regress/t/t_force_assign.py index fbf657b89..9ee68831e 100755 --- a/test_regress/t/t_force_assign.py +++ b/test_regress/t/t_force_assign.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=["--timing", "-Wno-IEEEMAYDEPRECATE"]) diff --git a/test_regress/t/t_force_assign_comb.py b/test_regress/t/t_force_assign_comb.py index 64141e405..3e2e75bee 100755 --- a/test_regress/t/t_force_assign_comb.py +++ b/test_regress/t/t_force_assign_comb.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=["--timing", "-Wno-IEEEMAYDEPRECATE"]) diff --git a/test_regress/t/t_force_chained.py b/test_regress/t/t_force_chained.py index 3c6aa8922..0a6d6f6fe 100755 --- a/test_regress/t/t_force_chained.py +++ b/test_regress/t/t_force_chained.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_force_complex_sel_unsup.py b/test_regress/t/t_force_complex_sel_unsup.py index 382ad0d44..3b5ec369f 100755 --- a/test_regress/t/t_force_complex_sel_unsup.py +++ b/test_regress/t/t_force_complex_sel_unsup.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_force_forceable_rhs_ref.py b/test_regress/t/t_force_forceable_rhs_ref.py index 8a938befd..a10e2547d 100755 --- a/test_regress/t/t_force_forceable_rhs_ref.py +++ b/test_regress/t/t_force_forceable_rhs_ref.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_force_immediate_release.py b/test_regress/t/t_force_immediate_release.py index 3c6aa8922..0a6d6f6fe 100755 --- a/test_regress/t/t_force_immediate_release.py +++ b/test_regress/t/t_force_immediate_release.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_force_initial.py b/test_regress/t/t_force_initial.py index 3c6aa8922..0a6d6f6fe 100755 --- a/test_regress/t/t_force_initial.py +++ b/test_regress/t/t_force_initial.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_force_mid.py b/test_regress/t/t_force_mid.py index b6662862a..0b2328993 100755 --- a/test_regress/t/t_force_mid.py +++ b/test_regress/t/t_force_mid.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) diff --git a/test_regress/t/t_force_nested_struct2.py b/test_regress/t/t_force_nested_struct2.py index c03142385..1727107ae 100755 --- a/test_regress/t/t_force_nested_struct2.py +++ b/test_regress/t/t_force_nested_struct2.py @@ -11,6 +11,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_force_release.py b/test_regress/t/t_force_release.py index 31b1f0e53..9da272f7d 100755 --- a/test_regress/t/t_force_release.py +++ b/test_regress/t/t_force_release.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_force_release_net.py b/test_regress/t/t_force_release_net.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_force_release_net.py +++ b/test_regress/t/t_force_release_net.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_force_release_net_reverse.py b/test_regress/t/t_force_release_net_reverse.py index e45d4e931..7eb660120 100755 --- a/test_regress/t/t_force_release_net_reverse.py +++ b/test_regress/t/t_force_release_net_reverse.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_force_release_net.v" test.compile(verilator_flags2=['+define+REVERSE']) diff --git a/test_regress/t/t_force_release_net_trace.py b/test_regress/t/t_force_release_net_trace.py index a26f72174..9d36c1e3c 100755 --- a/test_regress/t/t_force_release_net_trace.py +++ b/test_regress/t/t_force_release_net_trace.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_force_release_net.v" test.compile(verilator_flags2=['--trace-vcd']) diff --git a/test_regress/t/t_force_release_var.py b/test_regress/t/t_force_release_var.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_force_release_var.py +++ b/test_regress/t/t_force_release_var.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_force_release_var_reverse.py b/test_regress/t/t_force_release_var_reverse.py index d947b7f75..1f5eee617 100755 --- a/test_regress/t/t_force_release_var_reverse.py +++ b/test_regress/t/t_force_release_var_reverse.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_force_release_var.v" test.compile(verilator_flags2=['+define+REVERSE']) diff --git a/test_regress/t/t_force_release_var_trace.py b/test_regress/t/t_force_release_var_trace.py index 7d61c1978..9692aac4e 100755 --- a/test_regress/t/t_force_release_var_trace.py +++ b/test_regress/t/t_force_release_var_trace.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_force_release_var.v" test.compile(verilator_flags2=['--trace-vcd']) diff --git a/test_regress/t/t_force_rhs_ref.py b/test_regress/t/t_force_rhs_ref.py index 3c6aa8922..0a6d6f6fe 100755 --- a/test_regress/t/t_force_rhs_ref.py +++ b/test_regress/t/t_force_rhs_ref.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_force_rhs_ref_multiple.py b/test_regress/t/t_force_rhs_ref_multiple.py index 3c6aa8922..0a6d6f6fe 100755 --- a/test_regress/t/t_force_rhs_ref_multiple.py +++ b/test_regress/t/t_force_rhs_ref_multiple.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_force_struct_partial.py b/test_regress/t/t_force_struct_partial.py index 84b274f68..17424b42f 100755 --- a/test_regress/t/t_force_struct_partial.py +++ b/test_regress/t/t_force_struct_partial.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_force_struct_trace.py b/test_regress/t/t_force_struct_trace.py index 2089dade6..fceb1c686 100755 --- a/test_regress/t/t_force_struct_trace.py +++ b/test_regress/t/t_force_struct_trace.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--trace"]) diff --git a/test_regress/t/t_force_subnet.py b/test_regress/t/t_force_subnet.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_force_subnet.py +++ b/test_regress/t/t_force_subnet.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_force_tri.py b/test_regress/t/t_force_tri.py index 1952b53a1..873d22c46 100755 --- a/test_regress/t/t_force_tri.py +++ b/test_regress/t/t_force_tri.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_force_unpacked.py b/test_regress/t/t_force_unpacked.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_force_unpacked.py +++ b/test_regress/t/t_force_unpacked.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_force_unpacked_bitsel.py b/test_regress/t/t_force_unpacked_bitsel.py index 8a938befd..a10e2547d 100755 --- a/test_regress/t/t_force_unpacked_bitsel.py +++ b/test_regress/t/t_force_unpacked_bitsel.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_force_wide_sel.py b/test_regress/t/t_force_wide_sel.py index 19ed22916..76ddb710e 100755 --- a/test_regress/t/t_force_wide_sel.py +++ b/test_regress/t/t_force_wide_sel.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--stats"]) diff --git a/test_regress/t/t_forceable_net_cmt.py b/test_regress/t/t_forceable_net_cmt.py index 6af4a2030..42076ba6e 100755 --- a/test_regress/t/t_forceable_net_cmt.py +++ b/test_regress/t/t_forceable_net_cmt.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.pli_filename = "t/t_forceable_net.cpp" test.top_filename = "t/t_forceable_net.v" diff --git a/test_regress/t/t_forceable_net_cmt_trace.py b/test_regress/t/t_forceable_net_cmt_trace.py index 4a6c4e73a..6b97c3eb1 100755 --- a/test_regress/t/t_forceable_net_cmt_trace.py +++ b/test_regress/t/t_forceable_net_cmt_trace.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.pli_filename = "t/t_forceable_net.cpp" test.top_filename = "t/t_forceable_net.v" test.golden_filename = "t/t_forceable_net_trace.vcd.out" diff --git a/test_regress/t/t_forceable_net_vlt.py b/test_regress/t/t_forceable_net_vlt.py index 6d2340766..bb55667e4 100755 --- a/test_regress/t/t_forceable_net_vlt.py +++ b/test_regress/t/t_forceable_net_vlt.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.pli_filename = "t/t_forceable_net.cpp" test.top_filename = "t/t_forceable_net.v" diff --git a/test_regress/t/t_forceable_net_vlt_trace.py b/test_regress/t/t_forceable_net_vlt_trace.py index 2dbbaadd9..c7cad6ddd 100755 --- a/test_regress/t/t_forceable_net_vlt_trace.py +++ b/test_regress/t/t_forceable_net_vlt_trace.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.pli_filename = "t/t_forceable_net.cpp" test.top_filename = "t/t_forceable_net.v" test.golden_filename = "t/t_forceable_net_trace.vcd.out" diff --git a/test_regress/t/t_forceable_unpacked_bad.py b/test_regress/t/t_forceable_unpacked_bad.py index 4cebd5d8e..e6bb34c89 100755 --- a/test_regress/t/t_forceable_unpacked_bad.py +++ b/test_regress/t/t_forceable_unpacked_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_forceable_unpacked_cmt.py b/test_regress/t/t_forceable_unpacked_cmt.py index ca1b5e9ab..9bd698d26 100755 --- a/test_regress/t/t_forceable_unpacked_cmt.py +++ b/test_regress/t/t_forceable_unpacked_cmt.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.pli_filename = "t/t_forceable_unpacked.cpp" test.top_filename = "t/t_forceable_unpacked.v" diff --git a/test_regress/t/t_forceable_unpacked_vlt.py b/test_regress/t/t_forceable_unpacked_vlt.py index cf436261d..c04c624a5 100755 --- a/test_regress/t/t_forceable_unpacked_vlt.py +++ b/test_regress/t/t_forceable_unpacked_vlt.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.pli_filename = "t/t_forceable_unpacked.cpp" test.top_filename = "t/t_forceable_unpacked.v" diff --git a/test_regress/t/t_forceable_var_cmt.py b/test_regress/t/t_forceable_var_cmt.py index 260ae98f4..dd250a0fe 100755 --- a/test_regress/t/t_forceable_var_cmt.py +++ b/test_regress/t/t_forceable_var_cmt.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.pli_filename = "t/t_forceable_var.cpp" test.top_filename = "t/t_forceable_var.v" diff --git a/test_regress/t/t_forceable_var_cmt_trace.py b/test_regress/t/t_forceable_var_cmt_trace.py index a551105de..96cd84b20 100755 --- a/test_regress/t/t_forceable_var_cmt_trace.py +++ b/test_regress/t/t_forceable_var_cmt_trace.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.pli_filename = "t/t_forceable_var.cpp" test.top_filename = "t/t_forceable_var.v" test.golden_filename = "t/t_forceable_var_trace.vcd.out" diff --git a/test_regress/t/t_forceable_var_vlt.py b/test_regress/t/t_forceable_var_vlt.py index db3e6fb03..512a68df6 100755 --- a/test_regress/t/t_forceable_var_vlt.py +++ b/test_regress/t/t_forceable_var_vlt.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.pli_filename = "t/t_forceable_var.cpp" test.top_filename = "t/t_forceable_var.v" diff --git a/test_regress/t/t_forceable_var_vlt_trace.py b/test_regress/t/t_forceable_var_vlt_trace.py index 1ae5dec46..0982cc0b7 100755 --- a/test_regress/t/t_forceable_var_vlt_trace.py +++ b/test_regress/t/t_forceable_var_vlt_trace.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.pli_filename = "t/t_forceable_var.cpp" test.top_filename = "t/t_forceable_var.v" test.golden_filename = "t/t_forceable_var_trace.vcd.out" diff --git a/test_regress/t/t_foreach.py b/test_regress/t/t_foreach.py index 6a5a6175f..b0021a99b 100755 --- a/test_regress/t/t_foreach.py +++ b/test_regress/t/t_foreach.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--assert']) diff --git a/test_regress/t/t_foreach_array.py b/test_regress/t/t_foreach_array.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_foreach_array.py +++ b/test_regress/t/t_foreach_array.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_foreach_class.py b/test_regress/t/t_foreach_class.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_foreach_class.py +++ b/test_regress/t/t_foreach_class.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_foreach_const.py b/test_regress/t/t_foreach_const.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_foreach_const.py +++ b/test_regress/t/t_foreach_const.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_foreach_delete.py b/test_regress/t/t_foreach_delete.py index cf9cbcb93..0aee7445c 100755 --- a/test_regress/t/t_foreach_delete.py +++ b/test_regress/t/t_foreach_delete.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator_st') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_foreach_noivar.py b/test_regress/t/t_foreach_noivar.py index 865433d95..a9abbfda1 100755 --- a/test_regress/t/t_foreach_noivar.py +++ b/test_regress/t/t_foreach_noivar.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['-Wno-NOEFFECT']) diff --git a/test_regress/t/t_foreach_noivar_bad.py b/test_regress/t/t_foreach_noivar_bad.py index cfc73a4a4..64e86b358 100755 --- a/test_regress/t/t_foreach_noivar_bad.py +++ b/test_regress/t/t_foreach_noivar_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = 't/t_foreach_noivar.v' test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_foreach_sideeff_uvm.py b/test_regress/t/t_foreach_sideeff_uvm.py index 78ebab213..5b8e5a4a1 100755 --- a/test_regress/t/t_foreach_sideeff_uvm.py +++ b/test_regress/t/t_foreach_sideeff_uvm.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator_st') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_fork_dynscope_interface.py b/test_regress/t/t_fork_dynscope_interface.py index 6ed2bc5c7..9d4a4f59b 100755 --- a/test_regress/t/t_fork_dynscope_interface.py +++ b/test_regress/t/t_fork_dynscope_interface.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary --trace-fst']) diff --git a/test_regress/t/t_fork_dynscope_out.py b/test_regress/t/t_fork_dynscope_out.py index 7ded63f3a..d210ebd50 100755 --- a/test_regress/t/t_fork_dynscope_out.py +++ b/test_regress/t/t_fork_dynscope_out.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_fork_join_none_capture.py b/test_regress/t/t_fork_join_none_capture.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_fork_join_none_capture.py +++ b/test_regress/t/t_fork_join_none_capture.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_fork_join_none_nested_triggered.py b/test_regress/t/t_fork_join_none_nested_triggered.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_fork_join_none_nested_triggered.py +++ b/test_regress/t/t_fork_join_none_nested_triggered.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_fork_none_var.py b/test_regress/t/t_fork_none_var.py index 7ded63f3a..d210ebd50 100755 --- a/test_regress/t/t_fork_none_var.py +++ b/test_regress/t/t_fork_none_var.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_fourstate_arithmetics.py b/test_regress/t/t_fourstate_arithmetics.py new file mode 100755 index 000000000..5a1741a85 --- /dev/null +++ b/test_regress/t/t_fourstate_arithmetics.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.twostate_capable = False + +test.compile(verilator_flags2=['--binary']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fourstate_arithmetics.v b/test_regress/t/t_fourstate_arithmetics.v new file mode 100644 index 000000000..ff18744d3 --- /dev/null +++ b/test_regress/t/t_fourstate_arithmetics.v @@ -0,0 +1,84 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +`ifdef VERILATOR +`define IMPURE_ONE ($c(1)) +`else +`define IMPURE_ONE (|($random | $random)) +`endif + +module t; + function integer f(integer x); + if (`IMPURE_ONE) return x; + return 'x; + endfunction + function logic [31:0] g(logic [31:0] x); + if (`IMPURE_ONE) return x; + return 'x; + endfunction + + initial begin + if ((f(10) + f(-5)) !== 5) $stop; + if ((f(10) + f('b11x)) !== 'x) $stop; + if ((f(10) + f('b11z)) !== 'x) $stop; + if ((g(10) + g(5)) !== 15) $stop; + if ((g(10) + g('x)) !== 'x) $stop; + + if ((f(10) - f(-5)) !== 15) $stop; + if ((f(10) - f('b11x)) !== 'x) $stop; + if ((f(10) - f('b11z)) !== 'x) $stop; + if ((g(10) - g(5)) !== 5) $stop; + if ((g(10) - g('x)) !== 'x) $stop; + + if ((f(10) * f(-5)) !== -50) $stop; + if ((f(10) * f('b11x)) !== 'x) $stop; + if ((f(10) * f('b11z)) !== 'x) $stop; + if ((g(10) * g(5)) !== 50) $stop; + if ((g(10) * g('x)) !== 'x) $stop; + + if ((f(10) / f(5)) !== 2) $stop; + if ((f(9) / f(5)) !== 1) $stop; + if ((f(10) / f(2)) !== 5) $stop; + if ((f(-10) / f(5)) !== -2) $stop; + if ((f(9) / f(-5)) !== -1) $stop; + if ((f('bx) / f('bx)) !== 'x) $stop; + if ((f('bz) / f(5)) !== 'x) $stop; + if ((f(10) / f(0)) !== 'x) $stop; + if ((f(0) / f(0)) !== 'x) $stop; + if ((f(0) / f('z)) !== 'x) $stop; + + if ((g(10) / g(5)) !== 2) $stop; + if ((g(9) / g(5)) !== 1) $stop; + if ((g(10) / g(2)) !== 5) $stop; + if ((g('bx) / g('bx)) !== 'x) $stop; + if ((g('bz) / g(5)) !== 'x) $stop; + if ((g(10) / g(0)) !== 'x) $stop; + if ((g(0) / g(0)) !== 'x) $stop; + if ((g(0) / g('z)) !== 'x) $stop; + + if ((f(10) % f(5)) !== 0) $stop; + if ((f(9) % f(5)) !== 4) $stop; + if ((f(10) % f(2)) !== 0) $stop; + if ((f(-10) % f(5)) !== 0) $stop; + if ((f(9) % f(-5)) !== 4) $stop; + if ((f('bx) % f('bx)) !== 'x) $stop; + if ((f('bz) % f(5)) !== 'x) $stop; + if ((f(10) % f(0)) !== 'x) $stop; + if ((f(0) % f(0)) !== 'x) $stop; + if ((f(0) % f('z)) !== 'x) $stop; + + if ((g(10) % g(5)) !== 0) $stop; + if ((g(9) % g(5)) !== 4) $stop; + if ((g(10) % g(2)) !== 0) $stop; + if ((g('bx) % g('bx)) !== 'x) $stop; + if ((g('bz) % g(5)) !== 'x) $stop; + if ((g(10) % g(0)) !== 'x) $stop; + if ((g(0) % g(0)) !== 'x) $stop; + if ((g(0) % g('z)) !== 'x) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_fourstate_assign.py b/test_regress/t/t_fourstate_assign.py index 8a938befd..0aee7445c 100755 --- a/test_regress/t/t_fourstate_assign.py +++ b/test_regress/t/t_fourstate_assign.py @@ -9,7 +9,8 @@ import vltest_bootstrap -test.scenarios('simulator') +test.scenarios('simulator_st') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_fourstate_assign_complex_lhs_unsup.out b/test_regress/t/t_fourstate_assign_complex_lhs_unsup.out new file mode 100644 index 000000000..3eac819dc --- /dev/null +++ b/test_regress/t/t_fourstate_assign_complex_lhs_unsup.out @@ -0,0 +1,6 @@ +%Error-UNSUPPORTED: t/t_fourstate_assign_complex_lhs_unsup.v:10:10: Fourstate LHS other than a simple variable reference is not supported + : ... note: In instance 't' + 10 | x[1] = 1; + | ^ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error: Exiting due to diff --git a/test_regress/t/t_fourstate_assign_complex_lhs_unsup.py b/test_regress/t/t_fourstate_assign_complex_lhs_unsup.py new file mode 100755 index 000000000..578fc7b99 --- /dev/null +++ b/test_regress/t/t_fourstate_assign_complex_lhs_unsup.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.twostate_capable = False + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fourstate_assign_complex_lhs_unsup.v b/test_regress/t/t_fourstate_assign_complex_lhs_unsup.v new file mode 100644 index 000000000..63129c67c --- /dev/null +++ b/test_regress/t/t_fourstate_assign_complex_lhs_unsup.v @@ -0,0 +1,12 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +module t; + initial begin + static logic [2:0] x; + x[1] = 1; + end +endmodule diff --git a/test_regress/t/t_fourstate_case_onehot_unsup.out b/test_regress/t/t_fourstate_case_onehot_unsup.out new file mode 100644 index 000000000..676e33e70 --- /dev/null +++ b/test_regress/t/t_fourstate_case_onehot_unsup.out @@ -0,0 +1,20 @@ +%Error-UNSUPPORTED: t/t_case_onehot.v:88:15: Four-state case items values are unsupported with --fourstate + : ... note: In instance 't.test' + 88 | in[ST_0]: out <= 32'h1234; + | ^ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error-UNSUPPORTED: t/t_case_onehot.v:89:15: Four-state case items values are unsupported with --fourstate + : ... note: In instance 't.test' + 89 | in[ST_1]: out <= 32'h4356; + | ^ +%Error-UNSUPPORTED: t/t_case_onehot.v:90:15: Four-state case items values are unsupported with --fourstate + : ... note: In instance 't.test' + 90 | in[ST_2]: out <= 32'h9874; + | ^ +%Error-UNSUPPORTED: t/t_case_onehot.v:87:5: Unsupported: Operator ONEHOT not supported in the four-state mode + 87 | case (1'b1) /*verilator parallel_case*/ + | ^~~~ +%Error-UNSUPPORTED: t/t_case_onehot.v:87:5: Unsupported: Operator LOGNOT not supported in the four-state mode + 87 | case (1'b1) /*verilator parallel_case*/ + | ^~~~ +%Error: Exiting due to diff --git a/test_regress/t/t_fourstate_case_onehot_unsup.py b/test_regress/t/t_fourstate_case_onehot_unsup.py new file mode 100755 index 000000000..4fbd47fc4 --- /dev/null +++ b/test_regress/t/t_fourstate_case_onehot_unsup.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.twostate_capable = False + +test.top_filename = 't/t_case_onehot.v' + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fourstate_casex_unsup.out b/test_regress/t/t_fourstate_casex_unsup.out new file mode 100644 index 000000000..c6e77dd43 --- /dev/null +++ b/test_regress/t/t_fourstate_casex_unsup.out @@ -0,0 +1,82 @@ +%Error-UNSUPPORTED: t/t_case_x.v:21:5: All case statements with four-state value as an expression are unsupported with --fourstate + : ... note: In instance 't' + 21 | case (value) + | ^~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error-UNSUPPORTED: t/t_case_x.v:22:14: Four-state case items values are unsupported with --fourstate + : ... note: In instance 't' + 22 | 4'b1xxx: $stop; + | ^ +%Error-UNSUPPORTED: t/t_case_x.v:23:14: Four-state case items values are unsupported with --fourstate + : ... note: In instance 't' + 23 | 4'b1???: $stop; + | ^ +%Error-UNSUPPORTED: t/t_case_x.v:27:5: All case statements with four-state value as an expression are unsupported with --fourstate + : ... note: In instance 't' + 27 | case (valuex) + | ^~~~ +%Error-UNSUPPORTED: t/t_case_x.v:28:14: Four-state case items values are unsupported with --fourstate + : ... note: In instance 't' + 28 | 4'b1???: $stop; + | ^ +%Error-UNSUPPORTED: t/t_case_x.v:29:14: Four-state case items values are unsupported with --fourstate + : ... note: In instance 't' + 29 | 4'b1xxx: ; + | ^ +%Error-UNSUPPORTED: t/t_case_x.v:35:5: All case statements with four-state value as an expression are unsupported with --fourstate + : ... note: In instance 't' + 35 | casex (value) + | ^~~~~ +%Error-UNSUPPORTED: t/t_case_x.v:36:14: Four-state case items values are unsupported with --fourstate + : ... note: In instance 't' + 36 | 4'b100x: ; + | ^ +%Error-UNSUPPORTED: t/t_case_x.v:39:5: All case statements with four-state value as an expression are unsupported with --fourstate + : ... note: In instance 't' + 39 | casex (value) + | ^~~~~ +%Error-UNSUPPORTED: t/t_case_x.v:40:14: Four-state case items values are unsupported with --fourstate + : ... note: In instance 't' + 40 | 4'b100?: ; + | ^ +%Error-UNSUPPORTED: t/t_case_x.v:43:5: All case statements with four-state value as an expression are unsupported with --fourstate + : ... note: In instance 't' + 43 | casex (valuex) + | ^~~~~ +%Error-UNSUPPORTED: t/t_case_x.v:44:14: Four-state case items values are unsupported with --fourstate + : ... note: In instance 't' + 44 | 4'b100x: ; + | ^ +%Error-UNSUPPORTED: t/t_case_x.v:47:5: All case statements with four-state value as an expression are unsupported with --fourstate + : ... note: In instance 't' + 47 | casex (valuex) + | ^~~~~ +%Error-UNSUPPORTED: t/t_case_x.v:48:14: Four-state case items values are unsupported with --fourstate + : ... note: In instance 't' + 48 | 4'b100?: ; + | ^ +%Error-UNSUPPORTED: t/t_case_x.v:52:5: All case statements with four-state value as an expression are unsupported with --fourstate + : ... note: In instance 't' + 52 | casez (value) + | ^~~~~ +%Error-UNSUPPORTED: t/t_case_x.v:53:14: Four-state case items values are unsupported with --fourstate + : ... note: In instance 't' + 53 | 4'bxxxx: $stop; + | ^ +%Error-UNSUPPORTED: t/t_case_x.v:54:14: Four-state case items values are unsupported with --fourstate + : ... note: In instance 't' + 54 | 4'b100?: ; + | ^ +%Error-UNSUPPORTED: t/t_case_x.v:57:5: All case statements with four-state value as an expression are unsupported with --fourstate + : ... note: In instance 't' + 57 | casez (valuex) + | ^~~~~ +%Error-UNSUPPORTED: t/t_case_x.v:58:14: Four-state case items values are unsupported with --fourstate + : ... note: In instance 't' + 58 | 4'b1xx?: ; + | ^ +%Error-UNSUPPORTED: t/t_case_x.v:59:14: Four-state case items values are unsupported with --fourstate + : ... note: In instance 't' + 59 | 4'b100?: ; + | ^ +%Error: Exiting due to diff --git a/test_regress/t/t_fourstate_casex_unsup.py b/test_regress/t/t_fourstate_casex_unsup.py new file mode 100755 index 000000000..4fe995f37 --- /dev/null +++ b/test_regress/t/t_fourstate_casex_unsup.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.twostate_capable = False + +test.top_filename = "t/t_case_x.v" + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fourstate_cast.py b/test_regress/t/t_fourstate_cast.py new file mode 100755 index 000000000..5a1741a85 --- /dev/null +++ b/test_regress/t/t_fourstate_cast.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.twostate_capable = False + +test.compile(verilator_flags2=['--binary']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fourstate_cast.v b/test_regress/t/t_fourstate_cast.v new file mode 100644 index 000000000..c4891344f --- /dev/null +++ b/test_regress/t/t_fourstate_cast.v @@ -0,0 +1,16 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +module t; + initial begin + static int n = 12; + static integer m = 'x; + static int v = 1 + int'(1 + (n + m)); + if (v != 1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_fourstate_comparison.py b/test_regress/t/t_fourstate_comparison.py new file mode 100755 index 000000000..5a1741a85 --- /dev/null +++ b/test_regress/t/t_fourstate_comparison.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.twostate_capable = False + +test.compile(verilator_flags2=['--binary']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fourstate_comparison.v b/test_regress/t/t_fourstate_comparison.v new file mode 100644 index 000000000..6e728ed84 --- /dev/null +++ b/test_regress/t/t_fourstate_comparison.v @@ -0,0 +1,157 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +`ifdef VERILATOR +`define IMPURE_ONE ($c(1)) +`else +`define IMPURE_ONE (|($random | $random)) +`endif + +module t; + function integer f(integer x); + if (`IMPURE_ONE) return x; + return 'x; + endfunction + function logic [31:0] g(logic [31:0] x); + if (`IMPURE_ONE) return x; + return 'x; + endfunction + + initial begin + if ((f('b1) == f('b1)) !== 1'b1) $stop; + if ((f('b1) == f('b0)) !== 1'b0) $stop; + if ((f('b0) == f('b0)) !== 1'b1) $stop; + if ((f('b0) == f('b1)) !== 1'b0) $stop; + if ((f('b0) == f('bx)) !== 1'bx) $stop; + if ((f('b0) == f('bx)) !== 1'bx) $stop; + if ((f('b1) == f('bx)) !== 1'bx) $stop; + if ((f('bx) == f('bx)) !== 1'bx) $stop; + if ((f('bx) == f('bz)) !== 1'bx) $stop; + if ((f('bz) == f('bz)) !== 1'bx) $stop; + if ((f('bz) == f('b1)) !== 1'bx) $stop; + if ((f('bz) == f('b0)) !== 1'bx) $stop; + + if ((f('b1) != f('b1)) !== 1'b0) $stop; + if ((f('b1) != f('b0)) !== 1'b1) $stop; + if ((f('b0) != f('b0)) !== 1'b0) $stop; + if ((f('b0) != f('b1)) !== 1'b1) $stop; + if ((f('b0) != f('bx)) !== 1'bx) $stop; + if ((f('b0) != f('bx)) !== 1'bx) $stop; + if ((f('b1) != f('bx)) !== 1'bx) $stop; + if ((f('bx) != f('bx)) !== 1'bx) $stop; + if ((f('bx) != f('bz)) !== 1'bx) $stop; + if ((f('bz) != f('bz)) !== 1'bx) $stop; + if ((f('bz) != f('b1)) !== 1'bx) $stop; + if ((f('bz) != f('b0)) !== 1'bx) $stop; + + if ((f('b1) < f('b1)) !== 1'b0) $stop; + if ((f('b1) < f('b0)) !== 1'b0) $stop; + if ((f('b0) < f('b0)) !== 1'b0) $stop; + if ((f('b0) < f('b1)) !== 1'b1) $stop; + if ((f('b0) < f('bx)) !== 1'bx) $stop; + if ((f('b0) < f('bx)) !== 1'bx) $stop; + if ((f('b1) < f('bx)) !== 1'bx) $stop; + if ((f('bx) < f('bx)) !== 1'bx) $stop; + if ((f('bx) < f('bz)) !== 1'bx) $stop; + if ((f('bz) < f('bz)) !== 1'bx) $stop; + if ((f('bz) < f('b1)) !== 1'bx) $stop; + if ((f('bz) < f('b0)) !== 1'bx) $stop; + + if ((f('b1) <= f('b1)) !== 1'b1) $stop; + if ((f('b1) <= f('b0)) !== 1'b0) $stop; + if ((f('b0) <= f('b0)) !== 1'b1) $stop; + if ((f('b0) <= f('b1)) !== 1'b1) $stop; + if ((f('b0) <= f('bx)) !== 1'bx) $stop; + if ((f('b0) <= f('bx)) !== 1'bx) $stop; + if ((f('b1) <= f('bx)) !== 1'bx) $stop; + if ((f('bx) <= f('bx)) !== 1'bx) $stop; + if ((f('bx) <= f('bz)) !== 1'bx) $stop; + if ((f('bz) <= f('bz)) !== 1'bx) $stop; + if ((f('bz) <= f('b1)) !== 1'bx) $stop; + if ((f('bz) <= f('b0)) !== 1'bx) $stop; + + if ((f('b1) > f('b1)) !== 1'b0) $stop; + if ((f('b1) > f('b0)) !== 1'b1) $stop; + if ((f('b0) > f('b0)) !== 1'b0) $stop; + if ((f('b0) > f('b1)) !== 1'b0) $stop; + if ((f('b0) > f('bx)) !== 1'bx) $stop; + if ((f('b0) > f('bx)) !== 1'bx) $stop; + if ((f('b1) > f('bx)) !== 1'bx) $stop; + if ((f('bx) > f('bx)) !== 1'bx) $stop; + if ((f('bx) > f('bz)) !== 1'bx) $stop; + if ((f('bz) > f('bz)) !== 1'bx) $stop; + if ((f('bz) > f('b1)) !== 1'bx) $stop; + if ((f('bz) > f('b0)) !== 1'bx) $stop; + + if ((f('b1) >= f('b1)) !== 1'b1) $stop; + if ((f('b1) >= f('b0)) !== 1'b1) $stop; + if ((f('b0) >= f('b0)) !== 1'b1) $stop; + if ((f('b0) >= f('b1)) !== 1'b0) $stop; + if ((f('b0) >= f('bx)) !== 1'bx) $stop; + if ((f('b0) >= f('bx)) !== 1'bx) $stop; + if ((f('b1) >= f('bx)) !== 1'bx) $stop; + if ((f('bx) >= f('bx)) !== 1'bx) $stop; + if ((f('bx) >= f('bz)) !== 1'bx) $stop; + if ((f('bz) >= f('bz)) !== 1'bx) $stop; + if ((f('bz) >= f('b1)) !== 1'bx) $stop; + if ((f('bz) >= f('b0)) !== 1'bx) $stop; + + // Unsigned + if ((g('b1) < g('b1)) !== 1'b0) $stop; + if ((g('b1) < g('b0)) !== 1'b0) $stop; + if ((g('b0) < g('b0)) !== 1'b0) $stop; + if ((g('b0) < g('b1)) !== 1'b1) $stop; + if ((g('b0) < g('bx)) !== 1'bx) $stop; + if ((g('b0) < g('bx)) !== 1'bx) $stop; + if ((g('b1) < g('bx)) !== 1'bx) $stop; + if ((g('bx) < g('bx)) !== 1'bx) $stop; + if ((g('bx) < g('bz)) !== 1'bx) $stop; + if ((g('bz) < g('bz)) !== 1'bx) $stop; + if ((g('bz) < g('b1)) !== 1'bx) $stop; + if ((g('bz) < g('b0)) !== 1'bx) $stop; + + if ((g('b1) <= g('b1)) !== 1'b1) $stop; + if ((g('b1) <= g('b0)) !== 1'b0) $stop; + if ((g('b0) <= g('b0)) !== 1'b1) $stop; + if ((g('b0) <= g('b1)) !== 1'b1) $stop; + if ((g('b0) <= g('bx)) !== 1'bx) $stop; + if ((g('b0) <= g('bx)) !== 1'bx) $stop; + if ((g('b1) <= g('bx)) !== 1'bx) $stop; + if ((g('bx) <= g('bx)) !== 1'bx) $stop; + if ((g('bx) <= g('bz)) !== 1'bx) $stop; + if ((g('bz) <= g('bz)) !== 1'bx) $stop; + if ((g('bz) <= g('b1)) !== 1'bx) $stop; + if ((g('bz) <= g('b0)) !== 1'bx) $stop; + + if ((g('b1) > g('b1)) !== 1'b0) $stop; + if ((g('b1) > g('b0)) !== 1'b1) $stop; + if ((g('b0) > g('b0)) !== 1'b0) $stop; + if ((g('b0) > g('b1)) !== 1'b0) $stop; + if ((g('b0) > g('bx)) !== 1'bx) $stop; + if ((g('b0) > g('bx)) !== 1'bx) $stop; + if ((g('b1) > g('bx)) !== 1'bx) $stop; + if ((g('bx) > g('bx)) !== 1'bx) $stop; + if ((g('bx) > g('bz)) !== 1'bx) $stop; + if ((g('bz) > g('bz)) !== 1'bx) $stop; + if ((g('bz) > g('b1)) !== 1'bx) $stop; + if ((g('bz) > g('b0)) !== 1'bx) $stop; + + if ((g('b1) >= g('b1)) !== 1'b1) $stop; + if ((g('b1) >= g('b0)) !== 1'b1) $stop; + if ((g('b0) >= g('b0)) !== 1'b1) $stop; + if ((g('b0) >= g('b1)) !== 1'b0) $stop; + if ((g('b0) >= g('bx)) !== 1'bx) $stop; + if ((g('b0) >= g('bx)) !== 1'bx) $stop; + if ((g('b1) >= g('bx)) !== 1'bx) $stop; + if ((g('bx) >= g('bx)) !== 1'bx) $stop; + if ((g('bx) >= g('bz)) !== 1'bx) $stop; + if ((g('bz) >= g('bz)) !== 1'bx) $stop; + if ((g('bz) >= g('b1)) !== 1'bx) $stop; + if ((g('bz) >= g('b0)) !== 1'bx) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_fourstate_complex_expr.out b/test_regress/t/t_fourstate_complex_expr.out new file mode 100644 index 000000000..4f5f5e20e --- /dev/null +++ b/test_regress/t/t_fourstate_complex_expr.out @@ -0,0 +1,15 @@ +1 +1 +x +1 +0 +1 +x +0 +0 +x +0 +0 +z +0 +*-* All Finished *-* diff --git a/test_regress/t/t_fourstate_complex_expr.py b/test_regress/t/t_fourstate_complex_expr.py new file mode 100755 index 000000000..3fbfaf389 --- /dev/null +++ b/test_regress/t/t_fourstate_complex_expr.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.twostate_capable = False + +test.compile(verilator_flags2=['--binary']) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fourstate_complex_expr.v b/test_regress/t/t_fourstate_complex_expr.v new file mode 100644 index 000000000..14c912db1 --- /dev/null +++ b/test_regress/t/t_fourstate_complex_expr.v @@ -0,0 +1,29 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +module t; + function logic f(logic a); + if (a === 1'b1) $write("1"); + else if (a === 1'b0) $write("0"); + else if (a === 1'bx) $write("x"); + else if (a === 1'bz) $write("z"); + else $stop; + $write("\n"); + return a; + endfunction + + initial begin + if (( + ((f(1) ? f(1) : f('z)) && (f('x) ? f(1) : f(0))) ? + (((f(1) || f('z)) && (f('x))) && ((f(0) ? f('x) : f(0)))) : + ((f('x) || f(0)) && (f(0) || (f('z) && (f(0) && f('z)))) + )) !== 0) begin + $stop; + end + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_fourstate_complex_pin_unsup.out b/test_regress/t/t_fourstate_complex_pin_unsup.out new file mode 100644 index 000000000..8af2a4815 --- /dev/null +++ b/test_regress/t/t_fourstate_complex_pin_unsup.out @@ -0,0 +1,6 @@ +%Error-UNSUPPORTED: t/t_fourstate_complex_pin_unsup.v:13:8: Cells with pins that are not a variable reference or a constant are not supported with --fourstate + : ... note: In instance 't' + 13 | y h(x[0]); + | ^ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error: Exiting due to diff --git a/test_regress/t/t_fourstate_complex_pin_unsup.py b/test_regress/t/t_fourstate_complex_pin_unsup.py new file mode 100755 index 000000000..578fc7b99 --- /dev/null +++ b/test_regress/t/t_fourstate_complex_pin_unsup.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.twostate_capable = False + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fourstate_complex_pin_unsup.v b/test_regress/t/t_fourstate_complex_pin_unsup.v new file mode 100644 index 000000000..6faf01111 --- /dev/null +++ b/test_regress/t/t_fourstate_complex_pin_unsup.v @@ -0,0 +1,15 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +module y(input x); + initial $write("%d\n", bit'(x)); +endmodule + +module t; + logic [2:0] x; + y h(x[0]); + initial x = 3; +endmodule diff --git a/test_regress/t/t_fourstate_concat.py b/test_regress/t/t_fourstate_concat.py new file mode 100755 index 000000000..5a1741a85 --- /dev/null +++ b/test_regress/t/t_fourstate_concat.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.twostate_capable = False + +test.compile(verilator_flags2=['--binary']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fourstate_concat.v b/test_regress/t/t_fourstate_concat.v new file mode 100644 index 000000000..bc1566282 --- /dev/null +++ b/test_regress/t/t_fourstate_concat.v @@ -0,0 +1,43 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +`ifdef VERILATOR +`define IMPURE_ONE ($c(1)) +`else +`define IMPURE_ONE (|($random | $random)) +`endif + +module t; + function logic f(logic x); + if (`IMPURE_ONE) return x; + return 'x; + endfunction + + initial begin + if ({f(1'b0), f(1'b0)} !== 2'b00) $stop; + if ({f(1'b0), f(1'b1)} !== 2'b01) $stop; + if ({f(1'b0), f(1'bx)} !== 2'b0x) $stop; + if ({f(1'b0), f(1'bz)} !== 2'b0z) $stop; + + if ({f(1'b1), f(1'b0)} !== 2'b10) $stop; + if ({f(1'b1), f(1'b1)} !== 2'b11) $stop; + if ({f(1'b1), f(1'bx)} !== 2'b1x) $stop; + if ({f(1'b1), f(1'bz)} !== 2'b1z) $stop; + + if ({f(1'bz), f(1'b0)} !== 2'bz0) $stop; + if ({f(1'bz), f(1'b1)} !== 2'bz1) $stop; + if ({f(1'bz), f(1'bx)} !== 2'bzx) $stop; + if ({f(1'bz), f(1'bz)} !== 2'bzz) $stop; + + if ({f(1'bx), f(1'b0)} !== 2'bx0) $stop; + if ({f(1'bx), f(1'b1)} !== 2'bx1) $stop; + if ({f(1'bx), f(1'bx)} !== 2'bxx) $stop; + if ({f(1'bx), f(1'bz)} !== 2'bxz) $stop; + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_fourstate_cond.out b/test_regress/t/t_fourstate_cond.out new file mode 100644 index 000000000..7d94b78b5 --- /dev/null +++ b/test_regress/t/t_fourstate_cond.out @@ -0,0 +1,17 @@ +0 +0 +1 +1 +x +1 +0 +x +1 +1 +z +1 +0 +z +0 +0 +*-* All Finished *-* diff --git a/test_regress/t/t_fourstate_cond.py b/test_regress/t/t_fourstate_cond.py new file mode 100755 index 000000000..3fbfaf389 --- /dev/null +++ b/test_regress/t/t_fourstate_cond.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.twostate_capable = False + +test.compile(verilator_flags2=['--binary']) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fourstate_cond.v b/test_regress/t/t_fourstate_cond.v new file mode 100644 index 000000000..8ad269fc0 --- /dev/null +++ b/test_regress/t/t_fourstate_cond.v @@ -0,0 +1,44 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +`ifdef VERILATOR +`define IMPURE_ONE ($c(1)) +`else +`define IMPURE_ONE (|($random | $random)) +`endif + +module t; + static int calls = 0; + + function logic f(logic a); + if (a === 1'b1) $write("1"); + else if (a === 1'b0) $write("0"); + else if (a === 1'bx) $write("x"); + else if (a === 1'bz) $write("z"); + else $stop; + $write("\n"); + return a; + endfunction + + + function logic bar(); + calls++; + return 'x; + endfunction + + initial begin + if ((f(0) ? f(1) : f(0)) !== 0) $stop; + if ((f(1) ? f(1) : f(0)) !== 1) $stop; + if ((f('x) ? f(1) : f(0)) !== 'x) $stop; + if ((f('x) ? f(1) : f(1)) !== 1) $stop; + if ((f('z) ? f(1) : f(0)) !== 'x) $stop; + if ((f('z) ? f(0) : f(0)) !== 0) $stop; + if ((`IMPURE_ONE ? 0 : bar()) !== 0) $stop; + if (calls !== 0) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_fourstate_delay_var_unsup.out b/test_regress/t/t_fourstate_delay_var_unsup.out new file mode 100644 index 000000000..de04dc395 --- /dev/null +++ b/test_regress/t/t_fourstate_delay_var_unsup.out @@ -0,0 +1,18 @@ +%Error-UNSUPPORTED: t/t_delay_var.v:14:8: Continuous assignment delays are unsupported with --fourstate + : ... note: In instance 't' + 14 | wire #1.1 d_const = in; + | ^ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error-UNSUPPORTED: t/t_delay_var.v:15:8: Continuous assignment delays are unsupported with --fourstate + : ... note: In instance 't' + 15 | wire #idly d_int = in; + | ^ +%Error-UNSUPPORTED: t/t_delay_var.v:16:8: Continuous assignment delays are unsupported with --fourstate + : ... note: In instance 't' + 16 | wire #rdly d_real = in; + | ^ +%Error-UNSUPPORTED: t/t_delay_var.v:17:8: Continuous assignment delays are unsupported with --fourstate + : ... note: In instance 't' + 17 | wire #PDLY d_param = in; + | ^ +%Error: Exiting due to diff --git a/test_regress/t/t_fourstate_delay_var_unsup.py b/test_regress/t/t_fourstate_delay_var_unsup.py new file mode 100755 index 000000000..3da6cb752 --- /dev/null +++ b/test_regress/t/t_fourstate_delay_var_unsup.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.twostate_capable = False + +test.top_filename = 't/t_delay_var.v' + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fourstate_demo.out b/test_regress/t/t_fourstate_demo.out new file mode 100644 index 000000000..88c01b13e --- /dev/null +++ b/test_regress/t/t_fourstate_demo.out @@ -0,0 +1,21 @@ +res: x +res: x +res: 1 +res: 1 +res: 0 + ZERO | ONE | X | Z +ZERO 0 ^ 0 == 0 | 0 ^ 1 == 1 | 0 ^ x == x | 0 ^ z == x | +ONE 1 ^ 0 == 1 | 1 ^ 1 == 0 | 1 ^ x == x | 1 ^ z == x | +X x ^ 0 == x | x ^ 1 == x | x ^ x == x | x ^ z == x | +Z z ^ 0 == x | z ^ 1 == x | z ^ x == x | z ^ z == x | +x wire: 1 +z wor: 1 +u triand: 1 +t wire: 1 +x wire: 1 +z wor: 1 +u triand: 1 +t wire: 1 +vvv: x +Bye +*-* All Finished *-* diff --git a/test_regress/t/t_fourstate_demo.out.vcd b/test_regress/t/t_fourstate_demo.out.vcd new file mode 100644 index 000000000..58ac28b80 --- /dev/null +++ b/test_regress/t/t_fourstate_demo.out.vcd @@ -0,0 +1,185 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module t $end + $var wire 1 C clk $end + $var wire 1 D x $end + $var wire 1 L y $end + $var wire 1 F t $end + $var wire 1 H u $end + $var wire 1 J z $end + $var wire 1 N z3 $end + $var wire 4 P z2 [3:0] $end + $var wire 1 R lost $end + $var wire 1 T open $end + $var wire 129 / xx [128:0] $end + $var wire 129 % xy [128:0] $end + $var wire 129 9 xz [128:0] $end + $var wire 1 V one $end + $var wire 1 W vvv $end + $scope module unnamedblk1 $end + $var wire 32 " n [31:0] $end + $var wire 32 # res [31:0] $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#1 +b00000000000000000000000000001100 " +b000000000000000000000000000011xx # +b101001100100110000001101101100101111011001001111100010101000110000000010101101011101011111000001101010001010101011010110010100001 % +b101001100100110000001101101100101111011001001111100010101000110000000010101101011101011111000001101010001010101011010110010100001 / +b101001100100110000001101101100101111011001001111100010101000110000000010101101011101011111000001101010001010101011010110010100001 9 +1C +1D +1F +1H +1J +zL +zN +bzzzz P +zR +zT +1V +xW +#5 +0C +0D +0F +0H +0J +#10 +bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx / +b010110011011001111110010010011010000100110110000011101010111001111111101010010100010100000111110010101110101010100101001101011110 9 +1C +1D +1F +1H +1J +#15 +0C +0D +0F +0H +0J +#20 +b101001100100110000001101101100101111011001001111100010101000110000000010101101011101011111000001101010001010101011010110010100001 / +b101001100100110000001101101100101111011001001111100010101000110000000010101101011101011111000001101010001010101011010110010100001 9 +1C +1D +1F +1H +1J +#25 +0C +0D +0F +0H +0J +#30 +bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx / +b010110011011001111110010010011010000100110110000011101010111001111111101010010100010100000111110010101110101010100101001101011110 9 +1C +1D +1F +1H +1J +#35 +0C +0D +0F +0H +0J +#40 +b101001100100110000001101101100101111011001001111100010101000110000000010101101011101011111000001101010001010101011010110010100001 / +b101001100100110000001101101100101111011001001111100010101000110000000010101101011101011111000001101010001010101011010110010100001 9 +1C +1D +1F +1H +1J +#45 +0C +0D +0F +0H +0J +#50 +bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx / +b010110011011001111110010010011010000100110110000011101010111001111111101010010100010100000111110010101110101010100101001101011110 9 +1C +1D +1F +1H +1J +#55 +0C +0D +0F +0H +0J +#60 +b101001100100110000001101101100101111011001001111100010101000110000000010101101011101011111000001101010001010101011010110010100001 / +b101001100100110000001101101100101111011001001111100010101000110000000010101101011101011111000001101010001010101011010110010100001 9 +1C +1D +1F +1H +1J +#65 +0C +0D +0F +0H +0J +#70 +bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx / +b010110011011001111110010010011010000100110110000011101010111001111111101010010100010100000111110010101110101010100101001101011110 9 +1C +1D +1F +1H +1J +#75 +0C +0D +0F +0H +0J +#80 +b101001100100110000001101101100101111011001001111100010101000110000000010101101011101011111000001101010001010101011010110010100001 / +b101001100100110000001101101100101111011001001111100010101000110000000010101101011101011111000001101010001010101011010110010100001 9 +1C +1D +1F +1H +1J +#85 +0C +0D +0F +0H +0J +#90 +bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx / +b010110011011001111110010010011010000100110110000011101010111001111111101010010100010100000111110010101110101010100101001101011110 9 +1C +1D +1F +1H +1J +#95 +0C +0D +0F +0H +0J +#100 +b101001100100110000001101101100101111011001001111100010101000110000000010101101011101011111000001101010001010101011010110010100001 / +b101001100100110000001101101100101111011001001111100010101000110000000010101101011101011111000001101010001010101011010110010100001 9 +1C +1D +1F +1H +1J +#102 diff --git a/test_regress/t/t_fourstate_demo.py b/test_regress/t/t_fourstate_demo.py new file mode 100755 index 000000000..fb46873a9 --- /dev/null +++ b/test_regress/t/t_fourstate_demo.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.twostate_capable = False + +test.compile(verilator_flags2=['--binary', '--trace-vcd']) + +test.execute(expect_filename=test.golden_filename) + +test.vcd_identical(test.trace_filename, test.golden_filename + '.vcd') + +test.passes() diff --git a/test_regress/t/t_fourstate_demo.v b/test_regress/t/t_fourstate_demo.v new file mode 100644 index 000000000..520b47576 --- /dev/null +++ b/test_regress/t/t_fourstate_demo.v @@ -0,0 +1,141 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +module t; + bit clk = 1; + wire x; + tri y; + wire t; + triand u; + wor z; + wor z3; + wor [3:0] z2; + wire lost; + wire open = 'z; + assign x = clk; + assign z = x; + assign z = y; + assign u = z; + assign u = x; + assign t = u; + assign t = x; + assign t = y; + wire [128:0] xx; + logic [128:0] xy; + logic [128:0] xz; + bit one = 1; + always #5 clk <= ~clk; + + always #10 xz = ~xz; + assign xx = xy; + assign xx = xz; + + logic vvv; + // logic example; + task writeFourState(logic a); + if (a === 1'b1) $write("1"); + else if (a === 1'b0) $write("0"); + else if (a === 1'bx) $write("x"); + else if (a === 1'bz) $write("z"); + else $stop; + endtask + task print(logic a, logic b); + // $write(" %1d & %1d == %1d |", a, b, a & b); + $write(" "); + writeFourState(a); + $write(" ^ "); + writeFourState(b); + $write(" == "); + writeFourState(a ^ b); + $write(" |"); + endtask + initial begin + static int n = integer'('b0z0x1100); + static integer res = 'b01xz | n; + if ((int'('b01xz | n)) === n); + else $stop; + #1; + xy = 442093479423423857275364882039482723489; + xz = 442093479423423857275364882039482723489; + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + $dumpvars(); + $write("res: "); + writeFourState(res[0]); + $write("\n"); + $write("res: "); + writeFourState(res[1]); + $write("\n"); + $write("res: "); + writeFourState(res[2]); + $write("\n"); + $write("res: "); + writeFourState(res[3]); + $write("\n"); + $write("res: "); + writeFourState(res[31]); + $write("\n"); + $write(" ZERO | ONE | X | Z \n"); + $write("ZERO "); + print(0, 0); + print(0, 1); + print(0, 'x); + print(0, 'z); + $write("\nONE "); + print(1, 0); + print(1, 1); + print(1, 'x); + print(1, 'z); + $write("\nX "); + print('x, 0); + print('x, 1); + print('x, 'x); + print('x, 'z); + $write("\nZ "); + print('z, 0); + print('z, 1); + print('z, 'x); + print('z, 'z); + $write("\n"); + $write("x wire: "); + writeFourState(x); + $write("\n"); + $write("z wor: "); + writeFourState(z); + $write("\n"); + $write("u triand: "); + writeFourState(u); + $write("\n"); + $write("t wire: "); + writeFourState(t); + $write("\n"); + #1; + $write("x wire: "); + writeFourState(x); + $write("\n"); + $write("z wor: "); + writeFourState(z); + $write("\n"); + $write("u triand: "); + writeFourState(u); + $write("\n"); + $write("t wire: "); + writeFourState(t); + $write("\n"); + $write("vvv: "); + writeFourState(vvv); + $write("\n"); + if ('x & (t !== 0)) $stop; + else if (t != 1) $stop; + else if (~(t & one | t)) $stop; + else if (t | one) $write("Bye\n"); + else $stop; + #100; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_fourstate_demo2.out b/test_regress/t/t_fourstate_demo2.out new file mode 100644 index 000000000..f7095935c --- /dev/null +++ b/test_regress/t/t_fourstate_demo2.out @@ -0,0 +1,17 @@ +[out] xxxx +[out] xxxx +[out] xxxx +[out] xxxx +[out] xxxx +[out] 0000 +[out] 0001 +[out] 0010 +[out] 0011 +[out] 0100 +[out] 0101 +[out] 0110 +[out] 0111 +[out] 1000 +[out] 1001 +*-* All Finished *-* +[out] 1010 diff --git a/test_regress/t/t_fourstate_demo2.out.vcd b/test_regress/t/t_fourstate_demo2.out.vcd new file mode 100644 index 000000000..4d463dfce --- /dev/null +++ b/test_regress/t/t_fourstate_demo2.out.vcd @@ -0,0 +1,99 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module tb_counter $end + $var wire 1 " clk $end + $var wire 1 $ rstn $end + $var wire 4 & out [3:0] $end + $scope module c $end + $var wire 1 " clk $end + $var wire 1 $ rstn $end + $var wire 4 & out [3:0] $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +x" +x$ +bzzzz & +#20 +1$ +#40 +1" +bxxxx & +#45 +0" +#50 +1" +#55 +0" +#60 +1" +#65 +0" +#70 +1" +#75 +0" +#80 +1" +#85 +0" +0$ +#90 +1" +b0000 & +#95 +0" +1$ +#100 +1" +b0001 & +#105 +0" +#110 +1" +b0010 & +#115 +0" +#120 +1" +b0011 & +#125 +0" +#130 +1" +b0100 & +#135 +0" +#140 +1" +b0101 & +#145 +0" +#150 +1" +b0110 & +#155 +0" +#160 +1" +b0111 & +#165 +0" +#170 +1" +b1000 & +#175 +0" +#180 +1" +b1001 & +#185 +0" +#190 +1" +b1010 & +#195 +0" diff --git a/test_regress/t/t_fourstate_demo2.py b/test_regress/t/t_fourstate_demo2.py new file mode 100755 index 000000000..fb46873a9 --- /dev/null +++ b/test_regress/t/t_fourstate_demo2.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.twostate_capable = False + +test.compile(verilator_flags2=['--binary', '--trace-vcd']) + +test.execute(expect_filename=test.golden_filename) + +test.vcd_identical(test.trace_filename, test.golden_filename + '.vcd') + +test.passes() diff --git a/test_regress/t/t_fourstate_demo2.v b/test_regress/t/t_fourstate_demo2.v new file mode 100644 index 000000000..bac28a4e1 --- /dev/null +++ b/test_regress/t/t_fourstate_demo2.v @@ -0,0 +1,65 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +task writeFourState(logic a); + if (a === 1'b1) $write("1"); + else if (a === 1'b0) $write("0"); + else if (a === 1'bx) $write("x"); + else if (a === 1'bz) $write("z"); + else $stop; +endtask + +module counter ( + input clk, + input rstn, + output reg [3:0] out +); + always @(posedge clk) begin + if (!rstn) out <= 0; + else out <= out + 1; + end +endmodule + +module tb_counter; + reg clk; + reg rstn; + wire [3:0] out; + + counter c ( + .clk (clk), + .rstn(rstn), + .out (out) + ); + + always #5 begin + if (clk) begin + $write("[out] "); + writeFourState(out[3]); + writeFourState(out[2]); + writeFourState(out[1]); + writeFourState(out[0]); + $write("\n"); + end + clk = ~clk; + end + + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + $dumpvars(); + #20 rstn = 1; + #20 clk = 0; + + #25 rstn = 1; + #20 rstn = 0; + #10 rstn = 1; + + #100; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_fourstate_dfg_bin_to_one_hot.py b/test_regress/t/t_fourstate_dfg_bin_to_one_hot.py new file mode 100755 index 000000000..4d122074e --- /dev/null +++ b/test_regress/t/t_fourstate_dfg_bin_to_one_hot.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.twostate_capable = False + +test.top_filename = 't/t_dfg_bin_to_one_hot.v' + +test.skip("TODO: DFG does not detect one hot pattern created by V3Fourstate") + +test.compile(verilator_flags2=["--stats", "-fno-table", "-fno-inline"]) + +test.execute() + +test.file_grep(test.stats, r'Optimizations, DFG, BinToOneHot, decoders created\s+(\d+)', 5) + +test.passes() diff --git a/test_regress/t/t_fourstate_div.py b/test_regress/t/t_fourstate_div.py new file mode 100755 index 000000000..5a1741a85 --- /dev/null +++ b/test_regress/t/t_fourstate_div.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.twostate_capable = False + +test.compile(verilator_flags2=['--binary']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fourstate_div.v b/test_regress/t/t_fourstate_div.v new file mode 100644 index 000000000..2023f1ae9 --- /dev/null +++ b/test_regress/t/t_fourstate_div.v @@ -0,0 +1,18 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +module t; + initial begin + if (1 / $c(0) !== 'x) $stop; + if ($c(1) / $c(0) !== 'x) $stop; + if ($c(1) / 0 !== 'x) $stop; + if (1 / 0 !== 'x) $stop; + if (6 / 3 !== 2) $stop; + if ($c(6) / 3 !== 2) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_fourstate_dtype_unsup.out b/test_regress/t/t_fourstate_dtype_unsup.out new file mode 100644 index 000000000..319fc5d39 --- /dev/null +++ b/test_regress/t/t_fourstate_dtype_unsup.out @@ -0,0 +1,18 @@ +%Error-UNSUPPORTED: t/t_fourstate_dtype_unsup.v:13:9: Variables of type: 'logic$[$]' are unsupported with --fourstate + : ... note: In instance 't' + 13 | logic q [$]; + | ^ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error-UNSUPPORTED: t/t_fourstate_dtype_unsup.v:14:9: Variables of type: 'logic$[0:12]' are unsupported with --fourstate + : ... note: In instance 't' + 14 | logic p [13]; + | ^ +%Error-UNSUPPORTED: t/t_fourstate_dtype_unsup.v:15:9: Variables of type: 'logic$[integer]' are unsupported with --fourstate + : ... note: In instance 't' + 15 | logic a [integer]; + | ^ +%Error-UNSUPPORTED: t/t_fourstate_dtype_unsup.v:16:7: Variables of type: 'struct{}$unit::bar' are unsupported with --fourstate + : ... note: In instance 't' + 16 | bar c; + | ^ +%Error: Exiting due to diff --git a/test_regress/t/t_fourstate_dtype_unsup.py b/test_regress/t/t_fourstate_dtype_unsup.py new file mode 100755 index 000000000..578fc7b99 --- /dev/null +++ b/test_regress/t/t_fourstate_dtype_unsup.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.twostate_capable = False + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fourstate_dtype_unsup.v b/test_regress/t/t_fourstate_dtype_unsup.v new file mode 100644 index 000000000..2941e6018 --- /dev/null +++ b/test_regress/t/t_fourstate_dtype_unsup.v @@ -0,0 +1,17 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +typedef struct packed { + logic x; + logic y; +} bar; + +module t; + logic q [$]; + logic p [13]; + logic a [integer]; + bar c; +endmodule diff --git a/test_regress/t/t_fourstate_eqwild.py b/test_regress/t/t_fourstate_eqwild.py new file mode 100755 index 000000000..5a1741a85 --- /dev/null +++ b/test_regress/t/t_fourstate_eqwild.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.twostate_capable = False + +test.compile(verilator_flags2=['--binary']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fourstate_eqwild.v b/test_regress/t/t_fourstate_eqwild.v new file mode 100644 index 000000000..6cc581e7e --- /dev/null +++ b/test_regress/t/t_fourstate_eqwild.v @@ -0,0 +1,35 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +`ifdef VERILATOR +`define IMPURE_ONE ($c(1)) +`else +`define IMPURE_ONE (|($random | $random)) +`endif + +module t; + function integer f(integer x); + if (`IMPURE_ONE) return x; + return 'x; + endfunction + + initial begin + if ((f('b101) ==? f('b101)) !== 1) $stop; + if ((f('b101) ==? f('b10x)) !== 1) $stop; + if ((f('b101) ==? f('b1xz)) !== 1) $stop; + if ((f('b101) ==? f('b10z)) !== 1) $stop; + if ((f('b1z1) ==? f('b10z)) !== 'x) $stop; + if ((f('b1xx) ==? f('b1xx)) !== 1) $stop; + if ((f('b1x1) ==? f('b101)) !== 'x) $stop; + if ((f('b1zz) ==? f('b1xz)) !== 1) $stop; + if ((f('bz01) ==? f('b1zx)) !== 'x) $stop; + if ((f('b001) ==? f('b1zx)) !== 0) $stop; + if ((f('b001) ==? f('b111)) !== 0) $stop; + if ((f('bx00) ==? f('bxz1)) !== 0) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_fourstate_event_detection.py b/test_regress/t/t_fourstate_event_detection.py new file mode 100755 index 000000000..5a1741a85 --- /dev/null +++ b/test_regress/t/t_fourstate_event_detection.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.twostate_capable = False + +test.compile(verilator_flags2=['--binary']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fourstate_event_detection.v b/test_regress/t/t_fourstate_event_detection.v new file mode 100644 index 000000000..a64115424 --- /dev/null +++ b/test_regress/t/t_fourstate_event_detection.v @@ -0,0 +1,116 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +module t; + bit posedgeTriggered = 0; + bit negedgeTriggered = 0; + bit bothedgeTriggered = 0; + bit changeTriggered = 0; + bit initialized = 0; + logic val = 0; + + typedef enum bit [1:0] { + POS, + NEG, + CHANGE, + NONE + } expected_event_t; + + task assertTriggered(expected_event_t eventType); + if (eventType == POS) begin + if (!posedgeTriggered) $stop; + if (negedgeTriggered) $stop; + if (!bothedgeTriggered) $stop; + if (!changeTriggered) $stop; + end else if (eventType == NEG) begin + if (posedgeTriggered) $stop; + if (!negedgeTriggered) $stop; + if (!bothedgeTriggered) $stop; + if (!changeTriggered) $stop; + end else if (eventType == CHANGE) begin + if (posedgeTriggered) $stop; + if (negedgeTriggered) $stop; + if (bothedgeTriggered) $stop; + if (!changeTriggered) $stop; + end else if (eventType == NONE) begin + if (posedgeTriggered) $stop; + if (negedgeTriggered) $stop; + if (bothedgeTriggered) $stop; + if (changeTriggered) $stop; + end + posedgeTriggered = 0; + negedgeTriggered = 0; + bothedgeTriggered = 0; + changeTriggered = 0; + endtask + + always @(val) begin + if (initialized & changeTriggered) $stop; + changeTriggered = 1; + end + + always @(edge val) begin + if (bothedgeTriggered) $stop; + bothedgeTriggered = 1; + end + + always @(posedge val) begin + if (posedgeTriggered) $stop; + posedgeTriggered = 1; + end + + always @(negedge val) begin + if (negedgeTriggered) $stop; + negedgeTriggered = 1; + end + + initial begin + #1 changeTriggered = 0; + initialized = 1; + #1 val = 1; + #1 assertTriggered(POS); + #1 val = 1; + #1 assertTriggered(NONE); + #1 val = 'x; + #1 assertTriggered(NEG); + #1 val = 'z; + #1 assertTriggered(CHANGE); + #1 val = 0; + #1 assertTriggered(NEG); + #1 val = 'z; + #1 assertTriggered(POS); + #1 val = 'z; + #1 assertTriggered(NONE); + #1 val = 'x; + #1 assertTriggered(CHANGE); + #1 val = 'x; + #1 assertTriggered(NONE); + #1 val = 'z; + #1 assertTriggered(CHANGE); + #1 val = 'x; + #1 assertTriggered(CHANGE); + #1 val = 0; + #1 assertTriggered(NEG); + #1 val = 1; + #1 assertTriggered(POS); + #1 val = 0; + #1 assertTriggered(NEG); + #1 val = 'x; + #1 assertTriggered(POS); + #1 val = 1; + #1 assertTriggered(POS); + #1 val = 'z; + #1 assertTriggered(NEG); + #1 val = 1; + #1 assertTriggered(POS); + #1 val = 0; + #1 assertTriggered(NEG); + #1 val = 0; + #1 assertTriggered(NONE); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_fourstate_expr_not_handled_unsup.out b/test_regress/t/t_fourstate_expr_not_handled_unsup.out new file mode 100644 index 000000000..1b462b846 --- /dev/null +++ b/test_regress/t/t_fourstate_expr_not_handled_unsup.out @@ -0,0 +1,10 @@ +%Error-UNSUPPORTED: t/t_fourstate_expr_not_handled_unsup.v:10:9: This four-state expression has not been handled + : ... note: In instance 't' + 10 | alias y = x; + | ^ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error-UNSUPPORTED: t/t_fourstate_expr_not_handled_unsup.v:10:13: This four-state expression has not been handled + : ... note: In instance 't' + 10 | alias y = x; + | ^ +%Error: Exiting due to diff --git a/test_regress/t/t_fourstate_expr_not_handled_unsup.py b/test_regress/t/t_fourstate_expr_not_handled_unsup.py new file mode 100755 index 000000000..578fc7b99 --- /dev/null +++ b/test_regress/t/t_fourstate_expr_not_handled_unsup.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.twostate_capable = False + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fourstate_expr_not_handled_unsup.v b/test_regress/t/t_fourstate_expr_not_handled_unsup.v new file mode 100644 index 000000000..a00b36c85 --- /dev/null +++ b/test_regress/t/t_fourstate_expr_not_handled_unsup.v @@ -0,0 +1,11 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +module t; + wire x; + wire y; + alias y = x; +endmodule diff --git a/test_regress/t/t_fourstate_extend.py b/test_regress/t/t_fourstate_extend.py new file mode 100755 index 000000000..5a1741a85 --- /dev/null +++ b/test_regress/t/t_fourstate_extend.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.twostate_capable = False + +test.compile(verilator_flags2=['--binary']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fourstate_extend.v b/test_regress/t/t_fourstate_extend.v new file mode 100644 index 000000000..96ce9fbb0 --- /dev/null +++ b/test_regress/t/t_fourstate_extend.v @@ -0,0 +1,20 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +typedef logic unsigned [31:0] uinteger; + +module t; + initial begin + static logic unsigned [15:0] foo = 16'bz000000000000001; + static logic signed [15:0] foo2 = 16'bz000000000000001; + static integer bar = integer'(foo); + if (bar !== 32'b0000000000000000z000000000000001) $stop; + bar = uinteger'(foo2); + if (bar !== 32'bzzzzzzzzzzzzzzzzz000000000000001) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_fourstate_format.out b/test_regress/t/t_fourstate_format.out new file mode 100644 index 000000000..36c2e68a2 --- /dev/null +++ b/test_regress/t/t_fourstate_format.out @@ -0,0 +1,6 @@ +0 +0 +0 +1 + 3 +*-* All Finished *-* diff --git a/test_regress/t/t_fourstate_format.py b/test_regress/t/t_fourstate_format.py new file mode 100755 index 000000000..3fbfaf389 --- /dev/null +++ b/test_regress/t/t_fourstate_format.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.twostate_capable = False + +test.compile(verilator_flags2=['--binary']) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fourstate_format.v b/test_regress/t/t_fourstate_format.v new file mode 100644 index 000000000..bbea6a9b3 --- /dev/null +++ b/test_regress/t/t_fourstate_format.v @@ -0,0 +1,25 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +module t; + function integer foo(integer a, integer b); + return a + b; + endfunction + + initial begin + static logic v = 'x; + $write("%d\n", v); + v = 'z; + $write("%d\n", v); + v = 0; + $write("%d\n", v); + v = 1; + $write("%d\n", v); + $write("%d\n", foo(1, 2)); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_fourstate_format_unsup.out b/test_regress/t/t_fourstate_format_unsup.out new file mode 100644 index 000000000..6cd056d47 --- /dev/null +++ b/test_regress/t/t_fourstate_format_unsup.out @@ -0,0 +1,23 @@ +%Warning-CASTFOURSTATE: t/t_fourstate_format.v:14:20: Some features are not supported with four-state values - cast it to two-state logic or suppress this warning and it will be done implicitly + : ... note: In instance 't' + 14 | $write("%d\n", v); + | ^ + ... For warning description see https://verilator.org/warn/CASTFOURSTATE?v=latest + ... Use "/* verilator lint_off CASTFOURSTATE */" and lint_on around source to disable this message. +%Warning-CASTFOURSTATE: t/t_fourstate_format.v:16:20: Some features are not supported with four-state values - cast it to two-state logic or suppress this warning and it will be done implicitly + : ... note: In instance 't' + 16 | $write("%d\n", v); + | ^ +%Warning-CASTFOURSTATE: t/t_fourstate_format.v:18:20: Some features are not supported with four-state values - cast it to two-state logic or suppress this warning and it will be done implicitly + : ... note: In instance 't' + 18 | $write("%d\n", v); + | ^ +%Warning-CASTFOURSTATE: t/t_fourstate_format.v:20:20: Some features are not supported with four-state values - cast it to two-state logic or suppress this warning and it will be done implicitly + : ... note: In instance 't' + 20 | $write("%d\n", v); + | ^ +%Warning-CASTFOURSTATE: t/t_fourstate_format.v:21:20: Some features are not supported with four-state values - cast it to two-state logic or suppress this warning and it will be done implicitly + : ... note: In instance 't' + 21 | $write("%d\n", foo(1, 2)); + | ^~~ +%Error: Exiting due to diff --git a/test_regress/t/t_fourstate_format_unsup.py b/test_regress/t/t_fourstate_format_unsup.py new file mode 100755 index 000000000..3ef18b402 --- /dev/null +++ b/test_regress/t/t_fourstate_format_unsup.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.twostate_capable = False +test.fourstate_nowarn = False + +test.top_filename = "t/t_fourstate_format.v" + +test.lint(verilator_flags2=['-Wno-FUTURE'], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fourstate_fourstate_fst_unsup.out b/test_regress/t/t_fourstate_fourstate_fst_unsup.out new file mode 100644 index 000000000..ffa25bd87 --- /dev/null +++ b/test_regress/t/t_fourstate_fourstate_fst_unsup.out @@ -0,0 +1,3 @@ +%Error-UNSUPPORTED: --fourstate is not supported with fst trace + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error: Exiting due to diff --git a/test_regress/t/t_fourstate_fourstate_fst_unsup.py b/test_regress/t/t_fourstate_fourstate_fst_unsup.py new file mode 100755 index 000000000..8c66527af --- /dev/null +++ b/test_regress/t/t_fourstate_fourstate_fst_unsup.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.twostate_capable = False + +test.top_filename = "t_trace_split_cfuncs.v" + +test.lint(verilator_flags2=['--trace-fst'], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fourstate_fourstate_hier_unsup.out b/test_regress/t/t_fourstate_fourstate_hier_unsup.out index 1a1e0a5ce..7c08c08b6 100644 --- a/test_regress/t/t_fourstate_fourstate_hier_unsup.out +++ b/test_regress/t/t_fourstate_fourstate_hier_unsup.out @@ -1,6 +1,3 @@ -%Warning-FUTURE: --fourstate is not supported as is under development - ... For warning description see https://verilator.org/warn/FUTURE?v=latest - ... Use "/* verilator lint_off FUTURE */" and lint_on around source to disable this message. %Error-UNSUPPORTED: --fourstate is not supported with hierarchical Verilation ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_fourstate_fourstate_hier_unsup.py b/test_regress/t/t_fourstate_fourstate_hier_unsup.py index e17290ffa..eb3cb0d60 100755 --- a/test_regress/t/t_fourstate_fourstate_hier_unsup.py +++ b/test_regress/t/t_fourstate_fourstate_hier_unsup.py @@ -9,12 +9,11 @@ import vltest_bootstrap -test.scenarios('simulator') +test.scenarios('linter') +test.twostate_capable = False test.top_filename = "t_fourstate_fourstate_unsup.v" -test.lint(verilator_flags2=['--fourstate', '--hierarchical'], - fails=True, - expect_filename=test.golden_filename) +test.lint(verilator_flags2=['--hierarchical'], fails=True, expect_filename=test.golden_filename) test.passes() diff --git a/test_regress/t/t_fourstate_fourstate_sc_unsup.out b/test_regress/t/t_fourstate_fourstate_sc_unsup.out new file mode 100644 index 000000000..cd2ca4105 --- /dev/null +++ b/test_regress/t/t_fourstate_fourstate_sc_unsup.out @@ -0,0 +1,3 @@ +%Error-UNSUPPORTED: --fourstate is not supported with --sc + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error: Exiting due to diff --git a/test_regress/t/t_fourstate_fourstate_sc_unsup.py b/test_regress/t/t_fourstate_fourstate_sc_unsup.py new file mode 100755 index 000000000..581ef9175 --- /dev/null +++ b/test_regress/t/t_fourstate_fourstate_sc_unsup.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.twostate_capable = False + +test.top_filename = "t_fourstate_fourstate_unsup.v" + +test.lint(verilator_flags2=['--sc'], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fourstate_fourstate_unsup.out b/test_regress/t/t_fourstate_fourstate_unsup.out old mode 100755 new mode 100644 diff --git a/test_regress/t/t_fourstate_fourstate_unsup.py b/test_regress/t/t_fourstate_fourstate_unsup.py index 536d13cca..0fdbfd116 100755 --- a/test_regress/t/t_fourstate_fourstate_unsup.py +++ b/test_regress/t/t_fourstate_fourstate_unsup.py @@ -9,8 +9,11 @@ import vltest_bootstrap -test.scenarios('simulator') +test.scenarios('linter') -test.lint(verilator_flags2=['--fourstate'], fails=True, expect_filename=test.golden_filename) +test.twostate_capable = False +test.fourstate_nowarn = False + +test.lint(fails=True, expect_filename=test.golden_filename) test.passes() diff --git a/test_regress/t/t_fourstate_fwrite.out b/test_regress/t/t_fourstate_fwrite.out new file mode 100644 index 000000000..530a8a796 --- /dev/null +++ b/test_regress/t/t_fourstate_fwrite.out @@ -0,0 +1,4 @@ +0 +0 +0 +1 diff --git a/test_regress/t/t_fourstate_fwrite.py b/test_regress/t/t_fourstate_fwrite.py new file mode 100755 index 000000000..13ce85db1 --- /dev/null +++ b/test_regress/t/t_fourstate_fwrite.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.twostate_capable = False + +test.compile() + +test.execute() + +test.files_identical(test.obj_dir + "/" + test.name + "_logger.log", test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fourstate_fwrite.v b/test_regress/t/t_fourstate_fwrite.v new file mode 100644 index 000000000..9526edd87 --- /dev/null +++ b/test_regress/t/t_fourstate_fwrite.v @@ -0,0 +1,26 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +module t; + integer cycles; + initial begin + integer fd; + fd = $fopen({`STRINGIFY(`TEST_OBJ_DIR), "/t_fourstate_fwrite_logger.log"}, "w"); + $fwrite(fd, "%0d\n", cycles); + cycles++; + $fwrite(fd, "%0d\n", cycles); + cycles = 0; + $fwrite(fd, "%0d\n", cycles); + cycles++; + $fwrite(fd, "%0d\n", cycles); + $fflush(fd); + $fclose(fd); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_fourstate_hier_block_type_param_unsup.out b/test_regress/t/t_fourstate_hier_block_type_param_unsup.out new file mode 100644 index 000000000..7c08c08b6 --- /dev/null +++ b/test_regress/t/t_fourstate_hier_block_type_param_unsup.out @@ -0,0 +1,3 @@ +%Error-UNSUPPORTED: --fourstate is not supported with hierarchical Verilation + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error: Exiting due to diff --git a/test_regress/t/t_fourstate_hier_block_type_param_unsup.py b/test_regress/t/t_fourstate_hier_block_type_param_unsup.py new file mode 100755 index 000000000..8f9208207 --- /dev/null +++ b/test_regress/t/t_fourstate_hier_block_type_param_unsup.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.twostate_capable = False + +test.top_filename = 't/t_hier_block_type_param.v' + +test.lint(verilator_flags2=['--hierarchical'], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fourstate_init.py b/test_regress/t/t_fourstate_init.py new file mode 100755 index 000000000..5a1741a85 --- /dev/null +++ b/test_regress/t/t_fourstate_init.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.twostate_capable = False + +test.compile(verilator_flags2=['--binary']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fourstate_init.v b/test_regress/t/t_fourstate_init.v new file mode 100644 index 000000000..9cdfbe9df --- /dev/null +++ b/test_regress/t/t_fourstate_init.v @@ -0,0 +1,45 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +module sub(input [95:0] notTopLvlInput, input notTopLvlInputs); + initial begin + if (notTopLvlInput !== 96'bz) $stop; + if (notTopLvlInputs !== 1'bz) $stop; + end +endmodule + +module t(input [95:0] topLvlInput, input topLvlInputs); + reg [95:0] r; + reg rs; + wire [95:0] w; + wire ws; + logic [95:0] l; + logic ls; + logic [96:0] l2; + + // verilator lint_off PINMISSING + sub s(); + // verilator lint_on PINMISSING + + initial begin + logic [127:0] tmp; + if (topLvlInput !== 96'b0) $stop; + if (topLvlInputs !== 1'b0) $stop; + if (r !== 96'bx) $stop; + if (rs !== 1'bx) $stop; + if (w !== 96'bz) $stop; + if (ws !== 1'bz) $stop; + if (ls !== 1'bx) $stop; + if (l2 !== 97'bx) $stop; + // verilator lint_off WIDTHEXPAND + tmp = l2; // To check weather bits are clean + // verilator lint_on WIDTHEXPAND + if (tmp !== {{31'd0, 97'bx}}) $stop; + #1; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_fourstate_inst_unsup.out b/test_regress/t/t_fourstate_inst_unsup.out new file mode 100644 index 000000000..e5b4dc0bf --- /dev/null +++ b/test_regress/t/t_fourstate_inst_unsup.out @@ -0,0 +1,10 @@ +%Error-UNSUPPORTED: t/t_inst_sv.v:14:17: supply0/tri0 and supply1/tri1 are not supported with --fourstate + : ... note: In instance 't' + 14 | supply0 [1:0] low; + | ^~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error-UNSUPPORTED: t/t_inst_sv.v:15:17: supply0/tri0 and supply1/tri1 are not supported with --fourstate + : ... note: In instance 't' + 15 | supply1 [1:0] high; + | ^~~~ +%Error: Exiting due to diff --git a/test_regress/t/t_fourstate_inst_unsup.py b/test_regress/t/t_fourstate_inst_unsup.py new file mode 100755 index 000000000..e705b6034 --- /dev/null +++ b/test_regress/t/t_fourstate_inst_unsup.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.twostate_capable = False + +test.top_filename = 't/t_inst_sv.v' + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fourstate_lint_unused_iface_unsup.out b/test_regress/t/t_fourstate_lint_unused_iface_unsup.out new file mode 100644 index 000000000..55c88f356 --- /dev/null +++ b/test_regress/t/t_fourstate_lint_unused_iface_unsup.out @@ -0,0 +1,10 @@ +%Error-UNSUPPORTED: t/t_lint_unused_iface.v:10:23: modports are not supported with --fourstate + : ... note: In instance 't.sub' + 10 | modport slave(input signal); + | ^~~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error-UNSUPPORTED: t/t_lint_unused_iface.v:12:25: modports are not supported with --fourstate + : ... note: In instance 't.sub' + 12 | modport master(output signal); + | ^~~~~~ +%Error: Exiting due to diff --git a/test_regress/t/t_fourstate_lint_unused_iface_unsup.py b/test_regress/t/t_fourstate_lint_unused_iface_unsup.py new file mode 100755 index 000000000..bc6a56bb4 --- /dev/null +++ b/test_regress/t/t_fourstate_lint_unused_iface_unsup.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.twostate_capable = False + +test.top_filename = 't/t_lint_unused_iface.v' + +test.lint(verilator_flags2=['--Wall', '-Wno-DECLFILENAME'], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fourstate_logand.out b/test_regress/t/t_fourstate_logand.out new file mode 100644 index 000000000..4b40ce433 --- /dev/null +++ b/test_regress/t/t_fourstate_logand.out @@ -0,0 +1,29 @@ +0 +0 +0 +0 +1 +0 +1 +1 +1 +x +1 +z +x +0 +x +1 +x +x +x +z +z +0 +z +1 +z +x +z +z +*-* All Finished *-* diff --git a/test_regress/t/t_fourstate_logand.py b/test_regress/t/t_fourstate_logand.py new file mode 100755 index 000000000..3fbfaf389 --- /dev/null +++ b/test_regress/t/t_fourstate_logand.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.twostate_capable = False + +test.compile(verilator_flags2=['--binary']) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fourstate_logand.v b/test_regress/t/t_fourstate_logand.v new file mode 100644 index 000000000..bb4202180 --- /dev/null +++ b/test_regress/t/t_fourstate_logand.v @@ -0,0 +1,41 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +module t; + function logic f(logic a); + if (a === 1'b1) $write("1"); + else if (a === 1'b0) $write("0"); + else if (a === 1'bx) $write("x"); + else if (a === 1'bz) $write("z"); + else $stop; + $write("\n"); + return a; + endfunction + + initial begin + if ((f(0) && f(0)) !== 0) $stop; + if ((f(0) && f(1)) !== 0) $stop; + if ((f(0) && f('x)) !== 0) $stop; + if ((f(0) && f('z)) !== 0) $stop; + + if ((f(1) && f(0)) !== 0) $stop; + if ((f(1) && f(1)) !== 1) $stop; + if ((f(1) && f('x)) !== 'x) $stop; + if ((f(1) && f('z)) !== 'x) $stop; + + if ((f('x) && f(0)) !== 0) $stop; + if ((f('x) && f(1)) !== 'x) $stop; + if ((f('x) && f('x)) !== 'x) $stop; + if ((f('x) && f('z)) !== 'x) $stop; + + if ((f('z) && f(0)) !== 0) $stop; + if ((f('z) && f(1)) !== 'x) $stop; + if ((f('z) && f('x)) !== 'x) $stop; + if ((f('z) && f('z)) !== 'x) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_fourstate_logor.out b/test_regress/t/t_fourstate_logor.out new file mode 100644 index 000000000..130a3017b --- /dev/null +++ b/test_regress/t/t_fourstate_logor.out @@ -0,0 +1,29 @@ +0 +0 +0 +1 +0 +x +0 +z +1 +1 +1 +1 +x +0 +x +1 +x +x +x +z +z +0 +z +1 +z +x +z +z +*-* All Finished *-* diff --git a/test_regress/t/t_fourstate_logor.py b/test_regress/t/t_fourstate_logor.py new file mode 100755 index 000000000..3fbfaf389 --- /dev/null +++ b/test_regress/t/t_fourstate_logor.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.twostate_capable = False + +test.compile(verilator_flags2=['--binary']) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fourstate_logor.v b/test_regress/t/t_fourstate_logor.v new file mode 100644 index 000000000..510feeee6 --- /dev/null +++ b/test_regress/t/t_fourstate_logor.v @@ -0,0 +1,41 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +module t; + function logic f(logic a); + if (a === 1'b1) $write("1"); + else if (a === 1'b0) $write("0"); + else if (a === 1'bx) $write("x"); + else if (a === 1'bz) $write("z"); + else $stop; + $write("\n"); + return a; + endfunction + + initial begin + if ((f(0) || f(0)) !== 0) $stop; + if ((f(0) || f(1)) !== 1) $stop; + if ((f(0) || f('x)) !== 'x) $stop; + if ((f(0) || f('z)) !== 'x) $stop; + + if ((f(1) || f(0)) !== 1) $stop; + if ((f(1) || f(1)) !== 1) $stop; + if ((f(1) || f('x)) !== 1) $stop; + if ((f(1) || f('z)) !== 1) $stop; + + if ((f('x) || f(0)) !== 'x) $stop; + if ((f('x) || f(1)) !== 1) $stop; + if ((f('x) || f('x)) !== 'x) $stop; + if ((f('x) || f('z)) !== 'x) $stop; + + if ((f('z) || f(0)) !== 'x) $stop; + if ((f('z) || f(1)) !== 1) $stop; + if ((f('z) || f('x)) !== 'x) $stop; + if ((f('z) || f('z)) !== 'x) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_fourstate_loop.py b/test_regress/t/t_fourstate_loop.py new file mode 100755 index 000000000..5a1741a85 --- /dev/null +++ b/test_regress/t/t_fourstate_loop.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.twostate_capable = False + +test.compile(verilator_flags2=['--binary']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fourstate_loop.v b/test_regress/t/t_fourstate_loop.v new file mode 100644 index 000000000..a4630452e --- /dev/null +++ b/test_regress/t/t_fourstate_loop.v @@ -0,0 +1,23 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +module t; + initial begin + static bit foo; + static logic bar; + + if (bar !== 'x) $stop; + while (!bar) $stop; + while (bar) $stop; + while (bar) $stop; + while (!foo) foo++; + while (!bar) bar++; + while (!foo) $stop; + while (!bar) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_fourstate_mixed_short_circuting.py b/test_regress/t/t_fourstate_mixed_short_circuting.py new file mode 100755 index 000000000..a16833e52 --- /dev/null +++ b/test_regress/t/t_fourstate_mixed_short_circuting.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') + +test.compile(verilator_flags2=['--binary']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fourstate_mixed_short_circuting.v b/test_regress/t/t_fourstate_mixed_short_circuting.v new file mode 100644 index 000000000..f21e6550d --- /dev/null +++ b/test_regress/t/t_fourstate_mixed_short_circuting.v @@ -0,0 +1,30 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +`ifdef VERILATOR +`define IMPURE_ONE ($c(1)) +`else +`define IMPURE_ONE (|($random | $random)) +`endif + + +module t; + static int calls = 0; + + function logic bar(); + calls++; + return 'x; + endfunction + + initial begin + if ((bit'(`IMPURE_ONE) || bit'(bar() || ('x && 1))) !== 1) $stop; + if ((bit'(!`IMPURE_ONE) && bit'(bar() || ('x && 1))) !== 0) $stop; + if ((`IMPURE_ONE ? 0 : bit'(bar())) !== 0) $stop; + if (calls !== 0) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_fourstate_mod_interface_array5_unsup.out b/test_regress/t/t_fourstate_mod_interface_array5_unsup.out new file mode 100644 index 000000000..ed07a3992 --- /dev/null +++ b/test_regress/t/t_fourstate_mod_interface_array5_unsup.out @@ -0,0 +1,8 @@ +%Error-UNSUPPORTED: t/t_mod_interface_array5.v:60:55: Hierarchical references are unsupported in assigns with --fourstate + 60 | assign muxIn[muxIdx].value = demuxOut[demuxIdx].value; + | ^~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error-UNSUPPORTED: t/t_mod_interface_array5.v:24:71: Hierarchical references are unsupported in assigns with --fourstate + 24 | for (i = 0; i < N; i = i + 1) assign downstream[i].value = upstream.value; + | ^~~~~ +%Error: Exiting due to diff --git a/test_regress/t/t_fourstate_mod_interface_array5_unsup.py b/test_regress/t/t_fourstate_mod_interface_array5_unsup.py new file mode 100755 index 000000000..3f2cd9b95 --- /dev/null +++ b/test_regress/t/t_fourstate_mod_interface_array5_unsup.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.twostate_capable = False + +test.top_filename = 't/t_mod_interface_array5.v' + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fourstate_module_input_default_value_unsup.out b/test_regress/t/t_fourstate_module_input_default_value_unsup.out new file mode 100644 index 000000000..72f5bba3c --- /dev/null +++ b/test_regress/t/t_fourstate_module_input_default_value_unsup.out @@ -0,0 +1,10 @@ +%Error-UNSUPPORTED: t/t_module_input_default_value.v:150:9: Cells with pins that are not a variable reference or a constant are not supported with --fourstate + : ... note: In instance 't' + 150 | (.i(logic0_from_some_function()), + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error-UNSUPPORTED: t/t_module_input_default_value.v:160:23: Cells with pins that are not a variable reference or a constant are not supported with --fourstate + : ... note: In instance 't' + 160 | (.i(32'h6789_2345 + 32'(cyc)), + | ^ +%Error: Exiting due to diff --git a/test_regress/t/t_fourstate_module_input_default_value_unsup.py b/test_regress/t/t_fourstate_module_input_default_value_unsup.py new file mode 100755 index 000000000..1f7a02a8b --- /dev/null +++ b/test_regress/t/t_fourstate_module_input_default_value_unsup.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.twostate_capable = False + +test.top_filename = 't/t_module_input_default_value.v' + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fourstate_neqwild.py b/test_regress/t/t_fourstate_neqwild.py new file mode 100755 index 000000000..5a1741a85 --- /dev/null +++ b/test_regress/t/t_fourstate_neqwild.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.twostate_capable = False + +test.compile(verilator_flags2=['--binary']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fourstate_neqwild.v b/test_regress/t/t_fourstate_neqwild.v new file mode 100644 index 000000000..aec1c41ae --- /dev/null +++ b/test_regress/t/t_fourstate_neqwild.v @@ -0,0 +1,35 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +`ifdef VERILATOR +`define IMPURE_ONE ($c(1)) +`else +`define IMPURE_ONE (|($random | $random)) +`endif + +module t; + function integer f(integer x); + if (`IMPURE_ONE) return x; + return 'x; + endfunction + + initial begin + if ((f('b101) !=? f('b101)) !== 0) $stop; + if ((f('b101) !=? f('b10x)) !== 0) $stop; + if ((f('b101) !=? f('b1xz)) !== 0) $stop; + if ((f('b101) !=? f('b10z)) !== 0) $stop; + if ((f('b1z1) !=? f('b10z)) !== 'x) $stop; + if ((f('b1xx) !=? f('b1xx)) !== 0) $stop; + if ((f('b1x1) !=? f('b101)) !== 'x) $stop; + if ((f('b1zz) !=? f('b1xz)) !== 0) $stop; + if ((f('bz01) !=? f('b1zx)) !== 'x) $stop; + if ((f('b001) !=? f('b1zx)) !== 1) $stop; + if ((f('b001) !=? f('b111)) !== 1) $stop; + if ((f('bx00) !=? f('bxz1)) !== 1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_fourstate_no_fourstate.py b/test_regress/t/t_fourstate_no_fourstate.py index a3be7a21a..774f5727d 100755 --- a/test_regress/t/t_fourstate_no_fourstate.py +++ b/test_regress/t/t_fourstate_no_fourstate.py @@ -9,7 +9,7 @@ import vltest_bootstrap -test.scenarios('simulator') +test.scenarios('simulator_st') test.compile(verilator_flags2=['--binary', '--no-fourstate']) diff --git a/test_regress/t/t_fourstate_no_zero_top_ports.py b/test_regress/t/t_fourstate_no_zero_top_ports.py new file mode 100755 index 000000000..beeb63a0d --- /dev/null +++ b/test_regress/t/t_fourstate_no_zero_top_ports.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.twostate_capable = False + +test.top_filename = 't_fourstate_zero_top_ports.v' + +test.compile(verilator_flags2=['--binary', '--no-zero-top-ports', "-DINPUT_VAL=\"'z\""]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fourstate_no_zero_top_ports_twostate.out b/test_regress/t/t_fourstate_no_zero_top_ports_twostate.out new file mode 100644 index 000000000..668ef3d8d --- /dev/null +++ b/test_regress/t/t_fourstate_no_zero_top_ports_twostate.out @@ -0,0 +1,3 @@ +%Error: --zero-top-ports and --no-zero-top-ports shall be used only with --fourstate + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error: Exiting due to diff --git a/test_regress/t/t_fourstate_no_zero_top_ports_twostate.py b/test_regress/t/t_fourstate_no_zero_top_ports_twostate.py new file mode 100755 index 000000000..0f5c07e8e --- /dev/null +++ b/test_regress/t/t_fourstate_no_zero_top_ports_twostate.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.top_filename = 't_fourstate_zero_top_ports.v' + +test.scenarios('linter') + +test.lint(verilator_flags2=['--no-fourstate', '--no-zero-top-ports', '-DINPUT_VAL=0'], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fourstate_noreturn.py b/test_regress/t/t_fourstate_noreturn.py new file mode 100755 index 000000000..3cbb86f28 --- /dev/null +++ b/test_regress/t/t_fourstate_noreturn.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.twostate_capable = False + +test.compile(verilator_flags2=['--binary', '-Wno-NORETURN']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fourstate_noreturn.v b/test_regress/t/t_fourstate_noreturn.v new file mode 100644 index 000000000..43b6b9f55 --- /dev/null +++ b/test_regress/t/t_fourstate_noreturn.v @@ -0,0 +1,20 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +module t; + function logic foo(); + $c(";"); + endfunction + function logic bar(); + endfunction + + initial begin + if (foo() !== 'x) $stop; + if (bar() !== 'x) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_fourstate_operator_unsup.out b/test_regress/t/t_fourstate_operator_unsup.out new file mode 100644 index 000000000..3aa476472 --- /dev/null +++ b/test_regress/t/t_fourstate_operator_unsup.out @@ -0,0 +1,6 @@ +%Error-UNSUPPORTED: t/t_fourstate_operator_unsup.v:11:11: Unsupported: Operator POWSS not supported in the four-state mode + : ... note: In instance 't' + 11 | y = 2 ** x; + | ^~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error: Exiting due to diff --git a/test_regress/t/t_fourstate_operator_unsup.py b/test_regress/t/t_fourstate_operator_unsup.py new file mode 100755 index 000000000..578fc7b99 --- /dev/null +++ b/test_regress/t/t_fourstate_operator_unsup.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.twostate_capable = False + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fourstate_operator_unsup.v b/test_regress/t/t_fourstate_operator_unsup.v new file mode 100644 index 000000000..1f72e2ff0 --- /dev/null +++ b/test_regress/t/t_fourstate_operator_unsup.v @@ -0,0 +1,13 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +module t; + initial begin + static integer x; + static integer y; + y = 2 ** x; + end +endmodule diff --git a/test_regress/t/t_fourstate_pull_unsup.out b/test_regress/t/t_fourstate_pull_unsup.out new file mode 100644 index 000000000..e3acee275 --- /dev/null +++ b/test_regress/t/t_fourstate_pull_unsup.out @@ -0,0 +1,18 @@ +%Error-UNSUPPORTED: t/t_fourstate_pull_unsup.v:10:10: Pullups and pulldowns are unsupported with --fourstate + : ... note: In instance 't' + 10 | pullup d_0_pup (iolines[0]); + | ^~~~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error-UNSUPPORTED: t/t_fourstate_pull_unsup.v:11:10: Pullups and pulldowns are unsupported with --fourstate + : ... note: In instance 't' + 11 | pullup d_1_pup (iolines[1]); + | ^~~~~~~ +%Error-UNSUPPORTED: t/t_fourstate_pull_unsup.v:12:12: Pullups and pulldowns are unsupported with --fourstate + : ... note: In instance 't' + 12 | pulldown d_2_pdown (iolines[2]); + | ^~~~~~~~~ +%Error-UNSUPPORTED: t/t_fourstate_pull_unsup.v:13:12: Pullups and pulldowns are unsupported with --fourstate + : ... note: In instance 't' + 13 | pulldown d_3_pdown (iolines[3]); + | ^~~~~~~~~ +%Error: Exiting due to diff --git a/test_regress/t/t_fourstate_pull_unsup.py b/test_regress/t/t_fourstate_pull_unsup.py new file mode 100755 index 000000000..578fc7b99 --- /dev/null +++ b/test_regress/t/t_fourstate_pull_unsup.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.twostate_capable = False + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fourstate_pull_unsup.v b/test_regress/t/t_fourstate_pull_unsup.v new file mode 100644 index 000000000..fe45e0145 --- /dev/null +++ b/test_regress/t/t_fourstate_pull_unsup.v @@ -0,0 +1,14 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +module t ( + inout [7:0] iolines +); + pullup d_0_pup (iolines[0]); + pullup d_1_pup (iolines[1]); + pulldown d_2_pdown (iolines[2]); + pulldown d_3_pdown (iolines[3]); +endmodule diff --git a/test_regress/t/t_fourstate_redand.py b/test_regress/t/t_fourstate_redand.py new file mode 100755 index 000000000..b5f04fabf --- /dev/null +++ b/test_regress/t/t_fourstate_redand.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulasimulator_sttor') +test.twostate_capable = False + +test.compile(verilator_flags2=['--binary']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fourstate_redand.v b/test_regress/t/t_fourstate_redand.v new file mode 100644 index 000000000..1c79694c4 --- /dev/null +++ b/test_regress/t/t_fourstate_redand.v @@ -0,0 +1,36 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +`ifdef VERILATOR +`define IMPURE_ONE ($c(1)) +`else +`define IMPURE_ONE (|($random | $random)) +`endif + +module t; + function integer f(integer x); + if (`IMPURE_ONE) return x; + return 'x; + endfunction + + initial begin + if (&f('b00000000000000000000000000000000) !== 0) $stop; + if (&f('b00000000000000000000000000000100) !== 0) $stop; + if (&f('b10000000000000000000000000010100) !== 0) $stop; + if (&f('b0000000000000000000000000000000x) !== 0) $stop; + if (&f('b00000000000000000000000000000z0x) !== 0) $stop; + if (&f('b00000000000000000000000000000z00) !== 0) $stop; + if (&f('b0xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) !== 0) $stop; + if (&f('b1xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) !== 'x) $stop; + if (&f('b1zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz) !== 'x) $stop; + if (&f('b1zzzzzzzzzzzzzzzzzzzzzxxxxxxxxxx) !== 'x) $stop; + if (&f('b1111111111111111111111111111111x) !== 'x) $stop; + if (&f('b1111111111111111111111111111111z) !== 'x) $stop; + if (&f('b11111111111111111111111111111111) !== 1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_fourstate_redor.py b/test_regress/t/t_fourstate_redor.py new file mode 100755 index 000000000..5a1741a85 --- /dev/null +++ b/test_regress/t/t_fourstate_redor.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.twostate_capable = False + +test.compile(verilator_flags2=['--binary']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fourstate_redor.v b/test_regress/t/t_fourstate_redor.v new file mode 100644 index 000000000..21cd682b2 --- /dev/null +++ b/test_regress/t/t_fourstate_redor.v @@ -0,0 +1,30 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +`ifdef VERILATOR +`define IMPURE_ONE ($c(1)) +`else +`define IMPURE_ONE (|($random | $random)) +`endif + +module t; + function integer f(integer x); + if (`IMPURE_ONE) return x; + return 'x; + endfunction + initial begin + if (|f(0) !== 0) $stop; + if (|f(1) !== 1) $stop; + if (|f('x) !== 'x) $stop; + if (|f('z) !== 'x) $stop; + if (|f('b0000z0000) !== 'x) $stop; + if (|f('b0000x0000) !== 'x) $stop; + if (|f('b0000z0010) !== 1) $stop; + if (|f('b0000x0100) !== 1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_fourstate_redxor.py b/test_regress/t/t_fourstate_redxor.py new file mode 100755 index 000000000..5a1741a85 --- /dev/null +++ b/test_regress/t/t_fourstate_redxor.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.twostate_capable = False + +test.compile(verilator_flags2=['--binary']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fourstate_redxor.v b/test_regress/t/t_fourstate_redxor.v new file mode 100644 index 000000000..167d1a708 --- /dev/null +++ b/test_regress/t/t_fourstate_redxor.v @@ -0,0 +1,34 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +`ifdef VERILATOR +`define IMPURE_ONE ($c(1)) +`else +`define IMPURE_ONE (|($random | $random)) +`endif + +module t; + function integer f(integer x); + if (`IMPURE_ONE) return x; + return 'x; + endfunction + initial begin + if (^f(0) !== 0) $stop; + if (^f(1) !== 1) $stop; + if (^f('x) !== 'x) $stop; + if (^f('z) !== 'x) $stop; + if (^f('b0000z0000) !== 'x) $stop; + if (^f('b0000x0000) !== 'x) $stop; + if (^f('b0000z0010) !== 'x) $stop; + if (^f('b0000x0100) !== 'x) $stop; + if (^f('b0000z0011) !== 'x) $stop; + if (^f('b0000x0101) !== 'x) $stop; + if (^f('b000000011) !== 0) $stop; + if (^f('b000000101) !== 0) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_fourstate_replicate.py b/test_regress/t/t_fourstate_replicate.py new file mode 100755 index 000000000..5a1741a85 --- /dev/null +++ b/test_regress/t/t_fourstate_replicate.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.twostate_capable = False + +test.compile(verilator_flags2=['--binary']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fourstate_replicate.v b/test_regress/t/t_fourstate_replicate.v new file mode 100644 index 000000000..04601e613 --- /dev/null +++ b/test_regress/t/t_fourstate_replicate.v @@ -0,0 +1,43 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +`ifdef VERILATOR +`define IMPURE_ONE ($c(1)) +`else +`define IMPURE_ONE (|($random | $random)) +`endif + +module t; + function logic f(logic x); + if (`IMPURE_ONE) return x; + return 'x; + endfunction + + initial begin + if ({1{f(1'b0)}} !== 1'b0) $stop; + if ({1{f(1'b1)}} !== 1'b1) $stop; + if ({1{f(1'bx)}} !== 1'bx) $stop; + if ({1{f(1'bz)}} !== 1'bz) $stop; + + if ({2{f(1'b0)}} !== 2'b00) $stop; + if ({2{f(1'b1)}} !== 2'b11) $stop; + if ({2{f(1'bx)}} !== 2'bxx) $stop; + if ({2{f(1'bz)}} !== 2'bzz) $stop; + + if ({3{f(1'b0)}} !== 3'b000) $stop; + if ({3{f(1'b1)}} !== 3'b111) $stop; + if ({3{f(1'bx)}} !== 3'bxxx) $stop; + if ({3{f(1'bz)}} !== 3'bzzz) $stop; + + if ({4{f(1'b0)}} !== 4'b0000) $stop; + if ({4{f(1'b1)}} !== 4'b1111) $stop; + if ({4{f(1'bx)}} !== 4'bxxxx) $stop; + if ({4{f(1'bz)}} !== 4'bzzzz) $stop; + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_fourstate_sel.out b/test_regress/t/t_fourstate_sel.out new file mode 100644 index 000000000..acc0a9ed7 --- /dev/null +++ b/test_regress/t/t_fourstate_sel.out @@ -0,0 +1,23 @@ +0: 0 +1: z +2: x +3: 1 +4: x +y: z +z: 0 +w: x +a: 1 +b: 1 +c: x +0: 0 +1: 0 +2: 0 +3: 1 +4: 1 +y: 0 +z: 0 +w: 0 +a: 1 +b: 1 +c: 0 +*-* All Finished *-* diff --git a/test_regress/t/t_fourstate_sel.py b/test_regress/t/t_fourstate_sel.py new file mode 100755 index 000000000..212e051c4 --- /dev/null +++ b/test_regress/t/t_fourstate_sel.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.twostate_capable = False + +test.compile(verilator_flags2=['--binary', '-Wno-WIDTHEXPAND', '-Wno-WIDTHTRUNC']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fourstate_sel.v b/test_regress/t/t_fourstate_sel.v new file mode 100644 index 000000000..c0579f525 --- /dev/null +++ b/test_regress/t/t_fourstate_sel.v @@ -0,0 +1,100 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +`ifdef VERILATOR +`define IMPURE_ONE ($c(1)) +`else +`define IMPURE_ONE (|($random | $random)) +`endif + +module t; + function logic f(logic a); + if (a === 1'b1) $write("1"); + else if (a === 1'b0) $write("0"); + else if (a === 1'bx) $write("x"); + else if (a === 1'bz) $write("z"); + else $stop; + $write("\n"); + return a; + endfunction + + function logic [5:0] bar(); + $write("Side effect\n"); + return 'b1x01xz; + endfunction + + bit sideEffect = 0; + function logic [13:0] foo(); + sideEffect = 1; + return 'z; + endfunction + + initial begin + static logic [4:0] x = 5'bx1xz0; + static bit [4:0] xx = 5'b11000; + static logic y = 1; + static bit [15:0] yy = `IMPURE_ONE; + static logic z = 0; + static logic [3:0] w = 7; + static logic [3:0] a = 3; + static bit [3:0] b = 3; + static bit [3:0] c = 7; + $write("0: "); + f(x[`IMPURE_ONE ? 0 : 'x]); + $write("1: "); + f(x[`IMPURE_ONE ? 1 : 'x]); + $write("2: "); + f(x[`IMPURE_ONE ? 2 : 'x]); + $write("3: "); + f(x[`IMPURE_ONE ? 3 : 'x]); + $write("4: "); + f(x[`IMPURE_ONE ? 4 : 'x]); + $write("y: "); + f(x[`IMPURE_ONE ? y : 'x]); + $write("z: "); + f(x[`IMPURE_ONE ? z : 'x]); + $write("w: "); + f(x[`IMPURE_ONE ? w : 'x]); + $write("a: "); + f(x[`IMPURE_ONE ? a : 'x]); + $write("b: "); + f(x[`IMPURE_ONE ? b : 0]); + $write("c: "); + f(x[`IMPURE_ONE ? c : 'x]); + $write("0: "); + f(xx[`IMPURE_ONE ? 0 : 'x]); + $write("1: "); + f(xx[`IMPURE_ONE ? 1 : 'x]); + $write("2: "); + f(xx[`IMPURE_ONE ? 2 : 'x]); + $write("3: "); + f(xx[`IMPURE_ONE ? 3 : 'x]); + $write("4: "); + f(xx[`IMPURE_ONE ? 4 : 'x]); + $write("y: "); + f(xx[`IMPURE_ONE ? y : 'x]); + $write("z: "); + f(xx[`IMPURE_ONE ? z : 'x]); + $write("w: "); + f(xx[`IMPURE_ONE ? w : 'x]); + $write("a: "); + f(xx[`IMPURE_ONE ? a : 'x]); + $write("b: "); + f(xx[`IMPURE_ONE ? b : 'x]); + $write("c: "); + f(xx[`IMPURE_ONE ? c : 'x]); + if (xx[yy] !== 0) $stop; + if (x[yy] !== 'z) $stop; + // verilator lint_off SELRANGE + if (foo() [101] !== 'x) $stop; + if (x[7] !== 'x) $stop; + if (xx[7] !== 0) $stop; + // verilator lint_on SELRANGE + if (sideEffect !== 1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_fourstate_shift.py b/test_regress/t/t_fourstate_shift.py new file mode 100755 index 000000000..5a1741a85 --- /dev/null +++ b/test_regress/t/t_fourstate_shift.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.twostate_capable = False + +test.compile(verilator_flags2=['--binary']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fourstate_shift.v b/test_regress/t/t_fourstate_shift.v new file mode 100644 index 000000000..911d1b577 --- /dev/null +++ b/test_regress/t/t_fourstate_shift.v @@ -0,0 +1,39 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +`ifdef VERILATOR +`define IMPURE_ONE ($c(1)) +`else +`define IMPURE_ONE (|($random | $random)) +`endif + +module t; + function integer f(integer x); + if (`IMPURE_ONE) return x; + return 'x; + endfunction + + initial begin + if ((f('b1) << f('b0)) !== 'b1) $stop; + if ((f('b1) << f('b1)) !== 'b10) $stop; + if ((f('b1) << f('b10)) !== 'b100) $stop; + if ((f('b0x01) << f('b10)) !== 'b0x0100) $stop; + if ((f('b0zx01) << f('b10)) !== 'b0zx0100) $stop; + if ((f('b1) << f('b1x)) !== 'x) $stop; + if ((f('b1) << f('b1z)) !== 'x) $stop; + + if ((f('b1) >> f('b0)) !== 'b1) $stop; + if ((f('b10) >> f('b0)) !== 'b10) $stop; + if ((f('b1) >> f('b1)) !== 'b0) $stop; + if ((f('b100) >> f('b10)) !== 'b1) $stop; + if ((f('b0x010000) >> f('b10)) !== 'b0x0100) $stop; + if ((f('b0zx01) >> f('b10)) !== 'b0zx) $stop; + if ((f('b1) >> f('b1x)) !== 'x) $stop; + if ((f('b1) >> f('b1z)) !== 'x) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_fourstate_twostate.py b/test_regress/t/t_fourstate_twostate.py new file mode 100755 index 000000000..5a1741a85 --- /dev/null +++ b/test_regress/t/t_fourstate_twostate.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.twostate_capable = False + +test.compile(verilator_flags2=['--binary']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fourstate_twostate.v b/test_regress/t/t_fourstate_twostate.v new file mode 100644 index 000000000..8ae5119f3 --- /dev/null +++ b/test_regress/t/t_fourstate_twostate.v @@ -0,0 +1,32 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +class Foo; + task test(logic x, bit y, bit z); + if (x !== 'z) $stop; + if (y !== 0) $stop; + if (z !== 0) $stop; + endtask + + function bit foo(bit z); + if (!z) $stop; + return 0; + endfunction + + function bit bar(logic x, bit y, bit z); + return x || !y || z || (foo(z) || foo(z)); + endfunction +endclass + +module t; + initial begin + static Foo foo = new; + foo.test('z, 'z, 0); + if (foo.bar('z, 'z, 0) !== 1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_fourstate_x_initial_assign.out b/test_regress/t/t_fourstate_x_initial_assign.out new file mode 100644 index 000000000..22096e3dd --- /dev/null +++ b/test_regress/t/t_fourstate_x_initial_assign.out @@ -0,0 +1,4 @@ +%Error: --x-initial has no sense with --fourstate + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error: --x-assign has no sense with --fourstate +%Error: Exiting due to diff --git a/test_regress/t/t_fourstate_x_initial_assign.py b/test_regress/t/t_fourstate_x_initial_assign.py new file mode 100755 index 000000000..6cc3a435c --- /dev/null +++ b/test_regress/t/t_fourstate_x_initial_assign.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.twostate_capable = False + +test.top_filename = "t_fourstate_fourstate_unsup.v" + +test.lint(verilator_flags2=['--x-assign', '0', '--x-initial', '0'], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fourstate_zero_top_ports.py b/test_regress/t/t_fourstate_zero_top_ports.py new file mode 100755 index 000000000..3879bf8e9 --- /dev/null +++ b/test_regress/t/t_fourstate_zero_top_ports.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.twostate_capable = False + +test.compile(verilator_flags2=['--binary', '--zero-top-ports', '-DINPUT_VAL=0']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fourstate_zero_top_ports.v b/test_regress/t/t_fourstate_zero_top_ports.v new file mode 100644 index 000000000..4faa6ecff --- /dev/null +++ b/test_regress/t/t_fourstate_zero_top_ports.v @@ -0,0 +1,13 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +module t(input foo); + initial begin + if (foo !== `INPUT_VAL) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_fourstate_zero_top_ports_default.py b/test_regress/t/t_fourstate_zero_top_ports_default.py new file mode 100755 index 000000000..abc9f01cb --- /dev/null +++ b/test_regress/t/t_fourstate_zero_top_ports_default.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') + +test.top_filename = 't_fourstate_zero_top_ports.v' + +test.compile(verilator_flags2=['--binary', '-DINPUT_VAL=0']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fourstate_zero_top_ports_twostate.out b/test_regress/t/t_fourstate_zero_top_ports_twostate.out new file mode 100644 index 000000000..668ef3d8d --- /dev/null +++ b/test_regress/t/t_fourstate_zero_top_ports_twostate.out @@ -0,0 +1,3 @@ +%Error: --zero-top-ports and --no-zero-top-ports shall be used only with --fourstate + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error: Exiting due to diff --git a/test_regress/t/t_fourstate_zero_top_ports_twostate.py b/test_regress/t/t_fourstate_zero_top_ports_twostate.py new file mode 100755 index 000000000..c5be5f968 --- /dev/null +++ b/test_regress/t/t_fourstate_zero_top_ports_twostate.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') + +test.top_filename = 't_fourstate_zero_top_ports.v' + +test.compile(verilator_flags2=['--binary', '--no-fourstate', '--zero-top-ports', '-DINPUT_VAL=0'], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fsm_duplicate.py b/test_regress/t/t_fsm_duplicate.py index 7f4205522..6d528775d 100755 --- a/test_regress/t/t_fsm_duplicate.py +++ b/test_regress/t/t_fsm_duplicate.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--coverage -Wno-PINMISSING"]) diff --git a/test_regress/t/t_fsm_register_wrapper.py b/test_regress/t/t_fsm_register_wrapper.py index e92b74275..d2c2fc7a1 100755 --- a/test_regress/t/t_fsm_register_wrapper.py +++ b/test_regress/t/t_fsm_register_wrapper.py @@ -12,6 +12,7 @@ import os import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--cc --coverage-fsm t/t_fsm_register_wrapper.vlt']) diff --git a/test_regress/t/t_fsm_register_wrapper_noinline.py b/test_regress/t/t_fsm_register_wrapper_noinline.py index e14e8228c..c57edf448 100755 --- a/test_regress/t/t_fsm_register_wrapper_noinline.py +++ b/test_regress/t/t_fsm_register_wrapper_noinline.py @@ -12,6 +12,7 @@ import os import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile( verilator_flags2=['--cc --coverage-fsm -fno-inline t/t_fsm_register_wrapper_noinline.vlt']) diff --git a/test_regress/t/t_fsm_register_wrapper_warn_bad.py b/test_regress/t/t_fsm_register_wrapper_warn_bad.py index 2ff9f32f0..b21182261 100755 --- a/test_regress/t/t_fsm_register_wrapper_warn_bad.py +++ b/test_regress/t/t_fsm_register_wrapper_warn_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint( verilator_flags2=["--coverage-fsm", "-fno-inline", "t/t_fsm_register_wrapper_warn_bad.vlt"], diff --git a/test_regress/t/t_fsmmulti_combo_multi_warn_bad.py b/test_regress/t/t_fsmmulti_combo_multi_warn_bad.py index 9359d4535..a0f6c296e 100755 --- a/test_regress/t/t_fsmmulti_combo_multi_warn_bad.py +++ b/test_regress/t/t_fsmmulti_combo_multi_warn_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(verilator_flags2=["--coverage-fsm"], fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_fsmmulti_same_bad.py b/test_regress/t/t_fsmmulti_same_bad.py index 7982b1bdd..b0cd4cd02 100755 --- a/test_regress/t/t_fsmmulti_same_bad.py +++ b/test_regress/t/t_fsmmulti_same_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False # Multiple supported case candidates on the same state variable in one # always_ff now warn and keep only the first candidate instrumented. Different- diff --git a/test_regress/t/t_fsmmulti_warn_bad.py b/test_regress/t/t_fsmmulti_warn_bad.py index 5f224eae6..e2b99cd1a 100755 --- a/test_regress/t/t_fsmmulti_warn_bad.py +++ b/test_regress/t/t_fsmmulti_warn_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(verilator_flags2=["--coverage-fsm"], fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_fsmmulti_warn_off.py b/test_regress/t/t_fsmmulti_warn_off.py index 018b61822..a86ae4cdc 100755 --- a/test_regress/t/t_fsmmulti_warn_off.py +++ b/test_regress/t/t_fsmmulti_warn_off.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(verilator_flags2=["--coverage-line"]) test.file_grep_not(test.compile_log_filename, r"FSMMULTI") diff --git a/test_regress/t/t_func.py b/test_regress/t/t_func.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_func.py +++ b/test_regress/t/t_func.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_func_automatic_clear.py b/test_regress/t/t_func_automatic_clear.py index 84b274f68..17424b42f 100755 --- a/test_regress/t/t_func_automatic_clear.py +++ b/test_regress/t/t_func_automatic_clear.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_func_check.py b/test_regress/t/t_func_check.py index af8b14903..d2cd6405e 100755 --- a/test_regress/t/t_func_check.py +++ b/test_regress/t/t_func_check.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.verilated_randReset = 1 test.compile() diff --git a/test_regress/t/t_func_complex.py b/test_regress/t/t_func_complex.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_func_complex.py +++ b/test_regress/t/t_func_complex.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_func_complex_noinl.py b/test_regress/t/t_func_complex_noinl.py index b50a4cab1..e4491b752 100755 --- a/test_regress/t/t_func_complex_noinl.py +++ b/test_regress/t/t_func_complex_noinl.py @@ -12,6 +12,7 @@ test.top_filename = "t/t_func_complex.v" import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(v_flags2=["+define+TEST_NOINLINE"]) diff --git a/test_regress/t/t_func_const.py b/test_regress/t/t_func_const.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_func_const.py +++ b/test_regress/t/t_func_const.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_func_crc.py b/test_regress/t/t_func_crc.py index 0f6ce0c75..303835859 100755 --- a/test_regress/t/t_func_crc.py +++ b/test_regress/t/t_func_crc.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile( # We have deep expressions we want to test diff --git a/test_regress/t/t_func_dotted_inl0.py b/test_regress/t/t_func_dotted_inl0.py index 97e26834a..1c541da36 100755 --- a/test_regress/t/t_func_dotted_inl0.py +++ b/test_regress/t/t_func_dotted_inl0.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_func_dotted.v" out_filename = test.obj_dir + "/V" + test.name + ".tree.json" diff --git a/test_regress/t/t_func_dotted_inl0_vlt.py b/test_regress/t/t_func_dotted_inl0_vlt.py index 20d633489..0abe4f340 100755 --- a/test_regress/t/t_func_dotted_inl0_vlt.py +++ b/test_regress/t/t_func_dotted_inl0_vlt.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_func_dotted.v" out_filename = test.obj_dir + "/V" + test.name + ".tree.json" diff --git a/test_regress/t/t_func_dotted_inl1.py b/test_regress/t/t_func_dotted_inl1.py index 4f57eb710..ad05e65b1 100755 --- a/test_regress/t/t_func_dotted_inl1.py +++ b/test_regress/t/t_func_dotted_inl1.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_func_dotted.v" out_filename = test.obj_dir + "/V" + test.name + ".tree.json" diff --git a/test_regress/t/t_func_dotted_inl1_vlt.py b/test_regress/t/t_func_dotted_inl1_vlt.py index 5051ce0ad..bf826972e 100755 --- a/test_regress/t/t_func_dotted_inl1_vlt.py +++ b/test_regress/t/t_func_dotted_inl1_vlt.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_func_dotted.v" out_filename = test.obj_dir + "/V" + test.name + ".tree.json" diff --git a/test_regress/t/t_func_dotted_inl2.py b/test_regress/t/t_func_dotted_inl2.py index 958c06200..a15ecb867 100755 --- a/test_regress/t/t_func_dotted_inl2.py +++ b/test_regress/t/t_func_dotted_inl2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_func_dotted.v" out_filename = test.obj_dir + "/V" + test.name + ".tree.json" diff --git a/test_regress/t/t_func_dotted_inl2_vlt.py b/test_regress/t/t_func_dotted_inl2_vlt.py index 6b58a6ae3..5ed61fc9f 100755 --- a/test_regress/t/t_func_dotted_inl2_vlt.py +++ b/test_regress/t/t_func_dotted_inl2_vlt.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_func_dotted.v" out_filename = test.obj_dir + "/V" + test.name + ".tree.json" diff --git a/test_regress/t/t_func_endian.py b/test_regress/t/t_func_endian.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_func_endian.py +++ b/test_regress/t/t_func_endian.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_func_gen.py b/test_regress/t/t_func_gen.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_func_gen.py +++ b/test_regress/t/t_func_gen.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_func_grey.py b/test_regress/t/t_func_grey.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_func_grey.py +++ b/test_regress/t/t_func_grey.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_func_lib_sub.py b/test_regress/t/t_func_lib_sub.py index ce610dcf1..c68a430bc 100755 --- a/test_regress/t/t_func_lib_sub.py +++ b/test_regress/t/t_func_lib_sub.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.compile(verilator_flags2=['--no-timing']) diff --git a/test_regress/t/t_func_lib_sub_timing.py b/test_regress/t/t_func_lib_sub_timing.py index 706390916..6aed8db1d 100755 --- a/test_regress/t/t_func_lib_sub_timing.py +++ b/test_regress/t/t_func_lib_sub_timing.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') # UNOPTTHREADS in vltmt +test.fourstate_capable = False test.top_filename = "t/t_func_lib_sub.v" test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_func_many_return.py b/test_regress/t/t_func_many_return.py index 09e1e8923..0cab4711b 100755 --- a/test_regress/t/t_func_many_return.py +++ b/test_regress/t/t_func_many_return.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--comp-limit-blocks 100"]) diff --git a/test_regress/t/t_func_noinl.py b/test_regress/t/t_func_noinl.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_func_noinl.py +++ b/test_regress/t/t_func_noinl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_func_outp.py b/test_regress/t/t_func_outp.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_func_outp.py +++ b/test_regress/t/t_func_outp.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_func_paramed.py b/test_regress/t/t_func_paramed.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_func_paramed.py +++ b/test_regress/t/t_func_paramed.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_func_public.py b/test_regress/t/t_func_public.py index b9e93fcc8..717246b88 100755 --- a/test_regress/t/t_func_public.py +++ b/test_regress/t/t_func_public.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['+define+VERILATOR_PUBLIC_TASKS']) diff --git a/test_regress/t/t_func_public.v b/test_regress/t/t_func_public.v index 301cd4e47..42f5dcba6 100644 --- a/test_regress/t/t_func_public.v +++ b/test_regress/t/t_func_public.v @@ -120,7 +120,7 @@ module tpub ( if (24'h11bca != got_long) $stop; $c("{ uint64_t qq; this->publicGetQuad(qq); this->got_quad=qq; }"); if (60'haaaa_bbbb_cccc != got_quad) $stop; - $c("{ EData gw[3]; this->publicGetWide(gw); VL_ASSIGN_W(72,this->got_wide,WDataInP::external(gw)); }"); + $c("{ EData gw[3]; this->publicGetWide(gw); VL_ASSIGN_W_TT(72,this->got_wide,WDataInP::external(gw)); }"); if (72'hac_abca_aaaa_bbbb_1234 != got_wide) $stop; //Below doesn't work, because we're calling it inside the loop that sets var_flop // if (12'h321 != var_flop) $stop; diff --git a/test_regress/t/t_func_public_trace.py b/test_regress/t/t_func_public_trace.py index 07719b2e0..000c16d01 100755 --- a/test_regress/t/t_func_public_trace.py +++ b/test_regress/t/t_func_public_trace.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_func_public.v" test.compile(verilator_flags2=["--trace-vcd"]) diff --git a/test_regress/t/t_func_redef.py b/test_regress/t/t_func_redef.py index 66009b455..52533feae 100755 --- a/test_regress/t/t_func_redef.py +++ b/test_regress/t/t_func_redef.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_func_ref_arg.py b/test_regress/t/t_func_ref_arg.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_func_ref_arg.py +++ b/test_regress/t/t_func_ref_arg.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_func_ref_arg_default.py b/test_regress/t/t_func_ref_arg_default.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_func_ref_arg_default.py +++ b/test_regress/t/t_func_ref_arg_default.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_func_ref_arg_default_noinl.py b/test_regress/t/t_func_ref_arg_default_noinl.py index f8a597ade..d17fbf240 100755 --- a/test_regress/t/t_func_ref_arg_default_noinl.py +++ b/test_regress/t/t_func_ref_arg_default_noinl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_func_ref_arg_default.v" test.compile(verilator_flags2=["--binary"], v_flags2=["+define+TEST_NOINLINE"]) diff --git a/test_regress/t/t_func_return_init.py b/test_regress/t/t_func_return_init.py index 8a938befd..a10e2547d 100755 --- a/test_regress/t/t_func_return_init.py +++ b/test_regress/t/t_func_return_init.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_func_sel.py b/test_regress/t/t_func_sel.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_func_sel.py +++ b/test_regress/t/t_func_sel.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_func_twocall.py b/test_regress/t/t_func_twocall.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_func_twocall.py +++ b/test_regress/t/t_func_twocall.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_func_twocall_noexpand.py b/test_regress/t/t_func_twocall_noexpand.py index ae6db56dd..ca7a7e6b8 100755 --- a/test_regress/t/t_func_twocall_noexpand.py +++ b/test_regress/t/t_func_twocall_noexpand.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_func_twocall.v" test.compile(verilator_flags2=['-fno-expand']) diff --git a/test_regress/t/t_func_under2.py b/test_regress/t/t_func_under2.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_func_under2.py +++ b/test_regress/t/t_func_under2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_func_uninit.py b/test_regress/t/t_func_uninit.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_func_uninit.py +++ b/test_regress/t/t_func_uninit.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_func_unit.py b/test_regress/t/t_func_unit.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_func_unit.py +++ b/test_regress/t/t_func_unit.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_func_unit_recursive.py b/test_regress/t/t_func_unit_recursive.py index 8a938befd..a10e2547d 100755 --- a/test_regress/t/t_func_unit_recursive.py +++ b/test_regress/t/t_func_unit_recursive.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_func_wide_out.py b/test_regress/t/t_func_wide_out.py index e8e85a995..f7de4a88e 100755 --- a/test_regress/t/t_func_wide_out.py +++ b/test_regress/t/t_func_wide_out.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["-Wno-WIDTHTRUNC"], v_flags2=["+define+T_FUNC_WIDE_OUT t/t_func_wide_out_c.cpp"]) diff --git a/test_regress/t/t_func_wide_out_bad.py b/test_regress/t/t_func_wide_out_bad.py index 71309d152..96739b0a1 100755 --- a/test_regress/t/t_func_wide_out_bad.py +++ b/test_regress/t/t_func_wide_out_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_func_wide_out.v" test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_func_wide_out_noinl.py b/test_regress/t/t_func_wide_out_noinl.py index 63c25c186..77f53d255 100755 --- a/test_regress/t/t_func_wide_out_noinl.py +++ b/test_regress/t/t_func_wide_out_noinl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t_func_wide_out.v" test.compile( diff --git a/test_regress/t/t_gantt_hier.py b/test_regress/t/t_gantt_hier.py index 28f6e1427..c906e8563 100755 --- a/test_regress/t/t_gantt_hier.py +++ b/test_regress/t/t_gantt_hier.py @@ -13,6 +13,7 @@ import vltest_bootstrap test.priority(30) test.scenarios('vlt_all') +test.fourstate_capable = False test.top_filename = "t/t_gantt.v" test.pli_filename = "t/t_gantt_c.cpp" diff --git a/test_regress/t/t_gate_array.py b/test_regress/t/t_gate_array.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_gate_array.py +++ b/test_regress/t/t_gate_array.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_gate_basic.py b/test_regress/t/t_gate_basic.py index 543805b26..a38495d88 100755 --- a/test_regress/t/t_gate_basic.py +++ b/test_regress/t/t_gate_basic.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--no-timing", "-Wno-SPECIFYIGN"]) diff --git a/test_regress/t/t_gate_basic_specify_bad.py b/test_regress/t/t_gate_basic_specify_bad.py index 203508fa3..c7e7fcb1c 100755 --- a/test_regress/t/t_gate_basic_specify_bad.py +++ b/test_regress/t/t_gate_basic_specify_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = 't/t_gate_basic.v' test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_gate_basic_timing.py b/test_regress/t/t_gate_basic_timing.py index d6b5b15df..16b81f1d4 100755 --- a/test_regress/t/t_gate_basic_timing.py +++ b/test_regress/t/t_gate_basic_timing.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_gate_basic.v" test.compile(verilator_flags2=["--binary --timescale 10ns/1ns -Wno-RISEFALLDLY -Wno-SPECIFYIGN"]) diff --git a/test_regress/t/t_gate_chained.py b/test_regress/t/t_gate_chained.py index ddf8bef62..4a66b4440 100755 --- a/test_regress/t/t_gate_chained.py +++ b/test_regress/t/t_gate_chained.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = test.obj_dir + "/t_gate_chained.v" diff --git a/test_regress/t/t_gate_delay_unsup.py b/test_regress/t/t_gate_delay_unsup.py index f56f1b87d..f203ef9a9 100755 --- a/test_regress/t/t_gate_delay_unsup.py +++ b/test_regress/t/t_gate_delay_unsup.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_gate_basic.v" test.compile( diff --git a/test_regress/t/t_gate_elim_cycle.py b/test_regress/t/t_gate_elim_cycle.py index 0379f0dd0..945124978 100755 --- a/test_regress/t/t_gate_elim_cycle.py +++ b/test_regress/t/t_gate_elim_cycle.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_gate_fdup.py b/test_regress/t/t_gate_fdup.py index d63392a97..500a59b01 100755 --- a/test_regress/t/t_gate_fdup.py +++ b/test_regress/t/t_gate_fdup.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_gate_implicit.py b/test_regress/t/t_gate_implicit.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_gate_implicit.py +++ b/test_regress/t/t_gate_implicit.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_gate_inline_wide_exclude_multiple.py b/test_regress/t/t_gate_inline_wide_exclude_multiple.py index 2bf5b1241..e45a0c116 100755 --- a/test_regress/t/t_gate_inline_wide_exclude_multiple.py +++ b/test_regress/t/t_gate_inline_wide_exclude_multiple.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(verilator_flags2=['--stats', '--expand-limit 5']) diff --git a/test_regress/t/t_gate_inline_wide_noexclude_arraysel.py b/test_regress/t/t_gate_inline_wide_noexclude_arraysel.py index 15370ae7c..39e0ac550 100755 --- a/test_regress/t/t_gate_inline_wide_noexclude_arraysel.py +++ b/test_regress/t/t_gate_inline_wide_noexclude_arraysel.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(verilator_flags2=['--stats', '--expand-limit 5', '-fno-dfg']) diff --git a/test_regress/t/t_gate_inline_wide_noexclude_const.py b/test_regress/t/t_gate_inline_wide_noexclude_const.py index cb6511e21..e84171ac9 100755 --- a/test_regress/t/t_gate_inline_wide_noexclude_const.py +++ b/test_regress/t/t_gate_inline_wide_noexclude_const.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(verilator_flags2=['--stats', '--expand-limit 5']) diff --git a/test_regress/t/t_gate_ormux.py b/test_regress/t/t_gate_ormux.py index 65a710e42..6aa82c19f 100755 --- a/test_regress/t/t_gate_ormux.py +++ b/test_regress/t/t_gate_ormux.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.cycles = (100000000 if test.benchmark else 100) test.sim_time = test.cycles * 10 + 1000 diff --git a/test_regress/t/t_gate_primitives_implicit_net.py b/test_regress/t/t_gate_primitives_implicit_net.py index b93d271a7..be1bfb714 100755 --- a/test_regress/t/t_gate_primitives_implicit_net.py +++ b/test_regress/t/t_gate_primitives_implicit_net.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(verilator_flags2=["-Wno-fatal --no-skip-identical"], expect_filename=test.golden_filename) diff --git a/test_regress/t/t_gate_tree.py b/test_regress/t/t_gate_tree.py index 685e592d7..3b6b1ff90 100755 --- a/test_regress/t/t_gate_tree.py +++ b/test_regress/t/t_gate_tree.py @@ -12,6 +12,7 @@ import collections import math test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = test.obj_dir + "/t_gate_tree.v" test.cycles = (1000000 if test.benchmark else 100) test.sim_time = test.cycles * 10 + 1000 diff --git a/test_regress/t/t_gen_alw.py b/test_regress/t/t_gen_alw.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_gen_alw.py +++ b/test_regress/t/t_gen_alw.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_gen_assign.py b/test_regress/t/t_gen_assign.py index fabbdb10f..9295a194b 100755 --- a/test_regress/t/t_gen_assign.py +++ b/test_regress/t/t_gen_assign.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_gen_for.py b/test_regress/t/t_gen_for.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_gen_for.py +++ b/test_regress/t/t_gen_for.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_gen_for_shuffle.py b/test_regress/t/t_gen_for_shuffle.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_gen_for_shuffle.py +++ b/test_regress/t/t_gen_for_shuffle.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_gen_forif.py b/test_regress/t/t_gen_forif.py index ab0e2f0f5..80cded1c6 100755 --- a/test_regress/t/t_gen_forif.py +++ b/test_regress/t/t_gen_forif.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(nc_flags2=['+access+r'], verilator_flags2=["--no-timing"]) diff --git a/test_regress/t/t_gen_genblk_noinl.py b/test_regress/t/t_gen_genblk_noinl.py index 6412dc2e4..0874d9b68 100755 --- a/test_regress/t/t_gen_genblk_noinl.py +++ b/test_regress/t/t_gen_genblk_noinl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t_gen_genblk.v" test.golden_filename = "t/t_gen_genblk.out" test.sim_time = 11000 diff --git a/test_regress/t/t_gen_inc.py b/test_regress/t/t_gen_inc.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_gen_inc.py +++ b/test_regress/t/t_gen_inc.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_gen_index.py b/test_regress/t/t_gen_index.py index 66009b455..52533feae 100755 --- a/test_regress/t/t_gen_index.py +++ b/test_regress/t/t_gen_index.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_gen_local.py b/test_regress/t/t_gen_local.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_gen_local.py +++ b/test_regress/t/t_gen_local.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_gen_missing.py b/test_regress/t/t_gen_missing.py index 6e83f4dbb..a6a541413 100755 --- a/test_regress/t/t_gen_missing.py +++ b/test_regress/t/t_gen_missing.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(v_flags2=['+define+T_GEN_MISSING']) diff --git a/test_regress/t/t_gen_missing_bad.py b/test_regress/t/t_gen_missing_bad.py index a13895572..e7f273300 100755 --- a/test_regress/t/t_gen_missing_bad.py +++ b/test_regress/t/t_gen_missing_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_gen_missing.v" test.lint(v_flags2=['+define+T_GEN_MISSING_BAD'], fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_gen_self_return.py b/test_regress/t/t_gen_self_return.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_gen_self_return.py +++ b/test_regress/t/t_gen_self_return.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_hier_block.py b/test_regress/t/t_hier_block.py index 294b5139a..5ba4e8d3c 100755 --- a/test_regress/t/t_hier_block.py +++ b/test_regress/t/t_hier_block.py @@ -11,6 +11,7 @@ import vltest_bootstrap test.priority(30) test.scenarios('vlt_all') +test.fourstate_capable = False # stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. test.clean_objs() diff --git a/test_regress/t/t_hier_block0_bad.py b/test_regress/t/t_hier_block0_bad.py index 6199d736e..73a872ef6 100755 --- a/test_regress/t/t_hier_block0_bad.py +++ b/test_regress/t/t_hier_block0_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(fails=True, verilator_flags2=['--hierarchical'], expect_filename=test.golden_filename) diff --git a/test_regress/t/t_hier_block1_bad.py b/test_regress/t/t_hier_block1_bad.py index 0b4856f98..d897c5842 100755 --- a/test_regress/t/t_hier_block1_bad.py +++ b/test_regress/t/t_hier_block1_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(fails=True, verilator_flags2=['--hierarchical'], expect_filename=test.golden_filename) diff --git a/test_regress/t/t_hier_block_binary.py b/test_regress/t/t_hier_block_binary.py index 775bd9b18..20b22e50d 100755 --- a/test_regress/t/t_hier_block_binary.py +++ b/test_regress/t/t_hier_block_binary.py @@ -11,6 +11,7 @@ import vltest_bootstrap test.priority(30) test.scenarios('vlt_all') +test.fourstate_capable = False test.top_filename = "t/t_hier_block.v" # stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. diff --git a/test_regress/t/t_hier_block_chained.py b/test_regress/t/t_hier_block_chained.py index 41e89faab..59ad07e18 100755 --- a/test_regress/t/t_hier_block_chained.py +++ b/test_regress/t/t_hier_block_chained.py @@ -11,6 +11,7 @@ import vltest_bootstrap test.priority(30) test.scenarios('vlt_all') +test.fourstate_capable = False test.cycles = (int(test.benchmark) if test.benchmark else 100000) test.sim_time = test.cycles * 10 + 1000 diff --git a/test_regress/t/t_hier_block_import.py b/test_regress/t/t_hier_block_import.py index 92c27cdf9..e2749bc31 100755 --- a/test_regress/t/t_hier_block_import.py +++ b/test_regress/t/t_hier_block_import.py @@ -11,6 +11,7 @@ import vltest_bootstrap test.priority(30) test.scenarios('vlt_all') +test.fourstate_capable = False # stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. test.clean_objs() diff --git a/test_regress/t/t_hier_block_import_cmake.py b/test_regress/t/t_hier_block_import_cmake.py index fb565ef8d..c6429c8e8 100755 --- a/test_regress/t/t_hier_block_import_cmake.py +++ b/test_regress/t/t_hier_block_import_cmake.py @@ -11,6 +11,7 @@ import vltest_bootstrap test.priority(30) test.scenarios('vlt_all') +test.fourstate_capable = False # CMake build executes from a different directory than the Make one. test.top_filename = os.path.abspath("t/t_hier_block_import.v") diff --git a/test_regress/t/t_hier_block_int.py b/test_regress/t/t_hier_block_int.py index 2377a6597..f61c89a0d 100755 --- a/test_regress/t/t_hier_block_int.py +++ b/test_regress/t/t_hier_block_int.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--stats', '--hierarchical']) diff --git a/test_regress/t/t_hier_block_libmod.py b/test_regress/t/t_hier_block_libmod.py index 6ab133aa1..3ea70f26d 100755 --- a/test_regress/t/t_hier_block_libmod.py +++ b/test_regress/t/t_hier_block_libmod.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.compile(verilator_flags2=[ '--hierarchical', '-y', test.t_dir + '/t_flag_relinc_dir/chip', '+incdir+' + test.t_dir + diff --git a/test_regress/t/t_hier_block_nohier.py b/test_regress/t/t_hier_block_nohier.py index a5d3dd14e..22f1acf3f 100755 --- a/test_regress/t/t_hier_block_nohier.py +++ b/test_regress/t/t_hier_block_nohier.py @@ -16,6 +16,7 @@ import vltest_bootstrap test.clean_objs() test.scenarios('vlt_all') +test.fourstate_capable = False test.top_filename = "t/t_hier_block.v" # CI environment offers 2 VCPUs, 2 thread setting causes the following warning. diff --git a/test_regress/t/t_hier_block_perf.py b/test_regress/t/t_hier_block_perf.py index ea6d40c8b..a7a7ea440 100755 --- a/test_regress/t/t_hier_block_perf.py +++ b/test_regress/t/t_hier_block_perf.py @@ -11,6 +11,7 @@ import vltest_bootstrap test.priority(30) test.scenarios('vlt_all') +test.fourstate_capable = False test.cycles = (int(test.benchmark) if test.benchmark else 100000) test.sim_time = test.cycles * 10 + 1000 diff --git a/test_regress/t/t_hier_block_sc.py b/test_regress/t/t_hier_block_sc.py index 0baec1b0f..e2f05ceac 100755 --- a/test_regress/t/t_hier_block_sc.py +++ b/test_regress/t/t_hier_block_sc.py @@ -11,6 +11,7 @@ import vltest_bootstrap test.priority(30) test.scenarios('vlt_all') +test.fourstate_capable = False test.top_filename = "t/t_hier_block.v" # CI environment offers 2 VCPUs, 2 thread setting causes the following warning. diff --git a/test_regress/t/t_hier_block_signed_logic.py b/test_regress/t/t_hier_block_signed_logic.py index cb667c1ec..48b2b3357 100755 --- a/test_regress/t/t_hier_block_signed_logic.py +++ b/test_regress/t/t_hier_block_signed_logic.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--stats', '--hierarchical']) diff --git a/test_regress/t/t_hier_block_struct.py b/test_regress/t/t_hier_block_struct.py index 86f31f21b..c7a01a5be 100755 --- a/test_regress/t/t_hier_block_struct.py +++ b/test_regress/t/t_hier_block_struct.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--hierarchical']) diff --git a/test_regress/t/t_hier_block_struct_nohier.py b/test_regress/t/t_hier_block_struct_nohier.py index f212303f1..44c775b20 100755 --- a/test_regress/t/t_hier_block_struct_nohier.py +++ b/test_regress/t/t_hier_block_struct_nohier.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_hier_block_struct.v" test.compile() diff --git a/test_regress/t/t_hier_block_threads_bad.py b/test_regress/t/t_hier_block_threads_bad.py index f26c32f77..9a9d4d823 100755 --- a/test_regress/t/t_hier_block_threads_bad.py +++ b/test_regress/t/t_hier_block_threads_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vltmt') +test.fourstate_capable = False test.compile(fails=True, verilator_flags2=['t/t_hier_block_threads_bad.vlt', '-DWORKERS=8', '--hierarchical'], diff --git a/test_regress/t/t_hier_block_type_param.py b/test_regress/t/t_hier_block_type_param.py index 1032275a2..ae8c64313 100755 --- a/test_regress/t/t_hier_block_type_param.py +++ b/test_regress/t/t_hier_block_type_param.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--hierarchical']) diff --git a/test_regress/t/t_hier_block_type_param_multiple.py b/test_regress/t/t_hier_block_type_param_multiple.py index 7db19f9cc..d700400ae 100755 --- a/test_regress/t/t_hier_block_type_param_multiple.py +++ b/test_regress/t/t_hier_block_type_param_multiple.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--hierarchical']) diff --git a/test_regress/t/t_hier_block_type_param_multiple_instances.py b/test_regress/t/t_hier_block_type_param_multiple_instances.py index 7db19f9cc..d700400ae 100755 --- a/test_regress/t/t_hier_block_type_param_multiple_instances.py +++ b/test_regress/t/t_hier_block_type_param_multiple_instances.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--hierarchical']) diff --git a/test_regress/t/t_hier_block_type_param_nested.py b/test_regress/t/t_hier_block_type_param_nested.py index 7db19f9cc..d700400ae 100755 --- a/test_regress/t/t_hier_block_type_param_nested.py +++ b/test_regress/t/t_hier_block_type_param_nested.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--hierarchical']) diff --git a/test_regress/t/t_hier_block_type_param_notfound_bad.py b/test_regress/t/t_hier_block_type_param_notfound_bad.py index 111841bf4..e32b960d0 100755 --- a/test_regress/t/t_hier_block_type_param_notfound_bad.py +++ b/test_regress/t/t_hier_block_type_param_notfound_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_hier_block_type_param.v" test.compile(verilator_flags2=["--hierarchical-params-file", "/does-not-exist"], diff --git a/test_regress/t/t_hier_block_typedef_param.py b/test_regress/t/t_hier_block_typedef_param.py index 234927d29..c68eeb936 100755 --- a/test_regress/t/t_hier_block_typedef_param.py +++ b/test_regress/t/t_hier_block_typedef_param.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_typedef_param.v" test.compile(verilator_flags2=["--hierarchical"]) diff --git a/test_regress/t/t_hier_block_vlt.py b/test_regress/t/t_hier_block_vlt.py index 90f2fdacd..8e27bdfca 100755 --- a/test_regress/t/t_hier_block_vlt.py +++ b/test_regress/t/t_hier_block_vlt.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.top_filename = "t/t_hier_block.v" # stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. diff --git a/test_regress/t/t_hier_bynum.py b/test_regress/t/t_hier_bynum.py index e470c0d7d..bdddd4b3b 100755 --- a/test_regress/t/t_hier_bynum.py +++ b/test_regress/t/t_hier_bynum.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.compile(v_flags2=['t/t_hier_block.cpp'], verilator_flags2=['--hierarchical'], diff --git a/test_regress/t/t_hier_parm_under.py b/test_regress/t/t_hier_parm_under.py index e9ae8f7df..84a35696b 100755 --- a/test_regress/t/t_hier_parm_under.py +++ b/test_regress/t/t_hier_parm_under.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False # stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. test.clean_objs() diff --git a/test_regress/t/t_if_same_bad.py b/test_regress/t/t_if_same_bad.py index 5fc1c82aa..cdba19313 100755 --- a/test_regress/t/t_if_same_bad.py +++ b/test_regress/t/t_if_same_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint( # expect_filename = test.golden_filename diff --git a/test_regress/t/t_if_swap.py b/test_regress/t/t_if_swap.py index 66009b455..52533feae 100755 --- a/test_regress/t/t_if_swap.py +++ b/test_regress/t/t_if_swap.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_iface_array_multidim.py b/test_regress/t/t_iface_array_multidim.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_iface_array_multidim.py +++ b/test_regress/t/t_iface_array_multidim.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_iface_array_multidim_3d.py b/test_regress/t/t_iface_array_multidim_3d.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_iface_array_multidim_3d.py +++ b/test_regress/t/t_iface_array_multidim_3d.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_iface_array_multidim_3d_port.py b/test_regress/t/t_iface_array_multidim_3d_port.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_iface_array_multidim_3d_port.py +++ b/test_regress/t/t_iface_array_multidim_3d_port.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_iface_array_multidim_hier.py b/test_regress/t/t_iface_array_multidim_hier.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_iface_array_multidim_hier.py +++ b/test_regress/t/t_iface_array_multidim_hier.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_iface_array_multidim_modport.py b/test_regress/t/t_iface_array_multidim_modport.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_iface_array_multidim_modport.py +++ b/test_regress/t/t_iface_array_multidim_modport.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_iface_array_multidim_multi_inst.py b/test_regress/t/t_iface_array_multidim_multi_inst.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_iface_array_multidim_multi_inst.py +++ b/test_regress/t/t_iface_array_multidim_multi_inst.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_iface_array_multidim_nested.py b/test_regress/t/t_iface_array_multidim_nested.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_iface_array_multidim_nested.py +++ b/test_regress/t/t_iface_array_multidim_nested.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_iface_array_multidim_nested_port.py b/test_regress/t/t_iface_array_multidim_nested_port.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_iface_array_multidim_nested_port.py +++ b/test_regress/t/t_iface_array_multidim_nested_port.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_iface_array_multidim_port.py b/test_regress/t/t_iface_array_multidim_port.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_iface_array_multidim_port.py +++ b/test_regress/t/t_iface_array_multidim_port.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_iface_chained_consumer_struct.py b/test_regress/t/t_iface_chained_consumer_struct.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_iface_chained_consumer_struct.py +++ b/test_regress/t/t_iface_chained_consumer_struct.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_iface_name_collision.py b/test_regress/t/t_iface_name_collision.py index ee8fad784..2ca1154e0 100755 --- a/test_regress/t/t_iface_name_collision.py +++ b/test_regress/t/t_iface_name_collision.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(verilator_flags2=["--lint-only -Werror-MULTIDRIVEN -Werror-UNOPTFLAT"]) diff --git a/test_regress/t/t_iface_nested_width2.py b/test_regress/t/t_iface_nested_width2.py index fb3797b25..e34d52316 100755 --- a/test_regress/t/t_iface_nested_width2.py +++ b/test_regress/t/t_iface_nested_width2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary']) diff --git a/test_regress/t/t_iface_nested_width3.py b/test_regress/t/t_iface_nested_width3.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_iface_nested_width3.py +++ b/test_regress/t/t_iface_nested_width3.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_iface_param_class_type.py b/test_regress/t/t_iface_param_class_type.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_iface_param_class_type.py +++ b/test_regress/t/t_iface_param_class_type.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_iface_param_class_type_noinl.py b/test_regress/t/t_iface_param_class_type_noinl.py index 6bd95f991..0d8ce0eae 100755 --- a/test_regress/t/t_iface_param_class_type_noinl.py +++ b/test_regress/t/t_iface_param_class_type_noinl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_iface_param_class_type.v" diff --git a/test_regress/t/t_iface_param_class_typedef.py b/test_regress/t/t_iface_param_class_typedef.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_iface_param_class_typedef.py +++ b/test_regress/t/t_iface_param_class_typedef.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_iface_param_type_derived_range.py b/test_regress/t/t_iface_param_type_derived_range.py index 46d1fe4c0..bd6ade23d 100755 --- a/test_regress/t/t_iface_param_type_derived_range.py +++ b/test_regress/t/t_iface_param_type_derived_range.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary']) diff --git a/test_regress/t/t_iface_typedef_scale.py b/test_regress/t/t_iface_typedef_scale.py index 3d1724e3e..27c097ff0 100755 --- a/test_regress/t/t_iface_typedef_scale.py +++ b/test_regress/t/t_iface_typedef_scale.py @@ -16,10 +16,11 @@ import time import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = test.obj_dir + "/t_iface_typedef_scale.sv" N_TYPEDEFS = 5000 -MAX_COMPILE_SECS = 10 # Generous budget; catches O(N^2) explosion where 5k typedefs would take minutes without the cache +MAX_COMPILE_SECS = 20 # Generous budget; catches O(N^2) explosion where 5k typedefs would take minutes without the cache def gen(filename, n): diff --git a/test_regress/t/t_iface_typedef_struct_member.py b/test_regress/t/t_iface_typedef_struct_member.py index 95e4478dd..bf5bbb79a 100755 --- a/test_regress/t/t_iface_typedef_struct_member.py +++ b/test_regress/t/t_iface_typedef_struct_member.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_iface_typedef_struct_member.v" test.compile(v_flags2=["--binary"]) diff --git a/test_regress/t/t_iface_typedef_wrong_clone.py b/test_regress/t/t_iface_typedef_wrong_clone.py index 44d191244..384788405 100755 --- a/test_regress/t/t_iface_typedef_wrong_clone.py +++ b/test_regress/t/t_iface_typedef_wrong_clone.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(v_flags2=["--binary"]) diff --git a/test_regress/t/t_iff.py b/test_regress/t/t_iff.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_iff.py +++ b/test_regress/t/t_iff.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_incorrect_multi_driven.py b/test_regress/t/t_incorrect_multi_driven.py index 0d2c50fcf..8879f51cf 100755 --- a/test_regress/t/t_incorrect_multi_driven.py +++ b/test_regress/t/t_incorrect_multi_driven.py @@ -11,6 +11,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.top_filename = "t/t_incorrect_multi_driven.v" test.lint(fails=False) diff --git a/test_regress/t/t_incr_void.py b/test_regress/t/t_incr_void.py index c6cfafd7b..ea9dbb725 100755 --- a/test_regress/t/t_incr_void.py +++ b/test_regress/t/t_incr_void.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--fno-split -x-assign 0"]) diff --git a/test_regress/t/t_infinite_recursion.py b/test_regress/t/t_infinite_recursion.py index 30b3e1786..d266e294b 100755 --- a/test_regress/t/t_infinite_recursion.py +++ b/test_regress/t/t_infinite_recursion.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.lint(verilator_flags2=["--no-unlimited-stack"]) diff --git a/test_regress/t/t_init_concat.py b/test_regress/t/t_init_concat.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_init_concat.py +++ b/test_regress/t/t_init_concat.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_initarray_nonarray.py b/test_regress/t/t_initarray_nonarray.py index 66009b455..52533feae 100755 --- a/test_regress/t/t_initarray_nonarray.py +++ b/test_regress/t/t_initarray_nonarray.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_initial_delay_assign.py b/test_regress/t/t_initial_delay_assign.py index b7cce95a7..c28be9e5c 100755 --- a/test_regress/t/t_initial_delay_assign.py +++ b/test_regress/t/t_initial_delay_assign.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios("simulator_st") +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=["--timing"]) diff --git a/test_regress/t/t_initial_edge_bad.py b/test_regress/t/t_initial_edge_bad.py index b929b7b19..422967559 100755 --- a/test_regress/t/t_initial_edge_bad.py +++ b/test_regress/t/t_initial_edge_bad.py @@ -13,6 +13,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.top_filename = "t/t_initial_edge.v" test.compile() diff --git a/test_regress/t/t_inside.py b/test_regress/t/t_inside.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_inside.py +++ b/test_regress/t/t_inside.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_inside2.py b/test_regress/t/t_inside2.py index 66009b455..52533feae 100755 --- a/test_regress/t/t_inside2.py +++ b/test_regress/t/t_inside2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_inside3.py b/test_regress/t/t_inside3.py index 84b274f68..17424b42f 100755 --- a/test_regress/t/t_inside3.py +++ b/test_regress/t/t_inside3.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_inside_dyn.py b/test_regress/t/t_inside_dyn.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_inside_dyn.py +++ b/test_regress/t/t_inside_dyn.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_inside_impure_unsized.py b/test_regress/t/t_inside_impure_unsized.py index 8a938befd..a10e2547d 100755 --- a/test_regress/t/t_inside_impure_unsized.py +++ b/test_regress/t/t_inside_impure_unsized.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_inside_queue_elem.py b/test_regress/t/t_inside_queue_elem.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_inside_queue_elem.py +++ b/test_regress/t/t_inside_queue_elem.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_inside_unpacked.py b/test_regress/t/t_inside_unpacked.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_inside_unpacked.py +++ b/test_regress/t/t_inside_unpacked.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_inst_array_connect.py b/test_regress/t/t_inst_array_connect.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_inst_array_connect.py +++ b/test_regress/t/t_inst_array_connect.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_inst_array_inl0.py b/test_regress/t/t_inst_array_inl0.py index 85188349b..71e5ad56a 100755 --- a/test_regress/t/t_inst_array_inl0.py +++ b/test_regress/t/t_inst_array_inl0.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_inst_array.v" test.compile(v_flags2=['+define+NOUSE_INLINE']) diff --git a/test_regress/t/t_inst_array_inl1.py b/test_regress/t/t_inst_array_inl1.py index ba989a59a..18cb9b286 100755 --- a/test_regress/t/t_inst_array_inl1.py +++ b/test_regress/t/t_inst_array_inl1.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_inst_array.v" test.compile(v_flags2=['+define+USE_INLINE']) diff --git a/test_regress/t/t_inst_array_partial.py b/test_regress/t/t_inst_array_partial.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_inst_array_partial.py +++ b/test_regress/t/t_inst_array_partial.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_inst_array_struct.py b/test_regress/t/t_inst_array_struct.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_inst_array_struct.py +++ b/test_regress/t/t_inst_array_struct.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_inst_comma_inl0.py b/test_regress/t/t_inst_comma_inl0.py index 1f7b491cc..2a3c90b09 100755 --- a/test_regress/t/t_inst_comma_inl0.py +++ b/test_regress/t/t_inst_comma_inl0.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_inst_comma.v" test.compile(v_flags2=['+define+NOUSE_INLINE']) diff --git a/test_regress/t/t_inst_comma_inl1.py b/test_regress/t/t_inst_comma_inl1.py index f60677020..49e67c498 100755 --- a/test_regress/t/t_inst_comma_inl1.py +++ b/test_regress/t/t_inst_comma_inl1.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_inst_comma.v" test.compile(v_flags2=['+define+USE_INLINE']) diff --git a/test_regress/t/t_inst_darray.py b/test_regress/t/t_inst_darray.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_inst_darray.py +++ b/test_regress/t/t_inst_darray.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_inst_dff.py b/test_regress/t/t_inst_dff.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_inst_dff.py +++ b/test_regress/t/t_inst_dff.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_inst_first.py b/test_regress/t/t_inst_first.py index c996a862c..b0623d58c 100755 --- a/test_regress/t/t_inst_first.py +++ b/test_regress/t/t_inst_first.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=[test.wno_unopthreads_for_few_cores]) diff --git a/test_regress/t/t_inst_implicit.py b/test_regress/t/t_inst_implicit.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_inst_implicit.py +++ b/test_regress/t/t_inst_implicit.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_inst_mism.py b/test_regress/t/t_inst_mism.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_inst_mism.py +++ b/test_regress/t/t_inst_mism.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_inst_mnpipe.py b/test_regress/t/t_inst_mnpipe.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_inst_mnpipe.py +++ b/test_regress/t/t_inst_mnpipe.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_inst_notunsized.py b/test_regress/t/t_inst_notunsized.py index 762a53022..4d8a1bd89 100755 --- a/test_regress/t/t_inst_notunsized.py +++ b/test_regress/t/t_inst_notunsized.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["-Wno-IMPLICIT"]) diff --git a/test_regress/t/t_inst_overwide.py b/test_regress/t/t_inst_overwide.py index 018361beb..bb19c75a7 100755 --- a/test_regress/t/t_inst_overwide.py +++ b/test_regress/t/t_inst_overwide.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["-sc -Wno-WIDTH"], verilator_make_gmake=False, diff --git a/test_regress/t/t_inst_overwide_bad.py b/test_regress/t/t_inst_overwide_bad.py index 56722b4f7..36adf5285 100755 --- a/test_regress/t/t_inst_overwide_bad.py +++ b/test_regress/t/t_inst_overwide_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.top_filename = "t/t_inst_overwide.v" test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_inst_port_array.py b/test_regress/t/t_inst_port_array.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_inst_port_array.py +++ b/test_regress/t/t_inst_port_array.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_inst_slice.py b/test_regress/t/t_inst_slice.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_inst_slice.py +++ b/test_regress/t/t_inst_slice.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_inst_slice_noinl.py b/test_regress/t/t_inst_slice_noinl.py index 88ff3e6f7..46919b79f 100755 --- a/test_regress/t/t_inst_slice_noinl.py +++ b/test_regress/t/t_inst_slice_noinl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_inst_slice.v" test.compile(v_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_inst_sv.py b/test_regress/t/t_inst_sv.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_inst_sv.py +++ b/test_regress/t/t_inst_sv.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_inst_tree_inl0_pub0.py b/test_regress/t/t_inst_tree_inl0_pub0.py index a5bc9523b..d479c4bda 100755 --- a/test_regress/t/t_inst_tree_inl0_pub0.py +++ b/test_regress/t/t_inst_tree_inl0_pub0.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_inst_tree.v" out_filename = test.obj_dir + "/V" + test.name + ".tree.json" diff --git a/test_regress/t/t_inst_tree_inl0_pub1.py b/test_regress/t/t_inst_tree_inl0_pub1.py index be831d2c5..650437221 100755 --- a/test_regress/t/t_inst_tree_inl0_pub1.py +++ b/test_regress/t/t_inst_tree_inl0_pub1.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_inst_tree.v" default_vltmt_threads = test.get_default_vltmt_threads diff --git a/test_regress/t/t_inst_tree_inl1_pub0.py b/test_regress/t/t_inst_tree_inl1_pub0.py index 036210aaa..58fa19523 100755 --- a/test_regress/t/t_inst_tree_inl1_pub0.py +++ b/test_regress/t/t_inst_tree_inl1_pub0.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_inst_tree.v" out_filename = test.obj_dir + "/V" + test.name + ".tree.json" diff --git a/test_regress/t/t_inst_tree_inl1_pub1.py b/test_regress/t/t_inst_tree_inl1_pub1.py index 67900ceaf..908b94115 100755 --- a/test_regress/t/t_inst_tree_inl1_pub1.py +++ b/test_regress/t/t_inst_tree_inl1_pub1.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_inst_tree.v" out_filename = test.obj_dir + "/V" + test.name + ".tree.json" diff --git a/test_regress/t/t_inst_v2k.py b/test_regress/t/t_inst_v2k.py index 1ec3b0e4a..65d23a696 100755 --- a/test_regress/t/t_inst_v2k.py +++ b/test_regress/t/t_inst_v2k.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile( v_flags2=['+libext+.vi+.extranoneed'], diff --git a/test_regress/t/t_inst_wideconst.py b/test_regress/t/t_inst_wideconst.py index b18ae571f..2df02bb16 100755 --- a/test_regress/t/t_inst_wideconst.py +++ b/test_regress/t/t_inst_wideconst.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['-public']) diff --git a/test_regress/t/t_interface.py b/test_regress/t/t_interface.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_interface.py +++ b/test_regress/t/t_interface.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_interface1_modport.py b/test_regress/t/t_interface1_modport.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_interface1_modport.py +++ b/test_regress/t/t_interface1_modport.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_interface1_modport_nansi.py b/test_regress/t/t_interface1_modport_nansi.py index 7f2c0bde5..456d30006 100755 --- a/test_regress/t/t_interface1_modport_nansi.py +++ b/test_regress/t/t_interface1_modport_nansi.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_interface1_modport.v" test.compile(v_flags2=['+define+NANSI']) diff --git a/test_regress/t/t_interface1_modport_noinl.py b/test_regress/t/t_interface1_modport_noinl.py index 1aec8386a..0cd8af39a 100755 --- a/test_regress/t/t_interface1_modport_noinl.py +++ b/test_regress/t/t_interface1_modport_noinl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_interface1_modport.v" test.compile(v_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_interface1_modport_trace.py b/test_regress/t/t_interface1_modport_trace.py index e291222e0..72a3ef62c 100755 --- a/test_regress/t/t_interface1_modport_trace.py +++ b/test_regress/t/t_interface1_modport_trace.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_interface1_modport.v" test.compile(verilator_flags2=['--trace-vcd']) diff --git a/test_regress/t/t_interface1_noinl.py b/test_regress/t/t_interface1_noinl.py index e25d72676..6be8665fc 100755 --- a/test_regress/t/t_interface1_noinl.py +++ b/test_regress/t/t_interface1_noinl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_interface1.v" test.compile(v_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_interface2_noinl.py b/test_regress/t/t_interface2_noinl.py index bd529e930..164918755 100755 --- a/test_regress/t/t_interface2_noinl.py +++ b/test_regress/t/t_interface2_noinl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_interface2.v" test.compile(verilator_flags2=["--top-module t -fno-inline"]) diff --git a/test_regress/t/t_interface_and_struct_pattern.py b/test_regress/t/t_interface_and_struct_pattern.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_interface_and_struct_pattern.py +++ b/test_regress/t/t_interface_and_struct_pattern.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_interface_ar2a.py b/test_regress/t/t_interface_ar2a.py index 66009b455..52533feae 100755 --- a/test_regress/t/t_interface_ar2a.py +++ b/test_regress/t/t_interface_ar2a.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_interface_ar2b.py b/test_regress/t/t_interface_ar2b.py index 66009b455..52533feae 100755 --- a/test_regress/t/t_interface_ar2b.py +++ b/test_regress/t/t_interface_ar2b.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_interface_array2.py b/test_regress/t/t_interface_array2.py index 9e69cbd92..6b0204909 100755 --- a/test_regress/t/t_interface_array2.py +++ b/test_regress/t/t_interface_array2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, v_flags2=["--timing"]) diff --git a/test_regress/t/t_interface_array2_coverage.py b/test_regress/t/t_interface_array2_coverage.py index 70f8d1678..c642e79a6 100755 --- a/test_regress/t/t_interface_array2_coverage.py +++ b/test_regress/t/t_interface_array2_coverage.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_interface_array2.v" test.compile(timing_loop=True, v_flags2=["--coverage --timing"]) diff --git a/test_regress/t/t_interface_array2_noinl.py b/test_regress/t/t_interface_array2_noinl.py index 4de8eeb5d..a818d4d09 100755 --- a/test_regress/t/t_interface_array2_noinl.py +++ b/test_regress/t/t_interface_array2_noinl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_interface_array2.v" test.compile(timing_loop=True, v_flags2=["-fno-inline --timing"]) diff --git a/test_regress/t/t_interface_array3.py b/test_regress/t/t_interface_array3.py index 4ee7f9e14..64d4ecb78 100755 --- a/test_regress/t/t_interface_array3.py +++ b/test_regress/t/t_interface_array3.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary']) diff --git a/test_regress/t/t_interface_array4.py b/test_regress/t/t_interface_array4.py index 4ee7f9e14..64d4ecb78 100755 --- a/test_regress/t/t_interface_array4.py +++ b/test_regress/t/t_interface_array4.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary']) diff --git a/test_regress/t/t_interface_array_modport.py b/test_regress/t/t_interface_array_modport.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_interface_array_modport.py +++ b/test_regress/t/t_interface_array_modport.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_interface_array_nocolon.py b/test_regress/t/t_interface_array_nocolon.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_interface_array_nocolon.py +++ b/test_regress/t/t_interface_array_nocolon.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_interface_array_nocolon_bad.py b/test_regress/t/t_interface_array_nocolon_bad.py index 1952b53a1..873d22c46 100755 --- a/test_regress/t/t_interface_array_nocolon_bad.py +++ b/test_regress/t/t_interface_array_nocolon_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_interface_array_noinl.py b/test_regress/t/t_interface_array_noinl.py index 1749f03fd..7113ae602 100755 --- a/test_regress/t/t_interface_array_noinl.py +++ b/test_regress/t/t_interface_array_noinl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_interface_array.v" test.compile(v_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_interface_array_parameter_access.py b/test_regress/t/t_interface_array_parameter_access.py index 1a93d5310..5ce5416d4 100755 --- a/test_regress/t/t_interface_array_parameter_access.py +++ b/test_regress/t/t_interface_array_parameter_access.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator_st') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_interface_array_parameter_aggregate.py b/test_regress/t/t_interface_array_parameter_aggregate.py index 096e10e28..34fdd9247 100755 --- a/test_regress/t/t_interface_array_parameter_aggregate.py +++ b/test_regress/t/t_interface_array_parameter_aggregate.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator_st') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary']) diff --git a/test_regress/t/t_interface_arraymux.py b/test_regress/t/t_interface_arraymux.py index 67b896515..8a1a7b033 100755 --- a/test_regress/t/t_interface_arraymux.py +++ b/test_regress/t/t_interface_arraymux.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint() diff --git a/test_regress/t/t_interface_bind_public.py b/test_regress/t/t_interface_bind_public.py index b18ae571f..2df02bb16 100755 --- a/test_regress/t/t_interface_bind_public.py +++ b/test_regress/t/t_interface_bind_public.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['-public']) diff --git a/test_regress/t/t_interface_derived_type.py b/test_regress/t/t_interface_derived_type.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_interface_derived_type.py +++ b/test_regress/t/t_interface_derived_type.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_interface_down_noinl.py b/test_regress/t/t_interface_down_noinl.py index 6fdb3819b..4642cf641 100755 --- a/test_regress/t/t_interface_down_noinl.py +++ b/test_regress/t/t_interface_down_noinl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_interface_down.v" test.compile(v_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_interface_dups.py b/test_regress/t/t_interface_dups.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_interface_dups.py +++ b/test_regress/t/t_interface_dups.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_interface_gen.py b/test_regress/t/t_interface_gen.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_interface_gen.py +++ b/test_regress/t/t_interface_gen.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_interface_gen2.py b/test_regress/t/t_interface_gen2.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_interface_gen2.py +++ b/test_regress/t/t_interface_gen2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_interface_gen2_collision.py b/test_regress/t/t_interface_gen2_collision.py index 78a1e96e1..96e2d804b 100755 --- a/test_regress/t/t_interface_gen2_collision.py +++ b/test_regress/t/t_interface_gen2_collision.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_interface_gen2.v" test.compile(verilator_flags2=["--debug-collision"]) diff --git a/test_regress/t/t_interface_gen2_noinl.py b/test_regress/t/t_interface_gen2_noinl.py index f0ea8f993..74433f2ac 100755 --- a/test_regress/t/t_interface_gen2_noinl.py +++ b/test_regress/t/t_interface_gen2_noinl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_interface_gen2.v" test.compile(v_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_interface_gen3.py b/test_regress/t/t_interface_gen3.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_interface_gen3.py +++ b/test_regress/t/t_interface_gen3.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_interface_gen3_collision.py b/test_regress/t/t_interface_gen3_collision.py index 4483913c3..bc2657306 100755 --- a/test_regress/t/t_interface_gen3_collision.py +++ b/test_regress/t/t_interface_gen3_collision.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_interface_gen3.v" test.compile(verilator_flags2=["--debug-collision"]) diff --git a/test_regress/t/t_interface_gen3_noinl.py b/test_regress/t/t_interface_gen3_noinl.py index ff08a6a4f..efb26ca0e 100755 --- a/test_regress/t/t_interface_gen3_noinl.py +++ b/test_regress/t/t_interface_gen3_noinl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_interface_gen3.v" test.compile(v_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_interface_gen4_noinl.py b/test_regress/t/t_interface_gen4_noinl.py index d37bf8dc5..db0ca2355 100755 --- a/test_regress/t/t_interface_gen4_noinl.py +++ b/test_regress/t/t_interface_gen4_noinl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_interface_gen4.v" test.compile(v_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_interface_gen9.py b/test_regress/t/t_interface_gen9.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_interface_gen9.py +++ b/test_regress/t/t_interface_gen9.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_interface_gen9_noinl.py b/test_regress/t/t_interface_gen9_noinl.py index 24ea30b07..555bea53f 100755 --- a/test_regress/t/t_interface_gen9_noinl.py +++ b/test_regress/t/t_interface_gen9_noinl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_interface_gen9.v" test.compile(v_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_interface_gen_noinl.py b/test_regress/t/t_interface_gen_noinl.py index c3c20b2fe..f452508a8 100755 --- a/test_regress/t/t_interface_gen_noinl.py +++ b/test_regress/t/t_interface_gen_noinl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_interface_gen.v" test.compile(v_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_interface_import_param.py b/test_regress/t/t_interface_import_param.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_interface_import_param.py +++ b/test_regress/t/t_interface_import_param.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_interface_inl.py b/test_regress/t/t_interface_inl.py index 65ab2e2cf..91f7656c8 100755 --- a/test_regress/t/t_interface_inl.py +++ b/test_regress/t/t_interface_inl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_interface.v" test.compile( diff --git a/test_regress/t/t_interface_inout_tristate.py b/test_regress/t/t_interface_inout_tristate.py index 1ddad07d5..514560607 100755 --- a/test_regress/t/t_interface_inout_tristate.py +++ b/test_regress/t/t_interface_inout_tristate.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=['--timing']) diff --git a/test_regress/t/t_interface_modport.py b/test_regress/t/t_interface_modport.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_interface_modport.py +++ b/test_regress/t/t_interface_modport.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_interface_modport_coverage.py b/test_regress/t/t_interface_modport_coverage.py index b473cbb28..5bc2040b1 100755 --- a/test_regress/t/t_interface_modport_coverage.py +++ b/test_regress/t/t_interface_modport_coverage.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_interface_modport.v" test.compile(verilator_flags2=["-fno-inline --coverage"]) diff --git a/test_regress/t/t_interface_modport_expr.py b/test_regress/t/t_interface_modport_expr.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_interface_modport_expr.py +++ b/test_regress/t/t_interface_modport_expr.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_interface_modport_expr_hier.py b/test_regress/t/t_interface_modport_expr_hier.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_interface_modport_expr_hier.py +++ b/test_regress/t/t_interface_modport_expr_hier.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_interface_modport_expr_hier_noinl.py b/test_regress/t/t_interface_modport_expr_hier_noinl.py index 092cc4a23..df43d6f62 100755 --- a/test_regress/t/t_interface_modport_expr_hier_noinl.py +++ b/test_regress/t/t_interface_modport_expr_hier_noinl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_interface_modport_expr_hier.v" test.compile(verilator_flags2=["--binary", "-fno-inline"]) diff --git a/test_regress/t/t_interface_modport_expr_nested.py b/test_regress/t/t_interface_modport_expr_nested.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_interface_modport_expr_nested.py +++ b/test_regress/t/t_interface_modport_expr_nested.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_interface_modport_expr_nested_noinl.py b/test_regress/t/t_interface_modport_expr_nested_noinl.py index c8b950dc5..eec0b4971 100755 --- a/test_regress/t/t_interface_modport_expr_nested_noinl.py +++ b/test_regress/t/t_interface_modport_expr_nested_noinl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_interface_modport_expr_nested.v" test.compile(verilator_flags2=["--binary", "-fno-inline"]) diff --git a/test_regress/t/t_interface_modport_expr_noinl.py b/test_regress/t/t_interface_modport_expr_noinl.py index 63982213e..c0d735942 100755 --- a/test_regress/t/t_interface_modport_expr_noinl.py +++ b/test_regress/t/t_interface_modport_expr_noinl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_interface_modport_expr.v" test.compile(verilator_flags2=["--binary", "-fno-inline"]) diff --git a/test_regress/t/t_interface_modport_hier.py b/test_regress/t/t_interface_modport_hier.py index 3fb25347f..41b3dcb32 100755 --- a/test_regress/t/t_interface_modport_hier.py +++ b/test_regress/t/t_interface_modport_hier.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False # Test hierarchical access through modport interface ports # Related to Issue #5941 and #2656 diff --git a/test_regress/t/t_interface_modport_hier_noinl.py b/test_regress/t/t_interface_modport_hier_noinl.py index 0950605f0..d78ac7219 100755 --- a/test_regress/t/t_interface_modport_hier_noinl.py +++ b/test_regress/t/t_interface_modport_hier_noinl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_interface_modport_hier.v" test.compile(v_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_interface_modport_import.py b/test_regress/t/t_interface_modport_import.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_interface_modport_import.py +++ b/test_regress/t/t_interface_modport_import.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_interface_modport_import_export_list.py b/test_regress/t/t_interface_modport_import_export_list.py index 66009b455..52533feae 100755 --- a/test_regress/t/t_interface_modport_import_export_list.py +++ b/test_regress/t/t_interface_modport_import_export_list.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_interface_modport_import_noinl.py b/test_regress/t/t_interface_modport_import_noinl.py index 83452502c..55b44d703 100755 --- a/test_regress/t/t_interface_modport_import_noinl.py +++ b/test_regress/t/t_interface_modport_import_noinl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_interface_modport_import.v" test.compile(v_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_interface_modport_inl.py b/test_regress/t/t_interface_modport_inl.py index 664b9c9a1..9f4685d83 100755 --- a/test_regress/t/t_interface_modport_inl.py +++ b/test_regress/t/t_interface_modport_inl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_interface_modport.v" test.compile( diff --git a/test_regress/t/t_interface_modport_noinl.py b/test_regress/t/t_interface_modport_noinl.py index 1c56d9b01..2e19eb20d 100755 --- a/test_regress/t/t_interface_modport_noinl.py +++ b/test_regress/t/t_interface_modport_noinl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_interface_modport.v" test.compile(v_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_interface_modport_param.py b/test_regress/t/t_interface_modport_param.py index e7721d960..2800c5539 100755 --- a/test_regress/t/t_interface_modport_param.py +++ b/test_regress/t/t_interface_modport_param.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios("simulator_st") +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_interface_modportlist.py b/test_regress/t/t_interface_modportlist.py index 1d54c793f..481eeaa8f 100755 --- a/test_regress/t/t_interface_modportlist.py +++ b/test_regress/t/t_interface_modportlist.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_make_gmake=False, make_top_shell=False, make_main=False) diff --git a/test_regress/t/t_interface_mp_func.py b/test_regress/t/t_interface_mp_func.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_interface_mp_func.py +++ b/test_regress/t/t_interface_mp_func.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_interface_mp_func_noinl.py b/test_regress/t/t_interface_mp_func_noinl.py index 1e22253e7..290bf90ba 100755 --- a/test_regress/t/t_interface_mp_func_noinl.py +++ b/test_regress/t/t_interface_mp_func_noinl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_interface_mp_func.v" test.compile(v_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_interface_nest_noinl.py b/test_regress/t/t_interface_nest_noinl.py index 8105695d5..c9b952923 100755 --- a/test_regress/t/t_interface_nest_noinl.py +++ b/test_regress/t/t_interface_nest_noinl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_interface_nest.v" test.compile(v_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_interface_nested_port.py b/test_regress/t/t_interface_nested_port.py index 46d1fe4c0..bd6ade23d 100755 --- a/test_regress/t/t_interface_nested_port.py +++ b/test_regress/t/t_interface_nested_port.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary']) diff --git a/test_regress/t/t_interface_nested_port_noinl.py b/test_regress/t/t_interface_nested_port_noinl.py index 50db1bfbd..e68e810f1 100755 --- a/test_regress/t/t_interface_nested_port_noinl.py +++ b/test_regress/t/t_interface_nested_port_noinl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_interface_nested_port.v" test.compile(verilator_flags2=['--binary', '-fno-inline']) diff --git a/test_regress/t/t_interface_nested_port_type.py b/test_regress/t/t_interface_nested_port_type.py index 46d1fe4c0..bd6ade23d 100755 --- a/test_regress/t/t_interface_nested_port_type.py +++ b/test_regress/t/t_interface_nested_port_type.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary']) diff --git a/test_regress/t/t_interface_nested_port_type_noinl.py b/test_regress/t/t_interface_nested_port_type_noinl.py index 21954d583..8f0f4a8e1 100755 --- a/test_regress/t/t_interface_nested_port_type_noinl.py +++ b/test_regress/t/t_interface_nested_port_type_noinl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_interface_nested_port_type.v" # Type parameters in nested interfaces (no-inline mode) diff --git a/test_regress/t/t_interface_nested_struct_param.py b/test_regress/t/t_interface_nested_struct_param.py index 46d1fe4c0..bd6ade23d 100755 --- a/test_regress/t/t_interface_nested_struct_param.py +++ b/test_regress/t/t_interface_nested_struct_param.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary']) diff --git a/test_regress/t/t_interface_noinl.py b/test_regress/t/t_interface_noinl.py index f67e05814..0168066f4 100755 --- a/test_regress/t/t_interface_noinl.py +++ b/test_regress/t/t_interface_noinl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_interface.v" test.compile(v_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_interface_notpublic.py b/test_regress/t/t_interface_notpublic.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_interface_notpublic.py +++ b/test_regress/t/t_interface_notpublic.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_interface_param1.py b/test_regress/t/t_interface_param1.py index 67b896515..8a1a7b033 100755 --- a/test_regress/t/t_interface_param1.py +++ b/test_regress/t/t_interface_param1.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint() diff --git a/test_regress/t/t_interface_param2.py b/test_regress/t/t_interface_param2.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_interface_param2.py +++ b/test_regress/t/t_interface_param2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_interface_param_dependency.py b/test_regress/t/t_interface_param_dependency.py index 597ea5463..83e8c4280 100755 --- a/test_regress/t/t_interface_param_dependency.py +++ b/test_regress/t/t_interface_param_dependency.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios("simulator_st") +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_interface_parameter_access.py b/test_regress/t/t_interface_parameter_access.py index 1a93d5310..5ce5416d4 100755 --- a/test_regress/t/t_interface_parameter_access.py +++ b/test_regress/t/t_interface_parameter_access.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator_st') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_interface_parent_scope.py b/test_regress/t/t_interface_parent_scope.py index a09d6d38a..b9325ab12 100755 --- a/test_regress/t/t_interface_parent_scope.py +++ b/test_regress/t/t_interface_parent_scope.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint( # Should fail, Verilator unsupported, bug1623 diff --git a/test_regress/t/t_interface_tristate_hier.py b/test_regress/t/t_interface_tristate_hier.py index 1ddad07d5..514560607 100755 --- a/test_regress/t/t_interface_tristate_hier.py +++ b/test_regress/t/t_interface_tristate_hier.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=['--timing']) diff --git a/test_regress/t/t_interface_tristate_plain_xhier.py b/test_regress/t/t_interface_tristate_plain_xhier.py index 1ddad07d5..514560607 100755 --- a/test_regress/t/t_interface_tristate_plain_xhier.py +++ b/test_regress/t/t_interface_tristate_plain_xhier.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=['--timing']) diff --git a/test_regress/t/t_interface_tristate_plain_xhier_noinl.py b/test_regress/t/t_interface_tristate_plain_xhier_noinl.py index 12aff0c40..3eaeb6f99 100755 --- a/test_regress/t/t_interface_tristate_plain_xhier_noinl.py +++ b/test_regress/t/t_interface_tristate_plain_xhier_noinl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t_interface_tristate_plain_xhier.v" test.compile(timing_loop=True, verilator_flags2=['--timing', '-fno-inline']) diff --git a/test_regress/t/t_interface_twod.py b/test_regress/t/t_interface_twod.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_interface_twod.py +++ b/test_regress/t/t_interface_twod.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_interface_twod_noinl.py b/test_regress/t/t_interface_twod_noinl.py index 6ba3e743e..4ca537284 100755 --- a/test_regress/t/t_interface_twod_noinl.py +++ b/test_regress/t/t_interface_twod_noinl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_interface_twod.v" test.compile(v_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_interface_typedef.py b/test_regress/t/t_interface_typedef.py index 096e10e28..34fdd9247 100755 --- a/test_regress/t/t_interface_typedef.py +++ b/test_regress/t/t_interface_typedef.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator_st') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary']) diff --git a/test_regress/t/t_interface_typedef2.py b/test_regress/t/t_interface_typedef2.py index a16833e52..ba297a91a 100755 --- a/test_regress/t/t_interface_typedef2.py +++ b/test_regress/t/t_interface_typedef2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator_st') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary']) diff --git a/test_regress/t/t_interface_update.py b/test_regress/t/t_interface_update.py index 9c3430fc9..ec5dc7d67 100755 --- a/test_regress/t/t_interface_update.py +++ b/test_regress/t/t_interface_update.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator_st') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_interface_virtual.py b/test_regress/t/t_interface_virtual.py index ed8db10e9..8aeecc749 100755 --- a/test_regress/t/t_interface_virtual.py +++ b/test_regress/t/t_interface_virtual.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_interface_virtual_controlflow.py b/test_regress/t/t_interface_virtual_controlflow.py index ab012d5ce..bd1b7d7b4 100755 --- a/test_regress/t/t_interface_virtual_controlflow.py +++ b/test_regress/t/t_interface_virtual_controlflow.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary -fno-reorder"]) diff --git a/test_regress/t/t_interface_virtual_inl.py b/test_regress/t/t_interface_virtual_inl.py index 3d30f0a27..cf1e1ed90 100755 --- a/test_regress/t/t_interface_virtual_inl.py +++ b/test_regress/t/t_interface_virtual_inl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_interface_virtual.v" test.golden_filename = "t/t_interface_virtual.out" diff --git a/test_regress/t/t_interface_virtual_modport_sel.py b/test_regress/t/t_interface_virtual_modport_sel.py index 664e902bf..ab9765c24 100755 --- a/test_regress/t/t_interface_virtual_modport_sel.py +++ b/test_regress/t/t_interface_virtual_modport_sel.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary", "--timing"]) diff --git a/test_regress/t/t_interface_virtual_opt.py b/test_regress/t/t_interface_virtual_opt.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_interface_virtual_opt.py +++ b/test_regress/t/t_interface_virtual_opt.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_interface_virtual_param.py b/test_regress/t/t_interface_virtual_param.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_interface_virtual_param.py +++ b/test_regress/t/t_interface_virtual_param.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_interface_virtual_sched_act.py b/test_regress/t/t_interface_virtual_sched_act.py index 55248e18d..0c18d9c79 100755 --- a/test_regress/t/t_interface_virtual_sched_act.py +++ b/test_regress/t/t_interface_virtual_sched_act.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_interface_virtual_sched_ico.py b/test_regress/t/t_interface_virtual_sched_ico.py index 7a2535255..5f37dcdbb 100755 --- a/test_regress/t/t_interface_virtual_sched_ico.py +++ b/test_regress/t/t_interface_virtual_sched_ico.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_interface_virtual_sched_nba.py b/test_regress/t/t_interface_virtual_sched_nba.py index 55248e18d..0c18d9c79 100755 --- a/test_regress/t/t_interface_virtual_sched_nba.py +++ b/test_regress/t/t_interface_virtual_sched_nba.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_interface_virtual_sub_iface.py b/test_regress/t/t_interface_virtual_sub_iface.py index 8a938befd..a10e2547d 100755 --- a/test_regress/t/t_interface_virtual_sub_iface.py +++ b/test_regress/t/t_interface_virtual_sub_iface.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_interface_virtual_sub_iface_method.py b/test_regress/t/t_interface_virtual_sub_iface_method.py index 8a938befd..a10e2547d 100755 --- a/test_regress/t/t_interface_virtual_sub_iface_method.py +++ b/test_regress/t/t_interface_virtual_sub_iface_method.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_interface_virtual_timing.py b/test_regress/t/t_interface_virtual_timing.py index 55248e18d..0c18d9c79 100755 --- a/test_regress/t/t_interface_virtual_timing.py +++ b/test_regress/t/t_interface_virtual_timing.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_interface_virtual_unused2.py b/test_regress/t/t_interface_virtual_unused2.py index 84b274f68..17424b42f 100755 --- a/test_regress/t/t_interface_virtual_unused2.py +++ b/test_regress/t/t_interface_virtual_unused2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_json_only_begin_hier.out b/test_regress/t/t_json_only_begin_hier.out index 68cc2bd11..4c008fcb1 100644 --- a/test_regress/t/t_json_only_begin_hier.out +++ b/test_regress/t/t_json_only_begin_hier.out @@ -2,7 +2,7 @@ "modulesp": [ {"type":"MODULE","name":"test","addr":"(E)","loc":"d,21:8,21:12","origName":"test","verilogName":"test","level":1,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"N","addr":"(F)","loc":"d,22:10,22:11","dtypep":"(G)","origName":"N","verilogName":"N","direction":"NONE","isUsedLoopIdx":true,"icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"GENVAR","dtypeName":"integer","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"N","addr":"(F)","loc":"d,22:10,22:11","dtypep":"(G)","origName":"N","verilogName":"N","direction":"NONE","isUsedLoopIdx":true,"icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"GENVAR","dtypeName":"integer","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"GENBLOCK","name":"FOR_GENERATE","addr":"(H)","loc":"d,24:5,24:8","implied":true,"genforp": [],"itemsp": []}, {"type":"GENBLOCK","name":"FOR_GENERATE[0]","addr":"(I)","loc":"d,25:14,25:24","genforp": [], "itemsp": [ @@ -27,7 +27,7 @@ "stmtsp": [ {"type":"GENBLOCK","name":"submod_gen","addr":"(T)","loc":"d,11:18,11:28","genforp": [], "itemsp": [ - {"type":"VAR","name":"l1_sig","addr":"(U)","loc":"d,12:10,12:16","dtypep":"(V)","origName":"l1_sig","verilogName":"l1_sig","direction":"NONE","lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"l1_sig","addr":"(U)","loc":"d,12:10,12:16","dtypep":"(V)","origName":"l1_sig","verilogName":"l1_sig","direction":"NONE","lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"GENBLOCK","name":"nested_gen","addr":"(W)","loc":"d,13:20,13:30","genforp": [], "itemsp": [ {"type":"CELL","name":"submod_nested","addr":"(X)","loc":"d,14:15,14:28","origName":"submod_nested","verilogName":"submod_nested","modp":"(Y)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []} diff --git a/test_regress/t/t_json_only_debugcheck.py b/test_regress/t/t_json_only_debugcheck.py index aeef0a17b..bc632f59c 100755 --- a/test_regress/t/t_json_only_debugcheck.py +++ b/test_regress/t/t_json_only_debugcheck.py @@ -11,6 +11,7 @@ import json import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_enum_type_methods.v" out_filename = test.obj_dir + "/V" + test.name + ".tree.json" diff --git a/test_regress/t/t_json_only_first.out b/test_regress/t/t_json_only_first.out index 0f60e9c25..b41e5f17a 100644 --- a/test_regress/t/t_json_only_first.out +++ b/test_regress/t/t_json_only_first.out @@ -2,22 +2,22 @@ "modulesp": [ {"type":"MODULE","name":"t","addr":"(E)","loc":"d,7:8,7:9","origName":"t","verilogName":"t","level":1,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"q","addr":"(F)","loc":"d,16:21,16:22","dtypep":"(G)","origName":"q","verilogName":"q","isPrimaryIO":true,"direction":"OUTPUT","isSigPublic":true,"icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"clk","addr":"(H)","loc":"d,14:9,14:12","dtypep":"(I)","origName":"clk","verilogName":"clk","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"d","addr":"(J)","loc":"d,15:15,15:16","dtypep":"(G)","origName":"d","verilogName":"d","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"between","addr":"(K)","loc":"d,18:15,18:22","dtypep":"(G)","origName":"between","verilogName":"between","direction":"NONE","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"direct_named","addr":"(L)","loc":"d,19:9,19:21","dtypep":"(I)","origName":"direct_named","verilogName":"direct_named","direction":"NONE","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"computed_named","addr":"(M)","loc":"d,20:9,20:23","dtypep":"(I)","origName":"computed_named","verilogName":"computed_named","direction":"NONE","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"anonymous_expr","addr":"(N)","loc":"d,21:9,21:23","dtypep":"(I)","origName":"anonymous_expr","verilogName":"anonymous_expr","direction":"NONE","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"S_IDLE","addr":"(O)","loc":"d,23:26,23:32","dtypep":"(P)","origName":"S_IDLE","verilogName":"S_IDLE","direction":"NONE","isConst":true,"lifetime":"VSTATICI","varType":"LPARAM","dtypeName":"logic","isParam":true,"hasUserInit":true,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [], + {"type":"VAR","name":"q","addr":"(F)","loc":"d,16:21,16:22","dtypep":"(G)","origName":"q","verilogName":"q","isPrimaryIO":true,"direction":"OUTPUT","isSigPublic":true,"icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"clk","addr":"(H)","loc":"d,14:9,14:12","dtypep":"(I)","origName":"clk","verilogName":"clk","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"d","addr":"(J)","loc":"d,15:15,15:16","dtypep":"(G)","origName":"d","verilogName":"d","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"between","addr":"(K)","loc":"d,18:15,18:22","dtypep":"(G)","origName":"between","verilogName":"between","direction":"NONE","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"direct_named","addr":"(L)","loc":"d,19:9,19:21","dtypep":"(I)","origName":"direct_named","verilogName":"direct_named","direction":"NONE","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"computed_named","addr":"(M)","loc":"d,20:9,20:23","dtypep":"(I)","origName":"computed_named","verilogName":"computed_named","direction":"NONE","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"anonymous_expr","addr":"(N)","loc":"d,21:9,21:23","dtypep":"(I)","origName":"anonymous_expr","verilogName":"anonymous_expr","direction":"NONE","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"S_IDLE","addr":"(O)","loc":"d,23:26,23:32","dtypep":"(P)","origName":"S_IDLE","verilogName":"S_IDLE","direction":"NONE","isConst":true,"lifetime":"VSTATICI","varType":"LPARAM","dtypeName":"logic","isParam":true,"hasUserInit":true,"sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [], "valuep": [ {"type":"CONST","name":"2'h0","addr":"(Q)","loc":"d,23:35,23:40","dtypep":"(R)"} ],"attrsp": []}, - {"type":"VAR","name":"S_FETCH","addr":"(S)","loc":"d,24:26,24:33","dtypep":"(P)","origName":"S_FETCH","verilogName":"S_FETCH","direction":"NONE","isConst":true,"lifetime":"VSTATICI","varType":"LPARAM","dtypeName":"logic","isParam":true,"hasUserInit":true,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [], + {"type":"VAR","name":"S_FETCH","addr":"(S)","loc":"d,24:26,24:33","dtypep":"(P)","origName":"S_FETCH","verilogName":"S_FETCH","direction":"NONE","isConst":true,"lifetime":"VSTATICI","varType":"LPARAM","dtypeName":"logic","isParam":true,"hasUserInit":true,"sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [], "valuep": [ {"type":"CONST","name":"2'h1","addr":"(T)","loc":"d,24:36,24:41","dtypep":"(R)"} ],"attrsp": []}, - {"type":"VAR","name":"S_EXEC","addr":"(U)","loc":"d,25:26,25:32","dtypep":"(P)","origName":"S_EXEC","verilogName":"S_EXEC","direction":"NONE","isConst":true,"lifetime":"VSTATICI","varType":"LPARAM","dtypeName":"logic","isParam":true,"hasUserInit":true,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [], + {"type":"VAR","name":"S_EXEC","addr":"(U)","loc":"d,25:26,25:32","dtypep":"(P)","origName":"S_EXEC","verilogName":"S_EXEC","direction":"NONE","isConst":true,"lifetime":"VSTATICI","varType":"LPARAM","dtypeName":"logic","isParam":true,"hasUserInit":true,"sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [], "valuep": [ {"type":"CONST","name":"2'h2","addr":"(V)","loc":"d,25:43,25:44","dtypep":"(P)"} ],"attrsp": []}, @@ -120,9 +120,9 @@ ]}, {"type":"MODULE","name":"mod2","addr":"(IC)","loc":"d,61:8,61:12","origName":"mod2","verilogName":"mod2","level":2,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"clk","addr":"(QC)","loc":"d,62:11,62:14","dtypep":"(I)","origName":"clk","verilogName":"clk","direction":"INPUT","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"d","addr":"(KC)","loc":"d,63:17,63:18","dtypep":"(G)","origName":"d","verilogName":"d","direction":"INPUT","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"q","addr":"(NC)","loc":"d,64:23,64:24","dtypep":"(G)","origName":"q","verilogName":"q","direction":"OUTPUT","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"clk","addr":"(QC)","loc":"d,62:11,62:14","dtypep":"(I)","origName":"clk","verilogName":"clk","direction":"INPUT","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"d","addr":"(KC)","loc":"d,63:17,63:18","dtypep":"(G)","origName":"d","verilogName":"d","direction":"INPUT","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"q","addr":"(NC)","loc":"d,64:23,64:24","dtypep":"(G)","origName":"q","verilogName":"q","direction":"OUTPUT","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"ALWAYS","name":"","addr":"(SC)","loc":"d,67:12,67:13","keyword":"cont_assign","sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(TC)","loc":"d,67:12,67:13","dtypep":"(G)", @@ -136,14 +136,14 @@ ]}, {"type":"MODULE","name":"mod1__W4","addr":"(XB)","loc":"d,47:8,47:12","origName":"mod1","verilogName":"mod1","level":2,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"WIDTH","addr":"(WC)","loc":"d,48:15,48:20","dtypep":"(XC)","origName":"WIDTH","verilogName":"WIDTH","direction":"NONE","isConst":true,"lifetime":"VSTATICI","varType":"GPARAM","dtypeName":"logic","isGParam":true,"isParam":true,"hasUserInit":true,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [], + {"type":"VAR","name":"WIDTH","addr":"(WC)","loc":"d,48:15,48:20","dtypep":"(XC)","origName":"WIDTH","verilogName":"WIDTH","direction":"NONE","isConst":true,"lifetime":"VSTATICI","varType":"GPARAM","dtypeName":"logic","isGParam":true,"isParam":true,"hasUserInit":true,"sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [], "valuep": [ {"type":"CONST","name":"32'sh4","addr":"(YC)","loc":"d,32:14,32:15","dtypep":"(ZC)"} ],"attrsp": []}, - {"type":"VAR","name":"clk","addr":"(CC)","loc":"d,50:11,50:14","dtypep":"(I)","origName":"clk","verilogName":"clk","direction":"INPUT","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"d","addr":"(FC)","loc":"d,51:23,51:24","dtypep":"(G)","origName":"d","verilogName":"d","direction":"INPUT","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"q","addr":"(ZB)","loc":"d,52:30,52:31","dtypep":"(G)","origName":"q","verilogName":"q","direction":"OUTPUT","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"IGNORED","addr":"(AD)","loc":"d,55:14,55:21","dtypep":"(XC)","origName":"IGNORED","verilogName":"IGNORED","direction":"NONE","isConst":true,"lifetime":"VSTATICI","varType":"LPARAM","dtypeName":"logic","isParam":true,"hasUserInit":true,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [], + {"type":"VAR","name":"clk","addr":"(CC)","loc":"d,50:11,50:14","dtypep":"(I)","origName":"clk","verilogName":"clk","direction":"INPUT","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"d","addr":"(FC)","loc":"d,51:23,51:24","dtypep":"(G)","origName":"d","verilogName":"d","direction":"INPUT","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"q","addr":"(ZB)","loc":"d,52:30,52:31","dtypep":"(G)","origName":"q","verilogName":"q","direction":"OUTPUT","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"IGNORED","addr":"(AD)","loc":"d,55:14,55:21","dtypep":"(XC)","origName":"IGNORED","verilogName":"IGNORED","direction":"NONE","isConst":true,"lifetime":"VSTATICI","varType":"LPARAM","dtypeName":"logic","isParam":true,"hasUserInit":true,"sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [], "valuep": [ {"type":"CONST","name":"32'sh1","addr":"(BD)","loc":"d,55:24,55:25","dtypep":"(ZC)"} ],"attrsp": []}, diff --git a/test_regress/t/t_json_only_first.py b/test_regress/t/t_json_only_first.py index 2c764bd51..d41ccb43c 100755 --- a/test_regress/t/t_json_only_first.py +++ b/test_regress/t/t_json_only_first.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False out_filename = test.obj_dir + "/V" + test.name + ".tree.json" diff --git a/test_regress/t/t_json_only_flat.out b/test_regress/t/t_json_only_flat.out index 6b3d6ca6c..7c8326507 100644 --- a/test_regress/t/t_json_only_flat.out +++ b/test_regress/t/t_json_only_flat.out @@ -2,39 +2,39 @@ "modulesp": [ {"type":"MODULE","name":"$root","addr":"(F)","loc":"d,7:8,7:9","origName":"$root","verilogName":"$root","level":1,"modPublic":true,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"q","addr":"(G)","loc":"d,16:21,16:22","dtypep":"(H)","origName":"q","verilogName":"q","isPrimaryIO":true,"direction":"OUTPUT","isSigPublic":true,"icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"clk","addr":"(I)","loc":"d,14:9,14:12","dtypep":"(J)","origName":"clk","verilogName":"clk","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"d","addr":"(K)","loc":"d,15:15,15:16","dtypep":"(H)","origName":"d","verilogName":"d","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"t.q","addr":"(L)","loc":"d,16:21,16:22","dtypep":"(H)","origName":"q","verilogName":"q","direction":"NONE","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"t.clk","addr":"(M)","loc":"d,14:9,14:12","dtypep":"(J)","origName":"clk","verilogName":"clk","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"t.d","addr":"(N)","loc":"d,15:15,15:16","dtypep":"(H)","origName":"d","verilogName":"d","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"t.between","addr":"(O)","loc":"d,18:15,18:22","dtypep":"(H)","origName":"between","verilogName":"between","direction":"NONE","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"t.direct_named","addr":"(P)","loc":"d,19:9,19:21","dtypep":"(J)","origName":"direct_named","verilogName":"direct_named","direction":"NONE","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"t.computed_named","addr":"(Q)","loc":"d,20:9,20:23","dtypep":"(J)","origName":"computed_named","verilogName":"computed_named","direction":"NONE","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"t.anonymous_expr","addr":"(R)","loc":"d,21:9,21:23","dtypep":"(J)","origName":"anonymous_expr","verilogName":"anonymous_expr","direction":"NONE","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"t.S_IDLE","addr":"(S)","loc":"d,23:26,23:32","dtypep":"(T)","origName":"S_IDLE","verilogName":"S_IDLE","direction":"NONE","isConst":true,"lifetime":"VSTATICI","varType":"LPARAM","dtypeName":"logic","isParam":true,"hasUserInit":true,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [], + {"type":"VAR","name":"q","addr":"(G)","loc":"d,16:21,16:22","dtypep":"(H)","origName":"q","verilogName":"q","isPrimaryIO":true,"direction":"OUTPUT","isSigPublic":true,"icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"clk","addr":"(I)","loc":"d,14:9,14:12","dtypep":"(J)","origName":"clk","verilogName":"clk","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"d","addr":"(K)","loc":"d,15:15,15:16","dtypep":"(H)","origName":"d","verilogName":"d","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"t.q","addr":"(L)","loc":"d,16:21,16:22","dtypep":"(H)","origName":"q","verilogName":"q","direction":"NONE","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"t.clk","addr":"(M)","loc":"d,14:9,14:12","dtypep":"(J)","origName":"clk","verilogName":"clk","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"t.d","addr":"(N)","loc":"d,15:15,15:16","dtypep":"(H)","origName":"d","verilogName":"d","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"t.between","addr":"(O)","loc":"d,18:15,18:22","dtypep":"(H)","origName":"between","verilogName":"between","direction":"NONE","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"t.direct_named","addr":"(P)","loc":"d,19:9,19:21","dtypep":"(J)","origName":"direct_named","verilogName":"direct_named","direction":"NONE","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"t.computed_named","addr":"(Q)","loc":"d,20:9,20:23","dtypep":"(J)","origName":"computed_named","verilogName":"computed_named","direction":"NONE","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"t.anonymous_expr","addr":"(R)","loc":"d,21:9,21:23","dtypep":"(J)","origName":"anonymous_expr","verilogName":"anonymous_expr","direction":"NONE","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"t.S_IDLE","addr":"(S)","loc":"d,23:26,23:32","dtypep":"(T)","origName":"S_IDLE","verilogName":"S_IDLE","direction":"NONE","isConst":true,"lifetime":"VSTATICI","varType":"LPARAM","dtypeName":"logic","isParam":true,"hasUserInit":true,"sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [], "valuep": [ {"type":"CONST","name":"2'h0","addr":"(U)","loc":"d,23:35,23:40","dtypep":"(V)"} ],"attrsp": []}, - {"type":"VAR","name":"t.S_FETCH","addr":"(W)","loc":"d,24:26,24:33","dtypep":"(T)","origName":"S_FETCH","verilogName":"S_FETCH","direction":"NONE","isConst":true,"lifetime":"VSTATICI","varType":"LPARAM","dtypeName":"logic","isParam":true,"hasUserInit":true,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [], + {"type":"VAR","name":"t.S_FETCH","addr":"(W)","loc":"d,24:26,24:33","dtypep":"(T)","origName":"S_FETCH","verilogName":"S_FETCH","direction":"NONE","isConst":true,"lifetime":"VSTATICI","varType":"LPARAM","dtypeName":"logic","isParam":true,"hasUserInit":true,"sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [], "valuep": [ {"type":"CONST","name":"2'h1","addr":"(X)","loc":"d,24:36,24:41","dtypep":"(V)"} ],"attrsp": []}, - {"type":"VAR","name":"t.S_EXEC","addr":"(Y)","loc":"d,25:26,25:32","dtypep":"(T)","origName":"S_EXEC","verilogName":"S_EXEC","direction":"NONE","isConst":true,"lifetime":"VSTATICI","varType":"LPARAM","dtypeName":"logic","isParam":true,"hasUserInit":true,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [], + {"type":"VAR","name":"t.S_EXEC","addr":"(Y)","loc":"d,25:26,25:32","dtypep":"(T)","origName":"S_EXEC","verilogName":"S_EXEC","direction":"NONE","isConst":true,"lifetime":"VSTATICI","varType":"LPARAM","dtypeName":"logic","isParam":true,"hasUserInit":true,"sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [], "valuep": [ {"type":"CONST","name":"2'h2","addr":"(Z)","loc":"d,25:43,25:44","dtypep":"(T)"} ],"attrsp": []}, - {"type":"VAR","name":"t.cell2.clk","addr":"(AB)","loc":"d,62:11,62:14","dtypep":"(J)","origName":"clk","verilogName":"clk","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"t.cell2.d","addr":"(BB)","loc":"d,63:17,63:18","dtypep":"(H)","origName":"d","verilogName":"d","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"t.cell2.q","addr":"(CB)","loc":"d,64:23,64:24","dtypep":"(H)","origName":"q","verilogName":"q","direction":"NONE","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"t.cell1.WIDTH","addr":"(DB)","loc":"d,48:15,48:20","dtypep":"(EB)","origName":"WIDTH","verilogName":"WIDTH","direction":"NONE","isConst":true,"lifetime":"VSTATICI","varType":"GPARAM","dtypeName":"logic","isGParam":true,"isParam":true,"hasUserInit":true,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [], + {"type":"VAR","name":"t.cell2.clk","addr":"(AB)","loc":"d,62:11,62:14","dtypep":"(J)","origName":"clk","verilogName":"clk","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"t.cell2.d","addr":"(BB)","loc":"d,63:17,63:18","dtypep":"(H)","origName":"d","verilogName":"d","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"t.cell2.q","addr":"(CB)","loc":"d,64:23,64:24","dtypep":"(H)","origName":"q","verilogName":"q","direction":"NONE","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"t.cell1.WIDTH","addr":"(DB)","loc":"d,48:15,48:20","dtypep":"(EB)","origName":"WIDTH","verilogName":"WIDTH","direction":"NONE","isConst":true,"lifetime":"VSTATICI","varType":"GPARAM","dtypeName":"logic","isGParam":true,"isParam":true,"hasUserInit":true,"sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [], "valuep": [ {"type":"CONST","name":"32'sh4","addr":"(FB)","loc":"d,32:14,32:15","dtypep":"(GB)"} ],"attrsp": []}, - {"type":"VAR","name":"t.cell1.clk","addr":"(HB)","loc":"d,50:11,50:14","dtypep":"(J)","origName":"clk","verilogName":"clk","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"t.cell1.d","addr":"(IB)","loc":"d,51:23,51:24","dtypep":"(H)","origName":"d","verilogName":"d","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"t.cell1.q","addr":"(JB)","loc":"d,52:30,52:31","dtypep":"(H)","origName":"q","verilogName":"q","direction":"NONE","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"t.cell1.IGNORED","addr":"(KB)","loc":"d,55:14,55:21","dtypep":"(EB)","origName":"IGNORED","verilogName":"IGNORED","direction":"NONE","isConst":true,"lifetime":"VSTATICI","varType":"LPARAM","dtypeName":"logic","isParam":true,"hasUserInit":true,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [], + {"type":"VAR","name":"t.cell1.clk","addr":"(HB)","loc":"d,50:11,50:14","dtypep":"(J)","origName":"clk","verilogName":"clk","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"t.cell1.d","addr":"(IB)","loc":"d,51:23,51:24","dtypep":"(H)","origName":"d","verilogName":"d","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"t.cell1.q","addr":"(JB)","loc":"d,52:30,52:31","dtypep":"(H)","origName":"q","verilogName":"q","direction":"NONE","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"t.cell1.IGNORED","addr":"(KB)","loc":"d,55:14,55:21","dtypep":"(EB)","origName":"IGNORED","verilogName":"IGNORED","direction":"NONE","isConst":true,"lifetime":"VSTATICI","varType":"LPARAM","dtypeName":"logic","isParam":true,"hasUserInit":true,"sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [], "valuep": [ {"type":"CONST","name":"32'sh1","addr":"(LB)","loc":"d,55:24,55:25","dtypep":"(GB)"} ],"attrsp": []}, diff --git a/test_regress/t/t_json_only_flat.py b/test_regress/t/t_json_only_flat.py index a60a658b6..dadabbeee 100755 --- a/test_regress/t/t_json_only_flat.py +++ b/test_regress/t/t_json_only_flat.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_json_only_first.v" out_filename = test.obj_dir + "/V" + test.name + ".tree.json" diff --git a/test_regress/t/t_json_only_flat_no_inline_mod.out b/test_regress/t/t_json_only_flat_no_inline_mod.out index b87493b24..158a3ccaf 100644 --- a/test_regress/t/t_json_only_flat_no_inline_mod.out +++ b/test_regress/t/t_json_only_flat_no_inline_mod.out @@ -2,9 +2,9 @@ "modulesp": [ {"type":"MODULE","name":"$root","addr":"(F)","loc":"d,11:8,11:11","origName":"$root","verilogName":"$root","level":1,"modPublic":true,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"i_clk","addr":"(G)","loc":"d,11:24,11:29","dtypep":"(H)","origName":"i_clk","verilogName":"i_clk","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"top.i_clk","addr":"(I)","loc":"d,11:24,11:29","dtypep":"(H)","origName":"i_clk","verilogName":"i_clk","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"top.f.i_clk","addr":"(J)","loc":"d,7:24,7:29","dtypep":"(H)","origName":"i_clk","verilogName":"i_clk","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"i_clk","addr":"(G)","loc":"d,11:24,11:29","dtypep":"(H)","origName":"i_clk","verilogName":"i_clk","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"top.i_clk","addr":"(I)","loc":"d,11:24,11:29","dtypep":"(H)","origName":"i_clk","verilogName":"i_clk","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"top.f.i_clk","addr":"(J)","loc":"d,7:24,7:29","dtypep":"(H)","origName":"i_clk","verilogName":"i_clk","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"TOPSCOPE","name":"","addr":"(E)","loc":"d,11:8,11:11","senTreesp": [], "scopep": [ {"type":"SCOPE","name":"TOP","addr":"(K)","loc":"d,11:8,11:11","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(F)", diff --git a/test_regress/t/t_json_only_flat_no_inline_mod.py b/test_regress/t/t_json_only_flat_no_inline_mod.py index d6779da1e..33e81e6fd 100755 --- a/test_regress/t/t_json_only_flat_no_inline_mod.py +++ b/test_regress/t/t_json_only_flat_no_inline_mod.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False out_filename = test.obj_dir + "/V" + test.name + ".tree.json" diff --git a/test_regress/t/t_json_only_flat_pub_mod.out b/test_regress/t/t_json_only_flat_pub_mod.out index b87493b24..158a3ccaf 100644 --- a/test_regress/t/t_json_only_flat_pub_mod.out +++ b/test_regress/t/t_json_only_flat_pub_mod.out @@ -2,9 +2,9 @@ "modulesp": [ {"type":"MODULE","name":"$root","addr":"(F)","loc":"d,11:8,11:11","origName":"$root","verilogName":"$root","level":1,"modPublic":true,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"i_clk","addr":"(G)","loc":"d,11:24,11:29","dtypep":"(H)","origName":"i_clk","verilogName":"i_clk","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"top.i_clk","addr":"(I)","loc":"d,11:24,11:29","dtypep":"(H)","origName":"i_clk","verilogName":"i_clk","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"top.f.i_clk","addr":"(J)","loc":"d,7:24,7:29","dtypep":"(H)","origName":"i_clk","verilogName":"i_clk","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"i_clk","addr":"(G)","loc":"d,11:24,11:29","dtypep":"(H)","origName":"i_clk","verilogName":"i_clk","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"top.i_clk","addr":"(I)","loc":"d,11:24,11:29","dtypep":"(H)","origName":"i_clk","verilogName":"i_clk","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"top.f.i_clk","addr":"(J)","loc":"d,7:24,7:29","dtypep":"(H)","origName":"i_clk","verilogName":"i_clk","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"TOPSCOPE","name":"","addr":"(E)","loc":"d,11:8,11:11","senTreesp": [], "scopep": [ {"type":"SCOPE","name":"TOP","addr":"(K)","loc":"d,11:8,11:11","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(F)", diff --git a/test_regress/t/t_json_only_flat_pub_mod.py b/test_regress/t/t_json_only_flat_pub_mod.py index d6779da1e..33e81e6fd 100755 --- a/test_regress/t/t_json_only_flat_pub_mod.py +++ b/test_regress/t/t_json_only_flat_pub_mod.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False out_filename = test.obj_dir + "/V" + test.name + ".tree.json" diff --git a/test_regress/t/t_json_only_flat_vlvbound.out b/test_regress/t/t_json_only_flat_vlvbound.out index 1725da9ef..e008c3350 100644 --- a/test_regress/t/t_json_only_flat_vlvbound.out +++ b/test_regress/t/t_json_only_flat_vlvbound.out @@ -2,14 +2,14 @@ "modulesp": [ {"type":"MODULE","name":"$root","addr":"(F)","loc":"d,7:8,7:21","origName":"$root","verilogName":"$root","level":1,"modPublic":true,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"i_a","addr":"(G)","loc":"d,8:24,8:27","dtypep":"(H)","origName":"i_a","verilogName":"i_a","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"i_b","addr":"(I)","loc":"d,9:24,9:27","dtypep":"(H)","origName":"i_b","verilogName":"i_b","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"o_a","addr":"(J)","loc":"d,10:24,10:27","dtypep":"(K)","origName":"o_a","verilogName":"o_a","isPrimaryIO":true,"direction":"OUTPUT","isSigPublic":true,"icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"o_b","addr":"(L)","loc":"d,11:24,11:27","dtypep":"(K)","origName":"o_b","verilogName":"o_b","isPrimaryIO":true,"direction":"OUTPUT","isSigPublic":true,"icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"vlvbound_test.i_a","addr":"(M)","loc":"d,8:24,8:27","dtypep":"(H)","origName":"i_a","verilogName":"i_a","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"vlvbound_test.i_b","addr":"(N)","loc":"d,9:24,9:27","dtypep":"(H)","origName":"i_b","verilogName":"i_b","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"vlvbound_test.o_a","addr":"(O)","loc":"d,10:24,10:27","dtypep":"(K)","origName":"o_a","verilogName":"o_a","direction":"NONE","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"vlvbound_test.o_b","addr":"(P)","loc":"d,11:24,11:27","dtypep":"(K)","origName":"o_b","verilogName":"o_b","direction":"NONE","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"i_a","addr":"(G)","loc":"d,8:24,8:27","dtypep":"(H)","origName":"i_a","verilogName":"i_a","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"i_b","addr":"(I)","loc":"d,9:24,9:27","dtypep":"(H)","origName":"i_b","verilogName":"i_b","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"o_a","addr":"(J)","loc":"d,10:24,10:27","dtypep":"(K)","origName":"o_a","verilogName":"o_a","isPrimaryIO":true,"direction":"OUTPUT","isSigPublic":true,"icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"o_b","addr":"(L)","loc":"d,11:24,11:27","dtypep":"(K)","origName":"o_b","verilogName":"o_b","isPrimaryIO":true,"direction":"OUTPUT","isSigPublic":true,"icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + 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{"type":"VAR","name":"__Vfunc_vlvbound_test.foo__0__val","addr":"(SB)","loc":"d,14:57,14:60","dtypep":"(H)","origName":"__Vfunc_vlvbound_test__DOT__foo__0__val","verilogName":"__Vfunc_vlvbound_test.foo__0__val","direction":"NONE","lifetime":"NONE","varType":"BLOCKTEMP","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"__Vfunc_vlvbound_test.foo__0__ret","addr":"(UB)","loc":"d,15:17,15:20","dtypep":"(K)","origName":"__Vfunc_vlvbound_test__DOT__foo__0__ret","verilogName":"__Vfunc_vlvbound_test.foo__0__ret","direction":"NONE","lifetime":"NONE","varType":"BLOCKTEMP","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"__Vfunc_vlvbound_test.foo__0__i","addr":"(XB)","loc":"d,16:13,16:14","dtypep":"(WB)","origName":"__Vfunc_vlvbound_test__DOT__foo__0__i","verilogName":"__Vfunc_vlvbound_test.foo__0__i","direction":"NONE","lifetime":"NONE","varType":"BLOCKTEMP","dtypeName":"integer","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"__Vfunc_vlvbound_test.foo__1__Vfuncout","addr":"(ZB)","loc":"d,14:34,14:37","dtypep":"(K)","origName":"__Vfunc_vlvbound_test__DOT__foo__1__Vfuncout","verilogName":"__Vfunc_vlvbound_test.foo__1__Vfuncout","direction":"NONE","lifetime":"NONE","varType":"BLOCKTEMP","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"__Vfunc_vlvbound_test.foo__1__val","addr":"(BC)","loc":"d,14:57,14:60","dtypep":"(H)","origName":"__Vfunc_vlvbound_test__DOT__foo__1__val","verilogName":"__Vfunc_vlvbound_test.foo__1__val","direction":"NONE","lifetime":"NONE","varType":"BLOCKTEMP","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"__Vfunc_vlvbound_test.foo__1__ret","addr":"(DC)","loc":"d,15:17,15:20","dtypep":"(K)","origName":"__Vfunc_vlvbound_test__DOT__foo__1__ret","verilogName":"__Vfunc_vlvbound_test.foo__1__ret","direction":"NONE","lifetime":"NONE","varType":"BLOCKTEMP","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"__Vfunc_vlvbound_test.foo__1__i","addr":"(FC)","loc":"d,16:13,16:14","dtypep":"(WB)","origName":"__Vfunc_vlvbound_test__DOT__foo__1__i","verilogName":"__Vfunc_vlvbound_test.foo__1__i","direction":"NONE","lifetime":"NONE","varType":"BLOCKTEMP","dtypeName":"integer","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ]} ],"filesp": [], "miscsp": [ diff --git a/test_regress/t/t_json_only_flat_vlvbound.py b/test_regress/t/t_json_only_flat_vlvbound.py index d6779da1e..33e81e6fd 100755 --- a/test_regress/t/t_json_only_flat_vlvbound.py +++ b/test_regress/t/t_json_only_flat_vlvbound.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False out_filename = test.obj_dir + "/V" + test.name + ".tree.json" diff --git a/test_regress/t/t_json_only_output.out b/test_regress/t/t_json_only_output.out index c66ad57a3..698954810 100644 --- a/test_regress/t/t_json_only_output.out +++ b/test_regress/t/t_json_only_output.out @@ -2,7 +2,7 @@ "modulesp": [ {"type":"MODULE","name":"m","addr":"(E)","loc":"d,7:8,7:9","origName":"m","verilogName":"m","level":1,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"clk","addr":"(F)","loc":"d,8:11,8:14","dtypep":"(G)","origName":"clk","verilogName":"clk","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} + {"type":"VAR","name":"clk","addr":"(F)","loc":"d,8:11,8:14","dtypep":"(G)","origName":"clk","verilogName":"clk","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ]} ],"filesp": [], "miscsp": [ diff --git a/test_regress/t/t_json_only_primary_io.out b/test_regress/t/t_json_only_primary_io.out index a611f6917..cfeef6c7f 100644 --- a/test_regress/t/t_json_only_primary_io.out +++ b/test_regress/t/t_json_only_primary_io.out @@ -2,11 +2,11 @@ "modulesp": [ {"type":"MODULE","name":"top","addr":"(E)","loc":"d,7:8,7:11","origName":"top","verilogName":"top","level":1,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"clk","addr":"(F)","loc":"d,13:9,13:12","dtypep":"(G)","origName":"clk","verilogName":"clk","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"a1","addr":"(H)","loc":"d,14:9,14:11","dtypep":"(G)","origName":"a1","verilogName":"a1","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"a2","addr":"(I)","loc":"d,15:9,15:11","dtypep":"(G)","origName":"a2","verilogName":"a2","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"ready","addr":"(J)","loc":"d,16:10,16:15","dtypep":"(G)","origName":"ready","verilogName":"ready","isPrimaryIO":true,"direction":"OUTPUT","isSigPublic":true,"icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"ready_reg","addr":"(K)","loc":"d,18:8,18:17","dtypep":"(G)","origName":"ready_reg","verilogName":"ready_reg","direction":"NONE","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"clk","addr":"(F)","loc":"d,13:9,13:12","dtypep":"(G)","origName":"clk","verilogName":"clk","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"a1","addr":"(H)","loc":"d,14:9,14:11","dtypep":"(G)","origName":"a1","verilogName":"a1","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"a2","addr":"(I)","loc":"d,15:9,15:11","dtypep":"(G)","origName":"a2","verilogName":"a2","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"ready","addr":"(J)","loc":"d,16:10,16:15","dtypep":"(G)","origName":"ready","verilogName":"ready","isPrimaryIO":true,"direction":"OUTPUT","isSigPublic":true,"icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"ready_reg","addr":"(K)","loc":"d,18:8,18:17","dtypep":"(G)","origName":"ready_reg","verilogName":"ready_reg","direction":"NONE","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"CELL","name":"and_cell","addr":"(L)","loc":"d,20:11,20:19","origName":"and_cell","verilogName":"and_cell","modp":"(M)", "pinsp": [ {"type":"PIN","name":"a1","addr":"(N)","loc":"d,21:8,21:10","svDotName":true,"modVarp":"(O)","modPTypep":"UNLINKED", @@ -35,9 +35,9 @@ ]}, {"type":"MODULE","name":"and2_x1","addr":"(M)","loc":"d,29:8,29:15","origName":"and2_x1","verilogName":"and2_x1","level":2,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"a1","addr":"(O)","loc":"d,30:16,30:18","dtypep":"(G)","origName":"a1","verilogName":"a1","direction":"INPUT","lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"a2","addr":"(R)","loc":"d,31:16,31:18","dtypep":"(G)","origName":"a2","verilogName":"a2","direction":"INPUT","lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"zn","addr":"(U)","loc":"d,32:17,32:19","dtypep":"(G)","origName":"zn","verilogName":"zn","direction":"OUTPUT","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"a1","addr":"(O)","loc":"d,30:16,30:18","dtypep":"(G)","origName":"a1","verilogName":"a1","direction":"INPUT","lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"a2","addr":"(R)","loc":"d,31:16,31:18","dtypep":"(G)","origName":"a2","verilogName":"a2","direction":"INPUT","lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"zn","addr":"(U)","loc":"d,32:17,32:19","dtypep":"(G)","origName":"zn","verilogName":"zn","direction":"OUTPUT","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"ALWAYS","name":"","addr":"(AB)","loc":"d,34:13,34:14","keyword":"cont_assign","sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(BB)","loc":"d,34:13,34:14","dtypep":"(G)", diff --git a/test_regress/t/t_json_only_tag.out b/test_regress/t/t_json_only_tag.out index c7e9999c6..f82fb2592 100644 --- a/test_regress/t/t_json_only_tag.out +++ b/test_regress/t/t_json_only_tag.out @@ -2,14 +2,14 @@ "modulesp": [ {"type":"MODULE","name":"m","addr":"(E)","loc":"d,12:8,12:9","origName":"m","verilogName":"m","level":1,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"clk_ip","addr":"(F)","loc":"d,13:11,13:17","dtypep":"(G)","origName":"clk_ip","verilogName":"clk_ip","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"rst_ip","addr":"(H)","loc":"d,14:11,14:17","dtypep":"(G)","origName":"rst_ip","verilogName":"rst_ip","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"foo_op","addr":"(I)","loc":"d,15:12,15:18","dtypep":"(G)","origName":"foo_op","verilogName":"foo_op","isPrimaryIO":true,"direction":"OUTPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"clk_ip","addr":"(F)","loc":"d,13:11,13:17","dtypep":"(G)","origName":"clk_ip","verilogName":"clk_ip","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"rst_ip","addr":"(H)","loc":"d,14:11,14:17","dtypep":"(G)","origName":"rst_ip","verilogName":"rst_ip","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"foo_op","addr":"(I)","loc":"d,15:12,15:18","dtypep":"(G)","origName":"foo_op","verilogName":"foo_op","isPrimaryIO":true,"direction":"OUTPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"TYPEDEF","name":"my_struct","addr":"(J)","loc":"d,25:5,25:14","dtypep":"(K)","childDTypep": [],"attrsp": []}, {"type":"CELL","name":"itop","addr":"(L)","loc":"d,29:7,29:11","origName":"itop","verilogName":"itop","modp":"(M)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []}, - {"type":"VAR","name":"itop","addr":"(N)","loc":"d,29:7,29:11","dtypep":"(O)","origName":"itop__Viftop","verilogName":"itop__Viftop","direction":"NONE","lifetime":"VSTATICI","varType":"IFACEREF","dtypeName":"","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"this_struct","addr":"(P)","loc":"d,31:13,31:24","dtypep":"(Q)","origName":"this_struct","verilogName":"this_struct","direction":"NONE","lifetime":"VSTATICI","varType":"VAR","dtypeName":"","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"dotted","addr":"(R)","loc":"d,33:15,33:21","dtypep":"(S)","origName":"dotted","verilogName":"dotted","direction":"NONE","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"itop","addr":"(N)","loc":"d,29:7,29:11","dtypep":"(O)","origName":"itop__Viftop","verilogName":"itop__Viftop","direction":"NONE","lifetime":"VSTATICI","varType":"IFACEREF","dtypeName":"","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"this_struct","addr":"(P)","loc":"d,31:13,31:24","dtypep":"(Q)","origName":"this_struct","verilogName":"this_struct","direction":"NONE","lifetime":"VSTATICI","varType":"VAR","dtypeName":"","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"dotted","addr":"(R)","loc":"d,33:15,33:21","dtypep":"(S)","origName":"dotted","verilogName":"dotted","direction":"NONE","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"ALWAYS","name":"","addr":"(T)","loc":"d,33:22,33:23","keyword":"cont_assign","sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(U)","loc":"d,33:22,33:23","dtypep":"(S)", @@ -22,7 +22,7 @@ ]}, {"type":"TASK","name":"f","addr":"(Z)","loc":"d,35:17,35:18","cname":"f","fvarp": [],"classOrPackagep": [], "stmtsp": [ - {"type":"VAR","name":"m","addr":"(AB)","loc":"d,35:32,35:33","dtypep":"(BB)","origName":"m","verilogName":"m","direction":"INPUT","isFuncLocal":true,"lifetime":"VAUTOMI","varType":"PORT","dtypeName":"string","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"m","addr":"(AB)","loc":"d,35:32,35:33","dtypep":"(BB)","origName":"m","verilogName":"m","direction":"INPUT","isFuncLocal":true,"lifetime":"VAUTOMI","varType":"PORT","dtypeName":"string","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"DISPLAY","name":"","addr":"(CB)","loc":"d,36:5,36:13", "fmtp": [ {"type":"SFORMATF","name":"%s","addr":"(DB)","loc":"d,36:5,36:13","dtypep":"(BB)", @@ -53,7 +53,7 @@ ]}, {"type":"IFACE","name":"ifc","addr":"(M)","loc":"d,7:11,7:14","origName":"ifc","verilogName":"ifc","level":2,"inLibrary":true,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"value","addr":"(X)","loc":"d,8:11,8:16","dtypep":"(W)","origName":"value","verilogName":"value","direction":"NONE","lifetime":"VSTATICI","varType":"VAR","dtypeName":"integer","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"value","addr":"(X)","loc":"d,8:11,8:16","dtypep":"(W)","origName":"value","verilogName":"value","direction":"NONE","lifetime":"VSTATICI","varType":"VAR","dtypeName":"integer","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"MODPORT","name":"out_modport","addr":"(NB)","loc":"d,9:11,9:22", "varsp": [ {"type":"MODPORTVARREF","name":"value","addr":"(OB)","loc":"d,9:30,9:35","direction":"OUTPUT","varp":"(X)","exprp": []} diff --git a/test_regress/t/t_langext_1.py b/test_regress/t/t_langext_1.py index f24fb336a..1c9887c95 100755 --- a/test_regress/t/t_langext_1.py +++ b/test_regress/t/t_langext_1.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False # This is a compile only test. test.compile(v_flags2=["+verilog2001ext+v"]) diff --git a/test_regress/t/t_langext_1d.py b/test_regress/t/t_langext_1d.py index 3ba6d1701..859989dee 100755 --- a/test_regress/t/t_langext_1d.py +++ b/test_regress/t/t_langext_1d.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_langext_1.v" # This is a compile only test. diff --git a/test_regress/t/t_langext_2.py b/test_regress/t/t_langext_2.py index 24a67d2a8..1b4b73c6c 100755 --- a/test_regress/t/t_langext_2.py +++ b/test_regress/t/t_langext_2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False # This is a compile only test. test.compile(v_flags2=["+systemverilogext+v"]) diff --git a/test_regress/t/t_langext_2012ext.py b/test_regress/t/t_langext_2012ext.py index 6e3f4f41f..4440c6d55 100755 --- a/test_regress/t/t_langext_2012ext.py +++ b/test_regress/t/t_langext_2012ext.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_langext_2.v" # This is a compile only test. diff --git a/test_regress/t/t_langext_2017ext.py b/test_regress/t/t_langext_2017ext.py index e7e5ebc1e..6aa69c5e9 100755 --- a/test_regress/t/t_langext_2017ext.py +++ b/test_regress/t/t_langext_2017ext.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_langext_2.v" # This is a compile only test. diff --git a/test_regress/t/t_langext_2023ext.py b/test_regress/t/t_langext_2023ext.py index c11e3ca37..0fe344b1d 100755 --- a/test_regress/t/t_langext_2023ext.py +++ b/test_regress/t/t_langext_2023ext.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_langext_2.v" # This is a compile only test. diff --git a/test_regress/t/t_langext_4.py b/test_regress/t/t_langext_4.py index 5b1ea1068..bc39a6be4 100755 --- a/test_regress/t/t_langext_4.py +++ b/test_regress/t/t_langext_4.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_langext_2.v" # This is a compile only test. diff --git a/test_regress/t/t_lib.py b/test_regress/t/t_lib.py index 05ad77f62..6a23b29f6 100755 --- a/test_regress/t/t_lib.py +++ b/test_regress/t/t_lib.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt', 'xsim') +test.fourstate_capable = False test.top_filename = "t/t_lib_prot.v" if test.benchmark: test.sim_time = test.benchmark * 100 diff --git a/test_regress/t/t_lib_clk_vec.py b/test_regress/t/t_lib_clk_vec.py index 45b37b72d..2eea0010d 100755 --- a/test_regress/t/t_lib_clk_vec.py +++ b/test_regress/t/t_lib_clk_vec.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False lib_dir = test.obj_dir + "/sub" test.mkdir_ok(lib_dir) diff --git a/test_regress/t/t_lib_nolib.py b/test_regress/t/t_lib_nolib.py index e0d740a76..4c4c7762a 100755 --- a/test_regress/t/t_lib_nolib.py +++ b/test_regress/t/t_lib_nolib.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all', 'xsim') +test.fourstate_capable = False test.top_filename = "t/t_lib_prot.v" if test.benchmark: diff --git a/test_regress/t/t_lib_prof_exec.py b/test_regress/t/t_lib_prof_exec.py index 8ac00b186..f85241af8 100755 --- a/test_regress/t/t_lib_prof_exec.py +++ b/test_regress/t/t_lib_prof_exec.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_lib_prot.v" if test.benchmark: test.sim_time = test.benchmark * 100 diff --git a/test_regress/t/t_lib_prot.py b/test_regress/t/t_lib_prot.py index 127bab7ec..904554425 100755 --- a/test_regress/t/t_lib_prot.py +++ b/test_regress/t/t_lib_prot.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt', 'xsim') +test.fourstate_capable = False if test.benchmark: test.sim_time = test.benchmark * 100 diff --git a/test_regress/t/t_lib_prot_clk_gated.py b/test_regress/t/t_lib_prot_clk_gated.py index 0abc2bf38..05a0c6e4d 100755 --- a/test_regress/t/t_lib_prot_clk_gated.py +++ b/test_regress/t/t_lib_prot_clk_gated.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt', 'xsim') +test.fourstate_capable = False test.top_filename = "t/t_lib_prot.v" if test.benchmark: diff --git a/test_regress/t/t_lib_prot_comb.py b/test_regress/t/t_lib_prot_comb.py index 30391c0f9..b6f183379 100755 --- a/test_regress/t/t_lib_prot_comb.py +++ b/test_regress/t/t_lib_prot_comb.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all', 'xsim') +test.fourstate_capable = False if test.benchmark: test.sim_time = test.benchmark * 100 diff --git a/test_regress/t/t_lib_prot_secret.py b/test_regress/t/t_lib_prot_secret.py index 1dbf65877..94d6cc254 100755 --- a/test_regress/t/t_lib_prot_secret.py +++ b/test_regress/t/t_lib_prot_secret.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(verilator_flags2=["--protect-lib", "secret", "--protect-key", "SECRET_FAKE_KEY"], verilator_make_gcc=False, diff --git a/test_regress/t/t_lib_prot_shared.py b/test_regress/t/t_lib_prot_shared.py index 8705dc539..6fc9524eb 100755 --- a/test_regress/t/t_lib_prot_shared.py +++ b/test_regress/t/t_lib_prot_shared.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all', 'xsim') +test.fourstate_capable = False test.top_filename = "t/t_lib_prot.v" if test.benchmark: diff --git a/test_regress/t/t_lint_always_comb_bad.py b/test_regress/t/t_lint_always_comb_bad.py index c7d9b21a5..692e6eeb1 100755 --- a/test_regress/t/t_lint_always_comb_bad.py +++ b/test_regress/t/t_lint_always_comb_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_lint_always_comb_iface.py b/test_regress/t/t_lint_always_comb_iface.py index 67b896515..8a1a7b033 100755 --- a/test_regress/t/t_lint_always_comb_iface.py +++ b/test_regress/t/t_lint_always_comb_iface.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint() diff --git a/test_regress/t/t_lint_always_comb_multidriven_bad.py b/test_regress/t/t_lint_always_comb_multidriven_bad.py index c7d9b21a5..692e6eeb1 100755 --- a/test_regress/t/t_lint_always_comb_multidriven_bad.py +++ b/test_regress/t/t_lint_always_comb_multidriven_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_lint_always_comb_multidriven_public_bad.py b/test_regress/t/t_lint_always_comb_multidriven_public_bad.py index bba2bd225..f51412970 100755 --- a/test_regress/t/t_lint_always_comb_multidriven_public_bad.py +++ b/test_regress/t/t_lint_always_comb_multidriven_public_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_lint_always_comb_multidriven_bad.v" test.lint(verilator_flags2=['--public-flat-rw'], fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_lint_always_ff_multidriven_bad.py b/test_regress/t/t_lint_always_ff_multidriven_bad.py index 38cf36b43..5dd624dc6 100755 --- a/test_regress/t/t_lint_always_ff_multidriven_bad.py +++ b/test_regress/t/t_lint_always_ff_multidriven_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_lint_assigneqexpr.py b/test_regress/t/t_lint_assigneqexpr.py index d24e41475..a7b192846 100755 --- a/test_regress/t/t_lint_assigneqexpr.py +++ b/test_regress/t/t_lint_assigneqexpr.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary', '--trace', '-Wno-ASSIGNEQEXPR']) diff --git a/test_regress/t/t_lint_assigneqexpr_bad.py b/test_regress/t/t_lint_assigneqexpr_bad.py index 6b8b54ad2..f0e361b6e 100755 --- a/test_regress/t/t_lint_assigneqexpr_bad.py +++ b/test_regress/t/t_lint_assigneqexpr_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_lint_assigneqexpr.v" test.lint(verilator_flags2=['-Wall -Wno-DECLFILENAME'], diff --git a/test_regress/t/t_lint_blkseq_bad.py b/test_regress/t/t_lint_blkseq_bad.py index 71d1e489b..1699f5197 100755 --- a/test_regress/t/t_lint_blkseq_bad.py +++ b/test_regress/t/t_lint_blkseq_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(verilator_flags2=["-Wwarn-BLKSEQ -Wwarn-COMBDLY"], fails=True, diff --git a/test_regress/t/t_lint_blkseq_loop.py b/test_regress/t/t_lint_blkseq_loop.py index c8f5704cf..7d5082b25 100755 --- a/test_regress/t/t_lint_blkseq_loop.py +++ b/test_regress/t/t_lint_blkseq_loop.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(verilator_flags2=["-Wwarn-BLKSEQ -Wwarn-COMBDLY"]) diff --git a/test_regress/t/t_lint_caseincomplete_bad.py b/test_regress/t/t_lint_caseincomplete_bad.py index c7d9b21a5..692e6eeb1 100755 --- a/test_regress/t/t_lint_caseincomplete_bad.py +++ b/test_regress/t/t_lint_caseincomplete_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_lint_comb_use.py b/test_regress/t/t_lint_comb_use.py index 53bc310a0..a2850fdb4 100755 --- a/test_regress/t/t_lint_comb_use.py +++ b/test_regress/t/t_lint_comb_use.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(verilator_flags2=["--bbox-sys"]) diff --git a/test_regress/t/t_lint_dtype_compare.py b/test_regress/t/t_lint_dtype_compare.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_lint_dtype_compare.py +++ b/test_regress/t/t_lint_dtype_compare.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_lint_eofnewline.py b/test_regress/t/t_lint_eofnewline.py index cc2766a36..68a5a94f8 100755 --- a/test_regress/t/t_lint_eofnewline.py +++ b/test_regress/t/t_lint_eofnewline.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = test.obj_dir + "/t_lint_eofnewline_bad.v" diff --git a/test_regress/t/t_lint_eofnewline_bad.py b/test_regress/t/t_lint_eofnewline_bad.py index 51fb0c244..07526c5b9 100755 --- a/test_regress/t/t_lint_eofnewline_bad.py +++ b/test_regress/t/t_lint_eofnewline_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = test.obj_dir + "/t_lint_eofnewline_bad.v" diff --git a/test_regress/t/t_lint_iface_array_topmodule1.py b/test_regress/t/t_lint_iface_array_topmodule1.py index 67b896515..8a1a7b033 100755 --- a/test_regress/t/t_lint_iface_array_topmodule1.py +++ b/test_regress/t/t_lint_iface_array_topmodule1.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint() diff --git a/test_regress/t/t_lint_iface_array_topmodule2.py b/test_regress/t/t_lint_iface_array_topmodule2.py index 67b896515..8a1a7b033 100755 --- a/test_regress/t/t_lint_iface_array_topmodule2.py +++ b/test_regress/t/t_lint_iface_array_topmodule2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint() diff --git a/test_regress/t/t_lint_iface_array_topmodule3.py b/test_regress/t/t_lint_iface_array_topmodule3.py index 67b896515..8a1a7b033 100755 --- a/test_regress/t/t_lint_iface_array_topmodule3.py +++ b/test_regress/t/t_lint_iface_array_topmodule3.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint() diff --git a/test_regress/t/t_lint_iface_topmodule1.py b/test_regress/t/t_lint_iface_topmodule1.py index 67b896515..8a1a7b033 100755 --- a/test_regress/t/t_lint_iface_topmodule1.py +++ b/test_regress/t/t_lint_iface_topmodule1.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint() diff --git a/test_regress/t/t_lint_iface_topmodule2.py b/test_regress/t/t_lint_iface_topmodule2.py index 67b896515..8a1a7b033 100755 --- a/test_regress/t/t_lint_iface_topmodule2.py +++ b/test_regress/t/t_lint_iface_topmodule2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint() diff --git a/test_regress/t/t_lint_iface_topmodule3.py b/test_regress/t/t_lint_iface_topmodule3.py index 67b896515..8a1a7b033 100755 --- a/test_regress/t/t_lint_iface_topmodule3.py +++ b/test_regress/t/t_lint_iface_topmodule3.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint() diff --git a/test_regress/t/t_lint_ifdepth_bad.py b/test_regress/t/t_lint_ifdepth_bad.py index de5d894a5..dece89ddc 100755 --- a/test_regress/t/t_lint_ifdepth_bad.py +++ b/test_regress/t/t_lint_ifdepth_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(verilator_flags2=["-Wall -Wno-DECLFILENAME --if-depth 10"], fails=True, diff --git a/test_regress/t/t_lint_implicit_port.py b/test_regress/t/t_lint_implicit_port.py index b4c5575c7..bfca7d1a4 100755 --- a/test_regress/t/t_lint_implicit_port.py +++ b/test_regress/t/t_lint_implicit_port.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(verilator_flags2=["-Wno-IMPLICIT"]) diff --git a/test_regress/t/t_lint_infinite.py b/test_regress/t/t_lint_infinite.py index 7ded63f3a..d210ebd50 100755 --- a/test_regress/t/t_lint_infinite.py +++ b/test_regress/t/t_lint_infinite.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_lint_inherit.py b/test_regress/t/t_lint_inherit.py index 9fd13a76c..bb84700b9 100755 --- a/test_regress/t/t_lint_inherit.py +++ b/test_regress/t/t_lint_inherit.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["-fno-dfg"]) diff --git a/test_regress/t/t_lint_latch_3.py b/test_regress/t/t_lint_latch_3.py index 88752b416..859fae682 100755 --- a/test_regress/t/t_lint_latch_3.py +++ b/test_regress/t/t_lint_latch_3.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint() diff --git a/test_regress/t/t_lint_latch_4.py b/test_regress/t/t_lint_latch_4.py index 88752b416..859fae682 100755 --- a/test_regress/t/t_lint_latch_4.py +++ b/test_regress/t/t_lint_latch_4.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint() diff --git a/test_regress/t/t_lint_latch_5.py b/test_regress/t/t_lint_latch_5.py index 88752b416..859fae682 100755 --- a/test_regress/t/t_lint_latch_5.py +++ b/test_regress/t/t_lint_latch_5.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint() diff --git a/test_regress/t/t_lint_latch_7.py b/test_regress/t/t_lint_latch_7.py index 88752b416..859fae682 100755 --- a/test_regress/t/t_lint_latch_7.py +++ b/test_regress/t/t_lint_latch_7.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint() diff --git a/test_regress/t/t_lint_latch_bad_2.py b/test_regress/t/t_lint_latch_bad_2.py index c7d9b21a5..692e6eeb1 100755 --- a/test_regress/t/t_lint_latch_bad_2.py +++ b/test_regress/t/t_lint_latch_bad_2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_lint_latch_bad_3.py b/test_regress/t/t_lint_latch_bad_3.py index c7d9b21a5..692e6eeb1 100755 --- a/test_regress/t/t_lint_latch_bad_3.py +++ b/test_regress/t/t_lint_latch_bad_3.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_lint_latch_casei_bad.py b/test_regress/t/t_lint_latch_casei_bad.py index 1d5ccb8f4..c1876edec 100755 --- a/test_regress/t/t_lint_latch_casei_bad.py +++ b/test_regress/t/t_lint_latch_casei_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_lint_multidriven_bad.py b/test_regress/t/t_lint_multidriven_bad.py index b265fb71a..fd972e15c 100755 --- a/test_regress/t/t_lint_multidriven_bad.py +++ b/test_regress/t/t_lint_multidriven_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_lint_multidriven_coverage_bad.py b/test_regress/t/t_lint_multidriven_coverage_bad.py index dceacd1b0..7a3c551cc 100755 --- a/test_regress/t/t_lint_multidriven_coverage_bad.py +++ b/test_regress/t/t_lint_multidriven_coverage_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(verilator_flags2=["--coverage"], fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_lint_noreturn_param.py b/test_regress/t/t_lint_noreturn_param.py index 609a0c821..3be8e745b 100755 --- a/test_regress/t/t_lint_noreturn_param.py +++ b/test_regress/t/t_lint_noreturn_param.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator_st') +test.fourstate_capable = False test.compile(verilator_flags2=['-Wall -Wno-DECLFILENAME -Wno-NORETURN']) diff --git a/test_regress/t/t_lint_notredop.py b/test_regress/t/t_lint_notredop.py index 36e360e43..5c913fbaf 100755 --- a/test_regress/t/t_lint_notredop.py +++ b/test_regress/t/t_lint_notredop.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(top_filename="t/t_lint_notredop_bad.v", verilator_flags2=["-Wno-NOTREDOP"]) diff --git a/test_regress/t/t_lint_subout_bad.py b/test_regress/t/t_lint_subout_bad.py index 7e2db3ed9..9e57696d7 100755 --- a/test_regress/t/t_lint_subout_bad.py +++ b/test_regress/t/t_lint_subout_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile( # No --lint-only as got compile error diff --git a/test_regress/t/t_lint_syncasyncnet_bad.py b/test_regress/t/t_lint_syncasyncnet_bad.py index d95ff8477..d0e63c634 100755 --- a/test_regress/t/t_lint_syncasyncnet_bad.py +++ b/test_regress/t/t_lint_syncasyncnet_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(verilator_flags2=["-Wall -Wno-DECLFILENAME --if-depth 10"], fails=True, diff --git a/test_regress/t/t_lint_top_bad.py b/test_regress/t/t_lint_top_bad.py index 15fe13439..18aa820b8 100755 --- a/test_regress/t/t_lint_top_bad.py +++ b/test_regress/t/t_lint_top_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(verilator_flags2=['-O0 --trace-fst'], fails=True, diff --git a/test_regress/t/t_lint_unused_iface.py b/test_regress/t/t_lint_unused_iface.py index 1a4c2178b..1628b4b01 100755 --- a/test_regress/t/t_lint_unused_iface.py +++ b/test_regress/t/t_lint_unused_iface.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(verilator_flags2=["-Wall -Wno-DECLFILENAME"]) diff --git a/test_regress/t/t_lint_unusedloop_removed_bad.py b/test_regress/t/t_lint_unusedloop_removed_bad.py index d7d105625..3737c2598 100755 --- a/test_regress/t/t_lint_unusedloop_removed_bad.py +++ b/test_regress/t/t_lint_unusedloop_removed_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename, diff --git a/test_regress/t/t_lint_waitconst_bad.py b/test_regress/t/t_lint_waitconst_bad.py index 51f19853e..df1413e3d 100755 --- a/test_regress/t/t_lint_waitconst_bad.py +++ b/test_regress/t/t_lint_waitconst_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_timing_wait1.v" test.lint(expect_filename=test.golden_filename, fails=True) diff --git a/test_regress/t/t_lint_width_arraydecl.py b/test_regress/t/t_lint_width_arraydecl.py index 88752b416..859fae682 100755 --- a/test_regress/t/t_lint_width_arraydecl.py +++ b/test_regress/t/t_lint_width_arraydecl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint() diff --git a/test_regress/t/t_lint_width_bad.py b/test_regress/t/t_lint_width_bad.py index 3160d0589..763d0b4d6 100755 --- a/test_regress/t/t_lint_width_bad.py +++ b/test_regress/t/t_lint_width_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_lint_width_shift_bad.py b/test_regress/t/t_lint_width_shift_bad.py index 3160d0589..763d0b4d6 100755 --- a/test_regress/t/t_lint_width_shift_bad.py +++ b/test_regress/t/t_lint_width_shift_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_lint_widthexpand_docs_bad.py b/test_regress/t/t_lint_widthexpand_docs_bad.py index 9af3b8485..14551582e 100755 --- a/test_regress/t/t_lint_widthexpand_docs_bad.py +++ b/test_regress/t/t_lint_widthexpand_docs_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_lparam_assign_iface_array_typedef.py b/test_regress/t/t_lparam_assign_iface_array_typedef.py index 31b1f0e53..9da272f7d 100755 --- a/test_regress/t/t_lparam_assign_iface_array_typedef.py +++ b/test_regress/t/t_lparam_assign_iface_array_typedef.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_lparam_assign_iface_array_typedef2.py b/test_regress/t/t_lparam_assign_iface_array_typedef2.py index 31b1f0e53..9da272f7d 100755 --- a/test_regress/t/t_lparam_assign_iface_array_typedef2.py +++ b/test_regress/t/t_lparam_assign_iface_array_typedef2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_lparam_assign_iface_const.py b/test_regress/t/t_lparam_assign_iface_const.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_lparam_assign_iface_const.py +++ b/test_regress/t/t_lparam_assign_iface_const.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_lparam_assign_iface_typedef.py b/test_regress/t/t_lparam_assign_iface_typedef.py index 31b1f0e53..9da272f7d 100755 --- a/test_regress/t/t_lparam_assign_iface_typedef.py +++ b/test_regress/t/t_lparam_assign_iface_typedef.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_lparam_assign_iface_typedef3.py b/test_regress/t/t_lparam_assign_iface_typedef3.py index 31b1f0e53..9da272f7d 100755 --- a/test_regress/t/t_lparam_assign_iface_typedef3.py +++ b/test_regress/t/t_lparam_assign_iface_typedef3.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested2.py b/test_regress/t/t_lparam_assign_iface_typedef_nested2.py index 31b1f0e53..9da272f7d 100755 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested2.py +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested3.py b/test_regress/t/t_lparam_assign_iface_typedef_nested3.py index 31b1f0e53..9da272f7d 100755 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested3.py +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested3.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested4.py b/test_regress/t/t_lparam_assign_iface_typedef_nested4.py index 31b1f0e53..9da272f7d 100755 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested4.py +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested4.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested5.py b/test_regress/t/t_lparam_assign_iface_typedef_nested5.py index 31b1f0e53..9da272f7d 100755 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested5.py +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested5.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested6.py b/test_regress/t/t_lparam_assign_iface_typedef_nested6.py index 31b1f0e53..9da272f7d 100755 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested6.py +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested6.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_mod2.py b/test_regress/t/t_lparam_assign_iface_typedef_nested_mod2.py index 31b1f0e53..9da272f7d 100755 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested_mod2.py +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested_mod2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_mod3.py b/test_regress/t/t_lparam_assign_iface_typedef_nested_mod3.py index 31b1f0e53..9da272f7d 100755 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested_mod3.py +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested_mod3.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg1.py b/test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg1.py index 31b1f0e53..9da272f7d 100755 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg1.py +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg1.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg3.py b/test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg3.py index 31b1f0e53..9da272f7d 100755 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg3.py +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg3.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg4.py b/test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg4.py index 31b1f0e53..9da272f7d 100755 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg4.py +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg4.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg5.py b/test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg5.py index 31b1f0e53..9da272f7d 100755 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg5.py +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg5.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg.py b/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg.py index 31b1f0e53..9da272f7d 100755 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg.py +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg2.py b/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg2.py index 31b1f0e53..9da272f7d 100755 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg2.py +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg3.py b/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg3.py index 31b1f0e53..9da272f7d 100755 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg3.py +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg3.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_lparam_dep_iface0.py b/test_regress/t/t_lparam_dep_iface0.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_lparam_dep_iface0.py +++ b/test_regress/t/t_lparam_dep_iface0.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_lparam_dep_iface1.py b/test_regress/t/t_lparam_dep_iface1.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_lparam_dep_iface1.py +++ b/test_regress/t/t_lparam_dep_iface1.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_lparam_dep_iface14.py b/test_regress/t/t_lparam_dep_iface14.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_lparam_dep_iface14.py +++ b/test_regress/t/t_lparam_dep_iface14.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_lparam_dep_iface15.py b/test_regress/t/t_lparam_dep_iface15.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_lparam_dep_iface15.py +++ b/test_regress/t/t_lparam_dep_iface15.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_lparam_dep_iface16.py b/test_regress/t/t_lparam_dep_iface16.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_lparam_dep_iface16.py +++ b/test_regress/t/t_lparam_dep_iface16.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_mailbox.py b/test_regress/t/t_mailbox.py index 72b5f8d81..029115332 100755 --- a/test_regress/t/t_mailbox.py +++ b/test_regress/t/t_mailbox.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary -Wall"]) diff --git a/test_regress/t/t_mailbox_array.py b/test_regress/t/t_mailbox_array.py index 1af568d44..c4c218b1f 100755 --- a/test_regress/t/t_mailbox_array.py +++ b/test_regress/t/t_mailbox_array.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--fno-slice']) # TODO remove -fno-slice, issue #5632/#5644 diff --git a/test_regress/t/t_mailbox_class.py b/test_regress/t/t_mailbox_class.py index e6fe26a20..c255c978b 100755 --- a/test_regress/t/t_mailbox_class.py +++ b/test_regress/t/t_mailbox_class.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_mailbox_concurrent.py b/test_regress/t/t_mailbox_concurrent.py index 55248e18d..0c18d9c79 100755 --- a/test_regress/t/t_mailbox_concurrent.py +++ b/test_regress/t/t_mailbox_concurrent.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_mailbox_notiming.py b/test_regress/t/t_mailbox_notiming.py index 5a1059281..9ad35117e 100755 --- a/test_regress/t/t_mailbox_notiming.py +++ b/test_regress/t/t_mailbox_notiming.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--exe --main --no-timing -Wall"]) diff --git a/test_regress/t/t_mailbox_std.py b/test_regress/t/t_mailbox_std.py index 5bacf05bf..21c9076d3 100755 --- a/test_regress/t/t_mailbox_std.py +++ b/test_regress/t/t_mailbox_std.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_mailbox.v" test.compile(verilator_flags2=["--binary -Wall --Wpedantic -DMAILBOX_T=std::mailbox"]) diff --git a/test_regress/t/t_mailbox_struct_param.py b/test_regress/t/t_mailbox_struct_param.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_mailbox_struct_param.py +++ b/test_regress/t/t_mailbox_struct_param.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_mailbox_unbounded.py b/test_regress/t/t_mailbox_unbounded.py index 72b5f8d81..029115332 100755 --- a/test_regress/t/t_mailbox_unbounded.py +++ b/test_regress/t/t_mailbox_unbounded.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary -Wall"]) diff --git a/test_regress/t/t_math_arith.py b/test_regress/t/t_math_arith.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_math_arith.py +++ b/test_regress/t/t_math_arith.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_math_clog2.py b/test_regress/t/t_math_clog2.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_math_clog2.py +++ b/test_regress/t/t_math_clog2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_math_cmp.py b/test_regress/t/t_math_cmp.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_math_cmp.py +++ b/test_regress/t/t_math_cmp.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_math_concat64.py b/test_regress/t/t_math_concat64.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_math_concat64.py +++ b/test_regress/t/t_math_concat64.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_math_cond_huge.py b/test_regress/t/t_math_cond_huge.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_math_cond_huge.py +++ b/test_regress/t/t_math_cond_huge.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_math_cond_huge_noexpand.py b/test_regress/t/t_math_cond_huge_noexpand.py index 47c1a25c1..0ab33e6a5 100755 --- a/test_regress/t/t_math_cond_huge_noexpand.py +++ b/test_regress/t/t_math_cond_huge_noexpand.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_math_cond_huge.v" test.compile(verilator_flags2=['-fno-expand']) diff --git a/test_regress/t/t_math_const.py b/test_regress/t/t_math_const.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_math_const.py +++ b/test_regress/t/t_math_const.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_math_countbits.py b/test_regress/t/t_math_countbits.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_math_countbits.py +++ b/test_regress/t/t_math_countbits.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_math_countbits_tri.py b/test_regress/t/t_math_countbits_tri.py index 690ae1cbf..6dc1eb6bb 100755 --- a/test_regress/t/t_math_countbits_tri.py +++ b/test_regress/t/t_math_countbits_tri.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--assert']) diff --git a/test_regress/t/t_math_cv_bitop.py b/test_regress/t/t_math_cv_bitop.py index 4641abd21..76fcaa443 100755 --- a/test_regress/t/t_math_cv_bitop.py +++ b/test_regress/t/t_math_cv_bitop.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_math_cv_concat.py b/test_regress/t/t_math_cv_concat.py index bf473484c..d25e5be40 100755 --- a/test_regress/t/t_math_cv_concat.py +++ b/test_regress/t/t_math_cv_concat.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary', '-fno-expand']) diff --git a/test_regress/t/t_math_cv_format.py b/test_regress/t/t_math_cv_format.py index 31b1f0e53..9da272f7d 100755 --- a/test_regress/t/t_math_cv_format.py +++ b/test_regress/t/t_math_cv_format.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_math_div.py b/test_regress/t/t_math_div.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_math_div.py +++ b/test_regress/t/t_math_div.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_math_div0.py b/test_regress/t/t_math_div0.py index 2b64bb43a..4a148412d 100755 --- a/test_regress/t/t_math_div0.py +++ b/test_regress/t/t_math_div0.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--x-assign 0']) diff --git a/test_regress/t/t_math_div_noexpand.py b/test_regress/t/t_math_div_noexpand.py index b7466ff27..d59e3186b 100755 --- a/test_regress/t/t_math_div_noexpand.py +++ b/test_regress/t/t_math_div_noexpand.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_math_div.v" test.compile(verilator_flags2=['-fno-expand']) diff --git a/test_regress/t/t_math_divw.py b/test_regress/t/t_math_divw.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_math_divw.py +++ b/test_regress/t/t_math_divw.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_math_eq.py b/test_regress/t/t_math_eq.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_math_eq.py +++ b/test_regress/t/t_math_eq.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_math_eq_noexpand.py b/test_regress/t/t_math_eq_noexpand.py index 01bfdfdb6..c90cc094f 100755 --- a/test_regress/t/t_math_eq_noexpand.py +++ b/test_regress/t/t_math_eq_noexpand.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_math_eq.v" test.compile(verilator_flags2=['-fno-expand']) diff --git a/test_regress/t/t_math_imm.py b/test_regress/t/t_math_imm.py index 84c09a3bb..73c8707f4 100755 --- a/test_regress/t/t_math_imm.py +++ b/test_regress/t/t_math_imm.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile( # We have deep expressions we want to test) diff --git a/test_regress/t/t_math_imm2.py b/test_regress/t/t_math_imm2.py index c012be81c..ef8972023 100755 --- a/test_regress/t/t_math_imm2.py +++ b/test_regress/t/t_math_imm2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) diff --git a/test_regress/t/t_math_insert_bound.py b/test_regress/t/t_math_insert_bound.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_math_insert_bound.py +++ b/test_regress/t/t_math_insert_bound.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_math_mul.py b/test_regress/t/t_math_mul.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_math_mul.py +++ b/test_regress/t/t_math_mul.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_math_pick.py b/test_regress/t/t_math_pick.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_math_pick.py +++ b/test_regress/t/t_math_pick.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_math_postinc.py b/test_regress/t/t_math_postinc.py index 8a938befd..a10e2547d 100755 --- a/test_regress/t/t_math_postinc.py +++ b/test_regress/t/t_math_postinc.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_math_pow.py b/test_regress/t/t_math_pow.py index 4b2bfc513..42fb1c67b 100755 --- a/test_regress/t/t_math_pow.py +++ b/test_regress/t/t_math_pow.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['-fno-gate']) diff --git a/test_regress/t/t_math_pow2.py b/test_regress/t/t_math_pow2.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_math_pow2.py +++ b/test_regress/t/t_math_pow2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_math_pow5.py b/test_regress/t/t_math_pow5.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_math_pow5.py +++ b/test_regress/t/t_math_pow5.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_math_pow6.py b/test_regress/t/t_math_pow6.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_math_pow6.py +++ b/test_regress/t/t_math_pow6.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_math_pow7.py b/test_regress/t/t_math_pow7.py index b6662862a..0b2328993 100755 --- a/test_regress/t/t_math_pow7.py +++ b/test_regress/t/t_math_pow7.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) diff --git a/test_regress/t/t_math_precedence.py b/test_regress/t/t_math_precedence.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_math_precedence.py +++ b/test_regress/t/t_math_precedence.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_math_real.py b/test_regress/t/t_math_real.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_math_real.py +++ b/test_regress/t/t_math_real.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_math_real_random.py b/test_regress/t/t_math_real_random.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_math_real_random.py +++ b/test_regress/t/t_math_real_random.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_math_real_round.py b/test_regress/t/t_math_real_round.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_math_real_round.py +++ b/test_regress/t/t_math_real_round.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_math_repl.py b/test_regress/t/t_math_repl.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_math_repl.py +++ b/test_regress/t/t_math_repl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_math_reverse.py b/test_regress/t/t_math_reverse.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_math_reverse.py +++ b/test_regress/t/t_math_reverse.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_math_shift.py b/test_regress/t/t_math_shift.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_math_shift.py +++ b/test_regress/t/t_math_shift.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_math_shift_noexpand.py b/test_regress/t/t_math_shift_noexpand.py index 1e604ddc3..b9681a9f5 100755 --- a/test_regress/t/t_math_shift_noexpand.py +++ b/test_regress/t/t_math_shift_noexpand.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_math_shift.v" test.compile(verilator_flags2=['-fno-expand']) diff --git a/test_regress/t/t_math_shiftrs.py b/test_regress/t/t_math_shiftrs.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_math_shiftrs.py +++ b/test_regress/t/t_math_shiftrs.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_math_shortcircuit_assocsel.py b/test_regress/t/t_math_shortcircuit_assocsel.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_math_shortcircuit_assocsel.py +++ b/test_regress/t/t_math_shortcircuit_assocsel.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_math_shortcircuit_dynsel.py b/test_regress/t/t_math_shortcircuit_dynsel.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_math_shortcircuit_dynsel.py +++ b/test_regress/t/t_math_shortcircuit_dynsel.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_math_shortreal.py b/test_regress/t/t_math_shortreal.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_math_shortreal.py +++ b/test_regress/t/t_math_shortreal.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_math_signed.py b/test_regress/t/t_math_signed.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_math_signed.py +++ b/test_regress/t/t_math_signed.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_math_signed2.py b/test_regress/t/t_math_signed2.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_math_signed2.py +++ b/test_regress/t/t_math_signed2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_math_signed3_noopt.py b/test_regress/t/t_math_signed3_noopt.py index 1903e42f5..05477d6c0 100755 --- a/test_regress/t/t_math_signed3_noopt.py +++ b/test_regress/t/t_math_signed3_noopt.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_math_signed3.v" diff --git a/test_regress/t/t_math_signed6.py b/test_regress/t/t_math_signed6.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_math_signed6.py +++ b/test_regress/t/t_math_signed6.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_math_signed_noexpand.py b/test_regress/t/t_math_signed_noexpand.py index c374a73cb..325e1fac5 100755 --- a/test_regress/t/t_math_signed_noexpand.py +++ b/test_regress/t/t_math_signed_noexpand.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_math_signed.v" test.compile(verilator_flags2=['-fno-expand']) diff --git a/test_regress/t/t_math_svl.py b/test_regress/t/t_math_svl.py index 7c9216f0e..4d3043b29 100755 --- a/test_regress/t/t_math_svl.py +++ b/test_regress/t/t_math_svl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_math_swap.py b/test_regress/t/t_math_swap.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_math_swap.py +++ b/test_regress/t/t_math_swap.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_math_synmul.py b/test_regress/t/t_math_synmul.py index 7f09b9e2c..ce6fd3122 100755 --- a/test_regress/t/t_math_synmul.py +++ b/test_regress/t/t_math_synmul.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["-Wno-UNOPTTHREADS"]) diff --git a/test_regress/t/t_math_trig.py b/test_regress/t/t_math_trig.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_math_trig.py +++ b/test_regress/t/t_math_trig.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_math_vgen.py b/test_regress/t/t_math_vgen.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_math_vgen.py +++ b/test_regress/t/t_math_vgen.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_math_vliw_noexpand.py b/test_regress/t/t_math_vliw_noexpand.py index 504aca69c..638468a44 100755 --- a/test_regress/t/t_math_vliw_noexpand.py +++ b/test_regress/t/t_math_vliw_noexpand.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_math_vliw.v" test.compile(verilator_flags2=['-fno-expand']) diff --git a/test_regress/t/t_math_wallace.py b/test_regress/t/t_math_wallace.py index c8511382a..47e15434c 100755 --- a/test_regress/t/t_math_wallace.py +++ b/test_regress/t/t_math_wallace.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_math_wide_bad.py b/test_regress/t/t_math_wide_bad.py index c7d9b21a5..692e6eeb1 100755 --- a/test_regress/t/t_math_wide_bad.py +++ b/test_regress/t/t_math_wide_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_mem.py b/test_regress/t/t_mem.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_mem.py +++ b/test_regress/t/t_mem.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_mem_banks.py b/test_regress/t/t_mem_banks.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_mem_banks.py +++ b/test_regress/t/t_mem_banks.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_mem_bound_bad.py b/test_regress/t/t_mem_bound_bad.py index 0b18482f0..2bd3a9236 100755 --- a/test_regress/t/t_mem_bound_bad.py +++ b/test_regress/t/t_mem_bound_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint( # Should fail, but doesn't) diff --git a/test_regress/t/t_mem_cond.py b/test_regress/t/t_mem_cond.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_mem_cond.py +++ b/test_regress/t/t_mem_cond.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_mem_fifo.py b/test_regress/t/t_mem_fifo.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_mem_fifo.py +++ b/test_regress/t/t_mem_fifo.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_mem_file.py b/test_regress/t/t_mem_file.py index c996a862c..b0623d58c 100755 --- a/test_regress/t/t_mem_file.py +++ b/test_regress/t/t_mem_file.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=[test.wno_unopthreads_for_few_cores]) diff --git a/test_regress/t/t_mem_first.py b/test_regress/t/t_mem_first.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_mem_first.py +++ b/test_regress/t/t_mem_first.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_mem_func.py b/test_regress/t/t_mem_func.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_mem_func.py +++ b/test_regress/t/t_mem_func.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_mem_iforder.py b/test_regress/t/t_mem_iforder.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_mem_iforder.py +++ b/test_regress/t/t_mem_iforder.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_mem_multi_io.py b/test_regress/t/t_mem_multi_io.py index 598ae0253..80c4432be 100755 --- a/test_regress/t/t_mem_multi_io.py +++ b/test_regress/t/t_mem_multi_io.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile( # Disable inlining, this test is trivial without it diff --git a/test_regress/t/t_mem_multi_io2_cc.py b/test_regress/t/t_mem_multi_io2_cc.py index c6c932196..9258635a4 100755 --- a/test_regress/t/t_mem_multi_io2_cc.py +++ b/test_regress/t/t_mem_multi_io2_cc.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.pli_filename = "t/t_mem_multi_io2.cpp" test.top_filename = "t/t_mem_multi_io2.v" diff --git a/test_regress/t/t_mem_multi_io2_sc.py b/test_regress/t/t_mem_multi_io2_sc.py index 703f7eb10..5e5b4d8f6 100755 --- a/test_regress/t/t_mem_multi_io2_sc.py +++ b/test_regress/t/t_mem_multi_io2_sc.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.pli_filename = "t/t_mem_multi_io2.cpp" test.top_filename = "t/t_mem_multi_io2.v" diff --git a/test_regress/t/t_mem_multi_io3_cc.py b/test_regress/t/t_mem_multi_io3_cc.py index dc29bdca4..1e76372f8 100755 --- a/test_regress/t/t_mem_multi_io3_cc.py +++ b/test_regress/t/t_mem_multi_io3_cc.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.pli_filename = "t/t_mem_multi_io3.cpp" test.top_filename = "t/t_mem_multi_io3.v" diff --git a/test_regress/t/t_mem_multi_io3_sc.py b/test_regress/t/t_mem_multi_io3_sc.py index de51ff34a..b4eaf879a 100755 --- a/test_regress/t/t_mem_multi_io3_sc.py +++ b/test_regress/t/t_mem_multi_io3_sc.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.pli_filename = "t/t_mem_multi_io3.cpp" test.top_filename = "t/t_mem_multi_io3.v" diff --git a/test_regress/t/t_mem_multidim.py b/test_regress/t/t_mem_multidim.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_mem_multidim.py +++ b/test_regress/t/t_mem_multidim.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_mem_multidim_Ox.py b/test_regress/t/t_mem_multidim_Ox.py index cdb59a71a..7a7952984 100755 --- a/test_regress/t/t_mem_multidim_Ox.py +++ b/test_regress/t/t_mem_multidim_Ox.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_mem_multidim.v" test.compile(verilator_flags2=['--fno-expand']) diff --git a/test_regress/t/t_mem_multidim_trace.py b/test_regress/t/t_mem_multidim_trace.py index 7da947d30..6b8b3c473 100755 --- a/test_regress/t/t_mem_multidim_trace.py +++ b/test_regress/t/t_mem_multidim_trace.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_mem_multidim.v" test.compile(verilator_flags2=['--cc --trace-vcd']) diff --git a/test_regress/t/t_mem_multiwire.py b/test_regress/t/t_mem_multiwire.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_mem_multiwire.py +++ b/test_regress/t/t_mem_multiwire.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_mem_packed.py b/test_regress/t/t_mem_packed.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_mem_packed.py +++ b/test_regress/t/t_mem_packed.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_mem_packed_assign.py b/test_regress/t/t_mem_packed_assign.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_mem_packed_assign.py +++ b/test_regress/t/t_mem_packed_assign.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_mem_packed_bad.py b/test_regress/t/t_mem_packed_bad.py index c7d9b21a5..692e6eeb1 100755 --- a/test_regress/t/t_mem_packed_bad.py +++ b/test_regress/t/t_mem_packed_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_mem_packed_noexpand.py b/test_regress/t/t_mem_packed_noexpand.py index 839d9ad10..db0334bf8 100755 --- a/test_regress/t/t_mem_packed_noexpand.py +++ b/test_regress/t/t_mem_packed_noexpand.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_mem_packed.v" test.compile(verilator_flags2=['-fno-expand']) diff --git a/test_regress/t/t_mem_shift.py b/test_regress/t/t_mem_shift.py index 4768655a8..b3708c0b5 100755 --- a/test_regress/t/t_mem_shift.py +++ b/test_regress/t/t_mem_shift.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--stats"]) diff --git a/test_regress/t/t_mem_slice.py b/test_regress/t/t_mem_slice.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_mem_slice.py +++ b/test_regress/t/t_mem_slice.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_mem_slice_conc_bad.py b/test_regress/t/t_mem_slice_conc_bad.py index c7d9b21a5..692e6eeb1 100755 --- a/test_regress/t/t_mem_slice_conc_bad.py +++ b/test_regress/t/t_mem_slice_conc_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_mem_slice_dtype_bad.py b/test_regress/t/t_mem_slice_dtype_bad.py index c7d9b21a5..692e6eeb1 100755 --- a/test_regress/t/t_mem_slice_dtype_bad.py +++ b/test_regress/t/t_mem_slice_dtype_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_mem_slot.py b/test_regress/t/t_mem_slot.py index eb8f88301..93a0cc779 100755 --- a/test_regress/t/t_mem_slot.py +++ b/test_regress/t/t_mem_slot.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.compile(make_top_shell=False, make_main=False, diff --git a/test_regress/t/t_mem_trace_split.py b/test_regress/t/t_mem_trace_split.py index 13eac0ce8..cc970de7e 100755 --- a/test_regress/t/t_mem_trace_split.py +++ b/test_regress/t/t_mem_trace_split.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--trace-vcd", "--trace-structs", "--output-split-ctrace", "32"]) diff --git a/test_regress/t/t_mem_twoedge.py b/test_regress/t/t_mem_twoedge.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_mem_twoedge.py +++ b/test_regress/t/t_mem_twoedge.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_mod_interface_array0.py b/test_regress/t/t_mod_interface_array0.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_mod_interface_array0.py +++ b/test_regress/t/t_mod_interface_array0.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_mod_interface_array0_noinl.py b/test_regress/t/t_mod_interface_array0_noinl.py index db670e888..445656801 100755 --- a/test_regress/t/t_mod_interface_array0_noinl.py +++ b/test_regress/t/t_mod_interface_array0_noinl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_mod_interface_array0.v" test.compile(v_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_mod_interface_array1.py b/test_regress/t/t_mod_interface_array1.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_mod_interface_array1.py +++ b/test_regress/t/t_mod_interface_array1.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_mod_interface_array1_noinl.py b/test_regress/t/t_mod_interface_array1_noinl.py index 22bd5306c..42038acf5 100755 --- a/test_regress/t/t_mod_interface_array1_noinl.py +++ b/test_regress/t/t_mod_interface_array1_noinl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_mod_interface_array1.v" test.compile(v_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_mod_interface_array2.py b/test_regress/t/t_mod_interface_array2.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_mod_interface_array2.py +++ b/test_regress/t/t_mod_interface_array2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_mod_interface_array2_noinl.py b/test_regress/t/t_mod_interface_array2_noinl.py index 02ffd87ef..2f85a3ab8 100755 --- a/test_regress/t/t_mod_interface_array2_noinl.py +++ b/test_regress/t/t_mod_interface_array2_noinl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_mod_interface_array2.v" test.compile(v_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_mod_interface_array4_noinl.py b/test_regress/t/t_mod_interface_array4_noinl.py index f0fae16bf..0fcf602f7 100755 --- a/test_regress/t/t_mod_interface_array4_noinl.py +++ b/test_regress/t/t_mod_interface_array4_noinl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_mod_interface_array4.v" test.compile(v_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_mod_interface_array5.py b/test_regress/t/t_mod_interface_array5.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_mod_interface_array5.py +++ b/test_regress/t/t_mod_interface_array5.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_mod_interface_array6_noinl.py b/test_regress/t/t_mod_interface_array6_noinl.py index f8d264939..7982f490b 100755 --- a/test_regress/t/t_mod_interface_array6_noinl.py +++ b/test_regress/t/t_mod_interface_array6_noinl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_mod_interface_array6.v" test.compile(v_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_mod_interface_clocking.py b/test_regress/t/t_mod_interface_clocking.py index 7ded63f3a..d210ebd50 100755 --- a/test_regress/t/t_mod_interface_clocking.py +++ b/test_regress/t/t_mod_interface_clocking.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_mod_param_class_typedef7.py b/test_regress/t/t_mod_param_class_typedef7.py index 31b1f0e53..9da272f7d 100755 --- a/test_regress/t/t_mod_param_class_typedef7.py +++ b/test_regress/t/t_mod_param_class_typedef7.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_mod_recurse.py b/test_regress/t/t_mod_recurse.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_mod_recurse.py +++ b/test_regress/t/t_mod_recurse.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_modport_export_task.py b/test_regress/t/t_modport_export_task.py index 8a938befd..a10e2547d 100755 --- a/test_regress/t/t_modport_export_task.py +++ b/test_regress/t/t_modport_export_task.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_module_input_default_value.py b/test_regress/t/t_module_input_default_value.py index d7538fa31..8e1a74184 100755 --- a/test_regress/t/t_module_input_default_value.py +++ b/test_regress/t/t_module_input_default_value.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False # Coverage for Issue #5920 test.compile(verilator_flags2=['--coverage-line']) diff --git a/test_regress/t/t_module_input_default_value_noinl.py b/test_regress/t/t_module_input_default_value_noinl.py index a105d2781..355014601 100755 --- a/test_regress/t/t_module_input_default_value_noinl.py +++ b/test_regress/t/t_module_input_default_value_noinl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_module_input_default_value.v" test.compile(v_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_module_reserved_keyword.py b/test_regress/t/t_module_reserved_keyword.py index 73bf16577..af040e5c5 100755 --- a/test_regress/t/t_module_reserved_keyword.py +++ b/test_regress/t/t_module_reserved_keyword.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios("simulator") +test.fourstate_capable = False test.compile( verilator_flags2=[ diff --git a/test_regress/t/t_multidriven_funcret0.py b/test_regress/t/t_multidriven_funcret0.py index 31b1f0e53..9da272f7d 100755 --- a/test_regress/t/t_multidriven_funcret0.py +++ b/test_regress/t/t_multidriven_funcret0.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_multidriven_iface.py b/test_regress/t/t_multidriven_iface.py index 31b1f0e53..9da272f7d 100755 --- a/test_regress/t/t_multidriven_iface.py +++ b/test_regress/t/t_multidriven_iface.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_multidriven_simple.py b/test_regress/t/t_multidriven_simple.py index 31b1f0e53..9da272f7d 100755 --- a/test_regress/t/t_multidriven_simple.py +++ b/test_regress/t/t_multidriven_simple.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_nba_assign_on_rhs.py b/test_regress/t/t_nba_assign_on_rhs.py index eafe7e6e5..f1d781219 100755 --- a/test_regress/t/t_nba_assign_on_rhs.py +++ b/test_regress/t/t_nba_assign_on_rhs.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_nba_commit_queue.py b/test_regress/t/t_nba_commit_queue.py index 63d6c69e3..f06305449 100755 --- a/test_regress/t/t_nba_commit_queue.py +++ b/test_regress/t/t_nba_commit_queue.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.compile(verilator_flags2=["-unroll-count 1", "--stats"]) diff --git a/test_regress/t/t_nba_hier.py b/test_regress/t/t_nba_hier.py index adb8e4da8..13dfbc407 100755 --- a/test_regress/t/t_nba_hier.py +++ b/test_regress/t/t_nba_hier.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary', '--stats', '-fno-inline', '--unroll-count', '0']) diff --git a/test_regress/t/t_nba_mixed_update_clocked.py b/test_regress/t/t_nba_mixed_update_clocked.py index f8e05bf18..96c229114 100755 --- a/test_regress/t/t_nba_mixed_update_clocked.py +++ b/test_regress/t/t_nba_mixed_update_clocked.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.compile(verilator_flags2=["--stats", "--unroll-count", "1"]) diff --git a/test_regress/t/t_nba_mixed_update_comb.py b/test_regress/t/t_nba_mixed_update_comb.py index 063b96de3..197a780d8 100755 --- a/test_regress/t/t_nba_mixed_update_comb.py +++ b/test_regress/t/t_nba_mixed_update_comb.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.compile(verilator_flags2=["--stats", "--unroll-count", "1"]) diff --git a/test_regress/t/t_nba_shared_flag_reuse.py b/test_regress/t/t_nba_shared_flag_reuse.py index 4ee7f9e14..64d4ecb78 100755 --- a/test_regress/t/t_nba_shared_flag_reuse.py +++ b/test_regress/t/t_nba_shared_flag_reuse.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary']) diff --git a/test_regress/t/t_net_delay_timing.py b/test_regress/t/t_net_delay_timing.py index 442c015eb..384d2fe50 100755 --- a/test_regress/t/t_net_delay_timing.py +++ b/test_regress/t/t_net_delay_timing.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_net_delay.v" test.compile(timing_loop=True, verilator_flags2=["--timing"]) diff --git a/test_regress/t/t_net_delay_timing_sc.py b/test_regress/t/t_net_delay_timing_sc.py index b99593275..1e9662516 100755 --- a/test_regress/t/t_net_delay_timing_sc.py +++ b/test_regress/t/t_net_delay_timing_sc.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_net_delay.v" test.main_time_multiplier = 2 diff --git a/test_regress/t/t_no_sel_assign_merge_in_cpp.py b/test_regress/t/t_no_sel_assign_merge_in_cpp.py index 88752b416..859fae682 100755 --- a/test_regress/t/t_no_sel_assign_merge_in_cpp.py +++ b/test_regress/t/t_no_sel_assign_merge_in_cpp.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint() diff --git a/test_regress/t/t_no_trace_top.py b/test_regress/t/t_no_trace_top.py index 83cc873eb..2f22e45f7 100755 --- a/test_regress/t/t_no_trace_top.py +++ b/test_regress/t/t_no_trace_top.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.top_filename = "t_trace_cat.v" test.compile(make_top_shell=False, diff --git a/test_regress/t/t_oob_2state_array.py b/test_regress/t/t_oob_2state_array.py index 7b63fce7f..51314f295 100755 --- a/test_regress/t/t_oob_2state_array.py +++ b/test_regress/t/t_oob_2state_array.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False # x-assign shouldn't affect 2-state oob read test.compile(verilator_flags2=["--binary --x-assign 1"]) diff --git a/test_regress/t/t_opt_assemble_cellarray.py b/test_regress/t/t_opt_assemble_cellarray.py index 79e99cda4..952b06286 100755 --- a/test_regress/t/t_opt_assemble_cellarray.py +++ b/test_regress/t/t_opt_assemble_cellarray.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(v_flags2=["--stats -fno-dfg"]) diff --git a/test_regress/t/t_opt_assemble_cellarray_off.py b/test_regress/t/t_opt_assemble_cellarray_off.py index ba7ec6d37..646418127 100755 --- a/test_regress/t/t_opt_assemble_cellarray_off.py +++ b/test_regress/t/t_opt_assemble_cellarray_off.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator_st') +test.fourstate_capable = False test.top_filename = "t/t_opt_life.v" test.compile(verilator_flags2=['--stats', '-fno-assemble']) diff --git a/test_regress/t/t_opt_balance_cats.py b/test_regress/t/t_opt_balance_cats.py index d5e863848..3852011ad 100755 --- a/test_regress/t/t_opt_balance_cats.py +++ b/test_regress/t/t_opt_balance_cats.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile( verilator_flags2=["--stats", "--build", "--gate-stmts", "10000", "--expand-limit", "128"]) diff --git a/test_regress/t/t_opt_balance_cats_nofunc.py b/test_regress/t/t_opt_balance_cats_nofunc.py index 4f19c30eb..936cd66b9 100755 --- a/test_regress/t/t_opt_balance_cats_nofunc.py +++ b/test_regress/t/t_opt_balance_cats_nofunc.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_opt_balance_cats.v" diff --git a/test_regress/t/t_opt_balance_cats_sc.py b/test_regress/t/t_opt_balance_cats_sc.py index ff851ed2a..ca34a48e4 100755 --- a/test_regress/t/t_opt_balance_cats_sc.py +++ b/test_regress/t/t_opt_balance_cats_sc.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_opt_balance_cats.v" diff --git a/test_regress/t/t_opt_const.py b/test_regress/t/t_opt_const.py index fa2e1cfee..36e4f29e1 100755 --- a/test_regress/t/t_opt_const.py +++ b/test_regress/t/t_opt_const.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["-Wno-UNOPTTHREADS", "-fno-dfg", "--stats", test.pli_filename]) diff --git a/test_regress/t/t_opt_const_cond_redundant.py b/test_regress/t/t_opt_const_cond_redundant.py index ee4352503..6f91aa7fe 100755 --- a/test_regress/t/t_opt_const_cond_redundant.py +++ b/test_regress/t/t_opt_const_cond_redundant.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--stats']) diff --git a/test_regress/t/t_opt_const_cov.py b/test_regress/t/t_opt_const_cov.py index 8cff7b332..461cbdd7a 100755 --- a/test_regress/t/t_opt_const_cov.py +++ b/test_regress/t/t_opt_const_cov.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["-Wno-UNOPTTHREADS", "--stats", "--coverage", "--trace-vcd"]) diff --git a/test_regress/t/t_opt_const_dfg.py b/test_regress/t/t_opt_const_dfg.py index 41f6a2976..6cc489318 100755 --- a/test_regress/t/t_opt_const_dfg.py +++ b/test_regress/t/t_opt_const_dfg.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_opt_const.v" test.pli_filename = "t/t_opt_const.cpp" diff --git a/test_regress/t/t_opt_const_no_expand.py b/test_regress/t/t_opt_const_no_expand.py index 2ab023f16..9d973da60 100755 --- a/test_regress/t/t_opt_const_no_expand.py +++ b/test_regress/t/t_opt_const_no_expand.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_opt_const.v" test.compile(verilator_flags2=[ diff --git a/test_regress/t/t_opt_const_no_opt.py b/test_regress/t/t_opt_const_no_opt.py index 2d893a3c6..a37ee088e 100755 --- a/test_regress/t/t_opt_const_no_opt.py +++ b/test_regress/t/t_opt_const_no_opt.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_opt_const.v" # Run the same design as t_opt_const.py without bitopt tree optimization to make sure that the result is same. diff --git a/test_regress/t/t_opt_const_or.py b/test_regress/t/t_opt_const_or.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_opt_const_or.py +++ b/test_regress/t/t_opt_const_or.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_opt_const_red.py b/test_regress/t/t_opt_const_red.py index a47814311..41de85e7b 100755 --- a/test_regress/t/t_opt_const_red.py +++ b/test_regress/t/t_opt_const_red.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["-Wno-UNOPTTHREADS", "--stats"]) diff --git a/test_regress/t/t_opt_const_shortcut.py b/test_regress/t/t_opt_const_shortcut.py index bbe1eaf69..1d7558176 100755 --- a/test_regress/t/t_opt_const_shortcut.py +++ b/test_regress/t/t_opt_const_shortcut.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(v_flags2=["t/" + test.name + ".cpp"], verilator_flags2=["-Wno-UNOPTTHREADS", "--stats"]) diff --git a/test_regress/t/t_opt_constpool_recache.py b/test_regress/t/t_opt_constpool_recache.py index ac30d3a16..bdfbd5fe5 100755 --- a/test_regress/t/t_opt_constpool_recache.py +++ b/test_regress/t/t_opt_constpool_recache.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary', '--stats']) diff --git a/test_regress/t/t_opt_dedupe_clk_gate.py b/test_regress/t/t_opt_dedupe_clk_gate.py index 0fbd122ba..cf1fa1757 100755 --- a/test_regress/t/t_opt_dedupe_clk_gate.py +++ b/test_regress/t/t_opt_dedupe_clk_gate.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False out_filename = test.obj_dir + "/V" + test.name + ".tree.json" diff --git a/test_regress/t/t_opt_dedupe_seq_logic.py b/test_regress/t/t_opt_dedupe_seq_logic.py index 1a30d0dd9..21d8aa203 100755 --- a/test_regress/t/t_opt_dedupe_seq_logic.py +++ b/test_regress/t/t_opt_dedupe_seq_logic.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--stats"]) diff --git a/test_regress/t/t_opt_expand_keep_widths.py b/test_regress/t/t_opt_expand_keep_widths.py index 85a35d675..cee52dfd6 100755 --- a/test_regress/t/t_opt_expand_keep_widths.py +++ b/test_regress/t/t_opt_expand_keep_widths.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary']) diff --git a/test_regress/t/t_opt_if_array.py b/test_regress/t/t_opt_if_array.py index 9abf44601..7f7442a06 100755 --- a/test_regress/t/t_opt_if_array.py +++ b/test_regress/t/t_opt_if_array.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_opt_inline_cfuncs.py b/test_regress/t/t_opt_inline_cfuncs.py index 1821f5ec5..2f5a0f1b6 100755 --- a/test_regress/t/t_opt_inline_cfuncs.py +++ b/test_regress/t/t_opt_inline_cfuncs.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.compile(verilator_flags2=[ "--stats", "--binary", "--inline-cfuncs-product", "200", "--dumpi-V3InlineCFuncs", "9" diff --git a/test_regress/t/t_opt_inline_cfuncs_off.py b/test_regress/t/t_opt_inline_cfuncs_off.py index 7e7361d8c..4fbc66541 100755 --- a/test_regress/t/t_opt_inline_cfuncs_off.py +++ b/test_regress/t/t_opt_inline_cfuncs_off.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.top_filename = "t/t_opt_inline_cfuncs.v" test.compile(verilator_flags2=["--stats", "--binary", "-fno-inline-cfuncs"]) diff --git a/test_regress/t/t_opt_inline_cfuncs_trace.py b/test_regress/t/t_opt_inline_cfuncs_trace.py index 515aa4510..b702afda3 100755 --- a/test_regress/t/t_opt_inline_cfuncs_trace.py +++ b/test_regress/t/t_opt_inline_cfuncs_trace.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.top_filename = "t/t_opt_inline_cfuncs.v" test.compile(verilator_flags2=["--stats", "--binary", "--trace", "--inline-cfuncs-product", "200"]) diff --git a/test_regress/t/t_opt_inline_funcs.py b/test_regress/t/t_opt_inline_funcs.py index b644fe663..0820a4f34 100755 --- a/test_regress/t/t_opt_inline_funcs.py +++ b/test_regress/t/t_opt_inline_funcs.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary', '--stats']) diff --git a/test_regress/t/t_opt_inline_funcs_no.py b/test_regress/t/t_opt_inline_funcs_no.py index 88f96ac39..c68d88c19 100755 --- a/test_regress/t/t_opt_inline_funcs_no.py +++ b/test_regress/t/t_opt_inline_funcs_no.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_opt_inline_funcs.v" test.compile(verilator_flags2=['--binary', '--fno-inline-funcs', '--stats']) diff --git a/test_regress/t/t_opt_inline_funcs_no_eager.py b/test_regress/t/t_opt_inline_funcs_no_eager.py index 69590605e..bbcc9f3a7 100755 --- a/test_regress/t/t_opt_inline_funcs_no_eager.py +++ b/test_regress/t/t_opt_inline_funcs_no_eager.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_opt_inline_funcs.v" test.compile(verilator_flags2=['--binary', '--fno-inline-funcs-eager', '--stats']) diff --git a/test_regress/t/t_opt_life.py b/test_regress/t/t_opt_life.py index fa4b9bb88..24028e7d8 100755 --- a/test_regress/t/t_opt_life.py +++ b/test_regress/t/t_opt_life.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--stats"]) diff --git a/test_regress/t/t_opt_life_off.py b/test_regress/t/t_opt_life_off.py index cb69d4615..5206c82d5 100755 --- a/test_regress/t/t_opt_life_off.py +++ b/test_regress/t/t_opt_life_off.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator_st') +test.fourstate_capable = False test.top_filename = "t/t_opt_life.v" test.compile(verilator_flags2=['--stats', '-fno-life', '-fno-life-post']) diff --git a/test_regress/t/t_opt_merge_cond.py b/test_regress/t/t_opt_merge_cond.py index 0d506462e..bac486bb6 100755 --- a/test_regress/t/t_opt_merge_cond.py +++ b/test_regress/t/t_opt_merge_cond.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.compile(verilator_flags2=["-unroll-count 64", "--stats"]) diff --git a/test_regress/t/t_opt_merge_cond_blowup.py b/test_regress/t/t_opt_merge_cond_blowup.py index eadc43963..e16bf17d1 100755 --- a/test_regress/t/t_opt_merge_cond_blowup.py +++ b/test_regress/t/t_opt_merge_cond_blowup.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False # TODO: This takes excessively long on vltmt, this should be fixed diff --git a/test_regress/t/t_opt_merge_cond_bug_3409.py b/test_regress/t/t_opt_merge_cond_bug_3409.py index b352fb2c0..6df88b374 100755 --- a/test_regress/t/t_opt_merge_cond_bug_3409.py +++ b/test_regress/t/t_opt_merge_cond_bug_3409.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--stats"]) diff --git a/test_regress/t/t_opt_merge_cond_no_merge.py b/test_regress/t/t_opt_merge_cond_no_merge.py index 400394df9..4165ead14 100755 --- a/test_regress/t/t_opt_merge_cond_no_merge.py +++ b/test_regress/t/t_opt_merge_cond_no_merge.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.top_filename = "t/t_opt_merge_cond.v" test.compile(verilator_flags2=["-unroll-count 64", "--stats", "-fno-merge-cond"]) diff --git a/test_regress/t/t_opt_merge_cond_no_motion.py b/test_regress/t/t_opt_merge_cond_no_motion.py index 88b894b75..98ce4182e 100755 --- a/test_regress/t/t_opt_merge_cond_no_motion.py +++ b/test_regress/t/t_opt_merge_cond_no_motion.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.top_filename = "t/t_opt_merge_cond.v" test.compile(verilator_flags2=["-unroll-count 64", "--stats", "-fno-merge-cond-motion"]) diff --git a/test_regress/t/t_opt_slice.py b/test_regress/t/t_opt_slice.py index 6d138a3d9..103920b6d 100755 --- a/test_regress/t/t_opt_slice.py +++ b/test_regress/t/t_opt_slice.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--sc', '--stats']) diff --git a/test_regress/t/t_opt_slice_element_limit.py b/test_regress/t/t_opt_slice_element_limit.py index f5dd17ce1..4aae56e78 100755 --- a/test_regress/t/t_opt_slice_element_limit.py +++ b/test_regress/t/t_opt_slice_element_limit.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_opt_slice_element_limit.v" diff --git a/test_regress/t/t_opt_slice_element_limit_allow_all.py b/test_regress/t/t_opt_slice_element_limit_allow_all.py index 037614d4b..2a84d87bc 100755 --- a/test_regress/t/t_opt_slice_element_limit_allow_all.py +++ b/test_regress/t/t_opt_slice_element_limit_allow_all.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_opt_slice_element_limit.v" diff --git a/test_regress/t/t_opt_slice_element_limit_default.py b/test_regress/t/t_opt_slice_element_limit_default.py index 7d6d1ceee..1f4a00d72 100755 --- a/test_regress/t/t_opt_slice_element_limit_default.py +++ b/test_regress/t/t_opt_slice_element_limit_default.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_opt_slice_element_limit.v" diff --git a/test_regress/t/t_opt_slice_no.py b/test_regress/t/t_opt_slice_no.py index 4348edaec..f0fc7def8 100755 --- a/test_regress/t/t_opt_slice_no.py +++ b/test_regress/t/t_opt_slice_no.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = 't/t_opt_slice.v' test.compile(verilator_flags2=['--sc', '--stats', '-fno-slice']) diff --git a/test_regress/t/t_opt_subst.py b/test_regress/t/t_opt_subst.py index b013d8319..4aa2ab610 100755 --- a/test_regress/t/t_opt_subst.py +++ b/test_regress/t/t_opt_subst.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator_st') +test.fourstate_capable = False test.compile(verilator_flags2=["--stats"]) diff --git a/test_regress/t/t_opt_subst_off.py b/test_regress/t/t_opt_subst_off.py index c59b32156..c30f46bd6 100755 --- a/test_regress/t/t_opt_subst_off.py +++ b/test_regress/t/t_opt_subst_off.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator_st') +test.fourstate_capable = False test.top_filename = "t/t_opt_life.v" test.compile(verilator_flags2=['--stats', '-fno-subst', '-fno-subst-const']) diff --git a/test_regress/t/t_opt_table_display.py b/test_regress/t/t_opt_table_display.py index 000166723..df66a1d66 100755 --- a/test_regress/t/t_opt_table_display.py +++ b/test_regress/t/t_opt_table_display.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--stats"]) diff --git a/test_regress/t/t_opt_table_enum.py b/test_regress/t/t_opt_table_enum.py index 00a2e3a5a..ff8660084 100755 --- a/test_regress/t/t_opt_table_enum.py +++ b/test_regress/t/t_opt_table_enum.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--stats", "-fno-case-table", "-fno-case-decoder"]) diff --git a/test_regress/t/t_opt_table_fsm.py b/test_regress/t/t_opt_table_fsm.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_opt_table_fsm.py +++ b/test_regress/t/t_opt_table_fsm.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_opt_table_packed_array.py b/test_regress/t/t_opt_table_packed_array.py index 00a2e3a5a..ff8660084 100755 --- a/test_regress/t/t_opt_table_packed_array.py +++ b/test_regress/t/t_opt_table_packed_array.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--stats", "-fno-case-table", "-fno-case-decoder"]) diff --git a/test_regress/t/t_opt_table_real.py b/test_regress/t/t_opt_table_real.py index 00a2e3a5a..ff8660084 100755 --- a/test_regress/t/t_opt_table_real.py +++ b/test_regress/t/t_opt_table_real.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--stats", "-fno-case-table", "-fno-case-decoder"]) diff --git a/test_regress/t/t_opt_table_real_off.py b/test_regress/t/t_opt_table_real_off.py index fbe8fd693..870744699 100755 --- a/test_regress/t/t_opt_table_real_off.py +++ b/test_regress/t/t_opt_table_real_off.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator_st') +test.fourstate_capable = False test.top_filename = 't/t_opt_table_real.v' test.golden_filename = 't/t_opt_table_real.out' diff --git a/test_regress/t/t_opt_table_same.py b/test_regress/t/t_opt_table_same.py index 8f09062b6..987b7e4ea 100755 --- a/test_regress/t/t_opt_table_same.py +++ b/test_regress/t/t_opt_table_same.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--stats", "-fno-case-table", "-fno-case-decoder"]) diff --git a/test_regress/t/t_opt_table_signed.py b/test_regress/t/t_opt_table_signed.py index 00a2e3a5a..ff8660084 100755 --- a/test_regress/t/t_opt_table_signed.py +++ b/test_regress/t/t_opt_table_signed.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--stats", "-fno-case-table", "-fno-case-decoder"]) diff --git a/test_regress/t/t_opt_table_sparse.py b/test_regress/t/t_opt_table_sparse.py index 4563aa80d..99568788f 100755 --- a/test_regress/t/t_opt_table_sparse.py +++ b/test_regress/t/t_opt_table_sparse.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--stats"]) diff --git a/test_regress/t/t_opt_table_sparse_output_split.py b/test_regress/t/t_opt_table_sparse_output_split.py index 3205c18ab..b11cf2ee6 100755 --- a/test_regress/t/t_opt_table_sparse_output_split.py +++ b/test_regress/t/t_opt_table_sparse_output_split.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_opt_table_sparse.v" test.golden_filename = "t/t_opt_table_sparse.out" diff --git a/test_regress/t/t_opt_table_string.py b/test_regress/t/t_opt_table_string.py index 00a2e3a5a..ff8660084 100755 --- a/test_regress/t/t_opt_table_string.py +++ b/test_regress/t/t_opt_table_string.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--stats", "-fno-case-table", "-fno-case-decoder"]) diff --git a/test_regress/t/t_opt_table_struct.py b/test_regress/t/t_opt_table_struct.py index 00a2e3a5a..ff8660084 100755 --- a/test_regress/t/t_opt_table_struct.py +++ b/test_regress/t/t_opt_table_struct.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--stats", "-fno-case-table", "-fno-case-decoder"]) diff --git a/test_regress/t/t_order.py b/test_regress/t/t_order.py index de3ece11f..088bd20b1 100755 --- a/test_regress/t/t_order.py +++ b/test_regress/t/t_order.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.main_time_multiplier = 1e-8 / 1e-9 test.compile(verilator_flags2=["--timescale 10ns/1ns --no-timing"]) diff --git a/test_regress/t/t_order_2d.py b/test_regress/t/t_order_2d.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_order_2d.py +++ b/test_regress/t/t_order_2d.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_order_blkandnblk_bad.py b/test_regress/t/t_order_blkandnblk_bad.py index 3160d0589..763d0b4d6 100755 --- a/test_regress/t/t_order_blkandnblk_bad.py +++ b/test_regress/t/t_order_blkandnblk_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_order_clkinst.py b/test_regress/t/t_order_clkinst.py index 0a7133fe3..b2b716269 100755 --- a/test_regress/t/t_order_clkinst.py +++ b/test_regress/t/t_order_clkinst.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False # On Verilator, we expect this to pass. # diff --git a/test_regress/t/t_order_comboclkloop.py b/test_regress/t/t_order_comboclkloop.py index c02254607..01260b3a4 100755 --- a/test_regress/t/t_order_comboclkloop.py +++ b/test_regress/t/t_order_comboclkloop.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["-fno-dfg"]) diff --git a/test_regress/t/t_order_comboloop.py b/test_regress/t/t_order_comboloop.py index c02254607..01260b3a4 100755 --- a/test_regress/t/t_order_comboloop.py +++ b/test_regress/t/t_order_comboloop.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["-fno-dfg"]) diff --git a/test_regress/t/t_order_doubleloop.py b/test_regress/t/t_order_doubleloop.py index c02254607..01260b3a4 100755 --- a/test_regress/t/t_order_doubleloop.py +++ b/test_regress/t/t_order_doubleloop.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["-fno-dfg"]) diff --git a/test_regress/t/t_order_multidriven.py b/test_regress/t/t_order_multidriven.py index 6bff8cd57..16fad4635 100755 --- a/test_regress/t/t_order_multidriven.py +++ b/test_regress/t/t_order_multidriven.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.compile(make_top_shell=False, make_main=False, diff --git a/test_regress/t/t_order_quad.py b/test_regress/t/t_order_quad.py index 9ec50ba9b..01fd75174 100755 --- a/test_regress/t/t_order_quad.py +++ b/test_regress/t/t_order_quad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(make_top_shell=False, make_main=False, diff --git a/test_regress/t/t_order_timing.py b/test_regress/t/t_order_timing.py index 9131fbe59..0666406b3 100755 --- a/test_regress/t/t_order_timing.py +++ b/test_regress/t/t_order_timing.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_order.v" test.main_time_multiplier = 1e-8 / 1e-9 diff --git a/test_regress/t/t_package_dot.py b/test_regress/t/t_package_dot.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_package_dot.py +++ b/test_regress/t/t_package_dot.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_package_dup_bad2.py b/test_regress/t/t_package_dup_bad2.py index 1d5ccb8f4..c1876edec 100755 --- a/test_regress/t/t_package_dup_bad2.py +++ b/test_regress/t/t_package_dup_bad2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_package_import_param.py b/test_regress/t/t_package_import_param.py index d6d35e7fd..485ded93c 100755 --- a/test_regress/t/t_package_import_param.py +++ b/test_regress/t/t_package_import_param.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint() diff --git a/test_regress/t/t_param.py b/test_regress/t/t_param.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_param.py +++ b/test_regress/t/t_param.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_param_array5.py b/test_regress/t/t_param_array5.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_param_array5.py +++ b/test_regress/t/t_param_array5.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_param_array6.py b/test_regress/t/t_param_array6.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_param_array6.py +++ b/test_regress/t/t_param_array6.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_param_array6_noslice.py b/test_regress/t/t_param_array6_noslice.py index 4a59ae5c1..d2aa5ca78 100755 --- a/test_regress/t/t_param_array6_noslice.py +++ b/test_regress/t/t_param_array6_noslice.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_param_array6.v" test.compile(verilator_flags2=['-fno-slice']) diff --git a/test_regress/t/t_param_avec.py b/test_regress/t/t_param_avec.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_param_avec.py +++ b/test_regress/t/t_param_avec.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_param_bracket.py b/test_regress/t/t_param_bracket.py index 67b896515..8a1a7b033 100755 --- a/test_regress/t/t_param_bracket.py +++ b/test_regress/t/t_param_bracket.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint() diff --git a/test_regress/t/t_param_const_part.py b/test_regress/t/t_param_const_part.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_param_const_part.py +++ b/test_regress/t/t_param_const_part.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_param_ddeep_width.py b/test_regress/t/t_param_ddeep_width.py index 67b896515..8a1a7b033 100755 --- a/test_regress/t/t_param_ddeep_width.py +++ b/test_regress/t/t_param_ddeep_width.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint() diff --git a/test_regress/t/t_param_default_override.py b/test_regress/t/t_param_default_override.py index 6f4204c2e..335ec6e18 100755 --- a/test_regress/t/t_param_default_override.py +++ b/test_regress/t/t_param_default_override.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary -Wno-MULTITOP']) diff --git a/test_regress/t/t_param_first.py b/test_regress/t/t_param_first.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_param_first.py +++ b/test_regress/t/t_param_first.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_param_func.py b/test_regress/t/t_param_func.py index 66009b455..52533feae 100755 --- a/test_regress/t/t_param_func.py +++ b/test_regress/t/t_param_func.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_param_if_blk.py b/test_regress/t/t_param_if_blk.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_param_if_blk.py +++ b/test_regress/t/t_param_if_blk.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_param_in_func.py b/test_regress/t/t_param_in_func.py index 88c27220f..a36cde5e7 100755 --- a/test_regress/t/t_param_in_func.py +++ b/test_regress/t/t_param_in_func.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--stats"]) diff --git a/test_regress/t/t_param_in_func_noinline.py b/test_regress/t/t_param_in_func_noinline.py index 716aa43be..5a22c8459 100755 --- a/test_regress/t/t_param_in_func_noinline.py +++ b/test_regress/t/t_param_in_func_noinline.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_param_in_func.v" test.compile(verilator_flags2=["--stats", "+define+NO_INLINE=1"]) diff --git a/test_regress/t/t_param_mem_attr.py b/test_regress/t/t_param_mem_attr.py index 15689f8e3..143da2806 100755 --- a/test_regress/t/t_param_mem_attr.py +++ b/test_regress/t/t_param_mem_attr.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False # Compile only test. test.compile() diff --git a/test_regress/t/t_param_order.py b/test_regress/t/t_param_order.py index 8a938befd..a10e2547d 100755 --- a/test_regress/t/t_param_order.py +++ b/test_regress/t/t_param_order.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_param_pattern_init.py b/test_regress/t/t_param_pattern_init.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_param_pattern_init.py +++ b/test_regress/t/t_param_pattern_init.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_param_pattern_init_scope.py b/test_regress/t/t_param_pattern_init_scope.py index 84b274f68..17424b42f 100755 --- a/test_regress/t/t_param_pattern_init_scope.py +++ b/test_regress/t/t_param_pattern_init_scope.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_param_repl.py b/test_regress/t/t_param_repl.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_param_repl.py +++ b/test_regress/t/t_param_repl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_param_scope_bad.py b/test_regress/t/t_param_scope_bad.py index c7d9b21a5..692e6eeb1 100755 --- a/test_regress/t/t_param_scope_bad.py +++ b/test_regress/t/t_param_scope_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_param_sel_range1_bad.py b/test_regress/t/t_param_sel_range1_bad.py index 6e2f64a44..4e1f6a509 100755 --- a/test_regress/t/t_param_sel_range1_bad.py +++ b/test_regress/t/t_param_sel_range1_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.top_filename = "t/t_param_sel_range1.v" test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_param_shift.py b/test_regress/t/t_param_shift.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_param_shift.py +++ b/test_regress/t/t_param_shift.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_param_type.py b/test_regress/t/t_param_type.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_param_type.py +++ b/test_regress/t/t_param_type.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_param_type5.py b/test_regress/t/t_param_type5.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_param_type5.py +++ b/test_regress/t/t_param_type5.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_param_type_collision.py b/test_regress/t/t_param_type_collision.py index 787a3afd4..cf7135154 100755 --- a/test_regress/t/t_param_type_collision.py +++ b/test_regress/t/t_param_type_collision.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_param_type.v" test.compile(verilator_flags2=["--debug-collision"]) diff --git a/test_regress/t/t_param_type_dep_struct.py b/test_regress/t/t_param_type_dep_struct.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_param_type_dep_struct.py +++ b/test_regress/t/t_param_type_dep_struct.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_param_type_from_iface_struct.py b/test_regress/t/t_param_type_from_iface_struct.py index 44d191244..384788405 100755 --- a/test_regress/t/t_param_type_from_iface_struct.py +++ b/test_regress/t/t_param_type_from_iface_struct.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(v_flags2=["--binary"]) diff --git a/test_regress/t/t_param_type_struct_member.py b/test_regress/t/t_param_type_struct_member.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_param_type_struct_member.py +++ b/test_regress/t/t_param_type_struct_member.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_param_type_struct_member2.py b/test_regress/t/t_param_type_struct_member2.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_param_type_struct_member2.py +++ b/test_regress/t/t_param_type_struct_member2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_param_x_unique.py b/test_regress/t/t_param_x_unique.py index ce00f0a74..a59c0d478 100755 --- a/test_regress/t/t_param_x_unique.py +++ b/test_regress/t/t_param_x_unique.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--trace-fst --x-assign unique"]) diff --git a/test_regress/t/t_paramgraph_ascrange_prelim_cfg.py b/test_regress/t/t_paramgraph_ascrange_prelim_cfg.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_paramgraph_ascrange_prelim_cfg.py +++ b/test_regress/t/t_paramgraph_ascrange_prelim_cfg.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_paramgraph_bits_corruption.py b/test_regress/t/t_paramgraph_bits_corruption.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_paramgraph_bits_corruption.py +++ b/test_regress/t/t_paramgraph_bits_corruption.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_paramgraph_bits_iface_typedef.py b/test_regress/t/t_paramgraph_bits_iface_typedef.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_paramgraph_bits_iface_typedef.py +++ b/test_regress/t/t_paramgraph_bits_iface_typedef.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_paramgraph_comined_iface.py b/test_regress/t/t_paramgraph_comined_iface.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_paramgraph_comined_iface.py +++ b/test_regress/t/t_paramgraph_comined_iface.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_paramgraph_comined_iface_stats.py b/test_regress/t/t_paramgraph_comined_iface_stats.py index 4732b2b49..ca422be27 100755 --- a/test_regress/t/t_paramgraph_comined_iface_stats.py +++ b/test_regress/t/t_paramgraph_comined_iface_stats.py @@ -13,6 +13,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_paramgraph_comined_iface.v" diff --git a/test_regress/t/t_paramgraph_iface_array_ports.py b/test_regress/t/t_paramgraph_iface_array_ports.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_paramgraph_iface_array_ports.py +++ b/test_regress/t/t_paramgraph_iface_array_ports.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_paramgraph_iface_dependency1.py b/test_regress/t/t_paramgraph_iface_dependency1.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_paramgraph_iface_dependency1.py +++ b/test_regress/t/t_paramgraph_iface_dependency1.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_paramgraph_iface_dependency2.py b/test_regress/t/t_paramgraph_iface_dependency2.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_paramgraph_iface_dependency2.py +++ b/test_regress/t/t_paramgraph_iface_dependency2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_paramgraph_iface_dependency3.py b/test_regress/t/t_paramgraph_iface_dependency3.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_paramgraph_iface_dependency3.py +++ b/test_regress/t/t_paramgraph_iface_dependency3.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_paramgraph_iface_pin.py b/test_regress/t/t_paramgraph_iface_pin.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_paramgraph_iface_pin.py +++ b/test_regress/t/t_paramgraph_iface_pin.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_paramgraph_iface_template_mismatch3.py b/test_regress/t/t_paramgraph_iface_template_mismatch3.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_paramgraph_iface_template_mismatch3.py +++ b/test_regress/t/t_paramgraph_iface_template_mismatch3.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_paramgraph_iface_template_nested.py b/test_regress/t/t_paramgraph_iface_template_nested.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_paramgraph_iface_template_nested.py +++ b/test_regress/t/t_paramgraph_iface_template_nested.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_paramgraph_iface_template_nested_stats.py b/test_regress/t/t_paramgraph_iface_template_nested_stats.py index f6e57844b..7fc9b006e 100755 --- a/test_regress/t/t_paramgraph_iface_template_nested_stats.py +++ b/test_regress/t/t_paramgraph_iface_template_nested_stats.py @@ -13,6 +13,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_paramgraph_iface_template_nested.v" diff --git a/test_regress/t/t_paramgraph_member_refdtype.py b/test_regress/t/t_paramgraph_member_refdtype.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_paramgraph_member_refdtype.py +++ b/test_regress/t/t_paramgraph_member_refdtype.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_paramgraph_member_refdtype_iface_chain.py b/test_regress/t/t_paramgraph_member_refdtype_iface_chain.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_paramgraph_member_refdtype_iface_chain.py +++ b/test_regress/t/t_paramgraph_member_refdtype_iface_chain.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_paramgraph_member_refdtype_iface_struct.py b/test_regress/t/t_paramgraph_member_refdtype_iface_struct.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_paramgraph_member_refdtype_iface_struct.py +++ b/test_regress/t/t_paramgraph_member_refdtype_iface_struct.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_paramgraph_member_refdtype_iface_typedef.py b/test_regress/t/t_paramgraph_member_refdtype_iface_typedef.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_paramgraph_member_refdtype_iface_typedef.py +++ b/test_regress/t/t_paramgraph_member_refdtype_iface_typedef.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_paramgraph_member_refdtype_pkg_iface.py b/test_regress/t/t_paramgraph_member_refdtype_pkg_iface.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_paramgraph_member_refdtype_pkg_iface.py +++ b/test_regress/t/t_paramgraph_member_refdtype_pkg_iface.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_paramgraph_nested_iface_typedef.py b/test_regress/t/t_paramgraph_nested_iface_typedef.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_paramgraph_nested_iface_typedef.py +++ b/test_regress/t/t_paramgraph_nested_iface_typedef.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_paramgraph_nested_iface_typedef_stats.py b/test_regress/t/t_paramgraph_nested_iface_typedef_stats.py index e0142486f..12a5ca6d7 100755 --- a/test_regress/t/t_paramgraph_nested_iface_typedef_stats.py +++ b/test_regress/t/t_paramgraph_nested_iface_typedef_stats.py @@ -13,6 +13,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_paramgraph_nested_iface_typedef.v" diff --git a/test_regress/t/t_paramgraph_param_not_const.py b/test_regress/t/t_paramgraph_param_not_const.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_paramgraph_param_not_const.py +++ b/test_regress/t/t_paramgraph_param_not_const.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_past.py b/test_regress/t/t_past.py index 538200ca5..7126bc7c1 100755 --- a/test_regress/t/t_past.py +++ b/test_regress/t/t_past.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--stats']) diff --git a/test_regress/t/t_past_funcs.py b/test_regress/t/t_past_funcs.py index 690ae1cbf..6dc1eb6bb 100755 --- a/test_regress/t/t_past_funcs.py +++ b/test_regress/t/t_past_funcs.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--assert']) diff --git a/test_regress/t/t_past_strobe.py b/test_regress/t/t_past_strobe.py index ed8db10e9..8aeecc749 100755 --- a/test_regress/t/t_past_strobe.py +++ b/test_regress/t/t_past_strobe.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_pgo_profoutofdate_bad.py b/test_regress/t/t_pgo_profoutofdate_bad.py index 6eb37c3ee..cc0b6b3c7 100755 --- a/test_regress/t/t_pgo_profoutofdate_bad.py +++ b/test_regress/t/t_pgo_profoutofdate_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vltmt') +test.fourstate_capable = False test.compile(threads=2, fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_pgo_threads.py b/test_regress/t/t_pgo_threads.py index a5864f805..fddff535a 100755 --- a/test_regress/t/t_pgo_threads.py +++ b/test_regress/t/t_pgo_threads.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vltmt') +test.fourstate_capable = False test.top_filename = "t/t_gen_alw.v" # It doesn't really matter what test test.compile(v_flags2=["--prof-pgo"], threads=2) diff --git a/test_regress/t/t_pgo_threads_hier.py b/test_regress/t/t_pgo_threads_hier.py index f09094b61..9cca9ab99 100755 --- a/test_regress/t/t_pgo_threads_hier.py +++ b/test_regress/t/t_pgo_threads_hier.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vltmt') +test.fourstate_capable = False test.top_filename = "t/t_hier_block_perf.v" cycles = 100 test.sim_time = cycles * 10 + 1000 diff --git a/test_regress/t/t_premit_rw.py b/test_regress/t/t_premit_rw.py index f8083269e..673bbd42b 100755 --- a/test_regress/t/t_premit_rw.py +++ b/test_regress/t/t_premit_rw.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_preproc_defines.py b/test_regress/t/t_preproc_defines.py index 10369de7d..1954767f5 100755 --- a/test_regress/t/t_preproc_defines.py +++ b/test_regress/t/t_preproc_defines.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_preproc.v" stdout_filename = os.path.join(test.obj_dir, test.name + "__test.vpp") diff --git a/test_regress/t/t_preproc_dump_defines.py b/test_regress/t/t_preproc_dump_defines.py index 70b8ac8ed..83b9d33f5 100755 --- a/test_regress/t/t_preproc_dump_defines.py +++ b/test_regress/t/t_preproc_dump_defines.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_preproc.v" stdout_filename = os.path.join(test.obj_dir, test.name + "__test.vpp") diff --git a/test_regress/t/t_preproc_inc_notfound_bad.py b/test_regress/t/t_preproc_inc_notfound_bad.py index c7d9b21a5..692e6eeb1 100755 --- a/test_regress/t/t_preproc_inc_notfound_bad.py +++ b/test_regress/t/t_preproc_inc_notfound_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_priority_case.py b/test_regress/t/t_priority_case.py index c7d9b21a5..692e6eeb1 100755 --- a/test_regress/t/t_priority_case.py +++ b/test_regress/t/t_priority_case.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_probdist.py b/test_regress/t/t_probdist.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_probdist.py +++ b/test_regress/t/t_probdist.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_probdist_bad.py b/test_regress/t/t_probdist_bad.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_probdist_bad.py +++ b/test_regress/t/t_probdist_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_probdist_cmake.py b/test_regress/t/t_probdist_cmake.py index 3238eefa8..9db136714 100755 --- a/test_regress/t/t_probdist_cmake.py +++ b/test_regress/t/t_probdist_cmake.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_probdist.v" test.compile(verilator_make_gmake=False, verilator_make_cmake=True) diff --git a/test_regress/t/t_process.py b/test_regress/t/t_process.py index a4f6212a5..667a7701d 100755 --- a/test_regress/t/t_process.py +++ b/test_regress/t/t_process.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(v_flags2=["--binary"]) diff --git a/test_regress/t/t_process_always.py b/test_regress/t/t_process_always.py index 31b1f0e53..9da272f7d 100755 --- a/test_regress/t/t_process_always.py +++ b/test_regress/t/t_process_always.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_process_compare.py b/test_regress/t/t_process_compare.py index 4ee7f9e14..64d4ecb78 100755 --- a/test_regress/t/t_process_compare.py +++ b/test_regress/t/t_process_compare.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary']) diff --git a/test_regress/t/t_process_compare_flat.py b/test_regress/t/t_process_compare_flat.py index 15559c749..cdd7024e7 100755 --- a/test_regress/t/t_process_compare_flat.py +++ b/test_regress/t/t_process_compare_flat.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_process_compare.v" test.compile(verilator_flags2=['--binary --public-flat-rw']) diff --git a/test_regress/t/t_process_copy_constr.py b/test_regress/t/t_process_copy_constr.py index c1140f359..957153f65 100755 --- a/test_regress/t/t_process_copy_constr.py +++ b/test_regress/t/t_process_copy_constr.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--timing"]) diff --git a/test_regress/t/t_process_finished.py b/test_regress/t/t_process_finished.py index c1140f359..957153f65 100755 --- a/test_regress/t/t_process_finished.py +++ b/test_regress/t/t_process_finished.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--timing"]) diff --git a/test_regress/t/t_process_fork.py b/test_regress/t/t_process_fork.py index 55248e18d..0c18d9c79 100755 --- a/test_regress/t/t_process_fork.py +++ b/test_regress/t/t_process_fork.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_process_fork_block.py b/test_regress/t/t_process_fork_block.py index 4641abd21..76fcaa443 100755 --- a/test_regress/t/t_process_fork_block.py +++ b/test_regress/t/t_process_fork_block.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_process_kill.py b/test_regress/t/t_process_kill.py index c1140f359..957153f65 100755 --- a/test_regress/t/t_process_kill.py +++ b/test_regress/t/t_process_kill.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--timing"]) diff --git a/test_regress/t/t_process_propagation.py b/test_regress/t/t_process_propagation.py index 7ded63f3a..d210ebd50 100755 --- a/test_regress/t/t_process_propagation.py +++ b/test_regress/t/t_process_propagation.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_process_rand.py b/test_regress/t/t_process_rand.py index 36f4378a8..240eff76f 100755 --- a/test_regress/t/t_process_rand.py +++ b/test_regress/t/t_process_rand.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(v_flags2=["--binary"]) diff --git a/test_regress/t/t_process_rand_state.py b/test_regress/t/t_process_rand_state.py index a4c5f8ea1..26ba83bdf 100755 --- a/test_regress/t/t_process_rand_state.py +++ b/test_regress/t/t_process_rand_state.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_process_rand_state_fork.py b/test_regress/t/t_process_rand_state_fork.py index a4c5f8ea1..26ba83bdf 100755 --- a/test_regress/t/t_process_rand_state_fork.py +++ b/test_regress/t/t_process_rand_state_fork.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_process_rand_state_public.py b/test_regress/t/t_process_rand_state_public.py index 59bb211b6..994a3b3fb 100755 --- a/test_regress/t/t_process_rand_state_public.py +++ b/test_regress/t/t_process_rand_state_public.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_process_rand_state.v" if not test.have_solver: diff --git a/test_regress/t/t_process_redecl.py b/test_regress/t/t_process_redecl.py index 67b896515..8a1a7b033 100755 --- a/test_regress/t/t_process_redecl.py +++ b/test_regress/t/t_process_redecl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint() diff --git a/test_regress/t/t_process_self_srand.py b/test_regress/t/t_process_self_srand.py index a3a2e41c6..98a9054cc 100755 --- a/test_regress/t/t_process_self_srand.py +++ b/test_regress/t/t_process_self_srand.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(v_flags2=["--binary"]) diff --git a/test_regress/t/t_process_std.py b/test_regress/t/t_process_std.py index 740e9060f..1f67056b7 100755 --- a/test_regress/t/t_process_std.py +++ b/test_regress/t/t_process_std.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_process.v" test.compile(v_flags2=["--binary", "+define+T_PROCESS+std::process"]) diff --git a/test_regress/t/t_process_task.py b/test_regress/t/t_process_task.py index 36f4378a8..240eff76f 100755 --- a/test_regress/t/t_process_task.py +++ b/test_regress/t/t_process_task.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(v_flags2=["--binary"]) diff --git a/test_regress/t/t_prop_always.py b/test_regress/t/t_prop_always.py index 2351d6963..4de85e908 100755 --- a/test_regress/t/t_prop_always.py +++ b/test_regress/t/t_prop_always.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_prop_always_wide.py b/test_regress/t/t_prop_always_wide.py index 2351d6963..4de85e908 100755 --- a/test_regress/t/t_prop_always_wide.py +++ b/test_regress/t/t_prop_always_wide.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_prop_followed_by.py b/test_regress/t/t_prop_followed_by.py index 8a938befd..a10e2547d 100755 --- a/test_regress/t/t_prop_followed_by.py +++ b/test_regress/t/t_prop_followed_by.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_prop_followed_by_bad.py b/test_regress/t/t_prop_followed_by_bad.py index bc7b9c4bf..9a21e4865 100755 --- a/test_regress/t/t_prop_followed_by_bad.py +++ b/test_regress/t/t_prop_followed_by_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(expect_filename=test.golden_filename, verilator_flags2=['--timing'], diff --git a/test_regress/t/t_prop_s_always_liveness.py b/test_regress/t/t_prop_s_always_liveness.py index e6fa1c51f..37f133a9b 100755 --- a/test_regress/t/t_prop_s_always_liveness.py +++ b/test_regress/t/t_prop_s_always_liveness.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(verilator_flags2=['--assert']) test.execute(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_property.py b/test_regress/t/t_property.py index 3c390daaf..9b307b320 100755 --- a/test_regress/t/t_property.py +++ b/test_regress/t/t_property.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--assert --cc']) diff --git a/test_regress/t/t_property_accept_reject_on.py b/test_regress/t/t_property_accept_reject_on.py index 35e44000c..84d6e744b 100755 --- a/test_regress/t/t_property_accept_reject_on.py +++ b/test_regress/t/t_property_accept_reject_on.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=['--assert', '--timing']) diff --git a/test_regress/t/t_property_case.py b/test_regress/t/t_property_case.py index 35e44000c..84d6e744b 100755 --- a/test_regress/t/t_property_case.py +++ b/test_regress/t/t_property_case.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=['--assert', '--timing']) diff --git a/test_regress/t/t_property_clock_collision_unsup.py b/test_regress/t/t_property_clock_collision_unsup.py index 344a4e20a..a88bd50c8 100755 --- a/test_regress/t/t_property_clock_collision_unsup.py +++ b/test_regress/t/t_property_clock_collision_unsup.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_property_default_clocking_sexpr.py b/test_regress/t/t_property_default_clocking_sexpr.py index 35e44000c..84d6e744b 100755 --- a/test_regress/t/t_property_default_clocking_sexpr.py +++ b/test_regress/t/t_property_default_clocking_sexpr.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=['--assert', '--timing']) diff --git a/test_regress/t/t_property_disable_iff_held.py b/test_regress/t/t_property_disable_iff_held.py index 8c5881f1b..138c75a32 100755 --- a/test_regress/t/t_property_disable_iff_held.py +++ b/test_regress/t/t_property_disable_iff_held.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=['--assert --timing --coverage']) diff --git a/test_regress/t/t_property_disable_iff_midreset.py b/test_regress/t/t_property_disable_iff_midreset.py index 35e44000c..84d6e744b 100755 --- a/test_regress/t/t_property_disable_iff_midreset.py +++ b/test_regress/t/t_property_disable_iff_midreset.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=['--assert', '--timing']) diff --git a/test_regress/t/t_property_disable_iff_unsup.py b/test_regress/t/t_property_disable_iff_unsup.py index fde6ea31b..52548f956 100755 --- a/test_regress/t/t_property_disable_iff_unsup.py +++ b/test_regress/t/t_property_disable_iff_unsup.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(fails=True, verilator_flags2=['--timing'], expect_filename=test.golden_filename) diff --git a/test_regress/t/t_property_fail_1.py b/test_regress/t/t_property_fail_1.py index 261586eee..645a9d810 100755 --- a/test_regress/t/t_property_fail_1.py +++ b/test_regress/t/t_property_fail_1.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_property.v" test.compile(v_flags2=['+define+FAIL_ASSERT_1'], verilator_flags2=['--assert --cc']) diff --git a/test_regress/t/t_property_fail_2_bad.py b/test_regress/t/t_property_fail_2_bad.py index 37c3a7bb5..4abf52ade 100755 --- a/test_regress/t/t_property_fail_2_bad.py +++ b/test_regress/t/t_property_fail_2_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_property.v" test.compile(v_flags2=['+define+FAIL_ASSERT_2'], verilator_flags2=['--assert --cc']) diff --git a/test_regress/t/t_property_if_else.py b/test_regress/t/t_property_if_else.py index 35e44000c..84d6e744b 100755 --- a/test_regress/t/t_property_if_else.py +++ b/test_regress/t/t_property_if_else.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=['--assert', '--timing']) diff --git a/test_regress/t/t_property_imply_delay.py b/test_regress/t/t_property_imply_delay.py index 35e44000c..84d6e744b 100755 --- a/test_regress/t/t_property_imply_delay.py +++ b/test_regress/t/t_property_imply_delay.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=['--assert', '--timing']) diff --git a/test_regress/t/t_property_local_var_delay.py b/test_regress/t/t_property_local_var_delay.py index 35e44000c..84d6e744b 100755 --- a/test_regress/t/t_property_local_var_delay.py +++ b/test_regress/t/t_property_local_var_delay.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=['--assert', '--timing']) diff --git a/test_regress/t/t_property_named.py b/test_regress/t/t_property_named.py index 690ae1cbf..6dc1eb6bb 100755 --- a/test_regress/t/t_property_named.py +++ b/test_regress/t/t_property_named.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--assert']) diff --git a/test_regress/t/t_property_negated.py b/test_regress/t/t_property_negated.py index 690ae1cbf..6dc1eb6bb 100755 --- a/test_regress/t/t_property_negated.py +++ b/test_regress/t/t_property_negated.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--assert']) diff --git a/test_regress/t/t_property_pexpr.py b/test_regress/t/t_property_pexpr.py index 05f4c1c48..48796f962 100755 --- a/test_regress/t/t_property_pexpr.py +++ b/test_regress/t/t_property_pexpr.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=['--timing']) diff --git a/test_regress/t/t_property_s_eventually.py b/test_regress/t/t_property_s_eventually.py index 0185a88b0..6ce79ea80 100755 --- a/test_regress/t/t_property_s_eventually.py +++ b/test_regress/t/t_property_s_eventually.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=['--timing']) diff --git a/test_regress/t/t_property_s_eventually2.py b/test_regress/t/t_property_s_eventually2.py index 1ddad07d5..514560607 100755 --- a/test_regress/t/t_property_s_eventually2.py +++ b/test_regress/t/t_property_s_eventually2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=['--timing']) diff --git a/test_regress/t/t_property_s_eventually_iface.py b/test_regress/t/t_property_s_eventually_iface.py index 1ddad07d5..514560607 100755 --- a/test_regress/t/t_property_s_eventually_iface.py +++ b/test_regress/t/t_property_s_eventually_iface.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=['--timing']) diff --git a/test_regress/t/t_property_s_eventually_iface_param.py b/test_regress/t/t_property_s_eventually_iface_param.py index 1ddad07d5..514560607 100755 --- a/test_regress/t/t_property_s_eventually_iface_param.py +++ b/test_regress/t/t_property_s_eventually_iface_param.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=['--timing']) diff --git a/test_regress/t/t_property_s_eventually_unsup.py b/test_regress/t/t_property_s_eventually_unsup.py index 63f7c17ce..105089005 100755 --- a/test_regress/t/t_property_s_eventually_unsup.py +++ b/test_regress/t/t_property_s_eventually_unsup.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.lint(expect_filename=test.golden_filename, verilator_flags2=['--timing'], fails=True) diff --git a/test_regress/t/t_property_sexpr.py b/test_regress/t/t_property_sexpr.py index a8d77fc30..3f7bcece0 100755 --- a/test_regress/t/t_property_sexpr.py +++ b/test_regress/t/t_property_sexpr.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=['--assert', '--timing']) diff --git a/test_regress/t/t_property_sexpr_cov.py b/test_regress/t/t_property_sexpr_cov.py index c7339ea5e..2ed987679 100755 --- a/test_regress/t/t_property_sexpr_cov.py +++ b/test_regress/t/t_property_sexpr_cov.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=['--assert', '--timing', '--coverage-user']) diff --git a/test_regress/t/t_property_sexpr_disable.py b/test_regress/t/t_property_sexpr_disable.py index 35e44000c..84d6e744b 100755 --- a/test_regress/t/t_property_sexpr_disable.py +++ b/test_regress/t/t_property_sexpr_disable.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=['--assert', '--timing']) diff --git a/test_regress/t/t_property_sexpr_disable_sampled.py b/test_regress/t/t_property_sexpr_disable_sampled.py index 599ecc419..210b7cdb5 100755 --- a/test_regress/t/t_property_sexpr_disable_sampled.py +++ b/test_regress/t/t_property_sexpr_disable_sampled.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(verilator_flags2=['--assert --timing --binary']) diff --git a/test_regress/t/t_property_sexpr_multi.py b/test_regress/t/t_property_sexpr_multi.py index 5de1b48bd..02782aa20 100755 --- a/test_regress/t/t_property_sexpr_multi.py +++ b/test_regress/t/t_property_sexpr_multi.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=['--assert', '--timing', '--dumpi-V3AssertProp 6']) diff --git a/test_regress/t/t_property_sexpr_parse_unsup.py b/test_regress/t/t_property_sexpr_parse_unsup.py index b775bd8bc..7f0ee6dfd 100755 --- a/test_regress/t/t_property_sexpr_parse_unsup.py +++ b/test_regress/t/t_property_sexpr_parse_unsup.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_property_sexpr_unsup.v" diff --git a/test_regress/t/t_property_sexpr_range_delay.py b/test_regress/t/t_property_sexpr_range_delay.py index 35e44000c..84d6e744b 100755 --- a/test_regress/t/t_property_sexpr_range_delay.py +++ b/test_regress/t/t_property_sexpr_range_delay.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=['--assert', '--timing']) diff --git a/test_regress/t/t_property_sexpr_range_delay_bad.py b/test_regress/t/t_property_sexpr_range_delay_bad.py index 504773395..9c510507c 100755 --- a/test_regress/t/t_property_sexpr_range_delay_bad.py +++ b/test_regress/t/t_property_sexpr_range_delay_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert', '--timing', '--error-limit 1000'], diff --git a/test_regress/t/t_property_sexpr_unsup.py b/test_regress/t/t_property_sexpr_unsup.py index f17bf6461..4204fffac 100755 --- a/test_regress/t/t_property_sexpr_unsup.py +++ b/test_regress/t/t_property_sexpr_unsup.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert', '--timing', '--error-limit 1000'], diff --git a/test_regress/t/t_property_until.py b/test_regress/t/t_property_until.py index 35e44000c..84d6e744b 100755 --- a/test_regress/t/t_property_until.py +++ b/test_regress/t/t_property_until.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=['--assert', '--timing']) diff --git a/test_regress/t/t_property_until_implication.py b/test_regress/t/t_property_until_implication.py index d93b04ea1..ca2de0bd5 100755 --- a/test_regress/t/t_property_until_implication.py +++ b/test_regress/t/t_property_until_implication.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--assert']) diff --git a/test_regress/t/t_property_untyped.py b/test_regress/t/t_property_untyped.py index 690ae1cbf..6dc1eb6bb 100755 --- a/test_regress/t/t_property_untyped.py +++ b/test_regress/t/t_property_untyped.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--assert']) diff --git a/test_regress/t/t_protect_ids.py b/test_regress/t/t_protect_ids.py index d92181ed2..edfce77bd 100755 --- a/test_regress/t/t_protect_ids.py +++ b/test_regress/t/t_protect_ids.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False # Use --debug-protect to assist debug diff --git a/test_regress/t/t_protect_ids_debug.py b/test_regress/t/t_protect_ids_debug.py index d7f9ecbca..ac7d64035 100755 --- a/test_regress/t/t_protect_ids_debug.py +++ b/test_regress/t/t_protect_ids_debug.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_protect_ids.v" test.compile(verilator_flags2=[ diff --git a/test_regress/t/t_protect_ids_key.py b/test_regress/t/t_protect_ids_key.py index c472b6c31..1d68c5d56 100755 --- a/test_regress/t/t_protect_ids_key.py +++ b/test_regress/t/t_protect_ids_key.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_protect_ids.v" test.compile(verilator_flags2=["--protect-ids --protect-key SECRET_KEY", "t/t_protect_ids_c.cpp"]) diff --git a/test_regress/t/t_public_clk.py b/test_regress/t/t_public_clk.py index b6662862a..0b2328993 100755 --- a/test_regress/t/t_public_clk.py +++ b/test_regress/t/t_public_clk.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) diff --git a/test_regress/t/t_public_unpacked_port.py b/test_regress/t/t_public_unpacked_port.py index eafe7e6e5..f1d781219 100755 --- a/test_regress/t/t_public_unpacked_port.py +++ b/test_regress/t/t_public_unpacked_port.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_pull_bitsel.py b/test_regress/t/t_pull_bitsel.py index d0918a353..26fecf6c7 100755 --- a/test_regress/t/t_pull_bitsel.py +++ b/test_regress/t/t_pull_bitsel.py @@ -7,6 +7,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_pull_bitsel_conflict_bad.py b/test_regress/t/t_pull_bitsel_conflict_bad.py index 38cf36b43..5dd624dc6 100755 --- a/test_regress/t/t_pull_bitsel_conflict_bad.py +++ b/test_regress/t/t_pull_bitsel_conflict_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_pull_bitsel_whole.py b/test_regress/t/t_pull_bitsel_whole.py index 4e863d585..12d70b8d8 100755 --- a/test_regress/t/t_pull_bitsel_whole.py +++ b/test_regress/t/t_pull_bitsel_whole.py @@ -7,6 +7,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_queue.py b/test_regress/t/t_queue.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_queue.py +++ b/test_regress/t/t_queue.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_queue_array.py b/test_regress/t/t_queue_array.py index 8a938befd..a10e2547d 100755 --- a/test_regress/t/t_queue_array.py +++ b/test_regress/t/t_queue_array.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_queue_assignment.py b/test_regress/t/t_queue_assignment.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_queue_assignment.py +++ b/test_regress/t/t_queue_assignment.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_queue_back.py b/test_regress/t/t_queue_back.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_queue_back.py +++ b/test_regress/t/t_queue_back.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_queue_bounded.py b/test_regress/t/t_queue_bounded.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_queue_bounded.py +++ b/test_regress/t/t_queue_bounded.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_queue_class.py b/test_regress/t/t_queue_class.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_queue_class.py +++ b/test_regress/t/t_queue_class.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_queue_concat_assign.py b/test_regress/t/t_queue_concat_assign.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_queue_concat_assign.py +++ b/test_regress/t/t_queue_concat_assign.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_queue_empty_pin.py b/test_regress/t/t_queue_empty_pin.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_queue_empty_pin.py +++ b/test_regress/t/t_queue_empty_pin.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_queue_inherit_call.py b/test_regress/t/t_queue_inherit_call.py index 8a938befd..a10e2547d 100755 --- a/test_regress/t/t_queue_inherit_call.py +++ b/test_regress/t/t_queue_inherit_call.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_queue_init.py b/test_regress/t/t_queue_init.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_queue_init.py +++ b/test_regress/t/t_queue_init.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_queue_insert_at_end.py b/test_regress/t/t_queue_insert_at_end.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_queue_insert_at_end.py +++ b/test_regress/t/t_queue_insert_at_end.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_queue_method.py b/test_regress/t/t_queue_method.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_queue_method.py +++ b/test_regress/t/t_queue_method.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_queue_persistence_inl.py b/test_regress/t/t_queue_persistence_inl.py index 48b9003cb..99fc413e0 100755 --- a/test_regress/t/t_queue_persistence_inl.py +++ b/test_regress/t/t_queue_persistence_inl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_queue_persistence.v" if not test.have_coroutines: diff --git a/test_regress/t/t_queue_persistence_noinl.py b/test_regress/t/t_queue_persistence_noinl.py index a8859ab7b..9e8640307 100755 --- a/test_regress/t/t_queue_persistence_noinl.py +++ b/test_regress/t/t_queue_persistence_noinl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_queue_persistence.v" if not test.have_coroutines: diff --git a/test_regress/t/t_queue_pushpop.py b/test_regress/t/t_queue_pushpop.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_queue_pushpop.py +++ b/test_regress/t/t_queue_pushpop.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_queue_slice.py b/test_regress/t/t_queue_slice.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_queue_slice.py +++ b/test_regress/t/t_queue_slice.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_queue_slice_assign.py b/test_regress/t/t_queue_slice_assign.py index 8a938befd..a10e2547d 100755 --- a/test_regress/t/t_queue_slice_assign.py +++ b/test_regress/t/t_queue_slice_assign.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_queue_struct.py b/test_regress/t/t_queue_struct.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_queue_struct.py +++ b/test_regress/t/t_queue_struct.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_queue_unknown_sel.py b/test_regress/t/t_queue_unknown_sel.py index 66009b455..52533feae 100755 --- a/test_regress/t/t_queue_unknown_sel.py +++ b/test_regress/t/t_queue_unknown_sel.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_queue_var_slice.py b/test_regress/t/t_queue_var_slice.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_queue_var_slice.py +++ b/test_regress/t/t_queue_var_slice.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_queue_void_ops.py b/test_regress/t/t_queue_void_ops.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_queue_void_ops.py +++ b/test_regress/t/t_queue_void_ops.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_rand_member_mode_deriv.py b/test_regress/t/t_rand_member_mode_deriv.py index 84b274f68..17424b42f 100755 --- a/test_regress/t/t_rand_member_mode_deriv.py +++ b/test_regress/t/t_rand_member_mode_deriv.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_rand_stability_process.py b/test_regress/t/t_rand_stability_process.py index 4301f9380..fdaedb7ff 100755 --- a/test_regress/t/t_rand_stability_process.py +++ b/test_regress/t/t_rand_stability_process.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(v_flags2=["--binary"]) diff --git a/test_regress/t/t_randc_constraint.py b/test_regress/t/t_randc_constraint.py index db1adb3f9..b19f4bf03 100755 --- a/test_regress/t/t_randc_constraint.py +++ b/test_regress/t/t_randc_constraint.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_randc_extends.py b/test_regress/t/t_randc_extends.py index 84b274f68..17424b42f 100755 --- a/test_regress/t/t_randc_extends.py +++ b/test_regress/t/t_randc_extends.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_randc_oversize_bad.py b/test_regress/t/t_randc_oversize_bad.py index 3160d0589..763d0b4d6 100755 --- a/test_regress/t/t_randc_oversize_bad.py +++ b/test_regress/t/t_randc_oversize_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_randc_wide_constraint.py b/test_regress/t/t_randc_wide_constraint.py index db1adb3f9..b19f4bf03 100755 --- a/test_regress/t/t_randc_wide_constraint.py +++ b/test_regress/t/t_randc_wide_constraint.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_randomize_array.py b/test_regress/t/t_randomize_array.py index ab048b5e8..0521af235 100755 --- a/test_regress/t/t_randomize_array.py +++ b/test_regress/t/t_randomize_array.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_randomize_array_elem_with.py b/test_regress/t/t_randomize_array_elem_with.py index db1adb3f9..b19f4bf03 100755 --- a/test_regress/t/t_randomize_array_elem_with.py +++ b/test_regress/t/t_randomize_array_elem_with.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_randomize_arraysel_membersel.py b/test_regress/t/t_randomize_arraysel_membersel.py index 8862c2c31..50fdc5f6d 100755 --- a/test_regress/t/t_randomize_arraysel_membersel.py +++ b/test_regress/t/t_randomize_arraysel_membersel.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_randomize_assoc_size.py b/test_regress/t/t_randomize_assoc_size.py index db1adb3f9..b19f4bf03 100755 --- a/test_regress/t/t_randomize_assoc_size.py +++ b/test_regress/t/t_randomize_assoc_size.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_randomize_class_inherit_size_foreach.py b/test_regress/t/t_randomize_class_inherit_size_foreach.py index db1adb3f9..b19f4bf03 100755 --- a/test_regress/t/t_randomize_class_inherit_size_foreach.py +++ b/test_regress/t/t_randomize_class_inherit_size_foreach.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_randomize_complex.py b/test_regress/t/t_randomize_complex.py index 8862c2c31..50fdc5f6d 100755 --- a/test_regress/t/t_randomize_complex.py +++ b/test_regress/t/t_randomize_complex.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_randomize_complex_arrays.py b/test_regress/t/t_randomize_complex_arrays.py index ab048b5e8..0521af235 100755 --- a/test_regress/t/t_randomize_complex_arrays.py +++ b/test_regress/t/t_randomize_complex_arrays.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_randomize_complex_associative_arrays.py b/test_regress/t/t_randomize_complex_associative_arrays.py index ab048b5e8..0521af235 100755 --- a/test_regress/t/t_randomize_complex_associative_arrays.py +++ b/test_regress/t/t_randomize_complex_associative_arrays.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_randomize_complex_dynamic_arrays.py b/test_regress/t/t_randomize_complex_dynamic_arrays.py index ab048b5e8..0521af235 100755 --- a/test_regress/t/t_randomize_complex_dynamic_arrays.py +++ b/test_regress/t/t_randomize_complex_dynamic_arrays.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_randomize_complex_queue.py b/test_regress/t/t_randomize_complex_queue.py index ab048b5e8..0521af235 100755 --- a/test_regress/t/t_randomize_complex_queue.py +++ b/test_regress/t/t_randomize_complex_queue.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_randomize_complex_typedef.py b/test_regress/t/t_randomize_complex_typedef.py index 8862c2c31..50fdc5f6d 100755 --- a/test_regress/t/t_randomize_complex_typedef.py +++ b/test_regress/t/t_randomize_complex_typedef.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_randomize_from_randomized_class.py b/test_regress/t/t_randomize_from_randomized_class.py index 8862c2c31..50fdc5f6d 100755 --- a/test_regress/t/t_randomize_from_randomized_class.py +++ b/test_regress/t/t_randomize_from_randomized_class.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_randomize_inline_funclocal.py b/test_regress/t/t_randomize_inline_funclocal.py index 84b274f68..17424b42f 100755 --- a/test_regress/t/t_randomize_inline_funclocal.py +++ b/test_regress/t/t_randomize_inline_funclocal.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_randomize_inline_var_ctl.py b/test_regress/t/t_randomize_inline_var_ctl.py index ab048b5e8..0521af235 100755 --- a/test_regress/t/t_randomize_inline_var_ctl.py +++ b/test_regress/t/t_randomize_inline_var_ctl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_randomize_inside_cond.py b/test_regress/t/t_randomize_inside_cond.py index 81df8362d..a611cb34b 100755 --- a/test_regress/t/t_randomize_inside_cond.py +++ b/test_regress/t/t_randomize_inside_cond.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_randomize_local_param.py b/test_regress/t/t_randomize_local_param.py index d6d35e7fd..485ded93c 100755 --- a/test_regress/t/t_randomize_local_param.py +++ b/test_regress/t/t_randomize_local_param.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint() diff --git a/test_regress/t/t_randomize_local_paramed.py b/test_regress/t/t_randomize_local_paramed.py index db1adb3f9..b19f4bf03 100755 --- a/test_regress/t/t_randomize_local_paramed.py +++ b/test_regress/t/t_randomize_local_paramed.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_randomize_member_select.py b/test_regress/t/t_randomize_member_select.py index 8862c2c31..50fdc5f6d 100755 --- a/test_regress/t/t_randomize_member_select.py +++ b/test_regress/t/t_randomize_member_select.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_randomize_method.py b/test_regress/t/t_randomize_method.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_randomize_method.py +++ b/test_regress/t/t_randomize_method.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_randomize_method_constraints.py b/test_regress/t/t_randomize_method_constraints.py index ab048b5e8..0521af235 100755 --- a/test_regress/t/t_randomize_method_constraints.py +++ b/test_regress/t/t_randomize_method_constraints.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_randomize_method_param.py b/test_regress/t/t_randomize_method_param.py index 84b274f68..17424b42f 100755 --- a/test_regress/t/t_randomize_method_param.py +++ b/test_regress/t/t_randomize_method_param.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_randomize_method_types_unsup.py b/test_regress/t/t_randomize_method_types_unsup.py index 4ea94519e..4ab87669f 100755 --- a/test_regress/t/t_randomize_method_types_unsup.py +++ b/test_regress/t/t_randomize_method_types_unsup.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_randomize_method_with.py b/test_regress/t/t_randomize_method_with.py index d71278a65..b5540478d 100755 --- a/test_regress/t/t_randomize_method_with.py +++ b/test_regress/t/t_randomize_method_with.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_randomize_method_with_bad.py b/test_regress/t/t_randomize_method_with_bad.py index c7d9b21a5..692e6eeb1 100755 --- a/test_regress/t/t_randomize_method_with_bad.py +++ b/test_regress/t/t_randomize_method_with_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_randomize_method_with_scoping.py b/test_regress/t/t_randomize_method_with_scoping.py index ab048b5e8..0521af235 100755 --- a/test_regress/t/t_randomize_method_with_scoping.py +++ b/test_regress/t/t_randomize_method_with_scoping.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_randomize_module_var.py b/test_regress/t/t_randomize_module_var.py index db1adb3f9..b19f4bf03 100755 --- a/test_regress/t/t_randomize_module_var.py +++ b/test_regress/t/t_randomize_module_var.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_randomize_null.py b/test_regress/t/t_randomize_null.py index db1adb3f9..b19f4bf03 100755 --- a/test_regress/t/t_randomize_null.py +++ b/test_regress/t/t_randomize_null.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_randomize_null_unsup.py b/test_regress/t/t_randomize_null_unsup.py index 02d2f5abe..20f3db872 100755 --- a/test_regress/t/t_randomize_null_unsup.py +++ b/test_regress/t/t_randomize_null_unsup.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_randomize_prepost_nested.py b/test_regress/t/t_randomize_prepost_nested.py index db1adb3f9..b19f4bf03 100755 --- a/test_regress/t/t_randomize_prepost_nested.py +++ b/test_regress/t/t_randomize_prepost_nested.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_randomize_prepost_with_baseref.py b/test_regress/t/t_randomize_prepost_with_baseref.py index db1adb3f9..b19f4bf03 100755 --- a/test_regress/t/t_randomize_prepost_with_baseref.py +++ b/test_regress/t/t_randomize_prepost_with_baseref.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_randomize_queue_constraints.py b/test_regress/t/t_randomize_queue_constraints.py index ab048b5e8..0521af235 100755 --- a/test_regress/t/t_randomize_queue_constraints.py +++ b/test_regress/t/t_randomize_queue_constraints.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_randomize_queue_size.py b/test_regress/t/t_randomize_queue_size.py index ab048b5e8..0521af235 100755 --- a/test_regress/t/t_randomize_queue_size.py +++ b/test_regress/t/t_randomize_queue_size.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_randomize_queue_size_element.py b/test_regress/t/t_randomize_queue_size_element.py index ab048b5e8..0521af235 100755 --- a/test_regress/t/t_randomize_queue_size_element.py +++ b/test_regress/t/t_randomize_queue_size_element.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_randomize_queue_wide.py b/test_regress/t/t_randomize_queue_wide.py index 8862c2c31..50fdc5f6d 100755 --- a/test_regress/t/t_randomize_queue_wide.py +++ b/test_regress/t/t_randomize_queue_wide.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_randomize_rand_mode.py b/test_regress/t/t_randomize_rand_mode.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_randomize_rand_mode.py +++ b/test_regress/t/t_randomize_rand_mode.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_randomize_rand_mode_constr.py b/test_regress/t/t_randomize_rand_mode_constr.py index ab048b5e8..0521af235 100755 --- a/test_regress/t/t_randomize_rand_mode_constr.py +++ b/test_regress/t/t_randomize_rand_mode_constr.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_randomize_rand_mode_funcarg.py b/test_regress/t/t_randomize_rand_mode_funcarg.py index 8a938befd..a10e2547d 100755 --- a/test_regress/t/t_randomize_rand_mode_funcarg.py +++ b/test_regress/t/t_randomize_rand_mode_funcarg.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_randomize_rand_mode_static.py b/test_regress/t/t_randomize_rand_mode_static.py index db1adb3f9..b19f4bf03 100755 --- a/test_regress/t/t_randomize_rand_mode_static.py +++ b/test_regress/t/t_randomize_rand_mode_static.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_randomize_randmode_subobj.py b/test_regress/t/t_randomize_randmode_subobj.py index db1adb3f9..b19f4bf03 100755 --- a/test_regress/t/t_randomize_randmode_subobj.py +++ b/test_regress/t/t_randomize_randmode_subobj.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_randomize_shift_distribution.py b/test_regress/t/t_randomize_shift_distribution.py index 56d461811..19d22c091 100755 --- a/test_regress/t/t_randomize_shift_distribution.py +++ b/test_regress/t/t_randomize_shift_distribution.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_randomize_solve_before_foreach.py b/test_regress/t/t_randomize_solve_before_foreach.py index db1adb3f9..b19f4bf03 100755 --- a/test_regress/t/t_randomize_solve_before_foreach.py +++ b/test_regress/t/t_randomize_solve_before_foreach.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_randomize_srandom.py b/test_regress/t/t_randomize_srandom.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_randomize_srandom.py +++ b/test_regress/t/t_randomize_srandom.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_randomize_std_inside_queue.py b/test_regress/t/t_randomize_std_inside_queue.py index db1adb3f9..b19f4bf03 100755 --- a/test_regress/t/t_randomize_std_inside_queue.py +++ b/test_regress/t/t_randomize_std_inside_queue.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_randomize_std_param_extends.py b/test_regress/t/t_randomize_std_param_extends.py index db1adb3f9..b19f4bf03 100755 --- a/test_regress/t/t_randomize_std_param_extends.py +++ b/test_regress/t/t_randomize_std_param_extends.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_randomize_std_static.py b/test_regress/t/t_randomize_std_static.py index db1adb3f9..b19f4bf03 100755 --- a/test_regress/t/t_randomize_std_static.py +++ b/test_regress/t/t_randomize_std_static.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_randomize_subobj_enum.py b/test_regress/t/t_randomize_subobj_enum.py index db1adb3f9..b19f4bf03 100755 --- a/test_regress/t/t_randomize_subobj_enum.py +++ b/test_regress/t/t_randomize_subobj_enum.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_randomize_this.py b/test_regress/t/t_randomize_this.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_randomize_this.py +++ b/test_regress/t/t_randomize_this.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_randomize_this_inline.py b/test_regress/t/t_randomize_this_inline.py index db1adb3f9..b19f4bf03 100755 --- a/test_regress/t/t_randomize_this_inline.py +++ b/test_regress/t/t_randomize_this_inline.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_randomize_this_with.py b/test_regress/t/t_randomize_this_with.py index 5e3c074cf..30119fd06 100755 --- a/test_regress/t/t_randomize_this_with.py +++ b/test_regress/t/t_randomize_this_with.py @@ -13,6 +13,7 @@ if not test.have_solver: test.skip("No constraint solver installed") test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_randomize_union.py b/test_regress/t/t_randomize_union.py index ab048b5e8..0521af235 100755 --- a/test_regress/t/t_randomize_union.py +++ b/test_regress/t/t_randomize_union.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_randomize_union_bad.py b/test_regress/t/t_randomize_union_bad.py index c7d9b21a5..692e6eeb1 100755 --- a/test_regress/t/t_randomize_union_bad.py +++ b/test_regress/t/t_randomize_union_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_randomize_unique_elem.py b/test_regress/t/t_randomize_unique_elem.py index db1adb3f9..b19f4bf03 100755 --- a/test_regress/t/t_randomize_unique_elem.py +++ b/test_regress/t/t_randomize_unique_elem.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_randomize_unpacked_bad.py b/test_regress/t/t_randomize_unpacked_bad.py index 1d5ccb8f4..c1876edec 100755 --- a/test_regress/t/t_randomize_unpacked_bad.py +++ b/test_regress/t/t_randomize_unpacked_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_randomize_with_constraint.py b/test_regress/t/t_randomize_with_constraint.py index 8862c2c31..50fdc5f6d 100755 --- a/test_regress/t/t_randomize_with_constraint.py +++ b/test_regress/t/t_randomize_with_constraint.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_randomize_within_func.py b/test_regress/t/t_randomize_within_func.py index 8862c2c31..50fdc5f6d 100755 --- a/test_regress/t/t_randomize_within_func.py +++ b/test_regress/t/t_randomize_within_func.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_randsequence_func_bad.py b/test_regress/t/t_randsequence_func_bad.py index 05284f5ad..96d789d2a 100755 --- a/test_regress/t/t_randsequence_func_bad.py +++ b/test_regress/t/t_randsequence_func_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(verilator_flags=["--lint-only"], fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_randstate_func.py b/test_regress/t/t_randstate_func.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_randstate_func.py +++ b/test_regress/t/t_randstate_func.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_randstate_obj.py b/test_regress/t/t_randstate_obj.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_randstate_obj.py +++ b/test_regress/t/t_randstate_obj.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_recursive_module_bug.py b/test_regress/t/t_recursive_module_bug.py index 66009b455..52533feae 100755 --- a/test_regress/t/t_recursive_module_bug.py +++ b/test_regress/t/t_recursive_module_bug.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_ref_arg_array_range_dir.py b/test_regress/t/t_ref_arg_array_range_dir.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_ref_arg_array_range_dir.py +++ b/test_regress/t/t_ref_arg_array_range_dir.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_ref_arg_array_range_dir_noinline.py b/test_regress/t/t_ref_arg_array_range_dir_noinline.py index 5f7f075f6..7d67c7354 100755 --- a/test_regress/t/t_ref_arg_array_range_dir_noinline.py +++ b/test_regress/t/t_ref_arg_array_range_dir_noinline.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_ref_arg_array_range_dir.v" test.compile(verilator_flags2=["--binary"], v_flags2=['+define+T_NOINLINE']) diff --git a/test_regress/t/t_reloop_cam.py b/test_regress/t/t_reloop_cam.py index 3333f0da8..f33ee44e4 100755 --- a/test_regress/t/t_reloop_cam.py +++ b/test_regress/t/t_reloop_cam.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=[ "-unroll-count 1024", "--expand-limit 1024", test.wno_unopthreads_for_few_cores, "--stats" diff --git a/test_regress/t/t_reloop_cam_off.py b/test_regress/t/t_reloop_cam_off.py index 935411bee..6e9113c75 100755 --- a/test_regress/t/t_reloop_cam_off.py +++ b/test_regress/t/t_reloop_cam_off.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator_st') +test.fourstate_capable = False test.top_filename = "t/t_reloop_cam.v" test.compile(verilator_flags2=["--stats", "-fno-reloop"]) diff --git a/test_regress/t/t_reloop_local.py b/test_regress/t/t_reloop_local.py index 690ae1cbf..6dc1eb6bb 100755 --- a/test_regress/t/t_reloop_local.py +++ b/test_regress/t/t_reloop_local.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--assert']) diff --git a/test_regress/t/t_risefall_delay.py b/test_regress/t/t_risefall_delay.py index 390bba1b8..51c729a6e 100755 --- a/test_regress/t/t_risefall_delay.py +++ b/test_regress/t/t_risefall_delay.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=["--timing"]) diff --git a/test_regress/t/t_runflag_seed.py b/test_regress/t/t_runflag_seed.py index 8b90c3d9f..452ab0113 100755 --- a/test_regress/t/t_runflag_seed.py +++ b/test_regress/t/t_runflag_seed.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_runflag_seed_zero.py b/test_regress/t/t_runflag_seed_zero.py index d74209a05..f693fb23d 100755 --- a/test_regress/t/t_runflag_seed_zero.py +++ b/test_regress/t/t_runflag_seed_zero.py @@ -14,6 +14,7 @@ import vltest_bootstrap # so independent invocations are not deterministic. test.scenarios('vlt') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary']) diff --git a/test_regress/t/t_runflag_uninit_bad.py b/test_regress/t/t_runflag_uninit_bad.py index 7604d8b42..694e8958a 100755 --- a/test_regress/t/t_runflag_uninit_bad.py +++ b/test_regress/t/t_runflag_uninit_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(v_flags2=["--savable --exe", test.pli_filename], make_main=False) diff --git a/test_regress/t/t_sampled_expr.py b/test_regress/t/t_sampled_expr.py index 690ae1cbf..6dc1eb6bb 100755 --- a/test_regress/t/t_sampled_expr.py +++ b/test_regress/t/t_sampled_expr.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--assert']) diff --git a/test_regress/t/t_sampled_sensitivity.py b/test_regress/t/t_sampled_sensitivity.py index 3160d0589..763d0b4d6 100755 --- a/test_regress/t/t_sampled_sensitivity.py +++ b/test_regress/t/t_sampled_sensitivity.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_sarif.py b/test_regress/t/t_sarif.py index cda774dd6..d1dec1e1d 100755 --- a/test_regress/t/t_sarif.py +++ b/test_regress/t/t_sarif.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(verilator_flags2=['-Wno-fatal --diagnostics-sarif --no-skip-identical'], expect_filename=test.golden_filename) diff --git a/test_regress/t/t_savable.py b/test_regress/t/t_savable.py index 333b3e2a0..13d56ae34 100755 --- a/test_regress/t/t_savable.py +++ b/test_regress/t/t_savable.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(v_flags2=["--savable"], save_time=500) diff --git a/test_regress/t/t_savable_format1_bad.py b/test_regress/t/t_savable_format1_bad.py index 9da748014..e6b978f9c 100755 --- a/test_regress/t/t_savable_format1_bad.py +++ b/test_regress/t/t_savable_format1_bad.py @@ -11,6 +11,7 @@ import vltest_bootstrap import time test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_savable.v" test.compile(v_flags2=["--savable"], save_time=500) diff --git a/test_regress/t/t_savable_format2_bad.py b/test_regress/t/t_savable_format2_bad.py index e3db8e74c..e3b3cc9ed 100755 --- a/test_regress/t/t_savable_format2_bad.py +++ b/test_regress/t/t_savable_format2_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_savable.v" test.compile(v_flags2=["--savable"], save_time=500) diff --git a/test_regress/t/t_savable_format3_bad.py b/test_regress/t/t_savable_format3_bad.py index 7fd834576..f96495930 100755 --- a/test_regress/t/t_savable_format3_bad.py +++ b/test_regress/t/t_savable_format3_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_savable.v" test.compile(v_flags2=["--savable"], save_time=500) diff --git a/test_regress/t/t_savable_open_bad.py b/test_regress/t/t_savable_open_bad.py index ccf4d977a..bfd150285 100755 --- a/test_regress/t/t_savable_open_bad.py +++ b/test_regress/t/t_savable_open_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_savable.v" test.compile(v_flags2=["--savable"], save_time=500) diff --git a/test_regress/t/t_sc_names.py b/test_regress/t/t_sc_names.py index fd4e8b8cf..477e2e470 100755 --- a/test_regress/t/t_sc_names.py +++ b/test_regress/t/t_sc_names.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_sc: test.skip("No SystemC installed") diff --git a/test_regress/t/t_sc_vl_assign_sbw.py b/test_regress/t/t_sc_vl_assign_sbw.py index f9993ae4a..16209a1e4 100755 --- a/test_regress/t/t_sc_vl_assign_sbw.py +++ b/test_regress/t/t_sc_vl_assign_sbw.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(make_top_shell=False, make_main=False, diff --git a/test_regress/t/t_sched_ico_change_detect_input_assigned.py b/test_regress/t/t_sched_ico_change_detect_input_assigned.py index c837fa2b9..814ab5b5b 100755 --- a/test_regress/t/t_sched_ico_change_detect_input_assigned.py +++ b/test_regress/t/t_sched_ico_change_detect_input_assigned.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_sched_ico_change_detect_input_assigned.v" diff --git a/test_regress/t/t_sched_ico_change_detect_input_assigned_off.py b/test_regress/t/t_sched_ico_change_detect_input_assigned_off.py index b98a8e1b6..9c2409316 100755 --- a/test_regress/t/t_sched_ico_change_detect_input_assigned_off.py +++ b/test_regress/t/t_sched_ico_change_detect_input_assigned_off.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_sched_ico_change_detect_input_assigned.v" diff --git a/test_regress/t/t_sched_ico_change_detect_input_assigned_vpi.py b/test_regress/t/t_sched_ico_change_detect_input_assigned_vpi.py index cd22fef43..7b1557efa 100755 --- a/test_regress/t/t_sched_ico_change_detect_input_assigned_vpi.py +++ b/test_regress/t/t_sched_ico_change_detect_input_assigned_vpi.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_sched_ico_change_detect_input_assigned.v" diff --git a/test_regress/t/t_sched_ico_change_detect_input_assigned_vpi_on.py b/test_regress/t/t_sched_ico_change_detect_input_assigned_vpi_on.py index afd44e7ce..fd9d0b19b 100755 --- a/test_regress/t/t_sched_ico_change_detect_input_assigned_vpi_on.py +++ b/test_regress/t/t_sched_ico_change_detect_input_assigned_vpi_on.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_sched_ico_change_detect_input_assigned.v" diff --git a/test_regress/t/t_scheduling_5.py b/test_regress/t/t_scheduling_5.py index 529492841..fc5fbca97 100755 --- a/test_regress/t/t_scheduling_5.py +++ b/test_regress/t/t_scheduling_5.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["-Wno-MULTIDRIVEN"]) diff --git a/test_regress/t/t_scheduling_initial_event.py b/test_regress/t/t_scheduling_initial_event.py index 31b1f0e53..9da272f7d 100755 --- a/test_regress/t/t_scheduling_initial_event.py +++ b/test_regress/t/t_scheduling_initial_event.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_scheduling_many_clocks.py b/test_regress/t/t_scheduling_many_clocks.py index 838900266..3e463d3e4 100755 --- a/test_regress/t/t_scheduling_many_clocks.py +++ b/test_regress/t/t_scheduling_many_clocks.py @@ -12,6 +12,7 @@ import vltest_bootstrap test.sim_time = 100000 test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--stats"]) diff --git a/test_regress/t/t_scheduling_virt_iface_array.py b/test_regress/t/t_scheduling_virt_iface_array.py index c63aaf108..b6c40e43e 100755 --- a/test_regress/t/t_scheduling_virt_iface_array.py +++ b/test_regress/t/t_scheduling_virt_iface_array.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios("vlt") +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_scheduling_virt_iface_class.py b/test_regress/t/t_scheduling_virt_iface_class.py index c63aaf108..b6c40e43e 100755 --- a/test_regress/t/t_scheduling_virt_iface_class.py +++ b/test_regress/t/t_scheduling_virt_iface_class.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios("vlt") +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_scheduling_virt_iface_converge_simple.py b/test_regress/t/t_scheduling_virt_iface_converge_simple.py index c63aaf108..b6c40e43e 100755 --- a/test_regress/t/t_scheduling_virt_iface_converge_simple.py +++ b/test_regress/t/t_scheduling_virt_iface_converge_simple.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios("vlt") +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_scheduling_virt_iface_dual_vif.py b/test_regress/t/t_scheduling_virt_iface_dual_vif.py index c63aaf108..b6c40e43e 100755 --- a/test_regress/t/t_scheduling_virt_iface_dual_vif.py +++ b/test_regress/t/t_scheduling_virt_iface_dual_vif.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios("vlt") +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_scheduling_virt_iface_nonvirt_write.py b/test_regress/t/t_scheduling_virt_iface_nonvirt_write.py index c63aaf108..b6c40e43e 100755 --- a/test_regress/t/t_scheduling_virt_iface_nonvirt_write.py +++ b/test_regress/t/t_scheduling_virt_iface_nonvirt_write.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios("vlt") +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_scope_map.py b/test_regress/t/t_scope_map.py index 6bff8cd57..16fad4635 100755 --- a/test_regress/t/t_scope_map.py +++ b/test_regress/t/t_scope_map.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.compile(make_top_shell=False, make_main=False, diff --git a/test_regress/t/t_select_2d.py b/test_regress/t/t_select_2d.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_select_2d.py +++ b/test_regress/t/t_select_2d.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_select_ascending.py b/test_regress/t/t_select_ascending.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_select_ascending.py +++ b/test_regress/t/t_select_ascending.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_select_bad_range3.py b/test_regress/t/t_select_bad_range3.py index 1952b53a1..873d22c46 100755 --- a/test_regress/t/t_select_bad_range3.py +++ b/test_regress/t/t_select_bad_range3.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_select_bad_range4.py b/test_regress/t/t_select_bad_range4.py index 1952b53a1..873d22c46 100755 --- a/test_regress/t/t_select_bad_range4.py +++ b/test_regress/t/t_select_bad_range4.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_select_bad_range5.py b/test_regress/t/t_select_bad_range5.py index 1952b53a1..873d22c46 100755 --- a/test_regress/t/t_select_bad_range5.py +++ b/test_regress/t/t_select_bad_range5.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_select_bad_tri.py b/test_regress/t/t_select_bad_tri.py index 1952b53a1..873d22c46 100755 --- a/test_regress/t/t_select_bad_tri.py +++ b/test_regress/t/t_select_bad_tri.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_select_bound1.py b/test_regress/t/t_select_bound1.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_select_bound1.py +++ b/test_regress/t/t_select_bound1.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_select_bound2.py b/test_regress/t/t_select_bound2.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_select_bound2.py +++ b/test_regress/t/t_select_bound2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_select_bound4.py b/test_regress/t/t_select_bound4.py index 00e3aae74..9ee41117b 100755 --- a/test_regress/t/t_select_bound4.py +++ b/test_regress/t/t_select_bound4.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--stats"]) diff --git a/test_regress/t/t_select_index.py b/test_regress/t/t_select_index.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_select_index.py +++ b/test_regress/t/t_select_index.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_select_lhs_oob.py b/test_regress/t/t_select_lhs_oob.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_select_lhs_oob.py +++ b/test_regress/t/t_select_lhs_oob.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_select_lhs_oob2.py b/test_regress/t/t_select_lhs_oob2.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_select_lhs_oob2.py +++ b/test_regress/t/t_select_lhs_oob2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_select_little.py b/test_regress/t/t_select_little.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_select_little.py +++ b/test_regress/t/t_select_little.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_select_little_pack.py b/test_regress/t/t_select_little_pack.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_select_little_pack.py +++ b/test_regress/t/t_select_little_pack.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_select_loop.py b/test_regress/t/t_select_loop.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_select_loop.py +++ b/test_regress/t/t_select_loop.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_select_mul_extend.py b/test_regress/t/t_select_mul_extend.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_select_mul_extend.py +++ b/test_regress/t/t_select_mul_extend.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_select_negative.py b/test_regress/t/t_select_negative.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_select_negative.py +++ b/test_regress/t/t_select_negative.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_select_plus.py b/test_regress/t/t_select_plus.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_select_plus.py +++ b/test_regress/t/t_select_plus.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_select_plus_mul_pow2.py b/test_regress/t/t_select_plus_mul_pow2.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_select_plus_mul_pow2.py +++ b/test_regress/t/t_select_plus_mul_pow2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_select_plusloop.py b/test_regress/t/t_select_plusloop.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_select_plusloop.py +++ b/test_regress/t/t_select_plusloop.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_select_set.py b/test_regress/t/t_select_set.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_select_set.py +++ b/test_regress/t/t_select_set.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_selrange_iface_type_param.py b/test_regress/t/t_selrange_iface_type_param.py index 7ded63f3a..d210ebd50 100755 --- a/test_regress/t/t_selrange_iface_type_param.py +++ b/test_regress/t/t_selrange_iface_type_param.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_semaphore.py b/test_regress/t/t_semaphore.py index 72b5f8d81..029115332 100755 --- a/test_regress/t/t_semaphore.py +++ b/test_regress/t/t_semaphore.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary -Wall"]) diff --git a/test_regress/t/t_semaphore_always.py b/test_regress/t/t_semaphore_always.py index c1140f359..957153f65 100755 --- a/test_regress/t/t_semaphore_always.py +++ b/test_regress/t/t_semaphore_always.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--timing"]) diff --git a/test_regress/t/t_semaphore_concurrent.py b/test_regress/t/t_semaphore_concurrent.py index 55248e18d..0c18d9c79 100755 --- a/test_regress/t/t_semaphore_concurrent.py +++ b/test_regress/t/t_semaphore_concurrent.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_semaphore_fair.py b/test_regress/t/t_semaphore_fair.py index 9aad707de..e027c2469 100755 --- a/test_regress/t/t_semaphore_fair.py +++ b/test_regress/t/t_semaphore_fair.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_semaphore_fifo_block.py b/test_regress/t/t_semaphore_fifo_block.py index 9aad707de..e027c2469 100755 --- a/test_regress/t/t_semaphore_fifo_block.py +++ b/test_regress/t/t_semaphore_fifo_block.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_semaphore_std.py b/test_regress/t/t_semaphore_std.py index f4ed98c34..469d68ccc 100755 --- a/test_regress/t/t_semaphore_std.py +++ b/test_regress/t/t_semaphore_std.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_semaphore.v" test.compile(verilator_flags2=["--binary -Wall -DSEMAPHORE_T=std::semaphore"]) diff --git a/test_regress/t/t_sequence_bool_ops.py b/test_regress/t/t_sequence_bool_ops.py index 35e44000c..84d6e744b 100755 --- a/test_regress/t/t_sequence_bool_ops.py +++ b/test_regress/t/t_sequence_bool_ops.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=['--assert', '--timing']) diff --git a/test_regress/t/t_sequence_first_match.py b/test_regress/t/t_sequence_first_match.py index d93b04ea1..ca2de0bd5 100755 --- a/test_regress/t/t_sequence_first_match.py +++ b/test_regress/t/t_sequence_first_match.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--assert']) diff --git a/test_regress/t/t_sequence_intersect.py b/test_regress/t/t_sequence_intersect.py index ddef50cab..786693053 100755 --- a/test_regress/t/t_sequence_intersect.py +++ b/test_regress/t/t_sequence_intersect.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--assert --timing']) diff --git a/test_regress/t/t_sequence_intersect_varlen.py b/test_regress/t/t_sequence_intersect_varlen.py index ddef50cab..786693053 100755 --- a/test_regress/t/t_sequence_intersect_varlen.py +++ b/test_regress/t/t_sequence_intersect_varlen.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--assert --timing']) diff --git a/test_regress/t/t_sequence_local_var.py b/test_regress/t/t_sequence_local_var.py index 35e44000c..84d6e744b 100755 --- a/test_regress/t/t_sequence_local_var.py +++ b/test_regress/t/t_sequence_local_var.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=['--assert', '--timing']) diff --git a/test_regress/t/t_sequence_ref.py b/test_regress/t/t_sequence_ref.py index 35e44000c..84d6e744b 100755 --- a/test_regress/t/t_sequence_ref.py +++ b/test_regress/t/t_sequence_ref.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=['--assert', '--timing']) diff --git a/test_regress/t/t_sequence_sexpr_throughout.py b/test_regress/t/t_sequence_sexpr_throughout.py index 35e44000c..84d6e744b 100755 --- a/test_regress/t/t_sequence_sexpr_throughout.py +++ b/test_regress/t/t_sequence_sexpr_throughout.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=['--assert', '--timing']) diff --git a/test_regress/t/t_sequence_unused.py b/test_regress/t/t_sequence_unused.py index 84b274f68..17424b42f 100755 --- a/test_regress/t/t_sequence_unused.py +++ b/test_regress/t/t_sequence_unused.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_sequence_within.py b/test_regress/t/t_sequence_within.py index ab1f7d03f..6f5fd3c81 100755 --- a/test_regress/t/t_sequence_within.py +++ b/test_regress/t/t_sequence_within.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--assert --timing --coverage']) diff --git a/test_regress/t/t_simulate_array.py b/test_regress/t/t_simulate_array.py index d19b59b98..c71775abf 100755 --- a/test_regress/t/t_simulate_array.py +++ b/test_regress/t/t_simulate_array.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_slice_cond.py b/test_regress/t/t_slice_cond.py index 66009b455..52533feae 100755 --- a/test_regress/t/t_slice_cond.py +++ b/test_regress/t/t_slice_cond.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_slice_init.py b/test_regress/t/t_slice_init.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_slice_init.py +++ b/test_regress/t/t_slice_init.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_slice_struct_array_modport.py b/test_regress/t/t_slice_struct_array_modport.py index 67b896515..8a1a7b033 100755 --- a/test_regress/t/t_slice_struct_array_modport.py +++ b/test_regress/t/t_slice_struct_array_modport.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint() diff --git a/test_regress/t/t_specparam.py b/test_regress/t/t_specparam.py index 148bcb2f4..8a57812ec 100755 --- a/test_regress/t/t_specparam.py +++ b/test_regress/t/t_specparam.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary']) diff --git a/test_regress/t/t_split_var_0.py b/test_regress/t/t_split_var_0.py index ce5aea5dd..6d61c7521 100755 --- a/test_regress/t/t_split_var_0.py +++ b/test_regress/t/t_split_var_0.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False # CI environment offers 2 VCPUs, 2 thread setting causes the following warning. # %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. diff --git a/test_regress/t/t_split_var_1_bad.py b/test_regress/t/t_split_var_1_bad.py index 95aae012d..31a084833 100755 --- a/test_regress/t/t_split_var_1_bad.py +++ b/test_regress/t/t_split_var_1_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(fails=True, verilator_flags2=['--stats', "-fno-dfg"], diff --git a/test_regress/t/t_split_var_2_trace.py b/test_regress/t/t_split_var_2_trace.py index 17b121bfd..7421f7042 100755 --- a/test_regress/t/t_split_var_2_trace.py +++ b/test_regress/t/t_split_var_2_trace.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_split_var_0.v" # CI environment offers 2 VCPUs, 2 thread setting causes the following warning. diff --git a/test_regress/t/t_split_var_4.py b/test_regress/t/t_split_var_4.py index 9a537e5d1..ad438e2a2 100755 --- a/test_regress/t/t_split_var_4.py +++ b/test_regress/t/t_split_var_4.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--stats', '-DENABLE_SPLIT_VAR=1', "-fno-dfg"]) diff --git a/test_regress/t/t_split_var_5.py b/test_regress/t/t_split_var_5.py index 02b633344..a14e6f93c 100755 --- a/test_regress/t/t_split_var_5.py +++ b/test_regress/t/t_split_var_5.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_split_var_4.v" test.compile(verilator_flags2=['--stats', "-fno-dfg"]) diff --git a/test_regress/t/t_split_var_auto.py b/test_regress/t/t_split_var_auto.py index 4e9240bde..6ef9d0e55 100755 --- a/test_regress/t/t_split_var_auto.py +++ b/test_regress/t/t_split_var_auto.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--stats"]) diff --git a/test_regress/t/t_split_var_issue.py b/test_regress/t/t_split_var_issue.py index ff0625848..01efcf9b3 100755 --- a/test_regress/t/t_split_var_issue.py +++ b/test_regress/t/t_split_var_issue.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios("simulator_st") +test.fourstate_capable = False test.compile(verilator_flags2=["--assert", "-fno-localize"]) diff --git a/test_regress/t/t_split_var_types.py b/test_regress/t/t_split_var_types.py index e60c66adb..0cece9bbe 100755 --- a/test_regress/t/t_split_var_types.py +++ b/test_regress/t/t_split_var_types.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--trace-vcd']) diff --git a/test_regress/t/t_split_var_xref.py b/test_regress/t/t_split_var_xref.py index 276645160..8824db0e5 100755 --- a/test_regress/t/t_split_var_xref.py +++ b/test_regress/t/t_split_var_xref.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=["--timing"]) diff --git a/test_regress/t/t_static_elab.py b/test_regress/t/t_static_elab.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_static_elab.py +++ b/test_regress/t/t_static_elab.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_static_function_in_class.py b/test_regress/t/t_static_function_in_class.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_static_function_in_class.py +++ b/test_regress/t/t_static_function_in_class.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_static_init_pkg_order.py b/test_regress/t/t_static_init_pkg_order.py index 8a938befd..a10e2547d 100755 --- a/test_regress/t/t_static_init_pkg_order.py +++ b/test_regress/t/t_static_init_pkg_order.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_static_task_args.py b/test_regress/t/t_static_task_args.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_static_task_args.py +++ b/test_regress/t/t_static_task_args.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_std_identifier.py b/test_regress/t/t_std_identifier.py index 5e48bb865..5f6ffbbf0 100755 --- a/test_regress/t/t_std_identifier.py +++ b/test_regress/t/t_std_identifier.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(verilator_flags2=["-DTEST_DECLARE_STD"]) diff --git a/test_regress/t/t_std_process_self.py b/test_regress/t/t_std_process_self.py index baeb93ae0..94323523a 100755 --- a/test_regress/t/t_std_process_self.py +++ b/test_regress/t/t_std_process_self.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--timing"]) diff --git a/test_regress/t/t_std_process_self_std.py b/test_regress/t/t_std_process_self_std.py index b99044e2f..592f20fb3 100755 --- a/test_regress/t/t_std_process_self_std.py +++ b/test_regress/t/t_std_process_self_std.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_std_process_self.v" test.compile(verilator_flags2=["--binary --DUSE_STD_PREFIX"]) diff --git a/test_regress/t/t_std_randomize.py b/test_regress/t/t_std_randomize.py index 8862c2c31..50fdc5f6d 100755 --- a/test_regress/t/t_std_randomize.py +++ b/test_regress/t/t_std_randomize.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_std_randomize_assoc.py b/test_regress/t/t_std_randomize_assoc.py index db1adb3f9..b19f4bf03 100755 --- a/test_regress/t/t_std_randomize_assoc.py +++ b/test_regress/t/t_std_randomize_assoc.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_std_randomize_mod.py b/test_regress/t/t_std_randomize_mod.py index 26440f70f..001f9d311 100755 --- a/test_regress/t/t_std_randomize_mod.py +++ b/test_regress/t/t_std_randomize_mod.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.lint() diff --git a/test_regress/t/t_std_randomize_no_args.py b/test_regress/t/t_std_randomize_no_args.py index 26440f70f..001f9d311 100755 --- a/test_regress/t/t_std_randomize_no_args.py +++ b/test_regress/t/t_std_randomize_no_args.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.lint() diff --git a/test_regress/t/t_std_randomize_queue.py b/test_regress/t/t_std_randomize_queue.py index db1adb3f9..b19f4bf03 100755 --- a/test_regress/t/t_std_randomize_queue.py +++ b/test_regress/t/t_std_randomize_queue.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_std_randomize_static_member.py b/test_regress/t/t_std_randomize_static_member.py index db1adb3f9..b19f4bf03 100755 --- a/test_regress/t/t_std_randomize_static_member.py +++ b/test_regress/t/t_std_randomize_static_member.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_std_randomize_unsup_unq_arr.py b/test_regress/t/t_std_randomize_unsup_unq_arr.py index 18ef27714..d1c8fa5b1 100755 --- a/test_regress/t/t_std_randomize_unsup_unq_arr.py +++ b/test_regress/t/t_std_randomize_unsup_unq_arr.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_std_randomize_with.py b/test_regress/t/t_std_randomize_with.py index ab048b5e8..0521af235 100755 --- a/test_regress/t/t_std_randomize_with.py +++ b/test_regress/t/t_std_randomize_with.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False if not test.have_solver: test.skip("No constraint solver installed") diff --git a/test_regress/t/t_stream.py b/test_regress/t/t_stream.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_stream.py +++ b/test_regress/t/t_stream.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_stream2.py b/test_regress/t/t_stream2.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_stream2.py +++ b/test_regress/t/t_stream2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_stream3.py b/test_regress/t/t_stream3.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_stream3.py +++ b/test_regress/t/t_stream3.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_stream4.py b/test_regress/t/t_stream4.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_stream4.py +++ b/test_regress/t/t_stream4.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_stream5.py b/test_regress/t/t_stream5.py index 7ded63f3a..d210ebd50 100755 --- a/test_regress/t/t_stream5.py +++ b/test_regress/t/t_stream5.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_stream_bitqueue.py b/test_regress/t/t_stream_bitqueue.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_stream_bitqueue.py +++ b/test_regress/t/t_stream_bitqueue.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_stream_crc_example.py b/test_regress/t/t_stream_crc_example.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_stream_crc_example.py +++ b/test_regress/t/t_stream_crc_example.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_stream_dynamic.py b/test_regress/t/t_stream_dynamic.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_stream_dynamic.py +++ b/test_regress/t/t_stream_dynamic.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_stream_integer_type.py b/test_regress/t/t_stream_integer_type.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_stream_integer_type.py +++ b/test_regress/t/t_stream_integer_type.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_stream_queue.py b/test_regress/t/t_stream_queue.py index f7785cc52..91d92a05f 100755 --- a/test_regress/t/t_stream_queue.py +++ b/test_regress/t/t_stream_queue.py @@ -11,6 +11,7 @@ import vltest_bootstrap # Issue #7780 unstable with --vltmt test.scenarios('simulator_st') +test.fourstate_capable = False test.compile(verilator_flags2=["--timing"]) diff --git a/test_regress/t/t_stream_queue_interface.py b/test_regress/t/t_stream_queue_interface.py index da1d399fc..085480642 100755 --- a/test_regress/t/t_stream_queue_interface.py +++ b/test_regress/t/t_stream_queue_interface.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_stream_queue_interface.sv" diff --git a/test_regress/t/t_stream_struct.py b/test_regress/t/t_stream_struct.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_stream_struct.py +++ b/test_regress/t/t_stream_struct.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_stream_trace.py b/test_regress/t/t_stream_trace.py index 3fbef9037..d7e596360 100755 --- a/test_regress/t/t_stream_trace.py +++ b/test_regress/t/t_stream_trace.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--cc --trace-vcd -fno-life']) diff --git a/test_regress/t/t_stream_type.py b/test_regress/t/t_stream_type.py index 387abbd9b..8b976cee9 100755 --- a/test_regress/t/t_stream_type.py +++ b/test_regress/t/t_stream_type.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False # Doesn't currently compile due to issue #6574 test.compile(verilator_make_gmake=False) diff --git a/test_regress/t/t_stream_unpack.py b/test_regress/t/t_stream_unpack.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_stream_unpack.py +++ b/test_regress/t/t_stream_unpack.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_stream_unpack_lhs.py b/test_regress/t/t_stream_unpack_lhs.py index 529757f59..d10d74bd3 100755 --- a/test_regress/t/t_stream_unpack_lhs.py +++ b/test_regress/t/t_stream_unpack_lhs.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile() test.execute() diff --git a/test_regress/t/t_stream_unpack_narrower.py b/test_regress/t/t_stream_unpack_narrower.py index 382ad0d44..3b5ec369f 100755 --- a/test_regress/t/t_stream_unpack_narrower.py +++ b/test_regress/t/t_stream_unpack_narrower.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_stream_unpack_wider.py b/test_regress/t/t_stream_unpack_wider.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_stream_unpack_wider.py +++ b/test_regress/t/t_stream_unpack_wider.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_stream_unpacked_struct.py b/test_regress/t/t_stream_unpacked_struct.py index 8a938befd..a10e2547d 100755 --- a/test_regress/t/t_stream_unpacked_struct.py +++ b/test_regress/t/t_stream_unpacked_struct.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_strength_2_uneq_assign.py b/test_regress/t/t_strength_2_uneq_assign.py index c7d9b21a5..692e6eeb1 100755 --- a/test_regress/t/t_strength_2_uneq_assign.py +++ b/test_regress/t/t_strength_2_uneq_assign.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_strength_assignments_constants.py b/test_regress/t/t_strength_assignments_constants.py index 73ee01534..bdc7553cb 100755 --- a/test_regress/t/t_strength_assignments_constants.py +++ b/test_regress/t/t_strength_assignments_constants.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--language 1364-2005"]) diff --git a/test_regress/t/t_strength_buf_not.py b/test_regress/t/t_strength_buf_not.py index 46d1fe4c0..bd6ade23d 100755 --- a/test_regress/t/t_strength_buf_not.py +++ b/test_regress/t/t_strength_buf_not.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary']) diff --git a/test_regress/t/t_strength_equal_strength.py b/test_regress/t/t_strength_equal_strength.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_strength_equal_strength.py +++ b/test_regress/t/t_strength_equal_strength.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_strength_strongest_constant.py b/test_regress/t/t_strength_strongest_constant.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_strength_strongest_constant.py +++ b/test_regress/t/t_strength_strongest_constant.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_strength_strongest_non_tristate.py b/test_regress/t/t_strength_strongest_non_tristate.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_strength_strongest_non_tristate.py +++ b/test_regress/t/t_strength_strongest_non_tristate.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_string.py b/test_regress/t/t_string.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_string.py +++ b/test_regress/t/t_string.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_string_dyn_num.py b/test_regress/t/t_string_dyn_num.py index ed8db10e9..8aeecc749 100755 --- a/test_regress/t/t_string_dyn_num.py +++ b/test_regress/t/t_string_dyn_num.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_string_repl.py b/test_regress/t/t_string_repl.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_string_repl.py +++ b/test_regress/t/t_string_repl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_struct_anon.py b/test_regress/t/t_struct_anon.py index 67b896515..8a1a7b033 100755 --- a/test_regress/t/t_struct_anon.py +++ b/test_regress/t/t_struct_anon.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint() diff --git a/test_regress/t/t_struct_array.py b/test_regress/t/t_struct_array.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_struct_array.py +++ b/test_regress/t/t_struct_array.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_struct_array_assignment.py b/test_regress/t/t_struct_array_assignment.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_struct_array_assignment.py +++ b/test_regress/t/t_struct_array_assignment.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_struct_cons_cast.py b/test_regress/t/t_struct_cons_cast.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_struct_cons_cast.py +++ b/test_regress/t/t_struct_cons_cast.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_struct_genfor.py b/test_regress/t/t_struct_genfor.py index 67b896515..8a1a7b033 100755 --- a/test_regress/t/t_struct_genfor.py +++ b/test_regress/t/t_struct_genfor.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint() diff --git a/test_regress/t/t_struct_init.py b/test_regress/t/t_struct_init.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_struct_init.py +++ b/test_regress/t/t_struct_init.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_struct_init_trace.py b/test_regress/t/t_struct_init_trace.py index 520fefb6b..73fd8cd64 100755 --- a/test_regress/t/t_struct_init_trace.py +++ b/test_regress/t/t_struct_init_trace.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_struct_init.v" test.compile(verilator_flags2=['--cc --trace-vcd']) diff --git a/test_regress/t/t_struct_initial_assign.py b/test_regress/t/t_struct_initial_assign.py index c1140f359..957153f65 100755 --- a/test_regress/t/t_struct_initial_assign.py +++ b/test_regress/t/t_struct_initial_assign.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--timing"]) diff --git a/test_regress/t/t_struct_initial_assign_public.py b/test_regress/t/t_struct_initial_assign_public.py index a17a67680..574512b65 100755 --- a/test_regress/t/t_struct_initial_assign_public.py +++ b/test_regress/t/t_struct_initial_assign_public.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_struct_initial_assign.v" test.compile(verilator_flags2=["--timing", "--public-flat-rw"]) diff --git a/test_regress/t/t_struct_negate.py b/test_regress/t/t_struct_negate.py index 84b274f68..17424b42f 100755 --- a/test_regress/t/t_struct_negate.py +++ b/test_regress/t/t_struct_negate.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_struct_nest.py b/test_regress/t/t_struct_nest.py index 67b896515..8a1a7b033 100755 --- a/test_regress/t/t_struct_nest.py +++ b/test_regress/t/t_struct_nest.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint() diff --git a/test_regress/t/t_struct_packed_sysfunct.py b/test_regress/t/t_struct_packed_sysfunct.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_struct_packed_sysfunct.py +++ b/test_regress/t/t_struct_packed_sysfunct.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_struct_packed_value_list.py b/test_regress/t/t_struct_packed_value_list.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_struct_packed_value_list.py +++ b/test_regress/t/t_struct_packed_value_list.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_struct_packed_write_read.py b/test_regress/t/t_struct_packed_write_read.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_struct_packed_write_read.py +++ b/test_regress/t/t_struct_packed_write_read.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_struct_param.py b/test_regress/t/t_struct_param.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_struct_param.py +++ b/test_regress/t/t_struct_param.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_struct_param_overflow.py b/test_regress/t/t_struct_param_overflow.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_struct_param_overflow.py +++ b/test_regress/t/t_struct_param_overflow.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_struct_pat.py b/test_regress/t/t_struct_pat.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_struct_pat.py +++ b/test_regress/t/t_struct_pat.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_struct_pat_width.py b/test_regress/t/t_struct_pat_width.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_struct_pat_width.py +++ b/test_regress/t/t_struct_pat_width.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_struct_port.py b/test_regress/t/t_struct_port.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_struct_port.py +++ b/test_regress/t/t_struct_port.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_struct_portsel.py b/test_regress/t/t_struct_portsel.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_struct_portsel.py +++ b/test_regress/t/t_struct_portsel.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_struct_unaligned.py b/test_regress/t/t_struct_unaligned.py index 643a457c5..d5247ec3a 100755 --- a/test_regress/t/t_struct_unaligned.py +++ b/test_regress/t/t_struct_unaligned.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False # Note: need to run at a higher optimization level to reproduce the issue test.benchmark = True diff --git a/test_regress/t/t_struct_unpacked.py b/test_regress/t/t_struct_unpacked.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_struct_unpacked.py +++ b/test_regress/t/t_struct_unpacked.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_struct_unpacked_array.py b/test_regress/t/t_struct_unpacked_array.py index 713e425ae..8ad6c6b4e 100755 --- a/test_regress/t/t_struct_unpacked_array.py +++ b/test_regress/t/t_struct_unpacked_array.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--x-assign unique --x-initial unique -Wno-WIDTH -O0"]) diff --git a/test_regress/t/t_struct_unpacked_clean.py b/test_regress/t/t_struct_unpacked_clean.py index 713e425ae..8ad6c6b4e 100755 --- a/test_regress/t/t_struct_unpacked_clean.py +++ b/test_regress/t/t_struct_unpacked_clean.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--x-assign unique --x-initial unique -Wno-WIDTH -O0"]) diff --git a/test_regress/t/t_struct_unpacked_init_param.py b/test_regress/t/t_struct_unpacked_init_param.py index 8a938befd..a10e2547d 100755 --- a/test_regress/t/t_struct_unpacked_init_param.py +++ b/test_regress/t/t_struct_unpacked_init_param.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_struct_unpacked_param.py b/test_regress/t/t_struct_unpacked_param.py index 903201f15..03b00189e 100755 --- a/test_regress/t/t_struct_unpacked_param.py +++ b/test_regress/t/t_struct_unpacked_param.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios("simulator") +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_struct_with_param_class.py b/test_regress/t/t_struct_with_param_class.py index 46d1fe4c0..bd6ade23d 100755 --- a/test_regress/t/t_struct_with_param_class.py +++ b/test_regress/t/t_struct_with_param_class.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary']) diff --git a/test_regress/t/t_structu_dataType_assignment.py b/test_regress/t/t_structu_dataType_assignment.py index 4a044903a..5cffa6ba3 100755 --- a/test_regress/t/t_structu_dataType_assignment.py +++ b/test_regress/t/t_structu_dataType_assignment.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator_st') +test.fourstate_capable = False test.compile(verilator_flags2=['-Wno-DEPRECATED', '--structs-packed']) diff --git a/test_regress/t/t_sv_bus_mux_demux.py b/test_regress/t/t_sv_bus_mux_demux.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_sv_bus_mux_demux.py +++ b/test_regress/t/t_sv_bus_mux_demux.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_sv_conditional.py b/test_regress/t/t_sv_conditional.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_sv_conditional.py +++ b/test_regress/t/t_sv_conditional.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_sv_cpu.py b/test_regress/t/t_sv_cpu.py index dcc41dab2..dfdcd5ca7 100755 --- a/test_regress/t/t_sv_cpu.py +++ b/test_regress/t/t_sv_cpu.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False # 22-Mar-2012: Modifications for this test contributed by Jeremy Bennett, # Embecosm. diff --git a/test_regress/t/t_sys_delta_monitor.py b/test_regress/t/t_sys_delta_monitor.py index b210cd8cd..56ea0adc0 100755 --- a/test_regress/t/t_sys_delta_monitor.py +++ b/test_regress/t/t_sys_delta_monitor.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary --timescale 1ns/1ns"]) diff --git a/test_regress/t/t_sys_file_autoflush.py b/test_regress/t/t_sys_file_autoflush.py index 1a46a2805..f8f44c23a 100755 --- a/test_regress/t/t_sys_file_autoflush.py +++ b/test_regress/t/t_sys_file_autoflush.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_sys_file_basic.v" test.compile(v_flags2=['+incdir+../include', '+define+AUTOFLUSH'], diff --git a/test_regress/t/t_sys_file_basic.py b/test_regress/t/t_sys_file_basic.py index 6a0d42341..b7e6352b8 100755 --- a/test_regress/t/t_sys_file_basic.py +++ b/test_regress/t/t_sys_file_basic.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.unlink_ok(test.obj_dir + "/t_sys_file_basic_test.log") diff --git a/test_regress/t/t_sys_file_basic_cover_expr.py b/test_regress/t/t_sys_file_basic_cover_expr.py index 44303846d..6ad3e56cf 100755 --- a/test_regress/t/t_sys_file_basic_cover_expr.py +++ b/test_regress/t/t_sys_file_basic_cover_expr.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios("simulator") +test.fourstate_capable = False test.top_filename = "t/t_sys_file_basic.v" test.unlink_ok(test.obj_dir + "/t_sys_file_basic_test.log") diff --git a/test_regress/t/t_sys_file_basic_mcd.py b/test_regress/t/t_sys_file_basic_mcd.py index b148c8295..bd78f625d 100755 --- a/test_regress/t/t_sys_file_basic_mcd.py +++ b/test_regress/t/t_sys_file_basic_mcd.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.unlink_ok(test.obj_dir + "/t_sys_file_basic_mcd.log") diff --git a/test_regress/t/t_sys_file_basic_uz.py b/test_regress/t/t_sys_file_basic_uz.py index 90409c781..a8e43ed10 100755 --- a/test_regress/t/t_sys_file_basic_uz.py +++ b/test_regress/t/t_sys_file_basic_uz.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.unlink_ok(test.obj_dir + "/t_sys_file_basic_uz_test.log") diff --git a/test_regress/t/t_sys_file_eof.py b/test_regress/t/t_sys_file_eof.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_sys_file_eof.py +++ b/test_regress/t/t_sys_file_eof.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_sys_file_scan.py b/test_regress/t/t_sys_file_scan.py index 3345c7917..618d78909 100755 --- a/test_regress/t/t_sys_file_scan.py +++ b/test_regress/t/t_sys_file_scan.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.unlink_ok(test.obj_dir + "/t_sys_file_scan_test.log") diff --git a/test_regress/t/t_sys_file_scan2.py b/test_regress/t/t_sys_file_scan2.py index 84b274f68..17424b42f 100755 --- a/test_regress/t/t_sys_file_scan2.py +++ b/test_regress/t/t_sys_file_scan2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_sys_file_scan_delay.py b/test_regress/t/t_sys_file_scan_delay.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_sys_file_scan_delay.py +++ b/test_regress/t/t_sys_file_scan_delay.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_sys_file_zero.py b/test_regress/t/t_sys_file_zero.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_sys_file_zero.py +++ b/test_regress/t/t_sys_file_zero.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_sys_fread.py b/test_regress/t/t_sys_fread.py index 92829167d..d04879850 100755 --- a/test_regress/t/t_sys_fread.py +++ b/test_regress/t/t_sys_fread.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False def gen(filename): diff --git a/test_regress/t/t_sys_get_init_seed.py b/test_regress/t/t_sys_get_init_seed.py index c27a581fe..faba51b8f 100755 --- a/test_regress/t/t_sys_get_init_seed.py +++ b/test_regress/t/t_sys_get_init_seed.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(fails=False) diff --git a/test_regress/t/t_sys_plusargs.py b/test_regress/t/t_sys_plusargs.py index fa6e7da58..c394fc376 100755 --- a/test_regress/t/t_sys_plusargs.py +++ b/test_regress/t/t_sys_plusargs.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(v_flags2=['-v', 't/t_flag_libinc.v']) diff --git a/test_regress/t/t_sys_plusargs_bad.py b/test_regress/t/t_sys_plusargs_bad.py index 1a93d5310..5ce5416d4 100755 --- a/test_regress/t/t_sys_plusargs_bad.py +++ b/test_regress/t/t_sys_plusargs_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator_st') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_sys_random_seed.py b/test_regress/t/t_sys_random_seed.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_sys_random_seed.py +++ b/test_regress/t/t_sys_random_seed.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_sys_readmem.py b/test_regress/t/t_sys_readmem.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_sys_readmem.py +++ b/test_regress/t/t_sys_readmem.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_sys_readmem_4state.py b/test_regress/t/t_sys_readmem_4state.py index aeeeb7891..d8ea22472 100755 --- a/test_regress/t/t_sys_readmem_4state.py +++ b/test_regress/t/t_sys_readmem_4state.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--x-initial unique"]) diff --git a/test_regress/t/t_sys_readmem_assoc.py b/test_regress/t/t_sys_readmem_assoc.py index 486ef733d..f2a71a4dc 100755 --- a/test_regress/t/t_sys_readmem_assoc.py +++ b/test_regress/t/t_sys_readmem_assoc.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_sys_readmem_bad_addr.py b/test_regress/t/t_sys_readmem_bad_addr.py index 4f406c821..69a19cb1e 100755 --- a/test_regress/t/t_sys_readmem_bad_addr.py +++ b/test_regress/t/t_sys_readmem_bad_addr.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator_st') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_sys_readmem_bad_addr2.py b/test_regress/t/t_sys_readmem_bad_addr2.py index 4f406c821..69a19cb1e 100755 --- a/test_regress/t/t_sys_readmem_bad_addr2.py +++ b/test_regress/t/t_sys_readmem_bad_addr2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator_st') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_sys_readmem_bad_digit.py b/test_regress/t/t_sys_readmem_bad_digit.py index 4f406c821..69a19cb1e 100755 --- a/test_regress/t/t_sys_readmem_bad_digit.py +++ b/test_regress/t/t_sys_readmem_bad_digit.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator_st') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_sys_readmem_bad_end.py b/test_regress/t/t_sys_readmem_bad_end.py index 82792bbb0..f06a398e1 100755 --- a/test_regress/t/t_sys_readmem_bad_end.py +++ b/test_regress/t/t_sys_readmem_bad_end.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator_st') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_sys_readmem_bad_notfound.py b/test_regress/t/t_sys_readmem_bad_notfound.py index 82792bbb0..f06a398e1 100755 --- a/test_regress/t/t_sys_readmem_bad_notfound.py +++ b/test_regress/t/t_sys_readmem_bad_notfound.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator_st') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_sys_readmem_eof.py b/test_regress/t/t_sys_readmem_eof.py index 5e176cb53..aa100d385 100755 --- a/test_regress/t/t_sys_readmem_eof.py +++ b/test_regress/t/t_sys_readmem_eof.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False def gen(filename): diff --git a/test_regress/t/t_sys_sformat.py b/test_regress/t/t_sys_sformat.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_sys_sformat.py +++ b/test_regress/t/t_sys_sformat.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_sys_sformat_noopt.py b/test_regress/t/t_sys_sformat_noopt.py index a6f7a1b3a..17a8f7db1 100755 --- a/test_regress/t/t_sys_sformat_noopt.py +++ b/test_regress/t/t_sys_sformat_noopt.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_sys_sformat.v" test.compile( diff --git a/test_regress/t/t_sys_sscanf.py b/test_regress/t/t_sys_sscanf.py index 84b274f68..17424b42f 100755 --- a/test_regress/t/t_sys_sscanf.py +++ b/test_regress/t/t_sys_sscanf.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_sys_system.py b/test_regress/t/t_sys_system.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_sys_system.py +++ b/test_regress/t/t_sys_system.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_sys_writemem.py b/test_regress/t/t_sys_writemem.py index 2696e7e84..f749d6cda 100755 --- a/test_regress/t/t_sys_writemem.py +++ b/test_regress/t/t_sys_writemem.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_sys_readmem.v" # Use random reset to ensure we're fully initializing arrays before diff --git a/test_regress/t/t_sys_writemem_b.py b/test_regress/t/t_sys_writemem_b.py index 3cac96257..626f84f0c 100755 --- a/test_regress/t/t_sys_writemem_b.py +++ b/test_regress/t/t_sys_writemem_b.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_sys_readmem.v" # Use random reset to ensure we're fully initializing arrays before diff --git a/test_regress/t/t_time_sc_10_ns.py b/test_regress/t/t_time_sc_10_ns.py index 9b4251995..1d39a6a4d 100755 --- a/test_regress/t/t_time_sc_10_ns.py +++ b/test_regress/t/t_time_sc_10_ns.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_time_sc.v" test.sc_time_resolution = 'SC_NS' diff --git a/test_regress/t/t_time_sc_bad.py b/test_regress/t/t_time_sc_bad.py index 6dc19a040..a543bcf22 100755 --- a/test_regress/t/t_time_sc_bad.py +++ b/test_regress/t/t_time_sc_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_time_sc.v" test.sc_time_resolution = 'SC_NS' diff --git a/test_regress/t/t_time_sc_bad_mt.py b/test_regress/t/t_time_sc_bad_mt.py index 237e904a2..d6025562e 100755 --- a/test_regress/t/t_time_sc_bad_mt.py +++ b/test_regress/t/t_time_sc_bad_mt.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vltmt') +test.fourstate_capable = False test.top_filename = "t/t_time_sc.v" test.sc_time_resolution = 'SC_NS' diff --git a/test_regress/t/t_time_sc_fs.py b/test_regress/t/t_time_sc_fs.py index 41f6279a7..b79d33bc1 100755 --- a/test_regress/t/t_time_sc_fs.py +++ b/test_regress/t/t_time_sc_fs.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_time_sc.v" test.sc_time_resolution = 'SC_FS' diff --git a/test_regress/t/t_time_sc_ms.py b/test_regress/t/t_time_sc_ms.py index 6ae867db2..46dd3539e 100755 --- a/test_regress/t/t_time_sc_ms.py +++ b/test_regress/t/t_time_sc_ms.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_time_sc.v" test.sc_time_resolution = 'SC_MS' diff --git a/test_regress/t/t_time_sc_ns.py b/test_regress/t/t_time_sc_ns.py index 6c17c824e..51d3b6404 100755 --- a/test_regress/t/t_time_sc_ns.py +++ b/test_regress/t/t_time_sc_ns.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_time_sc.v" test.sc_time_resolution = 'SC_NS' diff --git a/test_regress/t/t_time_sc_sec.py b/test_regress/t/t_time_sc_sec.py index 44fc52bc9..1a851546c 100755 --- a/test_regress/t/t_time_sc_sec.py +++ b/test_regress/t/t_time_sc_sec.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_time_sc.v" test.sc_time_resolution = 'SC_SEC' diff --git a/test_regress/t/t_time_sc_us.py b/test_regress/t/t_time_sc_us.py index b940d5547..5003854e8 100755 --- a/test_regress/t/t_time_sc_us.py +++ b/test_regress/t/t_time_sc_us.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_time_sc.v" test.sc_time_resolution = 'SC_US' diff --git a/test_regress/t/t_time_sscanf.py b/test_regress/t/t_time_sscanf.py index 84b274f68..17424b42f 100755 --- a/test_regress/t/t_time_sscanf.py +++ b/test_regress/t/t_time_sscanf.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_time_timeunit.py b/test_regress/t/t_time_timeunit.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_time_timeunit.py +++ b/test_regress/t/t_time_timeunit.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_timing_class.py b/test_regress/t/t_timing_class.py index a36e184d4..c705fc66e 100755 --- a/test_regress/t/t_timing_class.py +++ b/test_regress/t/t_timing_class.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_timing_clkgen1.py b/test_regress/t/t_timing_clkgen1.py index c847f1b57..c68a004ac 100755 --- a/test_regress/t/t_timing_clkgen1.py +++ b/test_regress/t/t_timing_clkgen1.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary -Wno-MINTYPMAXDLY"]) diff --git a/test_regress/t/t_timing_clkgen2.py b/test_regress/t/t_timing_clkgen2.py index 2f72a9f1c..2bfce92bd 100755 --- a/test_regress/t/t_timing_clkgen2.py +++ b/test_regress/t/t_timing_clkgen2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary -Wwarn-BLKSEQ"]) diff --git a/test_regress/t/t_timing_clkgen_sc.py b/test_regress/t/t_timing_clkgen_sc.py index c917da81b..46d77aa8a 100755 --- a/test_regress/t/t_timing_clkgen_sc.py +++ b/test_regress/t/t_timing_clkgen_sc.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_timing_clkgen2.v" if re.search(r'clang', test.cxx_version): diff --git a/test_regress/t/t_timing_cmake.py b/test_regress/t/t_timing_cmake.py index 956b19829..6d463bee5 100755 --- a/test_regress/t/t_timing_cmake.py +++ b/test_regress/t/t_timing_cmake.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_timing_events.v" if not test.have_coroutines: diff --git a/test_regress/t/t_timing_debug1.py b/test_regress/t/t_timing_debug1.py index a8648a97a..de44a35b4 100755 --- a/test_regress/t/t_timing_debug1.py +++ b/test_regress/t/t_timing_debug1.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.top_filename = "t/t_timing_sched.v" test.compile( diff --git a/test_regress/t/t_timing_debug2.py b/test_regress/t/t_timing_debug2.py index e5bb01e3c..62edb4a2c 100755 --- a/test_regress/t/t_timing_debug2.py +++ b/test_regress/t/t_timing_debug2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.top_filename = "t/t_timing_class.v" # Disable CFunc inlining so debug traces show all function entries diff --git a/test_regress/t/t_timing_dlyassign.py b/test_regress/t/t_timing_dlyassign.py index 7ded63f3a..d210ebd50 100755 --- a/test_regress/t/t_timing_dlyassign.py +++ b/test_regress/t/t_timing_dlyassign.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_timing_eval_act.py b/test_regress/t/t_timing_eval_act.py index 46dae2791..a357d46f2 100755 --- a/test_regress/t/t_timing_eval_act.py +++ b/test_regress/t/t_timing_eval_act.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary", "--runtime-debug", "-fno-inline-cfuncs"]) diff --git a/test_regress/t/t_timing_events.py b/test_regress/t/t_timing_events.py index a36e184d4..c705fc66e 100755 --- a/test_regress/t/t_timing_events.py +++ b/test_regress/t/t_timing_events.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_timing_func_fork_bad.py b/test_regress/t/t_timing_func_fork_bad.py index 1caa0a210..a88a72bc5 100755 --- a/test_regress/t/t_timing_func_fork_bad.py +++ b/test_regress/t/t_timing_func_fork_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.compile(fails=True, verilator_flags2=["--binary -Wno-UNOPTFLAT"], diff --git a/test_regress/t/t_timing_intra_assign.py b/test_regress/t/t_timing_intra_assign.py index 55248e18d..0c18d9c79 100755 --- a/test_regress/t/t_timing_intra_assign.py +++ b/test_regress/t/t_timing_intra_assign.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_timing_intra_assign_func.py b/test_regress/t/t_timing_intra_assign_func.py index 31b1f0e53..9da272f7d 100755 --- a/test_regress/t/t_timing_intra_assign_func.py +++ b/test_regress/t/t_timing_intra_assign_func.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_timing_intra_assign_nolocalize.py b/test_regress/t/t_timing_intra_assign_nolocalize.py index c3804992b..699ef43f0 100755 --- a/test_regress/t/t_timing_intra_assign_nolocalize.py +++ b/test_regress/t/t_timing_intra_assign_nolocalize.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_timing_intra_assign.v" test.golden_filename = "t/t_timing_intra_assign.out" diff --git a/test_regress/t/t_timing_nba_1.py b/test_regress/t/t_timing_nba_1.py index 7ded63f3a..d210ebd50 100755 --- a/test_regress/t/t_timing_nba_1.py +++ b/test_regress/t/t_timing_nba_1.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_timing_nba_2.py b/test_regress/t/t_timing_nba_2.py index 7ded63f3a..d210ebd50 100755 --- a/test_regress/t/t_timing_nba_2.py +++ b/test_regress/t/t_timing_nba_2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_timing_nested_assignment_on_lhs.py b/test_regress/t/t_timing_nested_assignment_on_lhs.py index d385ecc55..10c6f493a 100755 --- a/test_regress/t/t_timing_nested_assignment_on_lhs.py +++ b/test_regress/t/t_timing_nested_assignment_on_lhs.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_net_delay.v" test.compile(timing_loop=True, verilator_flags2=["--timing"]) diff --git a/test_regress/t/t_timing_off.py b/test_regress/t/t_timing_off.py index 7ded63f3a..d210ebd50 100755 --- a/test_regress/t/t_timing_off.py +++ b/test_regress/t/t_timing_off.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_timing_osc.py b/test_regress/t/t_timing_osc.py index c5fbbf167..71283c5b8 100755 --- a/test_regress/t/t_timing_osc.py +++ b/test_regress/t/t_timing_osc.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary --trace-vcd"], make_main=False) diff --git a/test_regress/t/t_timing_wait1.py b/test_regress/t/t_timing_wait1.py index 96df3e890..e4204e340 100755 --- a/test_regress/t/t_timing_wait1.py +++ b/test_regress/t/t_timing_wait1.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary -Wno-WAITCONST"]) diff --git a/test_regress/t/t_timing_wait3.py b/test_regress/t/t_timing_wait3.py index 7ded63f3a..d210ebd50 100755 --- a/test_regress/t/t_timing_wait3.py +++ b/test_regress/t/t_timing_wait3.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_timing_wait_long.py b/test_regress/t/t_timing_wait_long.py index bf27a0db2..844f478d2 100755 --- a/test_regress/t/t_timing_wait_long.py +++ b/test_regress/t/t_timing_wait_long.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary", "--no-sched-zero-delay"]) diff --git a/test_regress/t/t_timing_write_expr.py b/test_regress/t/t_timing_write_expr.py index bb3cf3bf1..ad429a977 100755 --- a/test_regress/t/t_timing_write_expr.py +++ b/test_regress/t/t_timing_write_expr.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"], make_main=False) diff --git a/test_regress/t/t_trace_abort_cc_fst.py b/test_regress/t/t_trace_abort_cc_fst.py index a6ad9fbef..8b5511848 100755 --- a/test_regress/t/t_trace_abort_cc_fst.py +++ b/test_regress/t/t_trace_abort_cc_fst.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_abort_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_abort_common.run(test) diff --git a/test_regress/t/t_trace_abort_sc_fst.py b/test_regress/t/t_trace_abort_sc_fst.py index a6ad9fbef..8b5511848 100755 --- a/test_regress/t/t_trace_abort_sc_fst.py +++ b/test_regress/t/t_trace_abort_sc_fst.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_abort_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_abort_common.run(test) diff --git a/test_regress/t/t_trace_array_cc_fst.py b/test_regress/t/t_trace_array_cc_fst.py index 499943a69..86cb8b97a 100755 --- a/test_regress/t/t_trace_array_cc_fst.py +++ b/test_regress/t/t_trace_array_cc_fst.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_array_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_array_common.run(test) diff --git a/test_regress/t/t_trace_array_cc_fst_portable.py b/test_regress/t/t_trace_array_cc_fst_portable.py index 95435ce0e..c6a7fe75c 100755 --- a/test_regress/t/t_trace_array_cc_fst_portable.py +++ b/test_regress/t/t_trace_array_cc_fst_portable.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_array_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_array_common.run(test, verilator_flags2=["-CFLAGS", "-DVL_PORTABLE_ONLY"]) diff --git a/test_regress/t/t_trace_array_cc_saif.py b/test_regress/t/t_trace_array_cc_saif.py index 499943a69..86cb8b97a 100755 --- a/test_regress/t/t_trace_array_cc_saif.py +++ b/test_regress/t/t_trace_array_cc_saif.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_array_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_array_common.run(test) diff --git a/test_regress/t/t_trace_array_cc_saif_portable.py b/test_regress/t/t_trace_array_cc_saif_portable.py index 95435ce0e..c6a7fe75c 100755 --- a/test_regress/t/t_trace_array_cc_saif_portable.py +++ b/test_regress/t/t_trace_array_cc_saif_portable.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_array_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_array_common.run(test, verilator_flags2=["-CFLAGS", "-DVL_PORTABLE_ONLY"]) diff --git a/test_regress/t/t_trace_array_cc_vcd.py b/test_regress/t/t_trace_array_cc_vcd.py index 499943a69..86cb8b97a 100755 --- a/test_regress/t/t_trace_array_cc_vcd.py +++ b/test_regress/t/t_trace_array_cc_vcd.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_array_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_array_common.run(test) diff --git a/test_regress/t/t_trace_array_sc_fst.py b/test_regress/t/t_trace_array_sc_fst.py index 499943a69..86cb8b97a 100755 --- a/test_regress/t/t_trace_array_sc_fst.py +++ b/test_regress/t/t_trace_array_sc_fst.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_array_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_array_common.run(test) diff --git a/test_regress/t/t_trace_array_sc_fst_portable.py b/test_regress/t/t_trace_array_sc_fst_portable.py index 95435ce0e..c6a7fe75c 100755 --- a/test_regress/t/t_trace_array_sc_fst_portable.py +++ b/test_regress/t/t_trace_array_sc_fst_portable.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_array_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_array_common.run(test, verilator_flags2=["-CFLAGS", "-DVL_PORTABLE_ONLY"]) diff --git a/test_regress/t/t_trace_ascendingrange_cc_fst.py b/test_regress/t/t_trace_ascendingrange_cc_fst.py index 41bbbddf8..937f9f2e1 100755 --- a/test_regress/t/t_trace_ascendingrange_cc_fst.py +++ b/test_regress/t/t_trace_ascendingrange_cc_fst.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_ascendingrange_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_ascendingrange_common.run(test) diff --git a/test_regress/t/t_trace_ascendingrange_cc_saif.py b/test_regress/t/t_trace_ascendingrange_cc_saif.py index 41bbbddf8..937f9f2e1 100755 --- a/test_regress/t/t_trace_ascendingrange_cc_saif.py +++ b/test_regress/t/t_trace_ascendingrange_cc_saif.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_ascendingrange_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_ascendingrange_common.run(test) diff --git a/test_regress/t/t_trace_ascendingrange_cc_vcd.py b/test_regress/t/t_trace_ascendingrange_cc_vcd.py index 41bbbddf8..937f9f2e1 100755 --- a/test_regress/t/t_trace_ascendingrange_cc_vcd.py +++ b/test_regress/t/t_trace_ascendingrange_cc_vcd.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_ascendingrange_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_ascendingrange_common.run(test) diff --git a/test_regress/t/t_trace_ascendingrange_sc_fst.py b/test_regress/t/t_trace_ascendingrange_sc_fst.py index 41bbbddf8..937f9f2e1 100755 --- a/test_regress/t/t_trace_ascendingrange_sc_fst.py +++ b/test_regress/t/t_trace_ascendingrange_sc_fst.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_ascendingrange_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_ascendingrange_common.run(test) diff --git a/test_regress/t/t_trace_basic_cc_fst.py b/test_regress/t/t_trace_basic_cc_fst.py index a95b13c4a..f3581c4bc 100755 --- a/test_regress/t/t_trace_basic_cc_fst.py +++ b/test_regress/t/t_trace_basic_cc_fst.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_basic_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_basic_common.run(test) diff --git a/test_regress/t/t_trace_basic_cc_fst_cmake.py b/test_regress/t/t_trace_basic_cc_fst_cmake.py index fa52fde4c..eb8b7c6dc 100755 --- a/test_regress/t/t_trace_basic_cc_fst_cmake.py +++ b/test_regress/t/t_trace_basic_cc_fst_cmake.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_basic_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_basic_common.run(test, cmake=True) diff --git a/test_regress/t/t_trace_basic_cc_saif.py b/test_regress/t/t_trace_basic_cc_saif.py index a95b13c4a..f3581c4bc 100755 --- a/test_regress/t/t_trace_basic_cc_saif.py +++ b/test_regress/t/t_trace_basic_cc_saif.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_basic_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_basic_common.run(test) diff --git a/test_regress/t/t_trace_basic_cc_saif_cmake.py b/test_regress/t/t_trace_basic_cc_saif_cmake.py index fa52fde4c..eb8b7c6dc 100755 --- a/test_regress/t/t_trace_basic_cc_saif_cmake.py +++ b/test_regress/t/t_trace_basic_cc_saif_cmake.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_basic_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_basic_common.run(test, cmake=True) diff --git a/test_regress/t/t_trace_basic_cc_vcd.py b/test_regress/t/t_trace_basic_cc_vcd.py index a95b13c4a..f3581c4bc 100755 --- a/test_regress/t/t_trace_basic_cc_vcd.py +++ b/test_regress/t/t_trace_basic_cc_vcd.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_basic_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_basic_common.run(test) diff --git a/test_regress/t/t_trace_basic_cc_vcd_cmake.py b/test_regress/t/t_trace_basic_cc_vcd_cmake.py index fa52fde4c..eb8b7c6dc 100755 --- a/test_regress/t/t_trace_basic_cc_vcd_cmake.py +++ b/test_regress/t/t_trace_basic_cc_vcd_cmake.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_basic_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_basic_common.run(test, cmake=True) diff --git a/test_regress/t/t_trace_basic_sc_fst.py b/test_regress/t/t_trace_basic_sc_fst.py index a95b13c4a..f3581c4bc 100755 --- a/test_regress/t/t_trace_basic_sc_fst.py +++ b/test_regress/t/t_trace_basic_sc_fst.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_basic_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_basic_common.run(test) diff --git a/test_regress/t/t_trace_basic_sc_fst_cmake.py b/test_regress/t/t_trace_basic_sc_fst_cmake.py index fa52fde4c..eb8b7c6dc 100755 --- a/test_regress/t/t_trace_basic_sc_fst_cmake.py +++ b/test_regress/t/t_trace_basic_sc_fst_cmake.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_basic_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_basic_common.run(test, cmake=True) diff --git a/test_regress/t/t_trace_basic_sc_saif.py b/test_regress/t/t_trace_basic_sc_saif.py index a95b13c4a..f3581c4bc 100755 --- a/test_regress/t/t_trace_basic_sc_saif.py +++ b/test_regress/t/t_trace_basic_sc_saif.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_basic_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_basic_common.run(test) diff --git a/test_regress/t/t_trace_basic_sc_saif_cmake.py b/test_regress/t/t_trace_basic_sc_saif_cmake.py index fa52fde4c..eb8b7c6dc 100755 --- a/test_regress/t/t_trace_basic_sc_saif_cmake.py +++ b/test_regress/t/t_trace_basic_sc_saif_cmake.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_basic_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_basic_common.run(test, cmake=True) diff --git a/test_regress/t/t_trace_basic_sc_vcd.py b/test_regress/t/t_trace_basic_sc_vcd.py index a95b13c4a..f3581c4bc 100755 --- a/test_regress/t/t_trace_basic_sc_vcd.py +++ b/test_regress/t/t_trace_basic_sc_vcd.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_basic_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_basic_common.run(test) diff --git a/test_regress/t/t_trace_basic_sc_vcd_cmake.py b/test_regress/t/t_trace_basic_sc_vcd_cmake.py index fa52fde4c..eb8b7c6dc 100755 --- a/test_regress/t/t_trace_basic_sc_vcd_cmake.py +++ b/test_regress/t/t_trace_basic_sc_vcd_cmake.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_basic_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_basic_common.run(test, cmake=True) diff --git a/test_regress/t/t_trace_cat_opennext_vcd.py b/test_regress/t/t_trace_cat_opennext_vcd.py index e1fda3adb..3b173d1c8 100755 --- a/test_regress/t/t_trace_cat_opennext_vcd.py +++ b/test_regress/t/t_trace_cat_opennext_vcd.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_cat_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_cat_common.run(test) diff --git a/test_regress/t/t_trace_cat_renew_fst.py b/test_regress/t/t_trace_cat_renew_fst.py index e1fda3adb..3b173d1c8 100755 --- a/test_regress/t/t_trace_cat_renew_fst.py +++ b/test_regress/t/t_trace_cat_renew_fst.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_cat_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_cat_common.run(test) diff --git a/test_regress/t/t_trace_cat_renew_saif.py b/test_regress/t/t_trace_cat_renew_saif.py index e1fda3adb..3b173d1c8 100755 --- a/test_regress/t/t_trace_cat_renew_saif.py +++ b/test_regress/t/t_trace_cat_renew_saif.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_cat_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_cat_common.run(test) diff --git a/test_regress/t/t_trace_cat_renew_vcd.py b/test_regress/t/t_trace_cat_renew_vcd.py index e1fda3adb..3b173d1c8 100755 --- a/test_regress/t/t_trace_cat_renew_vcd.py +++ b/test_regress/t/t_trace_cat_renew_vcd.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_cat_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_cat_common.run(test) diff --git a/test_regress/t/t_trace_cat_reopen_fst.py b/test_regress/t/t_trace_cat_reopen_fst.py index e1fda3adb..3b173d1c8 100755 --- a/test_regress/t/t_trace_cat_reopen_fst.py +++ b/test_regress/t/t_trace_cat_reopen_fst.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_cat_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_cat_common.run(test) diff --git a/test_regress/t/t_trace_cat_reopen_saif.py b/test_regress/t/t_trace_cat_reopen_saif.py index e1fda3adb..3b173d1c8 100755 --- a/test_regress/t/t_trace_cat_reopen_saif.py +++ b/test_regress/t/t_trace_cat_reopen_saif.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_cat_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_cat_common.run(test) diff --git a/test_regress/t/t_trace_cat_reopen_vcd.py b/test_regress/t/t_trace_cat_reopen_vcd.py index e1fda3adb..3b173d1c8 100755 --- a/test_regress/t/t_trace_cat_reopen_vcd.py +++ b/test_regress/t/t_trace_cat_reopen_vcd.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_cat_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_cat_common.run(test) diff --git a/test_regress/t/t_trace_complex_default_cc_fst.out b/test_regress/t/t_trace_complex_default_cc_fst.out index dd52c681b..e09852981 100644 --- a/test_regress/t/t_trace_complex_default_cc_fst.out +++ b/test_regress/t/t_trace_complex_default_cc_fst.out @@ -1,9 +1,5 @@ $date -<<<<<<< HEAD Tue Apr 14 15:20:37 2026 -======= -Tue Mar 31 17:14:29 2026 ->>>>>>> 8895f96e4 (CR) $end $version diff --git a/test_regress/t/t_trace_complex_default_cc_fst.py b/test_regress/t/t_trace_complex_default_cc_fst.py index 13a12d3b1..f2f518cb5 100755 --- a/test_regress/t/t_trace_complex_default_cc_fst.py +++ b/test_regress/t/t_trace_complex_default_cc_fst.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_complex_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_complex_common.run(test) diff --git a/test_regress/t/t_trace_complex_default_cc_fst_noinl.py b/test_regress/t/t_trace_complex_default_cc_fst_noinl.py index b929c69bc..06b870fc7 100755 --- a/test_regress/t/t_trace_complex_default_cc_fst_noinl.py +++ b/test_regress/t/t_trace_complex_default_cc_fst_noinl.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_complex_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_complex_common.run(test, verilator_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_trace_complex_default_cc_saif.py b/test_regress/t/t_trace_complex_default_cc_saif.py index 13a12d3b1..f2f518cb5 100755 --- a/test_regress/t/t_trace_complex_default_cc_saif.py +++ b/test_regress/t/t_trace_complex_default_cc_saif.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_complex_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_complex_common.run(test) diff --git a/test_regress/t/t_trace_complex_default_cc_saif_noinl.py b/test_regress/t/t_trace_complex_default_cc_saif_noinl.py index b929c69bc..06b870fc7 100755 --- a/test_regress/t/t_trace_complex_default_cc_saif_noinl.py +++ b/test_regress/t/t_trace_complex_default_cc_saif_noinl.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_complex_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_complex_common.run(test, verilator_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_trace_complex_default_cc_vcd.py b/test_regress/t/t_trace_complex_default_cc_vcd.py index 13a12d3b1..f2f518cb5 100755 --- a/test_regress/t/t_trace_complex_default_cc_vcd.py +++ b/test_regress/t/t_trace_complex_default_cc_vcd.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_complex_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_complex_common.run(test) diff --git a/test_regress/t/t_trace_complex_default_cc_vcd_noinl.py b/test_regress/t/t_trace_complex_default_cc_vcd_noinl.py index b929c69bc..06b870fc7 100755 --- a/test_regress/t/t_trace_complex_default_cc_vcd_noinl.py +++ b/test_regress/t/t_trace_complex_default_cc_vcd_noinl.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_complex_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_complex_common.run(test, verilator_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_trace_complex_default_cc_vcd_portable.py b/test_regress/t/t_trace_complex_default_cc_vcd_portable.py index 8df18bc02..950c246c0 100755 --- a/test_regress/t/t_trace_complex_default_cc_vcd_portable.py +++ b/test_regress/t/t_trace_complex_default_cc_vcd_portable.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_complex_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_complex_common.run(test, verilator_flags2=["-CFLAGS", "-DVL_PORTABLE_ONLY"]) diff --git a/test_regress/t/t_trace_complex_default_sc_fst.out b/test_regress/t/t_trace_complex_default_sc_fst.out index 0069d6a7f..dcb880cd3 100644 --- a/test_regress/t/t_trace_complex_default_sc_fst.out +++ b/test_regress/t/t_trace_complex_default_sc_fst.out @@ -1,9 +1,5 @@ $date -<<<<<<< HEAD Tue Apr 14 15:20:39 2026 -======= -Tue Mar 31 17:14:34 2026 ->>>>>>> 8895f96e4 (CR) $end $version diff --git a/test_regress/t/t_trace_complex_default_sc_fst.py b/test_regress/t/t_trace_complex_default_sc_fst.py index 13a12d3b1..f2f518cb5 100755 --- a/test_regress/t/t_trace_complex_default_sc_fst.py +++ b/test_regress/t/t_trace_complex_default_sc_fst.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_complex_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_complex_common.run(test) diff --git a/test_regress/t/t_trace_complex_default_sc_vcd.py b/test_regress/t/t_trace_complex_default_sc_vcd.py index 13a12d3b1..f2f518cb5 100755 --- a/test_regress/t/t_trace_complex_default_sc_vcd.py +++ b/test_regress/t/t_trace_complex_default_sc_vcd.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_complex_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_complex_common.run(test) diff --git a/test_regress/t/t_trace_complex_params_cc_fst.out b/test_regress/t/t_trace_complex_params_cc_fst.out index 3f10e2e50..a88fda804 100644 --- a/test_regress/t/t_trace_complex_params_cc_fst.out +++ b/test_regress/t/t_trace_complex_params_cc_fst.out @@ -1,9 +1,5 @@ $date -<<<<<<< HEAD Tue Apr 14 15:20:39 2026 -======= -Tue Mar 31 17:14:36 2026 ->>>>>>> 8895f96e4 (CR) $end $version diff --git a/test_regress/t/t_trace_complex_params_cc_fst.py b/test_regress/t/t_trace_complex_params_cc_fst.py index 13a12d3b1..f2f518cb5 100755 --- a/test_regress/t/t_trace_complex_params_cc_fst.py +++ b/test_regress/t/t_trace_complex_params_cc_fst.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_complex_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_complex_common.run(test) diff --git a/test_regress/t/t_trace_complex_params_cc_fst_noinl.py b/test_regress/t/t_trace_complex_params_cc_fst_noinl.py index b929c69bc..06b870fc7 100755 --- a/test_regress/t/t_trace_complex_params_cc_fst_noinl.py +++ b/test_regress/t/t_trace_complex_params_cc_fst_noinl.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_complex_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_complex_common.run(test, verilator_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_trace_complex_params_cc_saif.py b/test_regress/t/t_trace_complex_params_cc_saif.py index 13a12d3b1..f2f518cb5 100755 --- a/test_regress/t/t_trace_complex_params_cc_saif.py +++ b/test_regress/t/t_trace_complex_params_cc_saif.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_complex_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_complex_common.run(test) diff --git a/test_regress/t/t_trace_complex_params_cc_saif_noinl.py b/test_regress/t/t_trace_complex_params_cc_saif_noinl.py index b929c69bc..06b870fc7 100755 --- a/test_regress/t/t_trace_complex_params_cc_saif_noinl.py +++ b/test_regress/t/t_trace_complex_params_cc_saif_noinl.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_complex_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_complex_common.run(test, verilator_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_trace_complex_params_cc_vcd.py b/test_regress/t/t_trace_complex_params_cc_vcd.py index 13a12d3b1..f2f518cb5 100755 --- a/test_regress/t/t_trace_complex_params_cc_vcd.py +++ b/test_regress/t/t_trace_complex_params_cc_vcd.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_complex_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_complex_common.run(test) diff --git a/test_regress/t/t_trace_complex_params_cc_vcd_noinl.py b/test_regress/t/t_trace_complex_params_cc_vcd_noinl.py index b929c69bc..06b870fc7 100755 --- a/test_regress/t/t_trace_complex_params_cc_vcd_noinl.py +++ b/test_regress/t/t_trace_complex_params_cc_vcd_noinl.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_complex_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_complex_common.run(test, verilator_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_trace_complex_params_sc_fst.out b/test_regress/t/t_trace_complex_params_sc_fst.out index 34c978935..45f75ee37 100644 --- a/test_regress/t/t_trace_complex_params_sc_fst.out +++ b/test_regress/t/t_trace_complex_params_sc_fst.out @@ -1,9 +1,5 @@ $date -<<<<<<< HEAD Tue Apr 14 15:20:41 2026 -======= -Tue Mar 31 17:14:39 2026 ->>>>>>> 8895f96e4 (CR) $end $version diff --git a/test_regress/t/t_trace_complex_params_sc_fst.py b/test_regress/t/t_trace_complex_params_sc_fst.py index 13a12d3b1..f2f518cb5 100755 --- a/test_regress/t/t_trace_complex_params_sc_fst.py +++ b/test_regress/t/t_trace_complex_params_sc_fst.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_complex_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_complex_common.run(test) diff --git a/test_regress/t/t_trace_complex_params_sc_vcd.py b/test_regress/t/t_trace_complex_params_sc_vcd.py index 13a12d3b1..f2f518cb5 100755 --- a/test_regress/t/t_trace_complex_params_sc_vcd.py +++ b/test_regress/t/t_trace_complex_params_sc_vcd.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_complex_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_complex_common.run(test) diff --git a/test_regress/t/t_trace_complex_structs_cc_fst.out b/test_regress/t/t_trace_complex_structs_cc_fst.out index 3486fb134..520f2a3bb 100644 --- a/test_regress/t/t_trace_complex_structs_cc_fst.out +++ b/test_regress/t/t_trace_complex_structs_cc_fst.out @@ -1,9 +1,5 @@ $date -<<<<<<< HEAD Tue Apr 14 15:20:40 2026 -======= -Tue Mar 31 17:14:42 2026 ->>>>>>> 8895f96e4 (CR) $end $version diff --git a/test_regress/t/t_trace_complex_structs_cc_fst.py b/test_regress/t/t_trace_complex_structs_cc_fst.py index 13a12d3b1..f2f518cb5 100755 --- a/test_regress/t/t_trace_complex_structs_cc_fst.py +++ b/test_regress/t/t_trace_complex_structs_cc_fst.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_complex_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_complex_common.run(test) diff --git a/test_regress/t/t_trace_complex_structs_cc_fst_noinl.py b/test_regress/t/t_trace_complex_structs_cc_fst_noinl.py index b929c69bc..06b870fc7 100755 --- a/test_regress/t/t_trace_complex_structs_cc_fst_noinl.py +++ b/test_regress/t/t_trace_complex_structs_cc_fst_noinl.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_complex_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_complex_common.run(test, verilator_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_trace_complex_structs_cc_saif.py b/test_regress/t/t_trace_complex_structs_cc_saif.py index 13a12d3b1..f2f518cb5 100755 --- a/test_regress/t/t_trace_complex_structs_cc_saif.py +++ b/test_regress/t/t_trace_complex_structs_cc_saif.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_complex_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_complex_common.run(test) diff --git a/test_regress/t/t_trace_complex_structs_cc_saif_noinl.py b/test_regress/t/t_trace_complex_structs_cc_saif_noinl.py index b929c69bc..06b870fc7 100755 --- a/test_regress/t/t_trace_complex_structs_cc_saif_noinl.py +++ b/test_regress/t/t_trace_complex_structs_cc_saif_noinl.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_complex_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_complex_common.run(test, verilator_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_trace_complex_structs_cc_vcd.py b/test_regress/t/t_trace_complex_structs_cc_vcd.py index 13a12d3b1..f2f518cb5 100755 --- a/test_regress/t/t_trace_complex_structs_cc_vcd.py +++ b/test_regress/t/t_trace_complex_structs_cc_vcd.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_complex_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_complex_common.run(test) diff --git a/test_regress/t/t_trace_complex_structs_cc_vcd_noinl.py b/test_regress/t/t_trace_complex_structs_cc_vcd_noinl.py index b929c69bc..06b870fc7 100755 --- a/test_regress/t/t_trace_complex_structs_cc_vcd_noinl.py +++ b/test_regress/t/t_trace_complex_structs_cc_vcd_noinl.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_complex_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_complex_common.run(test, verilator_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_trace_complex_structs_sc_fst.out b/test_regress/t/t_trace_complex_structs_sc_fst.out index 662f16239..163e8787b 100644 --- a/test_regress/t/t_trace_complex_structs_sc_fst.out +++ b/test_regress/t/t_trace_complex_structs_sc_fst.out @@ -1,9 +1,5 @@ $date -<<<<<<< HEAD Tue Apr 14 15:20:41 2026 -======= -Tue Mar 31 17:14:45 2026 ->>>>>>> 8895f96e4 (CR) $end $version diff --git a/test_regress/t/t_trace_complex_structs_sc_fst.py b/test_regress/t/t_trace_complex_structs_sc_fst.py index 13a12d3b1..f2f518cb5 100755 --- a/test_regress/t/t_trace_complex_structs_sc_fst.py +++ b/test_regress/t/t_trace_complex_structs_sc_fst.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_complex_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_complex_common.run(test) diff --git a/test_regress/t/t_trace_complex_structs_sc_vcd.py b/test_regress/t/t_trace_complex_structs_sc_vcd.py index 13a12d3b1..f2f518cb5 100755 --- a/test_regress/t/t_trace_complex_structs_sc_vcd.py +++ b/test_regress/t/t_trace_complex_structs_sc_vcd.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_complex_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_complex_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_dyn_0_cc_fst.py b/test_regress/t/t_trace_dumpvars_dyn_0_cc_fst.py index 189a9b46d..2befad8b0 100755 --- a/test_regress/t/t_trace_dumpvars_dyn_0_cc_fst.py +++ b/test_regress/t/t_trace_dumpvars_dyn_0_cc_fst.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_dumpvars_dyn_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_dumpvars_dyn_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_dyn_1_cc_fst.py b/test_regress/t/t_trace_dumpvars_dyn_1_cc_fst.py index 189a9b46d..2befad8b0 100755 --- a/test_regress/t/t_trace_dumpvars_dyn_1_cc_fst.py +++ b/test_regress/t/t_trace_dumpvars_dyn_1_cc_fst.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_dumpvars_dyn_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_dumpvars_dyn_common.run(test) diff --git a/test_regress/t/t_trace_ena_cc.py b/test_regress/t/t_trace_ena_cc.py index feaf52dec..71a0b2ad2 100755 --- a/test_regress/t/t_trace_ena_cc.py +++ b/test_regress/t/t_trace_ena_cc.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_trace_ena.v" test.compile(verilator_flags2=['-trace']) diff --git a/test_regress/t/t_trace_ena_sc.py b/test_regress/t/t_trace_ena_sc.py index 8d20ab7f2..d91bbfde1 100755 --- a/test_regress/t/t_trace_ena_sc.py +++ b/test_regress/t/t_trace_ena_sc.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_trace_ena.v" if not test.have_sc: diff --git a/test_regress/t/t_trace_enum_fst.py b/test_regress/t/t_trace_enum_fst.py index aff027207..5c5869937 100755 --- a/test_regress/t/t_trace_enum_fst.py +++ b/test_regress/t/t_trace_enum_fst.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_enum_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_enum_common.run(test) diff --git a/test_regress/t/t_trace_enum_saif.py b/test_regress/t/t_trace_enum_saif.py index aff027207..5c5869937 100755 --- a/test_regress/t/t_trace_enum_saif.py +++ b/test_regress/t/t_trace_enum_saif.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_enum_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_enum_common.run(test) diff --git a/test_regress/t/t_trace_enum_vcd.py b/test_regress/t/t_trace_enum_vcd.py index aff027207..5c5869937 100755 --- a/test_regress/t/t_trace_enum_vcd.py +++ b/test_regress/t/t_trace_enum_vcd.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_enum_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_enum_common.run(test) diff --git a/test_regress/t/t_trace_event_fst.py b/test_regress/t/t_trace_event_fst.py index 7598a23bd..41402e73d 100755 --- a/test_regress/t/t_trace_event_fst.py +++ b/test_regress/t/t_trace_event_fst.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_event_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_event_common.run(test) diff --git a/test_regress/t/t_trace_hier_block_default_cc_fst.py b/test_regress/t/t_trace_hier_block_default_cc_fst.py index 14165eea8..dec3f0a8e 100755 --- a/test_regress/t/t_trace_hier_block_default_cc_fst.py +++ b/test_regress/t/t_trace_hier_block_default_cc_fst.py @@ -12,5 +12,6 @@ import trace_hier_block_common test.priority(30) test.scenarios('vlt_all') +test.fourstate_capable = False trace_hier_block_common.run(test) diff --git a/test_regress/t/t_trace_hier_block_default_cc_fst_noinl.py b/test_regress/t/t_trace_hier_block_default_cc_fst_noinl.py index b4ae62596..f88accb6b 100755 --- a/test_regress/t/t_trace_hier_block_default_cc_fst_noinl.py +++ b/test_regress/t/t_trace_hier_block_default_cc_fst_noinl.py @@ -12,5 +12,6 @@ import trace_hier_block_common test.priority(30) test.scenarios('vlt_all') +test.fourstate_capable = False trace_hier_block_common.run(test, verilator_flags2=["+define+NO_INLINE"]) diff --git a/test_regress/t/t_trace_hier_block_default_cc_saif.py b/test_regress/t/t_trace_hier_block_default_cc_saif.py index 14165eea8..dec3f0a8e 100755 --- a/test_regress/t/t_trace_hier_block_default_cc_saif.py +++ b/test_regress/t/t_trace_hier_block_default_cc_saif.py @@ -12,5 +12,6 @@ import trace_hier_block_common test.priority(30) test.scenarios('vlt_all') +test.fourstate_capable = False trace_hier_block_common.run(test) diff --git a/test_regress/t/t_trace_hier_block_default_cc_saif_noinl.py b/test_regress/t/t_trace_hier_block_default_cc_saif_noinl.py index b4ae62596..f88accb6b 100755 --- a/test_regress/t/t_trace_hier_block_default_cc_saif_noinl.py +++ b/test_regress/t/t_trace_hier_block_default_cc_saif_noinl.py @@ -12,5 +12,6 @@ import trace_hier_block_common test.priority(30) test.scenarios('vlt_all') +test.fourstate_capable = False trace_hier_block_common.run(test, verilator_flags2=["+define+NO_INLINE"]) diff --git a/test_regress/t/t_trace_hier_block_default_cc_vcd.py b/test_regress/t/t_trace_hier_block_default_cc_vcd.py index 14165eea8..dec3f0a8e 100755 --- a/test_regress/t/t_trace_hier_block_default_cc_vcd.py +++ b/test_regress/t/t_trace_hier_block_default_cc_vcd.py @@ -12,5 +12,6 @@ import trace_hier_block_common test.priority(30) test.scenarios('vlt_all') +test.fourstate_capable = False trace_hier_block_common.run(test) diff --git a/test_regress/t/t_trace_hier_block_default_cc_vcd_noinl.py b/test_regress/t/t_trace_hier_block_default_cc_vcd_noinl.py index b4ae62596..f88accb6b 100755 --- a/test_regress/t/t_trace_hier_block_default_cc_vcd_noinl.py +++ b/test_regress/t/t_trace_hier_block_default_cc_vcd_noinl.py @@ -12,5 +12,6 @@ import trace_hier_block_common test.priority(30) test.scenarios('vlt_all') +test.fourstate_capable = False trace_hier_block_common.run(test, verilator_flags2=["+define+NO_INLINE"]) diff --git a/test_regress/t/t_trace_hier_block_default_sc_fst.py b/test_regress/t/t_trace_hier_block_default_sc_fst.py index 14165eea8..dec3f0a8e 100755 --- a/test_regress/t/t_trace_hier_block_default_sc_fst.py +++ b/test_regress/t/t_trace_hier_block_default_sc_fst.py @@ -12,5 +12,6 @@ import trace_hier_block_common test.priority(30) test.scenarios('vlt_all') +test.fourstate_capable = False trace_hier_block_common.run(test) diff --git a/test_regress/t/t_trace_hier_block_default_sc_vcd.py b/test_regress/t/t_trace_hier_block_default_sc_vcd.py index 14165eea8..dec3f0a8e 100755 --- a/test_regress/t/t_trace_hier_block_default_sc_vcd.py +++ b/test_regress/t/t_trace_hier_block_default_sc_vcd.py @@ -12,5 +12,6 @@ import trace_hier_block_common test.priority(30) test.scenarios('vlt_all') +test.fourstate_capable = False trace_hier_block_common.run(test) diff --git a/test_regress/t/t_trace_hier_block_notop_cc_fst.py b/test_regress/t/t_trace_hier_block_notop_cc_fst.py index 14165eea8..dec3f0a8e 100755 --- a/test_regress/t/t_trace_hier_block_notop_cc_fst.py +++ b/test_regress/t/t_trace_hier_block_notop_cc_fst.py @@ -12,5 +12,6 @@ import trace_hier_block_common test.priority(30) test.scenarios('vlt_all') +test.fourstate_capable = False trace_hier_block_common.run(test) diff --git a/test_regress/t/t_trace_hier_block_notop_cc_saif.py b/test_regress/t/t_trace_hier_block_notop_cc_saif.py index 14165eea8..dec3f0a8e 100755 --- a/test_regress/t/t_trace_hier_block_notop_cc_saif.py +++ b/test_regress/t/t_trace_hier_block_notop_cc_saif.py @@ -12,5 +12,6 @@ import trace_hier_block_common test.priority(30) test.scenarios('vlt_all') +test.fourstate_capable = False trace_hier_block_common.run(test) diff --git a/test_regress/t/t_trace_hier_block_notop_cc_vcd.py b/test_regress/t/t_trace_hier_block_notop_cc_vcd.py index 14165eea8..dec3f0a8e 100755 --- a/test_regress/t/t_trace_hier_block_notop_cc_vcd.py +++ b/test_regress/t/t_trace_hier_block_notop_cc_vcd.py @@ -12,5 +12,6 @@ import trace_hier_block_common test.priority(30) test.scenarios('vlt_all') +test.fourstate_capable = False trace_hier_block_common.run(test) diff --git a/test_regress/t/t_trace_hier_block_statefulpkg_cc_vcd.py b/test_regress/t/t_trace_hier_block_statefulpkg_cc_vcd.py index 14165eea8..dec3f0a8e 100755 --- a/test_regress/t/t_trace_hier_block_statefulpkg_cc_vcd.py +++ b/test_regress/t/t_trace_hier_block_statefulpkg_cc_vcd.py @@ -12,5 +12,6 @@ import trace_hier_block_common test.priority(30) test.scenarios('vlt_all') +test.fourstate_capable = False trace_hier_block_common.run(test) diff --git a/test_regress/t/t_trace_hier_fst.py b/test_regress/t/t_trace_hier_fst.py index 8000fcfd0..4513b7df4 100755 --- a/test_regress/t/t_trace_hier_fst.py +++ b/test_regress/t/t_trace_hier_fst.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_hier_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_hier_common.run(test) diff --git a/test_regress/t/t_trace_hier_fst_noinl.py b/test_regress/t/t_trace_hier_fst_noinl.py index 532949897..4d51d97d6 100755 --- a/test_regress/t/t_trace_hier_fst_noinl.py +++ b/test_regress/t/t_trace_hier_fst_noinl.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_hier_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_hier_common.run(test, verilator_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_trace_hier_saif.py b/test_regress/t/t_trace_hier_saif.py index 8000fcfd0..4513b7df4 100755 --- a/test_regress/t/t_trace_hier_saif.py +++ b/test_regress/t/t_trace_hier_saif.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_hier_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_hier_common.run(test) diff --git a/test_regress/t/t_trace_hier_saif_noinl.py b/test_regress/t/t_trace_hier_saif_noinl.py index 532949897..4d51d97d6 100755 --- a/test_regress/t/t_trace_hier_saif_noinl.py +++ b/test_regress/t/t_trace_hier_saif_noinl.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_hier_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_hier_common.run(test, verilator_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_trace_hier_vcd.py b/test_regress/t/t_trace_hier_vcd.py index 8000fcfd0..4513b7df4 100755 --- a/test_regress/t/t_trace_hier_vcd.py +++ b/test_regress/t/t_trace_hier_vcd.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_hier_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_hier_common.run(test) diff --git a/test_regress/t/t_trace_hier_vcd_noinl.py b/test_regress/t/t_trace_hier_vcd_noinl.py index 532949897..4d51d97d6 100755 --- a/test_regress/t/t_trace_hier_vcd_noinl.py +++ b/test_regress/t/t_trace_hier_vcd_noinl.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_hier_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_hier_common.run(test, verilator_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_trace_huge_array.py b/test_regress/t/t_trace_huge_array.py index 5fc9fecce..1c961119f 100755 --- a/test_regress/t/t_trace_huge_array.py +++ b/test_regress/t/t_trace_huge_array.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios("vlt_all") +test.fourstate_capable = False test.compile(v_flags2=[ "--trace-vcd --trace-max-width 0 --trace-max-array 0 --output-split-ctrace 10 --trace-structs" diff --git a/test_regress/t/t_trace_iface.py b/test_regress/t/t_trace_iface.py index 91f67a0fe..72cfe1318 100755 --- a/test_regress/t/t_trace_iface.py +++ b/test_regress/t/t_trace_iface.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(verilator_flags2=['--trace-vcd']) diff --git a/test_regress/t/t_trace_interface_ref_cc_fst.py b/test_regress/t/t_trace_interface_ref_cc_fst.py index 0fac34f3a..23d5a4546 100755 --- a/test_regress/t/t_trace_interface_ref_cc_fst.py +++ b/test_regress/t/t_trace_interface_ref_cc_fst.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_interface_ref_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_interface_ref_common.run(test) diff --git a/test_regress/t/t_trace_interface_ref_cc_saif.py b/test_regress/t/t_trace_interface_ref_cc_saif.py index 0fac34f3a..23d5a4546 100755 --- a/test_regress/t/t_trace_interface_ref_cc_saif.py +++ b/test_regress/t/t_trace_interface_ref_cc_saif.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_interface_ref_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_interface_ref_common.run(test) diff --git a/test_regress/t/t_trace_interface_ref_cc_vcd.py b/test_regress/t/t_trace_interface_ref_cc_vcd.py index 0fac34f3a..23d5a4546 100755 --- a/test_regress/t/t_trace_interface_ref_cc_vcd.py +++ b/test_regress/t/t_trace_interface_ref_cc_vcd.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_interface_ref_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_interface_ref_common.run(test) diff --git a/test_regress/t/t_trace_interface_ref_cc_vcd_inla.py b/test_regress/t/t_trace_interface_ref_cc_vcd_inla.py index e311419f3..7b50e417e 100755 --- a/test_regress/t/t_trace_interface_ref_cc_vcd_inla.py +++ b/test_regress/t/t_trace_interface_ref_cc_vcd_inla.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_interface_ref_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_interface_ref_common.run(test, verilator_flags2=["+define+NO_INLINE_A"]) diff --git a/test_regress/t/t_trace_interface_ref_cc_vcd_inlab.py b/test_regress/t/t_trace_interface_ref_cc_vcd_inlab.py index 38b269e81..7f393eea2 100755 --- a/test_regress/t/t_trace_interface_ref_cc_vcd_inlab.py +++ b/test_regress/t/t_trace_interface_ref_cc_vcd_inlab.py @@ -11,6 +11,7 @@ import vltest_bootstrap import trace_interface_ref_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_interface_ref_common.run(test, verilator_flags2=["+define+NO_INLINE_A", "+define+NO_INLINE_B"]) diff --git a/test_regress/t/t_trace_interface_ref_cc_vcd_inlb.py b/test_regress/t/t_trace_interface_ref_cc_vcd_inlb.py index 389614688..507ca1ba9 100755 --- a/test_regress/t/t_trace_interface_ref_cc_vcd_inlb.py +++ b/test_regress/t/t_trace_interface_ref_cc_vcd_inlb.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_interface_ref_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_interface_ref_common.run(test, verilator_flags2=["+define+NO_INLINE_B"]) diff --git a/test_regress/t/t_trace_interface_ref_cc_vcd_noinl.py b/test_regress/t/t_trace_interface_ref_cc_vcd_noinl.py index 1a8543f75..58400b693 100755 --- a/test_regress/t/t_trace_interface_ref_cc_vcd_noinl.py +++ b/test_regress/t/t_trace_interface_ref_cc_vcd_noinl.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_interface_ref_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_interface_ref_common.run(test, verilator_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_trace_interface_ref_sc_fst.py b/test_regress/t/t_trace_interface_ref_sc_fst.py index 0fac34f3a..23d5a4546 100755 --- a/test_regress/t/t_trace_interface_ref_sc_fst.py +++ b/test_regress/t/t_trace_interface_ref_sc_fst.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_interface_ref_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_interface_ref_common.run(test) diff --git a/test_regress/t/t_trace_lib_as_top_fst.py b/test_regress/t/t_trace_lib_as_top_fst.py index b42540816..ae685e3c7 100755 --- a/test_regress/t/t_trace_lib_as_top_fst.py +++ b/test_regress/t/t_trace_lib_as_top_fst.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_lib_as_top_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_lib_as_top_common.run(test) diff --git a/test_regress/t/t_trace_lib_default_fst.py b/test_regress/t/t_trace_lib_default_fst.py index 5d5e0a225..324dc5bab 100755 --- a/test_regress/t/t_trace_lib_default_fst.py +++ b/test_regress/t/t_trace_lib_default_fst.py @@ -12,5 +12,6 @@ import trace_lib_common test.priority(10) test.scenarios('vlt_all') +test.fourstate_capable = False trace_lib_common.run(test) diff --git a/test_regress/t/t_trace_lib_default_saif.py b/test_regress/t/t_trace_lib_default_saif.py index 5d5e0a225..324dc5bab 100755 --- a/test_regress/t/t_trace_lib_default_saif.py +++ b/test_regress/t/t_trace_lib_default_saif.py @@ -12,5 +12,6 @@ import trace_lib_common test.priority(10) test.scenarios('vlt_all') +test.fourstate_capable = False trace_lib_common.run(test) diff --git a/test_regress/t/t_trace_lib_default_vcd.py b/test_regress/t/t_trace_lib_default_vcd.py index 5d5e0a225..324dc5bab 100755 --- a/test_regress/t/t_trace_lib_default_vcd.py +++ b/test_regress/t/t_trace_lib_default_vcd.py @@ -12,5 +12,6 @@ import trace_lib_common test.priority(10) test.scenarios('vlt_all') +test.fourstate_capable = False trace_lib_common.run(test) diff --git a/test_regress/t/t_trace_lib_notop_fst.py b/test_regress/t/t_trace_lib_notop_fst.py index 5d5e0a225..324dc5bab 100755 --- a/test_regress/t/t_trace_lib_notop_fst.py +++ b/test_regress/t/t_trace_lib_notop_fst.py @@ -12,5 +12,6 @@ import trace_lib_common test.priority(10) test.scenarios('vlt_all') +test.fourstate_capable = False trace_lib_common.run(test) diff --git a/test_regress/t/t_trace_lib_notop_saif.py b/test_regress/t/t_trace_lib_notop_saif.py index 5d5e0a225..324dc5bab 100755 --- a/test_regress/t/t_trace_lib_notop_saif.py +++ b/test_regress/t/t_trace_lib_notop_saif.py @@ -12,5 +12,6 @@ import trace_lib_common test.priority(10) test.scenarios('vlt_all') +test.fourstate_capable = False trace_lib_common.run(test) diff --git a/test_regress/t/t_trace_lib_notop_vcd.py b/test_regress/t/t_trace_lib_notop_vcd.py index 5d5e0a225..324dc5bab 100755 --- a/test_regress/t/t_trace_lib_notop_vcd.py +++ b/test_regress/t/t_trace_lib_notop_vcd.py @@ -12,5 +12,6 @@ import trace_lib_common test.priority(10) test.scenarios('vlt_all') +test.fourstate_capable = False trace_lib_common.run(test) diff --git a/test_regress/t/t_trace_max.py b/test_regress/t/t_trace_max.py index 8a25e10cb..8d6bc61cc 100755 --- a/test_regress/t/t_trace_max.py +++ b/test_regress/t/t_trace_max.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(verilator_flags2=["--cc --trace-vcd --trace-max-width 64 --trace-max-array 16"]) diff --git a/test_regress/t/t_trace_max_default.py b/test_regress/t/t_trace_max_default.py index 6255dd131..37555ff2c 100755 --- a/test_regress/t/t_trace_max_default.py +++ b/test_regress/t/t_trace_max_default.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_trace_max.v" test.compile(verilator_flags2=["--cc --trace-vcd"]) diff --git a/test_regress/t/t_trace_multi_bad.py b/test_regress/t/t_trace_multi_bad.py index 760ed777e..ebf609db1 100755 --- a/test_regress/t/t_trace_multi_bad.py +++ b/test_regress/t/t_trace_multi_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(verilator_flags2=['--trace-fst --trace-vcd'], fails=True, diff --git a/test_regress/t/t_trace_no_top_name2_fst.py b/test_regress/t/t_trace_no_top_name2_fst.py index 13ac10e86..7b8977fa4 100755 --- a/test_regress/t/t_trace_no_top_name2_fst.py +++ b/test_regress/t/t_trace_no_top_name2_fst.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_no_top_name2_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_no_top_name2_common.run(test) diff --git a/test_regress/t/t_trace_no_top_name_fst.py b/test_regress/t/t_trace_no_top_name_fst.py index 966299507..c5c515895 100755 --- a/test_regress/t/t_trace_no_top_name_fst.py +++ b/test_regress/t/t_trace_no_top_name_fst.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_no_top_name_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_no_top_name_common.run(test) diff --git a/test_regress/t/t_trace_off_sc.py b/test_regress/t/t_trace_off_sc.py index bf674de3e..716110253 100755 --- a/test_regress/t/t_trace_off_sc.py +++ b/test_regress/t/t_trace_off_sc.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_trace_ena.v" test.compile(verilator_flags2=['-notrace -sc']) diff --git a/test_regress/t/t_trace_packed_struct_cc_fst.py b/test_regress/t/t_trace_packed_struct_cc_fst.py index 8146fe41d..e7e05e719 100755 --- a/test_regress/t/t_trace_packed_struct_cc_fst.py +++ b/test_regress/t/t_trace_packed_struct_cc_fst.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_packed_struct_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_packed_struct_common.run(test) diff --git a/test_regress/t/t_trace_packed_struct_cc_saif.py b/test_regress/t/t_trace_packed_struct_cc_saif.py index 8146fe41d..e7e05e719 100755 --- a/test_regress/t/t_trace_packed_struct_cc_saif.py +++ b/test_regress/t/t_trace_packed_struct_cc_saif.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_packed_struct_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_packed_struct_common.run(test) diff --git a/test_regress/t/t_trace_packed_struct_cc_vcd.py b/test_regress/t/t_trace_packed_struct_cc_vcd.py index 8146fe41d..e7e05e719 100755 --- a/test_regress/t/t_trace_packed_struct_cc_vcd.py +++ b/test_regress/t/t_trace_packed_struct_cc_vcd.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_packed_struct_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_packed_struct_common.run(test) diff --git a/test_regress/t/t_trace_packed_struct_sc_fst.py b/test_regress/t/t_trace_packed_struct_sc_fst.py index 8146fe41d..e7e05e719 100755 --- a/test_regress/t/t_trace_packed_struct_sc_fst.py +++ b/test_regress/t/t_trace_packed_struct_sc_fst.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_packed_struct_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_packed_struct_common.run(test) diff --git a/test_regress/t/t_trace_param_fst.py b/test_regress/t/t_trace_param_fst.py index e5e5b7be2..53a89ac33 100755 --- a/test_regress/t/t_trace_param_fst.py +++ b/test_regress/t/t_trace_param_fst.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_param_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_param_common.run(test) diff --git a/test_regress/t/t_trace_primitive_cc_fst.py b/test_regress/t/t_trace_primitive_cc_fst.py index 364e68a7b..c410a972c 100755 --- a/test_regress/t/t_trace_primitive_cc_fst.py +++ b/test_regress/t/t_trace_primitive_cc_fst.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_primitive_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_primitive_common.run(test) diff --git a/test_regress/t/t_trace_primitive_cc_saif.py b/test_regress/t/t_trace_primitive_cc_saif.py index 364e68a7b..c410a972c 100755 --- a/test_regress/t/t_trace_primitive_cc_saif.py +++ b/test_regress/t/t_trace_primitive_cc_saif.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_primitive_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_primitive_common.run(test) diff --git a/test_regress/t/t_trace_primitive_cc_vcd.py b/test_regress/t/t_trace_primitive_cc_vcd.py index 364e68a7b..c410a972c 100755 --- a/test_regress/t/t_trace_primitive_cc_vcd.py +++ b/test_regress/t/t_trace_primitive_cc_vcd.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_primitive_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_primitive_common.run(test) diff --git a/test_regress/t/t_trace_primitive_sc_fst.py b/test_regress/t/t_trace_primitive_sc_fst.py index 364e68a7b..c410a972c 100755 --- a/test_regress/t/t_trace_primitive_sc_fst.py +++ b/test_regress/t/t_trace_primitive_sc_fst.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_primitive_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_primitive_common.run(test) diff --git a/test_regress/t/t_trace_public_func.py b/test_regress/t/t_trace_public_func.py index f830c67ee..74fa9a2ee 100755 --- a/test_regress/t/t_trace_public_func.py +++ b/test_regress/t/t_trace_public_func.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.top_filename = "t/t_trace_public.v" test.golden_filename = "t/t_trace_public.out" diff --git a/test_regress/t/t_trace_public_func_vlt.py b/test_regress/t/t_trace_public_func_vlt.py index d9bb72b4c..35fc02a76 100755 --- a/test_regress/t/t_trace_public_func_vlt.py +++ b/test_regress/t/t_trace_public_func_vlt.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.pli_filename = "t/t_trace_public_func.cpp" test.top_filename = "t/t_trace_public.v" test.golden_filename = "t/t_trace_public.out" diff --git a/test_regress/t/t_trace_public_sig.py b/test_regress/t/t_trace_public_sig.py index 29037763f..e9d4f95be 100755 --- a/test_regress/t/t_trace_public_sig.py +++ b/test_regress/t/t_trace_public_sig.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.top_filename = "t/t_trace_public.v" test.golden_filename = "t/t_trace_public.out" diff --git a/test_regress/t/t_trace_public_sig_vlt.py b/test_regress/t/t_trace_public_sig_vlt.py index 6cdcdb806..26b52b3d1 100755 --- a/test_regress/t/t_trace_public_sig_vlt.py +++ b/test_regress/t/t_trace_public_sig_vlt.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.pli_filename = "t/t_trace_public_sig.cpp" test.top_filename = "t/t_trace_public.v" test.golden_filename = "t/t_trace_public.out" diff --git a/test_regress/t/t_trace_rollover.py b/test_regress/t/t_trace_rollover.py index 41d3402ff..12f29138e 100755 --- a/test_regress/t/t_trace_rollover.py +++ b/test_regress/t/t_trace_rollover.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.top_filename = "t_trace_cat.v" test.compile(make_top_shell=False, diff --git a/test_regress/t/t_trace_sc_empty.py b/test_regress/t/t_trace_sc_empty.py index 54df565ff..52b56492c 100755 --- a/test_regress/t/t_trace_sc_empty.py +++ b/test_regress/t/t_trace_sc_empty.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['-sc', '--trace-vcd']) diff --git a/test_regress/t/t_trace_scope_no_inline.py b/test_regress/t/t_trace_scope_no_inline.py index d0f7105ec..dd10e26fb 100755 --- a/test_regress/t/t_trace_scope_no_inline.py +++ b/test_regress/t/t_trace_scope_no_inline.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(verilator_flags2=["--cc --trace-vcd -fno-inline t/" + test.name + ".vlt"]) diff --git a/test_regress/t/t_trace_scstruct.py b/test_regress/t/t_trace_scstruct.py index dbd69ed8a..b39fe37fc 100755 --- a/test_regress/t/t_trace_scstruct.py +++ b/test_regress/t/t_trace_scstruct.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--sc --trace-vcd --trace-structs --pins-bv 2']) diff --git a/test_regress/t/t_trace_split_struct_fst.py b/test_regress/t/t_trace_split_struct_fst.py index e60e691f2..df578ba5b 100755 --- a/test_regress/t/t_trace_split_struct_fst.py +++ b/test_regress/t/t_trace_split_struct_fst.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_split_struct_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_split_struct_common.run(test) diff --git a/test_regress/t/t_trace_split_struct_saif.py b/test_regress/t/t_trace_split_struct_saif.py index e60e691f2..df578ba5b 100755 --- a/test_regress/t/t_trace_split_struct_saif.py +++ b/test_regress/t/t_trace_split_struct_saif.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_split_struct_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_split_struct_common.run(test) diff --git a/test_regress/t/t_trace_split_struct_vcd.py b/test_regress/t/t_trace_split_struct_vcd.py index e60e691f2..df578ba5b 100755 --- a/test_regress/t/t_trace_split_struct_vcd.py +++ b/test_regress/t/t_trace_split_struct_vcd.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_split_struct_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_split_struct_common.run(test) diff --git a/test_regress/t/t_trace_string.py b/test_regress/t/t_trace_string.py index 31b62b04e..ba2725c77 100755 --- a/test_regress/t/t_trace_string.py +++ b/test_regress/t/t_trace_string.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--cc --trace-vcd']) diff --git a/test_regress/t/t_trace_string_fst.py b/test_regress/t/t_trace_string_fst.py index 4e081fbbf..0c4ef1fd9 100755 --- a/test_regress/t/t_trace_string_fst.py +++ b/test_regress/t/t_trace_string_fst.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_trace_string.v" test.compile(verilator_flags2=['--cc --trace-vcd']) diff --git a/test_regress/t/t_trace_string_fst_sc.py b/test_regress/t/t_trace_string_fst_sc.py index 057c29cfe..07a1f2443 100755 --- a/test_regress/t/t_trace_string_fst_sc.py +++ b/test_regress/t/t_trace_string_fst_sc.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_trace_string.v" if not test.have_sc: diff --git a/test_regress/t/t_trace_struct_alias_fst.py b/test_regress/t/t_trace_struct_alias_fst.py index 3fa9e9bce..ef6849a09 100755 --- a/test_regress/t/t_trace_struct_alias_fst.py +++ b/test_regress/t/t_trace_struct_alias_fst.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_struct_alias_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_struct_alias_common.run(test) diff --git a/test_regress/t/t_trace_struct_alias_vcd.py b/test_regress/t/t_trace_struct_alias_vcd.py index 3fa9e9bce..ef6849a09 100755 --- a/test_regress/t/t_trace_struct_alias_vcd.py +++ b/test_regress/t/t_trace_struct_alias_vcd.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_struct_alias_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_struct_alias_common.run(test) diff --git a/test_regress/t/t_trace_struct_array_multi_inst_cc_fst.py b/test_regress/t/t_trace_struct_array_multi_inst_cc_fst.py index 7e778d937..07375a7b8 100755 --- a/test_regress/t/t_trace_struct_array_multi_inst_cc_fst.py +++ b/test_regress/t/t_trace_struct_array_multi_inst_cc_fst.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_struct_array_multi_inst_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_struct_array_multi_inst_common.run(test) diff --git a/test_regress/t/t_trace_struct_array_multi_inst_cc_saif.py b/test_regress/t/t_trace_struct_array_multi_inst_cc_saif.py index 7e778d937..07375a7b8 100755 --- a/test_regress/t/t_trace_struct_array_multi_inst_cc_saif.py +++ b/test_regress/t/t_trace_struct_array_multi_inst_cc_saif.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_struct_array_multi_inst_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_struct_array_multi_inst_common.run(test) diff --git a/test_regress/t/t_trace_struct_array_multi_inst_cc_vcd.py b/test_regress/t/t_trace_struct_array_multi_inst_cc_vcd.py index 7e778d937..07375a7b8 100755 --- a/test_regress/t/t_trace_struct_array_multi_inst_cc_vcd.py +++ b/test_regress/t/t_trace_struct_array_multi_inst_cc_vcd.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_struct_array_multi_inst_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_struct_array_multi_inst_common.run(test) diff --git a/test_regress/t/t_trace_struct_array_multi_inst_sc_fst.py b/test_regress/t/t_trace_struct_array_multi_inst_sc_fst.py index 7e778d937..07375a7b8 100755 --- a/test_regress/t/t_trace_struct_array_multi_inst_sc_fst.py +++ b/test_regress/t/t_trace_struct_array_multi_inst_sc_fst.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_struct_array_multi_inst_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_struct_array_multi_inst_common.run(test) diff --git a/test_regress/t/t_trace_struct_array_multi_inst_sc_vcd.py b/test_regress/t/t_trace_struct_array_multi_inst_sc_vcd.py index 7e778d937..07375a7b8 100755 --- a/test_regress/t/t_trace_struct_array_multi_inst_sc_vcd.py +++ b/test_regress/t/t_trace_struct_array_multi_inst_sc_vcd.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_struct_array_multi_inst_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_struct_array_multi_inst_common.run(test) diff --git a/test_regress/t/t_trace_timing_fst.py b/test_regress/t/t_trace_timing_fst.py index 0b80fe230..bfa4217f1 100755 --- a/test_regress/t/t_trace_timing_fst.py +++ b/test_regress/t/t_trace_timing_fst.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_timing_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_timing_common.run(test) diff --git a/test_regress/t/t_trace_timing_saif.py b/test_regress/t/t_trace_timing_saif.py index 0b80fe230..bfa4217f1 100755 --- a/test_regress/t/t_trace_timing_saif.py +++ b/test_regress/t/t_trace_timing_saif.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_timing_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_timing_common.run(test) diff --git a/test_regress/t/t_trace_timing_vcd.py b/test_regress/t/t_trace_timing_vcd.py index 0b80fe230..bfa4217f1 100755 --- a/test_regress/t/t_trace_timing_vcd.py +++ b/test_regress/t/t_trace_timing_vcd.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_timing_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_timing_common.run(test) diff --git a/test_regress/t/t_trace_two_dump_cc_fst.py b/test_regress/t/t_trace_two_dump_cc_fst.py index 796e3105c..4eeae4336 100755 --- a/test_regress/t/t_trace_two_dump_cc_fst.py +++ b/test_regress/t/t_trace_two_dump_cc_fst.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_two_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_two_common.run(test) diff --git a/test_regress/t/t_trace_two_dump_cc_saif.py b/test_regress/t/t_trace_two_dump_cc_saif.py index 796e3105c..4eeae4336 100755 --- a/test_regress/t/t_trace_two_dump_cc_saif.py +++ b/test_regress/t/t_trace_two_dump_cc_saif.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_two_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_two_common.run(test) diff --git a/test_regress/t/t_trace_two_dump_cc_vcd.py b/test_regress/t/t_trace_two_dump_cc_vcd.py index 796e3105c..4eeae4336 100755 --- a/test_regress/t/t_trace_two_dump_cc_vcd.py +++ b/test_regress/t/t_trace_two_dump_cc_vcd.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_two_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_two_common.run(test) diff --git a/test_regress/t/t_trace_two_dump_sc_vcd.py b/test_regress/t/t_trace_two_dump_sc_vcd.py index 796e3105c..4eeae4336 100755 --- a/test_regress/t/t_trace_two_dump_sc_vcd.py +++ b/test_regress/t/t_trace_two_dump_sc_vcd.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_two_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_two_common.run(test) diff --git a/test_regress/t/t_trace_two_hdr_cc_fst.py b/test_regress/t/t_trace_two_hdr_cc_fst.py index 796e3105c..4eeae4336 100755 --- a/test_regress/t/t_trace_two_hdr_cc_fst.py +++ b/test_regress/t/t_trace_two_hdr_cc_fst.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_two_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_two_common.run(test) diff --git a/test_regress/t/t_trace_two_hdr_cc_saif.py b/test_regress/t/t_trace_two_hdr_cc_saif.py index 796e3105c..4eeae4336 100755 --- a/test_regress/t/t_trace_two_hdr_cc_saif.py +++ b/test_regress/t/t_trace_two_hdr_cc_saif.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_two_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_two_common.run(test) diff --git a/test_regress/t/t_trace_two_hdr_cc_vcd.py b/test_regress/t/t_trace_two_hdr_cc_vcd.py index 796e3105c..4eeae4336 100755 --- a/test_regress/t/t_trace_two_hdr_cc_vcd.py +++ b/test_regress/t/t_trace_two_hdr_cc_vcd.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_two_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_two_common.run(test) diff --git a/test_regress/t/t_trace_two_hdr_sc_vcd.py b/test_regress/t/t_trace_two_hdr_sc_vcd.py index 796e3105c..4eeae4336 100755 --- a/test_regress/t/t_trace_two_hdr_sc_vcd.py +++ b/test_regress/t/t_trace_two_hdr_sc_vcd.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_two_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_two_common.run(test) diff --git a/test_regress/t/t_trace_two_port_cc_fst.py b/test_regress/t/t_trace_two_port_cc_fst.py index 796e3105c..4eeae4336 100755 --- a/test_regress/t/t_trace_two_port_cc_fst.py +++ b/test_regress/t/t_trace_two_port_cc_fst.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_two_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_two_common.run(test) diff --git a/test_regress/t/t_trace_two_port_cc_saif.py b/test_regress/t/t_trace_two_port_cc_saif.py index 796e3105c..4eeae4336 100755 --- a/test_regress/t/t_trace_two_port_cc_saif.py +++ b/test_regress/t/t_trace_two_port_cc_saif.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_two_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_two_common.run(test) diff --git a/test_regress/t/t_trace_two_port_cc_vcd.py b/test_regress/t/t_trace_two_port_cc_vcd.py index 796e3105c..4eeae4336 100755 --- a/test_regress/t/t_trace_two_port_cc_vcd.py +++ b/test_regress/t/t_trace_two_port_cc_vcd.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_two_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_two_common.run(test) diff --git a/test_regress/t/t_trace_two_port_sc_vcd.py b/test_regress/t/t_trace_two_port_sc_vcd.py index 796e3105c..4eeae4336 100755 --- a/test_regress/t/t_trace_two_port_sc_vcd.py +++ b/test_regress/t/t_trace_two_port_sc_vcd.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_two_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_two_common.run(test) diff --git a/test_regress/t/t_trace_type_alias.py b/test_regress/t/t_trace_type_alias.py index 29345f414..147adaaa5 100755 --- a/test_regress/t/t_trace_type_alias.py +++ b/test_regress/t/t_trace_type_alias.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios("vlt_all") +test.fourstate_capable = False test.compile(v_flags2=["--trace-vcd --trace-structs"]) diff --git a/test_regress/t/t_trace_type_dupes_default_fst.py b/test_regress/t/t_trace_type_dupes_default_fst.py index e2f71b23f..a55da8d02 100755 --- a/test_regress/t/t_trace_type_dupes_default_fst.py +++ b/test_regress/t/t_trace_type_dupes_default_fst.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_type_dupes_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_type_dupes_common.run(test) diff --git a/test_regress/t/t_trace_type_dupes_default_saif.py b/test_regress/t/t_trace_type_dupes_default_saif.py index e2f71b23f..a55da8d02 100755 --- a/test_regress/t/t_trace_type_dupes_default_saif.py +++ b/test_regress/t/t_trace_type_dupes_default_saif.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_type_dupes_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_type_dupes_common.run(test) diff --git a/test_regress/t/t_trace_type_dupes_default_vcd.py b/test_regress/t/t_trace_type_dupes_default_vcd.py index e2f71b23f..a55da8d02 100755 --- a/test_regress/t/t_trace_type_dupes_default_vcd.py +++ b/test_regress/t/t_trace_type_dupes_default_vcd.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_type_dupes_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_type_dupes_common.run(test) diff --git a/test_regress/t/t_trace_type_dupes_structs_fst.py b/test_regress/t/t_trace_type_dupes_structs_fst.py index e2f71b23f..a55da8d02 100755 --- a/test_regress/t/t_trace_type_dupes_structs_fst.py +++ b/test_regress/t/t_trace_type_dupes_structs_fst.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_type_dupes_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_type_dupes_common.run(test) diff --git a/test_regress/t/t_trace_type_dupes_structs_saif.py b/test_regress/t/t_trace_type_dupes_structs_saif.py index e2f71b23f..a55da8d02 100755 --- a/test_regress/t/t_trace_type_dupes_structs_saif.py +++ b/test_regress/t/t_trace_type_dupes_structs_saif.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_type_dupes_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_type_dupes_common.run(test) diff --git a/test_regress/t/t_trace_type_dupes_structs_vcd.py b/test_regress/t/t_trace_type_dupes_structs_vcd.py index e2f71b23f..a55da8d02 100755 --- a/test_regress/t/t_trace_type_dupes_structs_vcd.py +++ b/test_regress/t/t_trace_type_dupes_structs_vcd.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_type_dupes_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_type_dupes_common.run(test) diff --git a/test_regress/t/t_trace_ub_misaligned_address.py b/test_regress/t/t_trace_ub_misaligned_address.py index 4f9e45d45..4123f4c0b 100755 --- a/test_regress/t/t_trace_ub_misaligned_address.py +++ b/test_regress/t/t_trace_ub_misaligned_address.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_trace_ub_misaligned_address.v" test.compile(verilator_flags2=["--binary --trace-vcd", "--runtime-debug"]) diff --git a/test_regress/t/t_trace_var_kind_cc_fst.py b/test_regress/t/t_trace_var_kind_cc_fst.py index 47ead2293..c974a2827 100755 --- a/test_regress/t/t_trace_var_kind_cc_fst.py +++ b/test_regress/t/t_trace_var_kind_cc_fst.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_var_kind_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_var_kind_common.run(test) diff --git a/test_regress/t/t_trace_var_kind_cc_saif.py b/test_regress/t/t_trace_var_kind_cc_saif.py index 47ead2293..c974a2827 100755 --- a/test_regress/t/t_trace_var_kind_cc_saif.py +++ b/test_regress/t/t_trace_var_kind_cc_saif.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_var_kind_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_var_kind_common.run(test) diff --git a/test_regress/t/t_trace_var_kind_cc_vcd.py b/test_regress/t/t_trace_var_kind_cc_vcd.py index 47ead2293..c974a2827 100755 --- a/test_regress/t/t_trace_var_kind_cc_vcd.py +++ b/test_regress/t/t_trace_var_kind_cc_vcd.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_var_kind_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_var_kind_common.run(test) diff --git a/test_regress/t/t_trace_var_kind_sc_fst.py b/test_regress/t/t_trace_var_kind_sc_fst.py index 47ead2293..c974a2827 100755 --- a/test_regress/t/t_trace_var_kind_sc_fst.py +++ b/test_regress/t/t_trace_var_kind_sc_fst.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_var_kind_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_var_kind_common.run(test) diff --git a/test_regress/t/t_trace_var_kind_sc_vcd.py b/test_regress/t/t_trace_var_kind_sc_vcd.py index 47ead2293..c974a2827 100755 --- a/test_regress/t/t_trace_var_kind_sc_vcd.py +++ b/test_regress/t/t_trace_var_kind_sc_vcd.py @@ -11,5 +11,6 @@ import vltest_bootstrap import trace_var_kind_common test.scenarios('vlt_all') +test.fourstate_capable = False trace_var_kind_common.run(test) diff --git a/test_regress/t/t_trace_wide_struct.py b/test_regress/t/t_trace_wide_struct.py index 558b51518..759b5e61d 100755 --- a/test_regress/t/t_trace_wide_struct.py +++ b/test_regress/t/t_trace_wide_struct.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--trace-vcd --trace-structs']) diff --git a/test_regress/t/t_tri_and_eqcase.py b/test_regress/t/t_tri_and_eqcase.py index b7449248c..5f4a1b488 100755 --- a/test_regress/t/t_tri_and_eqcase.py +++ b/test_regress/t/t_tri_and_eqcase.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_tri_array.py b/test_regress/t/t_tri_array.py index 0f7fe1942..c5a6afc19 100755 --- a/test_regress/t/t_tri_array.py +++ b/test_regress/t/t_tri_array.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator_st') +test.fourstate_capable = False test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_tri_array_bufif.py b/test_regress/t/t_tri_array_bufif.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_tri_array_bufif.py +++ b/test_regress/t/t_tri_array_bufif.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_tri_array_pull.py b/test_regress/t/t_tri_array_pull.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_tri_array_pull.py +++ b/test_regress/t/t_tri_array_pull.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_tri_assigndly_nba.py b/test_regress/t/t_tri_assigndly_nba.py index 8a938befd..a10e2547d 100755 --- a/test_regress/t/t_tri_assigndly_nba.py +++ b/test_regress/t/t_tri_assigndly_nba.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_tri_clocking.py b/test_regress/t/t_tri_clocking.py index 84b274f68..17424b42f 100755 --- a/test_regress/t/t_tri_clocking.py +++ b/test_regress/t/t_tri_clocking.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_tri_compass_bad.py b/test_regress/t/t_tri_compass_bad.py index 3160d0589..763d0b4d6 100755 --- a/test_regress/t/t_tri_compass_bad.py +++ b/test_regress/t/t_tri_compass_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_tri_eqcase.py b/test_regress/t/t_tri_eqcase.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_tri_eqcase.py +++ b/test_regress/t/t_tri_eqcase.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_tri_eqcase_input.py b/test_regress/t/t_tri_eqcase_input.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_tri_eqcase_input.py +++ b/test_regress/t/t_tri_eqcase_input.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_tri_gate_bufif0.py b/test_regress/t/t_tri_gate_bufif0.py index 97ee1b367..5b14c8d25 100755 --- a/test_regress/t/t_tri_gate_bufif0.py +++ b/test_regress/t/t_tri_gate_bufif0.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.pli_filename = "t/t_tri_gate.cpp" test.top_filename = "t/t_tri_gate.v" diff --git a/test_regress/t/t_tri_gate_bufif0_pins_inout.py b/test_regress/t/t_tri_gate_bufif0_pins_inout.py index 05e7201b3..4016dcefe 100755 --- a/test_regress/t/t_tri_gate_bufif0_pins_inout.py +++ b/test_regress/t/t_tri_gate_bufif0_pins_inout.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.pli_filename = "t/t_tri_gate.cpp" test.top_filename = "t/t_tri_gate.v" diff --git a/test_regress/t/t_tri_gate_bufif1.py b/test_regress/t/t_tri_gate_bufif1.py index 29127de06..6063900c9 100755 --- a/test_regress/t/t_tri_gate_bufif1.py +++ b/test_regress/t/t_tri_gate_bufif1.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.pli_filename = "t/t_tri_gate.cpp" test.top_filename = "t/t_tri_gate.v" diff --git a/test_regress/t/t_tri_gate_bufif1_pins_inout.py b/test_regress/t/t_tri_gate_bufif1_pins_inout.py index b0e2f3aeb..9ad839e3c 100755 --- a/test_regress/t/t_tri_gate_bufif1_pins_inout.py +++ b/test_regress/t/t_tri_gate_bufif1_pins_inout.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.pli_filename = "t/t_tri_gate.cpp" test.top_filename = "t/t_tri_gate.v" diff --git a/test_regress/t/t_tri_gate_cond.py b/test_regress/t/t_tri_gate_cond.py index 2cfc0ee1a..86a29c613 100755 --- a/test_regress/t/t_tri_gate_cond.py +++ b/test_regress/t/t_tri_gate_cond.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.pli_filename = "t/t_tri_gate.cpp" test.top_filename = "t/t_tri_gate.v" diff --git a/test_regress/t/t_tri_gate_cond_pins_inout.py b/test_regress/t/t_tri_gate_cond_pins_inout.py index 03c32e767..16e469e97 100755 --- a/test_regress/t/t_tri_gate_cond_pins_inout.py +++ b/test_regress/t/t_tri_gate_cond_pins_inout.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.pli_filename = "t/t_tri_gate.cpp" test.top_filename = "t/t_tri_gate.v" diff --git a/test_regress/t/t_tri_gate_nmos.py b/test_regress/t/t_tri_gate_nmos.py index eca8b57d5..d7926afa1 100755 --- a/test_regress/t/t_tri_gate_nmos.py +++ b/test_regress/t/t_tri_gate_nmos.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.pli_filename = "t/t_tri_gate.cpp" test.top_filename = "t/t_tri_gate.v" diff --git a/test_regress/t/t_tri_gate_nmos_pins_inout.py b/test_regress/t/t_tri_gate_nmos_pins_inout.py index 3bb5fd1bf..0634819d4 100755 --- a/test_regress/t/t_tri_gate_nmos_pins_inout.py +++ b/test_regress/t/t_tri_gate_nmos_pins_inout.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.pli_filename = "t/t_tri_gate.cpp" test.top_filename = "t/t_tri_gate.v" diff --git a/test_regress/t/t_tri_gate_notif0.py b/test_regress/t/t_tri_gate_notif0.py index f27090c7e..ccc20197e 100755 --- a/test_regress/t/t_tri_gate_notif0.py +++ b/test_regress/t/t_tri_gate_notif0.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.pli_filename = "t/t_tri_gate.cpp" test.top_filename = "t/t_tri_gate.v" diff --git a/test_regress/t/t_tri_gate_notif0_pins_inout.py b/test_regress/t/t_tri_gate_notif0_pins_inout.py index d06b9a0b6..297d05bf9 100755 --- a/test_regress/t/t_tri_gate_notif0_pins_inout.py +++ b/test_regress/t/t_tri_gate_notif0_pins_inout.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.pli_filename = "t/t_tri_gate.cpp" test.top_filename = "t/t_tri_gate.v" diff --git a/test_regress/t/t_tri_gate_notif1.py b/test_regress/t/t_tri_gate_notif1.py index bc180bf81..3ad8fa726 100755 --- a/test_regress/t/t_tri_gate_notif1.py +++ b/test_regress/t/t_tri_gate_notif1.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.pli_filename = "t/t_tri_gate.cpp" test.top_filename = "t/t_tri_gate.v" diff --git a/test_regress/t/t_tri_gate_notif1_pins_inout.py b/test_regress/t/t_tri_gate_notif1_pins_inout.py index 06c52aa2f..e9f3a52a4 100755 --- a/test_regress/t/t_tri_gate_notif1_pins_inout.py +++ b/test_regress/t/t_tri_gate_notif1_pins_inout.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.pli_filename = "t/t_tri_gate.cpp" test.top_filename = "t/t_tri_gate.v" diff --git a/test_regress/t/t_tri_gate_pmos.py b/test_regress/t/t_tri_gate_pmos.py index 6b26f68ff..e4c079f7f 100755 --- a/test_regress/t/t_tri_gate_pmos.py +++ b/test_regress/t/t_tri_gate_pmos.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.pli_filename = "t/t_tri_gate.cpp" test.top_filename = "t/t_tri_gate.v" diff --git a/test_regress/t/t_tri_gate_pmos_pins_inout.py b/test_regress/t/t_tri_gate_pmos_pins_inout.py index 172127396..823f0f698 100755 --- a/test_regress/t/t_tri_gate_pmos_pins_inout.py +++ b/test_regress/t/t_tri_gate_pmos_pins_inout.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.pli_filename = "t/t_tri_gate.cpp" test.top_filename = "t/t_tri_gate.v" diff --git a/test_regress/t/t_tri_gen.py b/test_regress/t/t_tri_gen.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_tri_gen.py +++ b/test_regress/t/t_tri_gen.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_tri_hier_ref_unsup.py b/test_regress/t/t_tri_hier_ref_unsup.py index a00127d05..37634cf2a 100755 --- a/test_regress/t/t_tri_hier_ref_unsup.py +++ b/test_regress/t/t_tri_hier_ref_unsup.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_tri_iface_port.py b/test_regress/t/t_tri_iface_port.py index 4348f3df1..90dbfb6d4 100755 --- a/test_regress/t/t_tri_iface_port.py +++ b/test_regress/t/t_tri_iface_port.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_tri_iface_semantics.py b/test_regress/t/t_tri_iface_semantics.py index 1ddad07d5..514560607 100755 --- a/test_regress/t/t_tri_iface_semantics.py +++ b/test_regress/t/t_tri_iface_semantics.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=['--timing']) diff --git a/test_regress/t/t_tri_inout.py b/test_regress/t/t_tri_inout.py index c012be81c..ef8972023 100755 --- a/test_regress/t/t_tri_inout.py +++ b/test_regress/t/t_tri_inout.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) diff --git a/test_regress/t/t_tri_inout2.py b/test_regress/t/t_tri_inout2.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_tri_inout2.py +++ b/test_regress/t/t_tri_inout2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_tri_inout_pins_inout.py b/test_regress/t/t_tri_inout_pins_inout.py index 859c1b9f4..a7f2270a9 100755 --- a/test_regress/t/t_tri_inout_pins_inout.py +++ b/test_regress/t/t_tri_inout_pins_inout.py @@ -12,6 +12,7 @@ import vltest_bootstrap test.top_filename = "t/t_tri_inout.v" test.scenarios('vlt_all') +test.fourstate_capable = False test.pli_filename = "t/t_tri_inout.cpp" test.compile(make_top_shell=False, diff --git a/test_regress/t/t_tri_inz.py b/test_regress/t/t_tri_inz.py index c012be81c..ef8972023 100755 --- a/test_regress/t/t_tri_inz.py +++ b/test_regress/t/t_tri_inz.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) diff --git a/test_regress/t/t_tri_no_top.py b/test_regress/t/t_tri_no_top.py index 301be6869..f1039d5ac 100755 --- a/test_regress/t/t_tri_no_top.py +++ b/test_regress/t/t_tri_no_top.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile( make_top_shell=False, diff --git a/test_regress/t/t_tri_pull01.py b/test_regress/t/t_tri_pull01.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_tri_pull01.py +++ b/test_regress/t/t_tri_pull01.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_tri_pull2_bad.py b/test_regress/t/t_tri_pull2_bad.py index 1952b53a1..873d22c46 100755 --- a/test_regress/t/t_tri_pull2_bad.py +++ b/test_regress/t/t_tri_pull2_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_tri_pull_bad.py b/test_regress/t/t_tri_pull_bad.py index 1952b53a1..873d22c46 100755 --- a/test_regress/t/t_tri_pull_bad.py +++ b/test_regress/t/t_tri_pull_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_tri_pull_implicit.py b/test_regress/t/t_tri_pull_implicit.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_tri_pull_implicit.py +++ b/test_regress/t/t_tri_pull_implicit.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_tri_pullup.py b/test_regress/t/t_tri_pullup.py index c012be81c..ef8972023 100755 --- a/test_regress/t/t_tri_pullup.py +++ b/test_regress/t/t_tri_pullup.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) diff --git a/test_regress/t/t_tri_pullup_bus.py b/test_regress/t/t_tri_pullup_bus.py index 862dfe8e1..4d760c759 100755 --- a/test_regress/t/t_tri_pullup_bus.py +++ b/test_regress/t/t_tri_pullup_bus.py @@ -7,6 +7,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=['--timing']) diff --git a/test_regress/t/t_tri_pullup_pins_inout.py b/test_regress/t/t_tri_pullup_pins_inout.py index f9f977fff..035813339 100755 --- a/test_regress/t/t_tri_pullup_pins_inout.py +++ b/test_regress/t/t_tri_pullup_pins_inout.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.pli_filename = "t/t_tri_pullup.cpp" test.top_filename = "t/t_tri_pullup.v" diff --git a/test_regress/t/t_tri_pullvec_bad.py b/test_regress/t/t_tri_pullvec_bad.py index b7449248c..5f4a1b488 100755 --- a/test_regress/t/t_tri_pullvec_bad.py +++ b/test_regress/t/t_tri_pullvec_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_tri_select.py b/test_regress/t/t_tri_select.py index c012be81c..ef8972023 100755 --- a/test_regress/t/t_tri_select.py +++ b/test_regress/t/t_tri_select.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) diff --git a/test_regress/t/t_tri_select_pins_inout.py b/test_regress/t/t_tri_select_pins_inout.py index 0865258ca..cb317f2d1 100755 --- a/test_regress/t/t_tri_select_pins_inout.py +++ b/test_regress/t/t_tri_select_pins_inout.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.pli_filename = "t/t_tri_select.cpp" test.top_filename = "t/t_tri_select.v" diff --git a/test_regress/t/t_tri_struct_packed.py b/test_regress/t/t_tri_struct_packed.py index 6a295cd2f..53d9067b2 100755 --- a/test_regress/t/t_tri_struct_packed.py +++ b/test_regress/t/t_tri_struct_packed.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary']) diff --git a/test_regress/t/t_tri_top_en_out.py b/test_regress/t/t_tri_top_en_out.py index 50bd0ba46..bc5384f42 100755 --- a/test_regress/t/t_tri_top_en_out.py +++ b/test_regress/t/t_tri_top_en_out.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(make_top_shell=False, make_main=False, diff --git a/test_regress/t/t_tri_top_en_out_bad.py b/test_regress/t/t_tri_top_en_out_bad.py index f5fd8e225..9b5775057 100755 --- a/test_regress/t/t_tri_top_en_out_bad.py +++ b/test_regress/t/t_tri_top_en_out_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(make_top_shell=False, make_main=1, diff --git a/test_regress/t/t_tri_unconn.py b/test_regress/t/t_tri_unconn.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_tri_unconn.py +++ b/test_regress/t/t_tri_unconn.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_tri_various.py b/test_regress/t/t_tri_various.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_tri_various.py +++ b/test_regress/t/t_tri_various.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_type_match.py b/test_regress/t/t_type_match.py index 30ee5e479..1f8a21994 100755 --- a/test_regress/t/t_type_match.py +++ b/test_regress/t/t_type_match.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["-Wno-UNOPTFLAT"]) diff --git a/test_regress/t/t_typedef.py b/test_regress/t/t_typedef.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_typedef.py +++ b/test_regress/t/t_typedef.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_typedef_array.py b/test_regress/t/t_typedef_array.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_typedef_array.py +++ b/test_regress/t/t_typedef_array.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_typedef_fwd.py b/test_regress/t/t_typedef_fwd.py index d6d35e7fd..485ded93c 100755 --- a/test_regress/t/t_typedef_fwd.py +++ b/test_regress/t/t_typedef_fwd.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint() diff --git a/test_regress/t/t_typedef_iface_typedef.py b/test_regress/t/t_typedef_iface_typedef.py index 31b1f0e53..9da272f7d 100755 --- a/test_regress/t/t_typedef_iface_typedef.py +++ b/test_regress/t/t_typedef_iface_typedef.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_typedef_iface_typedef3.py b/test_regress/t/t_typedef_iface_typedef3.py index 31b1f0e53..9da272f7d 100755 --- a/test_regress/t/t_typedef_iface_typedef3.py +++ b/test_regress/t/t_typedef_iface_typedef3.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_typedef_iface_typedef4.py b/test_regress/t/t_typedef_iface_typedef4.py index 31b1f0e53..9da272f7d 100755 --- a/test_regress/t/t_typedef_iface_typedef4.py +++ b/test_regress/t/t_typedef_iface_typedef4.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_typedef_iface_typedef5.py b/test_regress/t/t_typedef_iface_typedef5.py index 31b1f0e53..9da272f7d 100755 --- a/test_regress/t/t_typedef_iface_typedef5.py +++ b/test_regress/t/t_typedef_iface_typedef5.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_typedef_iface_typedef6.py b/test_regress/t/t_typedef_iface_typedef6.py index 31b1f0e53..9da272f7d 100755 --- a/test_regress/t/t_typedef_iface_typedef6.py +++ b/test_regress/t/t_typedef_iface_typedef6.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_typedef_iface_typedef7.py b/test_regress/t/t_typedef_iface_typedef7.py index 31b1f0e53..9da272f7d 100755 --- a/test_regress/t/t_typedef_iface_typedef7.py +++ b/test_regress/t/t_typedef_iface_typedef7.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_typedef_signed.py b/test_regress/t/t_typedef_signed.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_typedef_signed.py +++ b/test_regress/t/t_typedef_signed.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_udp_sequential_x.py b/test_regress/t/t_udp_sequential_x.py index f3e251121..11c18a019 100755 --- a/test_regress/t/t_udp_sequential_x.py +++ b/test_regress/t/t_udp_sequential_x.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.compile(verilator_flags2=["--x-assign", "1"]) diff --git a/test_regress/t/t_unbounded.py b/test_regress/t/t_unbounded.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_unbounded.py +++ b/test_regress/t/t_unbounded.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_unconnected.py b/test_regress/t/t_unconnected.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_unconnected.py +++ b/test_regress/t/t_unconnected.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_uniqueif.py b/test_regress/t/t_uniqueif.py index cae36a498..f79d4bbfe 100755 --- a/test_regress/t/t_uniqueif.py +++ b/test_regress/t/t_uniqueif.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--assert'], nc_flags2=['+assert']) diff --git a/test_regress/t/t_uniqueif_else.py b/test_regress/t/t_uniqueif_else.py index 4caa0e109..2726fcb53 100755 --- a/test_regress/t/t_uniqueif_else.py +++ b/test_regress/t/t_uniqueif_else.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator_st') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary']) diff --git a/test_regress/t/t_uniqueif_fail1.py b/test_regress/t/t_uniqueif_fail1.py index 53445c3da..33b2fe206 100755 --- a/test_regress/t/t_uniqueif_fail1.py +++ b/test_regress/t/t_uniqueif_fail1.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_uniqueif.v" test.compile(v_flags2=['+define+FAILING_ASSERTION1'], diff --git a/test_regress/t/t_uniqueif_fail2.py b/test_regress/t/t_uniqueif_fail2.py index d0e23fcfa..aa01edf9f 100755 --- a/test_regress/t/t_uniqueif_fail2.py +++ b/test_regress/t/t_uniqueif_fail2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_uniqueif.v" test.compile(v_flags2=['+define+FAILING_ASSERTION2'], diff --git a/test_regress/t/t_uniqueif_fail3.py b/test_regress/t/t_uniqueif_fail3.py index 0442aefd9..84089ad93 100755 --- a/test_regress/t/t_uniqueif_fail3.py +++ b/test_regress/t/t_uniqueif_fail3.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_uniqueif.v" test.compile(v_flags2=['+define+FAILING_ASSERTION3'], diff --git a/test_regress/t/t_uniqueif_fail4.py b/test_regress/t/t_uniqueif_fail4.py index 787d96e16..899ba8faa 100755 --- a/test_regress/t/t_uniqueif_fail4.py +++ b/test_regress/t/t_uniqueif_fail4.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_uniqueif.v" test.compile(v_flags2=['+define+FAILING_ASSERTION4'], diff --git a/test_regress/t/t_unopt_array.py b/test_regress/t/t_unopt_array.py index 0bed5b40c..54100b4eb 100755 --- a/test_regress/t/t_unopt_array.py +++ b/test_regress/t/t_unopt_array.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["-Wno-UNOPTFLAT", "-fno-dfg"]) diff --git a/test_regress/t/t_unopt_array_csplit.py b/test_regress/t/t_unopt_array_csplit.py index 5de52004f..3cf3d74af 100755 --- a/test_regress/t/t_unopt_array_csplit.py +++ b/test_regress/t/t_unopt_array_csplit.py @@ -11,6 +11,7 @@ import vltest_bootstrap test.priority(30) test.scenarios('vlt_all') +test.fourstate_capable = False test.top_filename = "t/t_unopt_array.v" test.compile(v_flags2=[ diff --git a/test_regress/t/t_unopt_array_typedef.py b/test_regress/t/t_unopt_array_typedef.py index 58c78ca86..ebe723083 100755 --- a/test_regress/t/t_unopt_array_typedef.py +++ b/test_regress/t/t_unopt_array_typedef.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_unopt_array.v" test.compile(verilator_flags2=["-Wno-UNOPTFLAT", "+define+USE_TYPEDEF", "-fno-dfg"]) diff --git a/test_regress/t/t_unopt_bound.py b/test_regress/t/t_unopt_bound.py index c02254607..01260b3a4 100755 --- a/test_regress/t/t_unopt_bound.py +++ b/test_regress/t/t_unopt_bound.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["-fno-dfg"]) diff --git a/test_regress/t/t_unopt_combo.py b/test_regress/t/t_unopt_combo.py index b576750b6..ecb982bb9 100755 --- a/test_regress/t/t_unopt_combo.py +++ b/test_regress/t/t_unopt_combo.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(v_flags2=['+define+ALLOW_UNOPT', "-fno-dfg"]) diff --git a/test_regress/t/t_unopt_combo_bad.py b/test_regress/t/t_unopt_combo_bad.py index d863f5a00..2db86cf02 100755 --- a/test_regress/t/t_unopt_combo_bad.py +++ b/test_regress/t/t_unopt_combo_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_unopt_combo.v" test.compile(v_flags2=['+define+ATTRIBUTES', "-fno-dfg"], diff --git a/test_regress/t/t_unopt_combo_isolate.py b/test_regress/t/t_unopt_combo_isolate.py index 3ffd80545..1033de904 100755 --- a/test_regress/t/t_unopt_combo_isolate.py +++ b/test_regress/t/t_unopt_combo_isolate.py @@ -14,6 +14,7 @@ import vltest_bootstrap # in SystemVerilog and Verilator control files for backward compatibility. test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_unopt_combo.v" test.compile(verilator_flags2=["+define+ISOLATE"]) diff --git a/test_regress/t/t_unopt_combo_isolate_vlt.py b/test_regress/t/t_unopt_combo_isolate_vlt.py index 1a041dac0..fa5ed527c 100755 --- a/test_regress/t/t_unopt_combo_isolate_vlt.py +++ b/test_regress/t/t_unopt_combo_isolate_vlt.py @@ -14,6 +14,7 @@ import vltest_bootstrap # in SystemVerilog and Verilator control files for backward compatibility. test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_unopt_combo.v" test.compile(verilator_flags2=[test.t_dir + "/t_unopt_combo_isolate.vlt"]) diff --git a/test_regress/t/t_unopt_combo_waive.py b/test_regress/t/t_unopt_combo_waive.py index c4824f4df..09b255eb5 100755 --- a/test_regress/t/t_unopt_combo_waive.py +++ b/test_regress/t/t_unopt_combo_waive.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.top_filename = "t/t_unopt_combo.v" test.compile(v_flags2=['+define+ATTRIBUTES', "t/t_unopt_combo.vlt", "-fno-dfg"], diff --git a/test_regress/t/t_unopt_converge_initial_run_bad.py b/test_regress/t/t_unopt_converge_initial_run_bad.py index f6be1d6bb..c48c7c460 100755 --- a/test_regress/t/t_unopt_converge_initial_run_bad.py +++ b/test_regress/t/t_unopt_converge_initial_run_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_unopt_converge_initial.v" test.compile(v_flags2=['+define+ALLOW_UNOPT', '--output-split 0', "-fno-dfg"]) diff --git a/test_regress/t/t_unopt_converge_ndbg_bad.py b/test_regress/t/t_unopt_converge_ndbg_bad.py index e5807fe72..a371b7c16 100755 --- a/test_regress/t/t_unopt_converge_ndbg_bad.py +++ b/test_regress/t/t_unopt_converge_ndbg_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_unopt_converge.v" test.compile(v_flags2=['+define+ALLOW_UNOPT', "-fno-dfg"], make_flags=['CPPFLAGS_ADD=-UVL_DEBUG']) diff --git a/test_regress/t/t_unopt_converge_print_bad.py b/test_regress/t/t_unopt_converge_print_bad.py index 155d7dc95..0fef6622f 100755 --- a/test_regress/t/t_unopt_converge_print_bad.py +++ b/test_regress/t/t_unopt_converge_print_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_unopt_converge.v" #test.verilated_debug = 1 diff --git a/test_regress/t/t_unopt_converge_run_bad.py b/test_regress/t/t_unopt_converge_run_bad.py index 367ecb192..7246cacdf 100755 --- a/test_regress/t/t_unopt_converge_run_bad.py +++ b/test_regress/t/t_unopt_converge_run_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_unopt_converge.v" test.compile( diff --git a/test_regress/t/t_unoptflat_simple_2_bad.py b/test_regress/t/t_unoptflat_simple_2_bad.py index 43b3725ee..6e8d6d632 100755 --- a/test_regress/t/t_unoptflat_simple_2_bad.py +++ b/test_regress/t/t_unoptflat_simple_2_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_unoptflat_simple_2.v" # Compile only diff --git a/test_regress/t/t_unoptflat_simple_3_bad.py b/test_regress/t/t_unoptflat_simple_3_bad.py index 0ad46840f..550eedfb8 100755 --- a/test_regress/t/t_unoptflat_simple_3_bad.py +++ b/test_regress/t/t_unoptflat_simple_3_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_unoptflat_simple_3.v" # Compile only diff --git a/test_regress/t/t_unoptflat_simple_bad.py b/test_regress/t/t_unoptflat_simple_bad.py index 3e1c35038..6b5ff480b 100755 --- a/test_regress/t/t_unoptflat_simple_bad.py +++ b/test_regress/t/t_unoptflat_simple_bad.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_unoptflat_simple.v" # Compile only diff --git a/test_regress/t/t_unpack_array_direct_assignment.py b/test_regress/t/t_unpack_array_direct_assignment.py index f290b6a69..a0045d0ba 100755 --- a/test_regress/t/t_unpack_array_direct_assignment.py +++ b/test_regress/t/t_unpack_array_direct_assignment.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_unpack_array_no_expand.v" test.compile(verilator_flags2=['-fno-expand']) diff --git a/test_regress/t/t_unpack_array_no_expand.py b/test_regress/t/t_unpack_array_no_expand.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_unpack_array_no_expand.py +++ b/test_regress/t/t_unpack_array_no_expand.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_unpacked_array_order.py b/test_regress/t/t_unpacked_array_order.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_unpacked_array_order.py +++ b/test_regress/t/t_unpacked_array_order.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_unpacked_array_p_fmt.py b/test_regress/t/t_unpacked_array_p_fmt.py index ed8db10e9..8aeecc749 100755 --- a/test_regress/t/t_unpacked_array_p_fmt.py +++ b/test_regress/t/t_unpacked_array_p_fmt.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_unpacked_concat.py b/test_regress/t/t_unpacked_concat.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_unpacked_concat.py +++ b/test_regress/t/t_unpacked_concat.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_unpacked_concat_bad2.py b/test_regress/t/t_unpacked_concat_bad2.py index 3160d0589..763d0b4d6 100755 --- a/test_regress/t/t_unpacked_concat_bad2.py +++ b/test_regress/t/t_unpacked_concat_bad2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_unpacked_str_init.py b/test_regress/t/t_unpacked_str_init.py index 5e011058b..02bcf88cc 100755 --- a/test_regress/t/t_unpacked_str_init.py +++ b/test_regress/t/t_unpacked_str_init.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_unpacked_str_init2.py b/test_regress/t/t_unpacked_str_init2.py index ed8db10e9..8aeecc749 100755 --- a/test_regress/t/t_unpacked_str_init2.py +++ b/test_regress/t/t_unpacked_str_init2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_unpacked_to_packed_param.py b/test_regress/t/t_unpacked_to_packed_param.py index db898a84c..157ea8892 100755 --- a/test_regress/t/t_unpacked_to_packed_param.py +++ b/test_regress/t/t_unpacked_to_packed_param.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios("vlt") +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_unpacked_to_queue.py b/test_regress/t/t_unpacked_to_queue.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_unpacked_to_queue.py +++ b/test_regress/t/t_unpacked_to_queue.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_unpacked_wide_unknown.py b/test_regress/t/t_unpacked_wide_unknown.py index 4ee7f9e14..64d4ecb78 100755 --- a/test_regress/t/t_unpacked_wide_unknown.py +++ b/test_regress/t/t_unpacked_wide_unknown.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary']) diff --git a/test_regress/t/t_unroll_complexcond.py b/test_regress/t/t_unroll_complexcond.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_unroll_complexcond.py +++ b/test_regress/t/t_unroll_complexcond.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_unroll_forfor.py b/test_regress/t/t_unroll_forfor.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_unroll_forfor.py +++ b/test_regress/t/t_unroll_forfor.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_unroll_signed.py b/test_regress/t/t_unroll_signed.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_unroll_signed.py +++ b/test_regress/t/t_unroll_signed.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_unroll_unopt_io.py b/test_regress/t/t_unroll_unopt_io.py index 13b7a55a0..0ebece521 100755 --- a/test_regress/t/t_unroll_unopt_io.py +++ b/test_regress/t/t_unroll_unopt_io.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--x-assign fast']) diff --git a/test_regress/t/t_user_type_xassign.py b/test_regress/t/t_user_type_xassign.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_user_type_xassign.py +++ b/test_regress/t/t_user_type_xassign.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_uvm_dpi_v2017_1_0.py b/test_regress/t/t_uvm_dpi_v2017_1_0.py index d0e1795d2..3e3eee73d 100755 --- a/test_regress/t/t_uvm_dpi_v2017_1_0.py +++ b/test_regress/t/t_uvm_dpi_v2017_1_0.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_uvm_dpi.v" test.pli_filename = "t/uvm/v2017_1_0/dpi/uvm_dpi.cc" diff --git a/test_regress/t/t_uvm_dpi_v2020_3_1.py b/test_regress/t/t_uvm_dpi_v2020_3_1.py index 7c3039b30..599eacd3f 100755 --- a/test_regress/t/t_uvm_dpi_v2020_3_1.py +++ b/test_regress/t/t_uvm_dpi_v2020_3_1.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_uvm_dpi.v" test.pli_filename = "t/uvm/v2020_3_1/dpi/uvm_dpi.cc" diff --git a/test_regress/t/t_uvm_hello_all_v2017_1_0_dpi.py b/test_regress/t/t_uvm_hello_all_v2017_1_0_dpi.py index 300bc7c0a..6c6b93959 100755 --- a/test_regress/t/t_uvm_hello_all_v2017_1_0_dpi.py +++ b/test_regress/t/t_uvm_hello_all_v2017_1_0_dpi.py @@ -11,6 +11,7 @@ import vltest_bootstrap test.priority(50) test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = 't/t_uvm_hello.v' test.pli_filename = "t/uvm/v2017_1_0/dpi/uvm_dpi.cc" diff --git a/test_regress/t/t_uvm_hello_all_v2017_1_0_nodpi.py b/test_regress/t/t_uvm_hello_all_v2017_1_0_nodpi.py index 359dc7ef8..dc40e18fb 100755 --- a/test_regress/t/t_uvm_hello_all_v2017_1_0_nodpi.py +++ b/test_regress/t/t_uvm_hello_all_v2017_1_0_nodpi.py @@ -11,6 +11,7 @@ import vltest_bootstrap test.priority(50) test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = 't/t_uvm_hello.v' if test.have_dev_gcov: diff --git a/test_regress/t/t_uvm_hello_all_v2020_3_1_dpi.py b/test_regress/t/t_uvm_hello_all_v2020_3_1_dpi.py index 4da9b7de7..7474e2e68 100755 --- a/test_regress/t/t_uvm_hello_all_v2020_3_1_dpi.py +++ b/test_regress/t/t_uvm_hello_all_v2020_3_1_dpi.py @@ -11,6 +11,7 @@ import vltest_bootstrap test.priority(50) test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = 't/t_uvm_hello.v' test.pli_filename = "t/uvm/v2020_3_1/dpi/uvm_dpi.cc" diff --git a/test_regress/t/t_uvm_hello_all_v2020_3_1_nodpi.py b/test_regress/t/t_uvm_hello_all_v2020_3_1_nodpi.py index c4b2139ce..b58f5b75d 100755 --- a/test_regress/t/t_uvm_hello_all_v2020_3_1_nodpi.py +++ b/test_regress/t/t_uvm_hello_all_v2020_3_1_nodpi.py @@ -11,6 +11,7 @@ import vltest_bootstrap test.priority(50) test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = 't/t_uvm_hello.v' if test.have_dev_gcov: diff --git a/test_regress/t/t_uvm_typeof_type.py b/test_regress/t/t_uvm_typeof_type.py index 6fe7d000c..c0f838642 100755 --- a/test_regress/t/t_uvm_typeof_type.py +++ b/test_regress/t/t_uvm_typeof_type.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary"]) diff --git a/test_regress/t/t_vams_wreal.py b/test_regress/t/t_vams_wreal.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_vams_wreal.py +++ b/test_regress/t/t_vams_wreal.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_var_assign_landr.py b/test_regress/t/t_var_assign_landr.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_var_assign_landr.py +++ b/test_regress/t/t_var_assign_landr.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_var_assign_landr_noexpand.py b/test_regress/t/t_var_assign_landr_noexpand.py index 9f5c9af04..b4830bad9 100755 --- a/test_regress/t/t_var_assign_landr_noexpand.py +++ b/test_regress/t/t_var_assign_landr_noexpand.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_var_assign_landr.v" test.compile(verilator_flags2=['-fno-expand']) diff --git a/test_regress/t/t_var_dotted1_inl0.py b/test_regress/t/t_var_dotted1_inl0.py index 604bcb233..56d8b1405 100755 --- a/test_regress/t/t_var_dotted1_inl0.py +++ b/test_regress/t/t_var_dotted1_inl0.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_var_dotted1.v" test.compile(v_flags2=['+define+NOUSE_INLINE']) diff --git a/test_regress/t/t_var_dotted1_inl1.py b/test_regress/t/t_var_dotted1_inl1.py index b27436339..944b14a9e 100755 --- a/test_regress/t/t_var_dotted1_inl1.py +++ b/test_regress/t/t_var_dotted1_inl1.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_var_dotted1.v" test.compile(v_flags2=['+define+USE_INLINE']) diff --git a/test_regress/t/t_var_dotted1_inl2.py b/test_regress/t/t_var_dotted1_inl2.py index 4608951b0..e29d54943 100755 --- a/test_regress/t/t_var_dotted1_inl2.py +++ b/test_regress/t/t_var_dotted1_inl2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_var_dotted1.v" test.compile(v_flags2=['+define+USE_INLINE_MID']) diff --git a/test_regress/t/t_var_dotted2_inl0.py b/test_regress/t/t_var_dotted2_inl0.py index cdd88b557..2ffbfb43e 100755 --- a/test_regress/t/t_var_dotted2_inl0.py +++ b/test_regress/t/t_var_dotted2_inl0.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_var_dotted2.v" test.compile(v_flags2=['+define+NOUSE_INLINE']) diff --git a/test_regress/t/t_var_dotted2_inl1.py b/test_regress/t/t_var_dotted2_inl1.py index 8d800dcde..693ee941b 100755 --- a/test_regress/t/t_var_dotted2_inl1.py +++ b/test_regress/t/t_var_dotted2_inl1.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_var_dotted2.v" test.compile(v_flags2=['+define+USE_INLINE']) diff --git a/test_regress/t/t_var_escape_noinl.py b/test_regress/t/t_var_escape_noinl.py index 4bb346b5d..c1b2dccee 100755 --- a/test_regress/t/t_var_escape_noinl.py +++ b/test_regress/t/t_var_escape_noinl.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_var_escape.v" test.golden_filename = "t/t_var_escape.out" diff --git a/test_regress/t/t_var_init_static_automatic.py b/test_regress/t/t_var_init_static_automatic.py index f090e5249..6b31d5fc7 100755 --- a/test_regress/t/t_var_init_static_automatic.py +++ b/test_regress/t/t_var_init_static_automatic.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--timing']) diff --git a/test_regress/t/t_var_nonamebegin.py b/test_regress/t/t_var_nonamebegin.py index 6f6a0cc62..d4efd95a8 100755 --- a/test_regress/t/t_var_nonamebegin.py +++ b/test_regress/t/t_var_nonamebegin.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['-trace']) diff --git a/test_regress/t/t_var_overzero.py b/test_regress/t/t_var_overzero.py index e7be559d1..7f262cc47 100755 --- a/test_regress/t/t_var_overzero.py +++ b/test_regress/t/t_var_overzero.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--x-initial fast"]) diff --git a/test_regress/t/t_var_pins_array_assign.py b/test_regress/t/t_var_pins_array_assign.py index 8a938befd..a10e2547d 100755 --- a/test_regress/t/t_var_pins_array_assign.py +++ b/test_regress/t/t_var_pins_array_assign.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_var_pins_cc.py b/test_regress/t/t_var_pins_cc.py index a9e8f9786..6bbdd074d 100755 --- a/test_regress/t/t_var_pins_cc.py +++ b/test_regress/t/t_var_pins_cc.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_var_pinsizes.v" test.compile(verilator_flags2=['-cc'], diff --git a/test_regress/t/t_var_pins_sc1.py b/test_regress/t/t_var_pins_sc1.py index 157e2b2ff..e5a95cd16 100755 --- a/test_regress/t/t_var_pins_sc1.py +++ b/test_regress/t/t_var_pins_sc1.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.pli_filename = "t/t_var_pinsizes.cpp" test.top_filename = "t/t_var_pinsizes.v" diff --git a/test_regress/t/t_var_pins_sc2.py b/test_regress/t/t_var_pins_sc2.py index 4339e6c27..31bcc65d5 100755 --- a/test_regress/t/t_var_pins_sc2.py +++ b/test_regress/t/t_var_pins_sc2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.pli_filename = "t/t_var_pinsizes.cpp" test.top_filename = "t/t_var_pinsizes.v" diff --git a/test_regress/t/t_var_pins_sc32.py b/test_regress/t/t_var_pins_sc32.py index 3b2cccd0c..a2d880be1 100755 --- a/test_regress/t/t_var_pins_sc32.py +++ b/test_regress/t/t_var_pins_sc32.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.pli_filename = "t/t_var_pinsizes.cpp" test.top_filename = "t/t_var_pinsizes.v" diff --git a/test_regress/t/t_var_pins_sc64.py b/test_regress/t/t_var_pins_sc64.py index a97c4a284..b12153103 100755 --- a/test_regress/t/t_var_pins_sc64.py +++ b/test_regress/t/t_var_pins_sc64.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.pli_filename = "t/t_var_pinsizes.cpp" test.top_filename = "t/t_var_pinsizes.v" diff --git a/test_regress/t/t_var_pins_sc_biguint.py b/test_regress/t/t_var_pins_sc_biguint.py index 5852501c4..dbf140e2b 100755 --- a/test_regress/t/t_var_pins_sc_biguint.py +++ b/test_regress/t/t_var_pins_sc_biguint.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.pli_filename = "t/t_var_pinsizes.cpp" test.top_filename = "t/t_var_pinsizes.v" diff --git a/test_regress/t/t_var_pins_sc_uint.py b/test_regress/t/t_var_pins_sc_uint.py index 3aa6428f9..9fd806afb 100755 --- a/test_regress/t/t_var_pins_sc_uint.py +++ b/test_regress/t/t_var_pins_sc_uint.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.pli_filename = "t/t_var_pinsizes.cpp" test.top_filename = "t/t_var_pinsizes.v" diff --git a/test_regress/t/t_var_pins_sc_uint_biguint.py b/test_regress/t/t_var_pins_sc_uint_biguint.py index 7049f7321..d09b3d638 100755 --- a/test_regress/t/t_var_pins_sc_uint_biguint.py +++ b/test_regress/t/t_var_pins_sc_uint_biguint.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.pli_filename = "t/t_var_pinsizes.cpp" test.top_filename = "t/t_var_pinsizes.v" diff --git a/test_regress/t/t_var_pins_sc_uint_bool.py b/test_regress/t/t_var_pins_sc_uint_bool.py index 8050f1ed3..e8fda5de9 100755 --- a/test_regress/t/t_var_pins_sc_uint_bool.py +++ b/test_regress/t/t_var_pins_sc_uint_bool.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.pli_filename = "t/t_var_pinsizes.cpp" test.top_filename = "t/t_var_pinsizes.v" diff --git a/test_regress/t/t_var_pins_sc_uint_bool_nomain.py b/test_regress/t/t_var_pins_sc_uint_bool_nomain.py index efc72b6c1..acc8fe5e1 100755 --- a/test_regress/t/t_var_pins_sc_uint_bool_nomain.py +++ b/test_regress/t/t_var_pins_sc_uint_bool_nomain.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.top_filename = "t/t_a1_first_cc.v" test.compile(verilator_flags2=["-sc --trace-vcd --pins-sc-uint-bool"]) diff --git a/test_regress/t/t_var_pins_scui.py b/test_regress/t/t_var_pins_scui.py index f9e3634e5..631b840d5 100755 --- a/test_regress/t/t_var_pins_scui.py +++ b/test_regress/t/t_var_pins_scui.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.pli_filename = "t/t_var_pinsizes.cpp" test.top_filename = "t/t_var_pinsizes.v" diff --git a/test_regress/t/t_var_port_json_only.out b/test_regress/t/t_var_port_json_only.out index cdd5447dc..97a83a624 100644 --- a/test_regress/t/t_var_port_json_only.out +++ b/test_regress/t/t_var_port_json_only.out @@ -2,68 +2,68 @@ "modulesp": [ {"type":"MODULE","name":"mh2","addr":"(E)","loc":"d,18:8,18:11","origName":"mh2","verilogName":"mh2","level":1,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"x_inout_wire_integer","addr":"(F)","loc":"d,18:27,18:47","dtypep":"(G)","origName":"x_inout_wire_integer","verilogName":"x_inout_wire_integer","isPrimaryIO":true,"direction":"INOUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"integer","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} + {"type":"VAR","name":"x_inout_wire_integer","addr":"(F)","loc":"d,18:27,18:47","dtypep":"(G)","origName":"x_inout_wire_integer","verilogName":"x_inout_wire_integer","isPrimaryIO":true,"direction":"INOUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"integer","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ]}, {"type":"MODULE","name":"mh5","addr":"(H)","loc":"d,24:8,24:11","origName":"mh5","verilogName":"mh5","level":1,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"x_input_wire_logic","addr":"(I)","loc":"d,24:19,24:37","dtypep":"(J)","origName":"x_input_wire_logic","verilogName":"x_input_wire_logic","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} + {"type":"VAR","name":"x_input_wire_logic","addr":"(I)","loc":"d,24:19,24:37","dtypep":"(J)","origName":"x_input_wire_logic","verilogName":"x_input_wire_logic","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ]}, {"type":"MODULE","name":"mh6","addr":"(K)","loc":"d,26:8,26:11","origName":"mh6","verilogName":"mh6","level":1,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"x_input_var_logic","addr":"(L)","loc":"d,26:23,26:40","dtypep":"(J)","origName":"x_input_var_logic","verilogName":"x_input_var_logic","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} + {"type":"VAR","name":"x_input_var_logic","addr":"(L)","loc":"d,26:23,26:40","dtypep":"(J)","origName":"x_input_var_logic","verilogName":"x_input_var_logic","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ]}, {"type":"MODULE","name":"mh7","addr":"(M)","loc":"d,28:8,28:11","origName":"mh7","verilogName":"mh7","level":1,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - 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{"type":"VAR","name":"x_ref_logic_p6","addr":"(Y)","loc":"d,38:23,38:37","dtypep":"(Z)","origName":"x_ref_logic_p6","verilogName":"x_ref_logic_p6","isPrimaryIO":true,"direction":"REF","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} + {"type":"VAR","name":"x_ref_logic_p6","addr":"(Y)","loc":"d,38:23,38:37","dtypep":"(Z)","origName":"x_ref_logic_p6","verilogName":"x_ref_logic_p6","isPrimaryIO":true,"direction":"REF","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ]}, {"type":"MODULE","name":"mh13","addr":"(AB)","loc":"d,40:8,40:12","origName":"mh13","verilogName":"mh13","level":1,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"x_ref_var_logic_u6","addr":"(BB)","loc":"d,40:17,40:35","dtypep":"(CB)","origName":"x_ref_var_logic_u6","verilogName":"x_ref_var_logic_u6","isPrimaryIO":true,"direction":"REF","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} + {"type":"VAR","name":"x_ref_var_logic_u6","addr":"(BB)","loc":"d,40:17,40:35","dtypep":"(CB)","origName":"x_ref_var_logic_u6","verilogName":"x_ref_var_logic_u6","isPrimaryIO":true,"direction":"REF","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ]}, {"type":"MODULE","name":"mh17","addr":"(DB)","loc":"d,50:8,50:12","origName":"mh17","verilogName":"mh17","level":1,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"x_input_var_integer","addr":"(EB)","loc":"d,50:31,50:50","dtypep":"(G)","origName":"x_input_var_integer","verilogName":"x_input_var_integer","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"integer","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"y_input_wire_logic","addr":"(FB)","loc":"d,50:57,50:75","dtypep":"(J)","origName":"y_input_wire_logic","verilogName":"y_input_wire_logic","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} + {"type":"VAR","name":"x_input_var_integer","addr":"(EB)","loc":"d,50:31,50:50","dtypep":"(G)","origName":"x_input_var_integer","verilogName":"x_input_var_integer","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"integer","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"y_input_wire_logic","addr":"(FB)","loc":"d,50:57,50:75","dtypep":"(J)","origName":"y_input_wire_logic","verilogName":"y_input_wire_logic","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ]}, {"type":"MODULE","name":"mh18","addr":"(GB)","loc":"d,52:8,52:12","origName":"mh18","verilogName":"mh18","level":1,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"x_output_var_logic","addr":"(HB)","loc":"d,52:24,52:42","dtypep":"(J)","origName":"x_output_var_logic","verilogName":"x_output_var_logic","isPrimaryIO":true,"direction":"OUTPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"y_input_wire_logic","addr":"(IB)","loc":"d,52:50,52:68","dtypep":"(J)","origName":"y_input_wire_logic","verilogName":"y_input_wire_logic","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} + {"type":"VAR","name":"x_output_var_logic","addr":"(HB)","loc":"d,52:24,52:42","dtypep":"(J)","origName":"x_output_var_logic","verilogName":"x_output_var_logic","isPrimaryIO":true,"direction":"OUTPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"y_input_wire_logic","addr":"(IB)","loc":"d,52:50,52:68","dtypep":"(J)","origName":"y_input_wire_logic","verilogName":"y_input_wire_logic","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ]}, {"type":"MODULE","name":"mh19","addr":"(JB)","loc":"d,54:8,54:12","origName":"mh19","verilogName":"mh19","level":1,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"x_output_wire_logic_signed_p6","addr":"(KB)","loc":"d,54:33,54:62","dtypep":"(U)","origName":"x_output_wire_logic_signed_p6","verilogName":"x_output_wire_logic_signed_p6","isPrimaryIO":true,"direction":"OUTPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"y_output_var_integer","addr":"(LB)","loc":"d,54:72,54:92","dtypep":"(G)","origName":"y_output_var_integer","verilogName":"y_output_var_integer","isPrimaryIO":true,"direction":"OUTPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"integer","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} + {"type":"VAR","name":"x_output_wire_logic_signed_p6","addr":"(KB)","loc":"d,54:33,54:62","dtypep":"(U)","origName":"x_output_wire_logic_signed_p6","verilogName":"x_output_wire_logic_signed_p6","isPrimaryIO":true,"direction":"OUTPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"y_output_var_integer","addr":"(LB)","loc":"d,54:72,54:92","dtypep":"(G)","origName":"y_output_var_integer","verilogName":"y_output_var_integer","isPrimaryIO":true,"direction":"OUTPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"integer","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ]}, {"type":"MODULE","name":"mh20","addr":"(MB)","loc":"d,56:8,56:12","origName":"mh20","verilogName":"mh20","level":1,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"x_ref_var_logic_p6","addr":"(NB)","loc":"d,56:23,56:41","dtypep":"(Z)","origName":"x_ref_var_logic_p6","verilogName":"x_ref_var_logic_p6","isPrimaryIO":true,"direction":"REF","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"y_ref_var_logic_p6","addr":"(OB)","loc":"d,56:43,56:61","dtypep":"(Z)","origName":"y_ref_var_logic_p6","verilogName":"y_ref_var_logic_p6","isPrimaryIO":true,"direction":"REF","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} + {"type":"VAR","name":"x_ref_var_logic_p6","addr":"(NB)","loc":"d,56:23,56:41","dtypep":"(Z)","origName":"x_ref_var_logic_p6","verilogName":"x_ref_var_logic_p6","isPrimaryIO":true,"direction":"REF","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"y_ref_var_logic_p6","addr":"(OB)","loc":"d,56:43,56:61","dtypep":"(Z)","origName":"y_ref_var_logic_p6","verilogName":"y_ref_var_logic_p6","isPrimaryIO":true,"direction":"REF","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ]}, {"type":"MODULE","name":"mh21","addr":"(PB)","loc":"d,58:8,58:12","origName":"mh21","verilogName":"mh21","level":1,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"ref_var_logic_u6","addr":"(QB)","loc":"d,58:17,58:33","dtypep":"(RB)","origName":"ref_var_logic_u6","verilogName":"ref_var_logic_u6","isPrimaryIO":true,"direction":"REF","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"y_ref_var_logic","addr":"(SB)","loc":"d,58:41,58:56","dtypep":"(J)","origName":"y_ref_var_logic","verilogName":"y_ref_var_logic","isPrimaryIO":true,"direction":"REF","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} + {"type":"VAR","name":"ref_var_logic_u6","addr":"(QB)","loc":"d,58:17,58:33","dtypep":"(RB)","origName":"ref_var_logic_u6","verilogName":"ref_var_logic_u6","isPrimaryIO":true,"direction":"REF","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"y_ref_var_logic","addr":"(SB)","loc":"d,58:41,58:56","dtypep":"(J)","origName":"y_ref_var_logic","verilogName":"y_ref_var_logic","isPrimaryIO":true,"direction":"REF","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","fourstateComplementp":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ]} ],"filesp": [], "miscsp": [ diff --git a/test_regress/t/t_var_rsvd.py b/test_regress/t/t_var_rsvd.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_var_rsvd.py +++ b/test_regress/t/t_var_rsvd.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_var_sc_bv.py b/test_regress/t/t_var_sc_bv.py index 04b92947c..f033216f9 100755 --- a/test_regress/t/t_var_sc_bv.py +++ b/test_regress/t/t_var_sc_bv.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(make_top_shell=False, make_main=False, diff --git a/test_regress/t/t_var_sc_double.py b/test_regress/t/t_var_sc_double.py index 04b92947c..f033216f9 100755 --- a/test_regress/t/t_var_sc_double.py +++ b/test_regress/t/t_var_sc_double.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(make_top_shell=False, make_main=False, diff --git a/test_regress/t/t_var_static.py b/test_regress/t/t_var_static.py index 8537b369d..80b8cb63c 100755 --- a/test_regress/t/t_var_static.py +++ b/test_regress/t/t_var_static.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['-Wno-IMPLICITSTATIC']) diff --git a/test_regress/t/t_var_top_struct.py b/test_regress/t/t_var_top_struct.py index 66009b455..52533feae 100755 --- a/test_regress/t/t_var_top_struct.py +++ b/test_regress/t/t_var_top_struct.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_var_types.py b/test_regress/t/t_var_types.py index 8b5344d9a..3f302107c 100755 --- a/test_regress/t/t_var_types.py +++ b/test_regress/t/t_var_types.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.verilated_randReset = 1 # allow checking if we initialize vars to zero only when needed test.compile(verilator_flags2=["--x-assign 1"]) diff --git a/test_regress/t/t_var_vec_sel.py b/test_regress/t/t_var_vec_sel.py index 67b896515..8a1a7b033 100755 --- a/test_regress/t/t_var_vec_sel.py +++ b/test_regress/t/t_var_vec_sel.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('linter') +test.fourstate_capable = False test.lint() diff --git a/test_regress/t/t_var_xref_gen.py b/test_regress/t/t_var_xref_gen.py index 52389589b..7c066dee5 100755 --- a/test_regress/t/t_var_xref_gen.py +++ b/test_regress/t/t_var_xref_gen.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.compile(verilator_flags2=["--debug-check"]) diff --git a/test_regress/t/t_varref_scope_in_interface.py b/test_regress/t/t_varref_scope_in_interface.py index 88752b416..859fae682 100755 --- a/test_regress/t/t_varref_scope_in_interface.py +++ b/test_regress/t/t_varref_scope_in_interface.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.lint() diff --git a/test_regress/t/t_verilated_all.py b/test_regress/t/t_verilated_all.py index 871acac69..85dedb66d 100755 --- a/test_regress/t/t_verilated_all.py +++ b/test_regress/t/t_verilated_all.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vltmt') +test.fourstate_capable = False if not os.path.exists(test.root + "/.git"): test.skip("Not in a git repository") diff --git a/test_regress/t/t_verilated_all_newest.py b/test_regress/t/t_verilated_all_newest.py index 417fc64a7..67cc3c6c3 100755 --- a/test_regress/t/t_verilated_all_newest.py +++ b/test_regress/t/t_verilated_all_newest.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_verilated_all.v" test.compile( diff --git a/test_regress/t/t_verilated_debug.py b/test_regress/t/t_verilated_debug.py index e880f1866..c446d86df 100755 --- a/test_regress/t/t_verilated_debug.py +++ b/test_regress/t/t_verilated_debug.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.verilated_debug = True test.compile(verilator_flags2=['-fno-inline-cfuncs']) diff --git a/test_regress/t/t_verilated_threaded.py b/test_regress/t/t_verilated_threaded.py index b7f070268..b525cdd79 100755 --- a/test_regress/t/t_verilated_threaded.py +++ b/test_regress/t/t_verilated_threaded.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vltmt') +test.fourstate_capable = False test.top_filename = "t/t_verilated_all.v" test.compile( diff --git a/test_regress/t/t_virtual_interface_delayed.py b/test_regress/t/t_virtual_interface_delayed.py index 4ee7f9e14..64d4ecb78 100755 --- a/test_regress/t/t_virtual_interface_delayed.py +++ b/test_regress/t/t_virtual_interface_delayed.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary']) diff --git a/test_regress/t/t_virtual_interface_member_trigger.py b/test_regress/t/t_virtual_interface_member_trigger.py index 4ee7f9e14..64d4ecb78 100755 --- a/test_regress/t/t_virtual_interface_member_trigger.py +++ b/test_regress/t/t_virtual_interface_member_trigger.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary']) diff --git a/test_regress/t/t_virtual_interface_member_trigger_real.py b/test_regress/t/t_virtual_interface_member_trigger_real.py index 4ee7f9e14..64d4ecb78 100755 --- a/test_regress/t/t_virtual_interface_member_trigger_real.py +++ b/test_regress/t/t_virtual_interface_member_trigger_real.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary']) diff --git a/test_regress/t/t_virtual_interface_method.py b/test_regress/t/t_virtual_interface_method.py index 61fae108a..f3210243d 100755 --- a/test_regress/t/t_virtual_interface_method.py +++ b/test_regress/t/t_virtual_interface_method.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False # It loops infinitely test.compile(v_flags2=["--binary"], verilator_make_gmake=False) diff --git a/test_regress/t/t_virtual_interface_method_sched.py b/test_regress/t/t_virtual_interface_method_sched.py index 6ac2815da..31861c135 100755 --- a/test_regress/t/t_virtual_interface_method_sched.py +++ b/test_regress/t/t_virtual_interface_method_sched.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--timing"]) diff --git a/test_regress/t/t_virtual_interface_nba_assign.py b/test_regress/t/t_virtual_interface_nba_assign.py index 4ee7f9e14..64d4ecb78 100755 --- a/test_regress/t/t_virtual_interface_nba_assign.py +++ b/test_regress/t/t_virtual_interface_nba_assign.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary']) diff --git a/test_regress/t/t_virtual_interface_only_with_assignw.py b/test_regress/t/t_virtual_interface_only_with_assignw.py index 46d1fe4c0..bd6ade23d 100755 --- a/test_regress/t/t_virtual_interface_only_with_assignw.py +++ b/test_regress/t/t_virtual_interface_only_with_assignw.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary']) diff --git a/test_regress/t/t_virtual_interface_unused_task_trigger.py b/test_regress/t/t_virtual_interface_unused_task_trigger.py index f2d7f08fa..5790553c6 100755 --- a/test_regress/t/t_virtual_interface_unused_task_trigger.py +++ b/test_regress/t/t_virtual_interface_unused_task_trigger.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary', '--timing']) diff --git a/test_regress/t/t_vlcov_covergroup.py b/test_regress/t/t_vlcov_covergroup.py index 05f12efa0..7cd0dec00 100755 --- a/test_regress/t/t_vlcov_covergroup.py +++ b/test_regress/t/t_vlcov_covergroup.py @@ -11,6 +11,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_covergroup_cross.v" diff --git a/test_regress/t/t_vlcov_fsm_report.py b/test_regress/t/t_vlcov_fsm_report.py index ccfc706ca..a73284df0 100755 --- a/test_regress/t/t_vlcov_fsm_report.py +++ b/test_regress/t/t_vlcov_fsm_report.py @@ -12,6 +12,7 @@ import os import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False # This regression targets the reporting side of FSM coverage rather than the # detector itself. The generated coverage.dat contains state points, ordinary diff --git a/test_regress/t/t_vlcov_hier_report_runtime.py b/test_regress/t/t_vlcov_hier_report_runtime.py index eba1c5dec..e2e189a83 100755 --- a/test_regress/t/t_vlcov_hier_report_runtime.py +++ b/test_regress/t/t_vlcov_hier_report_runtime.py @@ -12,6 +12,7 @@ import vltest_bootstrap from coverage_common import init_log, run_vlcov, vlcov_run_context test.scenarios('simulator') +test.fourstate_capable = False if not test.have_coroutines: test.skip("Test requires Coroutines; ignore error since not available") diff --git a/test_regress/t/t_vlt_timing.py b/test_regress/t/t_vlt_timing.py index 23cc86544..cf61f860c 100755 --- a/test_regress/t/t_vlt_timing.py +++ b/test_regress/t/t_vlt_timing.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=["--binary t/t_vlt_timing.vlt"]) diff --git a/test_regress/t/t_vpi_dump.py b/test_regress/t/t_vpi_dump.py index 89b8841ed..a9f02b375 100755 --- a/test_regress/t/t_vpi_dump.py +++ b/test_regress/t/t_vpi_dump.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(make_top_shell=False, make_main=False, diff --git a/test_regress/t/t_vpi_dump_missing_scopes.py b/test_regress/t/t_vpi_dump_missing_scopes.py index a762066ee..959b38322 100755 --- a/test_regress/t/t_vpi_dump_missing_scopes.py +++ b/test_regress/t/t_vpi_dump_missing_scopes.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.pli_filename = "t/t_vpi_dump.cpp" test.compile(make_top_shell=False, diff --git a/test_regress/t/t_vpi_dump_no_inline.py b/test_regress/t/t_vpi_dump_no_inline.py index e15bbd2a9..bc979754f 100755 --- a/test_regress/t/t_vpi_dump_no_inline.py +++ b/test_regress/t/t_vpi_dump_no_inline.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.pli_filename = "t/t_vpi_dump.cpp" test.golden_filename = "t/t_vpi_dump.out" test.top_filename = "t/t_vpi_dump.v" diff --git a/test_regress/t/t_vpi_escape.py b/test_regress/t/t_vpi_escape.py index ad5236557..99950ecdb 100755 --- a/test_regress/t/t_vpi_escape.py +++ b/test_regress/t/t_vpi_escape.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.pli_filename = "t/t_vpi_escape.cpp" test.compile(make_top_shell=False, diff --git a/test_regress/t/t_vpi_force.py b/test_regress/t/t_vpi_force.py index 43b39cb62..62485ee51 100755 --- a/test_regress/t/t_vpi_force.py +++ b/test_regress/t/t_vpi_force.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile( make_top_shell=False, diff --git a/test_regress/t/t_vpi_forceable_var.py b/test_regress/t/t_vpi_forceable_var.py index 0232be9e0..99c63fcc2 100755 --- a/test_regress/t/t_vpi_forceable_var.py +++ b/test_regress/t/t_vpi_forceable_var.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.pli_filename = "t/t_vpi_var.cpp" test.top_filename = "t/t_vpi_var.v" diff --git a/test_regress/t/t_vpi_get.py b/test_regress/t/t_vpi_get.py index 499796518..9f16bdfb7 100755 --- a/test_regress/t/t_vpi_get.py +++ b/test_regress/t/t_vpi_get.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(make_top_shell=False, make_main=False, diff --git a/test_regress/t/t_vpi_get_public_rw_switch.py b/test_regress/t/t_vpi_get_public_rw_switch.py index 158ec956a..14308de01 100755 --- a/test_regress/t/t_vpi_get_public_rw_switch.py +++ b/test_regress/t/t_vpi_get_public_rw_switch.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.vm_prefix = "Vt_vpi_get" test.top_filename = "t/t_vpi_get.v" test.pli_filename = "t/t_vpi_get.cpp" diff --git a/test_regress/t/t_vpi_get_value_array.py b/test_regress/t/t_vpi_get_value_array.py index 499796518..9f16bdfb7 100755 --- a/test_regress/t/t_vpi_get_value_array.py +++ b/test_regress/t/t_vpi_get_value_array.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(make_top_shell=False, make_main=False, diff --git a/test_regress/t/t_vpi_memory.py b/test_regress/t/t_vpi_memory.py index 83449045d..6e799c2f0 100755 --- a/test_regress/t/t_vpi_memory.py +++ b/test_regress/t/t_vpi_memory.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(make_top_shell=False, make_main=False, diff --git a/test_regress/t/t_vpi_multidim.py b/test_regress/t/t_vpi_multidim.py index e891344e5..f32204402 100755 --- a/test_regress/t/t_vpi_multidim.py +++ b/test_regress/t/t_vpi_multidim.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(make_top_shell=False, make_main=False, diff --git a/test_regress/t/t_vpi_param.py b/test_regress/t/t_vpi_param.py index 83449045d..6e799c2f0 100755 --- a/test_regress/t/t_vpi_param.py +++ b/test_regress/t/t_vpi_param.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(make_top_shell=False, make_main=False, diff --git a/test_regress/t/t_vpi_public_depthn_1.py b/test_regress/t/t_vpi_public_depthn_1.py index 62caa1eed..5a59ed8b6 100755 --- a/test_regress/t/t_vpi_public_depthn_1.py +++ b/test_regress/t/t_vpi_public_depthn_1.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_vpi_public_depthn.v" test.compile(verilator_flags2=['--public-depth 1']) diff --git a/test_regress/t/t_vpi_public_depthn_2.py b/test_regress/t/t_vpi_public_depthn_2.py index f3ef9238b..877bb9c78 100755 --- a/test_regress/t/t_vpi_public_depthn_2.py +++ b/test_regress/t/t_vpi_public_depthn_2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_vpi_public_depthn.v" test.compile(verilator_flags2=['--public-depth 2']) diff --git a/test_regress/t/t_vpi_public_depthn_3.py b/test_regress/t/t_vpi_public_depthn_3.py index 9d9be297b..0e6650212 100755 --- a/test_regress/t/t_vpi_public_depthn_3.py +++ b/test_regress/t/t_vpi_public_depthn_3.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False test.top_filename = "t/t_vpi_public_depthn.v" test.compile(verilator_flags2=['--public-depth 3']) diff --git a/test_regress/t/t_vpi_public_params.py b/test_regress/t/t_vpi_public_params.py index 26d0b8c0e..0a85049cc 100755 --- a/test_regress/t/t_vpi_public_params.py +++ b/test_regress/t/t_vpi_public_params.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.pli_filename = "t/t_vpi_param.cpp" # same vpi script should work with --public-params instead of inline publics diff --git a/test_regress/t/t_vpi_put_value_array.py b/test_regress/t/t_vpi_put_value_array.py index 499796518..9f16bdfb7 100755 --- a/test_regress/t/t_vpi_put_value_array.py +++ b/test_regress/t/t_vpi_put_value_array.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(make_top_shell=False, make_main=False, diff --git a/test_regress/t/t_vpi_sc.py b/test_regress/t/t_vpi_sc.py index bb2cd47cf..b74dac43d 100755 --- a/test_regress/t/t_vpi_sc.py +++ b/test_regress/t/t_vpi_sc.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile( # Must not make shell/main or hides bug diff --git a/test_regress/t/t_vpi_var.py b/test_regress/t/t_vpi_var.py index 86de3c42a..9d6414da4 100755 --- a/test_regress/t/t_vpi_var.py +++ b/test_regress/t/t_vpi_var.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(make_top_shell=False, make_main=False, diff --git a/test_regress/t/t_vpi_var2.py b/test_regress/t/t_vpi_var2.py index 7d4a550b1..89123caa3 100755 --- a/test_regress/t/t_vpi_var2.py +++ b/test_regress/t/t_vpi_var2.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.pli_filename = "t/t_vpi_var.cpp" test.compile(make_top_shell=False, diff --git a/test_regress/t/t_vpi_var3.py b/test_regress/t/t_vpi_var3.py index 7b2d9f412..884aea361 100755 --- a/test_regress/t/t_vpi_var3.py +++ b/test_regress/t/t_vpi_var3.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.pli_filename = "t/t_vpi_var.cpp" test.compile(make_top_shell=False, diff --git a/test_regress/t/t_wait_iface_vif.py b/test_regress/t/t_wait_iface_vif.py index 46d1fe4c0..bd6ade23d 100755 --- a/test_regress/t/t_wait_iface_vif.py +++ b/test_regress/t/t_wait_iface_vif.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile(verilator_flags2=['--binary']) diff --git a/test_regress/t/t_waiveroutput_roundtrip.py b/test_regress/t/t_waiveroutput_roundtrip.py index e3bc2e547..b82121164 100755 --- a/test_regress/t/t_waiveroutput_roundtrip.py +++ b/test_regress/t/t_waiveroutput_roundtrip.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') +test.fourstate_capable = False out_filename = test.obj_dir + "/" + test.name + ".waiver_gen.out" waiver_filename = test.obj_dir + "/" + test.name + "_waiver.vlt" diff --git a/test_regress/t/t_wired_net_test.py b/test_regress/t/t_wired_net_test.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_wired_net_test.py +++ b/test_regress/t/t_wired_net_test.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_with.py b/test_regress/t/t_with.py index 3cc73805c..c808eecc4 100755 --- a/test_regress/t/t_with.py +++ b/test_regress/t/t_with.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') +test.fourstate_capable = False test.compile() diff --git a/test_regress/t/t_wrapper_context.py b/test_regress/t/t_wrapper_context.py index 8df7e10ef..ee8771bc3 100755 --- a/test_regress/t/t_wrapper_context.py +++ b/test_regress/t/t_wrapper_context.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.compile( make_top_shell=False, diff --git a/test_regress/t/t_wrapper_context_fst.py b/test_regress/t/t_wrapper_context_fst.py index b4bed53eb..331dffd13 100755 --- a/test_regress/t/t_wrapper_context_fst.py +++ b/test_regress/t/t_wrapper_context_fst.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.pli_filename = "t/t_wrapper_context.cpp" test.top_filename = "t/t_wrapper_context.v" diff --git a/test_regress/t/t_wrapper_context_seq.py b/test_regress/t/t_wrapper_context_seq.py index 3a1222abc..cbbdf74fa 100755 --- a/test_regress/t/t_wrapper_context_seq.py +++ b/test_regress/t/t_wrapper_context_seq.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.pli_filename = "t/t_wrapper_context.cpp" test.top_filename = "t/t_wrapper_context.v" diff --git a/test_regress/t/t_x_assign_0.py b/test_regress/t/t_x_assign_0.py index 586ae8f62..0b47f821b 100755 --- a/test_regress/t/t_x_assign_0.py +++ b/test_regress/t/t_x_assign_0.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.pli_filename = "t/t_x_assign.cpp" test.top_filename = "t/t_x_assign.v" diff --git a/test_regress/t/t_x_assign_1.py b/test_regress/t/t_x_assign_1.py index 8957289a5..340dccd2a 100755 --- a/test_regress/t/t_x_assign_1.py +++ b/test_regress/t/t_x_assign_1.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.pli_filename = "t/t_x_assign.cpp" test.top_filename = "t/t_x_assign.v" diff --git a/test_regress/t/t_x_assign_unique_0.py b/test_regress/t/t_x_assign_unique_0.py index 723512416..568377f62 100755 --- a/test_regress/t/t_x_assign_unique_0.py +++ b/test_regress/t/t_x_assign_unique_0.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.pli_filename = "t/t_x_assign.cpp" test.top_filename = "t/t_x_assign.v" diff --git a/test_regress/t/t_x_assign_unique_1.py b/test_regress/t/t_x_assign_unique_1.py index 723512416..568377f62 100755 --- a/test_regress/t/t_x_assign_unique_1.py +++ b/test_regress/t/t_x_assign_unique_1.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.fourstate_capable = False test.pli_filename = "t/t_x_assign.cpp" test.top_filename = "t/t_x_assign.v" diff --git a/test_regress/t/t_x_rand_mt_stability.py b/test_regress/t/t_x_rand_mt_stability.py index 820119492..730348e95 100755 --- a/test_regress/t/t_x_rand_mt_stability.py +++ b/test_regress/t/t_x_rand_mt_stability.py @@ -11,6 +11,7 @@ import vltest_bootstrap import glob test.scenarios("vltmt") +test.fourstate_capable = False test.top_filename = "t/t_x_rand_stability.v" test.compile(verilator_flags2=["--x-initial unique"]) diff --git a/test_regress/t/t_x_rand_mt_stability_add.py b/test_regress/t/t_x_rand_mt_stability_add.py index 0bcc359a5..c6aaf6da8 100755 --- a/test_regress/t/t_x_rand_mt_stability_add.py +++ b/test_regress/t/t_x_rand_mt_stability_add.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios("vltmt") +test.fourstate_capable = False test.top_filename = "t/t_x_rand_stability.v" test.compile(verilator_flags2=["--x-initial unique", "-DADD_SIGNAL"]) diff --git a/test_regress/t/t_x_rand_mt_stability_add_trace.py b/test_regress/t/t_x_rand_mt_stability_add_trace.py index 278edc8c2..b4b10cfa0 100755 --- a/test_regress/t/t_x_rand_mt_stability_add_trace.py +++ b/test_regress/t/t_x_rand_mt_stability_add_trace.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios("vltmt") +test.fourstate_capable = False test.top_filename = "t/t_x_rand_stability.v" test.compile(verilator_flags2=["--x-initial unique", "-DADD_SIGNAL", "--trace"]) diff --git a/test_regress/t/t_x_rand_mt_stability_trace.py b/test_regress/t/t_x_rand_mt_stability_trace.py index 042bf344a..46a57686b 100755 --- a/test_regress/t/t_x_rand_mt_stability_trace.py +++ b/test_regress/t/t_x_rand_mt_stability_trace.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios("vltmt") +test.fourstate_capable = False test.top_filename = "t/t_x_rand_stability.v" test.compile(verilator_flags2=["--x-initial unique", "--trace"]) diff --git a/test_regress/t/t_x_rand_mt_stability_zeros.py b/test_regress/t/t_x_rand_mt_stability_zeros.py index 8a062d04d..af6b156bc 100755 --- a/test_regress/t/t_x_rand_mt_stability_zeros.py +++ b/test_regress/t/t_x_rand_mt_stability_zeros.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios("vltmt") +test.fourstate_capable = False test.top_filename = "t/t_x_rand_stability.v" test.compile(verilator_flags2=["--x-initial unique", "-DNOT_RAND"]) diff --git a/test_regress/t/t_x_rand_scoped_is_random.py b/test_regress/t/t_x_rand_scoped_is_random.py index 4d5a57238..e7545dceb 100755 --- a/test_regress/t/t_x_rand_scoped_is_random.py +++ b/test_regress/t/t_x_rand_scoped_is_random.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios("simulator_st") +test.fourstate_capable = False test.compile(timing_loop=True, verilator_flags2=["--timing"]) diff --git a/test_regress/t/t_x_rand_stability.py b/test_regress/t/t_x_rand_stability.py index e992309d3..3f2030776 100755 --- a/test_regress/t/t_x_rand_stability.py +++ b/test_regress/t/t_x_rand_stability.py @@ -11,6 +11,7 @@ import vltest_bootstrap import glob test.scenarios("vlt") +test.fourstate_capable = False test.compile(verilator_flags2=["--x-initial unique"]) diff --git a/test_regress/t/t_x_rand_stability_add.py b/test_regress/t/t_x_rand_stability_add.py index 4d2c7c257..8ef32adac 100755 --- a/test_regress/t/t_x_rand_stability_add.py +++ b/test_regress/t/t_x_rand_stability_add.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios("vlt") +test.fourstate_capable = False test.top_filename = "t/t_x_rand_stability.v" test.compile(verilator_flags2=["--x-initial unique", "-DADD_SIGNAL"]) diff --git a/test_regress/t/t_x_rand_stability_add_trace.py b/test_regress/t/t_x_rand_stability_add_trace.py index ace3b9790..6b08cb4ac 100755 --- a/test_regress/t/t_x_rand_stability_add_trace.py +++ b/test_regress/t/t_x_rand_stability_add_trace.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios("vlt") +test.fourstate_capable = False test.top_filename = "t/t_x_rand_stability.v" test.compile(verilator_flags2=["--x-initial unique", "-DADD_SIGNAL", "--trace"]) diff --git a/test_regress/t/t_x_rand_stability_trace.py b/test_regress/t/t_x_rand_stability_trace.py index 3ff7d8e20..2fe0a2dac 100755 --- a/test_regress/t/t_x_rand_stability_trace.py +++ b/test_regress/t/t_x_rand_stability_trace.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios("vlt") +test.fourstate_capable = False test.top_filename = "t/t_x_rand_stability.v" test.compile(verilator_flags2=["--x-initial unique", "--trace"]) diff --git a/test_regress/t/t_x_rand_stability_zeros.py b/test_regress/t/t_x_rand_stability_zeros.py index 78dac3f86..bb857200b 100755 --- a/test_regress/t/t_x_rand_stability_zeros.py +++ b/test_regress/t/t_x_rand_stability_zeros.py @@ -10,6 +10,7 @@ import vltest_bootstrap test.scenarios("vlt") +test.fourstate_capable = False test.top_filename = "t/t_x_rand_stability.v" test.compile(verilator_flags2=["--x-initial unique", "-DNOT_RAND"])