From 06521f6cf13062a2248625d838089770a69dfcae Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Thu, 27 Jul 2023 05:33:34 -0400 Subject: [PATCH] Tests: Fix some missing coverage, and cleanup some error messages --- src/V3LinkDot.cpp | 4 ++-- src/V3Task.cpp | 2 +- src/V3Width.cpp | 2 +- src/verilog.y | 4 ++-- test_regress/t/t_assert_imm_nz_bad.out | 4 ++++ test_regress/t/t_assert_imm_nz_bad.pl | 20 +++++++++++++++++ test_regress/t/t_assert_imm_nz_bad.v | 15 +++++++++++++ test_regress/t/t_cast_size_bad.out | 11 ++++++++++ test_regress/t/t_cast_size_bad.pl | 19 ++++++++++++++++ test_regress/t/t_cast_size_bad.v | 17 ++++++++++++++ .../t/t_class_member_var_virt_bad.out | 4 ++++ test_regress/t/t_class_member_var_virt_bad.pl | 19 ++++++++++++++++ test_regress/t/t_class_member_var_virt_bad.v | 12 ++++++++++ test_regress/t/t_concat_link_bad.out | 6 ++--- test_regress/t/t_dist_warn_coverage.pl | 9 +------- test_regress/t/t_vlt_warn_ecode_bad.out | 7 ++++++ test_regress/t/t_vlt_warn_ecode_bad.pl | 22 +++++++++++++++++++ test_regress/t/t_vlt_warn_ecode_bad.vlt | 10 +++++++++ 18 files changed, 170 insertions(+), 17 deletions(-) create mode 100644 test_regress/t/t_assert_imm_nz_bad.out create mode 100755 test_regress/t/t_assert_imm_nz_bad.pl create mode 100644 test_regress/t/t_assert_imm_nz_bad.v create mode 100644 test_regress/t/t_cast_size_bad.out create mode 100755 test_regress/t/t_cast_size_bad.pl create mode 100644 test_regress/t/t_cast_size_bad.v create mode 100644 test_regress/t/t_class_member_var_virt_bad.out create mode 100755 test_regress/t/t_class_member_var_virt_bad.pl create mode 100644 test_regress/t/t_class_member_var_virt_bad.v create mode 100644 test_regress/t/t_vlt_warn_ecode_bad.out create mode 100755 test_regress/t/t_vlt_warn_ecode_bad.pl create mode 100644 test_regress/t/t_vlt_warn_ecode_bad.vlt diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp index b7546f62c..20379ad40 100644 --- a/src/V3LinkDot.cpp +++ b/src/V3LinkDot.cpp @@ -2144,7 +2144,7 @@ private: void checkNoDot(AstNode* nodep) { if (VL_UNLIKELY(m_ds.m_dotPos != DP_NONE)) { // UINFO(9, "ds=" << m_ds.ascii() << endl); - nodep->v3error("Syntax Error: Not expecting " << nodep->type() << " under a " + nodep->v3error("Syntax error: Not expecting " << nodep->type() << " under a " << nodep->backp()->type() << " in dotted expression"); m_ds.m_dotErr = true; @@ -3240,7 +3240,7 @@ private: if (nodep->user3SetOnce()) return; if (m_ds.m_dotPos == DP_SCOPE) { // Already under dot, so this is {modulepart} DOT {modulepart} - nodep->v3error("Syntax Error: Range ':', '+:' etc are not allowed in the instance " + nodep->v3error("Syntax error: Range ':', '+:' etc are not allowed in the instance " "part of a dotted reference"); m_ds.m_dotErr = true; return; diff --git a/src/V3Task.cpp b/src/V3Task.cpp index 9be0ce8c3..1ab29ea06 100644 --- a/src/V3Task.cpp +++ b/src/V3Task.cpp @@ -1099,7 +1099,7 @@ private: if (nodep->isFunction()) { AstVar* const portp = VN_AS(nodep->fvarp(), Var); UASSERT_OBJ(portp, nodep, "function without function output variable"); - if (!portp->isFuncReturn()) nodep->v3error("Not marked as function return var"); + UASSERT_OBJ(portp->isFuncReturn(), nodep, "Not marked as function return var"); if (nodep->dpiImport() || nodep->dpiExport()) { AstBasicDType* const bdtypep = portp->dtypep()->basicp(); if (!bdtypep->isDpiPrimitive()) { diff --git a/src/V3Width.cpp b/src/V3Width.cpp index 83e03069a..4012fb566 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -1549,7 +1549,7 @@ private: nodep->v3warn(E_UNSUPPORTED, "Unsupported: $bits for queue"); break; } - default: nodep->v3error("Unhandled attribute type"); + default: nodep->v3fatalSrc("Unhandled attribute type"); } } else { const std::pair dimpair = dtypep->skipRefp()->dimensions(true); diff --git a/src/verilog.y b/src/verilog.y index b83e8ce1f..bb0b15139 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -7230,7 +7230,7 @@ vltOffFront: { const char *codemsg = (*$3).c_str(); if (V3ErrorCode::unusedMsg(codemsg)) {$$ = V3ErrorCode::I_UNUSED; } else {$$ = V3ErrorCode{codemsg}; } - if ($$ == V3ErrorCode::EC_ERROR) { $1->v3error("Unknown Error Code: " << *$3); } } + if ($$ == V3ErrorCode::EC_ERROR) { $1->v3error("Unknown error code: " << *$3); } } ; vltOnFront: @@ -7242,7 +7242,7 @@ vltOnFront: { const char *codemsg = (*$3).c_str(); if (V3ErrorCode::unusedMsg(codemsg)) {$$ = V3ErrorCode::I_UNUSED; } else {$$ = V3ErrorCode{codemsg}; } - if ($$ == V3ErrorCode::EC_ERROR) { $1->v3error("Unknown Error Code: " << *$3); } } + if ($$ == V3ErrorCode::EC_ERROR) { $1->v3error("Unknown error code: " << *$3); } } ; vltDModuleE: diff --git a/test_regress/t/t_assert_imm_nz_bad.out b/test_regress/t/t_assert_imm_nz_bad.out new file mode 100644 index 000000000..2f81116f0 --- /dev/null +++ b/test_regress/t/t_assert_imm_nz_bad.out @@ -0,0 +1,4 @@ +%Error: t/t_assert_imm_nz_bad.v:13:26: Deferred assertions must use '#0' (IEEE 1800-2017 16.4) + 13 | labeled_imas: assert #1 (clk); + | ^ +%Error: Exiting due to diff --git a/test_regress/t/t_assert_imm_nz_bad.pl b/test_regress/t/t_assert_imm_nz_bad.pl new file mode 100755 index 000000000..efe818bd1 --- /dev/null +++ b/test_regress/t/t_assert_imm_nz_bad.pl @@ -0,0 +1,20 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2022 by Antmicro Ltd. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +compile( + expect_filename => $Self->{golden_filename}, + verilator_flags2 => ['--assert'], + fails => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_assert_imm_nz_bad.v b/test_regress/t/t_assert_imm_nz_bad.v new file mode 100644 index 000000000..ce0867766 --- /dev/null +++ b/test_regress/t/t_assert_imm_nz_bad.v @@ -0,0 +1,15 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2022 by Antmicro Ltd. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + clk + ); + + input clk; + + labeled_imas: assert #1 (clk); // BAD: #1 + +endmodule diff --git a/test_regress/t/t_cast_size_bad.out b/test_regress/t/t_cast_size_bad.out new file mode 100644 index 000000000..498099b69 --- /dev/null +++ b/test_regress/t/t_cast_size_bad.out @@ -0,0 +1,11 @@ +%Error: t/t_cast_size_bad.v:14:15: Size-changing cast to zero or negative size + : ... In instance t + 14 | b = (-1)'(a); + | ^ +%Warning-WIDTHEXPAND: t/t_cast_size_bad.v:14:9: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits. + : ... In instance t + 14 | b = (-1)'(a); + | ^ + ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest + ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. +%Error: Exiting due to diff --git a/test_regress/t/t_cast_size_bad.pl b/test_regress/t/t_cast_size_bad.pl new file mode 100755 index 000000000..9c9fb65a0 --- /dev/null +++ b/test_regress/t/t_cast_size_bad.pl @@ -0,0 +1,19 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2010 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(linter => 1); + +lint( + fails => 1, + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_cast_size_bad.v b/test_regress/t/t_cast_size_bad.v new file mode 100644 index 000000000..3cf88e1da --- /dev/null +++ b/test_regress/t/t_cast_size_bad.v @@ -0,0 +1,17 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2023 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + + int a; + reg [3:0] b; + + initial begin + a = 1; + b = (-1)'(a); // Bad + end + +endmodule diff --git a/test_regress/t/t_class_member_var_virt_bad.out b/test_regress/t/t_class_member_var_virt_bad.out new file mode 100644 index 000000000..21bee5fdf --- /dev/null +++ b/test_regress/t/t_class_member_var_virt_bad.out @@ -0,0 +1,4 @@ +%Error: t/t_class_member_var_virt_bad.v:8:16: Syntax error: 'virtual' not allowed before var declaration + 8 | virtual int member; + | ^~~~~~ +%Error: Exiting due to diff --git a/test_regress/t/t_class_member_var_virt_bad.pl b/test_regress/t/t_class_member_var_virt_bad.pl new file mode 100755 index 000000000..376c2d2ee --- /dev/null +++ b/test_regress/t/t_class_member_var_virt_bad.pl @@ -0,0 +1,19 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2023 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(linter => 1); + +lint( + fails => 1, + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_class_member_var_virt_bad.v b/test_regress/t/t_class_member_var_virt_bad.v new file mode 100644 index 000000000..492a70785 --- /dev/null +++ b/test_regress/t/t_class_member_var_virt_bad.v @@ -0,0 +1,12 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2023 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +class Foo; + virtual int member; +endclass + +module t; +endmodule diff --git a/test_regress/t/t_concat_link_bad.out b/test_regress/t/t_concat_link_bad.out index 5a1719518..ad22af64a 100644 --- a/test_regress/t/t_concat_link_bad.out +++ b/test_regress/t/t_concat_link_bad.out @@ -1,10 +1,10 @@ -%Error: t/t_concat_link_bad.v:13:20: Syntax Error: Not expecting REPLICATE under a DOT in dotted expression +%Error: t/t_concat_link_bad.v:13:20: Syntax error: Not expecting REPLICATE under a DOT in dotted expression 13 | assign bar_s = {foo_s, foo_s}.f1; | ^ -%Error: t/t_concat_link_bad.v:13:26: Syntax Error: Not expecting CONCAT under a REPLICATE in dotted expression +%Error: t/t_concat_link_bad.v:13:26: Syntax error: Not expecting CONCAT under a REPLICATE in dotted expression 13 | assign bar_s = {foo_s, foo_s}.f1; | ^ -%Error: t/t_concat_link_bad.v:13:20: Syntax Error: Not expecting CONST under a REPLICATE in dotted expression +%Error: t/t_concat_link_bad.v:13:20: Syntax error: Not expecting CONST under a REPLICATE in dotted expression 13 | assign bar_s = {foo_s, foo_s}.f1; | ^ %Warning-IMPLICIT: t/t_concat_link_bad.v:13:12: Signal definition not found, creating implicitly: 'bar_s' diff --git a/test_regress/t/t_dist_warn_coverage.pl b/test_regress/t/t_dist_warn_coverage.pl index bddd75ed5..2889553a5 100755 --- a/test_regress/t/t_dist_warn_coverage.pl +++ b/test_regress/t/t_dist_warn_coverage.pl @@ -26,6 +26,7 @@ foreach my $s ( 'Enum names without values only allowed on numeric types', # Hard to hit 'Enum ranges must be integral, per spec', # Hard to hit 'Return with return value isn\'t underneath a function', # Hard to hit, get other bad return messages + 'Syntax error: Range \':\', \'+:\' etc are not allowed in the instance ', # Instead get syntax error 'Syntax error parsing real: \'', # Instead can't lex the number 'Unsupported: Ranges ignored in port-lists', # Hard to hit 'dynamic new() not expected in this context (expected under an assign)', # Instead get syntax error @@ -40,12 +41,10 @@ foreach my $s ( 'Assigned pin is neither input nor output', 'Assignment pattern with no members', 'Attempted parameter setting of non-parameter: Param ', - 'Can\'t find typedef: ', 'Can\'t find varpin scope of ', 'Can\'t resolve module reference: \'', 'Cannot write preprocessor output: ', 'Circular logic when ordering code (non-cutable edge loop)', - 'Deferred assertions must use \'#0\' (IEEE 1800-2017 16.4)', 'Define or directive not defined: `', 'Exceeded limit of ', 'Extern declaration\'s scope is not a defined class', @@ -62,22 +61,16 @@ foreach my $s ( 'Modport not referenced as .', 'Modport not referenced from underneath an interface: ', 'Non-interface used as an interface: ', - 'Not marked as function return var', 'Parameter not found in sub-module: Param ', 'Parameter type pin value isn\'t a type: Param ', 'Parameter type variable isn\'t a type: Param ', 'Pattern replication value of 0 is not legal.', 'Signals inside functions/tasks cannot be marked forceable', - 'Size-changing cast to zero or negative size', 'Slice size cannot be zero.', 'Slices of arrays in assignments have different unpacked dimensions, ', 'String of ', 'Symbol matching ', - 'Syntax Error: Range \':\', \'+:\' etc are not allowed in the instance ', - 'Syntax error: \'virtual\' not allowed before var declaration', 'Unexpected connection to arrayed port', - 'Unhandled attribute type', - 'Unknown Error Code: ', 'Unknown `pragma', 'Unknown built-in event method ', 'Unsized numbers/parameters not allowed in streams.', diff --git a/test_regress/t/t_vlt_warn_ecode_bad.out b/test_regress/t/t_vlt_warn_ecode_bad.out new file mode 100644 index 000000000..ec0e047bf --- /dev/null +++ b/test_regress/t/t_vlt_warn_ecode_bad.out @@ -0,0 +1,7 @@ +%Error: t/t_vlt_warn_ecode_bad.vlt:9:1: Unknown error code: BADRULENAME + 9 | lint_off -rule BADRULENAME -file "t/t_vlt_warn.v" + | ^~~~~~~~ +%Error: t/t_vlt_warn_ecode_bad.vlt:10:1: Unknown error code: BADRULENAME + 10 | lint_on -rule BADRULENAME -file "t/t_vlt_warn.v" + | ^~~~~~~ +%Error: Exiting due to diff --git a/test_regress/t/t_vlt_warn_ecode_bad.pl b/test_regress/t/t_vlt_warn_ecode_bad.pl new file mode 100755 index 000000000..ebf322c30 --- /dev/null +++ b/test_regress/t/t_vlt_warn_ecode_bad.pl @@ -0,0 +1,22 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +top_filename("t/t_vlt_warn.v"); + +lint( + verilator_flags2 => ["--lint-only t/t_vlt_warn_ecode_bad.vlt"], + fails => 1, + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_vlt_warn_ecode_bad.vlt b/test_regress/t/t_vlt_warn_ecode_bad.vlt new file mode 100644 index 000000000..af0780399 --- /dev/null +++ b/test_regress/t/t_vlt_warn_ecode_bad.vlt @@ -0,0 +1,10 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2010 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`verilator_config + +lint_off -rule BADRULENAME -file "t/t_vlt_warn.v" +lint_on -rule BADRULENAME -file "t/t_vlt_warn.v"