From 063f9a7a4ce17c3229f40a8342366a9c45bf405a Mon Sep 17 00:00:00 2001
From: Ryszard Rozak <rrozak@antmicro.com>
Date: Thu, 16 Feb 2023 18:49:45 +0100
Subject: [PATCH] Fix dicts declared with ref type (#3960)

---
 src/V3Width.cpp                   |  3 +-
 test_regress/t/t_dict_ref_type.pl | 21 ++++++++++
 test_regress/t/t_dict_ref_type.v  | 68 +++++++++++++++++++++++++++++++
 3 files changed, 91 insertions(+), 1 deletion(-)
 create mode 100755 test_regress/t/t_dict_ref_type.pl
 create mode 100644 test_regress/t/t_dict_ref_type.v

diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index caeb19dfa..efcae0483 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -6209,7 +6209,8 @@ private:
 
     void checkClassAssign(AstNode* nodep, const char* side, AstNode* rhsp,
                           AstNodeDType* lhsDTypep) {
-        if (VN_IS(lhsDTypep, ClassRefDType) && !VN_IS(rhsp->dtypep(), ClassRefDType)) {
+        if (VN_IS(lhsDTypep, ClassRefDType)
+            && !(rhsp->dtypep() && VN_IS(rhsp->dtypep()->skipRefp(), ClassRefDType))) {
             if (auto* const constp = VN_CAST(rhsp, Const)) {
                 if (constp->num().isNull()) return;
             }
diff --git a/test_regress/t/t_dict_ref_type.pl b/test_regress/t/t_dict_ref_type.pl
new file mode 100755
index 000000000..1aa73f80a
--- /dev/null
+++ b/test_regress/t/t_dict_ref_type.pl
@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_dict_ref_type.v b/test_regress/t/t_dict_ref_type.v
new file mode 100644
index 000000000..b7dbc854f
--- /dev/null
+++ b/test_regress/t/t_dict_ref_type.v
@@ -0,0 +1,68 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2023 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+class Foo1;
+   int x = 1;
+   function int get_x;
+      return x;
+   endfunction
+endclass
+
+class Foo2;
+   int x = 2;
+   function int get_x;
+      return x;
+   endfunction
+endclass
+
+class Bar;
+   typedef Foo1 foo_t;
+   protected foo_t m_dict[int];
+
+   function void set(int key);
+      foo_t default_value = new;
+      m_dict[key] = default_value;
+   endfunction
+   function foo_t get(int key);
+      return m_dict[key];
+   endfunction
+endclass
+
+class Baz #(type T=Foo1);
+  protected T m_dict[int];
+
+  function void set(int key);
+     T default_value = new;
+     m_dict[key] = default_value;
+   endfunction
+   function T get(int key);
+      return m_dict[key];
+   endfunction
+endclass
+
+module t (/*AUTOARG*/
+   );
+
+   initial begin
+      Bar bar_i = new;
+      Baz baz_1_i = new;
+      Baz #(Foo2) baz_2_i = new;
+
+      bar_i.set(1);
+      baz_1_i.set(2);
+      baz_2_i.set(3);
+
+      if (bar_i.get(1).get_x() == 1 &&
+          baz_1_i.get(2).get_x() == 1 &&
+          baz_2_i.get(3).get_x() == 2) begin
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+      else begin
+         $stop;
+      end
+   end
+endmodule