From 058233fc87d45a47a1625c08b8a97a46afa0a855 Mon Sep 17 00:00:00 2001
From: Krzysztof Bieganski <kbieganski@antmicro.com>
Date: Tue, 6 Jun 2023 15:35:12 +0200
Subject: [PATCH] Set the global `usesTiming` flag if forks exist (#4274)

---
 src/V3Timing.cpp                              |  7 +++++
 .../t/t_timing_fork_no_timing_ctrl.pl         | 28 +++++++++++++++++++
 test_regress/t/t_timing_fork_no_timing_ctrl.v | 15 ++++++++++
 3 files changed, 50 insertions(+)
 create mode 100755 test_regress/t/t_timing_fork_no_timing_ctrl.pl
 create mode 100644 test_regress/t/t_timing_fork_no_timing_ctrl.v

diff --git a/src/V3Timing.cpp b/src/V3Timing.cpp
index fa9305000..fc2d06029 100644
--- a/src/V3Timing.cpp
+++ b/src/V3Timing.cpp
@@ -216,6 +216,13 @@ private:
         m_procp = nodep;
         iterateChildren(nodep);
     }
+    void visit(AstFork* nodep) override {
+        v3Global.setUsesTiming();  // Even if there are no event controls, we have to set this flag
+                                   // so that transformForks() in V3SchedTiming gets called and
+                                   // removes all forks and begins
+        if (nodep->isTimingControl() && m_procp) m_procp->user2(T_SUSP);
+        iterateChildren(nodep);
+    }
     void visit(AstNode* nodep) override {
         if (nodep->isTimingControl()) {
             v3Global.setUsesTiming();
diff --git a/test_regress/t/t_timing_fork_no_timing_ctrl.pl b/test_regress/t/t_timing_fork_no_timing_ctrl.pl
new file mode 100755
index 000000000..439181d0a
--- /dev/null
+++ b/test_regress/t/t_timing_fork_no_timing_ctrl.pl
@@ -0,0 +1,28 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2023 by Antmicro Ltd. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+if (!$Self->have_coroutines) {
+    skip("No coroutine support");
+}
+else {
+    compile(
+        verilator_flags2 => ["--exe --main --timing"],
+        make_main => 0,
+        );
+
+    execute(
+        check_finished => 1,
+        );
+}
+
+ok(1);
+1;
diff --git a/test_regress/t/t_timing_fork_no_timing_ctrl.v b/test_regress/t/t_timing_fork_no_timing_ctrl.v
new file mode 100644
index 000000000..2f9bb387c
--- /dev/null
+++ b/test_regress/t/t_timing_fork_no_timing_ctrl.v
@@ -0,0 +1,15 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2023 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+   initial
+      fork
+         begin
+            $write("*-* All Finished *-*\n");
+            $finish;
+         end
+      join_none
+endmodule