From 047a12cc62902940c6b6d797916203fcf147bcc3 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Wed, 13 Aug 2025 18:05:37 -0400
Subject: [PATCH] Fix variables hiding package imports (#6289).

---
 Changes                                     |  3 +-
 src/V3LinkDot.cpp                           |  2 +-
 test_regress/t/t_package_import_override.py | 16 +++++++
 test_regress/t/t_package_import_override.v  | 49 +++++++++++++++++++++
 4 files changed, 68 insertions(+), 2 deletions(-)
 create mode 100755 test_regress/t/t_package_import_override.py
 create mode 100644 test_regress/t/t_package_import_override.v

diff --git a/Changes b/Changes
index 3711067e3..cabe4e2ac 100644
--- a/Changes
+++ b/Changes
@@ -73,6 +73,7 @@ Verilator 5.039 devel
 * Fix dynamic cast purity (#6267). [Igor Zaworski, Antmicro Ltd.]
 * Fix same variable on the RHS forced to two different LHSs. (#6269). [Artur Bieniek, Antmicro Ltd.]
 * Fix spurious VPI value change callbacks (#6274). [Todd Strader]
+* Fix variables hiding package imports (#6289). [Johan Wouters]
 
 
 Verilator 5.038 2025-07-08
@@ -904,7 +905,7 @@ Verilator 5.016 2023-09-16
 * Fix nested assignments on the LHS (#4435). [Ryszard Rozak, Antmicro Ltd]
 * Fix false MULTITOP on bound interfaces (#4438). [Alex Solomatnikov]
 * Fix internal error on real conversion (#4447). [vdhotre-ventana]
-* Fix lifetime unknown error on enum.name (#4448). [jwoutersymatra]
+* Fix lifetime unknown error on enum.name (#4448). [Johan Wouters]
 * Fix unstable output of VHashSha256 (#4453). [Anthony Donlon]
 * Fix static cast from a stream type (#4469) (#4485). [Ryszard Rozak, Antmicro Ltd]
 * Fix error on enum with VARHIDDEN of cell (#4482). [Michail Rontionov]
diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp
index 6a53003d4..e6987da00 100644
--- a/src/V3LinkDot.cpp
+++ b/src/V3LinkDot.cpp
@@ -1462,7 +1462,7 @@ class LinkDotFindVisitor final : public VNVisitor {
             bool ins = false;
             if (!foundp) {
                 ins = true;
-            } else if (!findvarp && m_curSymp->findIdFlat(nodep->name())) {
+            } else if (!findvarp && m_curSymp->findIdFlat(nodep->name()) && !foundp->imported()) {
                 nodep->v3error("Unsupported in C: Variable has same name as "
                                << LinkDotState::nodeTextType(foundp->nodep()) << ": "
                                << nodep->prettyNameQ());
diff --git a/test_regress/t/t_package_import_override.py b/test_regress/t/t_package_import_override.py
new file mode 100755
index 000000000..6305a4fd8
--- /dev/null
+++ b/test_regress/t/t_package_import_override.py
@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('linter')
+
+test.compile(verilator_flags2=['--timing'])
+
+test.passes()
diff --git a/test_regress/t/t_package_import_override.v b/test_regress/t/t_package_import_override.v
new file mode 100644
index 000000000..3c3e5d10c
--- /dev/null
+++ b/test_regress/t/t_package_import_override.v
@@ -0,0 +1,49 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+package pkg;
+
+  typedef enum logic [1:0] {
+    INT,
+    BLA,
+    DUMMY
+  } t_shadowed_enum;
+
+endpackage
+
+module sub
+  import pkg::*;
+(
+    input logic INT,  // This is also in the pkg::t_shadowed_enum, but it shadows it
+    output logic dummy_out
+);
+
+  assign dummy_out = !INT;
+endmodule
+
+module t;
+  logic my_wire;
+  logic dummy_out;
+
+  sub i_sub (
+      .INT(my_wire),
+      .dummy_out(dummy_out)
+  );
+
+  initial begin
+    my_wire = 1'b0;
+
+    repeat (2) begin
+      my_wire = ~my_wire;
+      #1ns;
+      $display("my_wire = %b, dummy_out = %b", my_wire, dummy_out);
+    end
+
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+
+endmodule