From 0437d0abea0ee16c8bca44066e5a74d2f2abc7cb Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Tue, 15 Jan 2013 19:26:35 -0500
Subject: [PATCH] Fix pin width mismatch error, bug595.

---
 Changes                       |  3 +++
 src/V3Inst.cpp                |  1 -
 test_regress/t/t_inst_mism.pl | 18 +++++++++++++++
 test_regress/t/t_inst_mism.v  | 41 +++++++++++++++++++++++++++++++++++
 4 files changed, 62 insertions(+), 1 deletion(-)
 create mode 100755 test_regress/t/t_inst_mism.pl
 create mode 100644 test_regress/t/t_inst_mism.v

diff --git a/Changes b/Changes
index 0b162837b..ef6e0bc12 100644
--- a/Changes
+++ b/Changes
@@ -12,6 +12,9 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ***   Support bind, to module names only, bug602. [Ed Lander]
 
+***   Fix pin width mismatch error, bug595.  [Alex Solomatnikov]
+
+
 * Verilator 3.844 2013/01/09
 
 ***   Support "unsigned int" DPI import functions, msg966.  [Alex Lee]
diff --git a/src/V3Inst.cpp b/src/V3Inst.cpp
index c86ba9114..b7890aa1b 100644
--- a/src/V3Inst.cpp
+++ b/src/V3Inst.cpp
@@ -291,7 +291,6 @@ AstAssignW* V3Inst::pinReconnectSimple(AstPin* pinp, AstCell* cellp, AstNodeModu
 	    pinp->exprp(new AstVarRef (pinexprp->fileline(), newvarp, true));
 	} else {
 	    // V3 width should have range/extended to make the widths correct
-	    if (pinexprp->width() != pinVarp->width()) pinp->v3fatalSrc("Input pin width mismatch");
 	    assignp = new AstAssignW (pinp->fileline(),
 				      new AstVarRef(pinp->fileline(), newvarp, true),
 				      pinexprp);
diff --git a/test_regress/t/t_inst_mism.pl b/test_regress/t/t_inst_mism.pl
new file mode 100755
index 000000000..f91289753
--- /dev/null
+++ b/test_regress/t/t_inst_mism.pl
@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_inst_mism.v b/test_regress/t/t_inst_mism.v
new file mode 100644
index 000000000..bf1710b8b
--- /dev/null
+++ b/test_regress/t/t_inst_mism.v
@@ -0,0 +1,41 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2013 by Alex Solomatnikov.
+
+//bug595
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   logic [6-1:0] foo; initial foo = 20;
+
+   dut #(.W(6)) udut(.clk(clk),
+                     .foo(foo-16));
+endmodule
+
+module dut
+    #(parameter W = 1)
+    (input logic clk,
+     input logic [W-1:0] foo);
+
+    genvar i;
+    generate
+       for (i = 0; i < W; i++) begin
+          suba ua(.clk(clk), .foo(foo[i]));
+       end
+    endgenerate
+endmodule
+
+module suba
+  (input logic clk,
+   input logic foo);
+
+   always @(posedge clk) begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule