From 03ebd5554f22e28adbaa3493772d74428e8e5719 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Mon, 6 May 2019 19:21:25 -0400 Subject: [PATCH] Fix table compile error with multiinterfaces, bug1431. --- Changes | 2 + src/V3Table.cpp | 20 ++-- test_regress/t/t_interface_dups.pl | 20 ++++ test_regress/t/t_interface_dups.v | 167 +++++++++++++++++++++++++++++ 4 files changed, 203 insertions(+), 6 deletions(-) create mode 100755 test_regress/t/t_interface_dups.pl create mode 100644 test_regress/t/t_interface_dups.v diff --git a/Changes b/Changes index 78f6b8440..b4e4250ce 100644 --- a/Changes +++ b/Changes @@ -24,6 +24,8 @@ The contributors that suggested a given feature are shown in []. Thanks! **** Fix FST enums not displaying, bug1426. [Danilo Ramos] +**** Fix table compile error with multiinterfaces, bug1431. [Bogdan Vukobratovic] + * Verilator 4.012 2019-3-23 diff --git a/src/V3Table.cpp b/src/V3Table.cpp index eef32be6c..873be188a 100644 --- a/src/V3Table.cpp +++ b/src/V3Table.cpp @@ -226,7 +226,9 @@ private: } void createTableVars(AstNode* nodep) { - // Create table for each output + // Create table for each output + typedef std::map NameCounts; + NameCounts namecounts; for (std::deque::iterator it = m_outVarps.begin(); it!=m_outVarps.end(); ++it) { AstVarScope* outvscp = *it; AstVar* outvarp = outvscp->varp(); @@ -234,11 +236,17 @@ private: AstNodeArrayDType* dtypep = new AstUnpackArrayDType(fl, outvarp->dtypep(), new AstRange(fl, VL_MASK_I(m_inWidth), 0)); - v3Global.rootp()->typeTablep()->addTypesp(dtypep); - AstVar* tablevarp - = new AstVar(fl, AstVarType::MODULETEMP, - "__Vtable" + cvtToStr(m_modTables) +"_"+outvarp->name(), - dtypep); + v3Global.rootp()->typeTablep()->addTypesp(dtypep); + string name = "__Vtable"+cvtToStr(m_modTables)+"_"+outvarp->name(); + NameCounts::iterator nit = namecounts.find(name); + if (nit != namecounts.end()) { + // Multiple scopes can have same var name. We could append the + // scope name but that is very long, so just deduplicate. + name += "__dedup"+cvtToStr(++nit->second); + } else { + namecounts[name] = 0; + } + AstVar* tablevarp = new AstVar(fl, AstVarType::MODULETEMP, name, dtypep); tablevarp->isConst(true); tablevarp->isStatic(true); tablevarp->valuep(new AstInitArray(nodep->fileline(), dtypep, NULL)); diff --git a/test_regress/t/t_interface_dups.pl b/test_regress/t/t_interface_dups.pl new file mode 100755 index 000000000..1be18a66c --- /dev/null +++ b/test_regress/t/t_interface_dups.pl @@ -0,0 +1,20 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +scenarios(simulator => 1); + +compile( + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_interface_dups.v b/test_regress/t/t_interface_dups.v new file mode 100644 index 000000000..aa4281f1d --- /dev/null +++ b/test_regress/t/t_interface_dups.v @@ -0,0 +1,167 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [4:0] din_data = crc[4:0]; + wire [0:0] din_valid = crc[6]; + wire [0:0] dout0_ready = crc[16]; + wire [0:0] dout1_ready = crc[17]; + wire [0:0] dout2_ready = crc[18]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + logic din_ready; // From test of Test.v + logic [0:0] dout0_data; // From test of Test.v + logic dout0_valid; // From test of Test.v + logic [1:0] dout1_data; // From test of Test.v + logic dout1_valid; // From test of Test.v + logic [2:0] dout2_data; // From test of Test.v + logic dout2_valid; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .din_ready (din_ready), + .dout0_valid (dout0_valid), + .dout0_data (dout0_data[0:0]), + .dout1_valid (dout1_valid), + .dout1_data (dout1_data[1:0]), + .dout2_valid (dout2_valid), + .dout2_data (dout2_data[2:0]), + // Inputs + .din_valid (din_valid), + .din_data (din_data[4:0]), + .dout0_ready (dout0_ready), + .dout1_ready (dout1_ready), + .dout2_ready (dout2_ready)); + + // Aggregate outputs into a single result vector + wire [63:0] result = {48'h0, din_ready, + 2'd0, dout2_valid, dout2_data, + 2'd0, dout1_valid, dout1_data, + 2'd0, dout0_valid, dout0_data}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc<10) begin + sum <= '0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h6fd1bead9df31b07 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +interface dti + #(W_DATA = 64 + )(); + + logic [W_DATA-1:0] data; + logic valid; + logic ready; + + modport producer (output data, + output valid, + input ready); + modport consumer (input data, + input valid, + output ready); +endinterface : dti + +module Test + ( + output logic din_ready, + input logic din_valid, + input logic [4:0] din_data, + input logic dout0_ready, + output logic dout0_valid, + output logic [0:0] dout0_data, + input logic dout1_ready, + output logic dout1_valid, + output logic [1:0] dout1_data, + input logic dout2_ready, + output logic dout2_valid, + output logic [2:0] dout2_data + ); + + // Interface declarations + dti #(.W_DATA(5)) din(); + dti #(.W_DATA(1)) dout0(); + dti #(.W_DATA(2)) dout1(); + dti #(.W_DATA(3)) dout2(); + + // Interface wiring to top level ports + assign din.valid = din_valid; + assign din.data = din_data; + assign din_ready = din.ready; + + assign dout0_valid = dout0.valid; + assign dout0_data = dout0.data; + assign dout0.ready = dout0_ready; + + assign dout1_valid = dout1.valid; + assign dout1_data = dout1.data; + assign dout1.ready = dout1_ready; + + assign dout2_valid = dout2.valid; + assign dout2_data = dout2.data; + assign dout2.ready = dout2_ready; + + assign din.ready = 0; + assign dout0.data = 0; + assign dout1.data = 0; + assign dout2.data = 0; + + typedef struct packed { + logic [1:0] ctrl; + logic [2:0] data; + } din_t; + + din_t din_s; + assign din_s = din.data; + + always_comb begin + dout0.valid = 0; + dout1.valid = 0; + dout2.valid = 0; + + case (din_s.ctrl) + 0 : dout0.valid = din.valid; + 1 : dout1.valid = din.valid; + 2 : dout2.valid = din.valid; + default: ; + endcase + end +endmodule