diff --git a/Changes b/Changes index 05074b8f9..753fe9f14 100644 --- a/Changes +++ b/Changes @@ -18,12 +18,14 @@ indicates the contributor was also the author of the fix; Thanks! *** Add --no-trace-params. -*** Add assertions on 'unique if', bug725. [Jeff Bush] +*** Add assertions on 'unique if', bug725. [Jeff Bush] *** Add PINCONNECTEMPTY warning. [Holger Waechtler] *** Support parameter arrays, bug683. [Jeremy Bennett] +*** Fix begin_keywords "1800+VAMS", msg1211. + **** Documentation fixes, bug723. [Glen Gibb] **** Support {} in always sensitivity lists, bug745. [Igor Lesik] @@ -161,17 +163,17 @@ indicates the contributor was also the author of the fix; Thanks! * Verilator 3.847 2013-05-11 *** Add ALWCOMBORDER warning. [KC Buckenmaier] - + *** Add --pins-sc-uint and --pins-sc-biguint, bug638. [Alex Hornung] - + **** Support "signal[vec]++". - + **** Fix simulation error when inputs and MULTIDRIVEN, bug634. [Ted Campbell] - + **** Fix module resolution with __, bug631. [Jason McMullan] - + **** Fix packed array non-zero right index select crash, bug642. [Krzysztof Jankowski] - + **** Fix nested union crash, bug643. [Krzysztof Jankowski] @@ -487,7 +489,7 @@ indicates the contributor was also the author of the fix; Thanks! *** Support $fopen and I/O with integer instead of `verilator_file_descriptor. *** Support coverage in -cc and -sc output modes. [John Li] - Note this requires SystemPerl 1.338 or newer. + Note this requires SystemPerl 1.338 or newer. **** Fix vpi_register_cb using bad s_cb_data, bug370. [by Thomas Watts] diff --git a/src/verilog.l b/src/verilog.l index 1dcdc34d2..c3a3bda1e 100644 --- a/src/verilog.l +++ b/src/verilog.l @@ -138,7 +138,7 @@ void yyerrorf(const char* format, ...) { %s V95 V01 V05 S05 S09 S12 %s STRING ATTRMODE TABLE -%s VA5 SA9 PSL VLT +%s VA5 SAX PSL VLT %s SYSCHDR SYSCINT SYSCIMP SYSCIMPH SYSCCTOR SYSCDTOR %s IGNORE @@ -179,7 +179,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} /************************************************************************/ /* Verilog 1995 */ -{ +{ {ws} { } /* otherwise ignore white-space */ {crnl} { NEXTLINE(); } /* Count line numbers */ /* Extensions to Verilog set, some specified by PSL */ @@ -352,7 +352,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} } /* Verilog 2001 */ -{ +{ /* System Tasks */ "$signed" { FL; return yD_SIGNED; } "$unsigned" { FL; return yD_UNSIGNED; } @@ -383,13 +383,13 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} } /* Verilog 2005 */ -{ +{ /* Keywords */ "uwire" { FL; return yWIRE; } } /* System Verilog 2005 */ -{ +{ /* System Tasks */ "$bits" { FL; return yD_BITS; } "$clog2" { FL; return yD_CLOG2; } @@ -506,7 +506,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} } /* SystemVerilog 2005 ONLY not PSL; different rules for PSL as specified below */ -{ +{ /* Keywords */ "assert" { FL; return yASSERT; } "const" { FL; return yCONST__LEX; } @@ -521,7 +521,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} } /* SystemVerilog 2009 */ -{ +{ /* Keywords */ "global" { FL; return yGLOBAL__LEX; } "unique0" { FL; return yUNIQUE0; } @@ -550,7 +550,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} } /* System Verilog 2012 */ -{ +{ /* Keywords */ "implements" { yyerrorf("Unsupported: SystemVerilog 2012 reserved word not implemented: %s",yytext); } "interconnect" { yyerrorf("Unsupported: SystemVerilog 2012 reserved word not implemented: %s",yytext); } @@ -559,7 +559,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} } /* Default PLI rule */ -{ +{ "$"[a-zA-Z_$][a-zA-Z0-9_$]* { string str (yytext,yyleng); yylval.strp = PARSEP->newString(AstNode::encodeName(str)); // Lookup unencoded name including the $, to avoid hitting normal signals @@ -572,7 +572,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} /************************************************************************/ /* AMS */ -{ +{ /* Generic unsupported warnings */ "above" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); } "abs" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); } @@ -666,7 +666,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} /* PSL */ /*Entry into PSL; mode change */ -{ +{ "psl" { yy_push_state(PSL); FL; return yPSL; } } @@ -755,7 +755,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} /* Meta comments */ /* Converted from //{cmt}verilator ...{cmt} by preprocessor */ -{ +{ "/*verilator"{ws}*"*/" {} /* Ignore empty comments, may be `endif // verilator */ "/*verilator clock_enable*/" { FL; return yVL_CLOCK_ENABLE; } "/*verilator coverage_block_off*/" { FL; return yVL_COVERAGE_BLOCK_OFF; } @@ -790,11 +790,11 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} /************************************************************************/ /* Single character operator thingies */ -{ +{ "{" { FL; return yytext[0]; } "}" { FL; return yytext[0]; } } -{ +{ "!" { FL; return yytext[0]; } "#" { FL; return yytext[0]; } "$" { FL; return yytext[0]; } @@ -826,7 +826,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} /* Operators and multi-character symbols */ /* Verilog 1995 Operators */ -{ +{ "&&" { FL; return yP_ANDAND; } "||" { FL; return yP_OROR; } "<=" { FL; return yP_LTE; } @@ -848,7 +848,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} } /* Verilog 2001 Operators */ -{ +{ "<<<" { FL; return yP_SLEFT; } ">>>" { FL; return yP_SSRIGHT; } "**" { FL; return yP_POW; } @@ -858,7 +858,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} } /* SystemVerilog Operators */ -{ +{ "'" { FL; return yP_TICK; } "'{" { FL; return yP_TICKBRA; } "==?" { FL; return yP_WILDEQUAL; } @@ -907,7 +907,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} } /* Identifiers and numbers */ -{ +{ {escid} { FL; yylval.strp = PARSEP->newString (AstNode::encodeName(string(yytext+1))); // +1 to skip the backslash return yaID__LEX; @@ -980,7 +980,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} /************************************************************************/ /* Attributes */ /* Note simulators vary in support for "(* /_*something*_/ foo*)" where _ doesn't exist */ -{ +{ "(*"({ws}|{crnl})*({id}|{escid}) { yymore(); yy_push_state(ATTRMODE); } // Doesn't match (*), but (* attr_spec } @@ -997,7 +997,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} /* Preprocessor */ /* Common for all SYSC header states */ /* OPTIMIZE: we return one per line, make it one for the entire block */ -{ +{ "`accelerate" { } // Verilog-XL compatibility "`autoexpand_vectornets" { } // Verilog-XL compatibility "`celldefine" { PARSEP->inCellDefine(true); } @@ -1042,7 +1042,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} "`begin_keywords"[ \t]*\"1800-2005\" { yy_push_state(S05); PARSEP->pushBeginKeywords(YY_START); } "`begin_keywords"[ \t]*\"1800-2009\" { yy_push_state(S09); PARSEP->pushBeginKeywords(YY_START); } "`begin_keywords"[ \t]*\"1800-2012\" { yy_push_state(S12); PARSEP->pushBeginKeywords(YY_START); } - "`begin_keywords"[ \t]*\"1800+VAMS\" { yy_push_state(SA9); PARSEP->pushBeginKeywords(YY_START); } + "`begin_keywords"[ \t]*\"1800[+]VAMS\" { yy_push_state(SAX); PARSEP->pushBeginKeywords(YY_START); } /*Latest SV*/ "`end_keywords" { yy_pop_state(); if (!PARSEP->popBeginKeywords()) yyerrorf("`end_keywords when not inside `begin_keywords block"); } /* Verilator */ @@ -1073,7 +1073,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} /************************************************************************/ /* Default rules - leave last */ -{ +{ "`"[a-zA-Z_0-9]+ { FL; yyerrorf("Define or directive not defined: %s",yytext); } "//"[^\n]* { } /* throw away single line comments */ . { FL; return yytext[0]; } /* return single char ops. */ diff --git a/test_regress/t/t_dpi_vams.cpp b/test_regress/t/t_dpi_vams.cpp new file mode 100644 index 000000000..bcd243023 --- /dev/null +++ b/test_regress/t/t_dpi_vams.cpp @@ -0,0 +1,56 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +// +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2010 by Wilson Snyder. + +#include +#include "Vt_dpi_vams.h" + +//====================================================================== + +#if defined(VERILATOR) +# include "Vt_dpi_vams__Dpi.h" +#elif defined(VCS) +# include "../vc_hdrs.h" +#elif defined(CADENCE) +# define NEED_EXTERNS +#else +# error "Unknown simulator for DPI test" +#endif + +#ifdef NEED_EXTERNS +extern "C" { + extern void dpii_call (double in, double* outp); +} +#endif + +void dpii_call (double in, double* outp) { + *outp = in + 0.1; +} +//====================================================================== + +unsigned int main_time = 0; + +double sc_time_stamp () { + return main_time; +} + +VM_PREFIX* topp = NULL; + +int main (int argc, char *argv[]) { + topp = new VM_PREFIX; + + Verilated::debug(0); + + topp->in = 1.1; + topp->eval(); + if (topp->out != 1.2) { + VL_PRINTF("*-* All Finished *-*\n"); + topp->final(); + } else { + vl_fatal(__FILE__,__LINE__,"top", "Unexpected results\n"); + } + return 0; +} diff --git a/test_regress/t/t_dpi_vams.pl b/test_regress/t/t_dpi_vams.pl new file mode 100755 index 000000000..653add643 --- /dev/null +++ b/test_regress/t/t_dpi_vams.pl @@ -0,0 +1,21 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +compile ( + make_top_shell => 0, + make_main => 0, + verilator_flags2 => ["--exe","$Self->{t_dir}/$Self->{name}.cpp"], + ); + +execute ( + check_finished=>1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_dpi_vams.v b/test_regress/t/t_dpi_vams.v new file mode 100644 index 000000000..4621d82ec --- /dev/null +++ b/test_regress/t/t_dpi_vams.v @@ -0,0 +1,28 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +//`begin_keywords "VAMS-2.3" +`begin_keywords "1800+VAMS" + +module t (/*AUTOARG*/ + // Outputs + out, + // Inputs + in + ); + + input in; + wreal in; + output out; + wreal out; + + import "DPI-C" context function void dpii_call(input real in, output real out); + + initial begin + dpii_call(in,out); + $finish; + end + +endmodule