From 01e9bc485547475d9a2ecb8cfd09e1217f60ca22 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Tue, 13 Mar 2007 18:21:23 +0000 Subject: [PATCH] Support while and do-while loops. git-svn-id: file://localhost/svn/verilator/trunk/verilator@905 77ca24e4-aefa-0310-84f0-b9a241c72d87 --- Changes | 2 ++ bin/verilator | 13 +++++++------ src/verilog.l | 4 ++-- src/verilog.y | 4 ++++ test_regress/t/t_for_count.v | 25 +++++++++++++++++++++++-- 5 files changed, 38 insertions(+), 10 deletions(-) diff --git a/Changes b/Changes index b58887c27..04506c9bd 100644 --- a/Changes +++ b/Changes @@ -5,6 +5,8 @@ indicates the contributor was also the author of the fix; Thanks! * Verilator 3.64** +*** Support while and do-while loops. + **** Fix dotted bit reference to local memory. [Eugene Weber] * Verilator 3.640 3/12/2007 diff --git a/bin/verilator b/bin/verilator index 3c1c3fbcd..e0881c518 100755 --- a/bin/verilator +++ b/bin/verilator @@ -1373,12 +1373,13 @@ This section describes specific limitations for each language keyword. =over 4 -=item always always_comb always_ff always_latch and assign begin buf case -casex casez default defparam else end endcase endfunction endgenerate -endmodule endspecify endtask final for function generate genvar if initial -inout input integer localparam macromodule module nand negedge nor not or -output parameter posedge reg scalared signed supply0 supply1 task tri -vectored wire xnor xor +=item always, always_comb, always_ff, always_latch, and, assign, begin, +buf, case, casex, casez, default, defparam, do-while, else, end, endcase, +endfunction, endgenerate, endmodule, endspecify, endtask, final, for, +function, generate, genvar, if, initial, inout, input, integer, localparam, +macromodule, module, nand, negedge, nor, not, or, output, parameter, +posedge, reg, scalared, signed, supply0, supply1, task, tri, vectored, +while, wire, xnor, xor Generally supported. diff --git a/src/verilog.l b/src/verilog.l index 1608dadc8..fcfe55168 100644 --- a/src/verilog.l +++ b/src/verilog.l @@ -180,6 +180,7 @@ escid \\[^ \t\f\r\n]+ "task" {yylval.fileline = CRELINE(); return yTASK;} "tri" {yylval.fileline = CRELINE(); return yTRI;} "vectored" {yylval.fileline = CRELINE(); return yVECTORED;} + "while" {yylval.fileline = CRELINE(); return yWHILE;} "wire" {yylval.fileline = CRELINE(); return yWIRE;} "xnor" {yylval.fileline = CRELINE(); return yXNOR;} "xor" {yylval.fileline = CRELINE(); return yXOR;} @@ -250,7 +251,6 @@ escid \\[^ \t\f\r\n]+ "wand" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} "weak0" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} "weak1" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} - "while" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} "wor" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} } @@ -308,6 +308,7 @@ escid \\[^ \t\f\r\n]+ "always_comb" {yylval.fileline = CRELINE(); return yALWAYS;} "always_ff" {yylval.fileline = CRELINE(); return yALWAYS;} "always_latch" {yylval.fileline = CRELINE(); return yALWAYS;} + "do" {yylval.fileline = CRELINE(); return yDO;} "final" {yylval.fileline = CRELINE(); return yFINAL;} /* Generic unsupported warnings */ /* Note assert_strobe was in SystemVerilog 3.1, but removed for SystemVerilog 2005 */ @@ -328,7 +329,6 @@ escid \\[^ \t\f\r\n]+ "coverpoint" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} "cross" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} "dist" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "do" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} "endcass" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} "endclocking" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} "endgroup" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} diff --git a/src/verilog.y b/src/verilog.y index b50cf9056..e6489c130 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -140,10 +140,12 @@ class AstSenTree; %token yASSERT "assert" %token yCLOCK "clock" %token yCOVER "cover" +%token yDO "do" %token yFINAL "final" %token yPSL "psl" %token yREPORT "report" %token yTRUE "true" +%token yWHILE "while" %token yPSL_ASSERT "PSL assert" @@ -716,6 +718,8 @@ stateCaseForIf: caseStmt caseAttrE caseList yENDCASE { $$ = $1; $1->addItemsp($3 { $$ = new AstFor($1, new AstAssign($4,$3,$5) ,$7, new AstAssign($10,$9,$11) ,$13);} + | yWHILE '(' expr ')' stmtBlock { $$ = new AstWhile($1,$3,$5);} + | yDO stmtBlock yWHILE '(' expr ')' { $$ = $2->cloneTree(true); $$->addNext(new AstWhile($1,$5,$2));} ; assertStmt: yASSERT '(' expr ')' stmtBlock %prec yLOWER_THAN_ELSE { $$ = new AstVAssert($1,$3,$5, V3Parse::createDisplayError($1)); } diff --git a/test_regress/t/t_for_count.v b/test_regress/t/t_for_count.v index be0f527d3..82459c528 100644 --- a/test_regress/t/t_for_count.v +++ b/test_regress/t/t_for_count.v @@ -1,4 +1,4 @@ -// $Id:$ +// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -34,6 +34,27 @@ module t (/*AUTOARG*/ end end + // While loop + integer w; + initial begin + while (w<10) w=w+1; + if (w!=10) $stop; + while (w<20) begin w=w+2; end + while (w<20) begin w=w+99999; end // NEVER + if (w!=20) $stop; + end + + // Do-While loop + integer dw; + initial begin + do dw=dw+1; while (dw<10); + if (dw!=10) $stop; + do dw=dw+2; while (dw<20); + if (dw!=20) $stop; + do dw=dw+5; while (dw<20); // Once + if (dw!=25) $stop; + end + always @ (posedge clk) begin cam_lookup_hit_vector <= 0; if (cyc!=0) begin @@ -49,7 +70,7 @@ module t (/*AUTOARG*/ if (hit_count != 32'd5) $stop; if (wide_for_count != 32'h80) $stop; end - if (cyc==4) begin + if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end