From 12337ecb1ef3711c78c6a5d710b97bfa43aff921 Mon Sep 17 00:00:00 2001
From: Todd Strader <tstrader@hudson-trading.com>
Date: Thu, 29 Jan 2026 15:14:35 -0500
Subject: [PATCH] Fix iface internal type reference

---
 src/V3LinkDotIfaceCapture.cpp                 |  3 ++-
 .../t/t_interface_type_ref_internal.py        | 18 +++++++++++++++
 .../t/t_interface_type_ref_internal.v         | 23 +++++++++++++++++++
 3 files changed, 43 insertions(+), 1 deletion(-)
 create mode 100755 test_regress/t/t_interface_type_ref_internal.py
 create mode 100644 test_regress/t/t_interface_type_ref_internal.v

diff --git a/src/V3LinkDotIfaceCapture.cpp b/src/V3LinkDotIfaceCapture.cpp
index 437acea30..9c6a6bad0 100644
--- a/src/V3LinkDotIfaceCapture.cpp
+++ b/src/V3LinkDotIfaceCapture.cpp
@@ -56,7 +56,8 @@ string V3LinkDotIfaceCapture::extractIfacePortName(const string& dotText) {
 void V3LinkDotIfaceCapture::add(AstRefDType* refp, AstCell* cellp, AstNodeModule* ownerModp,
                                 AstTypedef* typedefp, AstNodeModule* typedefOwnerModp,
                                 AstVar* ifacePortVarp) {
-    if (!refp) return;
+    // TODO -- probably classes too
+    if (!refp || cellp->modp() == ownerModp) return;
     if (!typedefp) typedefp = refp->typedefp();
     if (!typedefOwnerModp && typedefp) typedefOwnerModp = findOwnerModule(typedefp);
     s_map[refp] = CapturedIfaceTypedef{
diff --git a/test_regress/t/t_interface_type_ref_internal.py b/test_regress/t/t_interface_type_ref_internal.py
new file mode 100755
index 000000000..84b274f68
--- /dev/null
+++ b/test_regress/t/t_interface_type_ref_internal.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2025 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile()
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_interface_type_ref_internal.v b/test_regress/t/t_interface_type_ref_internal.v
new file mode 100644
index 000000000..a9d825171
--- /dev/null
+++ b/test_regress/t/t_interface_type_ref_internal.v
@@ -0,0 +1,23 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain.
+// SPDX-FileCopyrightText: 2026 Wilson Snyder
+// SPDX-License-Identifier: CC0-1.0
+
+interface ifc #(parameter int width)(input logic [width-1:0] b);
+  logic [width-1:0] a;
+  typedef logic[width-1:0] type_t;
+  always_comb a = type_t'(b);
+endinterface
+
+module t;
+  logic [15:0] x;
+  ifc #(.width(16)) x_ifc(x);
+  logic [7:0] y;
+  ifc #(.width(8)) y_ifc(y);
+
+  initial begin
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+endmodule