diff --git a/src/V3AstNodes.h b/src/V3AstNodes.h
index 8155a7bbb..ff8f151a3 100644
--- a/src/V3AstNodes.h
+++ b/src/V3AstNodes.h
@@ -1288,7 +1288,7 @@ private:
     string	m_name;		// Cell name
     string	m_origName;	// Original name before dot addition
     string	m_modName;	// Module the cell instances
-    AstNodeModule*	m_modp;		// [AfterLink] Pointer to module instanced
+    AstNodeModule* m_modp;	// [AfterLink] Pointer to module instanced
 public:
     AstCell(FileLine* fl, const string& instName, const string& modName,
 	    AstPin* pinsp, AstPin* paramsp, AstRange* rangep)
diff --git a/test_regress/t/t_interface.pl b/test_regress/t/t_interface.pl
index 5277b6ecb..3bd8e9cf6 100755
--- a/test_regress/t/t_interface.pl
+++ b/test_regress/t/t_interface.pl
@@ -10,11 +10,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 $Self->{vlt} and $Self->unsupported("Verilator unsupported, bug102");
 
 compile (
-	 );
+    );
 
 execute (
-	 check_finished=>1,
-     );
+    check_finished=>1,
+    );
 
 ok(1);
 1;
diff --git a/test_regress/t/t_interface2.pl b/test_regress/t/t_interface2.pl
new file mode 100755
index 000000000..555a5a49b
--- /dev/null
+++ b/test_regress/t/t_interface2.pl
@@ -0,0 +1,21 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} and $Self->unsupported("Verilator unsupported, bug102");
+
+compile (
+    v_flags => []
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_interface2.v b/test_regress/t/t_interface2.v
new file mode 100644
index 000000000..a0c94d44b
--- /dev/null
+++ b/test_regress/t/t_interface2.v
@@ -0,0 +1,68 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2010 by Wilson Snyder.
+
+interface counter_io;
+   logic [3:0] value;
+   logic       reset;
+endinterface
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+   integer cyc=1;
+
+   counter_io c1_data();
+   counter_io c2_data();
+
+   counter    c1 (.clkm(clk),
+		  .c_data(c1_data),
+		  .i_value(4'h1));
+   counter    c2 (.clkm(clk),
+		  .c_data(c2_data),
+		  .i_value(4'h2));
+
+   initial begin
+      c1_data.value = 4'h4;
+      c2_data.value = 4'h5;
+   end
+
+   always @ (posedge clk) begin
+      cyc <= cyc + 1;
+      if (cyc<2) begin
+	 c1_data.reset <= 1;
+	 c2_data.reset <= 1;
+      end
+      if (cyc==2) begin
+	 c1_data.reset <= 0;
+	 c2_data.reset <= 0;
+      end
+      if (cyc==20) begin
+	 $write("[%0t] c1 cyc%0d: %0x %0x\n", $time, cyc, c1_data.value, c1_data.reset);
+	 $write("[%0t] c2 cyc%0d: %0x %0x\n", $time, cyc, c2_data.value, c2_data.reset);
+	 if (c1_data.value != 2) $stop;
+	 if (c2_data.value != 3) $stop;
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+      end
+   end
+endmodule
+
+module counter
+  (
+   input clkm,
+   counter_io c_data,
+   input logic [3:0] i_value
+   );
+
+   always @ (posedge clkm) begin
+      if (c_data.reset)
+	c_data.value <= i_value;
+      else
+	c_data.value <= c_data.value + 1;
+   end
+endmodule : counter
diff --git a/test_regress/t/t_interface_inl.pl b/test_regress/t/t_interface_inl.pl
new file mode 100755
index 000000000..860bef48e
--- /dev/null
+++ b/test_regress/t/t_interface_inl.pl
@@ -0,0 +1,24 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} and $Self->unsupported("Verilator unsupported, bug102");
+
+top_filename("t/t_interface.v");
+
+compile (
+    # Avoid inlining so we find bugs in the non-inliner connection code
+    v_flags => ["-Oi"],
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_interface_modport.pl b/test_regress/t/t_interface_modport.pl
new file mode 100755
index 000000000..d39b00a42
--- /dev/null
+++ b/test_regress/t/t_interface_modport.pl
@@ -0,0 +1,21 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} and $Self->unsupported("Verilator unsupported, bug102");
+
+compile (
+    v_flags => [],
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_interface_modport.v b/test_regress/t/t_interface_modport.v
new file mode 100644
index 000000000..b1479e2fc
--- /dev/null
+++ b/test_regress/t/t_interface_modport.v
@@ -0,0 +1,70 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2010 by Wilson Snyder.
+
+interface counter_io;
+   logic [3:0] value;
+   logic       reset;
+   modport counter_side (input reset, output value);
+   modport core_side (output reset, input value);
+endinterface
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+   integer cyc=1;
+
+   counter_io c1_data();
+   counter_io c2_data();
+
+   counter    c1 (.clkm(clk),
+		  .c_data(c1_data),
+		  .i_value(4'h1));
+   counter    c2 (.clkm(clk),
+		  .c_data(c2_data.counter_side),
+		  .i_value(4'h2));
+
+   initial begin
+      c1_data.value = 4'h4;
+      c2_data.value = 4'h5;
+   end
+
+   always @ (posedge clk) begin
+      cyc <= cyc + 1;
+      if (cyc<2) begin
+	 c1_data.reset <= 1;
+	 c2_data.reset <= 1;
+      end
+      if (cyc==2) begin
+	 c1_data.reset <= 0;
+	 c2_data.reset <= 0;
+      end
+      if (cyc==20) begin
+	 $write("[%0t] c1 cyc%0d: %0x %0x\n", $time, cyc, c1_data.value, c1_data.reset);
+	 $write("[%0t] c2 cyc%0d: %0x %0x\n", $time, cyc, c2_data.value, c2_data.reset);
+	 if (c1_data.value != 2) $stop;
+	 if (c2_data.value != 3) $stop;
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+      end
+   end
+endmodule
+
+module counter
+  (
+   input clkm,
+   counter_io c_data,
+   input logic [3:0] i_value
+   );
+
+   always @ (posedge clkm) begin
+      if (c_data.reset)
+	c_data.value <= i_value;
+      else
+	c_data.value <= c_data.value + 1;
+   end
+endmodule : counter
diff --git a/test_regress/t/t_interface_modport_inl.pl b/test_regress/t/t_interface_modport_inl.pl
new file mode 100755
index 000000000..37f649962
--- /dev/null
+++ b/test_regress/t/t_interface_modport_inl.pl
@@ -0,0 +1,24 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} and $Self->unsupported("Verilator unsupported, bug102");
+
+top_filename("t/t_interface_modport.v");
+
+compile (
+    # Avoid inlining so we find bugs in the non-inliner connection code
+    v_flags => ["-Oi"],
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_interface_top.pl b/test_regress/t/t_interface_top.pl
new file mode 100755
index 000000000..96dae041e
--- /dev/null
+++ b/test_regress/t/t_interface_top.pl
@@ -0,0 +1,17 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} and $Self->unsupported("Verilator unsupported, bug102");
+
+compile (
+    v_flags => ["--lint-only"]
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_interface_top.v b/test_regress/t/t_interface_top.v
new file mode 100644
index 000000000..f0cccaed7
--- /dev/null
+++ b/test_regress/t/t_interface_top.v
@@ -0,0 +1,22 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2010 by Wilson Snyder.
+
+interface counter_io;
+   logic [3:0] value;
+   logic       reset;
+   modport counter_side (input reset, output value);
+   modport core_side (output reset, input value);
+endinterface
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk,
+   counter_io.counter_side c_data
+   );
+
+   input clk;
+   integer cyc=1;
+
+endmodule