2019-05-03 00:45:32 +02:00
|
|
|
%Warning-WIDTH: t/t_lint_repeat_bad.v:17: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS's VARREF 'a' generates 2 bits.
|
2019-07-26 18:52:38 +02:00
|
|
|
: ... In instance t.sub2
|
2019-07-15 03:42:03 +02:00
|
|
|
wire [0:0] b = a;
|
|
|
|
|
^
|
2019-05-31 02:30:59 +02:00
|
|
|
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
|
2019-05-03 00:45:32 +02:00
|
|
|
%Error: Exiting due to
|
