41 lines
861 B
Systemverilog
41 lines
861 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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interface backdoor_if;
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logic [15:0] signal1;
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logic [15:0] signal2;
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assign signal1 = t.child1.sub1.signal3;
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assign signal2 = t.child2.sub2.signal3;
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function int get_size_signal1();
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return $bits(signal1);
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endfunction
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endinterface
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module sub #(
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parameter DELAY = 10
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) ();
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logic [15:0] signal3;
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endmodule
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package tests_pkg;
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class signal1_backdoor;
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virtual backdoor_if vif;
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virtual function int get_signal_size();
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return vif.get_size_signal1();
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endfunction
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endclass
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endpackage
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module child ();
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sub #(10) sub1 ();
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sub #(25) sub2 ();
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endmodule
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module t;
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child child1 ();
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child child2 ();
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endmodule
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