27 lines
488 B
Plaintext
27 lines
488 B
Plaintext
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`timescale 1ns/1ps
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module top(
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input logic clk,
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input logic rst,
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output logic top_out
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);
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submod u_submod (
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.clk (clk),
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.rst (rst),
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.out_signal(top_out)
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);
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endmodule
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`timescale 1ns/1ps
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module submod(
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input logic clk,
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input logic rst,
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output logic out_signal
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);
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always_ff @(posedge clk or posedge rst) begin
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if (rst) begin
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out_signal <= 1'b0;
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end else begin
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out_signal <= ~out_signal;
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end
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end
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endmodule
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