22 lines
496 B
Systemverilog
22 lines
496 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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module t ( /*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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bit val;
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always @(negedge clk) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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assert property (@(posedge clk) ##1 not val) $display("[%0t] single delay with negated var stmt, fileline:%d", $time, `__LINE__);
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endmodule
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