21 lines
511 B
Systemverilog
21 lines
511 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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`timescale 1ns/1ps
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module submod(/*AUTOARG*/
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input logic clk,
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input logic rst,
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output logic out_signal
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);
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always_ff @(posedge clk or posedge rst) begin
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if (rst) begin
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out_signal <= 1'b0;
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end else begin
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out_signal <= ~out_signal;
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end
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end
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endmodule
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