14 lines
346 B
Systemverilog
14 lines
346 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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function void imp_func_conflict();
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endfunction
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`default_nettype wire
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assign imp_func_conflict = 1'b1;
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endmodule
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