40 lines
1000 B
Systemverilog
40 lines
1000 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// verilator lint_off WIDTH
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module pipe_id_match #(
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parameter type ID_T = logic [4:0],
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parameter ID_T STAGE_IDS[3:0][1:0] = '{default: 1}
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);
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generate
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$info("%m %s:%0d: 4=%0d 2=%0d STAGE_IDS=%p", "test.sv", 25, 4, 2, STAGE_IDS);
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endgenerate
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endmodule
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module t #(
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parameter type ID_T = logic [4:0]
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);
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function automatic ID_T [3:0][1:0] gen_stage_ids();
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for (int unsigned st = 0; st < 4; st++) begin
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for (int unsigned id = 0; id < 2; id++) begin
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gen_stage_ids[st][id] = 3 + ((st + 1) * 2) + id - (3 + ((st + 1) * 2) + id < 18 ? 0 : 18);
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end
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end
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endfunction
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localparam ID_T STAGE_IDS[3:0][1:0] = gen_stage_ids();
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pipe_id_match #(
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.ID_T(ID_T),
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.STAGE_IDS(STAGE_IDS)
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) pipe (
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.*);
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initial $finish;
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endmodule
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