verilator/test_regress/t/t_interface_wire_bad.out

%Error: t/t_interface_wire_bad.v:17:20: Operator ASSIGNW expected non-interface on Assign RHS but 'a' is an interface.
                                      : ... note: In instance 't'
   17 |    wire wbad = sub.a;
      |                    ^
        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to