18 lines
582 B
Plaintext
18 lines
582 B
Plaintext
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`verilator_config
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instrument -callback "instrument_var" -id 0 -target "top_module.outa"
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instrument -callback "instrument_var" -id 0 -target "top.a1.b1.out"
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instrument -callback "instrument_var" -id 0 -target "top_module.a3.b1.out"
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instrument -callback "instrument_var" -id 0 -target "top_module.a1.b3.out"
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instrument -callback "instrument_var" -id 0 -target "top_module.a1.b1.clk"
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