2020-03-21 16:24:24 +01:00
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%Warning-WIDTH: t/t_lint_repeat_bad.v:18:17: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS's VARREF 'a' generates 2 bits.
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2022-03-05 15:08:49 +01:00
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: ... In instance t.sub3
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2020-04-04 02:07:46 +02:00
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18 | wire [0:0] b = a;
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2021-04-24 16:33:49 +02:00
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... For warning description see https://verilator.org/warn/WIDTH?v=latest
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2019-05-31 02:30:59 +02:00
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... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
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2019-05-03 00:45:32 +02:00
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%Error: Exiting due to
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