20 lines
468 B
Systemverilog
20 lines
468 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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export "DPI-C" task cfunc_finish; // this is just so the task becomes AstCFunc, we don't really use the export
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task cfunc_finish;
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$finish;
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endtask
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initial begin
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fork
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cfunc_finish();
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join_none
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#1 $stop;
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end
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endmodule
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