// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2019 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0

int a = -12'd1;
int b = 65536'd1;
int c = 1231232312312312'd1;
int e = 12'1;
int f = 12'0;
int g = 12'z;
int h = 12'x;
