// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2012 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0


module t (
    r
);

  output r;

  reg r;

  assign r = 1'b0;  // Bad

endmodule
