// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2022 Antmicro Ltd
// SPDX-License-Identifier: CC0-1.0

module t (
    input clk
);

  clocking cb @(posedge clk);
    output posedge #1 a;
    output negedge #1 b;
    output edge #1 b;
  endclocking

endmodule
