#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2024 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0

import vltest_bootstrap

test.scenarios('simulator')

test.compile(verilator_flags2=["--trace-vcd", "--trace-structs", "--output-split-ctrace", "32"])

if test.vlt_all:
    test.file_grep_count(
        test.obj_dir + "/V" + test.name + "__Trace__0.cpp",
        # dtype sub funcs prevent trace_chg splitting, but --vltmt still forces three of them
        r'void Vt.*trace_chg_.*sub.*{',
        3 if test.vltmt else 1)

test.execute()

test.passes()
