#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2024 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0

import vltest_bootstrap

test.scenarios('vlt')

test.lint(verilator_flags2=['--stats', '--expand-limit 5', '-fno-var-split'])

test.file_grep(test.stats, r'Optimizations, Gate signals not inlined due to cost\s+(\d+)', 2)
test.file_grep(test.stats, r'Optimizations, Gate signals inlined\s+(\d+)', 1)
test.file_grep(test.stats, r'SplitVar, packed variables split automatically\s+(\d+)', 0)

test.passes()
